Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.31 100.00 96.55 100.00 100.00 95.00


Total tests in report: 200
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
87.31 87.31 100.00 100.00 96.55 96.55 100.00 100.00 100.00 100.00 40.00 40.00 /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.3541065619
96.81 9.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 87.50 47.50 /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.3738576294
98.31 1.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 95.00 7.50 /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.1271673671

Tests that do not contribute to grading

Name
/workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.3877174298
/workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.1494994796
/workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.1712110599
/workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.3054732730
/workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.1278795986
/workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.580002818
/workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.3700367759
/workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.2358663029
/workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.3916205003
/workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.1775653741
/workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.531438627
/workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.2611702369
/workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.569539460
/workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.3582240928
/workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.1169237164
/workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.491739605
/workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.3710400637
/workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.846794401
/workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.925522042
/workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.3389986282
/workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.1165742970
/workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.128378271
/workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.1181574695
/workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.2507708723
/workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.1114378802
/workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.936567456
/workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.3579826070
/workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.499943934
/workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.2244103394
/workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.1481125677
/workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.1223669546
/workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.3856032407
/workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.12950810
/workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.1420365503
/workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.1372281538
/workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.2708669125
/workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.237183911
/workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.316738678
/workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.3813629843
/workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.3014993411
/workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.1017356716
/workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.2956986535
/workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.416037831
/workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.3255845810
/workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.1466307263
/workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.3434172565
/workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.178761396
/workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.2755262041
/workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.637614225
/workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.975004319
/workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.2571749108
/workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.149841156
/workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.3913904472
/workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.1355156978
/workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.2185389074
/workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.4232623753
/workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.4150807136
/workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.1526770214
/workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.830651297
/workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.103048654
/workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.3172062216
/workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.1803486177
/workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.1907562647
/workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.2333291418
/workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.61823655
/workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.1056554481
/workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.1784333044
/workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.2616444686
/workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.3135724314
/workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.900563181
/workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.2295753778
/workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.4265080876
/workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.2431439528
/workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.3900368485
/workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.2190145394
/workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.3757069668
/workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.1249732907
/workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.3744113986
/workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.2148599092
/workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.1074593389
/workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.2441001682
/workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.1919653889
/workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.1743294188
/workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.1809824873
/workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.1834115555
/workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.3864625217
/workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.3068651983
/workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.1454742561
/workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.4265730684
/workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.2711425041
/workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.1481108509
/workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.2088836978
/workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.3740990017
/workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.1253040550
/workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.1146402732
/workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.1547205653
/workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.3029151144
/workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.2370907396
/workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.3317030015
/workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.1363928240
/workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.792222440
/workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.812059629
/workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.125248111
/workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.3437368328
/workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.449916753
/workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.1275763183
/workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.1250560555
/workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.1007894551
/workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.3435728323
/workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.910087021
/workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.437561944
/workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.3240325725
/workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.90502482
/workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.3980252482
/workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.2973761411
/workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.3523246799
/workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.593525440
/workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.3394205529
/workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.295633263
/workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.99130316
/workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.3117107602
/workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.974514682
/workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.582431220
/workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.3775336448
/workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.1998052845
/workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.1780013023
/workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.2302753458
/workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.2013768129
/workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.3796279004
/workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.4111239831
/workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.1510409763
/workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.3468661771
/workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.2159954414
/workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.4009533364
/workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.1611824740
/workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.183767125
/workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.3567226001
/workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.1000370451
/workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.3912759302
/workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.12449982
/workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.2760609640
/workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.3687681358
/workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.451812500
/workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.4079190144
/workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.586667621
/workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.2949953291
/workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1147802023
/workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2756284070
/workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.1169506661
/workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.3906941233
/workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.63855938
/workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.4032217552
/workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.3893575265
/workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.358031792
/workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.2802474229
/workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.2364810868
/workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.3817601034
/workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.1748318593
/workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.4140865041
/workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.2937854761
/workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.4256791098
/workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.1127090252
/workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.2979400216
/workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.3330957438
/workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.2017111422
/workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.3653700031
/workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.225286513
/workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.3473008881
/workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.32367471
/workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.3362608232
/workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.1910021447
/workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.2503454354
/workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.3931885587
/workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.2276279347
/workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.3007723769
/workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.1385839349
/workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.3839260412
/workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.3053157868
/workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.1437776078
/workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.4237046270
/workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.486654639
/workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.651229733
/workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.1986034936
/workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.2759560265
/workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.1030314101
/workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.2465623268
/workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.3029599892
/workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.2400829856
/workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.2294695901
/workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.509737754
/workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.4001495629
/workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.3375689843
/workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.154564279
/workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.1704666380
/workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.1645728995
/workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.1406718240
/workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.2871001139



Total test records in report: 200
tests.html | tests1.html | tests2.html | tests3.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.3839260412 Jul 01 04:21:06 PM PDT 24 Jul 01 04:21:16 PM PDT 24 1434210000 ps
T2 /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.4001495629 Jul 01 04:18:38 PM PDT 24 Jul 01 04:18:48 PM PDT 24 1463550000 ps
T3 /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.225286513 Jul 01 04:21:29 PM PDT 24 Jul 01 04:21:39 PM PDT 24 1369690000 ps
T7 /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.3541065619 Jul 01 04:17:40 PM PDT 24 Jul 01 04:17:52 PM PDT 24 1509530000 ps
T8 /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.1437776078 Jul 01 04:20:52 PM PDT 24 Jul 01 04:21:03 PM PDT 24 1391410000 ps
T9 /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.3653700031 Jul 01 04:16:57 PM PDT 24 Jul 01 04:17:05 PM PDT 24 1284910000 ps
T10 /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.1986034936 Jul 01 04:20:44 PM PDT 24 Jul 01 04:20:56 PM PDT 24 1481850000 ps
T11 /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.2937854761 Jul 01 04:16:50 PM PDT 24 Jul 01 04:16:59 PM PDT 24 1559350000 ps
T12 /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.2802474229 Jul 01 04:18:23 PM PDT 24 Jul 01 04:18:32 PM PDT 24 1362830000 ps
T13 /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.2503454354 Jul 01 04:19:27 PM PDT 24 Jul 01 04:19:35 PM PDT 24 1275050000 ps
T31 /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.1127090252 Jul 01 04:16:39 PM PDT 24 Jul 01 04:16:46 PM PDT 24 1156210000 ps
T32 /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.1704666380 Jul 01 04:19:10 PM PDT 24 Jul 01 04:19:21 PM PDT 24 1530230000 ps
T33 /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.3375689843 Jul 01 04:20:51 PM PDT 24 Jul 01 04:21:00 PM PDT 24 1232210000 ps
T34 /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.2979400216 Jul 01 04:18:29 PM PDT 24 Jul 01 04:18:38 PM PDT 24 1447150000 ps
T35 /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.2017111422 Jul 01 04:18:46 PM PDT 24 Jul 01 04:18:58 PM PDT 24 1515730000 ps
T36 /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.3362608232 Jul 01 04:19:34 PM PDT 24 Jul 01 04:19:44 PM PDT 24 1439730000 ps
T37 /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.3906941233 Jul 01 04:21:33 PM PDT 24 Jul 01 04:21:46 PM PDT 24 1416830000 ps
T38 /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.3893575265 Jul 01 04:18:20 PM PDT 24 Jul 01 04:18:31 PM PDT 24 1400530000 ps
T39 /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.358031792 Jul 01 04:20:52 PM PDT 24 Jul 01 04:21:03 PM PDT 24 1572230000 ps
T40 /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.2871001139 Jul 01 04:20:51 PM PDT 24 Jul 01 04:21:02 PM PDT 24 1479650000 ps
T41 /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.1169506661 Jul 01 04:18:24 PM PDT 24 Jul 01 04:18:35 PM PDT 24 1599630000 ps
T42 /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.1385839349 Jul 01 04:20:37 PM PDT 24 Jul 01 04:20:46 PM PDT 24 1486830000 ps
T43 /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.2465623268 Jul 01 04:18:37 PM PDT 24 Jul 01 04:18:47 PM PDT 24 1318030000 ps
T44 /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.509737754 Jul 01 04:18:22 PM PDT 24 Jul 01 04:18:32 PM PDT 24 1462330000 ps
T45 /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.2364810868 Jul 01 04:18:38 PM PDT 24 Jul 01 04:18:47 PM PDT 24 1314110000 ps
T46 /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.4140865041 Jul 01 04:16:50 PM PDT 24 Jul 01 04:17:02 PM PDT 24 1558490000 ps
T47 /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.3473008881 Jul 01 04:20:50 PM PDT 24 Jul 01 04:21:00 PM PDT 24 1601990000 ps
T48 /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.3053157868 Jul 01 04:20:38 PM PDT 24 Jul 01 04:20:46 PM PDT 24 1450370000 ps
T49 /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.4237046270 Jul 01 04:17:46 PM PDT 24 Jul 01 04:17:56 PM PDT 24 1469970000 ps
T50 /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.1910021447 Jul 01 04:16:50 PM PDT 24 Jul 01 04:17:00 PM PDT 24 1534270000 ps
T51 /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.2276279347 Jul 01 04:20:51 PM PDT 24 Jul 01 04:21:02 PM PDT 24 1476990000 ps
T52 /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.154564279 Jul 01 04:18:28 PM PDT 24 Jul 01 04:18:37 PM PDT 24 1298490000 ps
T53 /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.3817601034 Jul 01 04:20:16 PM PDT 24 Jul 01 04:20:28 PM PDT 24 1469810000 ps
T54 /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.32367471 Jul 01 04:19:26 PM PDT 24 Jul 01 04:19:37 PM PDT 24 1595490000 ps
T55 /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.3330957438 Jul 01 04:18:53 PM PDT 24 Jul 01 04:19:04 PM PDT 24 1438390000 ps
T56 /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.1748318593 Jul 01 04:18:27 PM PDT 24 Jul 01 04:18:37 PM PDT 24 1429130000 ps
T57 /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.1645728995 Jul 01 04:17:40 PM PDT 24 Jul 01 04:17:48 PM PDT 24 1515110000 ps
T58 /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.1030314101 Jul 01 04:18:37 PM PDT 24 Jul 01 04:18:47 PM PDT 24 1508210000 ps
T59 /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.3931885587 Jul 01 04:18:23 PM PDT 24 Jul 01 04:18:34 PM PDT 24 1558350000 ps
T60 /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.651229733 Jul 01 04:18:46 PM PDT 24 Jul 01 04:18:57 PM PDT 24 1504790000 ps
T61 /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.3007723769 Jul 01 04:20:52 PM PDT 24 Jul 01 04:21:02 PM PDT 24 1340030000 ps
T62 /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.2294695901 Jul 01 04:18:24 PM PDT 24 Jul 01 04:18:32 PM PDT 24 1369070000 ps
T63 /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.2759560265 Jul 01 04:21:28 PM PDT 24 Jul 01 04:21:39 PM PDT 24 1491050000 ps
T64 /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.4032217552 Jul 01 04:20:36 PM PDT 24 Jul 01 04:20:45 PM PDT 24 1447810000 ps
T65 /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.4256791098 Jul 01 04:20:36 PM PDT 24 Jul 01 04:20:45 PM PDT 24 1303890000 ps
T66 /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.2400829856 Jul 01 04:17:43 PM PDT 24 Jul 01 04:17:52 PM PDT 24 1381590000 ps
T67 /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.486654639 Jul 01 04:21:28 PM PDT 24 Jul 01 04:21:39 PM PDT 24 1594210000 ps
T68 /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.1406718240 Jul 01 04:16:54 PM PDT 24 Jul 01 04:17:04 PM PDT 24 1390570000 ps
T69 /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.3029599892 Jul 01 04:18:37 PM PDT 24 Jul 01 04:18:47 PM PDT 24 1293370000 ps
T70 /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.63855938 Jul 01 04:18:54 PM PDT 24 Jul 01 04:19:06 PM PDT 24 1459270000 ps
T4 /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.1017356716 Jul 01 04:19:24 PM PDT 24 Jul 01 04:53:11 PM PDT 24 336549630000 ps
T5 /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.1420365503 Jul 01 04:21:09 PM PDT 24 Jul 01 04:58:04 PM PDT 24 336488990000 ps
T6 /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.1481125677 Jul 01 04:16:39 PM PDT 24 Jul 01 04:45:16 PM PDT 24 336451110000 ps
T14 /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.2755262041 Jul 01 04:20:12 PM PDT 24 Jul 01 04:56:20 PM PDT 24 336967850000 ps
T15 /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.237183911 Jul 01 04:18:32 PM PDT 24 Jul 01 04:52:51 PM PDT 24 336982310000 ps
T16 /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.1181574695 Jul 01 04:19:59 PM PDT 24 Jul 01 04:53:35 PM PDT 24 336757770000 ps
T17 /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.2507708723 Jul 01 04:18:24 PM PDT 24 Jul 01 04:57:54 PM PDT 24 336741630000 ps
T18 /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.3738576294 Jul 01 04:21:09 PM PDT 24 Jul 01 04:58:06 PM PDT 24 336783130000 ps
T19 /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.637614225 Jul 01 04:19:48 PM PDT 24 Jul 01 04:59:20 PM PDT 24 336755890000 ps
T20 /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.2956986535 Jul 01 04:17:38 PM PDT 24 Jul 01 04:51:05 PM PDT 24 336818510000 ps
T71 /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.499943934 Jul 01 04:18:36 PM PDT 24 Jul 01 04:54:18 PM PDT 24 336428930000 ps
T72 /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.1466307263 Jul 01 04:19:19 PM PDT 24 Jul 01 04:58:21 PM PDT 24 336463990000 ps
T73 /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.1278795986 Jul 01 04:16:53 PM PDT 24 Jul 01 04:55:31 PM PDT 24 336698190000 ps
T74 /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.1494994796 Jul 01 04:18:52 PM PDT 24 Jul 01 04:52:42 PM PDT 24 337031710000 ps
T75 /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.1712110599 Jul 01 04:17:00 PM PDT 24 Jul 01 04:47:07 PM PDT 24 336404310000 ps
T76 /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.416037831 Jul 01 04:17:03 PM PDT 24 Jul 01 04:50:11 PM PDT 24 336401050000 ps
T77 /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.3389986282 Jul 01 04:17:25 PM PDT 24 Jul 01 04:54:25 PM PDT 24 336812830000 ps
T78 /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.846794401 Jul 01 04:16:38 PM PDT 24 Jul 01 04:45:21 PM PDT 24 336672890000 ps
T79 /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.3255845810 Jul 01 04:18:25 PM PDT 24 Jul 01 04:51:48 PM PDT 24 336786730000 ps
T80 /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.3856032407 Jul 01 04:22:20 PM PDT 24 Jul 01 05:00:41 PM PDT 24 336797510000 ps
T81 /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.2358663029 Jul 01 04:19:19 PM PDT 24 Jul 01 04:58:23 PM PDT 24 336643350000 ps
T82 /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.3434172565 Jul 01 04:17:36 PM PDT 24 Jul 01 04:51:01 PM PDT 24 336866090000 ps
T83 /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.12950810 Jul 01 04:16:50 PM PDT 24 Jul 01 04:55:18 PM PDT 24 336854550000 ps
T84 /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.580002818 Jul 01 04:18:58 PM PDT 24 Jul 01 04:52:31 PM PDT 24 336855030000 ps
T85 /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.316738678 Jul 01 04:19:08 PM PDT 24 Jul 01 04:52:08 PM PDT 24 336434870000 ps
T86 /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.2244103394 Jul 01 04:18:31 PM PDT 24 Jul 01 04:46:26 PM PDT 24 336458010000 ps
T87 /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.925522042 Jul 01 04:17:41 PM PDT 24 Jul 01 04:55:40 PM PDT 24 336589130000 ps
T88 /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.178761396 Jul 01 04:17:25 PM PDT 24 Jul 01 04:53:53 PM PDT 24 336725910000 ps
T89 /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.1114378802 Jul 01 04:21:14 PM PDT 24 Jul 01 04:52:30 PM PDT 24 336508290000 ps
T90 /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.2611702369 Jul 01 04:17:39 PM PDT 24 Jul 01 04:56:12 PM PDT 24 337019810000 ps
T91 /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.128378271 Jul 01 04:18:24 PM PDT 24 Jul 01 04:57:48 PM PDT 24 336852110000 ps
T92 /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.1165742970 Jul 01 04:21:29 PM PDT 24 Jul 01 04:56:10 PM PDT 24 336961030000 ps
T93 /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.3579826070 Jul 01 04:20:58 PM PDT 24 Jul 01 04:47:28 PM PDT 24 336902450000 ps
T94 /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.491739605 Jul 01 04:18:46 PM PDT 24 Jul 01 04:49:34 PM PDT 24 336699810000 ps
T95 /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.3916205003 Jul 01 04:20:47 PM PDT 24 Jul 01 04:59:33 PM PDT 24 336596130000 ps
T96 /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.3014993411 Jul 01 04:20:36 PM PDT 24 Jul 01 04:43:48 PM PDT 24 336596290000 ps
T97 /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.3877174298 Jul 01 04:22:17 PM PDT 24 Jul 01 05:00:06 PM PDT 24 337020990000 ps
T98 /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.3700367759 Jul 01 04:20:11 PM PDT 24 Jul 01 04:55:39 PM PDT 24 336989190000 ps
T99 /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.3054732730 Jul 01 04:18:35 PM PDT 24 Jul 01 04:54:35 PM PDT 24 336666790000 ps
T100 /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.1372281538 Jul 01 04:22:15 PM PDT 24 Jul 01 05:00:42 PM PDT 24 336838890000 ps
T101 /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.531438627 Jul 01 04:22:05 PM PDT 24 Jul 01 04:47:35 PM PDT 24 336601350000 ps
T102 /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.569539460 Jul 01 04:19:59 PM PDT 24 Jul 01 04:53:42 PM PDT 24 337056650000 ps
T103 /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.2708669125 Jul 01 04:19:19 PM PDT 24 Jul 01 04:58:30 PM PDT 24 336578510000 ps
T104 /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.3582240928 Jul 01 04:22:15 PM PDT 24 Jul 01 05:00:17 PM PDT 24 336439390000 ps
T105 /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.936567456 Jul 01 04:21:00 PM PDT 24 Jul 01 04:53:52 PM PDT 24 336472950000 ps
T106 /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.1223669546 Jul 01 04:17:41 PM PDT 24 Jul 01 04:53:15 PM PDT 24 336693810000 ps
T107 /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.1169237164 Jul 01 04:19:12 PM PDT 24 Jul 01 04:57:18 PM PDT 24 336872070000 ps
T108 /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.1775653741 Jul 01 04:18:14 PM PDT 24 Jul 01 04:54:31 PM PDT 24 336992370000 ps
T109 /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.3710400637 Jul 01 04:18:08 PM PDT 24 Jul 01 04:54:37 PM PDT 24 336757750000 ps
T110 /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.3813629843 Jul 01 04:20:07 PM PDT 24 Jul 01 04:59:11 PM PDT 24 336349850000 ps
T111 /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.2302753458 Jul 01 04:29:10 PM PDT 24 Jul 01 04:29:29 PM PDT 24 1514590000 ps
T112 /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.792222440 Jul 01 04:29:14 PM PDT 24 Jul 01 04:29:32 PM PDT 24 1360550000 ps
T113 /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.3980252482 Jul 01 04:28:55 PM PDT 24 Jul 01 04:29:19 PM PDT 24 1565050000 ps
T114 /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.2159954414 Jul 01 04:28:52 PM PDT 24 Jul 01 04:29:13 PM PDT 24 1601550000 ps
T115 /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.4079190144 Jul 01 04:28:56 PM PDT 24 Jul 01 04:29:17 PM PDT 24 1527270000 ps
T116 /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.586667621 Jul 01 04:28:51 PM PDT 24 Jul 01 04:29:14 PM PDT 24 1507210000 ps
T117 /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.1275763183 Jul 01 04:28:54 PM PDT 24 Jul 01 04:29:15 PM PDT 24 1078590000 ps
T118 /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.295633263 Jul 01 04:28:56 PM PDT 24 Jul 01 04:29:18 PM PDT 24 1444350000 ps
T119 /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.974514682 Jul 01 04:29:02 PM PDT 24 Jul 01 04:29:22 PM PDT 24 1453670000 ps
T120 /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.910087021 Jul 01 04:29:26 PM PDT 24 Jul 01 04:29:41 PM PDT 24 1150190000 ps
T121 /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.90502482 Jul 01 04:28:59 PM PDT 24 Jul 01 04:29:19 PM PDT 24 1321870000 ps
T122 /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.3796279004 Jul 01 04:28:59 PM PDT 24 Jul 01 04:29:20 PM PDT 24 1451770000 ps
T123 /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.3394205529 Jul 01 04:28:57 PM PDT 24 Jul 01 04:29:23 PM PDT 24 1371910000 ps
T124 /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.125248111 Jul 01 04:29:11 PM PDT 24 Jul 01 04:29:29 PM PDT 24 1409410000 ps
T125 /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.437561944 Jul 01 04:28:53 PM PDT 24 Jul 01 04:29:17 PM PDT 24 1565710000 ps
T126 /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.3468661771 Jul 01 04:29:30 PM PDT 24 Jul 01 04:29:44 PM PDT 24 1378230000 ps
T127 /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.2949953291 Jul 01 04:28:57 PM PDT 24 Jul 01 04:29:20 PM PDT 24 1530310000 ps
T128 /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.1250560555 Jul 01 04:28:57 PM PDT 24 Jul 01 04:29:19 PM PDT 24 1568650000 ps
T129 /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.3435728323 Jul 01 04:29:16 PM PDT 24 Jul 01 04:29:35 PM PDT 24 1587950000 ps
T130 /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.1007894551 Jul 01 04:29:03 PM PDT 24 Jul 01 04:29:26 PM PDT 24 1535350000 ps
T131 /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.3912759302 Jul 01 04:28:56 PM PDT 24 Jul 01 04:29:20 PM PDT 24 1526670000 ps
T132 /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.582431220 Jul 01 04:29:02 PM PDT 24 Jul 01 04:29:22 PM PDT 24 1378550000 ps
T133 /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2756284070 Jul 01 04:28:55 PM PDT 24 Jul 01 04:29:19 PM PDT 24 1470690000 ps
T134 /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.2760609640 Jul 01 04:28:59 PM PDT 24 Jul 01 04:29:19 PM PDT 24 1380430000 ps
T135 /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.3523246799 Jul 01 04:29:06 PM PDT 24 Jul 01 04:29:23 PM PDT 24 1413930000 ps
T136 /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.3567226001 Jul 01 04:29:20 PM PDT 24 Jul 01 04:29:37 PM PDT 24 1438050000 ps
T137 /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.2013768129 Jul 01 04:28:57 PM PDT 24 Jul 01 04:29:23 PM PDT 24 1555770000 ps
T138 /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.1780013023 Jul 01 04:29:03 PM PDT 24 Jul 01 04:29:25 PM PDT 24 1516990000 ps
T139 /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.99130316 Jul 01 04:29:11 PM PDT 24 Jul 01 04:29:29 PM PDT 24 1367650000 ps
T140 /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.593525440 Jul 01 04:28:56 PM PDT 24 Jul 01 04:29:19 PM PDT 24 1278810000 ps
T141 /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.1363928240 Jul 01 04:28:54 PM PDT 24 Jul 01 04:29:16 PM PDT 24 1389470000 ps
T142 /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.4111239831 Jul 01 04:29:16 PM PDT 24 Jul 01 04:29:32 PM PDT 24 1387950000 ps
T143 /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.3437368328 Jul 01 04:28:55 PM PDT 24 Jul 01 04:29:17 PM PDT 24 1494330000 ps
T144 /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.2973761411 Jul 01 04:29:04 PM PDT 24 Jul 01 04:29:25 PM PDT 24 1478450000 ps
T145 /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.3775336448 Jul 01 04:29:05 PM PDT 24 Jul 01 04:29:24 PM PDT 24 1626550000 ps
T146 /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.451812500 Jul 01 04:29:15 PM PDT 24 Jul 01 04:29:36 PM PDT 24 1251330000 ps
T147 /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.1998052845 Jul 01 04:28:56 PM PDT 24 Jul 01 04:29:19 PM PDT 24 1559650000 ps
T148 /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.449916753 Jul 01 04:28:52 PM PDT 24 Jul 01 04:29:15 PM PDT 24 1535350000 ps
T149 /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.3240325725 Jul 01 04:28:57 PM PDT 24 Jul 01 04:29:19 PM PDT 24 1596750000 ps
T150 /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.3687681358 Jul 01 04:29:25 PM PDT 24 Jul 01 04:29:41 PM PDT 24 1536870000 ps
T151 /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.1510409763 Jul 01 04:28:57 PM PDT 24 Jul 01 04:29:25 PM PDT 24 1610790000 ps
T152 /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.4009533364 Jul 01 04:29:17 PM PDT 24 Jul 01 04:29:34 PM PDT 24 1494530000 ps
T153 /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.812059629 Jul 01 04:29:04 PM PDT 24 Jul 01 04:29:22 PM PDT 24 1513050000 ps
T154 /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.12449982 Jul 01 04:28:58 PM PDT 24 Jul 01 04:29:22 PM PDT 24 1541610000 ps
T155 /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.183767125 Jul 01 04:29:30 PM PDT 24 Jul 01 04:29:47 PM PDT 24 1444170000 ps
T156 /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.1000370451 Jul 01 04:29:24 PM PDT 24 Jul 01 04:29:42 PM PDT 24 1474910000 ps
T157 /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.1611824740 Jul 01 04:29:16 PM PDT 24 Jul 01 04:29:33 PM PDT 24 1404390000 ps
T158 /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.3117107602 Jul 01 04:28:56 PM PDT 24 Jul 01 04:29:18 PM PDT 24 1422530000 ps
T159 /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1147802023 Jul 01 04:28:55 PM PDT 24 Jul 01 04:29:16 PM PDT 24 1219590000 ps
T160 /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.3317030015 Jul 01 04:29:17 PM PDT 24 Jul 01 04:29:35 PM PDT 24 1426930000 ps
T21 /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.1146402732 Jul 01 04:29:13 PM PDT 24 Jul 01 05:03:37 PM PDT 24 336456010000 ps
T22 /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.1271673671 Jul 01 04:29:30 PM PDT 24 Jul 01 05:05:34 PM PDT 24 336965350000 ps
T23 /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.2088836978 Jul 01 04:29:39 PM PDT 24 Jul 01 05:05:42 PM PDT 24 336975710000 ps
T24 /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.2148599092 Jul 01 04:29:10 PM PDT 24 Jul 01 05:02:48 PM PDT 24 336460650000 ps
T25 /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.103048654 Jul 01 04:29:05 PM PDT 24 Jul 01 05:05:49 PM PDT 24 336355490000 ps
T26 /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.1743294188 Jul 01 04:29:24 PM PDT 24 Jul 01 05:03:02 PM PDT 24 336396370000 ps
T27 /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.1481108509 Jul 01 04:29:32 PM PDT 24 Jul 01 04:57:08 PM PDT 24 336723630000 ps
T28 /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.1253040550 Jul 01 04:29:24 PM PDT 24 Jul 01 05:05:13 PM PDT 24 336938570000 ps
T29 /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.2616444686 Jul 01 04:29:12 PM PDT 24 Jul 01 05:02:18 PM PDT 24 336465910000 ps
T30 /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.4265730684 Jul 01 04:29:27 PM PDT 24 Jul 01 05:02:44 PM PDT 24 336530170000 ps
T161 /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.900563181 Jul 01 04:29:14 PM PDT 24 Jul 01 05:00:56 PM PDT 24 336414310000 ps
T162 /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.3172062216 Jul 01 04:28:59 PM PDT 24 Jul 01 05:07:52 PM PDT 24 336739210000 ps
T163 /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.2333291418 Jul 01 04:29:17 PM PDT 24 Jul 01 05:04:08 PM PDT 24 336460070000 ps
T164 /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.4150807136 Jul 01 04:29:08 PM PDT 24 Jul 01 04:58:25 PM PDT 24 337017370000 ps
T165 /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.1784333044 Jul 01 04:29:14 PM PDT 24 Jul 01 05:02:37 PM PDT 24 336534950000 ps
T166 /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.1526770214 Jul 01 04:29:20 PM PDT 24 Jul 01 05:00:48 PM PDT 24 336988630000 ps
T167 /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.1919653889 Jul 01 04:29:20 PM PDT 24 Jul 01 04:59:15 PM PDT 24 336378170000 ps
T168 /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.830651297 Jul 01 04:29:05 PM PDT 24 Jul 01 04:57:14 PM PDT 24 337026090000 ps
T169 /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.3900368485 Jul 01 04:29:09 PM PDT 24 Jul 01 04:58:16 PM PDT 24 336567230000 ps
T170 /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.3135724314 Jul 01 04:29:22 PM PDT 24 Jul 01 04:58:57 PM PDT 24 336638010000 ps
T171 /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.1907562647 Jul 01 04:29:06 PM PDT 24 Jul 01 05:04:57 PM PDT 24 336571010000 ps
T172 /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.2441001682 Jul 01 04:29:26 PM PDT 24 Jul 01 05:01:07 PM PDT 24 337161070000 ps
T173 /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.3029151144 Jul 01 04:28:58 PM PDT 24 Jul 01 04:56:58 PM PDT 24 336972470000 ps
T174 /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.1249732907 Jul 01 04:29:05 PM PDT 24 Jul 01 05:06:17 PM PDT 24 336419830000 ps
T175 /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.1454742561 Jul 01 04:29:27 PM PDT 24 Jul 01 04:57:54 PM PDT 24 336773910000 ps
T176 /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.1056554481 Jul 01 04:29:12 PM PDT 24 Jul 01 04:59:42 PM PDT 24 336820550000 ps
T177 /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.3757069668 Jul 01 04:29:14 PM PDT 24 Jul 01 04:56:31 PM PDT 24 336497950000 ps
T178 /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.1355156978 Jul 01 04:29:03 PM PDT 24 Jul 01 04:51:17 PM PDT 24 336388130000 ps
T179 /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.2295753778 Jul 01 04:29:18 PM PDT 24 Jul 01 04:59:41 PM PDT 24 336589750000 ps
T180 /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.1809824873 Jul 01 04:29:07 PM PDT 24 Jul 01 05:05:00 PM PDT 24 337085810000 ps
T181 /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.2431439528 Jul 01 04:29:18 PM PDT 24 Jul 01 05:02:20 PM PDT 24 336782290000 ps
T182 /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.2711425041 Jul 01 04:29:09 PM PDT 24 Jul 01 04:57:29 PM PDT 24 336848790000 ps
T183 /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.3068651983 Jul 01 04:29:34 PM PDT 24 Jul 01 05:02:21 PM PDT 24 336956390000 ps
T184 /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.1547205653 Jul 01 04:29:10 PM PDT 24 Jul 01 05:07:30 PM PDT 24 336732710000 ps
T185 /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.1803486177 Jul 01 04:29:08 PM PDT 24 Jul 01 05:05:30 PM PDT 24 336992830000 ps
T186 /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.2370907396 Jul 01 04:29:19 PM PDT 24 Jul 01 04:59:16 PM PDT 24 336926750000 ps
T187 /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.1074593389 Jul 01 04:29:16 PM PDT 24 Jul 01 04:57:35 PM PDT 24 336884190000 ps
T188 /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.2185389074 Jul 01 04:29:07 PM PDT 24 Jul 01 05:00:58 PM PDT 24 336806690000 ps
T189 /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.2571749108 Jul 01 04:29:30 PM PDT 24 Jul 01 05:01:45 PM PDT 24 336387570000 ps
T190 /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.2190145394 Jul 01 04:29:19 PM PDT 24 Jul 01 04:56:31 PM PDT 24 336531770000 ps
T191 /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.975004319 Jul 01 04:29:38 PM PDT 24 Jul 01 05:01:29 PM PDT 24 336601870000 ps
T192 /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.3744113986 Jul 01 04:29:22 PM PDT 24 Jul 01 05:03:50 PM PDT 24 336751090000 ps
T193 /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.4232623753 Jul 01 04:29:20 PM PDT 24 Jul 01 05:00:45 PM PDT 24 336549490000 ps
T194 /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.1834115555 Jul 01 04:29:17 PM PDT 24 Jul 01 04:59:17 PM PDT 24 336479050000 ps
T195 /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.4265080876 Jul 01 04:29:29 PM PDT 24 Jul 01 05:04:36 PM PDT 24 337034750000 ps
T196 /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.149841156 Jul 01 04:29:03 PM PDT 24 Jul 01 05:01:57 PM PDT 24 336562610000 ps
T197 /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.3913904472 Jul 01 04:29:10 PM PDT 24 Jul 01 05:01:23 PM PDT 24 336620010000 ps
T198 /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.3864625217 Jul 01 04:29:33 PM PDT 24 Jul 01 05:05:31 PM PDT 24 336855230000 ps
T199 /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.61823655 Jul 01 04:29:22 PM PDT 24 Jul 01 05:01:02 PM PDT 24 336750870000 ps
T200 /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.3740990017 Jul 01 04:29:29 PM PDT 24 Jul 01 05:05:35 PM PDT 24 336459490000 ps

Test location /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.3541065619
Short name T7
Test name
Test status
Simulation time 1509530000 ps
CPU time 5.14 seconds
Started Jul 01 04:17:40 PM PDT 24
Finished Jul 01 04:17:52 PM PDT 24
Peak memory 164988 kb
Host smart-1f5e7e9f-5667-4d4a-9a87-b07ce95a3020
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3541065619 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.3541065619
Directory /workspace/13.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.3738576294
Short name T18
Test name
Test status
Simulation time 336783130000 ps
CPU time 906.31 seconds
Started Jul 01 04:21:09 PM PDT 24
Finished Jul 01 04:58:06 PM PDT 24
Peak memory 159472 kb
Host smart-4c93b6c3-cdd1-4c04-8e79-712f3b30a1a5
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3738576294 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.3738576294
Directory /workspace/12.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.1271673671
Short name T22
Test name
Test status
Simulation time 336965350000 ps
CPU time 876.84 seconds
Started Jul 01 04:29:30 PM PDT 24
Finished Jul 01 05:05:34 PM PDT 24
Peak memory 160704 kb
Host smart-9be57d22-e4cf-4c51-ae84-ac661994591d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1271673671 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.1271673671
Directory /workspace/16.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.3877174298
Short name T97
Test name
Test status
Simulation time 337020990000 ps
CPU time 910.55 seconds
Started Jul 01 04:22:17 PM PDT 24
Finished Jul 01 05:00:06 PM PDT 24
Peak memory 160276 kb
Host smart-65f9dafb-5a8f-4733-b0c2-b4b400fc7a87
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3877174298 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.3877174298
Directory /workspace/0.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.1494994796
Short name T74
Test name
Test status
Simulation time 337031710000 ps
CPU time 834.96 seconds
Started Jul 01 04:18:52 PM PDT 24
Finished Jul 01 04:52:42 PM PDT 24
Peak memory 160828 kb
Host smart-cc379dd7-6299-402d-b3ad-ccc8df09afd3
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1494994796 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.1494994796
Directory /workspace/1.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.1712110599
Short name T75
Test name
Test status
Simulation time 336404310000 ps
CPU time 740.12 seconds
Started Jul 01 04:17:00 PM PDT 24
Finished Jul 01 04:47:07 PM PDT 24
Peak memory 160792 kb
Host smart-132ef2a2-0b15-4eab-870d-f2e8ababb92d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1712110599 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.1712110599
Directory /workspace/10.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.3054732730
Short name T99
Test name
Test status
Simulation time 336666790000 ps
CPU time 873.66 seconds
Started Jul 01 04:18:35 PM PDT 24
Finished Jul 01 04:54:35 PM PDT 24
Peak memory 160836 kb
Host smart-1b1de454-11ca-4b30-84ca-82f00e0a578f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3054732730 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.3054732730
Directory /workspace/11.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.1278795986
Short name T73
Test name
Test status
Simulation time 336698190000 ps
CPU time 930.3 seconds
Started Jul 01 04:16:53 PM PDT 24
Finished Jul 01 04:55:31 PM PDT 24
Peak memory 160848 kb
Host smart-414f623a-bf9e-49e9-8914-1f89d3772052
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1278795986 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.1278795986
Directory /workspace/13.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.580002818
Short name T84
Test name
Test status
Simulation time 336855030000 ps
CPU time 827.43 seconds
Started Jul 01 04:18:58 PM PDT 24
Finished Jul 01 04:52:31 PM PDT 24
Peak memory 160904 kb
Host smart-62276db9-1d65-4c5e-9789-10c3810bb6db
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=580002818 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.580002818
Directory /workspace/14.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.3700367759
Short name T98
Test name
Test status
Simulation time 336989190000 ps
CPU time 876.87 seconds
Started Jul 01 04:20:11 PM PDT 24
Finished Jul 01 04:55:39 PM PDT 24
Peak memory 160860 kb
Host smart-d39d1e8d-5427-4f59-b794-b9a90c0b665e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3700367759 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.3700367759
Directory /workspace/15.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.2358663029
Short name T81
Test name
Test status
Simulation time 336643350000 ps
CPU time 936.49 seconds
Started Jul 01 04:19:19 PM PDT 24
Finished Jul 01 04:58:23 PM PDT 24
Peak memory 160908 kb
Host smart-e208fbe6-64ca-439d-b09c-05e603d86521
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2358663029 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.2358663029
Directory /workspace/16.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.3916205003
Short name T95
Test name
Test status
Simulation time 336596130000 ps
CPU time 927.04 seconds
Started Jul 01 04:20:47 PM PDT 24
Finished Jul 01 04:59:33 PM PDT 24
Peak memory 160908 kb
Host smart-98692d1f-0141-4556-95fe-a495e1bfbeaf
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3916205003 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.3916205003
Directory /workspace/17.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.1775653741
Short name T108
Test name
Test status
Simulation time 336992370000 ps
CPU time 891.5 seconds
Started Jul 01 04:18:14 PM PDT 24
Finished Jul 01 04:54:31 PM PDT 24
Peak memory 160856 kb
Host smart-adc829de-7985-4728-894e-c44d14c3d233
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1775653741 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.1775653741
Directory /workspace/18.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.531438627
Short name T101
Test name
Test status
Simulation time 336601350000 ps
CPU time 621.75 seconds
Started Jul 01 04:22:05 PM PDT 24
Finished Jul 01 04:47:35 PM PDT 24
Peak memory 159760 kb
Host smart-e38c8d4a-b568-4ee0-b633-62ee75b8aa72
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=531438627 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.531438627
Directory /workspace/19.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.2611702369
Short name T90
Test name
Test status
Simulation time 337019810000 ps
CPU time 954.24 seconds
Started Jul 01 04:17:39 PM PDT 24
Finished Jul 01 04:56:12 PM PDT 24
Peak memory 160852 kb
Host smart-22f2fc48-1b6b-4186-a680-b6fdb7cc5c76
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2611702369 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.2611702369
Directory /workspace/2.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.569539460
Short name T102
Test name
Test status
Simulation time 337056650000 ps
CPU time 824 seconds
Started Jul 01 04:19:59 PM PDT 24
Finished Jul 01 04:53:42 PM PDT 24
Peak memory 160844 kb
Host smart-289f99c1-18f4-425f-a9e5-b9e61b7c2c0d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=569539460 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.569539460
Directory /workspace/20.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.3582240928
Short name T104
Test name
Test status
Simulation time 336439390000 ps
CPU time 905.38 seconds
Started Jul 01 04:22:15 PM PDT 24
Finished Jul 01 05:00:17 PM PDT 24
Peak memory 160192 kb
Host smart-083915c9-0fe3-49d9-bfa5-52f5f4f5fafc
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3582240928 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.3582240928
Directory /workspace/21.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.1169237164
Short name T107
Test name
Test status
Simulation time 336872070000 ps
CPU time 933.51 seconds
Started Jul 01 04:19:12 PM PDT 24
Finished Jul 01 04:57:18 PM PDT 24
Peak memory 160864 kb
Host smart-af23a2e9-198b-4b93-8395-7212dc84b55b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1169237164 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.1169237164
Directory /workspace/22.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.491739605
Short name T94
Test name
Test status
Simulation time 336699810000 ps
CPU time 750.65 seconds
Started Jul 01 04:18:46 PM PDT 24
Finished Jul 01 04:49:34 PM PDT 24
Peak memory 160784 kb
Host smart-4d86123a-a675-455e-b8fd-5ac03a377bfb
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=491739605 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.491739605
Directory /workspace/23.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.3710400637
Short name T109
Test name
Test status
Simulation time 336757750000 ps
CPU time 898.65 seconds
Started Jul 01 04:18:08 PM PDT 24
Finished Jul 01 04:54:37 PM PDT 24
Peak memory 160840 kb
Host smart-b568695b-0c60-465b-937a-a80f2ded18c3
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3710400637 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.3710400637
Directory /workspace/24.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.846794401
Short name T78
Test name
Test status
Simulation time 336672890000 ps
CPU time 708.36 seconds
Started Jul 01 04:16:38 PM PDT 24
Finished Jul 01 04:45:21 PM PDT 24
Peak memory 160880 kb
Host smart-272caf04-6b94-4c9e-b691-bf071bf2bc12
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=846794401 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.846794401
Directory /workspace/25.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.925522042
Short name T87
Test name
Test status
Simulation time 336589130000 ps
CPU time 920.28 seconds
Started Jul 01 04:17:41 PM PDT 24
Finished Jul 01 04:55:40 PM PDT 24
Peak memory 160900 kb
Host smart-a88fa4d1-cceb-4820-8869-09e975633879
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=925522042 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.925522042
Directory /workspace/26.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.3389986282
Short name T77
Test name
Test status
Simulation time 336812830000 ps
CPU time 911.24 seconds
Started Jul 01 04:17:25 PM PDT 24
Finished Jul 01 04:54:25 PM PDT 24
Peak memory 160836 kb
Host smart-3e5b1375-0406-4fb4-ba24-b3302c4c87e2
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3389986282 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.3389986282
Directory /workspace/27.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.1165742970
Short name T92
Test name
Test status
Simulation time 336961030000 ps
CPU time 843.22 seconds
Started Jul 01 04:21:29 PM PDT 24
Finished Jul 01 04:56:10 PM PDT 24
Peak memory 160384 kb
Host smart-c4e3255e-c9b9-4361-8633-cccb8d339c41
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1165742970 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.1165742970
Directory /workspace/28.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.128378271
Short name T91
Test name
Test status
Simulation time 336852110000 ps
CPU time 954.42 seconds
Started Jul 01 04:18:24 PM PDT 24
Finished Jul 01 04:57:48 PM PDT 24
Peak memory 160840 kb
Host smart-481925a5-56c1-49b6-aa67-5316d102991a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=128378271 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.128378271
Directory /workspace/29.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.1181574695
Short name T16
Test name
Test status
Simulation time 336757770000 ps
CPU time 819.39 seconds
Started Jul 01 04:19:59 PM PDT 24
Finished Jul 01 04:53:35 PM PDT 24
Peak memory 160864 kb
Host smart-2b440856-a8ee-413b-ad30-31292bbc6280
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1181574695 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.1181574695
Directory /workspace/3.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.2507708723
Short name T17
Test name
Test status
Simulation time 336741630000 ps
CPU time 963.51 seconds
Started Jul 01 04:18:24 PM PDT 24
Finished Jul 01 04:57:54 PM PDT 24
Peak memory 160848 kb
Host smart-7a04219e-412c-422a-a672-bbfb698da3c0
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2507708723 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.2507708723
Directory /workspace/30.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.1114378802
Short name T89
Test name
Test status
Simulation time 336508290000 ps
CPU time 756.62 seconds
Started Jul 01 04:21:14 PM PDT 24
Finished Jul 01 04:52:30 PM PDT 24
Peak memory 159728 kb
Host smart-dea120ea-1fd1-4c0f-b7f7-92bd6ee11744
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1114378802 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.1114378802
Directory /workspace/31.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.936567456
Short name T105
Test name
Test status
Simulation time 336472950000 ps
CPU time 807.31 seconds
Started Jul 01 04:21:00 PM PDT 24
Finished Jul 01 04:53:52 PM PDT 24
Peak memory 159760 kb
Host smart-759483fa-f9ea-401f-88a8-4524ae791714
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=936567456 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.936567456
Directory /workspace/32.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.3579826070
Short name T93
Test name
Test status
Simulation time 336902450000 ps
CPU time 643.38 seconds
Started Jul 01 04:20:58 PM PDT 24
Finished Jul 01 04:47:28 PM PDT 24
Peak memory 159768 kb
Host smart-b03f3e9b-d273-472a-aad9-da3791bac539
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3579826070 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.3579826070
Directory /workspace/33.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.499943934
Short name T71
Test name
Test status
Simulation time 336428930000 ps
CPU time 867.76 seconds
Started Jul 01 04:18:36 PM PDT 24
Finished Jul 01 04:54:18 PM PDT 24
Peak memory 160832 kb
Host smart-420a9e9c-8eb9-4e6b-8247-fa9a82b06e0b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=499943934 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.499943934
Directory /workspace/34.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.2244103394
Short name T86
Test name
Test status
Simulation time 336458010000 ps
CPU time 684.72 seconds
Started Jul 01 04:18:31 PM PDT 24
Finished Jul 01 04:46:26 PM PDT 24
Peak memory 160884 kb
Host smart-fd0c1ec5-0ff7-47b8-8b0d-9c37d01f6fab
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2244103394 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.2244103394
Directory /workspace/35.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.1481125677
Short name T6
Test name
Test status
Simulation time 336451110000 ps
CPU time 701.51 seconds
Started Jul 01 04:16:39 PM PDT 24
Finished Jul 01 04:45:16 PM PDT 24
Peak memory 160884 kb
Host smart-acd82c3f-e289-4bc3-bf50-d255699ea6cd
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1481125677 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.1481125677
Directory /workspace/36.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.1223669546
Short name T106
Test name
Test status
Simulation time 336693810000 ps
CPU time 864.82 seconds
Started Jul 01 04:17:41 PM PDT 24
Finished Jul 01 04:53:15 PM PDT 24
Peak memory 160836 kb
Host smart-900024b6-a987-4270-9367-d9506bdb3998
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1223669546 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.1223669546
Directory /workspace/37.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.3856032407
Short name T80
Test name
Test status
Simulation time 336797510000 ps
CPU time 913.25 seconds
Started Jul 01 04:22:20 PM PDT 24
Finished Jul 01 05:00:41 PM PDT 24
Peak memory 160376 kb
Host smart-fc59b86c-4beb-4db8-ba1e-863229e60646
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3856032407 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.3856032407
Directory /workspace/38.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.12950810
Short name T83
Test name
Test status
Simulation time 336854550000 ps
CPU time 929.3 seconds
Started Jul 01 04:16:50 PM PDT 24
Finished Jul 01 04:55:18 PM PDT 24
Peak memory 160836 kb
Host smart-538b1512-f40b-49a8-91b1-6695878cbc36
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=12950810 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.12950810
Directory /workspace/39.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.1420365503
Short name T5
Test name
Test status
Simulation time 336488990000 ps
CPU time 907.67 seconds
Started Jul 01 04:21:09 PM PDT 24
Finished Jul 01 04:58:04 PM PDT 24
Peak memory 159420 kb
Host smart-dea4d5b0-51d7-4a62-829c-de2840d816b6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1420365503 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.1420365503
Directory /workspace/4.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.1372281538
Short name T100
Test name
Test status
Simulation time 336838890000 ps
CPU time 928.04 seconds
Started Jul 01 04:22:15 PM PDT 24
Finished Jul 01 05:00:42 PM PDT 24
Peak memory 160156 kb
Host smart-a1b966b9-0d25-4020-bb9c-99e13d70412f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1372281538 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.1372281538
Directory /workspace/40.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.2708669125
Short name T103
Test name
Test status
Simulation time 336578510000 ps
CPU time 946.05 seconds
Started Jul 01 04:19:19 PM PDT 24
Finished Jul 01 04:58:30 PM PDT 24
Peak memory 160908 kb
Host smart-c0b88e5e-9c41-4a96-bb5b-8d58f8145981
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2708669125 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.2708669125
Directory /workspace/41.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.237183911
Short name T15
Test name
Test status
Simulation time 336982310000 ps
CPU time 840.24 seconds
Started Jul 01 04:18:32 PM PDT 24
Finished Jul 01 04:52:51 PM PDT 24
Peak memory 160784 kb
Host smart-3af703cd-9888-43e8-afd8-30800e24986f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=237183911 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.237183911
Directory /workspace/42.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.316738678
Short name T85
Test name
Test status
Simulation time 336434870000 ps
CPU time 811.99 seconds
Started Jul 01 04:19:08 PM PDT 24
Finished Jul 01 04:52:08 PM PDT 24
Peak memory 160884 kb
Host smart-257425cf-a973-4276-a9a1-0047fb71263a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=316738678 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.316738678
Directory /workspace/43.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.3813629843
Short name T110
Test name
Test status
Simulation time 336349850000 ps
CPU time 952.67 seconds
Started Jul 01 04:20:07 PM PDT 24
Finished Jul 01 04:59:11 PM PDT 24
Peak memory 160848 kb
Host smart-a7e2f568-8b62-4d2b-b63b-62e8ea91be5f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3813629843 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.3813629843
Directory /workspace/44.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.3014993411
Short name T96
Test name
Test status
Simulation time 336596290000 ps
CPU time 563.09 seconds
Started Jul 01 04:20:36 PM PDT 24
Finished Jul 01 04:43:48 PM PDT 24
Peak memory 159768 kb
Host smart-89fd928d-d55c-434a-983d-4b2070a7da4c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3014993411 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.3014993411
Directory /workspace/45.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.1017356716
Short name T4
Test name
Test status
Simulation time 336549630000 ps
CPU time 822.83 seconds
Started Jul 01 04:19:24 PM PDT 24
Finished Jul 01 04:53:11 PM PDT 24
Peak memory 160788 kb
Host smart-42f2e6b0-3515-405d-9146-7109332fdd65
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1017356716 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.1017356716
Directory /workspace/46.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.2956986535
Short name T20
Test name
Test status
Simulation time 336818510000 ps
CPU time 825.91 seconds
Started Jul 01 04:17:38 PM PDT 24
Finished Jul 01 04:51:05 PM PDT 24
Peak memory 160892 kb
Host smart-c7c9e2bd-948a-489f-b9fa-5fdc6d476809
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2956986535 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.2956986535
Directory /workspace/47.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.416037831
Short name T76
Test name
Test status
Simulation time 336401050000 ps
CPU time 823.45 seconds
Started Jul 01 04:17:03 PM PDT 24
Finished Jul 01 04:50:11 PM PDT 24
Peak memory 160828 kb
Host smart-47c30601-dc8d-4d7a-8bd6-1f84caf83156
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=416037831 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.416037831
Directory /workspace/48.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.3255845810
Short name T79
Test name
Test status
Simulation time 336786730000 ps
CPU time 819.47 seconds
Started Jul 01 04:18:25 PM PDT 24
Finished Jul 01 04:51:48 PM PDT 24
Peak memory 160900 kb
Host smart-ce6347dd-bf63-4a7e-9f3e-cadda3c3e01a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3255845810 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.3255845810
Directory /workspace/49.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.1466307263
Short name T72
Test name
Test status
Simulation time 336463990000 ps
CPU time 938.57 seconds
Started Jul 01 04:19:19 PM PDT 24
Finished Jul 01 04:58:21 PM PDT 24
Peak memory 160896 kb
Host smart-a8b50ea0-8784-45cf-910a-16543bede4e6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1466307263 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.1466307263
Directory /workspace/5.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.3434172565
Short name T82
Test name
Test status
Simulation time 336866090000 ps
CPU time 825.51 seconds
Started Jul 01 04:17:36 PM PDT 24
Finished Jul 01 04:51:01 PM PDT 24
Peak memory 160884 kb
Host smart-3b49d87d-db2b-407f-8db4-4fa2837922e6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3434172565 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.3434172565
Directory /workspace/6.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.178761396
Short name T88
Test name
Test status
Simulation time 336725910000 ps
CPU time 899.54 seconds
Started Jul 01 04:17:25 PM PDT 24
Finished Jul 01 04:53:53 PM PDT 24
Peak memory 160832 kb
Host smart-c586657b-c591-4eff-bd14-ec6ffcca0813
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=178761396 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.178761396
Directory /workspace/7.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.2755262041
Short name T14
Test name
Test status
Simulation time 336967850000 ps
CPU time 888.52 seconds
Started Jul 01 04:20:12 PM PDT 24
Finished Jul 01 04:56:20 PM PDT 24
Peak memory 160848 kb
Host smart-ce17ed24-bcd8-45c1-b4c7-0797e44f3eb4
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2755262041 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.2755262041
Directory /workspace/8.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.637614225
Short name T19
Test name
Test status
Simulation time 336755890000 ps
CPU time 958.03 seconds
Started Jul 01 04:19:48 PM PDT 24
Finished Jul 01 04:59:20 PM PDT 24
Peak memory 160832 kb
Host smart-f19ea5ba-b47b-45db-bc9f-5dc4f6c9cf32
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=637614225 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.637614225
Directory /workspace/9.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.975004319
Short name T191
Test name
Test status
Simulation time 336601870000 ps
CPU time 774.72 seconds
Started Jul 01 04:29:38 PM PDT 24
Finished Jul 01 05:01:29 PM PDT 24
Peak memory 160708 kb
Host smart-c038c257-3fc6-44e7-ac39-8dda153933a0
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=975004319 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.975004319
Directory /workspace/0.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.2571749108
Short name T189
Test name
Test status
Simulation time 336387570000 ps
CPU time 793.45 seconds
Started Jul 01 04:29:30 PM PDT 24
Finished Jul 01 05:01:45 PM PDT 24
Peak memory 160704 kb
Host smart-cd6b8748-7a2e-4f17-963f-0b289b12bfaf
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2571749108 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.2571749108
Directory /workspace/1.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.149841156
Short name T196
Test name
Test status
Simulation time 336562610000 ps
CPU time 800.99 seconds
Started Jul 01 04:29:03 PM PDT 24
Finished Jul 01 05:01:57 PM PDT 24
Peak memory 160724 kb
Host smart-e1ceea8e-11db-4323-88b1-33abf46ead22
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=149841156 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.149841156
Directory /workspace/10.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.3913904472
Short name T197
Test name
Test status
Simulation time 336620010000 ps
CPU time 792.59 seconds
Started Jul 01 04:29:10 PM PDT 24
Finished Jul 01 05:01:23 PM PDT 24
Peak memory 160724 kb
Host smart-6f5bdf59-db9f-42a2-bbf5-23ba6383ff5a
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3913904472 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.3913904472
Directory /workspace/11.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.1355156978
Short name T178
Test name
Test status
Simulation time 336388130000 ps
CPU time 513.85 seconds
Started Jul 01 04:29:03 PM PDT 24
Finished Jul 01 04:51:17 PM PDT 24
Peak memory 160688 kb
Host smart-4bc48149-52cd-4581-b737-51525918e032
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1355156978 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.1355156978
Directory /workspace/12.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.2185389074
Short name T188
Test name
Test status
Simulation time 336806690000 ps
CPU time 771.55 seconds
Started Jul 01 04:29:07 PM PDT 24
Finished Jul 01 05:00:58 PM PDT 24
Peak memory 160732 kb
Host smart-6fa9e846-b221-45a9-a5bd-47707c2abcdd
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2185389074 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.2185389074
Directory /workspace/13.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.4232623753
Short name T193
Test name
Test status
Simulation time 336549490000 ps
CPU time 765.56 seconds
Started Jul 01 04:29:20 PM PDT 24
Finished Jul 01 05:00:45 PM PDT 24
Peak memory 160724 kb
Host smart-b211949c-7a8c-475d-96f3-c1341b5c833b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4232623753 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.4232623753
Directory /workspace/14.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.4150807136
Short name T164
Test name
Test status
Simulation time 337017370000 ps
CPU time 711.21 seconds
Started Jul 01 04:29:08 PM PDT 24
Finished Jul 01 04:58:25 PM PDT 24
Peak memory 160776 kb
Host smart-421dfa0c-3180-4208-b90b-feaf4da821f4
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4150807136 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.4150807136
Directory /workspace/15.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.1526770214
Short name T166
Test name
Test status
Simulation time 336988630000 ps
CPU time 763.26 seconds
Started Jul 01 04:29:20 PM PDT 24
Finished Jul 01 05:00:48 PM PDT 24
Peak memory 160724 kb
Host smart-2351300a-03f6-4848-b34b-7e4b9ff7bea0
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1526770214 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.1526770214
Directory /workspace/17.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.830651297
Short name T168
Test name
Test status
Simulation time 337026090000 ps
CPU time 682.3 seconds
Started Jul 01 04:29:05 PM PDT 24
Finished Jul 01 04:57:14 PM PDT 24
Peak memory 160716 kb
Host smart-08ed9752-9b3b-4790-a976-fa332890c4d5
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=830651297 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.830651297
Directory /workspace/18.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.103048654
Short name T25
Test name
Test status
Simulation time 336355490000 ps
CPU time 886.45 seconds
Started Jul 01 04:29:05 PM PDT 24
Finished Jul 01 05:05:49 PM PDT 24
Peak memory 160696 kb
Host smart-2dd2c1b7-b55c-44f1-81ef-86bff1134e6f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=103048654 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.103048654
Directory /workspace/19.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.3172062216
Short name T162
Test name
Test status
Simulation time 336739210000 ps
CPU time 941.34 seconds
Started Jul 01 04:28:59 PM PDT 24
Finished Jul 01 05:07:52 PM PDT 24
Peak memory 160716 kb
Host smart-c75cf2d5-ab81-4a4f-9d0b-76f684725726
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3172062216 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.3172062216
Directory /workspace/2.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.1803486177
Short name T185
Test name
Test status
Simulation time 336992830000 ps
CPU time 857.88 seconds
Started Jul 01 04:29:08 PM PDT 24
Finished Jul 01 05:05:30 PM PDT 24
Peak memory 160656 kb
Host smart-ac25d7a0-da80-4228-9c36-52cd85abbe65
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1803486177 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.1803486177
Directory /workspace/20.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.1907562647
Short name T171
Test name
Test status
Simulation time 336571010000 ps
CPU time 853.32 seconds
Started Jul 01 04:29:06 PM PDT 24
Finished Jul 01 05:04:57 PM PDT 24
Peak memory 160656 kb
Host smart-34f28ec2-0f71-455c-81e0-a2ac47e2eb40
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1907562647 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.1907562647
Directory /workspace/21.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.2333291418
Short name T163
Test name
Test status
Simulation time 336460070000 ps
CPU time 820.77 seconds
Started Jul 01 04:29:17 PM PDT 24
Finished Jul 01 05:04:08 PM PDT 24
Peak memory 160656 kb
Host smart-b66751c0-8e9a-4c85-8224-1a43e1b8e625
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2333291418 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.2333291418
Directory /workspace/22.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.61823655
Short name T199
Test name
Test status
Simulation time 336750870000 ps
CPU time 766.23 seconds
Started Jul 01 04:29:22 PM PDT 24
Finished Jul 01 05:01:02 PM PDT 24
Peak memory 160724 kb
Host smart-f6996ef7-bd46-41fa-943e-b673709542c7
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=61823655 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.61823655
Directory /workspace/23.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.1056554481
Short name T176
Test name
Test status
Simulation time 336820550000 ps
CPU time 735.48 seconds
Started Jul 01 04:29:12 PM PDT 24
Finished Jul 01 04:59:42 PM PDT 24
Peak memory 160816 kb
Host smart-b7246b22-d7d0-4cab-b62c-9d140ca4e7ba
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1056554481 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.1056554481
Directory /workspace/24.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.1784333044
Short name T165
Test name
Test status
Simulation time 336534950000 ps
CPU time 807.93 seconds
Started Jul 01 04:29:14 PM PDT 24
Finished Jul 01 05:02:37 PM PDT 24
Peak memory 160728 kb
Host smart-d0e84f0c-eae3-499c-9889-42257dc1ec0d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1784333044 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.1784333044
Directory /workspace/25.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.2616444686
Short name T29
Test name
Test status
Simulation time 336465910000 ps
CPU time 805.52 seconds
Started Jul 01 04:29:12 PM PDT 24
Finished Jul 01 05:02:18 PM PDT 24
Peak memory 160904 kb
Host smart-b16ef330-491c-48de-8469-097fa0ca8368
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2616444686 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.2616444686
Directory /workspace/26.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.3135724314
Short name T170
Test name
Test status
Simulation time 336638010000 ps
CPU time 716.74 seconds
Started Jul 01 04:29:22 PM PDT 24
Finished Jul 01 04:58:57 PM PDT 24
Peak memory 160724 kb
Host smart-f137f8fc-e428-4a79-8437-ceec0d7e2389
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3135724314 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.3135724314
Directory /workspace/27.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.900563181
Short name T161
Test name
Test status
Simulation time 336414310000 ps
CPU time 766.8 seconds
Started Jul 01 04:29:14 PM PDT 24
Finished Jul 01 05:00:56 PM PDT 24
Peak memory 160724 kb
Host smart-20c94bac-d882-4f92-b5fa-6566d6a44bc0
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=900563181 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.900563181
Directory /workspace/28.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.2295753778
Short name T179
Test name
Test status
Simulation time 336589750000 ps
CPU time 739.7 seconds
Started Jul 01 04:29:18 PM PDT 24
Finished Jul 01 04:59:41 PM PDT 24
Peak memory 160712 kb
Host smart-63612a67-34a2-4de6-9763-8308773630fe
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2295753778 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.2295753778
Directory /workspace/29.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.4265080876
Short name T195
Test name
Test status
Simulation time 337034750000 ps
CPU time 847.62 seconds
Started Jul 01 04:29:29 PM PDT 24
Finished Jul 01 05:04:36 PM PDT 24
Peak memory 160828 kb
Host smart-dd4f4e99-40e4-43db-89ee-c865e2aa0d27
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4265080876 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.4265080876
Directory /workspace/3.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.2431439528
Short name T181
Test name
Test status
Simulation time 336782290000 ps
CPU time 808.71 seconds
Started Jul 01 04:29:18 PM PDT 24
Finished Jul 01 05:02:20 PM PDT 24
Peak memory 160676 kb
Host smart-3c21b1fd-c918-4390-b45b-62e3bb836ff7
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2431439528 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.2431439528
Directory /workspace/30.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.3900368485
Short name T169
Test name
Test status
Simulation time 336567230000 ps
CPU time 707.29 seconds
Started Jul 01 04:29:09 PM PDT 24
Finished Jul 01 04:58:16 PM PDT 24
Peak memory 160704 kb
Host smart-196bd474-f957-4e58-9c40-021971946d36
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3900368485 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.3900368485
Directory /workspace/31.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.2190145394
Short name T190
Test name
Test status
Simulation time 336531770000 ps
CPU time 661.89 seconds
Started Jul 01 04:29:19 PM PDT 24
Finished Jul 01 04:56:31 PM PDT 24
Peak memory 160672 kb
Host smart-992c6fc1-f380-43b8-a1cd-ede15ab8dd48
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2190145394 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.2190145394
Directory /workspace/32.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.3757069668
Short name T177
Test name
Test status
Simulation time 336497950000 ps
CPU time 654.87 seconds
Started Jul 01 04:29:14 PM PDT 24
Finished Jul 01 04:56:31 PM PDT 24
Peak memory 160724 kb
Host smart-6567927a-14f4-4227-b91d-2d9ec1783b10
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3757069668 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.3757069668
Directory /workspace/33.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.1249732907
Short name T174
Test name
Test status
Simulation time 336419830000 ps
CPU time 893.33 seconds
Started Jul 01 04:29:05 PM PDT 24
Finished Jul 01 05:06:17 PM PDT 24
Peak memory 160912 kb
Host smart-f24f6428-358e-4088-a8f9-33ece5e15ee4
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1249732907 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.1249732907
Directory /workspace/34.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.3744113986
Short name T192
Test name
Test status
Simulation time 336751090000 ps
CPU time 842.95 seconds
Started Jul 01 04:29:22 PM PDT 24
Finished Jul 01 05:03:50 PM PDT 24
Peak memory 160844 kb
Host smart-1fe6c9ed-9a32-4d69-b6b5-9863802e5d89
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3744113986 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.3744113986
Directory /workspace/35.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.2148599092
Short name T24
Test name
Test status
Simulation time 336460650000 ps
CPU time 813.96 seconds
Started Jul 01 04:29:10 PM PDT 24
Finished Jul 01 05:02:48 PM PDT 24
Peak memory 160988 kb
Host smart-638833d3-3b62-4523-9f3f-1dafa14d6310
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2148599092 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.2148599092
Directory /workspace/36.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.1074593389
Short name T187
Test name
Test status
Simulation time 336884190000 ps
CPU time 684.13 seconds
Started Jul 01 04:29:16 PM PDT 24
Finished Jul 01 04:57:35 PM PDT 24
Peak memory 160724 kb
Host smart-fe65d714-d4d2-4d55-a86b-a5b5f84db09b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1074593389 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.1074593389
Directory /workspace/37.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.2441001682
Short name T172
Test name
Test status
Simulation time 337161070000 ps
CPU time 771.4 seconds
Started Jul 01 04:29:26 PM PDT 24
Finished Jul 01 05:01:07 PM PDT 24
Peak memory 160724 kb
Host smart-f8217ef6-80dd-4f49-b4a0-8f2aef3ec50a
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2441001682 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.2441001682
Directory /workspace/38.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.1919653889
Short name T167
Test name
Test status
Simulation time 336378170000 ps
CPU time 720.31 seconds
Started Jul 01 04:29:20 PM PDT 24
Finished Jul 01 04:59:15 PM PDT 24
Peak memory 160796 kb
Host smart-964b124a-975b-4a27-8cb2-758bf1b277fb
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1919653889 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.1919653889
Directory /workspace/39.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.1743294188
Short name T26
Test name
Test status
Simulation time 336396370000 ps
CPU time 822.82 seconds
Started Jul 01 04:29:24 PM PDT 24
Finished Jul 01 05:03:02 PM PDT 24
Peak memory 160724 kb
Host smart-b86194c8-d64d-45f9-bc73-04a1c5eed31a
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1743294188 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.1743294188
Directory /workspace/4.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.1809824873
Short name T180
Test name
Test status
Simulation time 337085810000 ps
CPU time 868.61 seconds
Started Jul 01 04:29:07 PM PDT 24
Finished Jul 01 05:05:00 PM PDT 24
Peak memory 160704 kb
Host smart-aab5d254-8cf7-48f1-b623-6cd2887ba80d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1809824873 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.1809824873
Directory /workspace/40.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.1834115555
Short name T194
Test name
Test status
Simulation time 336479050000 ps
CPU time 736.66 seconds
Started Jul 01 04:29:17 PM PDT 24
Finished Jul 01 04:59:17 PM PDT 24
Peak memory 160740 kb
Host smart-f37376b1-7e92-452d-8475-43b2558c8f62
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1834115555 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.1834115555
Directory /workspace/41.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.3864625217
Short name T198
Test name
Test status
Simulation time 336855230000 ps
CPU time 863.1 seconds
Started Jul 01 04:29:33 PM PDT 24
Finished Jul 01 05:05:31 PM PDT 24
Peak memory 160672 kb
Host smart-5182bb36-d979-4160-9498-ef7958ba9ff8
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3864625217 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.3864625217
Directory /workspace/42.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.3068651983
Short name T183
Test name
Test status
Simulation time 336956390000 ps
CPU time 809.61 seconds
Started Jul 01 04:29:34 PM PDT 24
Finished Jul 01 05:02:21 PM PDT 24
Peak memory 160896 kb
Host smart-cc3838d1-e8a6-4d09-9554-9ac96e086c7f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3068651983 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.3068651983
Directory /workspace/43.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.1454742561
Short name T175
Test name
Test status
Simulation time 336773910000 ps
CPU time 686.01 seconds
Started Jul 01 04:29:27 PM PDT 24
Finished Jul 01 04:57:54 PM PDT 24
Peak memory 160816 kb
Host smart-9efbd565-e74f-4b28-8f6c-00e34a898b44
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1454742561 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.1454742561
Directory /workspace/44.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.4265730684
Short name T30
Test name
Test status
Simulation time 336530170000 ps
CPU time 815.25 seconds
Started Jul 01 04:29:27 PM PDT 24
Finished Jul 01 05:02:44 PM PDT 24
Peak memory 160916 kb
Host smart-0755a37b-df22-4ae2-a079-8fb0cf9b733c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4265730684 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.4265730684
Directory /workspace/45.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.2711425041
Short name T182
Test name
Test status
Simulation time 336848790000 ps
CPU time 689.53 seconds
Started Jul 01 04:29:09 PM PDT 24
Finished Jul 01 04:57:29 PM PDT 24
Peak memory 160804 kb
Host smart-2a1d5172-02c5-42f9-ac56-e06e57272ee0
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2711425041 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.2711425041
Directory /workspace/46.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.1481108509
Short name T27
Test name
Test status
Simulation time 336723630000 ps
CPU time 679.02 seconds
Started Jul 01 04:29:32 PM PDT 24
Finished Jul 01 04:57:08 PM PDT 24
Peak memory 160724 kb
Host smart-1bd8a181-0d1d-44f6-baa2-20271ab449b4
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1481108509 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.1481108509
Directory /workspace/47.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.2088836978
Short name T23
Test name
Test status
Simulation time 336975710000 ps
CPU time 867.15 seconds
Started Jul 01 04:29:39 PM PDT 24
Finished Jul 01 05:05:42 PM PDT 24
Peak memory 160672 kb
Host smart-50b5ae4e-b0b1-4bd0-b23e-fd15a43f85ba
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2088836978 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.2088836978
Directory /workspace/48.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.3740990017
Short name T200
Test name
Test status
Simulation time 336459490000 ps
CPU time 869.22 seconds
Started Jul 01 04:29:29 PM PDT 24
Finished Jul 01 05:05:35 PM PDT 24
Peak memory 160672 kb
Host smart-7f19030b-9ffc-4449-a1d8-dff2957a25f7
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3740990017 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.3740990017
Directory /workspace/49.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.1253040550
Short name T28
Test name
Test status
Simulation time 336938570000 ps
CPU time 866.28 seconds
Started Jul 01 04:29:24 PM PDT 24
Finished Jul 01 05:05:13 PM PDT 24
Peak memory 160696 kb
Host smart-c910565f-2bdf-4d88-ac83-affb8c24e4bf
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1253040550 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.1253040550
Directory /workspace/5.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.1146402732
Short name T21
Test name
Test status
Simulation time 336456010000 ps
CPU time 844.56 seconds
Started Jul 01 04:29:13 PM PDT 24
Finished Jul 01 05:03:37 PM PDT 24
Peak memory 160836 kb
Host smart-ee018cf0-70e5-44b2-8f51-42d3306ddb23
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1146402732 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.1146402732
Directory /workspace/6.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.1547205653
Short name T184
Test name
Test status
Simulation time 336732710000 ps
CPU time 923.72 seconds
Started Jul 01 04:29:10 PM PDT 24
Finished Jul 01 05:07:30 PM PDT 24
Peak memory 160716 kb
Host smart-8d6c4852-75cf-489d-ba75-3c28f9a1861b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1547205653 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.1547205653
Directory /workspace/7.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.3029151144
Short name T173
Test name
Test status
Simulation time 336972470000 ps
CPU time 679.19 seconds
Started Jul 01 04:28:58 PM PDT 24
Finished Jul 01 04:56:58 PM PDT 24
Peak memory 160724 kb
Host smart-23f9246a-1313-4a73-a477-f99f0879efa3
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3029151144 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.3029151144
Directory /workspace/8.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.2370907396
Short name T186
Test name
Test status
Simulation time 336926750000 ps
CPU time 731.18 seconds
Started Jul 01 04:29:19 PM PDT 24
Finished Jul 01 04:59:16 PM PDT 24
Peak memory 160736 kb
Host smart-1a56e67d-69d6-4b66-8f97-641b2e55f3d9
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2370907396 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.2370907396
Directory /workspace/9.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.3317030015
Short name T160
Test name
Test status
Simulation time 1426930000 ps
CPU time 3.99 seconds
Started Jul 01 04:29:17 PM PDT 24
Finished Jul 01 04:29:35 PM PDT 24
Peak memory 164868 kb
Host smart-5bdc58b7-05a2-4184-aa87-a4527e72467c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3317030015 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.3317030015
Directory /workspace/0.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.1363928240
Short name T141
Test name
Test status
Simulation time 1389470000 ps
CPU time 3.46 seconds
Started Jul 01 04:28:54 PM PDT 24
Finished Jul 01 04:29:16 PM PDT 24
Peak memory 164876 kb
Host smart-2aae40c6-f6d8-4647-bd8e-31b03304e235
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1363928240 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.1363928240
Directory /workspace/1.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.792222440
Short name T112
Test name
Test status
Simulation time 1360550000 ps
CPU time 3.84 seconds
Started Jul 01 04:29:14 PM PDT 24
Finished Jul 01 04:29:32 PM PDT 24
Peak memory 164864 kb
Host smart-d97d71b9-b96a-44af-ab10-53cc9de33f83
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=792222440 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.792222440
Directory /workspace/10.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.812059629
Short name T153
Test name
Test status
Simulation time 1513050000 ps
CPU time 2.99 seconds
Started Jul 01 04:29:04 PM PDT 24
Finished Jul 01 04:29:22 PM PDT 24
Peak memory 164844 kb
Host smart-d4b4ea09-f902-4fa5-9dba-9ec1f7518cc3
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=812059629 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.812059629
Directory /workspace/11.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.125248111
Short name T124
Test name
Test status
Simulation time 1409410000 ps
CPU time 3.98 seconds
Started Jul 01 04:29:11 PM PDT 24
Finished Jul 01 04:29:29 PM PDT 24
Peak memory 164864 kb
Host smart-5465983f-ab90-45c7-aea6-9c15f3627aae
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=125248111 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.125248111
Directory /workspace/12.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.3437368328
Short name T143
Test name
Test status
Simulation time 1494330000 ps
CPU time 3.73 seconds
Started Jul 01 04:28:55 PM PDT 24
Finished Jul 01 04:29:17 PM PDT 24
Peak memory 164836 kb
Host smart-a41f4a3b-952e-4a67-be20-970e6a969ad0
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3437368328 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.3437368328
Directory /workspace/13.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.449916753
Short name T148
Test name
Test status
Simulation time 1535350000 ps
CPU time 4.07 seconds
Started Jul 01 04:28:52 PM PDT 24
Finished Jul 01 04:29:15 PM PDT 24
Peak memory 164872 kb
Host smart-d3ad8aab-f921-4905-a0a8-825e294714d0
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=449916753 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.449916753
Directory /workspace/14.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.1275763183
Short name T117
Test name
Test status
Simulation time 1078590000 ps
CPU time 3.16 seconds
Started Jul 01 04:28:54 PM PDT 24
Finished Jul 01 04:29:15 PM PDT 24
Peak memory 164848 kb
Host smart-1687fe12-d36c-4ed9-b03a-831bd5cc3a5f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1275763183 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.1275763183
Directory /workspace/15.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.1250560555
Short name T128
Test name
Test status
Simulation time 1568650000 ps
CPU time 3.37 seconds
Started Jul 01 04:28:57 PM PDT 24
Finished Jul 01 04:29:19 PM PDT 24
Peak memory 164772 kb
Host smart-347737fc-47ca-4bde-a2d4-780ae8034269
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1250560555 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.1250560555
Directory /workspace/16.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.1007894551
Short name T130
Test name
Test status
Simulation time 1535350000 ps
CPU time 5.12 seconds
Started Jul 01 04:29:03 PM PDT 24
Finished Jul 01 04:29:26 PM PDT 24
Peak memory 164928 kb
Host smart-dc8eff15-9c29-4e62-b4ed-6335c5f5a13a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1007894551 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.1007894551
Directory /workspace/17.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.3435728323
Short name T129
Test name
Test status
Simulation time 1587950000 ps
CPU time 4.9 seconds
Started Jul 01 04:29:16 PM PDT 24
Finished Jul 01 04:29:35 PM PDT 24
Peak memory 164868 kb
Host smart-d3dff84d-2059-44e5-a88c-4634fe906eaf
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3435728323 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.3435728323
Directory /workspace/18.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.910087021
Short name T120
Test name
Test status
Simulation time 1150190000 ps
CPU time 3.37 seconds
Started Jul 01 04:29:26 PM PDT 24
Finished Jul 01 04:29:41 PM PDT 24
Peak memory 164928 kb
Host smart-43668c3d-1fa1-40a6-aeb6-a0eefb851945
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=910087021 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.910087021
Directory /workspace/19.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.437561944
Short name T125
Test name
Test status
Simulation time 1565710000 ps
CPU time 4.28 seconds
Started Jul 01 04:28:53 PM PDT 24
Finished Jul 01 04:29:17 PM PDT 24
Peak memory 164772 kb
Host smart-9fa94835-3c65-40c2-afc5-95ecce03179c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=437561944 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.437561944
Directory /workspace/2.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.3240325725
Short name T149
Test name
Test status
Simulation time 1596750000 ps
CPU time 3.25 seconds
Started Jul 01 04:28:57 PM PDT 24
Finished Jul 01 04:29:19 PM PDT 24
Peak memory 164852 kb
Host smart-1ff8318b-9f25-42bb-862f-acf267f00fb3
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3240325725 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.3240325725
Directory /workspace/20.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.90502482
Short name T121
Test name
Test status
Simulation time 1321870000 ps
CPU time 3.03 seconds
Started Jul 01 04:28:59 PM PDT 24
Finished Jul 01 04:29:19 PM PDT 24
Peak memory 164792 kb
Host smart-661afee6-1597-4c02-bb5e-d12ed3d6903c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=90502482 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.90502482
Directory /workspace/21.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.3980252482
Short name T113
Test name
Test status
Simulation time 1565050000 ps
CPU time 4.42 seconds
Started Jul 01 04:28:55 PM PDT 24
Finished Jul 01 04:29:19 PM PDT 24
Peak memory 164876 kb
Host smart-0c633716-a380-4661-9fcc-ac8431757544
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3980252482 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.3980252482
Directory /workspace/22.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.2973761411
Short name T144
Test name
Test status
Simulation time 1478450000 ps
CPU time 4.42 seconds
Started Jul 01 04:29:04 PM PDT 24
Finished Jul 01 04:29:25 PM PDT 24
Peak memory 164932 kb
Host smart-7500a7bb-e1b9-444a-9b96-c42204eb853e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2973761411 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.2973761411
Directory /workspace/23.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.3523246799
Short name T135
Test name
Test status
Simulation time 1413930000 ps
CPU time 3.21 seconds
Started Jul 01 04:29:06 PM PDT 24
Finished Jul 01 04:29:23 PM PDT 24
Peak memory 164868 kb
Host smart-4d641401-2e58-482b-9d02-c68e2f476f87
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3523246799 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.3523246799
Directory /workspace/24.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.593525440
Short name T140
Test name
Test status
Simulation time 1278810000 ps
CPU time 4.39 seconds
Started Jul 01 04:28:56 PM PDT 24
Finished Jul 01 04:29:19 PM PDT 24
Peak memory 165032 kb
Host smart-1c44fd3f-1407-4957-8abe-b032112be400
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=593525440 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.593525440
Directory /workspace/25.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.3394205529
Short name T123
Test name
Test status
Simulation time 1371910000 ps
CPU time 5.06 seconds
Started Jul 01 04:28:57 PM PDT 24
Finished Jul 01 04:29:23 PM PDT 24
Peak memory 164988 kb
Host smart-bc04c3b9-4a30-4e61-8337-9c061d5a2243
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3394205529 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.3394205529
Directory /workspace/26.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.295633263
Short name T118
Test name
Test status
Simulation time 1444350000 ps
CPU time 4.09 seconds
Started Jul 01 04:28:56 PM PDT 24
Finished Jul 01 04:29:18 PM PDT 24
Peak memory 164864 kb
Host smart-426c85c1-d3f1-42c7-92f1-06d868a2f48e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=295633263 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.295633263
Directory /workspace/27.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.99130316
Short name T139
Test name
Test status
Simulation time 1367650000 ps
CPU time 3.96 seconds
Started Jul 01 04:29:11 PM PDT 24
Finished Jul 01 04:29:29 PM PDT 24
Peak memory 164924 kb
Host smart-8e86cd23-2cba-495e-9519-7886bdaa651b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=99130316 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.99130316
Directory /workspace/28.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.3117107602
Short name T158
Test name
Test status
Simulation time 1422530000 ps
CPU time 3.36 seconds
Started Jul 01 04:28:56 PM PDT 24
Finished Jul 01 04:29:18 PM PDT 24
Peak memory 164848 kb
Host smart-de12f894-827d-4c34-ae7e-9e889c9f4055
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3117107602 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.3117107602
Directory /workspace/29.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.974514682
Short name T119
Test name
Test status
Simulation time 1453670000 ps
CPU time 3.32 seconds
Started Jul 01 04:29:02 PM PDT 24
Finished Jul 01 04:29:22 PM PDT 24
Peak memory 164792 kb
Host smart-3869d193-2da0-4ab2-b3e3-ce24d2b1d4f6
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=974514682 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.974514682
Directory /workspace/3.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.582431220
Short name T132
Test name
Test status
Simulation time 1378550000 ps
CPU time 3.53 seconds
Started Jul 01 04:29:02 PM PDT 24
Finished Jul 01 04:29:22 PM PDT 24
Peak memory 164740 kb
Host smart-3e18fff8-3364-4473-bd54-04fd1017ef7f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=582431220 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.582431220
Directory /workspace/30.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.3775336448
Short name T145
Test name
Test status
Simulation time 1626550000 ps
CPU time 3.64 seconds
Started Jul 01 04:29:05 PM PDT 24
Finished Jul 01 04:29:24 PM PDT 24
Peak memory 164868 kb
Host smart-c6cd7a6d-3bc4-4b66-a7b6-07f7975f848d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3775336448 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.3775336448
Directory /workspace/31.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.1998052845
Short name T147
Test name
Test status
Simulation time 1559650000 ps
CPU time 3.97 seconds
Started Jul 01 04:28:56 PM PDT 24
Finished Jul 01 04:29:19 PM PDT 24
Peak memory 164868 kb
Host smart-bb9c61d3-f571-4305-9464-94612a321136
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1998052845 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.1998052845
Directory /workspace/32.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.1780013023
Short name T138
Test name
Test status
Simulation time 1516990000 ps
CPU time 4.82 seconds
Started Jul 01 04:29:03 PM PDT 24
Finished Jul 01 04:29:25 PM PDT 24
Peak memory 164972 kb
Host smart-85fbfb32-9fed-4b00-a4c4-f6da7c42ecfd
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1780013023 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.1780013023
Directory /workspace/33.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.2302753458
Short name T111
Test name
Test status
Simulation time 1514590000 ps
CPU time 4.08 seconds
Started Jul 01 04:29:10 PM PDT 24
Finished Jul 01 04:29:29 PM PDT 24
Peak memory 164872 kb
Host smart-713f100d-9f83-4724-8fc3-e5a70ab27561
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2302753458 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.2302753458
Directory /workspace/34.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.2013768129
Short name T137
Test name
Test status
Simulation time 1555770000 ps
CPU time 5.82 seconds
Started Jul 01 04:28:57 PM PDT 24
Finished Jul 01 04:29:23 PM PDT 24
Peak memory 164988 kb
Host smart-8179d889-f934-4752-8f69-49373e48136b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2013768129 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.2013768129
Directory /workspace/35.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.3796279004
Short name T122
Test name
Test status
Simulation time 1451770000 ps
CPU time 3.4 seconds
Started Jul 01 04:28:59 PM PDT 24
Finished Jul 01 04:29:20 PM PDT 24
Peak memory 164848 kb
Host smart-050b298a-73cc-4b3d-8cf4-42380b78cb1e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3796279004 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.3796279004
Directory /workspace/36.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.4111239831
Short name T142
Test name
Test status
Simulation time 1387950000 ps
CPU time 3.24 seconds
Started Jul 01 04:29:16 PM PDT 24
Finished Jul 01 04:29:32 PM PDT 24
Peak memory 164924 kb
Host smart-24b0b75e-9c79-4b31-8797-5f2fd2a8244c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4111239831 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.4111239831
Directory /workspace/37.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.1510409763
Short name T151
Test name
Test status
Simulation time 1610790000 ps
CPU time 6.31 seconds
Started Jul 01 04:28:57 PM PDT 24
Finished Jul 01 04:29:25 PM PDT 24
Peak memory 164988 kb
Host smart-ccbf5399-a37c-4087-ba3c-98eb3d68050b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1510409763 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.1510409763
Directory /workspace/38.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.3468661771
Short name T126
Test name
Test status
Simulation time 1378230000 ps
CPU time 3.28 seconds
Started Jul 01 04:29:30 PM PDT 24
Finished Jul 01 04:29:44 PM PDT 24
Peak memory 164808 kb
Host smart-2d677302-6d4e-47c8-8c21-afcfa83ee344
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3468661771 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.3468661771
Directory /workspace/39.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.2159954414
Short name T114
Test name
Test status
Simulation time 1601550000 ps
CPU time 3.27 seconds
Started Jul 01 04:28:52 PM PDT 24
Finished Jul 01 04:29:13 PM PDT 24
Peak memory 164788 kb
Host smart-d17e8946-bcf6-4550-ad2d-acb06c1332a8
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2159954414 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.2159954414
Directory /workspace/4.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.4009533364
Short name T152
Test name
Test status
Simulation time 1494530000 ps
CPU time 3.71 seconds
Started Jul 01 04:29:17 PM PDT 24
Finished Jul 01 04:29:34 PM PDT 24
Peak memory 164716 kb
Host smart-52ee33d3-afb1-46cf-a2ff-f56c076a0b9e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4009533364 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.4009533364
Directory /workspace/40.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.1611824740
Short name T157
Test name
Test status
Simulation time 1404390000 ps
CPU time 3.22 seconds
Started Jul 01 04:29:16 PM PDT 24
Finished Jul 01 04:29:33 PM PDT 24
Peak memory 164748 kb
Host smart-c5937723-7c07-41af-bcf0-054c9a834f04
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1611824740 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.1611824740
Directory /workspace/41.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.183767125
Short name T155
Test name
Test status
Simulation time 1444170000 ps
CPU time 4.82 seconds
Started Jul 01 04:29:30 PM PDT 24
Finished Jul 01 04:29:47 PM PDT 24
Peak memory 164844 kb
Host smart-a49ec8f7-2a2b-4e5a-be62-aa693fa659ae
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=183767125 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.183767125
Directory /workspace/42.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.3567226001
Short name T136
Test name
Test status
Simulation time 1438050000 ps
CPU time 4.05 seconds
Started Jul 01 04:29:20 PM PDT 24
Finished Jul 01 04:29:37 PM PDT 24
Peak memory 164876 kb
Host smart-b09156af-b4a2-4103-955b-fa0939076800
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3567226001 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.3567226001
Directory /workspace/43.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.1000370451
Short name T156
Test name
Test status
Simulation time 1474910000 ps
CPU time 4.68 seconds
Started Jul 01 04:29:24 PM PDT 24
Finished Jul 01 04:29:42 PM PDT 24
Peak memory 164932 kb
Host smart-57a3132a-dfdb-48ce-9ed3-f3b3e1ab6a8a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1000370451 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.1000370451
Directory /workspace/44.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.3912759302
Short name T131
Test name
Test status
Simulation time 1526670000 ps
CPU time 4.24 seconds
Started Jul 01 04:28:56 PM PDT 24
Finished Jul 01 04:29:20 PM PDT 24
Peak memory 164868 kb
Host smart-4ce0364e-0377-4379-9b47-ec8488bb3609
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3912759302 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.3912759302
Directory /workspace/45.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.12449982
Short name T154
Test name
Test status
Simulation time 1541610000 ps
CPU time 4.6 seconds
Started Jul 01 04:28:58 PM PDT 24
Finished Jul 01 04:29:22 PM PDT 24
Peak memory 164940 kb
Host smart-8c495f80-2b34-4e63-b6e6-07f71fa3378b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=12449982 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.12449982
Directory /workspace/46.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.2760609640
Short name T134
Test name
Test status
Simulation time 1380430000 ps
CPU time 2.99 seconds
Started Jul 01 04:28:59 PM PDT 24
Finished Jul 01 04:29:19 PM PDT 24
Peak memory 164716 kb
Host smart-592dcbb5-8adc-43f0-8916-4115c1e163fa
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2760609640 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.2760609640
Directory /workspace/47.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.3687681358
Short name T150
Test name
Test status
Simulation time 1536870000 ps
CPU time 3.87 seconds
Started Jul 01 04:29:25 PM PDT 24
Finished Jul 01 04:29:41 PM PDT 24
Peak memory 164808 kb
Host smart-db0ad1b6-40a9-4fad-a77a-000bda0b575b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3687681358 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.3687681358
Directory /workspace/48.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.451812500
Short name T146
Test name
Test status
Simulation time 1251330000 ps
CPU time 3.7 seconds
Started Jul 01 04:29:15 PM PDT 24
Finished Jul 01 04:29:36 PM PDT 24
Peak memory 164768 kb
Host smart-949cdc72-fd87-486b-9b3e-dfb1db79393c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=451812500 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.451812500
Directory /workspace/49.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.4079190144
Short name T115
Test name
Test status
Simulation time 1527270000 ps
CPU time 3.24 seconds
Started Jul 01 04:28:56 PM PDT 24
Finished Jul 01 04:29:17 PM PDT 24
Peak memory 164848 kb
Host smart-6a7cc426-68e3-4e22-969d-3fbb46664fe1
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4079190144 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.4079190144
Directory /workspace/5.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.586667621
Short name T116
Test name
Test status
Simulation time 1507210000 ps
CPU time 3.95 seconds
Started Jul 01 04:28:51 PM PDT 24
Finished Jul 01 04:29:14 PM PDT 24
Peak memory 164800 kb
Host smart-84511c1e-e1c2-4425-a792-b00ff3f2c21a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=586667621 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.586667621
Directory /workspace/6.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.2949953291
Short name T127
Test name
Test status
Simulation time 1530310000 ps
CPU time 3.95 seconds
Started Jul 01 04:28:57 PM PDT 24
Finished Jul 01 04:29:20 PM PDT 24
Peak memory 164836 kb
Host smart-f1f6fa51-3cd9-48f6-8083-a92e3fa34134
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2949953291 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.2949953291
Directory /workspace/7.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1147802023
Short name T159
Test name
Test status
Simulation time 1219590000 ps
CPU time 2.75 seconds
Started Jul 01 04:28:55 PM PDT 24
Finished Jul 01 04:29:16 PM PDT 24
Peak memory 164872 kb
Host smart-dc2157a2-5943-4500-88c8-40c90312f8a7
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1147802023 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.1147802023
Directory /workspace/8.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2756284070
Short name T133
Test name
Test status
Simulation time 1470690000 ps
CPU time 4.16 seconds
Started Jul 01 04:28:55 PM PDT 24
Finished Jul 01 04:29:19 PM PDT 24
Peak memory 164868 kb
Host smart-db31b4cb-8eb0-4346-ba09-674034d56cf0
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2756284070 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.2756284070
Directory /workspace/9.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.1169506661
Short name T41
Test name
Test status
Simulation time 1599630000 ps
CPU time 4.92 seconds
Started Jul 01 04:18:24 PM PDT 24
Finished Jul 01 04:18:35 PM PDT 24
Peak memory 164940 kb
Host smart-fcedb327-a540-4838-bfee-2f1721009d76
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1169506661 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.1169506661
Directory /workspace/0.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.3906941233
Short name T37
Test name
Test status
Simulation time 1416830000 ps
CPU time 4.49 seconds
Started Jul 01 04:21:33 PM PDT 24
Finished Jul 01 04:21:46 PM PDT 24
Peak memory 164680 kb
Host smart-027c9577-d41a-47bd-acdc-959b99da3223
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3906941233 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.3906941233
Directory /workspace/1.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.63855938
Short name T70
Test name
Test status
Simulation time 1459270000 ps
CPU time 4.92 seconds
Started Jul 01 04:18:54 PM PDT 24
Finished Jul 01 04:19:06 PM PDT 24
Peak memory 164908 kb
Host smart-91188363-38ba-412f-bf04-b24ae0158031
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=63855938 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.63855938
Directory /workspace/10.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.4032217552
Short name T64
Test name
Test status
Simulation time 1447810000 ps
CPU time 3.32 seconds
Started Jul 01 04:20:36 PM PDT 24
Finished Jul 01 04:20:45 PM PDT 24
Peak memory 163404 kb
Host smart-a9975579-4522-4da6-803a-af28059a5620
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4032217552 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.4032217552
Directory /workspace/11.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.3893575265
Short name T38
Test name
Test status
Simulation time 1400530000 ps
CPU time 5.02 seconds
Started Jul 01 04:18:20 PM PDT 24
Finished Jul 01 04:18:31 PM PDT 24
Peak memory 165028 kb
Host smart-346e04e3-b8c9-4e77-be97-ac51d4d9b195
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3893575265 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.3893575265
Directory /workspace/12.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.358031792
Short name T39
Test name
Test status
Simulation time 1572230000 ps
CPU time 4.5 seconds
Started Jul 01 04:20:52 PM PDT 24
Finished Jul 01 04:21:03 PM PDT 24
Peak memory 164520 kb
Host smart-7496839d-f1ae-43eb-ac13-ee6c2c1efa8c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=358031792 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.358031792
Directory /workspace/14.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.2802474229
Short name T12
Test name
Test status
Simulation time 1362830000 ps
CPU time 4.06 seconds
Started Jul 01 04:18:23 PM PDT 24
Finished Jul 01 04:18:32 PM PDT 24
Peak memory 164996 kb
Host smart-98522bbb-0b4f-4dda-b921-f516648b78a4
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2802474229 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.2802474229
Directory /workspace/15.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.2364810868
Short name T45
Test name
Test status
Simulation time 1314110000 ps
CPU time 4.06 seconds
Started Jul 01 04:18:38 PM PDT 24
Finished Jul 01 04:18:47 PM PDT 24
Peak memory 164964 kb
Host smart-c1790ac5-4607-4bd7-9435-b93d62ad747b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2364810868 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.2364810868
Directory /workspace/16.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.3817601034
Short name T53
Test name
Test status
Simulation time 1469810000 ps
CPU time 4.9 seconds
Started Jul 01 04:20:16 PM PDT 24
Finished Jul 01 04:20:28 PM PDT 24
Peak memory 165036 kb
Host smart-f4b9f230-27b0-4881-b58f-46cdff6e283b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3817601034 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.3817601034
Directory /workspace/17.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.1748318593
Short name T56
Test name
Test status
Simulation time 1429130000 ps
CPU time 4.1 seconds
Started Jul 01 04:18:27 PM PDT 24
Finished Jul 01 04:18:37 PM PDT 24
Peak memory 164952 kb
Host smart-ecab2480-7d68-48ba-8e09-7baa74f6c742
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1748318593 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.1748318593
Directory /workspace/18.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.4140865041
Short name T46
Test name
Test status
Simulation time 1558490000 ps
CPU time 4.89 seconds
Started Jul 01 04:16:50 PM PDT 24
Finished Jul 01 04:17:02 PM PDT 24
Peak memory 164972 kb
Host smart-98a0146b-af77-4e88-b1e8-8de6c17c2dcf
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4140865041 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.4140865041
Directory /workspace/19.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.2937854761
Short name T11
Test name
Test status
Simulation time 1559350000 ps
CPU time 3.94 seconds
Started Jul 01 04:16:50 PM PDT 24
Finished Jul 01 04:16:59 PM PDT 24
Peak memory 164952 kb
Host smart-fc10c59e-5487-469b-a54e-c825a83e97f1
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2937854761 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.2937854761
Directory /workspace/2.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.4256791098
Short name T65
Test name
Test status
Simulation time 1303890000 ps
CPU time 3.22 seconds
Started Jul 01 04:20:36 PM PDT 24
Finished Jul 01 04:20:45 PM PDT 24
Peak memory 164016 kb
Host smart-aad24acc-af66-4911-b415-1240319adb0d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4256791098 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.4256791098
Directory /workspace/20.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.1127090252
Short name T31
Test name
Test status
Simulation time 1156210000 ps
CPU time 3.02 seconds
Started Jul 01 04:16:39 PM PDT 24
Finished Jul 01 04:16:46 PM PDT 24
Peak memory 164952 kb
Host smart-70b6ea99-50da-4d5e-934d-892fa83ba686
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1127090252 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.1127090252
Directory /workspace/21.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.2979400216
Short name T34
Test name
Test status
Simulation time 1447150000 ps
CPU time 3.93 seconds
Started Jul 01 04:18:29 PM PDT 24
Finished Jul 01 04:18:38 PM PDT 24
Peak memory 164972 kb
Host smart-e4debf6e-4487-4c70-9f32-5b97ef014b2d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2979400216 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.2979400216
Directory /workspace/22.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.3330957438
Short name T55
Test name
Test status
Simulation time 1438390000 ps
CPU time 4.85 seconds
Started Jul 01 04:18:53 PM PDT 24
Finished Jul 01 04:19:04 PM PDT 24
Peak memory 164984 kb
Host smart-4da000ac-1e34-440f-8486-4ec0ca93c2e0
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3330957438 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.3330957438
Directory /workspace/23.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.2017111422
Short name T35
Test name
Test status
Simulation time 1515730000 ps
CPU time 4.9 seconds
Started Jul 01 04:18:46 PM PDT 24
Finished Jul 01 04:18:58 PM PDT 24
Peak memory 164940 kb
Host smart-1f1b5f2e-351f-4c7f-8d60-c2b88e4b5e32
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2017111422 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.2017111422
Directory /workspace/24.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.3653700031
Short name T9
Test name
Test status
Simulation time 1284910000 ps
CPU time 3.81 seconds
Started Jul 01 04:16:57 PM PDT 24
Finished Jul 01 04:17:05 PM PDT 24
Peak memory 164952 kb
Host smart-447891e9-364b-403e-8d42-df6586b8d302
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3653700031 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.3653700031
Directory /workspace/25.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.225286513
Short name T3
Test name
Test status
Simulation time 1369690000 ps
CPU time 3.9 seconds
Started Jul 01 04:21:29 PM PDT 24
Finished Jul 01 04:21:39 PM PDT 24
Peak memory 164508 kb
Host smart-69f04405-ccb7-4e50-908b-a977ebb697f7
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=225286513 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.225286513
Directory /workspace/26.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.3473008881
Short name T47
Test name
Test status
Simulation time 1601990000 ps
CPU time 3.5 seconds
Started Jul 01 04:20:50 PM PDT 24
Finished Jul 01 04:21:00 PM PDT 24
Peak memory 165012 kb
Host smart-0b3b1d73-2f33-4d9f-8eda-08bfd44079d8
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3473008881 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.3473008881
Directory /workspace/27.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.32367471
Short name T54
Test name
Test status
Simulation time 1595490000 ps
CPU time 4.35 seconds
Started Jul 01 04:19:26 PM PDT 24
Finished Jul 01 04:19:37 PM PDT 24
Peak memory 164924 kb
Host smart-7d9eda25-3cae-4dac-871e-b3aeb416ac2d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=32367471 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.32367471
Directory /workspace/28.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.3362608232
Short name T36
Test name
Test status
Simulation time 1439730000 ps
CPU time 4.35 seconds
Started Jul 01 04:19:34 PM PDT 24
Finished Jul 01 04:19:44 PM PDT 24
Peak memory 164952 kb
Host smart-3b174501-208a-40c6-a2ef-cf002a79de68
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3362608232 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.3362608232
Directory /workspace/29.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.1910021447
Short name T50
Test name
Test status
Simulation time 1534270000 ps
CPU time 3.83 seconds
Started Jul 01 04:16:50 PM PDT 24
Finished Jul 01 04:17:00 PM PDT 24
Peak memory 165032 kb
Host smart-58e55250-8432-4923-9ded-668a227a0270
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1910021447 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.1910021447
Directory /workspace/3.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.2503454354
Short name T13
Test name
Test status
Simulation time 1275050000 ps
CPU time 3.74 seconds
Started Jul 01 04:19:27 PM PDT 24
Finished Jul 01 04:19:35 PM PDT 24
Peak memory 164944 kb
Host smart-dd58ad62-2742-4587-b003-fda4912d745a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2503454354 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.2503454354
Directory /workspace/30.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.3931885587
Short name T59
Test name
Test status
Simulation time 1558350000 ps
CPU time 4.66 seconds
Started Jul 01 04:18:23 PM PDT 24
Finished Jul 01 04:18:34 PM PDT 24
Peak memory 164996 kb
Host smart-63c5153d-8605-40ee-9c04-63807c681923
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3931885587 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.3931885587
Directory /workspace/31.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.2276279347
Short name T51
Test name
Test status
Simulation time 1476990000 ps
CPU time 4.55 seconds
Started Jul 01 04:20:51 PM PDT 24
Finished Jul 01 04:21:02 PM PDT 24
Peak memory 164540 kb
Host smart-43c53013-5bd8-48c7-9f78-b6eb8ced64f7
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2276279347 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.2276279347
Directory /workspace/32.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.3007723769
Short name T61
Test name
Test status
Simulation time 1340030000 ps
CPU time 4.03 seconds
Started Jul 01 04:20:52 PM PDT 24
Finished Jul 01 04:21:02 PM PDT 24
Peak memory 164572 kb
Host smart-58a78db8-cfb1-4ead-a1d4-2578f3fd0127
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3007723769 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.3007723769
Directory /workspace/33.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.1385839349
Short name T42
Test name
Test status
Simulation time 1486830000 ps
CPU time 3.64 seconds
Started Jul 01 04:20:37 PM PDT 24
Finished Jul 01 04:20:46 PM PDT 24
Peak memory 164332 kb
Host smart-656b6974-c287-4322-9b1d-ee188cc1887e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1385839349 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.1385839349
Directory /workspace/34.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.3839260412
Short name T1
Test name
Test status
Simulation time 1434210000 ps
CPU time 4.4 seconds
Started Jul 01 04:21:06 PM PDT 24
Finished Jul 01 04:21:16 PM PDT 24
Peak memory 163780 kb
Host smart-f678182d-e778-4a25-b293-f2897f79d439
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3839260412 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.3839260412
Directory /workspace/35.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.3053157868
Short name T48
Test name
Test status
Simulation time 1450370000 ps
CPU time 3.52 seconds
Started Jul 01 04:20:38 PM PDT 24
Finished Jul 01 04:20:46 PM PDT 24
Peak memory 164260 kb
Host smart-1c55bb34-3af3-4ec4-8d62-77f1ea3d47d6
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3053157868 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.3053157868
Directory /workspace/36.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.1437776078
Short name T8
Test name
Test status
Simulation time 1391410000 ps
CPU time 4.06 seconds
Started Jul 01 04:20:52 PM PDT 24
Finished Jul 01 04:21:03 PM PDT 24
Peak memory 164572 kb
Host smart-f4d77678-ae54-460a-8946-152e892df60a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1437776078 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.1437776078
Directory /workspace/37.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.4237046270
Short name T49
Test name
Test status
Simulation time 1469970000 ps
CPU time 4.06 seconds
Started Jul 01 04:17:46 PM PDT 24
Finished Jul 01 04:17:56 PM PDT 24
Peak memory 164964 kb
Host smart-c1216646-2879-4220-952b-367786293048
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4237046270 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.4237046270
Directory /workspace/38.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.486654639
Short name T67
Test name
Test status
Simulation time 1594210000 ps
CPU time 4.24 seconds
Started Jul 01 04:21:28 PM PDT 24
Finished Jul 01 04:21:39 PM PDT 24
Peak memory 165016 kb
Host smart-1a3eec17-0423-4840-9d6a-be2f3dfe28aa
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=486654639 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.486654639
Directory /workspace/39.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.651229733
Short name T60
Test name
Test status
Simulation time 1504790000 ps
CPU time 4.65 seconds
Started Jul 01 04:18:46 PM PDT 24
Finished Jul 01 04:18:57 PM PDT 24
Peak memory 164864 kb
Host smart-e9807473-6bcb-4e19-87d7-985b54b1b2bf
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=651229733 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.651229733
Directory /workspace/4.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.1986034936
Short name T10
Test name
Test status
Simulation time 1481850000 ps
CPU time 4.77 seconds
Started Jul 01 04:20:44 PM PDT 24
Finished Jul 01 04:20:56 PM PDT 24
Peak memory 164980 kb
Host smart-edd8819c-ff1b-46ef-8ceb-bf6dc3c4cdee
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1986034936 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.1986034936
Directory /workspace/40.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.2759560265
Short name T63
Test name
Test status
Simulation time 1491050000 ps
CPU time 4.13 seconds
Started Jul 01 04:21:28 PM PDT 24
Finished Jul 01 04:21:39 PM PDT 24
Peak memory 164388 kb
Host smart-17202bb4-a413-46b8-b511-abd97d32b0d5
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2759560265 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.2759560265
Directory /workspace/41.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.1030314101
Short name T58
Test name
Test status
Simulation time 1508210000 ps
CPU time 4.27 seconds
Started Jul 01 04:18:37 PM PDT 24
Finished Jul 01 04:18:47 PM PDT 24
Peak memory 164932 kb
Host smart-14bf119a-16a6-4394-bf27-f9bf30693e11
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1030314101 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.1030314101
Directory /workspace/42.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.2465623268
Short name T43
Test name
Test status
Simulation time 1318030000 ps
CPU time 3.99 seconds
Started Jul 01 04:18:37 PM PDT 24
Finished Jul 01 04:18:47 PM PDT 24
Peak memory 164964 kb
Host smart-8e11a18f-103e-47ef-ac10-ce211f740bc5
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2465623268 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.2465623268
Directory /workspace/43.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.3029599892
Short name T69
Test name
Test status
Simulation time 1293370000 ps
CPU time 4.2 seconds
Started Jul 01 04:18:37 PM PDT 24
Finished Jul 01 04:18:47 PM PDT 24
Peak memory 164964 kb
Host smart-d3eefb02-b1df-44cd-94f9-2a2afdb3b665
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3029599892 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.3029599892
Directory /workspace/44.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.2400829856
Short name T66
Test name
Test status
Simulation time 1381590000 ps
CPU time 3.57 seconds
Started Jul 01 04:17:43 PM PDT 24
Finished Jul 01 04:17:52 PM PDT 24
Peak memory 164952 kb
Host smart-84269c65-c9fb-4501-9d08-683dcbdf10ba
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2400829856 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.2400829856
Directory /workspace/45.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.2294695901
Short name T62
Test name
Test status
Simulation time 1369070000 ps
CPU time 3.89 seconds
Started Jul 01 04:18:24 PM PDT 24
Finished Jul 01 04:18:32 PM PDT 24
Peak memory 164952 kb
Host smart-cec1641a-01c7-4f5a-b55c-1166d7cd63fa
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2294695901 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.2294695901
Directory /workspace/46.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.509737754
Short name T44
Test name
Test status
Simulation time 1462330000 ps
CPU time 4.24 seconds
Started Jul 01 04:18:22 PM PDT 24
Finished Jul 01 04:18:32 PM PDT 24
Peak memory 164960 kb
Host smart-0c5b1160-4dc9-454e-8e42-47f12edb7eda
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=509737754 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.509737754
Directory /workspace/47.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.4001495629
Short name T2
Test name
Test status
Simulation time 1463550000 ps
CPU time 4.28 seconds
Started Jul 01 04:18:38 PM PDT 24
Finished Jul 01 04:18:48 PM PDT 24
Peak memory 164964 kb
Host smart-47473759-f62f-4df0-bb95-366a0e163822
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4001495629 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.4001495629
Directory /workspace/48.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.3375689843
Short name T33
Test name
Test status
Simulation time 1232210000 ps
CPU time 3.46 seconds
Started Jul 01 04:20:51 PM PDT 24
Finished Jul 01 04:21:00 PM PDT 24
Peak memory 164524 kb
Host smart-2f71e1a6-601c-46fe-a3bd-652397bf36f4
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3375689843 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.3375689843
Directory /workspace/49.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.154564279
Short name T52
Test name
Test status
Simulation time 1298490000 ps
CPU time 3.63 seconds
Started Jul 01 04:18:28 PM PDT 24
Finished Jul 01 04:18:37 PM PDT 24
Peak memory 164916 kb
Host smart-fbfb221b-df49-49a3-9dc7-6d7a4cacc165
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=154564279 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.154564279
Directory /workspace/5.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.1704666380
Short name T32
Test name
Test status
Simulation time 1530230000 ps
CPU time 4.75 seconds
Started Jul 01 04:19:10 PM PDT 24
Finished Jul 01 04:19:21 PM PDT 24
Peak memory 164976 kb
Host smart-77eae075-54ee-4857-a2b2-20d24b9ea220
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1704666380 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.1704666380
Directory /workspace/6.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.1645728995
Short name T57
Test name
Test status
Simulation time 1515110000 ps
CPU time 3.32 seconds
Started Jul 01 04:17:40 PM PDT 24
Finished Jul 01 04:17:48 PM PDT 24
Peak memory 164952 kb
Host smart-365ae921-820d-4d0a-828b-592c1a068bba
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1645728995 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.1645728995
Directory /workspace/7.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.1406718240
Short name T68
Test name
Test status
Simulation time 1390570000 ps
CPU time 4.14 seconds
Started Jul 01 04:16:54 PM PDT 24
Finished Jul 01 04:17:04 PM PDT 24
Peak memory 164956 kb
Host smart-1384c088-0998-4e50-a365-907b63f59e63
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1406718240 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.1406718240
Directory /workspace/8.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.2871001139
Short name T40
Test name
Test status
Simulation time 1479650000 ps
CPU time 4.1 seconds
Started Jul 01 04:20:51 PM PDT 24
Finished Jul 01 04:21:02 PM PDT 24
Peak memory 164524 kb
Host smart-e4126a32-c004-4084-8df5-fcda6312d3b4
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2871001139 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.2871001139
Directory /workspace/9.prim_lfsr_gal_smoke/latest
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