| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 98.31 | 100.00 | 96.55 | 100.00 | 100.00 | 95.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 87.31 | 87.31 | 100.00 | 100.00 | 96.55 | 96.55 | 100.00 | 100.00 | 100.00 | 100.00 | 40.00 | 40.00 | /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.1887107479 | ||
| 96.81 | 9.50 | 100.00 | 0.00 | 96.55 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 87.50 | 47.50 | /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.2429691523 | ||
| 98.31 | 1.50 | 100.00 | 0.00 | 96.55 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 95.00 | 7.50 | /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.2072874347 | ||
| Name |
|---|
| /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.3243297585 |
| /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.205991672 |
| /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.3746301366 |
| /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.1314582750 |
| /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.662942251 |
| /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.2808879659 |
| /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.119856272 |
| /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.1894700225 |
| /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.4138726444 |
| /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.4157961927 |
| /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.1907533002 |
| /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.24367644 |
| /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.528083113 |
| /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.3871485501 |
| /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.2261972962 |
| /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.2501398552 |
| /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.91127287 |
| /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.2361267379 |
| /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.850846537 |
| /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.1125143801 |
| /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.3319707528 |
| /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.3255589353 |
| /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.1839525523 |
| /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3898137124 |
| /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.616421033 |
| /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.2773605834 |
| /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.3777542100 |
| /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.4116665476 |
| /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.3462785511 |
| /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.3982935332 |
| /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.590679009 |
| /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.2542024141 |
| /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.2310745016 |
| /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.1591171514 |
| /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.4080152062 |
| /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.1521962756 |
| /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.3866436125 |
| /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.904132177 |
| /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.3614717703 |
| /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.2667288148 |
| /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.3226118654 |
| /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.2043502129 |
| /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.2969475018 |
| /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.2367875239 |
| /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.3000848292 |
| /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.837742250 |
| /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.3861349561 |
| /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.2999969845 |
| /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.2091073041 |
| /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.3250027661 |
| /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.3606463280 |
| /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.2257887386 |
| /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.4059949487 |
| /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.957988687 |
| /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.3160951705 |
| /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.2841293810 |
| /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.3332985028 |
| /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.2998105001 |
| /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.1397833644 |
| /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.1704435683 |
| /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.3578010829 |
| /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.1914043896 |
| /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.445490214 |
| /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.2801869767 |
| /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.662865078 |
| /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.3749609142 |
| /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.1554972205 |
| /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.1459894369 |
| /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.3045890764 |
| /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.2044626242 |
| /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.2447711906 |
| /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.2412906009 |
| /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.4172902753 |
| /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.3059862114 |
| /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.4071253299 |
| /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.2696587610 |
| /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.1261052055 |
| /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.1231422675 |
| /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.186765538 |
| /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.3965957566 |
| /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.4267916381 |
| /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.492145059 |
| /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.2168572238 |
| /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.1743660866 |
| /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.3547022999 |
| /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.3486930750 |
| /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.1769331702 |
| /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.3844043872 |
| /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.3989955174 |
| /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.3287287604 |
| /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.610892357 |
| /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.654541853 |
| /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.332286803 |
| /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.22792625 |
| /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.178910697 |
| /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.2100524071 |
| /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.99946688 |
| /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.2078728685 |
| /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.3931974845 |
| /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.1166069468 |
| /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.217529662 |
| /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.1734069937 |
| /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.406199463 |
| /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.1639852594 |
| /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.2131639051 |
| /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.3610133982 |
| /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.1122354272 |
| /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.4103771333 |
| /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.3675488410 |
| /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.1562429066 |
| /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.4161559729 |
| /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.1057640343 |
| /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.1421804082 |
| /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.1030581754 |
| /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.1533618960 |
| /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.2159209554 |
| /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.1820560353 |
| /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.4019213645 |
| /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.334351739 |
| /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.1313460086 |
| /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.3934781913 |
| /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.2146312739 |
| /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.718589281 |
| /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.41416734 |
| /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.2272534973 |
| /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.1537553778 |
| /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.3850441375 |
| /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.3881804350 |
| /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.3707714869 |
| /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1467413038 |
| /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.738784301 |
| /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.729975110 |
| /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.496079583 |
| /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.658030574 |
| /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.2145549523 |
| /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.2061573652 |
| /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.3088873709 |
| /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.3199680788 |
| /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.1051577089 |
| /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.2218978881 |
| /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.302683517 |
| /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.346566785 |
| /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.4158133327 |
| /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.3768330122 |
| /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.3423739854 |
| /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.2045813333 |
| /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1397459232 |
| /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2612898575 |
| /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.808644911 |
| /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.658464301 |
| /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.2810356129 |
| /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.951416640 |
| /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.2219740213 |
| /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.3974773573 |
| /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.1691777511 |
| /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.536219142 |
| /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.2852206278 |
| /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.2895750884 |
| /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.836995625 |
| /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.1514538805 |
| /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.2423371638 |
| /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.2858720732 |
| /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.3236675444 |
| /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.830089286 |
| /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.4086945584 |
| /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.1646230037 |
| /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.695902964 |
| /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.2141810667 |
| /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.2285364248 |
| /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.3531717769 |
| /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.996196674 |
| /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.1975728386 |
| /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.967875225 |
| /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.1873031263 |
| /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.3156743604 |
| /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.1932610347 |
| /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.933511498 |
| /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.3313075866 |
| /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.119895951 |
| /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.3808958931 |
| /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.69582171 |
| /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.72831800 |
| /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.3534344023 |
| /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.2892410057 |
| /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.2930724429 |
| /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.907957001 |
| /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.2166024734 |
| /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.2351499751 |
| /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.3774366547 |
| /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.932067863 |
| /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.1897368031 |
| /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.2135925110 |
| /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.2455627314 |
| /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.170206008 |
| /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.2526259429 |
| /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.797015326 |
| /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.4203250912 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.1975728386 | Jul 02 09:04:24 AM PDT 24 | Jul 02 09:04:35 AM PDT 24 | 1329630000 ps | ||
| T2 | /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.2810356129 | Jul 02 09:04:24 AM PDT 24 | Jul 02 09:04:36 AM PDT 24 | 1396090000 ps | ||
| T3 | /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.3974773573 | Jul 02 09:04:26 AM PDT 24 | Jul 02 09:04:39 AM PDT 24 | 1461390000 ps | ||
| T7 | /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.4086945584 | Jul 02 09:04:25 AM PDT 24 | Jul 02 09:04:34 AM PDT 24 | 1371630000 ps | ||
| T8 | /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.2455627314 | Jul 02 09:04:24 AM PDT 24 | Jul 02 09:04:35 AM PDT 24 | 1338630000 ps | ||
| T9 | /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.2166024734 | Jul 02 09:04:26 AM PDT 24 | Jul 02 09:04:38 AM PDT 24 | 1577750000 ps | ||
| T10 | /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.170206008 | Jul 02 09:04:25 AM PDT 24 | Jul 02 09:04:38 AM PDT 24 | 1585930000 ps | ||
| T11 | /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.1887107479 | Jul 02 09:04:22 AM PDT 24 | Jul 02 09:04:31 AM PDT 24 | 1394350000 ps | ||
| T12 | /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.2892410057 | Jul 02 09:04:29 AM PDT 24 | Jul 02 09:04:39 AM PDT 24 | 1589150000 ps | ||
| T13 | /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.536219142 | Jul 02 09:04:22 AM PDT 24 | Jul 02 09:04:31 AM PDT 24 | 1218570000 ps | ||
| T31 | /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.2852206278 | Jul 02 09:04:24 AM PDT 24 | Jul 02 09:04:37 AM PDT 24 | 1544430000 ps | ||
| T32 | /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.1897368031 | Jul 02 09:04:26 AM PDT 24 | Jul 02 09:04:34 AM PDT 24 | 1141830000 ps | ||
| T33 | /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.830089286 | Jul 02 09:04:23 AM PDT 24 | Jul 02 09:04:33 AM PDT 24 | 1193770000 ps | ||
| T34 | /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.2895750884 | Jul 02 09:04:23 AM PDT 24 | Jul 02 09:04:33 AM PDT 24 | 1341990000 ps | ||
| T35 | /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.1873031263 | Jul 02 09:04:22 AM PDT 24 | Jul 02 09:04:34 AM PDT 24 | 1638770000 ps | ||
| T36 | /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.2135925110 | Jul 02 09:04:23 AM PDT 24 | Jul 02 09:04:33 AM PDT 24 | 1522230000 ps | ||
| T37 | /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.2351499751 | Jul 02 09:04:25 AM PDT 24 | Jul 02 09:04:36 AM PDT 24 | 1491710000 ps | ||
| T38 | /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.1691777511 | Jul 02 09:04:23 AM PDT 24 | Jul 02 09:04:36 AM PDT 24 | 1580730000 ps | ||
| T39 | /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.2526259429 | Jul 02 09:04:34 AM PDT 24 | Jul 02 09:04:46 AM PDT 24 | 1524390000 ps | ||
| T40 | /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.1646230037 | Jul 02 09:04:25 AM PDT 24 | Jul 02 09:04:36 AM PDT 24 | 1396690000 ps | ||
| T41 | /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.3808958931 | Jul 02 09:04:26 AM PDT 24 | Jul 02 09:04:35 AM PDT 24 | 1413050000 ps | ||
| T42 | /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.72831800 | Jul 02 09:04:25 AM PDT 24 | Jul 02 09:04:37 AM PDT 24 | 1619790000 ps | ||
| T43 | /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.3534344023 | Jul 02 09:04:23 AM PDT 24 | Jul 02 09:04:37 AM PDT 24 | 1507890000 ps | ||
| T44 | /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.1514538805 | Jul 02 09:04:24 AM PDT 24 | Jul 02 09:04:34 AM PDT 24 | 1208930000 ps | ||
| T45 | /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.658464301 | Jul 02 09:04:23 AM PDT 24 | Jul 02 09:04:37 AM PDT 24 | 1624910000 ps | ||
| T46 | /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.3774366547 | Jul 02 09:04:24 AM PDT 24 | Jul 02 09:04:35 AM PDT 24 | 1405410000 ps | ||
| T47 | /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.907957001 | Jul 02 09:04:46 AM PDT 24 | Jul 02 09:04:53 AM PDT 24 | 1042670000 ps | ||
| T48 | /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.2219740213 | Jul 02 09:04:21 AM PDT 24 | Jul 02 09:04:32 AM PDT 24 | 1377390000 ps | ||
| T49 | /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.3236675444 | Jul 02 09:04:21 AM PDT 24 | Jul 02 09:04:33 AM PDT 24 | 1452370000 ps | ||
| T50 | /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.2858720732 | Jul 02 09:04:21 AM PDT 24 | Jul 02 09:04:29 AM PDT 24 | 1458730000 ps | ||
| T51 | /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.3156743604 | Jul 02 09:04:22 AM PDT 24 | Jul 02 09:04:33 AM PDT 24 | 1478390000 ps | ||
| T52 | /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.3531717769 | Jul 02 09:04:25 AM PDT 24 | Jul 02 09:04:37 AM PDT 24 | 1479870000 ps | ||
| T53 | /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.967875225 | Jul 02 09:04:23 AM PDT 24 | Jul 02 09:04:36 AM PDT 24 | 1544150000 ps | ||
| T54 | /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.996196674 | Jul 02 09:04:24 AM PDT 24 | Jul 02 09:04:34 AM PDT 24 | 1232730000 ps | ||
| T55 | /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.836995625 | Jul 02 09:04:34 AM PDT 24 | Jul 02 09:04:44 AM PDT 24 | 1505930000 ps | ||
| T56 | /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.2285364248 | Jul 02 09:04:33 AM PDT 24 | Jul 02 09:04:45 AM PDT 24 | 1496610000 ps | ||
| T57 | /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.2423371638 | Jul 02 09:04:23 AM PDT 24 | Jul 02 09:04:35 AM PDT 24 | 1487910000 ps | ||
| T58 | /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.69582171 | Jul 02 09:04:27 AM PDT 24 | Jul 02 09:04:39 AM PDT 24 | 1577570000 ps | ||
| T59 | /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.119895951 | Jul 02 09:04:26 AM PDT 24 | Jul 02 09:04:35 AM PDT 24 | 1350350000 ps | ||
| T60 | /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.808644911 | Jul 02 09:04:18 AM PDT 24 | Jul 02 09:04:29 AM PDT 24 | 1477110000 ps | ||
| T61 | /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.932067863 | Jul 02 09:04:26 AM PDT 24 | Jul 02 09:04:38 AM PDT 24 | 1371930000 ps | ||
| T62 | /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.951416640 | Jul 02 09:04:27 AM PDT 24 | Jul 02 09:04:37 AM PDT 24 | 1325070000 ps | ||
| T63 | /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.1932610347 | Jul 02 09:04:25 AM PDT 24 | Jul 02 09:04:37 AM PDT 24 | 1538010000 ps | ||
| T64 | /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.933511498 | Jul 02 09:04:23 AM PDT 24 | Jul 02 09:04:32 AM PDT 24 | 1502230000 ps | ||
| T65 | /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.2930724429 | Jul 02 09:04:26 AM PDT 24 | Jul 02 09:04:40 AM PDT 24 | 1609870000 ps | ||
| T66 | /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.2141810667 | Jul 02 09:04:21 AM PDT 24 | Jul 02 09:04:31 AM PDT 24 | 1329110000 ps | ||
| T67 | /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.4203250912 | Jul 02 09:04:23 AM PDT 24 | Jul 02 09:04:35 AM PDT 24 | 1557450000 ps | ||
| T68 | /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.797015326 | Jul 02 09:04:24 AM PDT 24 | Jul 02 09:04:35 AM PDT 24 | 1517130000 ps | ||
| T69 | /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.3313075866 | Jul 02 09:04:34 AM PDT 24 | Jul 02 09:04:45 AM PDT 24 | 1482210000 ps | ||
| T70 | /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.695902964 | Jul 02 09:04:20 AM PDT 24 | Jul 02 09:04:27 AM PDT 24 | 1584390000 ps | ||
| T4 | /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.904132177 | Jul 02 09:04:24 AM PDT 24 | Jul 02 09:38:44 AM PDT 24 | 336854210000 ps | ||
| T5 | /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.2361267379 | Jul 02 09:04:18 AM PDT 24 | Jul 02 09:37:07 AM PDT 24 | 336744890000 ps | ||
| T6 | /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.2999969845 | Jul 02 09:04:17 AM PDT 24 | Jul 02 09:39:07 AM PDT 24 | 336568590000 ps | ||
| T14 | /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.2043502129 | Jul 02 09:04:21 AM PDT 24 | Jul 02 09:31:47 AM PDT 24 | 336999230000 ps | ||
| T15 | /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.2261972962 | Jul 02 09:04:19 AM PDT 24 | Jul 02 09:37:58 AM PDT 24 | 337100810000 ps | ||
| T16 | /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.2429691523 | Jul 02 09:04:17 AM PDT 24 | Jul 02 09:36:05 AM PDT 24 | 336565830000 ps | ||
| T17 | /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.1521962756 | Jul 02 09:04:20 AM PDT 24 | Jul 02 09:36:50 AM PDT 24 | 336679010000 ps | ||
| T18 | /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.837742250 | Jul 02 09:04:17 AM PDT 24 | Jul 02 09:45:06 AM PDT 24 | 337028590000 ps | ||
| T19 | /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.3000848292 | Jul 02 09:04:24 AM PDT 24 | Jul 02 09:34:31 AM PDT 24 | 336659430000 ps | ||
| T20 | /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.3871485501 | Jul 02 09:04:19 AM PDT 24 | Jul 02 09:33:30 AM PDT 24 | 336511890000 ps | ||
| T71 | /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.4157961927 | Jul 02 09:04:19 AM PDT 24 | Jul 02 09:41:30 AM PDT 24 | 336682710000 ps | ||
| T72 | /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.3866436125 | Jul 02 09:04:20 AM PDT 24 | Jul 02 09:38:37 AM PDT 24 | 336438730000 ps | ||
| T73 | /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3898137124 | Jul 02 09:04:22 AM PDT 24 | Jul 02 09:38:40 AM PDT 24 | 336783670000 ps | ||
| T74 | /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.2542024141 | Jul 02 09:04:28 AM PDT 24 | Jul 02 09:38:47 AM PDT 24 | 336659970000 ps | ||
| T75 | /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.91127287 | Jul 02 09:04:20 AM PDT 24 | Jul 02 09:34:10 AM PDT 24 | 337007130000 ps | ||
| T76 | /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.3982935332 | Jul 02 09:04:19 AM PDT 24 | Jul 02 09:40:51 AM PDT 24 | 336801050000 ps | ||
| T77 | /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.616421033 | Jul 02 09:04:20 AM PDT 24 | Jul 02 09:35:53 AM PDT 24 | 337203750000 ps | ||
| T78 | /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.3861349561 | Jul 02 09:04:22 AM PDT 24 | Jul 02 09:35:05 AM PDT 24 | 336874290000 ps | ||
| T79 | /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.1907533002 | Jul 02 09:04:19 AM PDT 24 | Jul 02 09:40:52 AM PDT 24 | 337081710000 ps | ||
| T80 | /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.24367644 | Jul 02 09:04:20 AM PDT 24 | Jul 02 09:37:16 AM PDT 24 | 336387450000 ps | ||
| T81 | /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.3226118654 | Jul 02 09:04:21 AM PDT 24 | Jul 02 09:38:34 AM PDT 24 | 336881630000 ps | ||
| T82 | /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.662942251 | Jul 02 09:04:23 AM PDT 24 | Jul 02 09:38:57 AM PDT 24 | 336416970000 ps | ||
| T83 | /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.4138726444 | Jul 02 09:04:20 AM PDT 24 | Jul 02 09:37:56 AM PDT 24 | 336921870000 ps | ||
| T84 | /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.3319707528 | Jul 02 09:04:19 AM PDT 24 | Jul 02 09:40:09 AM PDT 24 | 336848150000 ps | ||
| T85 | /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.2969475018 | Jul 02 09:04:21 AM PDT 24 | Jul 02 09:37:40 AM PDT 24 | 336992230000 ps | ||
| T86 | /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.3243297585 | Jul 02 09:04:22 AM PDT 24 | Jul 02 09:44:20 AM PDT 24 | 336700550000 ps | ||
| T87 | /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.1591171514 | Jul 02 09:04:23 AM PDT 24 | Jul 02 09:38:39 AM PDT 24 | 336703630000 ps | ||
| T88 | /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.3255589353 | Jul 02 09:04:22 AM PDT 24 | Jul 02 09:44:26 AM PDT 24 | 336311250000 ps | ||
| T89 | /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.850846537 | Jul 02 09:04:22 AM PDT 24 | Jul 02 09:36:01 AM PDT 24 | 336904350000 ps | ||
| T90 | /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.4116665476 | Jul 02 09:04:20 AM PDT 24 | Jul 02 09:35:44 AM PDT 24 | 336521670000 ps | ||
| T91 | /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.1314582750 | Jul 02 09:04:23 AM PDT 24 | Jul 02 09:38:36 AM PDT 24 | 336464210000 ps | ||
| T92 | /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.2808879659 | Jul 02 09:04:20 AM PDT 24 | Jul 02 09:41:31 AM PDT 24 | 336990630000 ps | ||
| T93 | /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.2773605834 | Jul 02 09:04:16 AM PDT 24 | Jul 02 09:37:16 AM PDT 24 | 337081990000 ps | ||
| T94 | /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.119856272 | Jul 02 09:04:28 AM PDT 24 | Jul 02 09:36:15 AM PDT 24 | 336705310000 ps | ||
| T95 | /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.2667288148 | Jul 02 09:04:22 AM PDT 24 | Jul 02 09:35:53 AM PDT 24 | 336330670000 ps | ||
| T96 | /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.2310745016 | Jul 02 09:04:21 AM PDT 24 | Jul 02 09:44:20 AM PDT 24 | 336477730000 ps | ||
| T97 | /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.2501398552 | Jul 02 09:04:24 AM PDT 24 | Jul 02 09:38:41 AM PDT 24 | 337019170000 ps | ||
| T98 | /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.2367875239 | Jul 02 09:04:37 AM PDT 24 | Jul 02 09:46:00 AM PDT 24 | 336980430000 ps | ||
| T99 | /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.528083113 | Jul 02 09:04:29 AM PDT 24 | Jul 02 09:39:03 AM PDT 24 | 336507090000 ps | ||
| T100 | /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.1894700225 | Jul 02 09:04:17 AM PDT 24 | Jul 02 09:45:00 AM PDT 24 | 336526450000 ps | ||
| T101 | /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.3614717703 | Jul 02 09:04:20 AM PDT 24 | Jul 02 09:35:00 AM PDT 24 | 336870750000 ps | ||
| T102 | /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.3462785511 | Jul 02 09:04:25 AM PDT 24 | Jul 02 09:32:23 AM PDT 24 | 336319470000 ps | ||
| T103 | /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.1839525523 | Jul 02 09:04:22 AM PDT 24 | Jul 02 09:43:58 AM PDT 24 | 336602710000 ps | ||
| T104 | /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.4080152062 | Jul 02 09:04:23 AM PDT 24 | Jul 02 09:38:44 AM PDT 24 | 336830350000 ps | ||
| T105 | /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.3746301366 | Jul 02 09:04:21 AM PDT 24 | Jul 02 09:36:00 AM PDT 24 | 336566550000 ps | ||
| T106 | /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.590679009 | Jul 02 09:04:18 AM PDT 24 | Jul 02 09:37:52 AM PDT 24 | 336634110000 ps | ||
| T107 | /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.1125143801 | Jul 02 09:04:18 AM PDT 24 | Jul 02 09:36:34 AM PDT 24 | 337147410000 ps | ||
| T108 | /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.205991672 | Jul 02 09:04:22 AM PDT 24 | Jul 02 09:38:52 AM PDT 24 | 336310230000 ps | ||
| T109 | /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.3777542100 | Jul 02 09:04:19 AM PDT 24 | Jul 02 09:40:07 AM PDT 24 | 337027810000 ps | ||
| T110 | /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.2091073041 | Jul 02 09:04:25 AM PDT 24 | Jul 02 09:37:27 AM PDT 24 | 336865370000 ps | ||
| T111 | /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.3768330122 | Jul 02 09:13:14 AM PDT 24 | Jul 02 09:13:28 AM PDT 24 | 1541730000 ps | ||
| T112 | /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.4019213645 | Jul 02 09:13:20 AM PDT 24 | Jul 02 09:13:32 AM PDT 24 | 1536170000 ps | ||
| T113 | /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.738784301 | Jul 02 09:13:22 AM PDT 24 | Jul 02 09:13:33 AM PDT 24 | 1561030000 ps | ||
| T114 | /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1467413038 | Jul 02 09:13:21 AM PDT 24 | Jul 02 09:13:31 AM PDT 24 | 1226390000 ps | ||
| T115 | /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.718589281 | Jul 02 09:13:19 AM PDT 24 | Jul 02 09:13:32 AM PDT 24 | 1553930000 ps | ||
| T116 | /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.1562429066 | Jul 02 09:13:19 AM PDT 24 | Jul 02 09:13:30 AM PDT 24 | 1446350000 ps | ||
| T117 | /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.496079583 | Jul 02 09:13:15 AM PDT 24 | Jul 02 09:13:29 AM PDT 24 | 1312970000 ps | ||
| T118 | /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.3675488410 | Jul 02 09:13:17 AM PDT 24 | Jul 02 09:13:30 AM PDT 24 | 1476970000 ps | ||
| T119 | /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2612898575 | Jul 02 09:13:10 AM PDT 24 | Jul 02 09:13:26 AM PDT 24 | 1435450000 ps | ||
| T120 | /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.1051577089 | Jul 02 09:13:22 AM PDT 24 | Jul 02 09:13:33 AM PDT 24 | 1386450000 ps | ||
| T121 | /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.1734069937 | Jul 02 09:13:12 AM PDT 24 | Jul 02 09:13:25 AM PDT 24 | 1344530000 ps | ||
| T122 | /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.1533618960 | Jul 02 09:13:18 AM PDT 24 | Jul 02 09:13:31 AM PDT 24 | 1361490000 ps | ||
| T123 | /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.729975110 | Jul 02 09:13:21 AM PDT 24 | Jul 02 09:13:32 AM PDT 24 | 1455990000 ps | ||
| T124 | /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.658030574 | Jul 02 09:13:25 AM PDT 24 | Jul 02 09:13:35 AM PDT 24 | 1441530000 ps | ||
| T125 | /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.1057640343 | Jul 02 09:13:17 AM PDT 24 | Jul 02 09:13:31 AM PDT 24 | 1461310000 ps | ||
| T126 | /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.2145549523 | Jul 02 09:13:32 AM PDT 24 | Jul 02 09:13:44 AM PDT 24 | 1522330000 ps | ||
| T127 | /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.4161559729 | Jul 02 09:13:14 AM PDT 24 | Jul 02 09:13:35 AM PDT 24 | 1580030000 ps | ||
| T128 | /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.2159209554 | Jul 02 09:13:20 AM PDT 24 | Jul 02 09:13:30 AM PDT 24 | 1350770000 ps | ||
| T129 | /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.2131639051 | Jul 02 09:13:18 AM PDT 24 | Jul 02 09:13:31 AM PDT 24 | 1351870000 ps | ||
| T130 | /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.3199680788 | Jul 02 09:13:22 AM PDT 24 | Jul 02 09:13:34 AM PDT 24 | 1592310000 ps | ||
| T131 | /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.3610133982 | Jul 02 09:13:17 AM PDT 24 | Jul 02 09:13:34 AM PDT 24 | 1562690000 ps | ||
| T132 | /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.41416734 | Jul 02 09:13:18 AM PDT 24 | Jul 02 09:13:30 AM PDT 24 | 1464930000 ps | ||
| T133 | /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.2061573652 | Jul 02 09:13:21 AM PDT 24 | Jul 02 09:13:32 AM PDT 24 | 1563390000 ps | ||
| T134 | /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.4158133327 | Jul 02 09:13:21 AM PDT 24 | Jul 02 09:13:33 AM PDT 24 | 1558170000 ps | ||
| T135 | /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.3850441375 | Jul 02 09:13:21 AM PDT 24 | Jul 02 09:13:32 AM PDT 24 | 1470870000 ps | ||
| T136 | /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.406199463 | Jul 02 09:13:14 AM PDT 24 | Jul 02 09:13:29 AM PDT 24 | 1482190000 ps | ||
| T137 | /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.217529662 | Jul 02 09:13:18 AM PDT 24 | Jul 02 09:13:33 AM PDT 24 | 1609090000 ps | ||
| T138 | /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.1421804082 | Jul 02 09:13:14 AM PDT 24 | Jul 02 09:13:29 AM PDT 24 | 1543310000 ps | ||
| T139 | /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.1820560353 | Jul 02 09:13:18 AM PDT 24 | Jul 02 09:13:31 AM PDT 24 | 1440050000 ps | ||
| T140 | /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.1166069468 | Jul 02 09:13:12 AM PDT 24 | Jul 02 09:13:26 AM PDT 24 | 1476310000 ps | ||
| T141 | /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.3934781913 | Jul 02 09:13:25 AM PDT 24 | Jul 02 09:13:35 AM PDT 24 | 1502950000 ps | ||
| T142 | /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.2218978881 | Jul 02 09:13:20 AM PDT 24 | Jul 02 09:13:34 AM PDT 24 | 1539270000 ps | ||
| T143 | /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.3931974845 | Jul 02 09:13:10 AM PDT 24 | Jul 02 09:13:26 AM PDT 24 | 1367690000 ps | ||
| T144 | /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.4103771333 | Jul 02 09:13:21 AM PDT 24 | Jul 02 09:13:32 AM PDT 24 | 1563430000 ps | ||
| T145 | /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.334351739 | Jul 02 09:13:18 AM PDT 24 | Jul 02 09:13:34 AM PDT 24 | 1400810000 ps | ||
| T146 | /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1397459232 | Jul 02 09:13:10 AM PDT 24 | Jul 02 09:13:26 AM PDT 24 | 1463410000 ps | ||
| T147 | /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.2146312739 | Jul 02 09:13:16 AM PDT 24 | Jul 02 09:13:29 AM PDT 24 | 1228630000 ps | ||
| T148 | /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.2272534973 | Jul 02 09:13:17 AM PDT 24 | Jul 02 09:13:31 AM PDT 24 | 1468370000 ps | ||
| T149 | /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.3088873709 | Jul 02 09:13:21 AM PDT 24 | Jul 02 09:13:32 AM PDT 24 | 1443790000 ps | ||
| T150 | /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.1313460086 | Jul 02 09:13:17 AM PDT 24 | Jul 02 09:13:31 AM PDT 24 | 1476630000 ps | ||
| T151 | /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.1122354272 | Jul 02 09:13:14 AM PDT 24 | Jul 02 09:13:28 AM PDT 24 | 1542850000 ps | ||
| T152 | /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.1537553778 | Jul 02 09:13:18 AM PDT 24 | Jul 02 09:13:31 AM PDT 24 | 1503810000 ps | ||
| T153 | /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.3707714869 | Jul 02 09:13:21 AM PDT 24 | Jul 02 09:13:34 AM PDT 24 | 1593290000 ps | ||
| T154 | /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.302683517 | Jul 02 09:13:22 AM PDT 24 | Jul 02 09:13:36 AM PDT 24 | 1546790000 ps | ||
| T155 | /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.3881804350 | Jul 02 09:13:22 AM PDT 24 | Jul 02 09:13:31 AM PDT 24 | 1328670000 ps | ||
| T156 | /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.2045813333 | Jul 02 09:13:11 AM PDT 24 | Jul 02 09:13:27 AM PDT 24 | 1531150000 ps | ||
| T157 | /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.1639852594 | Jul 02 09:13:16 AM PDT 24 | Jul 02 09:13:28 AM PDT 24 | 1440410000 ps | ||
| T158 | /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.346566785 | Jul 02 09:13:19 AM PDT 24 | Jul 02 09:13:32 AM PDT 24 | 1173930000 ps | ||
| T159 | /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.1030581754 | Jul 02 09:13:15 AM PDT 24 | Jul 02 09:13:27 AM PDT 24 | 1357570000 ps | ||
| T160 | /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.3423739854 | Jul 02 09:13:20 AM PDT 24 | Jul 02 09:13:32 AM PDT 24 | 1422890000 ps | ||
| T21 | /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.2841293810 | Jul 02 09:13:31 AM PDT 24 | Jul 02 09:49:16 AM PDT 24 | 336727070000 ps | ||
| T22 | /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.1554972205 | Jul 02 09:13:27 AM PDT 24 | Jul 02 09:47:00 AM PDT 24 | 336389470000 ps | ||
| T23 | /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.654541853 | Jul 02 09:13:27 AM PDT 24 | Jul 02 09:44:00 AM PDT 24 | 337110090000 ps | ||
| T24 | /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.1231422675 | Jul 02 09:13:42 AM PDT 24 | Jul 02 09:46:54 AM PDT 24 | 336642250000 ps | ||
| T25 | /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.662865078 | Jul 02 09:13:37 AM PDT 24 | Jul 02 09:47:20 AM PDT 24 | 336722130000 ps | ||
| T26 | /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.2072874347 | Jul 02 09:13:27 AM PDT 24 | Jul 02 09:46:41 AM PDT 24 | 336544330000 ps | ||
| T27 | /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.3989955174 | Jul 02 09:13:46 AM PDT 24 | Jul 02 09:43:38 AM PDT 24 | 336897290000 ps | ||
| T28 | /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.22792625 | Jul 02 09:13:35 AM PDT 24 | Jul 02 09:44:16 AM PDT 24 | 336479070000 ps | ||
| T29 | /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.610892357 | Jul 02 09:13:45 AM PDT 24 | Jul 02 09:55:53 AM PDT 24 | 336628850000 ps | ||
| T30 | /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.178910697 | Jul 02 09:13:26 AM PDT 24 | Jul 02 09:49:37 AM PDT 24 | 336911710000 ps | ||
| T161 | /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.3486930750 | Jul 02 09:13:35 AM PDT 24 | Jul 02 09:46:51 AM PDT 24 | 336865390000 ps | ||
| T162 | /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.2100524071 | Jul 02 09:13:30 AM PDT 24 | Jul 02 09:43:53 AM PDT 24 | 336848030000 ps | ||
| T163 | /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.4059949487 | Jul 02 09:13:24 AM PDT 24 | Jul 02 09:40:32 AM PDT 24 | 336488950000 ps | ||
| T164 | /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.4071253299 | Jul 02 09:13:48 AM PDT 24 | Jul 02 09:48:03 AM PDT 24 | 336698010000 ps | ||
| T165 | /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.4267916381 | Jul 02 09:13:41 AM PDT 24 | Jul 02 09:48:54 AM PDT 24 | 336737970000 ps | ||
| T166 | /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.3749609142 | Jul 02 09:13:24 AM PDT 24 | Jul 02 09:43:14 AM PDT 24 | 336985830000 ps | ||
| T167 | /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.3287287604 | Jul 02 09:13:43 AM PDT 24 | Jul 02 09:49:10 AM PDT 24 | 337024050000 ps | ||
| T168 | /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.445490214 | Jul 02 09:13:24 AM PDT 24 | Jul 02 09:41:53 AM PDT 24 | 336766590000 ps | ||
| T169 | /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.3160951705 | Jul 02 09:13:31 AM PDT 24 | Jul 02 09:45:24 AM PDT 24 | 336394070000 ps | ||
| T170 | /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.3606463280 | Jul 02 09:13:25 AM PDT 24 | Jul 02 09:44:42 AM PDT 24 | 336658290000 ps | ||
| T171 | /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.2168572238 | Jul 02 09:13:50 AM PDT 24 | Jul 02 09:55:53 AM PDT 24 | 336787510000 ps | ||
| T172 | /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.2044626242 | Jul 02 09:13:44 AM PDT 24 | Jul 02 09:43:35 AM PDT 24 | 336841870000 ps | ||
| T173 | /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.3045890764 | Jul 02 09:13:40 AM PDT 24 | Jul 02 09:47:53 AM PDT 24 | 336413450000 ps | ||
| T174 | /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.3250027661 | Jul 02 09:13:23 AM PDT 24 | Jul 02 09:43:57 AM PDT 24 | 336921950000 ps | ||
| T175 | /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.1743660866 | Jul 02 09:13:28 AM PDT 24 | Jul 02 09:46:30 AM PDT 24 | 336339110000 ps | ||
| T176 | /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.1459894369 | Jul 02 09:13:42 AM PDT 24 | Jul 02 09:46:01 AM PDT 24 | 337039230000 ps | ||
| T177 | /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.1397833644 | Jul 02 09:13:41 AM PDT 24 | Jul 02 09:55:51 AM PDT 24 | 336814450000 ps | ||
| T178 | /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.2447711906 | Jul 02 09:13:35 AM PDT 24 | Jul 02 09:47:32 AM PDT 24 | 337018770000 ps | ||
| T179 | /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.2257887386 | Jul 02 09:13:25 AM PDT 24 | Jul 02 09:41:40 AM PDT 24 | 336502690000 ps | ||
| T180 | /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.3844043872 | Jul 02 09:13:37 AM PDT 24 | Jul 02 09:44:04 AM PDT 24 | 336893730000 ps | ||
| T181 | /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.2412906009 | Jul 02 09:13:30 AM PDT 24 | Jul 02 09:44:50 AM PDT 24 | 337010250000 ps | ||
| T182 | /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.99946688 | Jul 02 09:13:25 AM PDT 24 | Jul 02 09:48:46 AM PDT 24 | 336789390000 ps | ||
| T183 | /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.3547022999 | Jul 02 09:13:41 AM PDT 24 | Jul 02 09:40:48 AM PDT 24 | 336533250000 ps | ||
| T184 | /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.1769331702 | Jul 02 09:13:37 AM PDT 24 | Jul 02 09:49:49 AM PDT 24 | 336437930000 ps | ||
| T185 | /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.186765538 | Jul 02 09:13:42 AM PDT 24 | Jul 02 09:40:45 AM PDT 24 | 336847370000 ps | ||
| T186 | /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.3578010829 | Jul 02 09:13:31 AM PDT 24 | Jul 02 09:39:55 AM PDT 24 | 336896230000 ps | ||
| T187 | /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.3965957566 | Jul 02 09:13:37 AM PDT 24 | Jul 02 09:45:55 AM PDT 24 | 336469250000 ps | ||
| T188 | /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.1261052055 | Jul 02 09:13:45 AM PDT 24 | Jul 02 09:49:56 AM PDT 24 | 336672230000 ps | ||
| T189 | /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.3059862114 | Jul 02 09:13:45 AM PDT 24 | Jul 02 09:52:53 AM PDT 24 | 336546250000 ps | ||
| T190 | /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.492145059 | Jul 02 09:13:28 AM PDT 24 | Jul 02 09:44:23 AM PDT 24 | 336496410000 ps | ||
| T191 | /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.957988687 | Jul 02 09:13:33 AM PDT 24 | Jul 02 09:41:04 AM PDT 24 | 336381550000 ps | ||
| T192 | /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.3332985028 | Jul 02 09:13:25 AM PDT 24 | Jul 02 09:46:38 AM PDT 24 | 336586950000 ps | ||
| T193 | /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.2998105001 | Jul 02 09:13:24 AM PDT 24 | Jul 02 09:41:27 AM PDT 24 | 336707750000 ps | ||
| T194 | /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.2078728685 | Jul 02 09:13:25 AM PDT 24 | Jul 02 09:50:02 AM PDT 24 | 336610910000 ps | ||
| T195 | /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.1914043896 | Jul 02 09:13:24 AM PDT 24 | Jul 02 09:48:36 AM PDT 24 | 336552750000 ps | ||
| T196 | /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.2801869767 | Jul 02 09:13:35 AM PDT 24 | Jul 02 09:48:32 AM PDT 24 | 337012910000 ps | ||
| T197 | /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.1704435683 | Jul 02 09:13:27 AM PDT 24 | Jul 02 09:49:01 AM PDT 24 | 336824130000 ps | ||
| T198 | /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.332286803 | Jul 02 09:13:33 AM PDT 24 | Jul 02 09:41:02 AM PDT 24 | 337008590000 ps | ||
| T199 | /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.4172902753 | Jul 02 09:13:41 AM PDT 24 | Jul 02 09:44:13 AM PDT 24 | 336783390000 ps | ||
| T200 | /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.2696587610 | Jul 02 09:13:43 AM PDT 24 | Jul 02 09:48:28 AM PDT 24 | 336996530000 ps |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.1887107479 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 1394350000 ps |
| CPU time | 3.42 seconds |
| Started | Jul 02 09:04:22 AM PDT 24 |
| Finished | Jul 02 09:04:31 AM PDT 24 |
| Peak memory | 164964 kb |
| Host | smart-bd8515f8-e57d-40e6-acd3-151d2f52067b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1887107479 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.1887107479 |
| Directory | /workspace/10.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.2429691523 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 336565830000 ps |
| CPU time | 774.73 seconds |
| Started | Jul 02 09:04:17 AM PDT 24 |
| Finished | Jul 02 09:36:05 AM PDT 24 |
| Peak memory | 160820 kb |
| Host | smart-782ac7f8-eebb-4efa-9ffb-deb526968168 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2429691523 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.2429691523 |
| Directory | /workspace/11.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.2072874347 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 336544330000 ps |
| CPU time | 806.69 seconds |
| Started | Jul 02 09:13:27 AM PDT 24 |
| Finished | Jul 02 09:46:41 AM PDT 24 |
| Peak memory | 160912 kb |
| Host | smart-2a24895a-456a-435a-8da8-6158734a46f2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2072874347 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.2072874347 |
| Directory | /workspace/10.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.3243297585 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 336700550000 ps |
| CPU time | 958.67 seconds |
| Started | Jul 02 09:04:22 AM PDT 24 |
| Finished | Jul 02 09:44:20 AM PDT 24 |
| Peak memory | 160808 kb |
| Host | smart-df5263da-adfe-4e5a-8724-a5f64091b728 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3243297585 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.3243297585 |
| Directory | /workspace/0.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.205991672 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 336310230000 ps |
| CPU time | 846.87 seconds |
| Started | Jul 02 09:04:22 AM PDT 24 |
| Finished | Jul 02 09:38:52 AM PDT 24 |
| Peak memory | 160800 kb |
| Host | smart-7a1d6ad3-6b47-4f1e-b1ad-1c37ef2a1cdb |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=205991672 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.205991672 |
| Directory | /workspace/1.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.3746301366 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 336566550000 ps |
| CPU time | 788.99 seconds |
| Started | Jul 02 09:04:21 AM PDT 24 |
| Finished | Jul 02 09:36:00 AM PDT 24 |
| Peak memory | 160828 kb |
| Host | smart-953a4e70-4857-47ab-81c4-031bba927d0c |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3746301366 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.3746301366 |
| Directory | /workspace/10.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.1314582750 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 336464210000 ps |
| CPU time | 846.02 seconds |
| Started | Jul 02 09:04:23 AM PDT 24 |
| Finished | Jul 02 09:38:36 AM PDT 24 |
| Peak memory | 160824 kb |
| Host | smart-f5b3e1f6-42b9-47ea-88ef-32c8fa0d63e1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1314582750 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.1314582750 |
| Directory | /workspace/12.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.662942251 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 336416970000 ps |
| CPU time | 845.57 seconds |
| Started | Jul 02 09:04:23 AM PDT 24 |
| Finished | Jul 02 09:38:57 AM PDT 24 |
| Peak memory | 160820 kb |
| Host | smart-9641edb8-d1f2-407e-b928-f713d23a74e0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=662942251 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.662942251 |
| Directory | /workspace/13.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.2808879659 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 336990630000 ps |
| CPU time | 903.04 seconds |
| Started | Jul 02 09:04:20 AM PDT 24 |
| Finished | Jul 02 09:41:31 AM PDT 24 |
| Peak memory | 160812 kb |
| Host | smart-1c667a67-275b-477d-99f3-3a492cb39967 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2808879659 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.2808879659 |
| Directory | /workspace/14.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.119856272 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 336705310000 ps |
| CPU time | 771.08 seconds |
| Started | Jul 02 09:04:28 AM PDT 24 |
| Finished | Jul 02 09:36:15 AM PDT 24 |
| Peak memory | 160816 kb |
| Host | smart-0a01965d-0fb8-439a-a5ca-525d67b2dd7b |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=119856272 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.119856272 |
| Directory | /workspace/15.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.1894700225 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 336526450000 ps |
| CPU time | 967.3 seconds |
| Started | Jul 02 09:04:17 AM PDT 24 |
| Finished | Jul 02 09:45:00 AM PDT 24 |
| Peak memory | 160820 kb |
| Host | smart-3adfbb37-5815-4d86-89c5-956bfbfd8aad |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1894700225 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.1894700225 |
| Directory | /workspace/16.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.4138726444 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 336921870000 ps |
| CPU time | 828.38 seconds |
| Started | Jul 02 09:04:20 AM PDT 24 |
| Finished | Jul 02 09:37:56 AM PDT 24 |
| Peak memory | 160828 kb |
| Host | smart-dfb3d750-3115-43fd-829f-0a5d3f2a94ce |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4138726444 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.4138726444 |
| Directory | /workspace/17.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.4157961927 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 336682710000 ps |
| CPU time | 910.32 seconds |
| Started | Jul 02 09:04:19 AM PDT 24 |
| Finished | Jul 02 09:41:30 AM PDT 24 |
| Peak memory | 160816 kb |
| Host | smart-05e54202-bad8-40f5-b284-29800541742c |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4157961927 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.4157961927 |
| Directory | /workspace/18.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.1907533002 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 337081710000 ps |
| CPU time | 872.2 seconds |
| Started | Jul 02 09:04:19 AM PDT 24 |
| Finished | Jul 02 09:40:52 AM PDT 24 |
| Peak memory | 160808 kb |
| Host | smart-2e65c22f-aff0-44f4-bd8b-5a494a2126c7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1907533002 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.1907533002 |
| Directory | /workspace/19.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.24367644 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 336387450000 ps |
| CPU time | 804.05 seconds |
| Started | Jul 02 09:04:20 AM PDT 24 |
| Finished | Jul 02 09:37:16 AM PDT 24 |
| Peak memory | 160804 kb |
| Host | smart-9e18dae0-bda8-4379-968a-56fce07b3bd6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=24367644 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.24367644 |
| Directory | /workspace/2.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.528083113 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 336507090000 ps |
| CPU time | 852.12 seconds |
| Started | Jul 02 09:04:29 AM PDT 24 |
| Finished | Jul 02 09:39:03 AM PDT 24 |
| Peak memory | 160820 kb |
| Host | smart-9ae30b40-730d-47e7-92e5-76a9ff2c781e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=528083113 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.528083113 |
| Directory | /workspace/20.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.3871485501 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 336511890000 ps |
| CPU time | 715.51 seconds |
| Started | Jul 02 09:04:19 AM PDT 24 |
| Finished | Jul 02 09:33:30 AM PDT 24 |
| Peak memory | 160836 kb |
| Host | smart-4e8bab76-2340-4c21-8389-c6f5191dba0a |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3871485501 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.3871485501 |
| Directory | /workspace/21.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.2261972962 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 337100810000 ps |
| CPU time | 838.19 seconds |
| Started | Jul 02 09:04:19 AM PDT 24 |
| Finished | Jul 02 09:37:58 AM PDT 24 |
| Peak memory | 160816 kb |
| Host | smart-6cd35695-17b2-4f32-98df-986cfadd6141 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2261972962 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.2261972962 |
| Directory | /workspace/22.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.2501398552 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 337019170000 ps |
| CPU time | 835.23 seconds |
| Started | Jul 02 09:04:24 AM PDT 24 |
| Finished | Jul 02 09:38:41 AM PDT 24 |
| Peak memory | 160820 kb |
| Host | smart-b9a9b25c-7b9c-48a8-951f-b19908943d52 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2501398552 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.2501398552 |
| Directory | /workspace/23.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.91127287 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 337007130000 ps |
| CPU time | 738.87 seconds |
| Started | Jul 02 09:04:20 AM PDT 24 |
| Finished | Jul 02 09:34:10 AM PDT 24 |
| Peak memory | 160824 kb |
| Host | smart-6a355db0-cedc-4c05-9aa2-ec19176debec |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=91127287 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.91127287 |
| Directory | /workspace/24.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.2361267379 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 336744890000 ps |
| CPU time | 777.46 seconds |
| Started | Jul 02 09:04:18 AM PDT 24 |
| Finished | Jul 02 09:37:07 AM PDT 24 |
| Peak memory | 160784 kb |
| Host | smart-f6306bc3-a85f-4e7e-90cc-3a5fc7bc26eb |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2361267379 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.2361267379 |
| Directory | /workspace/25.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.850846537 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 336904350000 ps |
| CPU time | 779.91 seconds |
| Started | Jul 02 09:04:22 AM PDT 24 |
| Finished | Jul 02 09:36:01 AM PDT 24 |
| Peak memory | 160820 kb |
| Host | smart-ecf7d40f-fbd1-4afc-b6ed-d38d36764628 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=850846537 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.850846537 |
| Directory | /workspace/26.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.1125143801 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 337147410000 ps |
| CPU time | 762.72 seconds |
| Started | Jul 02 09:04:18 AM PDT 24 |
| Finished | Jul 02 09:36:34 AM PDT 24 |
| Peak memory | 160780 kb |
| Host | smart-a0ddfc6b-10a9-4805-ab54-7250a6894b32 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1125143801 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.1125143801 |
| Directory | /workspace/27.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.3319707528 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 336848150000 ps |
| CPU time | 872.38 seconds |
| Started | Jul 02 09:04:19 AM PDT 24 |
| Finished | Jul 02 09:40:09 AM PDT 24 |
| Peak memory | 160808 kb |
| Host | smart-07998a25-8bfc-45d1-8022-0bd8f0e41f16 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3319707528 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.3319707528 |
| Directory | /workspace/28.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.3255589353 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 336311250000 ps |
| CPU time | 954.32 seconds |
| Started | Jul 02 09:04:22 AM PDT 24 |
| Finished | Jul 02 09:44:26 AM PDT 24 |
| Peak memory | 160816 kb |
| Host | smart-6836d19d-055e-4d61-b1bb-aefa25247eab |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3255589353 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.3255589353 |
| Directory | /workspace/29.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.1839525523 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 336602710000 ps |
| CPU time | 951.97 seconds |
| Started | Jul 02 09:04:22 AM PDT 24 |
| Finished | Jul 02 09:43:58 AM PDT 24 |
| Peak memory | 160808 kb |
| Host | smart-ea5b10f7-a0d5-4a78-8922-17d50fb58a61 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1839525523 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.1839525523 |
| Directory | /workspace/3.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3898137124 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 336783670000 ps |
| CPU time | 848.76 seconds |
| Started | Jul 02 09:04:22 AM PDT 24 |
| Finished | Jul 02 09:38:40 AM PDT 24 |
| Peak memory | 160820 kb |
| Host | smart-9507db47-10ce-4206-bc6e-fb0c88ae9496 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3898137124 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.3898137124 |
| Directory | /workspace/30.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.616421033 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 337203750000 ps |
| CPU time | 772.42 seconds |
| Started | Jul 02 09:04:20 AM PDT 24 |
| Finished | Jul 02 09:35:53 AM PDT 24 |
| Peak memory | 160792 kb |
| Host | smart-74d163d7-8132-47e3-82f6-9e2e765f0d3f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=616421033 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.616421033 |
| Directory | /workspace/31.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.2773605834 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 337081990000 ps |
| CPU time | 799.42 seconds |
| Started | Jul 02 09:04:16 AM PDT 24 |
| Finished | Jul 02 09:37:16 AM PDT 24 |
| Peak memory | 160732 kb |
| Host | smart-15a30db2-30f9-4c9f-9c1d-2baae076ca71 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2773605834 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.2773605834 |
| Directory | /workspace/32.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.3777542100 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 337027810000 ps |
| CPU time | 873.95 seconds |
| Started | Jul 02 09:04:19 AM PDT 24 |
| Finished | Jul 02 09:40:07 AM PDT 24 |
| Peak memory | 160808 kb |
| Host | smart-5363feea-7795-4f4d-bf3b-37a26600f69a |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3777542100 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.3777542100 |
| Directory | /workspace/33.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.4116665476 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 336521670000 ps |
| CPU time | 767.44 seconds |
| Started | Jul 02 09:04:20 AM PDT 24 |
| Finished | Jul 02 09:35:44 AM PDT 24 |
| Peak memory | 160796 kb |
| Host | smart-2a3ca4ff-264c-4c7d-af77-d1fe017ed393 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4116665476 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.4116665476 |
| Directory | /workspace/34.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.3462785511 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 336319470000 ps |
| CPU time | 676.14 seconds |
| Started | Jul 02 09:04:25 AM PDT 24 |
| Finished | Jul 02 09:32:23 AM PDT 24 |
| Peak memory | 160836 kb |
| Host | smart-4dcb3e65-d701-4893-827d-10a695262416 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3462785511 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.3462785511 |
| Directory | /workspace/35.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.3982935332 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 336801050000 ps |
| CPU time | 869.72 seconds |
| Started | Jul 02 09:04:19 AM PDT 24 |
| Finished | Jul 02 09:40:51 AM PDT 24 |
| Peak memory | 160808 kb |
| Host | smart-60e7e24e-b8a7-404e-9472-3b816db8f055 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3982935332 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.3982935332 |
| Directory | /workspace/36.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.590679009 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 336634110000 ps |
| CPU time | 813.73 seconds |
| Started | Jul 02 09:04:18 AM PDT 24 |
| Finished | Jul 02 09:37:52 AM PDT 24 |
| Peak memory | 160796 kb |
| Host | smart-10e78a10-640a-4516-9a22-75bec80caa8c |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=590679009 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.590679009 |
| Directory | /workspace/37.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.2542024141 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 336659970000 ps |
| CPU time | 841.38 seconds |
| Started | Jul 02 09:04:28 AM PDT 24 |
| Finished | Jul 02 09:38:47 AM PDT 24 |
| Peak memory | 160888 kb |
| Host | smart-a4926276-b3a6-41fa-ab8b-cba7eaa8907c |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2542024141 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.2542024141 |
| Directory | /workspace/38.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.2310745016 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 336477730000 ps |
| CPU time | 952.85 seconds |
| Started | Jul 02 09:04:21 AM PDT 24 |
| Finished | Jul 02 09:44:20 AM PDT 24 |
| Peak memory | 160820 kb |
| Host | smart-bb156cb1-daf6-43e6-a3f6-c81252fbe4aa |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2310745016 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.2310745016 |
| Directory | /workspace/39.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.1591171514 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 336703630000 ps |
| CPU time | 828.8 seconds |
| Started | Jul 02 09:04:23 AM PDT 24 |
| Finished | Jul 02 09:38:39 AM PDT 24 |
| Peak memory | 160800 kb |
| Host | smart-a17647c6-79cb-4761-a56f-50699a436467 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1591171514 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.1591171514 |
| Directory | /workspace/4.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.4080152062 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 336830350000 ps |
| CPU time | 833.73 seconds |
| Started | Jul 02 09:04:23 AM PDT 24 |
| Finished | Jul 02 09:38:44 AM PDT 24 |
| Peak memory | 160820 kb |
| Host | smart-4284fb93-636d-4d42-a128-0321ec0211fb |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4080152062 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.4080152062 |
| Directory | /workspace/40.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.1521962756 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 336679010000 ps |
| CPU time | 793.08 seconds |
| Started | Jul 02 09:04:20 AM PDT 24 |
| Finished | Jul 02 09:36:50 AM PDT 24 |
| Peak memory | 160800 kb |
| Host | smart-0d0242b6-f5dd-4c95-9a63-6246b69461c0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1521962756 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.1521962756 |
| Directory | /workspace/41.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.3866436125 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 336438730000 ps |
| CPU time | 830.88 seconds |
| Started | Jul 02 09:04:20 AM PDT 24 |
| Finished | Jul 02 09:38:37 AM PDT 24 |
| Peak memory | 160804 kb |
| Host | smart-4242d2e2-6e2b-4532-9c51-d3875e755aa8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3866436125 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.3866436125 |
| Directory | /workspace/42.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.904132177 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 336854210000 ps |
| CPU time | 844.35 seconds |
| Started | Jul 02 09:04:24 AM PDT 24 |
| Finished | Jul 02 09:38:44 AM PDT 24 |
| Peak memory | 160816 kb |
| Host | smart-c5fd9ec5-8fd2-4438-a125-9c35f09fb517 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=904132177 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.904132177 |
| Directory | /workspace/43.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.3614717703 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 336870750000 ps |
| CPU time | 755.58 seconds |
| Started | Jul 02 09:04:20 AM PDT 24 |
| Finished | Jul 02 09:35:00 AM PDT 24 |
| Peak memory | 160840 kb |
| Host | smart-643de1fd-49a9-4bf6-b227-1f781bc49f21 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3614717703 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.3614717703 |
| Directory | /workspace/44.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.2667288148 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 336330670000 ps |
| CPU time | 773.23 seconds |
| Started | Jul 02 09:04:22 AM PDT 24 |
| Finished | Jul 02 09:35:53 AM PDT 24 |
| Peak memory | 160824 kb |
| Host | smart-003617c5-9053-4169-a4e8-301b863b6655 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2667288148 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.2667288148 |
| Directory | /workspace/45.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.3226118654 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 336881630000 ps |
| CPU time | 838.23 seconds |
| Started | Jul 02 09:04:21 AM PDT 24 |
| Finished | Jul 02 09:38:34 AM PDT 24 |
| Peak memory | 160824 kb |
| Host | smart-fd50ae32-4d36-4c85-899b-3c79bf164361 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3226118654 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.3226118654 |
| Directory | /workspace/46.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.2043502129 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 336999230000 ps |
| CPU time | 668.87 seconds |
| Started | Jul 02 09:04:21 AM PDT 24 |
| Finished | Jul 02 09:31:47 AM PDT 24 |
| Peak memory | 160816 kb |
| Host | smart-9ef41b4a-2625-481e-8486-950d9aa66191 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2043502129 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.2043502129 |
| Directory | /workspace/47.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.2969475018 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 336992230000 ps |
| CPU time | 807.72 seconds |
| Started | Jul 02 09:04:21 AM PDT 24 |
| Finished | Jul 02 09:37:40 AM PDT 24 |
| Peak memory | 160800 kb |
| Host | smart-fb3968a3-f2de-4556-93b4-ff528a7bab46 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2969475018 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.2969475018 |
| Directory | /workspace/48.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.2367875239 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 336980430000 ps |
| CPU time | 983.45 seconds |
| Started | Jul 02 09:04:37 AM PDT 24 |
| Finished | Jul 02 09:46:00 AM PDT 24 |
| Peak memory | 160820 kb |
| Host | smart-a6ee45d9-1483-4240-8fc5-97a7ded077e5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2367875239 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.2367875239 |
| Directory | /workspace/49.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.3000848292 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 336659430000 ps |
| CPU time | 743.67 seconds |
| Started | Jul 02 09:04:24 AM PDT 24 |
| Finished | Jul 02 09:34:31 AM PDT 24 |
| Peak memory | 160760 kb |
| Host | smart-a2078c43-89c8-49fa-876e-bd215df32aef |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3000848292 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.3000848292 |
| Directory | /workspace/5.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.837742250 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 337028590000 ps |
| CPU time | 976.72 seconds |
| Started | Jul 02 09:04:17 AM PDT 24 |
| Finished | Jul 02 09:45:06 AM PDT 24 |
| Peak memory | 160812 kb |
| Host | smart-79fba8f5-fc7a-423f-84fd-9c4c7478e59a |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=837742250 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.837742250 |
| Directory | /workspace/6.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.3861349561 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 336874290000 ps |
| CPU time | 761.8 seconds |
| Started | Jul 02 09:04:22 AM PDT 24 |
| Finished | Jul 02 09:35:05 AM PDT 24 |
| Peak memory | 160804 kb |
| Host | smart-5dd26f13-87fa-4167-99cc-858697471044 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3861349561 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.3861349561 |
| Directory | /workspace/7.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.2999969845 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 336568590000 ps |
| CPU time | 853 seconds |
| Started | Jul 02 09:04:17 AM PDT 24 |
| Finished | Jul 02 09:39:07 AM PDT 24 |
| Peak memory | 160796 kb |
| Host | smart-e53196df-ef71-49d6-814b-fbac1157bc07 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2999969845 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.2999969845 |
| Directory | /workspace/8.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.2091073041 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 336865370000 ps |
| CPU time | 810.23 seconds |
| Started | Jul 02 09:04:25 AM PDT 24 |
| Finished | Jul 02 09:37:27 AM PDT 24 |
| Peak memory | 160772 kb |
| Host | smart-a6f45bc4-9656-45c0-b245-e2df2893feaa |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2091073041 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.2091073041 |
| Directory | /workspace/9.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.3250027661 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 336921950000 ps |
| CPU time | 752.35 seconds |
| Started | Jul 02 09:13:23 AM PDT 24 |
| Finished | Jul 02 09:43:57 AM PDT 24 |
| Peak memory | 160760 kb |
| Host | smart-be273d45-5990-4037-88be-d78b6dcccf63 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3250027661 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.3250027661 |
| Directory | /workspace/0.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.3606463280 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 336658290000 ps |
| CPU time | 751.39 seconds |
| Started | Jul 02 09:13:25 AM PDT 24 |
| Finished | Jul 02 09:44:42 AM PDT 24 |
| Peak memory | 160820 kb |
| Host | smart-73f6ea7f-bf53-43ca-8dd5-ce35928427dd |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3606463280 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.3606463280 |
| Directory | /workspace/1.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.2257887386 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 336502690000 ps |
| CPU time | 684.89 seconds |
| Started | Jul 02 09:13:25 AM PDT 24 |
| Finished | Jul 02 09:41:40 AM PDT 24 |
| Peak memory | 160764 kb |
| Host | smart-ef72df4d-2600-4317-8e4a-30980444b1f2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2257887386 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.2257887386 |
| Directory | /workspace/11.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.4059949487 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 336488950000 ps |
| CPU time | 654.33 seconds |
| Started | Jul 02 09:13:24 AM PDT 24 |
| Finished | Jul 02 09:40:32 AM PDT 24 |
| Peak memory | 160800 kb |
| Host | smart-f0b82cf8-cdbb-4b69-81fa-aed524ddad8d |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4059949487 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.4059949487 |
| Directory | /workspace/12.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.957988687 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 336381550000 ps |
| CPU time | 669.46 seconds |
| Started | Jul 02 09:13:33 AM PDT 24 |
| Finished | Jul 02 09:41:04 AM PDT 24 |
| Peak memory | 160792 kb |
| Host | smart-56818747-e965-4535-be39-e9898c01922e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=957988687 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.957988687 |
| Directory | /workspace/13.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.3160951705 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 336394070000 ps |
| CPU time | 770.98 seconds |
| Started | Jul 02 09:13:31 AM PDT 24 |
| Finished | Jul 02 09:45:24 AM PDT 24 |
| Peak memory | 160828 kb |
| Host | smart-18d891f3-8d12-4ee8-ac29-abed6162afb5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3160951705 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.3160951705 |
| Directory | /workspace/14.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.2841293810 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 336727070000 ps |
| CPU time | 848.97 seconds |
| Started | Jul 02 09:13:31 AM PDT 24 |
| Finished | Jul 02 09:49:16 AM PDT 24 |
| Peak memory | 160816 kb |
| Host | smart-95a6b0fd-687f-4f17-bc97-ade3e902891a |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2841293810 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.2841293810 |
| Directory | /workspace/15.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.3332985028 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 336586950000 ps |
| CPU time | 814.59 seconds |
| Started | Jul 02 09:13:25 AM PDT 24 |
| Finished | Jul 02 09:46:38 AM PDT 24 |
| Peak memory | 160832 kb |
| Host | smart-f1a2bff0-6fc8-4482-9987-79093455e9b0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3332985028 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.3332985028 |
| Directory | /workspace/16.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.2998105001 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 336707750000 ps |
| CPU time | 690.92 seconds |
| Started | Jul 02 09:13:24 AM PDT 24 |
| Finished | Jul 02 09:41:27 AM PDT 24 |
| Peak memory | 160816 kb |
| Host | smart-50982de0-69a3-4ec5-bd48-48ba3ea52c2a |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2998105001 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.2998105001 |
| Directory | /workspace/17.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.1397833644 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 336814450000 ps |
| CPU time | 987.84 seconds |
| Started | Jul 02 09:13:41 AM PDT 24 |
| Finished | Jul 02 09:55:51 AM PDT 24 |
| Peak memory | 160828 kb |
| Host | smart-cc92caa6-0ab0-4e16-a868-902be422d0dd |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1397833644 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.1397833644 |
| Directory | /workspace/18.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.1704435683 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 336824130000 ps |
| CPU time | 869.11 seconds |
| Started | Jul 02 09:13:27 AM PDT 24 |
| Finished | Jul 02 09:49:01 AM PDT 24 |
| Peak memory | 160756 kb |
| Host | smart-673e8ee9-98d5-490b-b93f-b065f9701580 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1704435683 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.1704435683 |
| Directory | /workspace/19.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.3578010829 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 336896230000 ps |
| CPU time | 642.11 seconds |
| Started | Jul 02 09:13:31 AM PDT 24 |
| Finished | Jul 02 09:39:55 AM PDT 24 |
| Peak memory | 160820 kb |
| Host | smart-abb9c19d-f744-4adb-8f7d-75554a20a670 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3578010829 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.3578010829 |
| Directory | /workspace/2.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.1914043896 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 336552750000 ps |
| CPU time | 864.79 seconds |
| Started | Jul 02 09:13:24 AM PDT 24 |
| Finished | Jul 02 09:48:36 AM PDT 24 |
| Peak memory | 160892 kb |
| Host | smart-28c66a93-6c6e-4070-a589-aef8df2e67f5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1914043896 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.1914043896 |
| Directory | /workspace/20.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.445490214 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 336766590000 ps |
| CPU time | 692.44 seconds |
| Started | Jul 02 09:13:24 AM PDT 24 |
| Finished | Jul 02 09:41:53 AM PDT 24 |
| Peak memory | 160812 kb |
| Host | smart-e0a42dfe-426f-43aa-b868-031cf3e90b9d |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=445490214 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.445490214 |
| Directory | /workspace/21.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.2801869767 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 337012910000 ps |
| CPU time | 852.65 seconds |
| Started | Jul 02 09:13:35 AM PDT 24 |
| Finished | Jul 02 09:48:32 AM PDT 24 |
| Peak memory | 160892 kb |
| Host | smart-e8c1f68d-bfa8-4691-baf1-2e81f26d62c8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2801869767 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.2801869767 |
| Directory | /workspace/22.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.662865078 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 336722130000 ps |
| CPU time | 834.29 seconds |
| Started | Jul 02 09:13:37 AM PDT 24 |
| Finished | Jul 02 09:47:20 AM PDT 24 |
| Peak memory | 160828 kb |
| Host | smart-20fe1dbd-8a8d-4078-8d9e-89cd66f47d60 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=662865078 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.662865078 |
| Directory | /workspace/23.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.3749609142 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 336985830000 ps |
| CPU time | 732.37 seconds |
| Started | Jul 02 09:13:24 AM PDT 24 |
| Finished | Jul 02 09:43:14 AM PDT 24 |
| Peak memory | 160800 kb |
| Host | smart-176809aa-acac-4905-a994-890e637449dc |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3749609142 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.3749609142 |
| Directory | /workspace/24.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.1554972205 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 336389470000 ps |
| CPU time | 818.17 seconds |
| Started | Jul 02 09:13:27 AM PDT 24 |
| Finished | Jul 02 09:47:00 AM PDT 24 |
| Peak memory | 160920 kb |
| Host | smart-4cf69675-cb7b-4164-b8f8-c7fa288a6d56 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1554972205 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.1554972205 |
| Directory | /workspace/25.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.1459894369 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 337039230000 ps |
| CPU time | 795.09 seconds |
| Started | Jul 02 09:13:42 AM PDT 24 |
| Finished | Jul 02 09:46:01 AM PDT 24 |
| Peak memory | 160844 kb |
| Host | smart-694be251-3067-45d5-9d8a-c1eeee96629a |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1459894369 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.1459894369 |
| Directory | /workspace/26.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.3045890764 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 336413450000 ps |
| CPU time | 836.17 seconds |
| Started | Jul 02 09:13:40 AM PDT 24 |
| Finished | Jul 02 09:47:53 AM PDT 24 |
| Peak memory | 160740 kb |
| Host | smart-2e3ce131-48a4-4f57-b64a-fd80f77559da |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3045890764 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.3045890764 |
| Directory | /workspace/27.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.2044626242 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 336841870000 ps |
| CPU time | 738.42 seconds |
| Started | Jul 02 09:13:44 AM PDT 24 |
| Finished | Jul 02 09:43:35 AM PDT 24 |
| Peak memory | 160780 kb |
| Host | smart-2f6eb9c6-e036-4fd6-9ae3-ae7acc2fedfc |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2044626242 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.2044626242 |
| Directory | /workspace/28.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.2447711906 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 337018770000 ps |
| CPU time | 840.58 seconds |
| Started | Jul 02 09:13:35 AM PDT 24 |
| Finished | Jul 02 09:47:32 AM PDT 24 |
| Peak memory | 160832 kb |
| Host | smart-b2820547-67de-45e9-b137-1d4508e45821 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2447711906 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.2447711906 |
| Directory | /workspace/29.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.2412906009 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 337010250000 ps |
| CPU time | 766.86 seconds |
| Started | Jul 02 09:13:30 AM PDT 24 |
| Finished | Jul 02 09:44:50 AM PDT 24 |
| Peak memory | 160760 kb |
| Host | smart-ce31bad8-6cac-4b3c-9ba7-edcfea7bad86 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2412906009 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.2412906009 |
| Directory | /workspace/3.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.4172902753 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 336783390000 ps |
| CPU time | 732.68 seconds |
| Started | Jul 02 09:13:41 AM PDT 24 |
| Finished | Jul 02 09:44:13 AM PDT 24 |
| Peak memory | 160808 kb |
| Host | smart-d9e0c3e0-22a9-4d3d-914d-a5fe6b81603a |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4172902753 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.4172902753 |
| Directory | /workspace/30.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.3059862114 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 336546250000 ps |
| CPU time | 934.63 seconds |
| Started | Jul 02 09:13:45 AM PDT 24 |
| Finished | Jul 02 09:52:53 AM PDT 24 |
| Peak memory | 160828 kb |
| Host | smart-dff76232-30c0-4791-8228-fbfe56fef1db |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3059862114 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.3059862114 |
| Directory | /workspace/31.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.4071253299 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 336698010000 ps |
| CPU time | 836.09 seconds |
| Started | Jul 02 09:13:48 AM PDT 24 |
| Finished | Jul 02 09:48:03 AM PDT 24 |
| Peak memory | 160832 kb |
| Host | smart-03e3db03-808b-4c44-b720-9ff20d9fd902 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4071253299 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.4071253299 |
| Directory | /workspace/32.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.2696587610 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 336996530000 ps |
| CPU time | 835.4 seconds |
| Started | Jul 02 09:13:43 AM PDT 24 |
| Finished | Jul 02 09:48:28 AM PDT 24 |
| Peak memory | 160828 kb |
| Host | smart-6c505b3d-7e4c-4bd0-afbb-486b2e265993 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2696587610 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.2696587610 |
| Directory | /workspace/33.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.1261052055 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 336672230000 ps |
| CPU time | 881.76 seconds |
| Started | Jul 02 09:13:45 AM PDT 24 |
| Finished | Jul 02 09:49:56 AM PDT 24 |
| Peak memory | 160816 kb |
| Host | smart-abeff064-2138-49e0-9132-3ee2a74e07a3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1261052055 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.1261052055 |
| Directory | /workspace/34.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.1231422675 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 336642250000 ps |
| CPU time | 806.26 seconds |
| Started | Jul 02 09:13:42 AM PDT 24 |
| Finished | Jul 02 09:46:54 AM PDT 24 |
| Peak memory | 160832 kb |
| Host | smart-c76a71fa-f12a-4983-aa23-e6b20b9b54a3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1231422675 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.1231422675 |
| Directory | /workspace/35.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.186765538 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 336847370000 ps |
| CPU time | 657.26 seconds |
| Started | Jul 02 09:13:42 AM PDT 24 |
| Finished | Jul 02 09:40:45 AM PDT 24 |
| Peak memory | 160820 kb |
| Host | smart-79cad6da-d88b-46e8-a8b9-9eb63f7942a5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=186765538 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.186765538 |
| Directory | /workspace/36.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.3965957566 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 336469250000 ps |
| CPU time | 776.71 seconds |
| Started | Jul 02 09:13:37 AM PDT 24 |
| Finished | Jul 02 09:45:55 AM PDT 24 |
| Peak memory | 160816 kb |
| Host | smart-a3010cd2-4b3f-4ff8-9271-2c36c0f2d5f1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3965957566 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.3965957566 |
| Directory | /workspace/37.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.4267916381 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 336737970000 ps |
| CPU time | 862.72 seconds |
| Started | Jul 02 09:13:41 AM PDT 24 |
| Finished | Jul 02 09:48:54 AM PDT 24 |
| Peak memory | 160760 kb |
| Host | smart-557f8a90-6bc0-44e8-bb24-301d33416f0b |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4267916381 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.4267916381 |
| Directory | /workspace/38.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.492145059 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 336496410000 ps |
| CPU time | 740.46 seconds |
| Started | Jul 02 09:13:28 AM PDT 24 |
| Finished | Jul 02 09:44:23 AM PDT 24 |
| Peak memory | 160784 kb |
| Host | smart-bda86afd-df2f-4455-a631-2da7549fec0c |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=492145059 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.492145059 |
| Directory | /workspace/39.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.2168572238 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 336787510000 ps |
| CPU time | 997.33 seconds |
| Started | Jul 02 09:13:50 AM PDT 24 |
| Finished | Jul 02 09:55:53 AM PDT 24 |
| Peak memory | 160816 kb |
| Host | smart-bbaac87f-5221-42ee-8d0d-59ad23cc305e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2168572238 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.2168572238 |
| Directory | /workspace/4.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.1743660866 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 336339110000 ps |
| CPU time | 806.19 seconds |
| Started | Jul 02 09:13:28 AM PDT 24 |
| Finished | Jul 02 09:46:30 AM PDT 24 |
| Peak memory | 160832 kb |
| Host | smart-8015decd-c929-4225-abb7-d31482040f58 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1743660866 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.1743660866 |
| Directory | /workspace/40.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.3547022999 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 336533250000 ps |
| CPU time | 651.5 seconds |
| Started | Jul 02 09:13:41 AM PDT 24 |
| Finished | Jul 02 09:40:48 AM PDT 24 |
| Peak memory | 160824 kb |
| Host | smart-c58aab74-0b27-452a-8cf9-b8966735b3d0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3547022999 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.3547022999 |
| Directory | /workspace/41.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.3486930750 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 336865390000 ps |
| CPU time | 805.15 seconds |
| Started | Jul 02 09:13:35 AM PDT 24 |
| Finished | Jul 02 09:46:51 AM PDT 24 |
| Peak memory | 160812 kb |
| Host | smart-e388c93e-73cb-4e7e-a8d8-132033111429 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3486930750 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.3486930750 |
| Directory | /workspace/42.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.1769331702 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 336437930000 ps |
| CPU time | 887.02 seconds |
| Started | Jul 02 09:13:37 AM PDT 24 |
| Finished | Jul 02 09:49:49 AM PDT 24 |
| Peak memory | 160816 kb |
| Host | smart-9b1fd4e2-f6dd-413a-b760-93fca2737239 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1769331702 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.1769331702 |
| Directory | /workspace/43.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.3844043872 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 336893730000 ps |
| CPU time | 747.68 seconds |
| Started | Jul 02 09:13:37 AM PDT 24 |
| Finished | Jul 02 09:44:04 AM PDT 24 |
| Peak memory | 160840 kb |
| Host | smart-cdf232af-62f7-428f-b722-419238a18344 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3844043872 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.3844043872 |
| Directory | /workspace/44.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.3989955174 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 336897290000 ps |
| CPU time | 721.48 seconds |
| Started | Jul 02 09:13:46 AM PDT 24 |
| Finished | Jul 02 09:43:38 AM PDT 24 |
| Peak memory | 160828 kb |
| Host | smart-ec1a5158-439b-4b88-bc0c-15063b3251c8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3989955174 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.3989955174 |
| Directory | /workspace/45.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.3287287604 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 337024050000 ps |
| CPU time | 862.92 seconds |
| Started | Jul 02 09:13:43 AM PDT 24 |
| Finished | Jul 02 09:49:10 AM PDT 24 |
| Peak memory | 160820 kb |
| Host | smart-561f9866-6daa-4837-8046-ed2429d2e57b |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3287287604 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.3287287604 |
| Directory | /workspace/46.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.610892357 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 336628850000 ps |
| CPU time | 1000.83 seconds |
| Started | Jul 02 09:13:45 AM PDT 24 |
| Finished | Jul 02 09:55:53 AM PDT 24 |
| Peak memory | 160820 kb |
| Host | smart-4918ed75-df17-4964-890d-a3c647766722 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=610892357 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.610892357 |
| Directory | /workspace/47.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.654541853 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 337110090000 ps |
| CPU time | 743.48 seconds |
| Started | Jul 02 09:13:27 AM PDT 24 |
| Finished | Jul 02 09:44:00 AM PDT 24 |
| Peak memory | 160828 kb |
| Host | smart-824a9b96-c0a8-4865-ac19-ffe4e784fe6a |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=654541853 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.654541853 |
| Directory | /workspace/48.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.332286803 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 337008590000 ps |
| CPU time | 670.47 seconds |
| Started | Jul 02 09:13:33 AM PDT 24 |
| Finished | Jul 02 09:41:02 AM PDT 24 |
| Peak memory | 160804 kb |
| Host | smart-cbb041cb-f93b-40cd-980e-d4c951e1dba1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=332286803 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.332286803 |
| Directory | /workspace/49.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.22792625 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 336479070000 ps |
| CPU time | 738.56 seconds |
| Started | Jul 02 09:13:35 AM PDT 24 |
| Finished | Jul 02 09:44:16 AM PDT 24 |
| Peak memory | 160812 kb |
| Host | smart-77e4137e-a0c5-4926-b197-8dbde471bcd8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=22792625 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.22792625 |
| Directory | /workspace/5.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.178910697 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 336911710000 ps |
| CPU time | 877.02 seconds |
| Started | Jul 02 09:13:26 AM PDT 24 |
| Finished | Jul 02 09:49:37 AM PDT 24 |
| Peak memory | 160812 kb |
| Host | smart-9e1a172a-0c4f-49a4-b4ca-d95153157add |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=178910697 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.178910697 |
| Directory | /workspace/6.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.2100524071 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 336848030000 ps |
| CPU time | 729.01 seconds |
| Started | Jul 02 09:13:30 AM PDT 24 |
| Finished | Jul 02 09:43:53 AM PDT 24 |
| Peak memory | 160820 kb |
| Host | smart-bf2b4c11-f94c-430c-972d-2060f2331926 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2100524071 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.2100524071 |
| Directory | /workspace/7.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.99946688 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 336789390000 ps |
| CPU time | 850.85 seconds |
| Started | Jul 02 09:13:25 AM PDT 24 |
| Finished | Jul 02 09:48:46 AM PDT 24 |
| Peak memory | 160800 kb |
| Host | smart-88f80535-497e-441b-8fe0-d49f070c3e6c |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=99946688 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.99946688 |
| Directory | /workspace/8.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.2078728685 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 336610910000 ps |
| CPU time | 884.87 seconds |
| Started | Jul 02 09:13:25 AM PDT 24 |
| Finished | Jul 02 09:50:02 AM PDT 24 |
| Peak memory | 160816 kb |
| Host | smart-c64f440c-a9c2-4ad7-9975-0d37e2cb4042 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2078728685 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.2078728685 |
| Directory | /workspace/9.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.3931974845 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 1367690000 ps |
| CPU time | 4.37 seconds |
| Started | Jul 02 09:13:10 AM PDT 24 |
| Finished | Jul 02 09:13:26 AM PDT 24 |
| Peak memory | 164940 kb |
| Host | smart-6db2f27f-c591-4fd7-8aa3-164a9a5fee02 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3931974845 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.3931974845 |
| Directory | /workspace/0.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.1166069468 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 1476310000 ps |
| CPU time | 4.22 seconds |
| Started | Jul 02 09:13:12 AM PDT 24 |
| Finished | Jul 02 09:13:26 AM PDT 24 |
| Peak memory | 164940 kb |
| Host | smart-50c9ffc8-f36e-4c96-b73f-1d30cd249204 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1166069468 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.1166069468 |
| Directory | /workspace/1.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.217529662 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 1609090000 ps |
| CPU time | 5.29 seconds |
| Started | Jul 02 09:13:18 AM PDT 24 |
| Finished | Jul 02 09:13:33 AM PDT 24 |
| Peak memory | 164952 kb |
| Host | smart-668913ac-1037-4cfe-9dcd-481eb677fb9c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=217529662 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.217529662 |
| Directory | /workspace/10.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.1734069937 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 1344530000 ps |
| CPU time | 3.53 seconds |
| Started | Jul 02 09:13:12 AM PDT 24 |
| Finished | Jul 02 09:13:25 AM PDT 24 |
| Peak memory | 164880 kb |
| Host | smart-c8a848fa-ec24-4bd9-8a4f-d5d6afd18e93 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1734069937 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.1734069937 |
| Directory | /workspace/11.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.406199463 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 1482190000 ps |
| CPU time | 4.75 seconds |
| Started | Jul 02 09:13:14 AM PDT 24 |
| Finished | Jul 02 09:13:29 AM PDT 24 |
| Peak memory | 164980 kb |
| Host | smart-e43b1bd3-2247-4eb3-96a0-f335eda246d7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=406199463 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.406199463 |
| Directory | /workspace/12.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.1639852594 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 1440410000 ps |
| CPU time | 3.7 seconds |
| Started | Jul 02 09:13:16 AM PDT 24 |
| Finished | Jul 02 09:13:28 AM PDT 24 |
| Peak memory | 164968 kb |
| Host | smart-664cf70e-a9c7-4d9d-b2de-2217120bd738 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1639852594 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.1639852594 |
| Directory | /workspace/13.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.2131639051 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 1351870000 ps |
| CPU time | 4.27 seconds |
| Started | Jul 02 09:13:18 AM PDT 24 |
| Finished | Jul 02 09:13:31 AM PDT 24 |
| Peak memory | 164972 kb |
| Host | smart-1a00fe82-e556-4ca7-bf5e-1399a8771260 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2131639051 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.2131639051 |
| Directory | /workspace/14.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.3610133982 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 1562690000 ps |
| CPU time | 5.93 seconds |
| Started | Jul 02 09:13:17 AM PDT 24 |
| Finished | Jul 02 09:13:34 AM PDT 24 |
| Peak memory | 164924 kb |
| Host | smart-4127a483-79d2-46d4-9bd0-f68dd38d6a14 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3610133982 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.3610133982 |
| Directory | /workspace/15.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.1122354272 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 1542850000 ps |
| CPU time | 4.16 seconds |
| Started | Jul 02 09:13:14 AM PDT 24 |
| Finished | Jul 02 09:13:28 AM PDT 24 |
| Peak memory | 164944 kb |
| Host | smart-91bb44ff-1096-420a-b954-173a58eddc23 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1122354272 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.1122354272 |
| Directory | /workspace/16.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.4103771333 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 1563430000 ps |
| CPU time | 4.41 seconds |
| Started | Jul 02 09:13:21 AM PDT 24 |
| Finished | Jul 02 09:13:32 AM PDT 24 |
| Peak memory | 164948 kb |
| Host | smart-4a7a7c86-1899-4443-bb15-58512b608d24 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4103771333 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.4103771333 |
| Directory | /workspace/17.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.3675488410 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 1476970000 ps |
| CPU time | 4.28 seconds |
| Started | Jul 02 09:13:17 AM PDT 24 |
| Finished | Jul 02 09:13:30 AM PDT 24 |
| Peak memory | 164928 kb |
| Host | smart-4e624593-aa28-4e99-ae6c-1a6921502709 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3675488410 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.3675488410 |
| Directory | /workspace/18.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.1562429066 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 1446350000 ps |
| CPU time | 4.14 seconds |
| Started | Jul 02 09:13:19 AM PDT 24 |
| Finished | Jul 02 09:13:30 AM PDT 24 |
| Peak memory | 164976 kb |
| Host | smart-6555441d-41d7-4dc2-a9b9-18d7d5972e17 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1562429066 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.1562429066 |
| Directory | /workspace/19.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.4161559729 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 1580030000 ps |
| CPU time | 5.57 seconds |
| Started | Jul 02 09:13:14 AM PDT 24 |
| Finished | Jul 02 09:13:35 AM PDT 24 |
| Peak memory | 164968 kb |
| Host | smart-26fd3e86-73a9-4b45-8f11-6298e90f7e7f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4161559729 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.4161559729 |
| Directory | /workspace/2.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.1057640343 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 1461310000 ps |
| CPU time | 4.98 seconds |
| Started | Jul 02 09:13:17 AM PDT 24 |
| Finished | Jul 02 09:13:31 AM PDT 24 |
| Peak memory | 164932 kb |
| Host | smart-b655f881-0e70-45b9-aadc-3356ac2734e6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1057640343 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.1057640343 |
| Directory | /workspace/20.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.1421804082 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 1543310000 ps |
| CPU time | 4.29 seconds |
| Started | Jul 02 09:13:14 AM PDT 24 |
| Finished | Jul 02 09:13:29 AM PDT 24 |
| Peak memory | 164972 kb |
| Host | smart-d9fc1dc5-390d-45f8-a813-d69fedb672a9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1421804082 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.1421804082 |
| Directory | /workspace/21.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.1030581754 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 1357570000 ps |
| CPU time | 3.29 seconds |
| Started | Jul 02 09:13:15 AM PDT 24 |
| Finished | Jul 02 09:13:27 AM PDT 24 |
| Peak memory | 164956 kb |
| Host | smart-af4fd9ad-77c6-4c95-bbfd-02147e622eca |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1030581754 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.1030581754 |
| Directory | /workspace/22.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.1533618960 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 1361490000 ps |
| CPU time | 4.25 seconds |
| Started | Jul 02 09:13:18 AM PDT 24 |
| Finished | Jul 02 09:13:31 AM PDT 24 |
| Peak memory | 164952 kb |
| Host | smart-d25b16dd-93d5-404f-b4a7-1ad87f115348 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1533618960 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.1533618960 |
| Directory | /workspace/23.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.2159209554 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 1350770000 ps |
| CPU time | 3.23 seconds |
| Started | Jul 02 09:13:20 AM PDT 24 |
| Finished | Jul 02 09:13:30 AM PDT 24 |
| Peak memory | 164936 kb |
| Host | smart-4f20a592-a4ae-48f8-a272-a6d26ac6b339 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2159209554 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.2159209554 |
| Directory | /workspace/24.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.1820560353 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 1440050000 ps |
| CPU time | 4.49 seconds |
| Started | Jul 02 09:13:18 AM PDT 24 |
| Finished | Jul 02 09:13:31 AM PDT 24 |
| Peak memory | 164980 kb |
| Host | smart-4cde556f-c38b-41fe-bc3b-6272c739dd07 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1820560353 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.1820560353 |
| Directory | /workspace/25.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.4019213645 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 1536170000 ps |
| CPU time | 4.74 seconds |
| Started | Jul 02 09:13:20 AM PDT 24 |
| Finished | Jul 02 09:13:32 AM PDT 24 |
| Peak memory | 164968 kb |
| Host | smart-1796e918-b566-40d3-a676-2c1bb6974777 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4019213645 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.4019213645 |
| Directory | /workspace/26.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.334351739 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 1400810000 ps |
| CPU time | 5.43 seconds |
| Started | Jul 02 09:13:18 AM PDT 24 |
| Finished | Jul 02 09:13:34 AM PDT 24 |
| Peak memory | 164932 kb |
| Host | smart-44c696f5-4c33-42c5-b338-b6d89625590b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=334351739 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.334351739 |
| Directory | /workspace/27.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.1313460086 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 1476630000 ps |
| CPU time | 4.48 seconds |
| Started | Jul 02 09:13:17 AM PDT 24 |
| Finished | Jul 02 09:13:31 AM PDT 24 |
| Peak memory | 164968 kb |
| Host | smart-d0aaf535-ab96-4f8d-983d-d64f948da6d4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1313460086 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.1313460086 |
| Directory | /workspace/28.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.3934781913 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 1502950000 ps |
| CPU time | 4 seconds |
| Started | Jul 02 09:13:25 AM PDT 24 |
| Finished | Jul 02 09:13:35 AM PDT 24 |
| Peak memory | 164916 kb |
| Host | smart-05b2184e-82cd-4126-b70a-f22cc5dae190 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3934781913 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.3934781913 |
| Directory | /workspace/29.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.2146312739 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 1228630000 ps |
| CPU time | 4.31 seconds |
| Started | Jul 02 09:13:16 AM PDT 24 |
| Finished | Jul 02 09:13:29 AM PDT 24 |
| Peak memory | 164936 kb |
| Host | smart-bc0d582d-5702-4d26-96c0-62e7ab90f2e7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2146312739 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.2146312739 |
| Directory | /workspace/3.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.718589281 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 1553930000 ps |
| CPU time | 4.84 seconds |
| Started | Jul 02 09:13:19 AM PDT 24 |
| Finished | Jul 02 09:13:32 AM PDT 24 |
| Peak memory | 164904 kb |
| Host | smart-700fb904-1792-466b-8126-0b2fd745a8f4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=718589281 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.718589281 |
| Directory | /workspace/30.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.41416734 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 1464930000 ps |
| CPU time | 4.06 seconds |
| Started | Jul 02 09:13:18 AM PDT 24 |
| Finished | Jul 02 09:13:30 AM PDT 24 |
| Peak memory | 164904 kb |
| Host | smart-cfff2acc-7165-463e-bf7d-2d278d6574ed |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=41416734 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.41416734 |
| Directory | /workspace/31.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.2272534973 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 1468370000 ps |
| CPU time | 4.47 seconds |
| Started | Jul 02 09:13:17 AM PDT 24 |
| Finished | Jul 02 09:13:31 AM PDT 24 |
| Peak memory | 164944 kb |
| Host | smart-036c1f9a-7ca6-4f04-aa65-81d5bee444b7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2272534973 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.2272534973 |
| Directory | /workspace/32.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.1537553778 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 1503810000 ps |
| CPU time | 4.21 seconds |
| Started | Jul 02 09:13:18 AM PDT 24 |
| Finished | Jul 02 09:13:31 AM PDT 24 |
| Peak memory | 164944 kb |
| Host | smart-f4463f38-6d2d-4073-b308-0dc6b4d769ef |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1537553778 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.1537553778 |
| Directory | /workspace/33.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.3850441375 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 1470870000 ps |
| CPU time | 4.28 seconds |
| Started | Jul 02 09:13:21 AM PDT 24 |
| Finished | Jul 02 09:13:32 AM PDT 24 |
| Peak memory | 164952 kb |
| Host | smart-dc11324d-997d-471e-b5e0-60ffc5e391ae |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3850441375 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.3850441375 |
| Directory | /workspace/34.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.3881804350 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 1328670000 ps |
| CPU time | 3.45 seconds |
| Started | Jul 02 09:13:22 AM PDT 24 |
| Finished | Jul 02 09:13:31 AM PDT 24 |
| Peak memory | 164976 kb |
| Host | smart-ba478afe-8c07-45c9-8403-62f8f98f9a0d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3881804350 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.3881804350 |
| Directory | /workspace/35.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.3707714869 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 1593290000 ps |
| CPU time | 5.32 seconds |
| Started | Jul 02 09:13:21 AM PDT 24 |
| Finished | Jul 02 09:13:34 AM PDT 24 |
| Peak memory | 164964 kb |
| Host | smart-28d209de-57b4-4528-94e8-adc56613296e |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3707714869 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.3707714869 |
| Directory | /workspace/36.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1467413038 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 1226390000 ps |
| CPU time | 3.56 seconds |
| Started | Jul 02 09:13:21 AM PDT 24 |
| Finished | Jul 02 09:13:31 AM PDT 24 |
| Peak memory | 164980 kb |
| Host | smart-fa302beb-fca1-4d39-aa2e-cb71cbba6c55 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1467413038 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.1467413038 |
| Directory | /workspace/37.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.738784301 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 1561030000 ps |
| CPU time | 4 seconds |
| Started | Jul 02 09:13:22 AM PDT 24 |
| Finished | Jul 02 09:13:33 AM PDT 24 |
| Peak memory | 164872 kb |
| Host | smart-2926523f-e93b-42b1-bd13-4cc94112bb8d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=738784301 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.738784301 |
| Directory | /workspace/38.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.729975110 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 1455990000 ps |
| CPU time | 3.93 seconds |
| Started | Jul 02 09:13:21 AM PDT 24 |
| Finished | Jul 02 09:13:32 AM PDT 24 |
| Peak memory | 164944 kb |
| Host | smart-311d39aa-7dda-47cc-9aca-8dea238907cc |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=729975110 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.729975110 |
| Directory | /workspace/39.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.496079583 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 1312970000 ps |
| CPU time | 4.16 seconds |
| Started | Jul 02 09:13:15 AM PDT 24 |
| Finished | Jul 02 09:13:29 AM PDT 24 |
| Peak memory | 164908 kb |
| Host | smart-cdeeda05-81f9-4271-b47d-75b0c6a10d03 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=496079583 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.496079583 |
| Directory | /workspace/4.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.658030574 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 1441530000 ps |
| CPU time | 4.25 seconds |
| Started | Jul 02 09:13:25 AM PDT 24 |
| Finished | Jul 02 09:13:35 AM PDT 24 |
| Peak memory | 164976 kb |
| Host | smart-2bec6507-b38e-4c0b-803f-6e1bbf50f05d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=658030574 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.658030574 |
| Directory | /workspace/40.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.2145549523 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 1522330000 ps |
| CPU time | 5.07 seconds |
| Started | Jul 02 09:13:32 AM PDT 24 |
| Finished | Jul 02 09:13:44 AM PDT 24 |
| Peak memory | 164968 kb |
| Host | smart-d4a69c9b-ed68-4c9b-b8db-beb5595949a5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2145549523 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.2145549523 |
| Directory | /workspace/41.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.2061573652 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 1563390000 ps |
| CPU time | 4.45 seconds |
| Started | Jul 02 09:13:21 AM PDT 24 |
| Finished | Jul 02 09:13:32 AM PDT 24 |
| Peak memory | 164896 kb |
| Host | smart-cc6bc7a5-5a8b-47ac-97f4-a1b321615847 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2061573652 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.2061573652 |
| Directory | /workspace/42.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.3088873709 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 1443790000 ps |
| CPU time | 3.96 seconds |
| Started | Jul 02 09:13:21 AM PDT 24 |
| Finished | Jul 02 09:13:32 AM PDT 24 |
| Peak memory | 164932 kb |
| Host | smart-c8d0ed0f-2274-4ee7-9f27-a2f7cd5e98de |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3088873709 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.3088873709 |
| Directory | /workspace/43.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.3199680788 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 1592310000 ps |
| CPU time | 4.97 seconds |
| Started | Jul 02 09:13:22 AM PDT 24 |
| Finished | Jul 02 09:13:34 AM PDT 24 |
| Peak memory | 164964 kb |
| Host | smart-8c845e0a-8513-4ff3-abb4-5ca33bc66c2c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3199680788 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.3199680788 |
| Directory | /workspace/44.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.1051577089 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 1386450000 ps |
| CPU time | 4.21 seconds |
| Started | Jul 02 09:13:22 AM PDT 24 |
| Finished | Jul 02 09:13:33 AM PDT 24 |
| Peak memory | 164896 kb |
| Host | smart-ebf9f9f2-20ab-4d6e-baa3-bc5d837b62f0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1051577089 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.1051577089 |
| Directory | /workspace/45.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.2218978881 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 1539270000 ps |
| CPU time | 5.18 seconds |
| Started | Jul 02 09:13:20 AM PDT 24 |
| Finished | Jul 02 09:13:34 AM PDT 24 |
| Peak memory | 164908 kb |
| Host | smart-c9053772-98fd-4979-935c-60ccc0966cfb |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2218978881 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.2218978881 |
| Directory | /workspace/46.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.302683517 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 1546790000 ps |
| CPU time | 5.55 seconds |
| Started | Jul 02 09:13:22 AM PDT 24 |
| Finished | Jul 02 09:13:36 AM PDT 24 |
| Peak memory | 164964 kb |
| Host | smart-c05c43da-1a88-44c6-a731-42c753b716fe |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=302683517 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.302683517 |
| Directory | /workspace/47.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.346566785 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 1173930000 ps |
| CPU time | 4.54 seconds |
| Started | Jul 02 09:13:19 AM PDT 24 |
| Finished | Jul 02 09:13:32 AM PDT 24 |
| Peak memory | 164932 kb |
| Host | smart-8a261633-f681-4790-a5eb-ead3b8572899 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=346566785 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.346566785 |
| Directory | /workspace/48.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.4158133327 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 1558170000 ps |
| CPU time | 4.56 seconds |
| Started | Jul 02 09:13:21 AM PDT 24 |
| Finished | Jul 02 09:13:33 AM PDT 24 |
| Peak memory | 164952 kb |
| Host | smart-bb1bbb6a-4749-47dd-9b8c-614e68c868e8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4158133327 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.4158133327 |
| Directory | /workspace/49.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.3768330122 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 1541730000 ps |
| CPU time | 4.15 seconds |
| Started | Jul 02 09:13:14 AM PDT 24 |
| Finished | Jul 02 09:13:28 AM PDT 24 |
| Peak memory | 164972 kb |
| Host | smart-7de188e1-2593-4080-83d9-6135cd379111 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3768330122 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.3768330122 |
| Directory | /workspace/5.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.3423739854 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 1422890000 ps |
| CPU time | 4.29 seconds |
| Started | Jul 02 09:13:20 AM PDT 24 |
| Finished | Jul 02 09:13:32 AM PDT 24 |
| Peak memory | 164920 kb |
| Host | smart-9160b649-af27-4698-982c-31771f08ed6f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3423739854 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.3423739854 |
| Directory | /workspace/6.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.2045813333 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 1531150000 ps |
| CPU time | 5.33 seconds |
| Started | Jul 02 09:13:11 AM PDT 24 |
| Finished | Jul 02 09:13:27 AM PDT 24 |
| Peak memory | 164900 kb |
| Host | smart-1a6b8f25-39cc-426d-adaf-087c236e8f1b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2045813333 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.2045813333 |
| Directory | /workspace/7.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1397459232 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 1463410000 ps |
| CPU time | 4.72 seconds |
| Started | Jul 02 09:13:10 AM PDT 24 |
| Finished | Jul 02 09:13:26 AM PDT 24 |
| Peak memory | 164976 kb |
| Host | smart-7891bfa6-8c86-46f4-b2be-8c6cd2dd6148 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1397459232 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.1397459232 |
| Directory | /workspace/8.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2612898575 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 1435450000 ps |
| CPU time | 5.02 seconds |
| Started | Jul 02 09:13:10 AM PDT 24 |
| Finished | Jul 02 09:13:26 AM PDT 24 |
| Peak memory | 164984 kb |
| Host | smart-f18980d6-14b5-4cc1-9673-c2371da396b5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2612898575 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.2612898575 |
| Directory | /workspace/9.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.808644911 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 1477110000 ps |
| CPU time | 4.49 seconds |
| Started | Jul 02 09:04:18 AM PDT 24 |
| Finished | Jul 02 09:04:29 AM PDT 24 |
| Peak memory | 164884 kb |
| Host | smart-15922bb1-8cd8-4aa1-9531-7c18f850d08b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=808644911 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.808644911 |
| Directory | /workspace/0.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.658464301 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 1624910000 ps |
| CPU time | 5.98 seconds |
| Started | Jul 02 09:04:23 AM PDT 24 |
| Finished | Jul 02 09:04:37 AM PDT 24 |
| Peak memory | 164872 kb |
| Host | smart-f9802fc1-1b80-4048-8863-b2819d51fff8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=658464301 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.658464301 |
| Directory | /workspace/1.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.2810356129 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 1396090000 ps |
| CPU time | 4.78 seconds |
| Started | Jul 02 09:04:24 AM PDT 24 |
| Finished | Jul 02 09:04:36 AM PDT 24 |
| Peak memory | 164960 kb |
| Host | smart-c9a39876-1148-467f-bf89-c5dfc029b9ff |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2810356129 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.2810356129 |
| Directory | /workspace/11.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.951416640 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 1325070000 ps |
| CPU time | 4.19 seconds |
| Started | Jul 02 09:04:27 AM PDT 24 |
| Finished | Jul 02 09:04:37 AM PDT 24 |
| Peak memory | 164876 kb |
| Host | smart-ef5074ef-9d95-4638-9b80-d419e1217773 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=951416640 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.951416640 |
| Directory | /workspace/12.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.2219740213 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 1377390000 ps |
| CPU time | 4.65 seconds |
| Started | Jul 02 09:04:21 AM PDT 24 |
| Finished | Jul 02 09:04:32 AM PDT 24 |
| Peak memory | 164952 kb |
| Host | smart-9f581c1e-f0a2-480e-9e6d-d2bb644a4567 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2219740213 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.2219740213 |
| Directory | /workspace/13.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.3974773573 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 1461390000 ps |
| CPU time | 5.42 seconds |
| Started | Jul 02 09:04:26 AM PDT 24 |
| Finished | Jul 02 09:04:39 AM PDT 24 |
| Peak memory | 164892 kb |
| Host | smart-4b34dd51-acee-4352-b3de-cf30e7bec8a5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3974773573 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.3974773573 |
| Directory | /workspace/14.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.1691777511 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 1580730000 ps |
| CPU time | 5.11 seconds |
| Started | Jul 02 09:04:23 AM PDT 24 |
| Finished | Jul 02 09:04:36 AM PDT 24 |
| Peak memory | 164960 kb |
| Host | smart-28820594-2b3a-4dd5-9857-bde337ea7402 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1691777511 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.1691777511 |
| Directory | /workspace/15.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.536219142 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 1218570000 ps |
| CPU time | 3.5 seconds |
| Started | Jul 02 09:04:22 AM PDT 24 |
| Finished | Jul 02 09:04:31 AM PDT 24 |
| Peak memory | 164832 kb |
| Host | smart-24bf94ce-5d96-4d5d-926f-1cd95e629564 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=536219142 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.536219142 |
| Directory | /workspace/16.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.2852206278 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 1544430000 ps |
| CPU time | 4.92 seconds |
| Started | Jul 02 09:04:24 AM PDT 24 |
| Finished | Jul 02 09:04:37 AM PDT 24 |
| Peak memory | 164952 kb |
| Host | smart-1c35ed6d-2082-47ad-a5dd-09549c57280f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2852206278 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.2852206278 |
| Directory | /workspace/17.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.2895750884 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 1341990000 ps |
| CPU time | 4.12 seconds |
| Started | Jul 02 09:04:23 AM PDT 24 |
| Finished | Jul 02 09:04:33 AM PDT 24 |
| Peak memory | 164964 kb |
| Host | smart-fedf0bf0-0490-4840-a821-d45e58ae0cdd |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2895750884 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.2895750884 |
| Directory | /workspace/18.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.836995625 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 1505930000 ps |
| CPU time | 4.48 seconds |
| Started | Jul 02 09:04:34 AM PDT 24 |
| Finished | Jul 02 09:04:44 AM PDT 24 |
| Peak memory | 164960 kb |
| Host | smart-6eb5d0e3-ba4f-43a0-a5cb-c90986dbb09b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=836995625 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.836995625 |
| Directory | /workspace/19.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.1514538805 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 1208930000 ps |
| CPU time | 4.01 seconds |
| Started | Jul 02 09:04:24 AM PDT 24 |
| Finished | Jul 02 09:04:34 AM PDT 24 |
| Peak memory | 164616 kb |
| Host | smart-075a0a84-8643-4e9a-93fc-4f9daa9ec39c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1514538805 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.1514538805 |
| Directory | /workspace/2.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.2423371638 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 1487910000 ps |
| CPU time | 5.07 seconds |
| Started | Jul 02 09:04:23 AM PDT 24 |
| Finished | Jul 02 09:04:35 AM PDT 24 |
| Peak memory | 164960 kb |
| Host | smart-ce3e48b1-0aef-4e8b-a1d6-f68c2968e623 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2423371638 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.2423371638 |
| Directory | /workspace/20.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.2858720732 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 1458730000 ps |
| CPU time | 3.45 seconds |
| Started | Jul 02 09:04:21 AM PDT 24 |
| Finished | Jul 02 09:04:29 AM PDT 24 |
| Peak memory | 164948 kb |
| Host | smart-fe6ae2f5-db73-4c1a-b9e7-d87e407011ec |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2858720732 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.2858720732 |
| Directory | /workspace/21.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.3236675444 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 1452370000 ps |
| CPU time | 5.1 seconds |
| Started | Jul 02 09:04:21 AM PDT 24 |
| Finished | Jul 02 09:04:33 AM PDT 24 |
| Peak memory | 164904 kb |
| Host | smart-71049a3d-186e-4b70-ae83-45b113b509d6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3236675444 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.3236675444 |
| Directory | /workspace/22.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.830089286 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 1193770000 ps |
| CPU time | 3.92 seconds |
| Started | Jul 02 09:04:23 AM PDT 24 |
| Finished | Jul 02 09:04:33 AM PDT 24 |
| Peak memory | 164960 kb |
| Host | smart-fa517d0e-edcf-42a9-bd2f-3e4cbfc3bd90 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=830089286 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.830089286 |
| Directory | /workspace/23.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.4086945584 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 1371630000 ps |
| CPU time | 3.38 seconds |
| Started | Jul 02 09:04:25 AM PDT 24 |
| Finished | Jul 02 09:04:34 AM PDT 24 |
| Peak memory | 164948 kb |
| Host | smart-354e3325-2e6a-4df6-bdd1-58a9e14508d7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4086945584 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.4086945584 |
| Directory | /workspace/24.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.1646230037 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 1396690000 ps |
| CPU time | 4.62 seconds |
| Started | Jul 02 09:04:25 AM PDT 24 |
| Finished | Jul 02 09:04:36 AM PDT 24 |
| Peak memory | 164944 kb |
| Host | smart-6c179944-c6ba-4016-98bb-ce325a55f176 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1646230037 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.1646230037 |
| Directory | /workspace/25.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.695902964 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 1584390000 ps |
| CPU time | 3.22 seconds |
| Started | Jul 02 09:04:20 AM PDT 24 |
| Finished | Jul 02 09:04:27 AM PDT 24 |
| Peak memory | 164860 kb |
| Host | smart-8c7aacdb-a846-4896-8c34-6815f6080701 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=695902964 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.695902964 |
| Directory | /workspace/26.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.2141810667 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 1329110000 ps |
| CPU time | 4.59 seconds |
| Started | Jul 02 09:04:21 AM PDT 24 |
| Finished | Jul 02 09:04:31 AM PDT 24 |
| Peak memory | 164924 kb |
| Host | smart-022c4d9b-33f4-411d-a049-8e4918e3ecef |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2141810667 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.2141810667 |
| Directory | /workspace/27.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.2285364248 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 1496610000 ps |
| CPU time | 4.78 seconds |
| Started | Jul 02 09:04:33 AM PDT 24 |
| Finished | Jul 02 09:04:45 AM PDT 24 |
| Peak memory | 164952 kb |
| Host | smart-1b11cb8c-e3d2-4d23-a189-95a0128de035 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2285364248 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.2285364248 |
| Directory | /workspace/28.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.3531717769 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 1479870000 ps |
| CPU time | 4.42 seconds |
| Started | Jul 02 09:04:25 AM PDT 24 |
| Finished | Jul 02 09:04:37 AM PDT 24 |
| Peak memory | 164880 kb |
| Host | smart-e70fbf6a-fa92-4112-8b71-a2065c7a5f0a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3531717769 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.3531717769 |
| Directory | /workspace/29.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.996196674 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 1232730000 ps |
| CPU time | 4.35 seconds |
| Started | Jul 02 09:04:24 AM PDT 24 |
| Finished | Jul 02 09:04:34 AM PDT 24 |
| Peak memory | 164808 kb |
| Host | smart-1d6eb1f8-a810-4eea-a342-eaf0501140c5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=996196674 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.996196674 |
| Directory | /workspace/3.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.1975728386 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 1329630000 ps |
| CPU time | 4.34 seconds |
| Started | Jul 02 09:04:24 AM PDT 24 |
| Finished | Jul 02 09:04:35 AM PDT 24 |
| Peak memory | 164944 kb |
| Host | smart-ab357d6e-881c-4080-be3a-26fa6fb3a326 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1975728386 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.1975728386 |
| Directory | /workspace/30.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.967875225 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 1544150000 ps |
| CPU time | 4.91 seconds |
| Started | Jul 02 09:04:23 AM PDT 24 |
| Finished | Jul 02 09:04:36 AM PDT 24 |
| Peak memory | 164960 kb |
| Host | smart-deef9a1d-bd2a-4e7d-b883-a4cdc8a00699 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=967875225 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.967875225 |
| Directory | /workspace/31.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.1873031263 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 1638770000 ps |
| CPU time | 4.84 seconds |
| Started | Jul 02 09:04:22 AM PDT 24 |
| Finished | Jul 02 09:04:34 AM PDT 24 |
| Peak memory | 164904 kb |
| Host | smart-521a0373-3ead-4a55-9e4a-2bc0f4f40729 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1873031263 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.1873031263 |
| Directory | /workspace/32.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.3156743604 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 1478390000 ps |
| CPU time | 4.31 seconds |
| Started | Jul 02 09:04:22 AM PDT 24 |
| Finished | Jul 02 09:04:33 AM PDT 24 |
| Peak memory | 164804 kb |
| Host | smart-5b8898d1-bdb3-4374-99bf-d57a464dd824 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3156743604 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.3156743604 |
| Directory | /workspace/33.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.1932610347 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 1538010000 ps |
| CPU time | 5.13 seconds |
| Started | Jul 02 09:04:25 AM PDT 24 |
| Finished | Jul 02 09:04:37 AM PDT 24 |
| Peak memory | 164952 kb |
| Host | smart-e1100a8f-6b4d-4939-b310-29c3d3504acc |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1932610347 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.1932610347 |
| Directory | /workspace/34.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.933511498 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 1502230000 ps |
| CPU time | 3.85 seconds |
| Started | Jul 02 09:04:23 AM PDT 24 |
| Finished | Jul 02 09:04:32 AM PDT 24 |
| Peak memory | 164920 kb |
| Host | smart-6fc6c684-b9f6-4e37-9447-6ed97e8a9fa1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=933511498 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.933511498 |
| Directory | /workspace/35.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.3313075866 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 1482210000 ps |
| CPU time | 4.89 seconds |
| Started | Jul 02 09:04:34 AM PDT 24 |
| Finished | Jul 02 09:04:45 AM PDT 24 |
| Peak memory | 164964 kb |
| Host | smart-a1a02af2-4e95-4fac-8fe8-b3cb7c600135 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3313075866 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.3313075866 |
| Directory | /workspace/36.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.119895951 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 1350350000 ps |
| CPU time | 3.74 seconds |
| Started | Jul 02 09:04:26 AM PDT 24 |
| Finished | Jul 02 09:04:35 AM PDT 24 |
| Peak memory | 164948 kb |
| Host | smart-1f94c541-5d5c-44be-964a-3c2c20565085 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=119895951 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.119895951 |
| Directory | /workspace/37.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.3808958931 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 1413050000 ps |
| CPU time | 3.73 seconds |
| Started | Jul 02 09:04:26 AM PDT 24 |
| Finished | Jul 02 09:04:35 AM PDT 24 |
| Peak memory | 164928 kb |
| Host | smart-e9c5ddf2-3bdb-4371-8d61-d56205fcbf79 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3808958931 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.3808958931 |
| Directory | /workspace/38.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.69582171 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 1577570000 ps |
| CPU time | 5.15 seconds |
| Started | Jul 02 09:04:27 AM PDT 24 |
| Finished | Jul 02 09:04:39 AM PDT 24 |
| Peak memory | 164852 kb |
| Host | smart-b62ca549-d6e3-4eea-8399-bcd0f2fcf20d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=69582171 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.69582171 |
| Directory | /workspace/39.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.72831800 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 1619790000 ps |
| CPU time | 5.22 seconds |
| Started | Jul 02 09:04:25 AM PDT 24 |
| Finished | Jul 02 09:04:37 AM PDT 24 |
| Peak memory | 164900 kb |
| Host | smart-6dd8c391-45c1-423e-9260-dadcffe4e394 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=72831800 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.72831800 |
| Directory | /workspace/4.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.3534344023 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 1507890000 ps |
| CPU time | 5.89 seconds |
| Started | Jul 02 09:04:23 AM PDT 24 |
| Finished | Jul 02 09:04:37 AM PDT 24 |
| Peak memory | 164960 kb |
| Host | smart-1d3b4e9a-9d47-4e57-9533-9eb86593a946 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3534344023 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.3534344023 |
| Directory | /workspace/40.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.2892410057 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 1589150000 ps |
| CPU time | 4.29 seconds |
| Started | Jul 02 09:04:29 AM PDT 24 |
| Finished | Jul 02 09:04:39 AM PDT 24 |
| Peak memory | 164952 kb |
| Host | smart-7feea8d3-8101-4d50-aeee-efbbe22f1ac0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2892410057 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.2892410057 |
| Directory | /workspace/41.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.2930724429 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 1609870000 ps |
| CPU time | 5.35 seconds |
| Started | Jul 02 09:04:26 AM PDT 24 |
| Finished | Jul 02 09:04:40 AM PDT 24 |
| Peak memory | 164956 kb |
| Host | smart-fa80c32e-710c-49f5-bb83-3e4fcd31d847 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2930724429 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.2930724429 |
| Directory | /workspace/42.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.907957001 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 1042670000 ps |
| CPU time | 2.99 seconds |
| Started | Jul 02 09:04:46 AM PDT 24 |
| Finished | Jul 02 09:04:53 AM PDT 24 |
| Peak memory | 164968 kb |
| Host | smart-8fe9871a-7144-4dfd-8109-6d385ba03678 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=907957001 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.907957001 |
| Directory | /workspace/43.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.2166024734 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 1577750000 ps |
| CPU time | 4.75 seconds |
| Started | Jul 02 09:04:26 AM PDT 24 |
| Finished | Jul 02 09:04:38 AM PDT 24 |
| Peak memory | 164952 kb |
| Host | smart-2ed228c2-e995-4d34-a64a-5ee2bf2d024a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2166024734 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.2166024734 |
| Directory | /workspace/44.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.2351499751 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 1491710000 ps |
| CPU time | 4.71 seconds |
| Started | Jul 02 09:04:25 AM PDT 24 |
| Finished | Jul 02 09:04:36 AM PDT 24 |
| Peak memory | 164892 kb |
| Host | smart-7d5d69d9-799e-4a19-b7af-5b71b7bfce63 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2351499751 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.2351499751 |
| Directory | /workspace/45.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.3774366547 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 1405410000 ps |
| CPU time | 4.37 seconds |
| Started | Jul 02 09:04:24 AM PDT 24 |
| Finished | Jul 02 09:04:35 AM PDT 24 |
| Peak memory | 164976 kb |
| Host | smart-2fbb81b5-4dc6-4aa5-9c7c-224acbe55c77 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3774366547 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.3774366547 |
| Directory | /workspace/46.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.932067863 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 1371930000 ps |
| CPU time | 5.31 seconds |
| Started | Jul 02 09:04:26 AM PDT 24 |
| Finished | Jul 02 09:04:38 AM PDT 24 |
| Peak memory | 164856 kb |
| Host | smart-427acc0c-226a-41f1-85a2-8209069a3354 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=932067863 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.932067863 |
| Directory | /workspace/47.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.1897368031 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 1141830000 ps |
| CPU time | 3.36 seconds |
| Started | Jul 02 09:04:26 AM PDT 24 |
| Finished | Jul 02 09:04:34 AM PDT 24 |
| Peak memory | 164940 kb |
| Host | smart-fac8bbc4-ad95-43d8-b980-dfd4c3566c2c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1897368031 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.1897368031 |
| Directory | /workspace/48.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.2135925110 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 1522230000 ps |
| CPU time | 4.26 seconds |
| Started | Jul 02 09:04:23 AM PDT 24 |
| Finished | Jul 02 09:04:33 AM PDT 24 |
| Peak memory | 164932 kb |
| Host | smart-847fd817-f1ff-449a-a406-2e48940a182e |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2135925110 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.2135925110 |
| Directory | /workspace/49.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.2455627314 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 1338630000 ps |
| CPU time | 4.3 seconds |
| Started | Jul 02 09:04:24 AM PDT 24 |
| Finished | Jul 02 09:04:35 AM PDT 24 |
| Peak memory | 164620 kb |
| Host | smart-35b1a11c-3512-41e4-9686-d0ea5bdb9fbe |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2455627314 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.2455627314 |
| Directory | /workspace/5.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.170206008 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 1585930000 ps |
| CPU time | 5.26 seconds |
| Started | Jul 02 09:04:25 AM PDT 24 |
| Finished | Jul 02 09:04:38 AM PDT 24 |
| Peak memory | 164872 kb |
| Host | smart-84f42e7d-aa81-43f8-9f59-be13a5226177 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=170206008 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.170206008 |
| Directory | /workspace/6.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.2526259429 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 1524390000 ps |
| CPU time | 4.99 seconds |
| Started | Jul 02 09:04:34 AM PDT 24 |
| Finished | Jul 02 09:04:46 AM PDT 24 |
| Peak memory | 164956 kb |
| Host | smart-d8e7bfbb-ffb1-408a-a801-bdc45c79c148 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2526259429 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.2526259429 |
| Directory | /workspace/7.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.797015326 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 1517130000 ps |
| CPU time | 4.59 seconds |
| Started | Jul 02 09:04:24 AM PDT 24 |
| Finished | Jul 02 09:04:35 AM PDT 24 |
| Peak memory | 164808 kb |
| Host | smart-4e6c2b9d-dbfe-4371-8047-e64c0293252d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=797015326 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.797015326 |
| Directory | /workspace/8.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.4203250912 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 1557450000 ps |
| CPU time | 4.71 seconds |
| Started | Jul 02 09:04:23 AM PDT 24 |
| Finished | Jul 02 09:04:35 AM PDT 24 |
| Peak memory | 164896 kb |
| Host | smart-1a629a9e-ca17-4863-9762-248f8f71e497 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4203250912 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.4203250912 |
| Directory | /workspace/9.prim_lfsr_gal_smoke/latest |
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