Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.31 100.00 96.55 100.00 100.00 95.00


Total tests in report: 200
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
87.31 87.31 100.00 100.00 96.55 96.55 100.00 100.00 100.00 100.00 40.00 40.00 /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.2700962720
96.81 9.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 87.50 47.50 /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.4199988826
98.31 1.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 95.00 7.50 /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.4256780266

Tests that do not contribute to grading

Name
/workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.3033792756
/workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.1927542503
/workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.747712486
/workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.2246877145
/workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.1641350940
/workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.942866951
/workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.51450950
/workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.753437008
/workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.3388365365
/workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.2885384404
/workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.3547780409
/workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.3737559036
/workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.3303446699
/workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.2649754618
/workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.271878227
/workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.3770470773
/workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.3777718175
/workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.886789051
/workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1223401467
/workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.1666640438
/workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.544586855
/workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.594026471
/workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.1586304948
/workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3440633552
/workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.3450489980
/workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.2703627637
/workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.2302495832
/workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.2173668714
/workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.1341856278
/workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.300480262
/workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.2363596200
/workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.1270115428
/workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.1217014300
/workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.117216571
/workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.3665442655
/workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.1315884767
/workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.2084824861
/workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.1733048106
/workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.3380253001
/workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.1226813778
/workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.1109056570
/workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.160820953
/workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.519222994
/workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.1361505647
/workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.1769401438
/workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.762498483
/workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.2197378024
/workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.2237293590
/workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.3364515428
/workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.305373529
/workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.2062323117
/workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.1863308252
/workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.4219143600
/workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.4166911754
/workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.1731402513
/workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.3216715471
/workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.100400464
/workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.4092711980
/workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.2751551433
/workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.3115703455
/workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.3772519870
/workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.2883725073
/workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3370474805
/workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.3075142988
/workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.1002301720
/workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.1240018376
/workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.2881745994
/workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.809217788
/workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.2223639718
/workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.3742378931
/workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.1513825097
/workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.616270598
/workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.2122042628
/workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.2318023255
/workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.1550618425
/workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.3582164935
/workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.2063512451
/workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.2288501626
/workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.3261274811
/workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.2964555403
/workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3844023770
/workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.919530888
/workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.87073273
/workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.2007217429
/workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.738216648
/workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.403465072
/workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.3284890234
/workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.208488500
/workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.3615059301
/workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.1212932692
/workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.1924456388
/workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1178522233
/workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.3270794647
/workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.105074438
/workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.2488000165
/workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.519986293
/workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.1531395617
/workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.2474726872
/workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.2328690293
/workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.2085882692
/workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.1444100029
/workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.118289408
/workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.3519534899
/workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.95957478
/workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.1320292457
/workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.1835020778
/workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.568182298
/workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.3864988384
/workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.176696475
/workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.1270934295
/workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.1867369499
/workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.1419717694
/workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.1253207332
/workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.1231053743
/workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.1895305056
/workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.2277197094
/workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.2582200862
/workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.1618212992
/workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.3186524744
/workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.3104295048
/workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.1649894088
/workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.1877161729
/workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.2537742203
/workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.158804551
/workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.1082903213
/workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.490477147
/workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.2769349918
/workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.100444714
/workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.2382070916
/workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.2814454724
/workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.2414555086
/workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.2122177329
/workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.1725125243
/workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.1002412001
/workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.1694075087
/workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.2024950413
/workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1179929759
/workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.286378971
/workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.3727215894
/workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.2569951306
/workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.3463456409
/workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.2273129596
/workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.3704213573
/workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.3914577092
/workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.3987963309
/workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.3149104495
/workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.3094879051
/workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.3907024956
/workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.2161617106
/workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.4040290452
/workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.897115484
/workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.2773112426
/workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.1621807030
/workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.575513166
/workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.3029605107
/workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.495213797
/workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.2628429683
/workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.2644886113
/workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.942114677
/workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.2688417251
/workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.2698376596
/workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.2327463577
/workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.760134936
/workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.1935347233
/workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.3887982529
/workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.440461946
/workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.950671286
/workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.4065515562
/workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.4076390681
/workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.1777502240
/workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.347450179
/workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.4006867235
/workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.910187265
/workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.2778547656
/workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.2642905329
/workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.3352009857
/workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.281967528
/workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.1132820977
/workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.1584913907
/workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.1913197589
/workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.1021550698
/workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.1580054422
/workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.2503969708
/workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.2649167193
/workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.2716876731
/workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.695209209
/workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.2360255671
/workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.1565177580
/workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.3025096196
/workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.4042098341
/workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.1167050964
/workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.1397661458
/workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.1496034079
/workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.422952096
/workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.3839642100
/workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.2264867439
/workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.2660391459



Total test records in report: 200
tests.html | tests1.html | tests2.html | tests3.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.2327463577 Jul 03 04:51:08 PM PDT 24 Jul 03 04:51:21 PM PDT 24 1616850000 ps
T2 /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.575513166 Jul 03 04:51:05 PM PDT 24 Jul 03 04:51:16 PM PDT 24 1406270000 ps
T3 /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.897115484 Jul 03 04:51:04 PM PDT 24 Jul 03 04:51:11 PM PDT 24 1562490000 ps
T7 /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.3025096196 Jul 03 04:51:16 PM PDT 24 Jul 03 04:51:27 PM PDT 24 1421990000 ps
T8 /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.2700962720 Jul 03 04:51:10 PM PDT 24 Jul 03 04:51:19 PM PDT 24 1503850000 ps
T9 /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.1132820977 Jul 03 04:51:14 PM PDT 24 Jul 03 04:51:27 PM PDT 24 1580210000 ps
T10 /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.2644886113 Jul 03 04:51:10 PM PDT 24 Jul 03 04:51:21 PM PDT 24 1553830000 ps
T11 /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.1913197589 Jul 03 04:51:13 PM PDT 24 Jul 03 04:51:23 PM PDT 24 1345190000 ps
T12 /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.2628429683 Jul 03 04:51:10 PM PDT 24 Jul 03 04:51:18 PM PDT 24 1253570000 ps
T13 /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.2716876731 Jul 03 04:51:14 PM PDT 24 Jul 03 04:51:23 PM PDT 24 1286630000 ps
T31 /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.760134936 Jul 03 04:51:11 PM PDT 24 Jul 03 04:51:21 PM PDT 24 1525410000 ps
T32 /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.2649167193 Jul 03 04:51:19 PM PDT 24 Jul 03 04:51:31 PM PDT 24 1410870000 ps
T33 /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.695209209 Jul 03 04:51:11 PM PDT 24 Jul 03 04:51:23 PM PDT 24 1472150000 ps
T34 /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.2778547656 Jul 03 04:51:09 PM PDT 24 Jul 03 04:51:18 PM PDT 24 1540510000 ps
T35 /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.1935347233 Jul 03 04:51:11 PM PDT 24 Jul 03 04:51:22 PM PDT 24 1592050000 ps
T36 /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.2773112426 Jul 03 04:51:10 PM PDT 24 Jul 03 04:51:20 PM PDT 24 1324210000 ps
T37 /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.1580054422 Jul 03 04:51:08 PM PDT 24 Jul 03 04:51:18 PM PDT 24 1512430000 ps
T38 /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.2503969708 Jul 03 04:51:10 PM PDT 24 Jul 03 04:51:21 PM PDT 24 1638590000 ps
T39 /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.950671286 Jul 03 04:51:03 PM PDT 24 Jul 03 04:51:12 PM PDT 24 1243310000 ps
T40 /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.3887982529 Jul 03 04:51:07 PM PDT 24 Jul 03 04:51:20 PM PDT 24 1537990000 ps
T41 /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.2264867439 Jul 03 04:51:11 PM PDT 24 Jul 03 04:51:20 PM PDT 24 1372370000 ps
T42 /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.2642905329 Jul 03 04:51:12 PM PDT 24 Jul 03 04:51:21 PM PDT 24 1359630000 ps
T43 /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.3839642100 Jul 03 04:51:08 PM PDT 24 Jul 03 04:51:17 PM PDT 24 1088170000 ps
T44 /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.4042098341 Jul 03 04:51:13 PM PDT 24 Jul 03 04:51:21 PM PDT 24 1308250000 ps
T45 /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.4065515562 Jul 03 04:51:11 PM PDT 24 Jul 03 04:51:19 PM PDT 24 1418310000 ps
T46 /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.1621807030 Jul 03 04:51:11 PM PDT 24 Jul 03 04:51:21 PM PDT 24 1597910000 ps
T47 /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.910187265 Jul 03 04:51:10 PM PDT 24 Jul 03 04:51:22 PM PDT 24 1557770000 ps
T48 /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.1565177580 Jul 03 04:51:24 PM PDT 24 Jul 03 04:51:36 PM PDT 24 1596750000 ps
T49 /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.3029605107 Jul 03 04:51:09 PM PDT 24 Jul 03 04:51:20 PM PDT 24 1442230000 ps
T50 /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.2660391459 Jul 03 04:51:16 PM PDT 24 Jul 03 04:51:27 PM PDT 24 1395910000 ps
T51 /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.942114677 Jul 03 04:51:12 PM PDT 24 Jul 03 04:51:21 PM PDT 24 1116070000 ps
T52 /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.281967528 Jul 03 04:51:06 PM PDT 24 Jul 03 04:51:17 PM PDT 24 1398390000 ps
T53 /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.1496034079 Jul 03 04:51:14 PM PDT 24 Jul 03 04:51:26 PM PDT 24 1598370000 ps
T54 /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.4006867235 Jul 03 04:51:12 PM PDT 24 Jul 03 04:51:25 PM PDT 24 1527290000 ps
T55 /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.1167050964 Jul 03 04:51:15 PM PDT 24 Jul 03 04:51:27 PM PDT 24 1561030000 ps
T56 /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.1397661458 Jul 03 04:51:11 PM PDT 24 Jul 03 04:51:21 PM PDT 24 1460550000 ps
T57 /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.2688417251 Jul 03 04:51:08 PM PDT 24 Jul 03 04:51:16 PM PDT 24 934710000 ps
T58 /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.2698376596 Jul 03 04:51:15 PM PDT 24 Jul 03 04:51:28 PM PDT 24 1546630000 ps
T59 /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.1584913907 Jul 03 04:51:09 PM PDT 24 Jul 03 04:51:20 PM PDT 24 1438610000 ps
T60 /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.3352009857 Jul 03 04:51:10 PM PDT 24 Jul 03 04:51:21 PM PDT 24 1537630000 ps
T61 /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.1777502240 Jul 03 04:51:06 PM PDT 24 Jul 03 04:51:14 PM PDT 24 1453750000 ps
T62 /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.4076390681 Jul 03 04:51:08 PM PDT 24 Jul 03 04:51:15 PM PDT 24 1374770000 ps
T63 /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.495213797 Jul 03 04:51:09 PM PDT 24 Jul 03 04:51:17 PM PDT 24 1350190000 ps
T64 /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.4040290452 Jul 03 04:51:10 PM PDT 24 Jul 03 04:51:23 PM PDT 24 1596090000 ps
T65 /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.422952096 Jul 03 04:51:13 PM PDT 24 Jul 03 04:51:22 PM PDT 24 1281430000 ps
T66 /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.2360255671 Jul 03 04:51:26 PM PDT 24 Jul 03 04:51:38 PM PDT 24 1415710000 ps
T67 /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.1021550698 Jul 03 04:51:16 PM PDT 24 Jul 03 04:51:26 PM PDT 24 1430490000 ps
T68 /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.347450179 Jul 03 04:51:08 PM PDT 24 Jul 03 04:51:17 PM PDT 24 1478970000 ps
T69 /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.2161617106 Jul 03 04:51:09 PM PDT 24 Jul 03 04:51:18 PM PDT 24 1361470000 ps
T70 /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.440461946 Jul 03 04:51:06 PM PDT 24 Jul 03 04:51:18 PM PDT 24 1586810000 ps
T4 /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.51450950 Jul 03 04:51:07 PM PDT 24 Jul 03 05:24:32 PM PDT 24 336410510000 ps
T5 /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.762498483 Jul 03 04:51:07 PM PDT 24 Jul 03 05:26:53 PM PDT 24 336680170000 ps
T6 /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3440633552 Jul 03 04:51:07 PM PDT 24 Jul 03 05:23:09 PM PDT 24 336687110000 ps
T14 /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.300480262 Jul 03 04:51:05 PM PDT 24 Jul 03 05:27:16 PM PDT 24 336668390000 ps
T15 /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.1109056570 Jul 03 04:51:09 PM PDT 24 Jul 03 05:24:19 PM PDT 24 336873170000 ps
T16 /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.3364515428 Jul 03 04:51:08 PM PDT 24 Jul 03 05:17:43 PM PDT 24 337165770000 ps
T17 /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.117216571 Jul 03 04:51:03 PM PDT 24 Jul 03 05:21:25 PM PDT 24 336649170000 ps
T18 /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.4199988826 Jul 03 04:51:06 PM PDT 24 Jul 03 05:22:05 PM PDT 24 336705690000 ps
T19 /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1223401467 Jul 03 04:51:06 PM PDT 24 Jul 03 05:24:27 PM PDT 24 336553270000 ps
T20 /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.3380253001 Jul 03 04:51:08 PM PDT 24 Jul 03 05:20:00 PM PDT 24 336396990000 ps
T71 /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.3777718175 Jul 03 04:51:04 PM PDT 24 Jul 03 05:23:18 PM PDT 24 336614230000 ps
T72 /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.1341856278 Jul 03 04:51:11 PM PDT 24 Jul 03 05:29:37 PM PDT 24 336497570000 ps
T73 /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.1270115428 Jul 03 04:51:04 PM PDT 24 Jul 03 05:20:12 PM PDT 24 336641670000 ps
T74 /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.3547780409 Jul 03 04:51:06 PM PDT 24 Jul 03 05:28:38 PM PDT 24 336526010000 ps
T75 /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.1641350940 Jul 03 04:51:06 PM PDT 24 Jul 03 05:27:15 PM PDT 24 336555030000 ps
T76 /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.1217014300 Jul 03 04:51:09 PM PDT 24 Jul 03 05:17:05 PM PDT 24 336947130000 ps
T77 /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.271878227 Jul 03 04:51:10 PM PDT 24 Jul 03 05:26:03 PM PDT 24 336989350000 ps
T78 /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.1586304948 Jul 03 04:51:08 PM PDT 24 Jul 03 05:21:19 PM PDT 24 336699310000 ps
T79 /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.1226813778 Jul 03 04:51:12 PM PDT 24 Jul 03 05:25:20 PM PDT 24 337085190000 ps
T80 /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.1361505647 Jul 03 04:51:12 PM PDT 24 Jul 03 05:20:55 PM PDT 24 336458170000 ps
T81 /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.942866951 Jul 03 04:51:06 PM PDT 24 Jul 03 05:24:21 PM PDT 24 336941310000 ps
T82 /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.1769401438 Jul 03 04:51:14 PM PDT 24 Jul 03 05:26:12 PM PDT 24 336394470000 ps
T83 /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.160820953 Jul 03 04:51:12 PM PDT 24 Jul 03 05:25:14 PM PDT 24 336612550000 ps
T84 /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.3303446699 Jul 03 04:51:03 PM PDT 24 Jul 03 05:29:54 PM PDT 24 336675450000 ps
T85 /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.3770470773 Jul 03 04:51:12 PM PDT 24 Jul 03 05:25:36 PM PDT 24 336894670000 ps
T86 /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.1315884767 Jul 03 04:51:12 PM PDT 24 Jul 03 05:24:20 PM PDT 24 336991510000 ps
T87 /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.3450489980 Jul 03 04:51:03 PM PDT 24 Jul 03 05:29:38 PM PDT 24 336715950000 ps
T88 /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.519222994 Jul 03 04:51:09 PM PDT 24 Jul 03 05:15:06 PM PDT 24 336757550000 ps
T89 /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.2703627637 Jul 03 04:51:11 PM PDT 24 Jul 03 05:19:49 PM PDT 24 336465990000 ps
T90 /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.2197378024 Jul 03 04:51:03 PM PDT 24 Jul 03 05:29:37 PM PDT 24 336780510000 ps
T91 /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.2302495832 Jul 03 04:51:11 PM PDT 24 Jul 03 05:20:37 PM PDT 24 336520030000 ps
T92 /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.747712486 Jul 03 04:51:06 PM PDT 24 Jul 03 05:23:12 PM PDT 24 336355550000 ps
T93 /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.2885384404 Jul 03 04:50:59 PM PDT 24 Jul 03 05:21:57 PM PDT 24 337017670000 ps
T94 /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.2649754618 Jul 03 04:51:05 PM PDT 24 Jul 03 05:20:10 PM PDT 24 336596270000 ps
T95 /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.3388365365 Jul 03 04:51:14 PM PDT 24 Jul 03 05:26:04 PM PDT 24 336375630000 ps
T96 /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.2246877145 Jul 03 04:51:02 PM PDT 24 Jul 03 05:24:25 PM PDT 24 336549590000 ps
T97 /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.3033792756 Jul 03 04:51:02 PM PDT 24 Jul 03 05:27:14 PM PDT 24 336567370000 ps
T98 /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.1927542503 Jul 03 04:51:06 PM PDT 24 Jul 03 05:29:33 PM PDT 24 336552210000 ps
T99 /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.2084824861 Jul 03 04:51:05 PM PDT 24 Jul 03 05:21:59 PM PDT 24 336873570000 ps
T100 /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.3737559036 Jul 03 04:51:08 PM PDT 24 Jul 03 05:19:57 PM PDT 24 336664670000 ps
T101 /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.2237293590 Jul 03 04:51:07 PM PDT 24 Jul 03 05:29:54 PM PDT 24 336916150000 ps
T102 /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.1666640438 Jul 03 04:51:00 PM PDT 24 Jul 03 05:29:26 PM PDT 24 336568250000 ps
T103 /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.2173668714 Jul 03 04:51:08 PM PDT 24 Jul 03 05:26:01 PM PDT 24 336443950000 ps
T104 /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.3665442655 Jul 03 04:51:12 PM PDT 24 Jul 03 05:25:06 PM PDT 24 336646810000 ps
T105 /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.886789051 Jul 03 04:51:04 PM PDT 24 Jul 03 05:25:44 PM PDT 24 336659590000 ps
T106 /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.544586855 Jul 03 04:51:03 PM PDT 24 Jul 03 05:25:42 PM PDT 24 336788470000 ps
T107 /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.753437008 Jul 03 04:51:11 PM PDT 24 Jul 03 05:19:52 PM PDT 24 336744210000 ps
T108 /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.594026471 Jul 03 04:51:07 PM PDT 24 Jul 03 05:26:58 PM PDT 24 336515750000 ps
T109 /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.1733048106 Jul 03 04:51:02 PM PDT 24 Jul 03 05:21:41 PM PDT 24 337141410000 ps
T110 /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.2363596200 Jul 03 04:51:09 PM PDT 24 Jul 03 05:18:06 PM PDT 24 336981550000 ps
T111 /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.286378971 Jul 03 04:51:16 PM PDT 24 Jul 03 04:51:25 PM PDT 24 1401490000 ps
T112 /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.2273129596 Jul 03 04:51:14 PM PDT 24 Jul 03 04:51:26 PM PDT 24 1441530000 ps
T113 /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.1270934295 Jul 03 04:51:14 PM PDT 24 Jul 03 04:51:24 PM PDT 24 1106790000 ps
T114 /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.3987963309 Jul 03 04:51:11 PM PDT 24 Jul 03 04:51:19 PM PDT 24 1333450000 ps
T115 /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1179929759 Jul 03 04:51:30 PM PDT 24 Jul 03 04:51:41 PM PDT 24 1398050000 ps
T116 /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.1725125243 Jul 03 04:51:11 PM PDT 24 Jul 03 04:51:24 PM PDT 24 1534790000 ps
T117 /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.3519534899 Jul 03 04:51:12 PM PDT 24 Jul 03 04:51:22 PM PDT 24 1341830000 ps
T118 /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.3463456409 Jul 03 04:51:21 PM PDT 24 Jul 03 04:51:30 PM PDT 24 1332930000 ps
T119 /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.1419717694 Jul 03 04:51:17 PM PDT 24 Jul 03 04:51:29 PM PDT 24 1477950000 ps
T120 /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.490477147 Jul 03 04:51:17 PM PDT 24 Jul 03 04:51:27 PM PDT 24 1395810000 ps
T121 /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.2414555086 Jul 03 04:51:31 PM PDT 24 Jul 03 04:51:41 PM PDT 24 1466030000 ps
T122 /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.95957478 Jul 03 04:51:11 PM PDT 24 Jul 03 04:51:19 PM PDT 24 1208210000 ps
T123 /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.1231053743 Jul 03 04:51:15 PM PDT 24 Jul 03 04:51:27 PM PDT 24 1429290000 ps
T124 /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.1649894088 Jul 03 04:51:29 PM PDT 24 Jul 03 04:51:41 PM PDT 24 1436570000 ps
T125 /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.1835020778 Jul 03 04:51:14 PM PDT 24 Jul 03 04:51:24 PM PDT 24 1533710000 ps
T126 /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.2537742203 Jul 03 04:51:15 PM PDT 24 Jul 03 04:51:25 PM PDT 24 1523870000 ps
T127 /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.100444714 Jul 03 04:51:24 PM PDT 24 Jul 03 04:51:33 PM PDT 24 1279910000 ps
T128 /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.3727215894 Jul 03 04:51:18 PM PDT 24 Jul 03 04:51:27 PM PDT 24 1291290000 ps
T129 /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.1002412001 Jul 03 04:51:15 PM PDT 24 Jul 03 04:51:26 PM PDT 24 1595070000 ps
T130 /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.2769349918 Jul 03 04:51:30 PM PDT 24 Jul 03 04:51:41 PM PDT 24 1576670000 ps
T131 /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.3914577092 Jul 03 04:51:12 PM PDT 24 Jul 03 04:51:23 PM PDT 24 1228030000 ps
T132 /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.2328690293 Jul 03 04:51:26 PM PDT 24 Jul 03 04:51:34 PM PDT 24 926350000 ps
T133 /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.568182298 Jul 03 04:51:13 PM PDT 24 Jul 03 04:51:21 PM PDT 24 1309450000 ps
T134 /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.2382070916 Jul 03 04:51:28 PM PDT 24 Jul 03 04:51:37 PM PDT 24 1437910000 ps
T135 /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.1694075087 Jul 03 04:51:18 PM PDT 24 Jul 03 04:51:30 PM PDT 24 1399610000 ps
T136 /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.1253207332 Jul 03 04:51:08 PM PDT 24 Jul 03 04:51:18 PM PDT 24 1519790000 ps
T137 /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.118289408 Jul 03 04:51:17 PM PDT 24 Jul 03 04:51:26 PM PDT 24 1480410000 ps
T138 /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.1444100029 Jul 03 04:51:15 PM PDT 24 Jul 03 04:51:25 PM PDT 24 1157950000 ps
T139 /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.3186524744 Jul 03 04:51:27 PM PDT 24 Jul 03 04:51:35 PM PDT 24 1402570000 ps
T140 /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.3907024956 Jul 03 04:51:20 PM PDT 24 Jul 03 04:51:28 PM PDT 24 1370810000 ps
T141 /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.2122177329 Jul 03 04:51:24 PM PDT 24 Jul 03 04:51:36 PM PDT 24 1564990000 ps
T142 /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.3864988384 Jul 03 04:51:18 PM PDT 24 Jul 03 04:51:28 PM PDT 24 1611930000 ps
T143 /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.2277197094 Jul 03 04:51:15 PM PDT 24 Jul 03 04:51:24 PM PDT 24 1345330000 ps
T144 /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.1320292457 Jul 03 04:51:17 PM PDT 24 Jul 03 04:51:26 PM PDT 24 1578090000 ps
T145 /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.2024950413 Jul 03 04:51:35 PM PDT 24 Jul 03 04:51:46 PM PDT 24 1518110000 ps
T146 /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.2569951306 Jul 03 04:51:13 PM PDT 24 Jul 03 04:51:26 PM PDT 24 1604350000 ps
T147 /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.3094879051 Jul 03 04:51:11 PM PDT 24 Jul 03 04:51:24 PM PDT 24 1507710000 ps
T148 /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.2582200862 Jul 03 04:51:29 PM PDT 24 Jul 03 04:51:37 PM PDT 24 1561310000 ps
T149 /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.158804551 Jul 03 04:51:24 PM PDT 24 Jul 03 04:51:34 PM PDT 24 1546490000 ps
T150 /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.1877161729 Jul 03 04:51:10 PM PDT 24 Jul 03 04:51:20 PM PDT 24 1544070000 ps
T151 /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.3104295048 Jul 03 04:51:29 PM PDT 24 Jul 03 04:51:40 PM PDT 24 1493710000 ps
T152 /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.176696475 Jul 03 04:51:11 PM PDT 24 Jul 03 04:51:20 PM PDT 24 1254250000 ps
T153 /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.1618212992 Jul 03 04:51:39 PM PDT 24 Jul 03 04:51:50 PM PDT 24 1565770000 ps
T154 /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.1867369499 Jul 03 04:51:17 PM PDT 24 Jul 03 04:51:25 PM PDT 24 1468450000 ps
T155 /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.2085882692 Jul 03 04:51:17 PM PDT 24 Jul 03 04:51:24 PM PDT 24 1472310000 ps
T156 /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.1082903213 Jul 03 04:51:13 PM PDT 24 Jul 03 04:51:25 PM PDT 24 1507670000 ps
T157 /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.1895305056 Jul 03 04:51:11 PM PDT 24 Jul 03 04:51:19 PM PDT 24 1537970000 ps
T158 /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.3149104495 Jul 03 04:51:16 PM PDT 24 Jul 03 04:51:24 PM PDT 24 1243390000 ps
T159 /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.2814454724 Jul 03 04:51:15 PM PDT 24 Jul 03 04:51:24 PM PDT 24 1484070000 ps
T160 /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.3704213573 Jul 03 04:51:19 PM PDT 24 Jul 03 04:51:29 PM PDT 24 1512270000 ps
T21 /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.403465072 Jul 03 04:47:03 PM PDT 24 Jul 03 05:22:38 PM PDT 24 336687910000 ps
T22 /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.105074438 Jul 03 04:46:59 PM PDT 24 Jul 03 05:25:22 PM PDT 24 336880130000 ps
T23 /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.2964555403 Jul 03 04:47:02 PM PDT 24 Jul 03 05:25:24 PM PDT 24 336754950000 ps
T24 /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.919530888 Jul 03 04:47:00 PM PDT 24 Jul 03 05:18:00 PM PDT 24 336505490000 ps
T25 /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.2007217429 Jul 03 04:46:59 PM PDT 24 Jul 03 05:15:06 PM PDT 24 336472110000 ps
T26 /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.2881745994 Jul 03 04:46:57 PM PDT 24 Jul 03 05:20:39 PM PDT 24 337014710000 ps
T27 /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.3075142988 Jul 03 04:47:00 PM PDT 24 Jul 03 05:25:17 PM PDT 24 336484390000 ps
T28 /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.4256780266 Jul 03 04:46:54 PM PDT 24 Jul 03 05:16:21 PM PDT 24 336418530000 ps
T29 /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.616270598 Jul 03 04:47:00 PM PDT 24 Jul 03 05:20:50 PM PDT 24 336650770000 ps
T30 /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.519986293 Jul 03 04:47:03 PM PDT 24 Jul 03 05:21:50 PM PDT 24 336840770000 ps
T161 /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.3582164935 Jul 03 04:47:03 PM PDT 24 Jul 03 05:15:32 PM PDT 24 336920330000 ps
T162 /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.305373529 Jul 03 04:46:58 PM PDT 24 Jul 03 05:20:28 PM PDT 24 336957890000 ps
T163 /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.2318023255 Jul 03 04:47:02 PM PDT 24 Jul 03 05:19:10 PM PDT 24 337070210000 ps
T164 /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.4092711980 Jul 03 04:46:51 PM PDT 24 Jul 03 05:11:34 PM PDT 24 336837170000 ps
T165 /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.1240018376 Jul 03 04:47:03 PM PDT 24 Jul 03 05:21:27 PM PDT 24 336723070000 ps
T166 /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.2488000165 Jul 03 04:47:00 PM PDT 24 Jul 03 05:21:08 PM PDT 24 336688810000 ps
T167 /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.87073273 Jul 03 04:46:55 PM PDT 24 Jul 03 05:17:53 PM PDT 24 336545310000 ps
T168 /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1178522233 Jul 03 04:47:04 PM PDT 24 Jul 03 05:22:46 PM PDT 24 336663410000 ps
T169 /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3844023770 Jul 03 04:47:01 PM PDT 24 Jul 03 05:17:02 PM PDT 24 336369870000 ps
T170 /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.1924456388 Jul 03 04:47:02 PM PDT 24 Jul 03 05:14:48 PM PDT 24 336510550000 ps
T171 /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.1002301720 Jul 03 04:46:57 PM PDT 24 Jul 03 05:16:52 PM PDT 24 336949110000 ps
T172 /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.1212932692 Jul 03 04:47:01 PM PDT 24 Jul 03 05:13:47 PM PDT 24 336680170000 ps
T173 /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.3270794647 Jul 03 04:47:00 PM PDT 24 Jul 03 05:17:39 PM PDT 24 336865770000 ps
T174 /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.1513825097 Jul 03 04:47:01 PM PDT 24 Jul 03 05:14:49 PM PDT 24 336521890000 ps
T175 /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.100400464 Jul 03 04:46:53 PM PDT 24 Jul 03 05:14:51 PM PDT 24 336557010000 ps
T176 /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.2062323117 Jul 03 04:46:56 PM PDT 24 Jul 03 05:24:36 PM PDT 24 336478570000 ps
T177 /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.1550618425 Jul 03 04:47:01 PM PDT 24 Jul 03 05:14:58 PM PDT 24 336948690000 ps
T178 /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.1863308252 Jul 03 04:46:57 PM PDT 24 Jul 03 05:20:32 PM PDT 24 337067490000 ps
T179 /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.2751551433 Jul 03 04:46:55 PM PDT 24 Jul 03 05:15:43 PM PDT 24 337109910000 ps
T180 /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.2883725073 Jul 03 04:47:01 PM PDT 24 Jul 03 05:19:56 PM PDT 24 336880390000 ps
T181 /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.3115703455 Jul 03 04:47:00 PM PDT 24 Jul 03 05:20:55 PM PDT 24 336942110000 ps
T182 /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.2063512451 Jul 03 04:47:00 PM PDT 24 Jul 03 05:13:53 PM PDT 24 336599030000 ps
T183 /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.3615059301 Jul 03 04:47:02 PM PDT 24 Jul 03 05:17:29 PM PDT 24 336645010000 ps
T184 /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3370474805 Jul 03 04:47:01 PM PDT 24 Jul 03 05:21:11 PM PDT 24 336719130000 ps
T185 /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.2122042628 Jul 03 04:47:00 PM PDT 24 Jul 03 05:15:56 PM PDT 24 336453450000 ps
T186 /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.1531395617 Jul 03 04:46:54 PM PDT 24 Jul 03 05:17:01 PM PDT 24 336456290000 ps
T187 /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.3261274811 Jul 03 04:46:59 PM PDT 24 Jul 03 05:16:31 PM PDT 24 336496790000 ps
T188 /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.208488500 Jul 03 04:47:03 PM PDT 24 Jul 03 05:13:46 PM PDT 24 336668590000 ps
T189 /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.738216648 Jul 03 04:46:58 PM PDT 24 Jul 03 05:16:47 PM PDT 24 336627510000 ps
T190 /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.4166911754 Jul 03 04:47:01 PM PDT 24 Jul 03 05:20:47 PM PDT 24 336672190000 ps
T191 /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.2288501626 Jul 03 04:46:58 PM PDT 24 Jul 03 05:21:57 PM PDT 24 337014490000 ps
T192 /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.3772519870 Jul 03 04:47:02 PM PDT 24 Jul 03 05:22:45 PM PDT 24 337105370000 ps
T193 /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.1731402513 Jul 03 04:47:00 PM PDT 24 Jul 03 05:25:27 PM PDT 24 337075150000 ps
T194 /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.809217788 Jul 03 04:46:54 PM PDT 24 Jul 03 05:17:10 PM PDT 24 336811350000 ps
T195 /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.2223639718 Jul 03 04:47:03 PM PDT 24 Jul 03 05:21:53 PM PDT 24 337049330000 ps
T196 /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.3284890234 Jul 03 04:46:59 PM PDT 24 Jul 03 05:18:09 PM PDT 24 336877390000 ps
T197 /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.2474726872 Jul 03 04:47:00 PM PDT 24 Jul 03 05:25:21 PM PDT 24 336522430000 ps
T198 /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.3742378931 Jul 03 04:47:01 PM PDT 24 Jul 03 05:21:14 PM PDT 24 336489310000 ps
T199 /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.3216715471 Jul 03 04:47:00 PM PDT 24 Jul 03 05:25:22 PM PDT 24 336698930000 ps
T200 /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.4219143600 Jul 03 04:46:57 PM PDT 24 Jul 03 05:18:03 PM PDT 24 337051550000 ps

Test location /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.2700962720
Short name T8
Test name
Test status
Simulation time 1503850000 ps
CPU time 4.03 seconds
Started Jul 03 04:51:10 PM PDT 24
Finished Jul 03 04:51:19 PM PDT 24
Peak memory 164916 kb
Host smart-563a1248-023a-4235-a8d6-e4485743a555
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2700962720 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.2700962720
Directory /workspace/1.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.4199988826
Short name T18
Test name
Test status
Simulation time 336705690000 ps
CPU time 763.41 seconds
Started Jul 03 04:51:06 PM PDT 24
Finished Jul 03 05:22:05 PM PDT 24
Peak memory 160756 kb
Host smart-79fa06a4-050b-4e78-9269-fee447b7dfc6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4199988826 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.4199988826
Directory /workspace/12.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.4256780266
Short name T28
Test name
Test status
Simulation time 336418530000 ps
CPU time 717.18 seconds
Started Jul 03 04:46:54 PM PDT 24
Finished Jul 03 05:16:21 PM PDT 24
Peak memory 160780 kb
Host smart-422345e6-a6e9-4aa1-aa00-2a3a8b40334f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4256780266 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.4256780266
Directory /workspace/2.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.3033792756
Short name T97
Test name
Test status
Simulation time 336567370000 ps
CPU time 890.82 seconds
Started Jul 03 04:51:02 PM PDT 24
Finished Jul 03 05:27:14 PM PDT 24
Peak memory 160780 kb
Host smart-1961145a-8230-42a4-b2e2-3460fa6db265
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3033792756 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.3033792756
Directory /workspace/0.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.1927542503
Short name T98
Test name
Test status
Simulation time 336552210000 ps
CPU time 912.79 seconds
Started Jul 03 04:51:06 PM PDT 24
Finished Jul 03 05:29:33 PM PDT 24
Peak memory 160768 kb
Host smart-07b2d049-5865-4bfc-8778-8c78e7d2f9c8
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1927542503 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.1927542503
Directory /workspace/1.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.747712486
Short name T92
Test name
Test status
Simulation time 336355550000 ps
CPU time 770.13 seconds
Started Jul 03 04:51:06 PM PDT 24
Finished Jul 03 05:23:12 PM PDT 24
Peak memory 160772 kb
Host smart-6ee18f3f-879e-41f6-ac70-4aa0a95b0a32
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=747712486 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.747712486
Directory /workspace/10.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.2246877145
Short name T96
Test name
Test status
Simulation time 336549590000 ps
CPU time 804.41 seconds
Started Jul 03 04:51:02 PM PDT 24
Finished Jul 03 05:24:25 PM PDT 24
Peak memory 160776 kb
Host smart-c46789bf-b8fc-466e-bf8f-475c047bbecb
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2246877145 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.2246877145
Directory /workspace/11.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.1641350940
Short name T75
Test name
Test status
Simulation time 336555030000 ps
CPU time 859.12 seconds
Started Jul 03 04:51:06 PM PDT 24
Finished Jul 03 05:27:15 PM PDT 24
Peak memory 160760 kb
Host smart-9bf33321-0a3d-4bdb-8d9e-56fc6b4b0a5c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1641350940 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.1641350940
Directory /workspace/13.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.942866951
Short name T81
Test name
Test status
Simulation time 336941310000 ps
CPU time 810.73 seconds
Started Jul 03 04:51:06 PM PDT 24
Finished Jul 03 05:24:21 PM PDT 24
Peak memory 160776 kb
Host smart-aafa6817-cf11-4a09-8436-b1d395b1ca02
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=942866951 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.942866951
Directory /workspace/14.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.51450950
Short name T4
Test name
Test status
Simulation time 336410510000 ps
CPU time 801.47 seconds
Started Jul 03 04:51:07 PM PDT 24
Finished Jul 03 05:24:32 PM PDT 24
Peak memory 160780 kb
Host smart-fd83e2a3-d540-4463-ae18-b985108988bf
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=51450950 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.51450950
Directory /workspace/15.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.753437008
Short name T107
Test name
Test status
Simulation time 336744210000 ps
CPU time 692.07 seconds
Started Jul 03 04:51:11 PM PDT 24
Finished Jul 03 05:19:52 PM PDT 24
Peak memory 160792 kb
Host smart-b4a836be-e129-4cdb-bd4d-566ad74ed012
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=753437008 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.753437008
Directory /workspace/16.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.3388365365
Short name T95
Test name
Test status
Simulation time 336375630000 ps
CPU time 848.14 seconds
Started Jul 03 04:51:14 PM PDT 24
Finished Jul 03 05:26:04 PM PDT 24
Peak memory 160508 kb
Host smart-a0487f36-1894-42d0-93fb-c99c600c9206
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3388365365 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.3388365365
Directory /workspace/17.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.2885384404
Short name T93
Test name
Test status
Simulation time 337017670000 ps
CPU time 759.85 seconds
Started Jul 03 04:50:59 PM PDT 24
Finished Jul 03 05:21:57 PM PDT 24
Peak memory 160756 kb
Host smart-fd6f18db-715b-4eba-a03d-b70e1838a989
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2885384404 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.2885384404
Directory /workspace/18.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.3547780409
Short name T74
Test name
Test status
Simulation time 336526010000 ps
CPU time 898.88 seconds
Started Jul 03 04:51:06 PM PDT 24
Finished Jul 03 05:28:38 PM PDT 24
Peak memory 160772 kb
Host smart-2e70be4b-e109-4cf3-9cb6-6c3f66bf2698
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3547780409 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.3547780409
Directory /workspace/19.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.3737559036
Short name T100
Test name
Test status
Simulation time 336664670000 ps
CPU time 697.06 seconds
Started Jul 03 04:51:08 PM PDT 24
Finished Jul 03 05:19:57 PM PDT 24
Peak memory 160792 kb
Host smart-3988357f-085a-4feb-8025-a9a7be132538
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3737559036 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.3737559036
Directory /workspace/2.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.3303446699
Short name T84
Test name
Test status
Simulation time 336675450000 ps
CPU time 946.69 seconds
Started Jul 03 04:51:03 PM PDT 24
Finished Jul 03 05:29:54 PM PDT 24
Peak memory 160744 kb
Host smart-aa16c884-5f43-4b5b-b675-8ee4cbffa1d0
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3303446699 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.3303446699
Directory /workspace/20.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.2649754618
Short name T94
Test name
Test status
Simulation time 336596270000 ps
CPU time 707.1 seconds
Started Jul 03 04:51:05 PM PDT 24
Finished Jul 03 05:20:10 PM PDT 24
Peak memory 160740 kb
Host smart-754ac332-c7cc-4859-bca0-1f7e34588359
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2649754618 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.2649754618
Directory /workspace/21.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.271878227
Short name T77
Test name
Test status
Simulation time 336989350000 ps
CPU time 845.56 seconds
Started Jul 03 04:51:10 PM PDT 24
Finished Jul 03 05:26:03 PM PDT 24
Peak memory 160756 kb
Host smart-aa9b5937-d785-4a73-8078-b517870205e3
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=271878227 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.271878227
Directory /workspace/22.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.3770470773
Short name T85
Test name
Test status
Simulation time 336894670000 ps
CPU time 845.26 seconds
Started Jul 03 04:51:12 PM PDT 24
Finished Jul 03 05:25:36 PM PDT 24
Peak memory 160660 kb
Host smart-c9224b02-65c6-4ed2-8135-80ec44f2b0df
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3770470773 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.3770470773
Directory /workspace/23.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.3777718175
Short name T71
Test name
Test status
Simulation time 336614230000 ps
CPU time 772.63 seconds
Started Jul 03 04:51:04 PM PDT 24
Finished Jul 03 05:23:18 PM PDT 24
Peak memory 160780 kb
Host smart-bf04ade4-c763-43a2-8033-cb6f599ca481
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3777718175 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.3777718175
Directory /workspace/24.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.886789051
Short name T105
Test name
Test status
Simulation time 336659590000 ps
CPU time 838.14 seconds
Started Jul 03 04:51:04 PM PDT 24
Finished Jul 03 05:25:44 PM PDT 24
Peak memory 160756 kb
Host smart-d8f59745-9846-42b9-b710-166e93111110
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=886789051 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.886789051
Directory /workspace/25.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1223401467
Short name T19
Test name
Test status
Simulation time 336553270000 ps
CPU time 801.66 seconds
Started Jul 03 04:51:06 PM PDT 24
Finished Jul 03 05:24:27 PM PDT 24
Peak memory 160776 kb
Host smart-46fd5f48-2f0a-4f47-baf7-7c2271ba172a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1223401467 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.1223401467
Directory /workspace/26.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.1666640438
Short name T102
Test name
Test status
Simulation time 336568250000 ps
CPU time 904.52 seconds
Started Jul 03 04:51:00 PM PDT 24
Finished Jul 03 05:29:26 PM PDT 24
Peak memory 160772 kb
Host smart-634d8484-b4c6-4683-b0a2-d4cbf5a57e7f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1666640438 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.1666640438
Directory /workspace/27.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.544586855
Short name T106
Test name
Test status
Simulation time 336788470000 ps
CPU time 840.4 seconds
Started Jul 03 04:51:03 PM PDT 24
Finished Jul 03 05:25:42 PM PDT 24
Peak memory 160756 kb
Host smart-871275c1-f833-4e22-8df9-9c1412676292
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=544586855 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.544586855
Directory /workspace/28.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.594026471
Short name T108
Test name
Test status
Simulation time 336515750000 ps
CPU time 849.68 seconds
Started Jul 03 04:51:07 PM PDT 24
Finished Jul 03 05:26:58 PM PDT 24
Peak memory 160756 kb
Host smart-9e5a91a4-b3f3-4f99-92d5-4986f62f49f5
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=594026471 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.594026471
Directory /workspace/29.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.1586304948
Short name T78
Test name
Test status
Simulation time 336699310000 ps
CPU time 735.11 seconds
Started Jul 03 04:51:08 PM PDT 24
Finished Jul 03 05:21:19 PM PDT 24
Peak memory 160752 kb
Host smart-0fd6b7bd-c7f0-411e-b7fb-712d75fad380
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1586304948 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.1586304948
Directory /workspace/3.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3440633552
Short name T6
Test name
Test status
Simulation time 336687110000 ps
CPU time 767.06 seconds
Started Jul 03 04:51:07 PM PDT 24
Finished Jul 03 05:23:09 PM PDT 24
Peak memory 160780 kb
Host smart-4821796f-1760-4895-b843-c0957c25e079
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3440633552 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.3440633552
Directory /workspace/30.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.3450489980
Short name T87
Test name
Test status
Simulation time 336715950000 ps
CPU time 917.9 seconds
Started Jul 03 04:51:03 PM PDT 24
Finished Jul 03 05:29:38 PM PDT 24
Peak memory 160776 kb
Host smart-7a70e529-d6ee-475f-ac3a-04079f57c634
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3450489980 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.3450489980
Directory /workspace/31.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.2703627637
Short name T89
Test name
Test status
Simulation time 336465990000 ps
CPU time 690.94 seconds
Started Jul 03 04:51:11 PM PDT 24
Finished Jul 03 05:19:49 PM PDT 24
Peak memory 160796 kb
Host smart-7014a9f0-42a0-4339-ba7a-da3888d2dd0d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2703627637 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.2703627637
Directory /workspace/32.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.2302495832
Short name T91
Test name
Test status
Simulation time 336520030000 ps
CPU time 716.45 seconds
Started Jul 03 04:51:11 PM PDT 24
Finished Jul 03 05:20:37 PM PDT 24
Peak memory 160776 kb
Host smart-55e47da3-137e-4e1a-b550-100d4d7b725e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2302495832 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.2302495832
Directory /workspace/33.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.2173668714
Short name T103
Test name
Test status
Simulation time 336443950000 ps
CPU time 837.93 seconds
Started Jul 03 04:51:08 PM PDT 24
Finished Jul 03 05:26:01 PM PDT 24
Peak memory 160792 kb
Host smart-df9ed872-e333-4766-8283-4c84f04613d4
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2173668714 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.2173668714
Directory /workspace/34.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.1341856278
Short name T72
Test name
Test status
Simulation time 336497570000 ps
CPU time 912.05 seconds
Started Jul 03 04:51:11 PM PDT 24
Finished Jul 03 05:29:37 PM PDT 24
Peak memory 160776 kb
Host smart-25b68fc8-a64d-4e35-8fb3-e4f57f107829
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1341856278 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.1341856278
Directory /workspace/35.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.300480262
Short name T14
Test name
Test status
Simulation time 336668390000 ps
CPU time 889.74 seconds
Started Jul 03 04:51:05 PM PDT 24
Finished Jul 03 05:27:16 PM PDT 24
Peak memory 160780 kb
Host smart-5a3fecb5-c9c3-43b8-87bb-3d4ba7d4201c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=300480262 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.300480262
Directory /workspace/36.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.2363596200
Short name T110
Test name
Test status
Simulation time 336981550000 ps
CPU time 649.47 seconds
Started Jul 03 04:51:09 PM PDT 24
Finished Jul 03 05:18:06 PM PDT 24
Peak memory 160764 kb
Host smart-a9a17111-556b-402b-8215-bb58e21a31c6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2363596200 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.2363596200
Directory /workspace/37.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.1270115428
Short name T73
Test name
Test status
Simulation time 336641670000 ps
CPU time 705.67 seconds
Started Jul 03 04:51:04 PM PDT 24
Finished Jul 03 05:20:12 PM PDT 24
Peak memory 160780 kb
Host smart-475a7c9f-b23e-4e94-9dbc-fbec0a3fea93
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1270115428 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.1270115428
Directory /workspace/38.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.1217014300
Short name T76
Test name
Test status
Simulation time 336947130000 ps
CPU time 607.04 seconds
Started Jul 03 04:51:09 PM PDT 24
Finished Jul 03 05:17:05 PM PDT 24
Peak memory 160788 kb
Host smart-113f7ffc-04e2-49e4-97d8-46b51f9f6f4e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1217014300 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.1217014300
Directory /workspace/39.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.117216571
Short name T17
Test name
Test status
Simulation time 336649170000 ps
CPU time 736.96 seconds
Started Jul 03 04:51:03 PM PDT 24
Finished Jul 03 05:21:25 PM PDT 24
Peak memory 160788 kb
Host smart-fa23789d-53d8-45d4-95fd-76bc8a0545f2
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=117216571 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.117216571
Directory /workspace/4.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.3665442655
Short name T104
Test name
Test status
Simulation time 336646810000 ps
CPU time 835.47 seconds
Started Jul 03 04:51:12 PM PDT 24
Finished Jul 03 05:25:06 PM PDT 24
Peak memory 160700 kb
Host smart-c896c673-e10c-4402-911a-14cc3be6e9b6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3665442655 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.3665442655
Directory /workspace/40.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.1315884767
Short name T86
Test name
Test status
Simulation time 336991510000 ps
CPU time 813.44 seconds
Started Jul 03 04:51:12 PM PDT 24
Finished Jul 03 05:24:20 PM PDT 24
Peak memory 160776 kb
Host smart-460d86bd-bb4d-4a67-bb5c-e8e98bd5d13e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1315884767 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.1315884767
Directory /workspace/41.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.2084824861
Short name T99
Test name
Test status
Simulation time 336873570000 ps
CPU time 752.76 seconds
Started Jul 03 04:51:05 PM PDT 24
Finished Jul 03 05:21:59 PM PDT 24
Peak memory 160780 kb
Host smart-a31127d6-7f2d-4c49-a0ef-eb1a35db5b1b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2084824861 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.2084824861
Directory /workspace/42.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.1733048106
Short name T109
Test name
Test status
Simulation time 337141410000 ps
CPU time 750.81 seconds
Started Jul 03 04:51:02 PM PDT 24
Finished Jul 03 05:21:41 PM PDT 24
Peak memory 160756 kb
Host smart-f2403389-1243-497c-b842-3ba77f4f491e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1733048106 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.1733048106
Directory /workspace/43.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.3380253001
Short name T20
Test name
Test status
Simulation time 336396990000 ps
CPU time 704.11 seconds
Started Jul 03 04:51:08 PM PDT 24
Finished Jul 03 05:20:00 PM PDT 24
Peak memory 160720 kb
Host smart-eeda3c38-d73b-4b8f-b3ea-3540f59444d5
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3380253001 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.3380253001
Directory /workspace/44.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.1226813778
Short name T79
Test name
Test status
Simulation time 337085190000 ps
CPU time 839.16 seconds
Started Jul 03 04:51:12 PM PDT 24
Finished Jul 03 05:25:20 PM PDT 24
Peak memory 160700 kb
Host smart-d0a3178d-85d8-4c5d-9513-e84252479ba1
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1226813778 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.1226813778
Directory /workspace/45.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.1109056570
Short name T15
Test name
Test status
Simulation time 336873170000 ps
CPU time 813.41 seconds
Started Jul 03 04:51:09 PM PDT 24
Finished Jul 03 05:24:19 PM PDT 24
Peak memory 160780 kb
Host smart-81c43f4c-5291-4a2f-97df-3413a55285c7
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1109056570 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.1109056570
Directory /workspace/46.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.160820953
Short name T83
Test name
Test status
Simulation time 336612550000 ps
CPU time 839.39 seconds
Started Jul 03 04:51:12 PM PDT 24
Finished Jul 03 05:25:14 PM PDT 24
Peak memory 160776 kb
Host smart-a6ed842e-d502-4fba-a79c-c1967b3c5ecc
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=160820953 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.160820953
Directory /workspace/47.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.519222994
Short name T88
Test name
Test status
Simulation time 336757550000 ps
CPU time 572.39 seconds
Started Jul 03 04:51:09 PM PDT 24
Finished Jul 03 05:15:06 PM PDT 24
Peak memory 160680 kb
Host smart-ed6ea310-3740-4ae2-9130-387aee2cb60e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=519222994 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.519222994
Directory /workspace/48.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.1361505647
Short name T80
Test name
Test status
Simulation time 336458170000 ps
CPU time 719.83 seconds
Started Jul 03 04:51:12 PM PDT 24
Finished Jul 03 05:20:55 PM PDT 24
Peak memory 160784 kb
Host smart-eff33c94-7610-42dd-bf00-0015b418b335
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1361505647 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.1361505647
Directory /workspace/49.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.1769401438
Short name T82
Test name
Test status
Simulation time 336394470000 ps
CPU time 855.46 seconds
Started Jul 03 04:51:14 PM PDT 24
Finished Jul 03 05:26:12 PM PDT 24
Peak memory 160656 kb
Host smart-271493fb-5c0e-49bf-814b-08967569dee0
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1769401438 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.1769401438
Directory /workspace/5.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.762498483
Short name T5
Test name
Test status
Simulation time 336680170000 ps
CPU time 851.86 seconds
Started Jul 03 04:51:07 PM PDT 24
Finished Jul 03 05:26:53 PM PDT 24
Peak memory 160756 kb
Host smart-5fe46589-307a-432d-8872-553befbb882e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=762498483 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.762498483
Directory /workspace/6.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.2197378024
Short name T90
Test name
Test status
Simulation time 336780510000 ps
CPU time 918.68 seconds
Started Jul 03 04:51:03 PM PDT 24
Finished Jul 03 05:29:37 PM PDT 24
Peak memory 160768 kb
Host smart-a3fddede-1a36-40be-b24f-d0fbe0855972
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2197378024 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.2197378024
Directory /workspace/7.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.2237293590
Short name T101
Test name
Test status
Simulation time 336916150000 ps
CPU time 945.17 seconds
Started Jul 03 04:51:07 PM PDT 24
Finished Jul 03 05:29:54 PM PDT 24
Peak memory 160736 kb
Host smart-e3eb3b32-6d2e-4706-a049-92f89ffb9b79
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2237293590 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.2237293590
Directory /workspace/8.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.3364515428
Short name T16
Test name
Test status
Simulation time 337165770000 ps
CPU time 629.88 seconds
Started Jul 03 04:51:08 PM PDT 24
Finished Jul 03 05:17:43 PM PDT 24
Peak memory 160772 kb
Host smart-2707fa5d-85f3-4583-9240-e48f7ad8dd3a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3364515428 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.3364515428
Directory /workspace/9.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.305373529
Short name T162
Test name
Test status
Simulation time 336957890000 ps
CPU time 812.79 seconds
Started Jul 03 04:46:58 PM PDT 24
Finished Jul 03 05:20:28 PM PDT 24
Peak memory 160776 kb
Host smart-37c18519-75d3-4a1f-a6a9-6d49965cf61d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=305373529 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.305373529
Directory /workspace/0.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.2062323117
Short name T176
Test name
Test status
Simulation time 336478570000 ps
CPU time 915.78 seconds
Started Jul 03 04:46:56 PM PDT 24
Finished Jul 03 05:24:36 PM PDT 24
Peak memory 160740 kb
Host smart-97c47338-b2ad-4be8-8992-16cb9f18c55d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2062323117 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.2062323117
Directory /workspace/1.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.1863308252
Short name T178
Test name
Test status
Simulation time 337067490000 ps
CPU time 816.49 seconds
Started Jul 03 04:46:57 PM PDT 24
Finished Jul 03 05:20:32 PM PDT 24
Peak memory 160780 kb
Host smart-c9b30332-6e22-4842-8fa2-f1f59528f098
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1863308252 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.1863308252
Directory /workspace/10.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.4219143600
Short name T200
Test name
Test status
Simulation time 337051550000 ps
CPU time 762.16 seconds
Started Jul 03 04:46:57 PM PDT 24
Finished Jul 03 05:18:03 PM PDT 24
Peak memory 160788 kb
Host smart-65e10e1d-d145-4023-ab34-4accd4682369
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4219143600 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.4219143600
Directory /workspace/11.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.4166911754
Short name T190
Test name
Test status
Simulation time 336672190000 ps
CPU time 813.8 seconds
Started Jul 03 04:47:01 PM PDT 24
Finished Jul 03 05:20:47 PM PDT 24
Peak memory 160688 kb
Host smart-cc38f850-594c-4adf-bfe1-677b441f4453
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4166911754 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.4166911754
Directory /workspace/12.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.1731402513
Short name T193
Test name
Test status
Simulation time 337075150000 ps
CPU time 936.63 seconds
Started Jul 03 04:47:00 PM PDT 24
Finished Jul 03 05:25:27 PM PDT 24
Peak memory 160640 kb
Host smart-68512304-a3f5-4d97-9b90-692d6af6c95f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1731402513 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.1731402513
Directory /workspace/13.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.3216715471
Short name T199
Test name
Test status
Simulation time 336698930000 ps
CPU time 925.45 seconds
Started Jul 03 04:47:00 PM PDT 24
Finished Jul 03 05:25:22 PM PDT 24
Peak memory 160640 kb
Host smart-efeacfda-7531-4bf1-8038-87f97583b0c0
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3216715471 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.3216715471
Directory /workspace/14.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.100400464
Short name T175
Test name
Test status
Simulation time 336557010000 ps
CPU time 680.57 seconds
Started Jul 03 04:46:53 PM PDT 24
Finished Jul 03 05:14:51 PM PDT 24
Peak memory 160780 kb
Host smart-0f42bd8a-f9c4-4452-a7aa-342a01080cff
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=100400464 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.100400464
Directory /workspace/15.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.4092711980
Short name T164
Test name
Test status
Simulation time 336837170000 ps
CPU time 580.88 seconds
Started Jul 03 04:46:51 PM PDT 24
Finished Jul 03 05:11:34 PM PDT 24
Peak memory 160924 kb
Host smart-6074b1c1-99e5-4d69-ac27-c7c4a1af2ed4
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4092711980 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.4092711980
Directory /workspace/16.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.2751551433
Short name T179
Test name
Test status
Simulation time 337109910000 ps
CPU time 708.38 seconds
Started Jul 03 04:46:55 PM PDT 24
Finished Jul 03 05:15:43 PM PDT 24
Peak memory 160768 kb
Host smart-d579bb4f-e9b7-4d49-a828-e0bd388cb355
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2751551433 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.2751551433
Directory /workspace/17.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.3115703455
Short name T181
Test name
Test status
Simulation time 336942110000 ps
CPU time 810.51 seconds
Started Jul 03 04:47:00 PM PDT 24
Finished Jul 03 05:20:55 PM PDT 24
Peak memory 160688 kb
Host smart-871f0f24-39de-45f3-b909-f946ca52fa10
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3115703455 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.3115703455
Directory /workspace/18.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.3772519870
Short name T192
Test name
Test status
Simulation time 337105370000 ps
CPU time 858.56 seconds
Started Jul 03 04:47:02 PM PDT 24
Finished Jul 03 05:22:45 PM PDT 24
Peak memory 160796 kb
Host smart-4a43a3f9-cb29-4d2f-9e30-308e630f9e3c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3772519870 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.3772519870
Directory /workspace/19.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.2883725073
Short name T180
Test name
Test status
Simulation time 336880390000 ps
CPU time 786.61 seconds
Started Jul 03 04:47:01 PM PDT 24
Finished Jul 03 05:19:56 PM PDT 24
Peak memory 160688 kb
Host smart-5e9b28af-3c24-487c-8e9f-5004b80daae4
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2883725073 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.2883725073
Directory /workspace/20.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3370474805
Short name T184
Test name
Test status
Simulation time 336719130000 ps
CPU time 840.15 seconds
Started Jul 03 04:47:01 PM PDT 24
Finished Jul 03 05:21:11 PM PDT 24
Peak memory 160780 kb
Host smart-bfc947d3-1bef-434f-af31-660bece7f991
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3370474805 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.3370474805
Directory /workspace/21.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.3075142988
Short name T27
Test name
Test status
Simulation time 336484390000 ps
CPU time 922.91 seconds
Started Jul 03 04:47:00 PM PDT 24
Finished Jul 03 05:25:17 PM PDT 24
Peak memory 160640 kb
Host smart-532bed48-99fd-49cb-b730-a3e905e95955
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3075142988 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.3075142988
Directory /workspace/22.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.1002301720
Short name T171
Test name
Test status
Simulation time 336949110000 ps
CPU time 731.05 seconds
Started Jul 03 04:46:57 PM PDT 24
Finished Jul 03 05:16:52 PM PDT 24
Peak memory 160776 kb
Host smart-aece76bc-3c47-434f-98bb-4643250550d4
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1002301720 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.1002301720
Directory /workspace/23.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.1240018376
Short name T165
Test name
Test status
Simulation time 336723070000 ps
CPU time 830.81 seconds
Started Jul 03 04:47:03 PM PDT 24
Finished Jul 03 05:21:27 PM PDT 24
Peak memory 160744 kb
Host smart-a784946d-6639-416f-82bb-ceb69464cf52
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1240018376 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.1240018376
Directory /workspace/24.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.2881745994
Short name T26
Test name
Test status
Simulation time 337014710000 ps
CPU time 820.45 seconds
Started Jul 03 04:46:57 PM PDT 24
Finished Jul 03 05:20:39 PM PDT 24
Peak memory 160784 kb
Host smart-453f0852-b872-4f9d-9718-8b791d068691
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2881745994 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.2881745994
Directory /workspace/25.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.809217788
Short name T194
Test name
Test status
Simulation time 336811350000 ps
CPU time 732.65 seconds
Started Jul 03 04:46:54 PM PDT 24
Finished Jul 03 05:17:10 PM PDT 24
Peak memory 160780 kb
Host smart-6a253baf-686b-48a5-acaa-9786e1d7acdb
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=809217788 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.809217788
Directory /workspace/26.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.2223639718
Short name T195
Test name
Test status
Simulation time 337049330000 ps
CPU time 843.92 seconds
Started Jul 03 04:47:03 PM PDT 24
Finished Jul 03 05:21:53 PM PDT 24
Peak memory 160744 kb
Host smart-3958c6ec-d68c-42c4-aac1-240b73eaa463
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2223639718 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.2223639718
Directory /workspace/27.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.3742378931
Short name T198
Test name
Test status
Simulation time 336489310000 ps
CPU time 826.53 seconds
Started Jul 03 04:47:01 PM PDT 24
Finished Jul 03 05:21:14 PM PDT 24
Peak memory 160780 kb
Host smart-10cbabcc-6413-4431-8171-a503934d516e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3742378931 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.3742378931
Directory /workspace/28.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.1513825097
Short name T174
Test name
Test status
Simulation time 336521890000 ps
CPU time 670.35 seconds
Started Jul 03 04:47:01 PM PDT 24
Finished Jul 03 05:14:49 PM PDT 24
Peak memory 160784 kb
Host smart-dce2d3c6-53e2-4aa0-bcc5-9b94aef2cd3c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1513825097 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.1513825097
Directory /workspace/29.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.616270598
Short name T29
Test name
Test status
Simulation time 336650770000 ps
CPU time 808.92 seconds
Started Jul 03 04:47:00 PM PDT 24
Finished Jul 03 05:20:50 PM PDT 24
Peak memory 160684 kb
Host smart-edd5e1f0-7de2-4e1c-a0d5-e1a03a427a04
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=616270598 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.616270598
Directory /workspace/3.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.2122042628
Short name T185
Test name
Test status
Simulation time 336453450000 ps
CPU time 709.64 seconds
Started Jul 03 04:47:00 PM PDT 24
Finished Jul 03 05:15:56 PM PDT 24
Peak memory 160776 kb
Host smart-0940c7be-711e-4063-8e5f-3d7de3d6a379
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2122042628 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.2122042628
Directory /workspace/30.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.2318023255
Short name T163
Test name
Test status
Simulation time 337070210000 ps
CPU time 786.87 seconds
Started Jul 03 04:47:02 PM PDT 24
Finished Jul 03 05:19:10 PM PDT 24
Peak memory 160792 kb
Host smart-c026228f-ae02-411e-bcf9-7d66736e4990
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2318023255 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.2318023255
Directory /workspace/31.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.1550618425
Short name T177
Test name
Test status
Simulation time 336948690000 ps
CPU time 675.35 seconds
Started Jul 03 04:47:01 PM PDT 24
Finished Jul 03 05:14:58 PM PDT 24
Peak memory 160796 kb
Host smart-2ddeb37f-cde5-492c-92b6-df841bc0c138
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1550618425 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.1550618425
Directory /workspace/32.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.3582164935
Short name T161
Test name
Test status
Simulation time 336920330000 ps
CPU time 680.67 seconds
Started Jul 03 04:47:03 PM PDT 24
Finished Jul 03 05:15:32 PM PDT 24
Peak memory 160740 kb
Host smart-dcfe1866-8248-444f-af6a-bbc218c9b4b1
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3582164935 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.3582164935
Directory /workspace/33.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.2063512451
Short name T182
Test name
Test status
Simulation time 336599030000 ps
CPU time 640.22 seconds
Started Jul 03 04:47:00 PM PDT 24
Finished Jul 03 05:13:53 PM PDT 24
Peak memory 160788 kb
Host smart-4bd65d0d-f347-4d00-8037-5e5df73e88ec
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2063512451 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.2063512451
Directory /workspace/34.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.2288501626
Short name T191
Test name
Test status
Simulation time 337014490000 ps
CPU time 869.44 seconds
Started Jul 03 04:46:58 PM PDT 24
Finished Jul 03 05:21:57 PM PDT 24
Peak memory 160788 kb
Host smart-b28ed27e-8446-4583-9526-65c5aa813769
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2288501626 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.2288501626
Directory /workspace/35.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.3261274811
Short name T187
Test name
Test status
Simulation time 336496790000 ps
CPU time 726.17 seconds
Started Jul 03 04:46:59 PM PDT 24
Finished Jul 03 05:16:31 PM PDT 24
Peak memory 160788 kb
Host smart-11374227-e3e5-4445-8508-69865951e132
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3261274811 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.3261274811
Directory /workspace/36.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.2964555403
Short name T23
Test name
Test status
Simulation time 336754950000 ps
CPU time 908.68 seconds
Started Jul 03 04:47:02 PM PDT 24
Finished Jul 03 05:25:24 PM PDT 24
Peak memory 160776 kb
Host smart-d536d424-4c49-432f-be5e-72742d760f65
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2964555403 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.2964555403
Directory /workspace/37.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3844023770
Short name T169
Test name
Test status
Simulation time 336369870000 ps
CPU time 735.81 seconds
Started Jul 03 04:47:01 PM PDT 24
Finished Jul 03 05:17:02 PM PDT 24
Peak memory 160784 kb
Host smart-ec4e5214-fba2-4208-9747-d5d5c6ebdb23
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3844023770 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.3844023770
Directory /workspace/38.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.919530888
Short name T24
Test name
Test status
Simulation time 336505490000 ps
CPU time 756.13 seconds
Started Jul 03 04:47:00 PM PDT 24
Finished Jul 03 05:18:00 PM PDT 24
Peak memory 160780 kb
Host smart-008ae265-df1c-4b44-b216-ccf3f3395a40
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=919530888 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.919530888
Directory /workspace/39.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.87073273
Short name T167
Test name
Test status
Simulation time 336545310000 ps
CPU time 760.99 seconds
Started Jul 03 04:46:55 PM PDT 24
Finished Jul 03 05:17:53 PM PDT 24
Peak memory 160776 kb
Host smart-6c649fc8-4d98-49ad-9acd-7b82c12d13ab
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=87073273 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.87073273
Directory /workspace/4.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.2007217429
Short name T25
Test name
Test status
Simulation time 336472110000 ps
CPU time 684.61 seconds
Started Jul 03 04:46:59 PM PDT 24
Finished Jul 03 05:15:06 PM PDT 24
Peak memory 160784 kb
Host smart-c6d42e10-a447-4298-8b19-ae441926d9dd
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2007217429 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.2007217429
Directory /workspace/40.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.738216648
Short name T189
Test name
Test status
Simulation time 336627510000 ps
CPU time 722.38 seconds
Started Jul 03 04:46:58 PM PDT 24
Finished Jul 03 05:16:47 PM PDT 24
Peak memory 160764 kb
Host smart-5362a5fa-637e-45c0-8376-395d40208afa
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=738216648 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.738216648
Directory /workspace/41.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.403465072
Short name T21
Test name
Test status
Simulation time 336687910000 ps
CPU time 850.63 seconds
Started Jul 03 04:47:03 PM PDT 24
Finished Jul 03 05:22:38 PM PDT 24
Peak memory 160796 kb
Host smart-1280f9e1-7f9b-4a0d-9ac3-d78dbdd5e0b0
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=403465072 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.403465072
Directory /workspace/42.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.3284890234
Short name T196
Test name
Test status
Simulation time 336877390000 ps
CPU time 762.49 seconds
Started Jul 03 04:46:59 PM PDT 24
Finished Jul 03 05:18:09 PM PDT 24
Peak memory 160788 kb
Host smart-64eec77f-96e8-4d2b-9f1d-ba10de034286
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3284890234 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.3284890234
Directory /workspace/43.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.208488500
Short name T188
Test name
Test status
Simulation time 336668590000 ps
CPU time 644.71 seconds
Started Jul 03 04:47:03 PM PDT 24
Finished Jul 03 05:13:46 PM PDT 24
Peak memory 160772 kb
Host smart-dbcb7255-8577-49fe-8fec-37bd0f1fec7f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=208488500 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.208488500
Directory /workspace/44.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.3615059301
Short name T183
Test name
Test status
Simulation time 336645010000 ps
CPU time 741.99 seconds
Started Jul 03 04:47:02 PM PDT 24
Finished Jul 03 05:17:29 PM PDT 24
Peak memory 160792 kb
Host smart-522441a1-8637-49f3-a794-2eea291ce6c3
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3615059301 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.3615059301
Directory /workspace/45.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.1212932692
Short name T172
Test name
Test status
Simulation time 336680170000 ps
CPU time 646.92 seconds
Started Jul 03 04:47:01 PM PDT 24
Finished Jul 03 05:13:47 PM PDT 24
Peak memory 160740 kb
Host smart-b9aa1b4a-cbf7-4e8b-8b33-7ba791de9299
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1212932692 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.1212932692
Directory /workspace/46.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.1924456388
Short name T170
Test name
Test status
Simulation time 336510550000 ps
CPU time 684.49 seconds
Started Jul 03 04:47:02 PM PDT 24
Finished Jul 03 05:14:48 PM PDT 24
Peak memory 160796 kb
Host smart-b7afa4ff-e8d2-43dd-8df0-168b05b354da
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1924456388 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.1924456388
Directory /workspace/47.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1178522233
Short name T168
Test name
Test status
Simulation time 336663410000 ps
CPU time 863.18 seconds
Started Jul 03 04:47:04 PM PDT 24
Finished Jul 03 05:22:46 PM PDT 24
Peak memory 160800 kb
Host smart-6c81ab68-e26f-41fe-8b95-e20a5b7842af
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1178522233 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.1178522233
Directory /workspace/48.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.3270794647
Short name T173
Test name
Test status
Simulation time 336865770000 ps
CPU time 761.03 seconds
Started Jul 03 04:47:00 PM PDT 24
Finished Jul 03 05:17:39 PM PDT 24
Peak memory 160784 kb
Host smart-75574e6d-d657-407d-bb9c-788cb754dedf
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3270794647 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.3270794647
Directory /workspace/49.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.105074438
Short name T22
Test name
Test status
Simulation time 336880130000 ps
CPU time 922.2 seconds
Started Jul 03 04:46:59 PM PDT 24
Finished Jul 03 05:25:22 PM PDT 24
Peak memory 160640 kb
Host smart-38bf1c36-cb04-400e-81c0-2bf8b3465c84
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=105074438 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.105074438
Directory /workspace/5.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.2488000165
Short name T166
Test name
Test status
Simulation time 336688810000 ps
CPU time 832.62 seconds
Started Jul 03 04:47:00 PM PDT 24
Finished Jul 03 05:21:08 PM PDT 24
Peak memory 160780 kb
Host smart-83579630-4d68-4663-a63c-c2d359726ac0
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2488000165 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.2488000165
Directory /workspace/6.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.519986293
Short name T30
Test name
Test status
Simulation time 336840770000 ps
CPU time 840.25 seconds
Started Jul 03 04:47:03 PM PDT 24
Finished Jul 03 05:21:50 PM PDT 24
Peak memory 160740 kb
Host smart-20a01a9b-3add-43ea-8fec-91c9bfe618c5
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=519986293 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.519986293
Directory /workspace/7.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.1531395617
Short name T186
Test name
Test status
Simulation time 336456290000 ps
CPU time 726.4 seconds
Started Jul 03 04:46:54 PM PDT 24
Finished Jul 03 05:17:01 PM PDT 24
Peak memory 160780 kb
Host smart-84cf3ca4-2a88-47f7-9690-ed107c1198bc
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1531395617 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.1531395617
Directory /workspace/8.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.2474726872
Short name T197
Test name
Test status
Simulation time 336522430000 ps
CPU time 924.31 seconds
Started Jul 03 04:47:00 PM PDT 24
Finished Jul 03 05:25:21 PM PDT 24
Peak memory 160640 kb
Host smart-00ed4f5f-ba4e-41ec-ad86-d995dbd10d61
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2474726872 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.2474726872
Directory /workspace/9.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.2328690293
Short name T132
Test name
Test status
Simulation time 926350000 ps
CPU time 3.33 seconds
Started Jul 03 04:51:26 PM PDT 24
Finished Jul 03 04:51:34 PM PDT 24
Peak memory 164904 kb
Host smart-8dbeec22-034a-4b99-93cf-2403abc40ede
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2328690293 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.2328690293
Directory /workspace/0.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.2085882692
Short name T155
Test name
Test status
Simulation time 1472310000 ps
CPU time 3.17 seconds
Started Jul 03 04:51:17 PM PDT 24
Finished Jul 03 04:51:24 PM PDT 24
Peak memory 164924 kb
Host smart-d69aee87-246c-43d6-a24d-63fddd9591a5
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2085882692 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.2085882692
Directory /workspace/1.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.1444100029
Short name T138
Test name
Test status
Simulation time 1157950000 ps
CPU time 4.22 seconds
Started Jul 03 04:51:15 PM PDT 24
Finished Jul 03 04:51:25 PM PDT 24
Peak memory 166420 kb
Host smart-80d55d12-3120-45ae-87b7-67c2c301411e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1444100029 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.1444100029
Directory /workspace/10.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.118289408
Short name T137
Test name
Test status
Simulation time 1480410000 ps
CPU time 3.61 seconds
Started Jul 03 04:51:17 PM PDT 24
Finished Jul 03 04:51:26 PM PDT 24
Peak memory 164880 kb
Host smart-1a922148-b628-4c29-a810-27f6cf1079ff
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=118289408 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.118289408
Directory /workspace/11.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.3519534899
Short name T117
Test name
Test status
Simulation time 1341830000 ps
CPU time 4.24 seconds
Started Jul 03 04:51:12 PM PDT 24
Finished Jul 03 04:51:22 PM PDT 24
Peak memory 166444 kb
Host smart-c012b193-a8e2-424d-9b53-ee90a2e4354b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3519534899 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.3519534899
Directory /workspace/12.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.95957478
Short name T122
Test name
Test status
Simulation time 1208210000 ps
CPU time 3.26 seconds
Started Jul 03 04:51:11 PM PDT 24
Finished Jul 03 04:51:19 PM PDT 24
Peak memory 164876 kb
Host smart-772331c3-c620-4cab-a91c-75cd96eaff01
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=95957478 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.95957478
Directory /workspace/13.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.1320292457
Short name T144
Test name
Test status
Simulation time 1578090000 ps
CPU time 4.28 seconds
Started Jul 03 04:51:17 PM PDT 24
Finished Jul 03 04:51:26 PM PDT 24
Peak memory 166444 kb
Host smart-6d3e3c45-5475-4aec-945a-0c0fe351675a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1320292457 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.1320292457
Directory /workspace/14.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.1835020778
Short name T125
Test name
Test status
Simulation time 1533710000 ps
CPU time 4.67 seconds
Started Jul 03 04:51:14 PM PDT 24
Finished Jul 03 04:51:24 PM PDT 24
Peak memory 166468 kb
Host smart-7ec10a94-7519-4845-ade5-c00b244642c9
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1835020778 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.1835020778
Directory /workspace/15.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.568182298
Short name T133
Test name
Test status
Simulation time 1309450000 ps
CPU time 3.45 seconds
Started Jul 03 04:51:13 PM PDT 24
Finished Jul 03 04:51:21 PM PDT 24
Peak memory 166424 kb
Host smart-c2f7224b-8aeb-486f-93c0-6408678c750f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=568182298 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.568182298
Directory /workspace/16.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.3864988384
Short name T142
Test name
Test status
Simulation time 1611930000 ps
CPU time 4.56 seconds
Started Jul 03 04:51:18 PM PDT 24
Finished Jul 03 04:51:28 PM PDT 24
Peak memory 164844 kb
Host smart-18505b00-9c81-47ae-b719-9a9730fa1fca
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3864988384 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.3864988384
Directory /workspace/17.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.176696475
Short name T152
Test name
Test status
Simulation time 1254250000 ps
CPU time 4.18 seconds
Started Jul 03 04:51:11 PM PDT 24
Finished Jul 03 04:51:20 PM PDT 24
Peak memory 164916 kb
Host smart-f551a1fd-a544-4b2c-99b2-6589f1f3c122
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=176696475 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.176696475
Directory /workspace/18.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.1270934295
Short name T113
Test name
Test status
Simulation time 1106790000 ps
CPU time 4.14 seconds
Started Jul 03 04:51:14 PM PDT 24
Finished Jul 03 04:51:24 PM PDT 24
Peak memory 164876 kb
Host smart-8d309fe9-9a3e-4b10-bb73-de589b9161c9
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1270934295 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.1270934295
Directory /workspace/19.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.1867369499
Short name T154
Test name
Test status
Simulation time 1468450000 ps
CPU time 3.42 seconds
Started Jul 03 04:51:17 PM PDT 24
Finished Jul 03 04:51:25 PM PDT 24
Peak memory 164948 kb
Host smart-48653582-8d25-46c3-85da-d05b5b781970
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1867369499 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.1867369499
Directory /workspace/2.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.1419717694
Short name T119
Test name
Test status
Simulation time 1477950000 ps
CPU time 5.37 seconds
Started Jul 03 04:51:17 PM PDT 24
Finished Jul 03 04:51:29 PM PDT 24
Peak memory 166420 kb
Host smart-0a817305-c533-40bc-9d14-95d38157abd3
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1419717694 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.1419717694
Directory /workspace/20.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.1253207332
Short name T136
Test name
Test status
Simulation time 1519790000 ps
CPU time 4.52 seconds
Started Jul 03 04:51:08 PM PDT 24
Finished Jul 03 04:51:18 PM PDT 24
Peak memory 164916 kb
Host smart-2675c4e8-37f2-4e90-9f93-a9e6713bb641
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1253207332 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.1253207332
Directory /workspace/21.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.1231053743
Short name T123
Test name
Test status
Simulation time 1429290000 ps
CPU time 4.94 seconds
Started Jul 03 04:51:15 PM PDT 24
Finished Jul 03 04:51:27 PM PDT 24
Peak memory 164876 kb
Host smart-b08e432d-ee1c-42ca-8d81-28c68f0d3806
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1231053743 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.1231053743
Directory /workspace/22.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.1895305056
Short name T157
Test name
Test status
Simulation time 1537970000 ps
CPU time 3.54 seconds
Started Jul 03 04:51:11 PM PDT 24
Finished Jul 03 04:51:19 PM PDT 24
Peak memory 164936 kb
Host smart-0f880f78-bb0a-449f-9c05-b830cab9c3e3
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1895305056 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.1895305056
Directory /workspace/23.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.2277197094
Short name T143
Test name
Test status
Simulation time 1345330000 ps
CPU time 4.29 seconds
Started Jul 03 04:51:15 PM PDT 24
Finished Jul 03 04:51:24 PM PDT 24
Peak memory 166468 kb
Host smart-0d49cec3-f579-4386-8712-739636027cb2
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2277197094 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.2277197094
Directory /workspace/24.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.2582200862
Short name T148
Test name
Test status
Simulation time 1561310000 ps
CPU time 3.36 seconds
Started Jul 03 04:51:29 PM PDT 24
Finished Jul 03 04:51:37 PM PDT 24
Peak memory 166420 kb
Host smart-0a2463b7-8503-4428-be7c-16d36f3a5fee
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2582200862 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.2582200862
Directory /workspace/25.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.1618212992
Short name T153
Test name
Test status
Simulation time 1565770000 ps
CPU time 4.6 seconds
Started Jul 03 04:51:39 PM PDT 24
Finished Jul 03 04:51:50 PM PDT 24
Peak memory 164912 kb
Host smart-6a4a021f-ed34-459c-9f01-e1471653f42f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1618212992 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.1618212992
Directory /workspace/26.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.3186524744
Short name T139
Test name
Test status
Simulation time 1402570000 ps
CPU time 3.28 seconds
Started Jul 03 04:51:27 PM PDT 24
Finished Jul 03 04:51:35 PM PDT 24
Peak memory 166468 kb
Host smart-9cbe81c1-40b5-441b-9010-43407d83faa0
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3186524744 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.3186524744
Directory /workspace/27.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.3104295048
Short name T151
Test name
Test status
Simulation time 1493710000 ps
CPU time 4.16 seconds
Started Jul 03 04:51:29 PM PDT 24
Finished Jul 03 04:51:40 PM PDT 24
Peak memory 166388 kb
Host smart-556c9ac2-5602-4c63-a30a-db364136421f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3104295048 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.3104295048
Directory /workspace/28.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.1649894088
Short name T124
Test name
Test status
Simulation time 1436570000 ps
CPU time 4.26 seconds
Started Jul 03 04:51:29 PM PDT 24
Finished Jul 03 04:51:41 PM PDT 24
Peak memory 164912 kb
Host smart-45c3c4ff-2946-4b03-a692-d9d3ac5930fc
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1649894088 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.1649894088
Directory /workspace/29.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.1877161729
Short name T150
Test name
Test status
Simulation time 1544070000 ps
CPU time 4.37 seconds
Started Jul 03 04:51:10 PM PDT 24
Finished Jul 03 04:51:20 PM PDT 24
Peak memory 164872 kb
Host smart-3cbb319d-5be1-4383-87ce-5029f32f7985
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1877161729 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.1877161729
Directory /workspace/3.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.2537742203
Short name T126
Test name
Test status
Simulation time 1523870000 ps
CPU time 4.35 seconds
Started Jul 03 04:51:15 PM PDT 24
Finished Jul 03 04:51:25 PM PDT 24
Peak memory 164880 kb
Host smart-9874a8e6-612a-4380-b08d-49caaad1ad67
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2537742203 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.2537742203
Directory /workspace/30.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.158804551
Short name T149
Test name
Test status
Simulation time 1546490000 ps
CPU time 4.23 seconds
Started Jul 03 04:51:24 PM PDT 24
Finished Jul 03 04:51:34 PM PDT 24
Peak memory 164864 kb
Host smart-3ae029d2-0366-42f0-b8c1-17bb72525de1
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=158804551 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.158804551
Directory /workspace/31.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.1082903213
Short name T156
Test name
Test status
Simulation time 1507670000 ps
CPU time 5.04 seconds
Started Jul 03 04:51:13 PM PDT 24
Finished Jul 03 04:51:25 PM PDT 24
Peak memory 164896 kb
Host smart-ef0df199-129e-47b0-8125-909168081abc
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1082903213 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.1082903213
Directory /workspace/32.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.490477147
Short name T120
Test name
Test status
Simulation time 1395810000 ps
CPU time 3.73 seconds
Started Jul 03 04:51:17 PM PDT 24
Finished Jul 03 04:51:27 PM PDT 24
Peak memory 164936 kb
Host smart-8494bc84-bf80-46e4-83a8-15d1674533f7
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=490477147 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.490477147
Directory /workspace/33.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.2769349918
Short name T130
Test name
Test status
Simulation time 1576670000 ps
CPU time 4.1 seconds
Started Jul 03 04:51:30 PM PDT 24
Finished Jul 03 04:51:41 PM PDT 24
Peak memory 164928 kb
Host smart-123ebe2d-3d44-4d91-9e4f-bfa1d92530c4
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2769349918 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.2769349918
Directory /workspace/34.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.100444714
Short name T127
Test name
Test status
Simulation time 1279910000 ps
CPU time 3.72 seconds
Started Jul 03 04:51:24 PM PDT 24
Finished Jul 03 04:51:33 PM PDT 24
Peak memory 164908 kb
Host smart-1b0e680d-31ae-49e6-ab9f-e654fab3cabe
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=100444714 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.100444714
Directory /workspace/35.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.2382070916
Short name T134
Test name
Test status
Simulation time 1437910000 ps
CPU time 3.21 seconds
Started Jul 03 04:51:28 PM PDT 24
Finished Jul 03 04:51:37 PM PDT 24
Peak memory 166456 kb
Host smart-868947af-4833-4e64-a488-3dc913fa538f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2382070916 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.2382070916
Directory /workspace/36.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.2814454724
Short name T159
Test name
Test status
Simulation time 1484070000 ps
CPU time 3.59 seconds
Started Jul 03 04:51:15 PM PDT 24
Finished Jul 03 04:51:24 PM PDT 24
Peak memory 164924 kb
Host smart-57cf3eee-f87d-41a5-887d-192ec5f4e358
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2814454724 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.2814454724
Directory /workspace/37.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.2414555086
Short name T121
Test name
Test status
Simulation time 1466030000 ps
CPU time 3.72 seconds
Started Jul 03 04:51:31 PM PDT 24
Finished Jul 03 04:51:41 PM PDT 24
Peak memory 166452 kb
Host smart-b6e78392-83c7-427e-a0f8-af26271ab641
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2414555086 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.2414555086
Directory /workspace/38.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.2122177329
Short name T141
Test name
Test status
Simulation time 1564990000 ps
CPU time 5.12 seconds
Started Jul 03 04:51:24 PM PDT 24
Finished Jul 03 04:51:36 PM PDT 24
Peak memory 164908 kb
Host smart-4cee2407-490a-466a-960f-f1cdd4d42039
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2122177329 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.2122177329
Directory /workspace/39.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.1725125243
Short name T116
Test name
Test status
Simulation time 1534790000 ps
CPU time 5.49 seconds
Started Jul 03 04:51:11 PM PDT 24
Finished Jul 03 04:51:24 PM PDT 24
Peak memory 164892 kb
Host smart-5f7bb808-95bf-46ce-b7ee-2d6efa92a148
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1725125243 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.1725125243
Directory /workspace/4.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.1002412001
Short name T129
Test name
Test status
Simulation time 1595070000 ps
CPU time 4.96 seconds
Started Jul 03 04:51:15 PM PDT 24
Finished Jul 03 04:51:26 PM PDT 24
Peak memory 164880 kb
Host smart-02c7dce3-3d6a-4d2d-9c54-5a99130d630f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1002412001 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.1002412001
Directory /workspace/40.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.1694075087
Short name T135
Test name
Test status
Simulation time 1399610000 ps
CPU time 4.77 seconds
Started Jul 03 04:51:18 PM PDT 24
Finished Jul 03 04:51:30 PM PDT 24
Peak memory 164828 kb
Host smart-a73fcbaf-61f6-4e29-bd8d-3cc776f43c7e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1694075087 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.1694075087
Directory /workspace/41.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.2024950413
Short name T145
Test name
Test status
Simulation time 1518110000 ps
CPU time 4.52 seconds
Started Jul 03 04:51:35 PM PDT 24
Finished Jul 03 04:51:46 PM PDT 24
Peak memory 164912 kb
Host smart-da4f2a5d-1f59-46c6-a6bc-8d0b1dbf102c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2024950413 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.2024950413
Directory /workspace/42.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1179929759
Short name T115
Test name
Test status
Simulation time 1398050000 ps
CPU time 4.11 seconds
Started Jul 03 04:51:30 PM PDT 24
Finished Jul 03 04:51:41 PM PDT 24
Peak memory 164876 kb
Host smart-c47e904c-c517-4156-a8cd-736f2d5b9caf
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1179929759 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.1179929759
Directory /workspace/43.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.286378971
Short name T111
Test name
Test status
Simulation time 1401490000 ps
CPU time 4.08 seconds
Started Jul 03 04:51:16 PM PDT 24
Finished Jul 03 04:51:25 PM PDT 24
Peak memory 164888 kb
Host smart-43740f60-722d-47b8-ace7-167c66ce61db
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=286378971 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.286378971
Directory /workspace/44.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.3727215894
Short name T128
Test name
Test status
Simulation time 1291290000 ps
CPU time 3.71 seconds
Started Jul 03 04:51:18 PM PDT 24
Finished Jul 03 04:51:27 PM PDT 24
Peak memory 166440 kb
Host smart-41255395-82dc-44fa-81af-93b7cd087d3f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3727215894 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.3727215894
Directory /workspace/45.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.2569951306
Short name T146
Test name
Test status
Simulation time 1604350000 ps
CPU time 5.51 seconds
Started Jul 03 04:51:13 PM PDT 24
Finished Jul 03 04:51:26 PM PDT 24
Peak memory 164872 kb
Host smart-24613fcd-7f8e-45e4-8dd7-549c03f498ab
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2569951306 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.2569951306
Directory /workspace/46.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.3463456409
Short name T118
Test name
Test status
Simulation time 1332930000 ps
CPU time 3.92 seconds
Started Jul 03 04:51:21 PM PDT 24
Finished Jul 03 04:51:30 PM PDT 24
Peak memory 164924 kb
Host smart-dd3f5e6b-4e67-4db5-b6d4-39a2c17129ed
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3463456409 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.3463456409
Directory /workspace/47.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.2273129596
Short name T112
Test name
Test status
Simulation time 1441530000 ps
CPU time 5.1 seconds
Started Jul 03 04:51:14 PM PDT 24
Finished Jul 03 04:51:26 PM PDT 24
Peak memory 164876 kb
Host smart-c9a3fdca-7e3b-41fe-84d9-a5a7df4c325b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2273129596 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.2273129596
Directory /workspace/48.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.3704213573
Short name T160
Test name
Test status
Simulation time 1512270000 ps
CPU time 4.65 seconds
Started Jul 03 04:51:19 PM PDT 24
Finished Jul 03 04:51:29 PM PDT 24
Peak memory 164928 kb
Host smart-610a63ac-02ed-4ca5-a3ee-ce8317a56f3e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3704213573 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.3704213573
Directory /workspace/49.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.3914577092
Short name T131
Test name
Test status
Simulation time 1228030000 ps
CPU time 4.9 seconds
Started Jul 03 04:51:12 PM PDT 24
Finished Jul 03 04:51:23 PM PDT 24
Peak memory 164904 kb
Host smart-5f5456c3-93bb-4333-820f-0be6cc7a42ac
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3914577092 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.3914577092
Directory /workspace/5.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.3987963309
Short name T114
Test name
Test status
Simulation time 1333450000 ps
CPU time 3.63 seconds
Started Jul 03 04:51:11 PM PDT 24
Finished Jul 03 04:51:19 PM PDT 24
Peak memory 164872 kb
Host smart-eefcce33-a181-4771-86bd-ca7aed188b6f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3987963309 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.3987963309
Directory /workspace/6.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.3149104495
Short name T158
Test name
Test status
Simulation time 1243390000 ps
CPU time 3.75 seconds
Started Jul 03 04:51:16 PM PDT 24
Finished Jul 03 04:51:24 PM PDT 24
Peak memory 164912 kb
Host smart-f5a2397f-7156-431f-aaa7-53bc4a7a536a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3149104495 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.3149104495
Directory /workspace/7.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.3094879051
Short name T147
Test name
Test status
Simulation time 1507710000 ps
CPU time 5.35 seconds
Started Jul 03 04:51:11 PM PDT 24
Finished Jul 03 04:51:24 PM PDT 24
Peak memory 164904 kb
Host smart-c9b0ba98-e9d4-44b8-87c5-c43a6ca5a99e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3094879051 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.3094879051
Directory /workspace/8.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.3907024956
Short name T140
Test name
Test status
Simulation time 1370810000 ps
CPU time 3.33 seconds
Started Jul 03 04:51:20 PM PDT 24
Finished Jul 03 04:51:28 PM PDT 24
Peak memory 164872 kb
Host smart-3c941d31-8325-4264-b1f0-961a38d2365f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3907024956 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.3907024956
Directory /workspace/9.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.2161617106
Short name T69
Test name
Test status
Simulation time 1361470000 ps
CPU time 3.49 seconds
Started Jul 03 04:51:09 PM PDT 24
Finished Jul 03 04:51:18 PM PDT 24
Peak memory 164912 kb
Host smart-b24295b4-3e66-4507-b682-16c4320642ee
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2161617106 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.2161617106
Directory /workspace/0.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.4040290452
Short name T64
Test name
Test status
Simulation time 1596090000 ps
CPU time 5.75 seconds
Started Jul 03 04:51:10 PM PDT 24
Finished Jul 03 04:51:23 PM PDT 24
Peak memory 166488 kb
Host smart-24626b64-54e2-490b-9d70-9d2abdbb34f7
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4040290452 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.4040290452
Directory /workspace/10.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.897115484
Short name T3
Test name
Test status
Simulation time 1562490000 ps
CPU time 2.77 seconds
Started Jul 03 04:51:04 PM PDT 24
Finished Jul 03 04:51:11 PM PDT 24
Peak memory 164736 kb
Host smart-7f90443f-de18-4c6a-bf1d-f06054df3aad
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=897115484 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.897115484
Directory /workspace/11.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.2773112426
Short name T36
Test name
Test status
Simulation time 1324210000 ps
CPU time 4.03 seconds
Started Jul 03 04:51:10 PM PDT 24
Finished Jul 03 04:51:20 PM PDT 24
Peak memory 164844 kb
Host smart-eff9c388-812f-40e7-ad15-28bf5cbaf8ed
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2773112426 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.2773112426
Directory /workspace/12.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.1621807030
Short name T46
Test name
Test status
Simulation time 1597910000 ps
CPU time 4.76 seconds
Started Jul 03 04:51:11 PM PDT 24
Finished Jul 03 04:51:21 PM PDT 24
Peak memory 164928 kb
Host smart-1bb0a03b-297b-4e1f-98d8-a371ab9c46e4
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1621807030 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.1621807030
Directory /workspace/13.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.575513166
Short name T2
Test name
Test status
Simulation time 1406270000 ps
CPU time 4.71 seconds
Started Jul 03 04:51:05 PM PDT 24
Finished Jul 03 04:51:16 PM PDT 24
Peak memory 164904 kb
Host smart-06389851-1a11-4ab2-98b0-302d7d08d3ca
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=575513166 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.575513166
Directory /workspace/14.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.3029605107
Short name T49
Test name
Test status
Simulation time 1442230000 ps
CPU time 4.97 seconds
Started Jul 03 04:51:09 PM PDT 24
Finished Jul 03 04:51:20 PM PDT 24
Peak memory 166388 kb
Host smart-4ff18b24-6f46-412c-9625-1a75babbb1da
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3029605107 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.3029605107
Directory /workspace/15.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.495213797
Short name T63
Test name
Test status
Simulation time 1350190000 ps
CPU time 3.16 seconds
Started Jul 03 04:51:09 PM PDT 24
Finished Jul 03 04:51:17 PM PDT 24
Peak memory 164912 kb
Host smart-7a8508a0-9ab1-4dfd-921b-40bbfaa04392
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=495213797 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.495213797
Directory /workspace/16.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.2628429683
Short name T12
Test name
Test status
Simulation time 1253570000 ps
CPU time 3.75 seconds
Started Jul 03 04:51:10 PM PDT 24
Finished Jul 03 04:51:18 PM PDT 24
Peak memory 164916 kb
Host smart-6412372e-2ee2-4e54-acb3-3b56f56741c0
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2628429683 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.2628429683
Directory /workspace/17.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.2644886113
Short name T10
Test name
Test status
Simulation time 1553830000 ps
CPU time 4.74 seconds
Started Jul 03 04:51:10 PM PDT 24
Finished Jul 03 04:51:21 PM PDT 24
Peak memory 164844 kb
Host smart-427d4e58-2b59-4f5e-8359-d00bfa866f8d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2644886113 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.2644886113
Directory /workspace/18.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.942114677
Short name T51
Test name
Test status
Simulation time 1116070000 ps
CPU time 3.8 seconds
Started Jul 03 04:51:12 PM PDT 24
Finished Jul 03 04:51:21 PM PDT 24
Peak memory 164872 kb
Host smart-4a295013-1925-46a8-a6cf-46fccda3fe96
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=942114677 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.942114677
Directory /workspace/19.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.2688417251
Short name T57
Test name
Test status
Simulation time 934710000 ps
CPU time 3.87 seconds
Started Jul 03 04:51:08 PM PDT 24
Finished Jul 03 04:51:16 PM PDT 24
Peak memory 164924 kb
Host smart-3cbd20d3-708d-4bf6-945d-eaeb7773a0d3
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2688417251 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.2688417251
Directory /workspace/2.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.2698376596
Short name T58
Test name
Test status
Simulation time 1546630000 ps
CPU time 5.26 seconds
Started Jul 03 04:51:15 PM PDT 24
Finished Jul 03 04:51:28 PM PDT 24
Peak memory 164872 kb
Host smart-107d2622-4638-4684-a7f3-1d217b98530d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2698376596 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.2698376596
Directory /workspace/20.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.2327463577
Short name T1
Test name
Test status
Simulation time 1616850000 ps
CPU time 5.64 seconds
Started Jul 03 04:51:08 PM PDT 24
Finished Jul 03 04:51:21 PM PDT 24
Peak memory 166448 kb
Host smart-9ae1c519-e132-445f-abba-702719434277
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2327463577 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.2327463577
Directory /workspace/21.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.760134936
Short name T31
Test name
Test status
Simulation time 1525410000 ps
CPU time 4.59 seconds
Started Jul 03 04:51:11 PM PDT 24
Finished Jul 03 04:51:21 PM PDT 24
Peak memory 164860 kb
Host smart-8b238be4-5d01-4388-8a67-5ca42ad3371f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=760134936 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.760134936
Directory /workspace/22.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.1935347233
Short name T35
Test name
Test status
Simulation time 1592050000 ps
CPU time 5.11 seconds
Started Jul 03 04:51:11 PM PDT 24
Finished Jul 03 04:51:22 PM PDT 24
Peak memory 164892 kb
Host smart-463c92e8-84b0-48cb-9908-ee3fdea795c2
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1935347233 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.1935347233
Directory /workspace/23.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.3887982529
Short name T40
Test name
Test status
Simulation time 1537990000 ps
CPU time 5.64 seconds
Started Jul 03 04:51:07 PM PDT 24
Finished Jul 03 04:51:20 PM PDT 24
Peak memory 164928 kb
Host smart-85d3e697-2c81-4b11-8968-719cca9d39ad
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3887982529 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.3887982529
Directory /workspace/24.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.440461946
Short name T70
Test name
Test status
Simulation time 1586810000 ps
CPU time 5.31 seconds
Started Jul 03 04:51:06 PM PDT 24
Finished Jul 03 04:51:18 PM PDT 24
Peak memory 164892 kb
Host smart-16debcea-9fbe-4b2f-b486-db24cc24f75a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=440461946 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.440461946
Directory /workspace/25.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.950671286
Short name T39
Test name
Test status
Simulation time 1243310000 ps
CPU time 3.73 seconds
Started Jul 03 04:51:03 PM PDT 24
Finished Jul 03 04:51:12 PM PDT 24
Peak memory 164912 kb
Host smart-743a2abd-5d36-4051-aad6-731515184ea1
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=950671286 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.950671286
Directory /workspace/26.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.4065515562
Short name T45
Test name
Test status
Simulation time 1418310000 ps
CPU time 3.62 seconds
Started Jul 03 04:51:11 PM PDT 24
Finished Jul 03 04:51:19 PM PDT 24
Peak memory 164876 kb
Host smart-9bc89829-11d7-47c2-b6d7-e8822d6107e3
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4065515562 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.4065515562
Directory /workspace/27.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.4076390681
Short name T62
Test name
Test status
Simulation time 1374770000 ps
CPU time 3.18 seconds
Started Jul 03 04:51:08 PM PDT 24
Finished Jul 03 04:51:15 PM PDT 24
Peak memory 166476 kb
Host smart-4c545c23-6e14-4da0-8092-61b2084b8157
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4076390681 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.4076390681
Directory /workspace/28.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.1777502240
Short name T61
Test name
Test status
Simulation time 1453750000 ps
CPU time 3.59 seconds
Started Jul 03 04:51:06 PM PDT 24
Finished Jul 03 04:51:14 PM PDT 24
Peak memory 166452 kb
Host smart-d480aed5-a565-42ae-abbe-50c020adf8d6
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1777502240 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.1777502240
Directory /workspace/29.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.347450179
Short name T68
Test name
Test status
Simulation time 1478970000 ps
CPU time 4.01 seconds
Started Jul 03 04:51:08 PM PDT 24
Finished Jul 03 04:51:17 PM PDT 24
Peak memory 164908 kb
Host smart-55734df8-d572-4bdb-9c98-2fa7699d72d2
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=347450179 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.347450179
Directory /workspace/3.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.4006867235
Short name T54
Test name
Test status
Simulation time 1527290000 ps
CPU time 5.28 seconds
Started Jul 03 04:51:12 PM PDT 24
Finished Jul 03 04:51:25 PM PDT 24
Peak memory 164876 kb
Host smart-77243112-ea06-4139-a22d-d96b63ffd8c7
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4006867235 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.4006867235
Directory /workspace/30.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.910187265
Short name T47
Test name
Test status
Simulation time 1557770000 ps
CPU time 5.41 seconds
Started Jul 03 04:51:10 PM PDT 24
Finished Jul 03 04:51:22 PM PDT 24
Peak memory 164884 kb
Host smart-faa272b6-e9a8-4bb3-8696-4347830b7e77
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=910187265 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.910187265
Directory /workspace/31.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.2778547656
Short name T34
Test name
Test status
Simulation time 1540510000 ps
CPU time 3.87 seconds
Started Jul 03 04:51:09 PM PDT 24
Finished Jul 03 04:51:18 PM PDT 24
Peak memory 164936 kb
Host smart-2d3f3a32-a7d0-4150-9723-a0e1d6976c65
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2778547656 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.2778547656
Directory /workspace/32.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.2642905329
Short name T42
Test name
Test status
Simulation time 1359630000 ps
CPU time 3.96 seconds
Started Jul 03 04:51:12 PM PDT 24
Finished Jul 03 04:51:21 PM PDT 24
Peak memory 164912 kb
Host smart-a3439f59-4fa6-41b9-80df-d74f1ed8639a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2642905329 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.2642905329
Directory /workspace/33.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.3352009857
Short name T60
Test name
Test status
Simulation time 1537630000 ps
CPU time 5.12 seconds
Started Jul 03 04:51:10 PM PDT 24
Finished Jul 03 04:51:21 PM PDT 24
Peak memory 166404 kb
Host smart-746b7ea3-91ff-4d03-bfd5-a5aac1618239
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3352009857 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.3352009857
Directory /workspace/34.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.281967528
Short name T52
Test name
Test status
Simulation time 1398390000 ps
CPU time 4.76 seconds
Started Jul 03 04:51:06 PM PDT 24
Finished Jul 03 04:51:17 PM PDT 24
Peak memory 164936 kb
Host smart-fa450d3a-8ce3-4c2a-9c20-536d58cd79e5
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=281967528 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.281967528
Directory /workspace/35.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.1132820977
Short name T9
Test name
Test status
Simulation time 1580210000 ps
CPU time 5.63 seconds
Started Jul 03 04:51:14 PM PDT 24
Finished Jul 03 04:51:27 PM PDT 24
Peak memory 164896 kb
Host smart-99722184-d5ef-4738-8cb8-f69028889501
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1132820977 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.1132820977
Directory /workspace/36.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.1584913907
Short name T59
Test name
Test status
Simulation time 1438610000 ps
CPU time 4.95 seconds
Started Jul 03 04:51:09 PM PDT 24
Finished Jul 03 04:51:20 PM PDT 24
Peak memory 166388 kb
Host smart-dbd3d0df-953e-4f56-8c71-b3024af825bd
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1584913907 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.1584913907
Directory /workspace/37.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.1913197589
Short name T11
Test name
Test status
Simulation time 1345190000 ps
CPU time 4.34 seconds
Started Jul 03 04:51:13 PM PDT 24
Finished Jul 03 04:51:23 PM PDT 24
Peak memory 164900 kb
Host smart-60a91916-0749-4148-a0aa-7345ab397523
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1913197589 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.1913197589
Directory /workspace/38.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.1021550698
Short name T67
Test name
Test status
Simulation time 1430490000 ps
CPU time 4.28 seconds
Started Jul 03 04:51:16 PM PDT 24
Finished Jul 03 04:51:26 PM PDT 24
Peak memory 166440 kb
Host smart-c58de261-6a73-4f90-a50a-59fa2c4edd30
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1021550698 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.1021550698
Directory /workspace/39.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.1580054422
Short name T37
Test name
Test status
Simulation time 1512430000 ps
CPU time 4.39 seconds
Started Jul 03 04:51:08 PM PDT 24
Finished Jul 03 04:51:18 PM PDT 24
Peak memory 164912 kb
Host smart-1a8758c3-25ef-470f-a921-27aed950b4cd
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1580054422 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.1580054422
Directory /workspace/4.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.2503969708
Short name T38
Test name
Test status
Simulation time 1638590000 ps
CPU time 4.46 seconds
Started Jul 03 04:51:10 PM PDT 24
Finished Jul 03 04:51:21 PM PDT 24
Peak memory 164872 kb
Host smart-b7922a19-37cc-44c2-a8f8-45975d3243ee
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2503969708 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.2503969708
Directory /workspace/40.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.2649167193
Short name T32
Test name
Test status
Simulation time 1410870000 ps
CPU time 5.3 seconds
Started Jul 03 04:51:19 PM PDT 24
Finished Jul 03 04:51:31 PM PDT 24
Peak memory 166432 kb
Host smart-98cd23e9-9ceb-41da-8069-7f5f4112435d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2649167193 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.2649167193
Directory /workspace/41.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.2716876731
Short name T13
Test name
Test status
Simulation time 1286630000 ps
CPU time 3.96 seconds
Started Jul 03 04:51:14 PM PDT 24
Finished Jul 03 04:51:23 PM PDT 24
Peak memory 166452 kb
Host smart-293e8cdc-c874-40f3-9573-d0977904b2f1
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2716876731 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.2716876731
Directory /workspace/42.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.695209209
Short name T33
Test name
Test status
Simulation time 1472150000 ps
CPU time 4.84 seconds
Started Jul 03 04:51:11 PM PDT 24
Finished Jul 03 04:51:23 PM PDT 24
Peak memory 164896 kb
Host smart-c63b8b4c-6929-4fd0-9fe9-2ede1b35cee1
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=695209209 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.695209209
Directory /workspace/43.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.2360255671
Short name T66
Test name
Test status
Simulation time 1415710000 ps
CPU time 4.57 seconds
Started Jul 03 04:51:26 PM PDT 24
Finished Jul 03 04:51:38 PM PDT 24
Peak memory 166444 kb
Host smart-dcaedf1a-9744-4fb0-939a-61780f9b8ee7
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2360255671 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.2360255671
Directory /workspace/44.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.1565177580
Short name T48
Test name
Test status
Simulation time 1596750000 ps
CPU time 4.73 seconds
Started Jul 03 04:51:24 PM PDT 24
Finished Jul 03 04:51:36 PM PDT 24
Peak memory 166496 kb
Host smart-cae554b5-f262-4be9-90d6-0fd07abffe0c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1565177580 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.1565177580
Directory /workspace/45.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.3025096196
Short name T7
Test name
Test status
Simulation time 1421990000 ps
CPU time 4.47 seconds
Started Jul 03 04:51:16 PM PDT 24
Finished Jul 03 04:51:27 PM PDT 24
Peak memory 164900 kb
Host smart-a33fdaf2-5d4e-4d78-a87a-668373b21be6
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3025096196 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.3025096196
Directory /workspace/46.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.4042098341
Short name T44
Test name
Test status
Simulation time 1308250000 ps
CPU time 3.46 seconds
Started Jul 03 04:51:13 PM PDT 24
Finished Jul 03 04:51:21 PM PDT 24
Peak memory 166448 kb
Host smart-5ccdd6c7-b930-4ad6-8847-d0749256b766
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4042098341 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.4042098341
Directory /workspace/47.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.1167050964
Short name T55
Test name
Test status
Simulation time 1561030000 ps
CPU time 5.46 seconds
Started Jul 03 04:51:15 PM PDT 24
Finished Jul 03 04:51:27 PM PDT 24
Peak memory 166404 kb
Host smart-10865c26-58d5-4dbd-9ba3-f5ba6ffff80e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1167050964 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.1167050964
Directory /workspace/48.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.1397661458
Short name T56
Test name
Test status
Simulation time 1460550000 ps
CPU time 4.15 seconds
Started Jul 03 04:51:11 PM PDT 24
Finished Jul 03 04:51:21 PM PDT 24
Peak memory 166380 kb
Host smart-1427c9ce-1178-4dbf-86d9-a8cb27557034
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1397661458 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.1397661458
Directory /workspace/49.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.1496034079
Short name T53
Test name
Test status
Simulation time 1598370000 ps
CPU time 5.11 seconds
Started Jul 03 04:51:14 PM PDT 24
Finished Jul 03 04:51:26 PM PDT 24
Peak memory 164740 kb
Host smart-5dc097bb-038c-4f22-85e8-8208e44479c4
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1496034079 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.1496034079
Directory /workspace/5.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.422952096
Short name T65
Test name
Test status
Simulation time 1281430000 ps
CPU time 4.06 seconds
Started Jul 03 04:51:13 PM PDT 24
Finished Jul 03 04:51:22 PM PDT 24
Peak memory 164900 kb
Host smart-7405d5e6-9044-498d-b94e-29cb6370e2e2
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=422952096 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.422952096
Directory /workspace/6.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.3839642100
Short name T43
Test name
Test status
Simulation time 1088170000 ps
CPU time 3.93 seconds
Started Jul 03 04:51:08 PM PDT 24
Finished Jul 03 04:51:17 PM PDT 24
Peak memory 164908 kb
Host smart-ce4b206a-cd07-435c-a4fb-d7c10ebd14bd
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3839642100 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.3839642100
Directory /workspace/7.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.2264867439
Short name T41
Test name
Test status
Simulation time 1372370000 ps
CPU time 3.56 seconds
Started Jul 03 04:51:11 PM PDT 24
Finished Jul 03 04:51:20 PM PDT 24
Peak memory 164880 kb
Host smart-04a17744-781b-4a49-ac9a-8916a668c18f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2264867439 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.2264867439
Directory /workspace/8.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.2660391459
Short name T50
Test name
Test status
Simulation time 1395910000 ps
CPU time 4.75 seconds
Started Jul 03 04:51:16 PM PDT 24
Finished Jul 03 04:51:27 PM PDT 24
Peak memory 164908 kb
Host smart-c9f16dc6-2ea7-43fc-b4ec-87c32b3c784e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2660391459 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.2660391459
Directory /workspace/9.prim_lfsr_gal_smoke/latest
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