Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.31 100.00 96.55 100.00 100.00 95.00


Total tests in report: 200
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
87.31 87.31 100.00 100.00 96.55 96.55 100.00 100.00 100.00 100.00 40.00 40.00 /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.3705568877
96.81 9.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 87.50 47.50 /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.3441315235
98.31 1.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 95.00 7.50 /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.4122767419

Tests that do not contribute to grading

Name
/workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.1654623505
/workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.1885256194
/workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.2447846812
/workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.3483069457
/workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.2027151430
/workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.2423301449
/workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.1899608503
/workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.1913388279
/workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.2827948609
/workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.3865218481
/workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.3961213779
/workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.1622681543
/workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.3019584239
/workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.1853976546
/workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.3053635157
/workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.2160340971
/workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.2665832057
/workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.1168394563
/workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1060018447
/workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.3362893925
/workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.1526475758
/workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.2717918446
/workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.3721171847
/workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.2883968046
/workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.1309955217
/workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.3193022933
/workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.1440904351
/workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.3299084145
/workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.2466252992
/workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.1649612309
/workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.2707981738
/workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.1372508457
/workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.210203778
/workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.487914584
/workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.3994810901
/workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.3522343774
/workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.1339992163
/workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.338596075
/workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.2638287367
/workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.824514030
/workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.835542289
/workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.2319917760
/workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.3863450186
/workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.2556636462
/workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.2317310595
/workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.635637222
/workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.3729892338
/workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.662614468
/workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.1269345153
/workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.1304214463
/workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.263005539
/workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.2358208446
/workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.2608956606
/workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.277761771
/workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.994333471
/workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.3350715664
/workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.3828913583
/workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.1236837027
/workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.700489198
/workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.3389093559
/workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.380283697
/workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.617152288
/workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3437079759
/workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.3907799718
/workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.2477951187
/workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.3671105881
/workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.4231247029
/workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.4160984269
/workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.3315908322
/workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.897014515
/workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.777783679
/workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.528368169
/workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.377549245
/workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.1798308450
/workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.4183456178
/workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.2398639612
/workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.3329847906
/workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.1758555346
/workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.805291949
/workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.3931761048
/workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.1272311346
/workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.3976592885
/workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.3796433153
/workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.252556362
/workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.2749519552
/workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.3013974685
/workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.2546245253
/workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.3597958022
/workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.943457003
/workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.1016412021
/workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.1825842456
/workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.3630688995
/workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.2612317647
/workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.1514316143
/workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.6012025
/workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.2598606875
/workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.2656367871
/workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.3699622659
/workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.896711359
/workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.984518712
/workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.1432951559
/workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.232265155
/workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.1726597658
/workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.2933567741
/workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.3600268550
/workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.3986712466
/workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.3439949088
/workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.1071256394
/workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.1788100409
/workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.1714689914
/workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.174359535
/workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.2465651385
/workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3848429275
/workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.3324109920
/workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.1549054937
/workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.212760548
/workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.3683366301
/workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.3033224356
/workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.4033047738
/workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.3835973569
/workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.3809453646
/workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.1207671429
/workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.2139817566
/workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.572869542
/workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.3641784312
/workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.2848021101
/workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.459284060
/workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.3814808715
/workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.1433094059
/workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.2844375532
/workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.3196909445
/workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.1134181052
/workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.2654117203
/workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.2680862408
/workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.3692849980
/workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.3760669784
/workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.3620891683
/workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.830502138
/workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.1836411691
/workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.355634326
/workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.4044228877
/workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.134645625
/workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.2673129684
/workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.2917327939
/workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.1803030618
/workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.1343109505
/workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1406477111
/workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.3467056390
/workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.1821933980
/workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.4036852522
/workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.2769235412
/workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.4128047900
/workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.2663724587
/workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.1418262492
/workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.2497397826
/workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.3983348076
/workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.2078000615
/workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.344694344
/workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.2375741148
/workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.374513776
/workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.2229469365
/workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.1541313283
/workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.2577382376
/workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.3818628188
/workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.2152806902
/workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.1869381026
/workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.709129732
/workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.824247437
/workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.4248082930
/workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.4261544648
/workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.281260664
/workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.681922191
/workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.2269773938
/workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.1913601194
/workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.2994252867
/workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.1853630764
/workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.4237746298
/workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.3159650273
/workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.4055211038
/workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.355986422
/workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.4054039996
/workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.474376475
/workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.729866311
/workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.1651363303
/workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.2775253010
/workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.696796807
/workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.1286709639
/workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.3647301498
/workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.4050600024
/workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.1072913443
/workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.2736937436
/workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.1935493286
/workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.3496877755
/workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.1932509152
/workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.1402964754
/workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.3821914941
/workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.1140648526



Total test records in report: 200
tests.html | tests1.html | tests2.html | tests3.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.3496877755 Jul 05 04:33:22 PM PDT 24 Jul 05 04:33:36 PM PDT 24 1376530000 ps
T2 /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.2769235412 Jul 05 04:33:39 PM PDT 24 Jul 05 04:33:52 PM PDT 24 1498090000 ps
T3 /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.709129732 Jul 05 04:33:38 PM PDT 24 Jul 05 04:33:48 PM PDT 24 1416030000 ps
T7 /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.3983348076 Jul 05 04:33:27 PM PDT 24 Jul 05 04:33:40 PM PDT 24 1520090000 ps
T8 /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.696796807 Jul 05 04:33:45 PM PDT 24 Jul 05 04:33:56 PM PDT 24 1436750000 ps
T9 /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.3705568877 Jul 05 04:33:39 PM PDT 24 Jul 05 04:33:49 PM PDT 24 1545370000 ps
T10 /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.681922191 Jul 05 04:33:41 PM PDT 24 Jul 05 04:33:53 PM PDT 24 1600010000 ps
T11 /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.1913601194 Jul 05 04:33:32 PM PDT 24 Jul 05 04:33:44 PM PDT 24 1318130000 ps
T12 /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.4036852522 Jul 05 04:33:35 PM PDT 24 Jul 05 04:33:48 PM PDT 24 1597990000 ps
T13 /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.4054039996 Jul 05 04:33:42 PM PDT 24 Jul 05 04:33:51 PM PDT 24 1485250000 ps
T31 /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.3159650273 Jul 05 04:33:41 PM PDT 24 Jul 05 04:33:53 PM PDT 24 1458090000 ps
T32 /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.3818628188 Jul 05 04:33:33 PM PDT 24 Jul 05 04:33:43 PM PDT 24 1355930000 ps
T33 /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.2375741148 Jul 05 04:33:43 PM PDT 24 Jul 05 04:33:51 PM PDT 24 1496750000 ps
T34 /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.1418262492 Jul 05 04:33:20 PM PDT 24 Jul 05 04:33:33 PM PDT 24 1202710000 ps
T35 /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.1869381026 Jul 05 04:33:40 PM PDT 24 Jul 05 04:33:48 PM PDT 24 1499350000 ps
T36 /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.1651363303 Jul 05 04:33:41 PM PDT 24 Jul 05 04:33:52 PM PDT 24 1334910000 ps
T37 /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.1935493286 Jul 05 04:33:40 PM PDT 24 Jul 05 04:33:49 PM PDT 24 1452370000 ps
T38 /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.3647301498 Jul 05 04:33:41 PM PDT 24 Jul 05 04:33:50 PM PDT 24 1185470000 ps
T39 /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.355986422 Jul 05 04:33:41 PM PDT 24 Jul 05 04:33:50 PM PDT 24 1477650000 ps
T40 /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.4248082930 Jul 05 04:33:26 PM PDT 24 Jul 05 04:33:37 PM PDT 24 1128330000 ps
T41 /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.2269773938 Jul 05 04:33:42 PM PDT 24 Jul 05 04:33:52 PM PDT 24 1102010000 ps
T42 /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.1541313283 Jul 05 04:33:28 PM PDT 24 Jul 05 04:33:42 PM PDT 24 1631990000 ps
T43 /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.374513776 Jul 05 04:33:38 PM PDT 24 Jul 05 04:33:45 PM PDT 24 1361910000 ps
T44 /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.4050600024 Jul 05 04:33:31 PM PDT 24 Jul 05 04:33:41 PM PDT 24 1413890000 ps
T45 /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.2577382376 Jul 05 04:33:26 PM PDT 24 Jul 05 04:33:44 PM PDT 24 1566950000 ps
T46 /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.4128047900 Jul 05 04:33:19 PM PDT 24 Jul 05 04:33:35 PM PDT 24 1484490000 ps
T47 /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.4261544648 Jul 05 04:33:40 PM PDT 24 Jul 05 04:33:49 PM PDT 24 1420530000 ps
T48 /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.4237746298 Jul 05 04:33:44 PM PDT 24 Jul 05 04:33:52 PM PDT 24 1120830000 ps
T49 /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.2736937436 Jul 05 04:33:42 PM PDT 24 Jul 05 04:33:49 PM PDT 24 1304310000 ps
T50 /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.474376475 Jul 05 04:33:24 PM PDT 24 Jul 05 04:33:42 PM PDT 24 1534590000 ps
T51 /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.4055211038 Jul 05 04:33:35 PM PDT 24 Jul 05 04:33:43 PM PDT 24 1395970000 ps
T52 /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.1821933980 Jul 05 04:33:22 PM PDT 24 Jul 05 04:33:35 PM PDT 24 1364090000 ps
T53 /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.729866311 Jul 05 04:33:32 PM PDT 24 Jul 05 04:33:42 PM PDT 24 1565070000 ps
T54 /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.3821914941 Jul 05 04:33:39 PM PDT 24 Jul 05 04:33:47 PM PDT 24 1456450000 ps
T55 /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.1286709639 Jul 05 04:34:10 PM PDT 24 Jul 05 04:34:21 PM PDT 24 1218430000 ps
T56 /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.1932509152 Jul 05 04:33:20 PM PDT 24 Jul 05 04:33:33 PM PDT 24 1514790000 ps
T57 /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.2994252867 Jul 05 04:33:45 PM PDT 24 Jul 05 04:33:57 PM PDT 24 1210970000 ps
T58 /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.281260664 Jul 05 04:33:33 PM PDT 24 Jul 05 04:33:44 PM PDT 24 1490090000 ps
T59 /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.1402964754 Jul 05 04:33:42 PM PDT 24 Jul 05 04:33:51 PM PDT 24 1362410000 ps
T60 /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.2078000615 Jul 05 04:33:40 PM PDT 24 Jul 05 04:33:47 PM PDT 24 1073150000 ps
T61 /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.824247437 Jul 05 04:33:41 PM PDT 24 Jul 05 04:33:52 PM PDT 24 1482950000 ps
T62 /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.2229469365 Jul 05 04:33:39 PM PDT 24 Jul 05 04:33:50 PM PDT 24 1584850000 ps
T63 /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.2152806902 Jul 05 04:33:28 PM PDT 24 Jul 05 04:33:39 PM PDT 24 1429610000 ps
T64 /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.2663724587 Jul 05 04:33:39 PM PDT 24 Jul 05 04:33:45 PM PDT 24 1116490000 ps
T65 /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.2497397826 Jul 05 04:33:42 PM PDT 24 Jul 05 04:33:52 PM PDT 24 1080750000 ps
T66 /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.1140648526 Jul 05 04:33:26 PM PDT 24 Jul 05 04:33:41 PM PDT 24 1389230000 ps
T67 /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.1853630764 Jul 05 04:33:31 PM PDT 24 Jul 05 04:33:42 PM PDT 24 1529770000 ps
T68 /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.1072913443 Jul 05 04:33:44 PM PDT 24 Jul 05 04:33:54 PM PDT 24 1577130000 ps
T69 /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.2775253010 Jul 05 04:33:31 PM PDT 24 Jul 05 04:33:43 PM PDT 24 1414910000 ps
T70 /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.344694344 Jul 05 04:33:37 PM PDT 24 Jul 05 04:33:45 PM PDT 24 1237930000 ps
T4 /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.3483069457 Jul 05 04:33:19 PM PDT 24 Jul 05 05:08:11 PM PDT 24 336356010000 ps
T5 /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.3441315235 Jul 05 04:33:20 PM PDT 24 Jul 05 05:01:49 PM PDT 24 336975790000 ps
T6 /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.2447846812 Jul 05 04:33:18 PM PDT 24 Jul 05 05:08:13 PM PDT 24 336708930000 ps
T14 /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1060018447 Jul 05 04:33:22 PM PDT 24 Jul 05 05:03:31 PM PDT 24 336626590000 ps
T15 /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.338596075 Jul 05 04:33:28 PM PDT 24 Jul 05 05:09:18 PM PDT 24 336410890000 ps
T16 /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.2556636462 Jul 05 04:33:35 PM PDT 24 Jul 05 05:07:43 PM PDT 24 336520090000 ps
T17 /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.2717918446 Jul 05 04:33:35 PM PDT 24 Jul 05 05:08:50 PM PDT 24 336678190000 ps
T18 /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.1649612309 Jul 05 04:33:29 PM PDT 24 Jul 05 05:02:03 PM PDT 24 336911830000 ps
T19 /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.3053635157 Jul 05 04:33:19 PM PDT 24 Jul 05 05:08:47 PM PDT 24 336722010000 ps
T20 /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.2319917760 Jul 05 04:33:22 PM PDT 24 Jul 05 05:07:17 PM PDT 24 336477850000 ps
T71 /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.2160340971 Jul 05 04:33:34 PM PDT 24 Jul 05 05:10:51 PM PDT 24 336354830000 ps
T72 /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.1372508457 Jul 05 04:33:21 PM PDT 24 Jul 05 05:04:32 PM PDT 24 336622450000 ps
T73 /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.2027151430 Jul 05 04:33:27 PM PDT 24 Jul 05 05:04:46 PM PDT 24 337023830000 ps
T74 /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.2466252992 Jul 05 04:33:22 PM PDT 24 Jul 05 05:06:44 PM PDT 24 336678670000 ps
T75 /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.3522343774 Jul 05 04:33:22 PM PDT 24 Jul 05 05:08:50 PM PDT 24 336336010000 ps
T76 /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.3193022933 Jul 05 04:33:22 PM PDT 24 Jul 05 05:07:05 PM PDT 24 336328790000 ps
T77 /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.1654623505 Jul 05 04:33:36 PM PDT 24 Jul 05 05:16:23 PM PDT 24 336518490000 ps
T78 /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.3865218481 Jul 05 04:33:18 PM PDT 24 Jul 05 05:07:17 PM PDT 24 336608090000 ps
T79 /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.1885256194 Jul 05 04:33:24 PM PDT 24 Jul 05 05:15:26 PM PDT 24 336646330000 ps
T80 /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.2827948609 Jul 05 04:33:28 PM PDT 24 Jul 05 05:07:00 PM PDT 24 336737010000 ps
T81 /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.3299084145 Jul 05 04:33:15 PM PDT 24 Jul 05 05:06:42 PM PDT 24 336369230000 ps
T82 /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.2317310595 Jul 05 04:33:21 PM PDT 24 Jul 05 05:08:52 PM PDT 24 336548190000 ps
T83 /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.210203778 Jul 05 04:33:35 PM PDT 24 Jul 05 05:11:21 PM PDT 24 336316090000 ps
T84 /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.1526475758 Jul 05 04:33:24 PM PDT 24 Jul 05 05:14:29 PM PDT 24 336552270000 ps
T85 /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.1269345153 Jul 05 04:33:12 PM PDT 24 Jul 05 05:06:53 PM PDT 24 336482070000 ps
T86 /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.487914584 Jul 05 04:33:25 PM PDT 24 Jul 05 05:15:41 PM PDT 24 336700970000 ps
T87 /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.835542289 Jul 05 04:33:22 PM PDT 24 Jul 05 05:15:01 PM PDT 24 336820050000 ps
T88 /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.3994810901 Jul 05 04:33:26 PM PDT 24 Jul 05 05:08:18 PM PDT 24 336795630000 ps
T89 /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.3863450186 Jul 05 04:33:35 PM PDT 24 Jul 05 05:04:57 PM PDT 24 336526090000 ps
T90 /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.2638287367 Jul 05 04:33:26 PM PDT 24 Jul 05 05:07:56 PM PDT 24 336470290000 ps
T91 /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.1899608503 Jul 05 04:33:24 PM PDT 24 Jul 05 05:14:31 PM PDT 24 336620270000 ps
T92 /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.635637222 Jul 05 04:33:22 PM PDT 24 Jul 05 05:16:46 PM PDT 24 336480930000 ps
T93 /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.3961213779 Jul 05 04:33:17 PM PDT 24 Jul 05 05:03:38 PM PDT 24 336785390000 ps
T94 /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.3019584239 Jul 05 04:33:27 PM PDT 24 Jul 05 05:07:56 PM PDT 24 336943710000 ps
T95 /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.1853976546 Jul 05 04:33:23 PM PDT 24 Jul 05 05:09:05 PM PDT 24 336696190000 ps
T96 /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.662614468 Jul 05 04:33:26 PM PDT 24 Jul 05 05:16:32 PM PDT 24 336636190000 ps
T97 /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.1622681543 Jul 05 04:33:29 PM PDT 24 Jul 05 05:16:46 PM PDT 24 336963190000 ps
T98 /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.1440904351 Jul 05 04:33:19 PM PDT 24 Jul 05 05:16:59 PM PDT 24 336998750000 ps
T99 /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.824514030 Jul 05 04:33:23 PM PDT 24 Jul 05 05:04:53 PM PDT 24 336437890000 ps
T100 /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.3729892338 Jul 05 04:33:25 PM PDT 24 Jul 05 05:04:46 PM PDT 24 336813790000 ps
T101 /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.2423301449 Jul 05 04:33:32 PM PDT 24 Jul 05 05:15:18 PM PDT 24 336362330000 ps
T102 /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.2707981738 Jul 05 04:33:38 PM PDT 24 Jul 05 05:07:52 PM PDT 24 336444510000 ps
T103 /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.2883968046 Jul 05 04:33:19 PM PDT 24 Jul 05 05:08:14 PM PDT 24 336789770000 ps
T104 /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.1339992163 Jul 05 04:33:38 PM PDT 24 Jul 05 05:08:21 PM PDT 24 336700950000 ps
T105 /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.3721171847 Jul 05 04:33:22 PM PDT 24 Jul 05 05:17:13 PM PDT 24 336813210000 ps
T106 /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.2665832057 Jul 05 04:33:27 PM PDT 24 Jul 05 05:07:55 PM PDT 24 336793950000 ps
T107 /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.1168394563 Jul 05 04:33:19 PM PDT 24 Jul 05 05:12:59 PM PDT 24 336958770000 ps
T108 /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.1309955217 Jul 05 04:33:33 PM PDT 24 Jul 05 05:07:49 PM PDT 24 336521070000 ps
T109 /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.3362893925 Jul 05 04:33:34 PM PDT 24 Jul 05 05:05:31 PM PDT 24 336641410000 ps
T110 /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.1913388279 Jul 05 04:33:26 PM PDT 24 Jul 05 05:07:24 PM PDT 24 337010350000 ps
T111 /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.1207671429 Jul 05 04:33:45 PM PDT 24 Jul 05 04:33:55 PM PDT 24 1376550000 ps
T112 /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.3809453646 Jul 05 04:33:44 PM PDT 24 Jul 05 04:33:54 PM PDT 24 1263050000 ps
T113 /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.1788100409 Jul 05 04:33:43 PM PDT 24 Jul 05 04:33:58 PM PDT 24 1441750000 ps
T114 /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3848429275 Jul 05 04:33:46 PM PDT 24 Jul 05 04:33:59 PM PDT 24 1408770000 ps
T115 /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.3620891683 Jul 05 04:34:02 PM PDT 24 Jul 05 04:34:12 PM PDT 24 1462250000 ps
T116 /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.2654117203 Jul 05 04:33:46 PM PDT 24 Jul 05 04:33:55 PM PDT 24 1084550000 ps
T117 /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.1432951559 Jul 05 04:33:41 PM PDT 24 Jul 05 04:33:52 PM PDT 24 1415670000 ps
T118 /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.4033047738 Jul 05 04:33:43 PM PDT 24 Jul 05 04:33:54 PM PDT 24 1425790000 ps
T119 /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.3683366301 Jul 05 04:33:43 PM PDT 24 Jul 05 04:33:58 PM PDT 24 1312890000 ps
T120 /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.3033224356 Jul 05 04:33:52 PM PDT 24 Jul 05 04:33:58 PM PDT 24 1080570000 ps
T121 /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.2917327939 Jul 05 04:33:43 PM PDT 24 Jul 05 04:33:55 PM PDT 24 1571230000 ps
T122 /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.3692849980 Jul 05 04:33:54 PM PDT 24 Jul 05 04:34:05 PM PDT 24 1333450000 ps
T123 /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.3196909445 Jul 05 04:33:59 PM PDT 24 Jul 05 04:34:09 PM PDT 24 1523790000 ps
T124 /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.4044228877 Jul 05 04:34:00 PM PDT 24 Jul 05 04:34:11 PM PDT 24 1303010000 ps
T125 /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.1549054937 Jul 05 04:33:43 PM PDT 24 Jul 05 04:33:57 PM PDT 24 1414530000 ps
T126 /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.2848021101 Jul 05 04:34:02 PM PDT 24 Jul 05 04:34:12 PM PDT 24 1597570000 ps
T127 /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.2673129684 Jul 05 04:33:43 PM PDT 24 Jul 05 04:33:57 PM PDT 24 1542870000 ps
T128 /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.1726597658 Jul 05 04:33:44 PM PDT 24 Jul 05 04:33:56 PM PDT 24 1547530000 ps
T129 /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.3600268550 Jul 05 04:34:05 PM PDT 24 Jul 05 04:34:19 PM PDT 24 1574110000 ps
T130 /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.984518712 Jul 05 04:33:45 PM PDT 24 Jul 05 04:33:58 PM PDT 24 1275990000 ps
T131 /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.3467056390 Jul 05 04:33:44 PM PDT 24 Jul 05 04:33:54 PM PDT 24 1417970000 ps
T132 /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.896711359 Jul 05 04:33:28 PM PDT 24 Jul 05 04:33:45 PM PDT 24 1545250000 ps
T133 /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.830502138 Jul 05 04:33:47 PM PDT 24 Jul 05 04:33:58 PM PDT 24 1565330000 ps
T134 /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.134645625 Jul 05 04:34:04 PM PDT 24 Jul 05 04:34:15 PM PDT 24 1548710000 ps
T135 /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.2680862408 Jul 05 04:33:51 PM PDT 24 Jul 05 04:33:58 PM PDT 24 1218190000 ps
T136 /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.1071256394 Jul 05 04:33:45 PM PDT 24 Jul 05 04:33:56 PM PDT 24 1329250000 ps
T137 /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.1803030618 Jul 05 04:33:40 PM PDT 24 Jul 05 04:33:51 PM PDT 24 1426510000 ps
T138 /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.1134181052 Jul 05 04:33:59 PM PDT 24 Jul 05 04:34:13 PM PDT 24 1458930000 ps
T139 /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.572869542 Jul 05 04:33:49 PM PDT 24 Jul 05 04:33:58 PM PDT 24 1645510000 ps
T140 /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.1433094059 Jul 05 04:33:58 PM PDT 24 Jul 05 04:34:08 PM PDT 24 1489830000 ps
T141 /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.355634326 Jul 05 04:33:46 PM PDT 24 Jul 05 04:33:57 PM PDT 24 1384830000 ps
T142 /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.3986712466 Jul 05 04:33:44 PM PDT 24 Jul 05 04:33:55 PM PDT 24 1290590000 ps
T143 /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.2139817566 Jul 05 04:33:56 PM PDT 24 Jul 05 04:34:06 PM PDT 24 1362790000 ps
T144 /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.3324109920 Jul 05 04:33:43 PM PDT 24 Jul 05 04:33:52 PM PDT 24 1366430000 ps
T145 /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.459284060 Jul 05 04:33:47 PM PDT 24 Jul 05 04:33:57 PM PDT 24 1243150000 ps
T146 /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.212760548 Jul 05 04:33:47 PM PDT 24 Jul 05 04:33:57 PM PDT 24 1306190000 ps
T147 /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.1343109505 Jul 05 04:33:47 PM PDT 24 Jul 05 04:33:57 PM PDT 24 1165090000 ps
T148 /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.2844375532 Jul 05 04:33:45 PM PDT 24 Jul 05 04:34:00 PM PDT 24 1571370000 ps
T149 /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.3760669784 Jul 05 04:34:17 PM PDT 24 Jul 05 04:34:29 PM PDT 24 1404510000 ps
T150 /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1406477111 Jul 05 04:33:44 PM PDT 24 Jul 05 04:33:56 PM PDT 24 1563390000 ps
T151 /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.1714689914 Jul 05 04:33:45 PM PDT 24 Jul 05 04:33:57 PM PDT 24 1495910000 ps
T152 /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.3439949088 Jul 05 04:33:45 PM PDT 24 Jul 05 04:33:55 PM PDT 24 1455490000 ps
T153 /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.2465651385 Jul 05 04:33:44 PM PDT 24 Jul 05 04:33:56 PM PDT 24 1448950000 ps
T154 /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.174359535 Jul 05 04:33:48 PM PDT 24 Jul 05 04:33:55 PM PDT 24 1099890000 ps
T155 /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.232265155 Jul 05 04:33:45 PM PDT 24 Jul 05 04:33:55 PM PDT 24 1438030000 ps
T156 /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.1836411691 Jul 05 04:33:43 PM PDT 24 Jul 05 04:33:56 PM PDT 24 1350930000 ps
T157 /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.2933567741 Jul 05 04:33:43 PM PDT 24 Jul 05 04:33:57 PM PDT 24 1488390000 ps
T158 /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.3814808715 Jul 05 04:33:52 PM PDT 24 Jul 05 04:34:01 PM PDT 24 1594450000 ps
T159 /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.3835973569 Jul 05 04:34:05 PM PDT 24 Jul 05 04:34:17 PM PDT 24 1510850000 ps
T160 /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.3641784312 Jul 05 04:33:46 PM PDT 24 Jul 05 04:33:57 PM PDT 24 1551770000 ps
T21 /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.2656367871 Jul 05 04:34:12 PM PDT 24 Jul 05 05:15:56 PM PDT 24 336411170000 ps
T22 /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.2612317647 Jul 05 04:34:24 PM PDT 24 Jul 05 05:07:57 PM PDT 24 336617350000 ps
T23 /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.4122767419 Jul 05 04:34:16 PM PDT 24 Jul 05 05:08:05 PM PDT 24 336898530000 ps
T24 /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.3671105881 Jul 05 04:34:14 PM PDT 24 Jul 05 05:08:26 PM PDT 24 336917170000 ps
T25 /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.528368169 Jul 05 04:34:26 PM PDT 24 Jul 05 05:07:51 PM PDT 24 336555770000 ps
T26 /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.3350715664 Jul 05 04:34:27 PM PDT 24 Jul 05 05:11:02 PM PDT 24 336959170000 ps
T27 /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.3329847906 Jul 05 04:34:08 PM PDT 24 Jul 05 05:17:43 PM PDT 24 336447650000 ps
T28 /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.2477951187 Jul 05 04:34:14 PM PDT 24 Jul 05 05:12:45 PM PDT 24 336916310000 ps
T29 /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.1272311346 Jul 05 04:34:19 PM PDT 24 Jul 05 05:10:30 PM PDT 24 336946710000 ps
T30 /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.380283697 Jul 05 04:34:29 PM PDT 24 Jul 05 05:04:47 PM PDT 24 336521610000 ps
T161 /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.2546245253 Jul 05 04:34:18 PM PDT 24 Jul 05 05:11:52 PM PDT 24 337111330000 ps
T162 /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.3389093559 Jul 05 04:34:27 PM PDT 24 Jul 05 05:04:43 PM PDT 24 337068990000 ps
T163 /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.3315908322 Jul 05 04:34:17 PM PDT 24 Jul 05 05:01:04 PM PDT 24 336655510000 ps
T164 /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.617152288 Jul 05 04:34:14 PM PDT 24 Jul 05 05:14:59 PM PDT 24 336335790000 ps
T165 /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.3907799718 Jul 05 04:34:25 PM PDT 24 Jul 05 05:03:13 PM PDT 24 336874210000 ps
T166 /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.3931761048 Jul 05 04:34:28 PM PDT 24 Jul 05 05:03:45 PM PDT 24 336811690000 ps
T167 /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.1825842456 Jul 05 04:34:13 PM PDT 24 Jul 05 05:09:48 PM PDT 24 336892510000 ps
T168 /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.805291949 Jul 05 04:34:12 PM PDT 24 Jul 05 05:16:16 PM PDT 24 336780910000 ps
T169 /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.1016412021 Jul 05 04:34:32 PM PDT 24 Jul 05 05:11:05 PM PDT 24 337019130000 ps
T170 /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.6012025 Jul 05 04:34:14 PM PDT 24 Jul 05 05:11:48 PM PDT 24 336402430000 ps
T171 /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.777783679 Jul 05 04:34:12 PM PDT 24 Jul 05 05:08:38 PM PDT 24 336883530000 ps
T172 /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.3597958022 Jul 05 04:34:19 PM PDT 24 Jul 05 05:06:29 PM PDT 24 337066490000 ps
T173 /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.4160984269 Jul 05 04:34:15 PM PDT 24 Jul 05 05:08:02 PM PDT 24 336699230000 ps
T174 /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.3630688995 Jul 05 04:34:25 PM PDT 24 Jul 05 04:57:36 PM PDT 24 336441170000 ps
T175 /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.3699622659 Jul 05 04:34:14 PM PDT 24 Jul 05 05:09:06 PM PDT 24 336738110000 ps
T176 /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.3828913583 Jul 05 04:34:27 PM PDT 24 Jul 05 05:12:34 PM PDT 24 336394710000 ps
T177 /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.3976592885 Jul 05 04:34:23 PM PDT 24 Jul 05 05:06:14 PM PDT 24 336643090000 ps
T178 /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.4183456178 Jul 05 04:34:13 PM PDT 24 Jul 05 05:08:20 PM PDT 24 336897850000 ps
T179 /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.994333471 Jul 05 04:34:12 PM PDT 24 Jul 05 05:01:56 PM PDT 24 336673510000 ps
T180 /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.1798308450 Jul 05 04:34:18 PM PDT 24 Jul 05 05:13:55 PM PDT 24 336668470000 ps
T181 /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.943457003 Jul 05 04:34:11 PM PDT 24 Jul 05 05:12:05 PM PDT 24 337010610000 ps
T182 /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.897014515 Jul 05 04:34:29 PM PDT 24 Jul 05 05:09:13 PM PDT 24 336537010000 ps
T183 /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.1758555346 Jul 05 04:34:35 PM PDT 24 Jul 05 05:08:16 PM PDT 24 337102990000 ps
T184 /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.4231247029 Jul 05 04:34:13 PM PDT 24 Jul 05 05:13:39 PM PDT 24 336530530000 ps
T185 /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.1304214463 Jul 05 04:34:16 PM PDT 24 Jul 05 05:13:45 PM PDT 24 336457390000 ps
T186 /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.252556362 Jul 05 04:34:13 PM PDT 24 Jul 05 05:09:02 PM PDT 24 336683970000 ps
T187 /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.2398639612 Jul 05 04:34:13 PM PDT 24 Jul 05 05:00:38 PM PDT 24 336375130000 ps
T188 /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3437079759 Jul 05 04:34:23 PM PDT 24 Jul 05 05:02:00 PM PDT 24 336602750000 ps
T189 /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.2749519552 Jul 05 04:34:18 PM PDT 24 Jul 05 05:08:57 PM PDT 24 336562930000 ps
T190 /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.1236837027 Jul 05 04:34:09 PM PDT 24 Jul 05 05:17:46 PM PDT 24 336684550000 ps
T191 /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.263005539 Jul 05 04:34:13 PM PDT 24 Jul 05 05:10:03 PM PDT 24 336849250000 ps
T192 /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.3013974685 Jul 05 04:34:11 PM PDT 24 Jul 05 05:01:51 PM PDT 24 336480490000 ps
T193 /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.1514316143 Jul 05 04:34:29 PM PDT 24 Jul 05 05:08:22 PM PDT 24 336953290000 ps
T194 /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.2608956606 Jul 05 04:34:29 PM PDT 24 Jul 05 05:09:02 PM PDT 24 337156190000 ps
T195 /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.2358208446 Jul 05 04:34:40 PM PDT 24 Jul 05 05:10:15 PM PDT 24 336943310000 ps
T196 /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.700489198 Jul 05 04:34:12 PM PDT 24 Jul 05 05:02:39 PM PDT 24 336710250000 ps
T197 /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.277761771 Jul 05 04:34:14 PM PDT 24 Jul 05 05:13:02 PM PDT 24 336818790000 ps
T198 /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.3796433153 Jul 05 04:34:12 PM PDT 24 Jul 05 05:05:13 PM PDT 24 336615130000 ps
T199 /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.377549245 Jul 05 04:34:35 PM PDT 24 Jul 05 05:09:06 PM PDT 24 336725330000 ps
T200 /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.2598606875 Jul 05 04:34:14 PM PDT 24 Jul 05 05:08:00 PM PDT 24 336783530000 ps

Test location /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.3705568877
Short name T9
Test name
Test status
Simulation time 1545370000 ps
CPU time 4.17 seconds
Started Jul 05 04:33:39 PM PDT 24
Finished Jul 05 04:33:49 PM PDT 24
Peak memory 164892 kb
Host smart-6732faae-a7d5-4ac3-acc6-ffef225f99d8
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3705568877 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.3705568877
Directory /workspace/0.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.3441315235
Short name T5
Test name
Test status
Simulation time 336975790000 ps
CPU time 694.69 seconds
Started Jul 05 04:33:20 PM PDT 24
Finished Jul 05 05:01:49 PM PDT 24
Peak memory 160708 kb
Host smart-65550652-9786-4c27-881c-096eb80ecf8f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3441315235 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.3441315235
Directory /workspace/1.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.4122767419
Short name T23
Test name
Test status
Simulation time 336898530000 ps
CPU time 807.65 seconds
Started Jul 05 04:34:16 PM PDT 24
Finished Jul 05 05:08:05 PM PDT 24
Peak memory 160712 kb
Host smart-c063ae63-51ed-4de4-8ebb-c69687a4d25c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4122767419 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.4122767419
Directory /workspace/12.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.1654623505
Short name T77
Test name
Test status
Simulation time 336518490000 ps
CPU time 1014.78 seconds
Started Jul 05 04:33:36 PM PDT 24
Finished Jul 05 05:16:23 PM PDT 24
Peak memory 160764 kb
Host smart-3ed98821-cf1e-404e-af34-8cc08996e5a8
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1654623505 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.1654623505
Directory /workspace/0.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.1885256194
Short name T79
Test name
Test status
Simulation time 336646330000 ps
CPU time 987.05 seconds
Started Jul 05 04:33:24 PM PDT 24
Finished Jul 05 05:15:26 PM PDT 24
Peak memory 160700 kb
Host smart-f9928da0-d296-4aba-970f-a591387a4517
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1885256194 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.1885256194
Directory /workspace/10.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.2447846812
Short name T6
Test name
Test status
Simulation time 336708930000 ps
CPU time 834.27 seconds
Started Jul 05 04:33:18 PM PDT 24
Finished Jul 05 05:08:13 PM PDT 24
Peak memory 160708 kb
Host smart-0a38a67a-f9eb-47a6-b0f3-9808637ae26e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2447846812 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.2447846812
Directory /workspace/11.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.3483069457
Short name T4
Test name
Test status
Simulation time 336356010000 ps
CPU time 826.58 seconds
Started Jul 05 04:33:19 PM PDT 24
Finished Jul 05 05:08:11 PM PDT 24
Peak memory 160788 kb
Host smart-8ed51751-d86f-45f8-ad2a-a7d2d9cd311c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3483069457 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.3483069457
Directory /workspace/12.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.2027151430
Short name T73
Test name
Test status
Simulation time 337023830000 ps
CPU time 760.7 seconds
Started Jul 05 04:33:27 PM PDT 24
Finished Jul 05 05:04:46 PM PDT 24
Peak memory 160676 kb
Host smart-c5faf70d-b9ab-4219-a89a-48670841f15d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2027151430 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.2027151430
Directory /workspace/13.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.2423301449
Short name T101
Test name
Test status
Simulation time 336362330000 ps
CPU time 983.59 seconds
Started Jul 05 04:33:32 PM PDT 24
Finished Jul 05 05:15:18 PM PDT 24
Peak memory 160776 kb
Host smart-6d13a9c7-4ccc-4fe1-8a1c-3d9dcd380360
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2423301449 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.2423301449
Directory /workspace/14.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.1899608503
Short name T91
Test name
Test status
Simulation time 336620270000 ps
CPU time 993.84 seconds
Started Jul 05 04:33:24 PM PDT 24
Finished Jul 05 05:14:31 PM PDT 24
Peak memory 160736 kb
Host smart-afc0989c-0aff-4061-9be3-1a39cd6b0390
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1899608503 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.1899608503
Directory /workspace/15.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.1913388279
Short name T110
Test name
Test status
Simulation time 337010350000 ps
CPU time 838.83 seconds
Started Jul 05 04:33:26 PM PDT 24
Finished Jul 05 05:07:24 PM PDT 24
Peak memory 160732 kb
Host smart-23acbcf8-9dfd-4409-a21d-8efe300671ec
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1913388279 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.1913388279
Directory /workspace/16.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.2827948609
Short name T80
Test name
Test status
Simulation time 336737010000 ps
CPU time 819.31 seconds
Started Jul 05 04:33:28 PM PDT 24
Finished Jul 05 05:07:00 PM PDT 24
Peak memory 160792 kb
Host smart-7848fcbb-9969-4c87-bf45-5eedd9873e82
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2827948609 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.2827948609
Directory /workspace/17.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.3865218481
Short name T78
Test name
Test status
Simulation time 336608090000 ps
CPU time 809.94 seconds
Started Jul 05 04:33:18 PM PDT 24
Finished Jul 05 05:07:17 PM PDT 24
Peak memory 160708 kb
Host smart-3fdd5c91-6219-41b6-b762-fdc852042f71
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3865218481 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.3865218481
Directory /workspace/18.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.3961213779
Short name T93
Test name
Test status
Simulation time 336785390000 ps
CPU time 743.76 seconds
Started Jul 05 04:33:17 PM PDT 24
Finished Jul 05 05:03:38 PM PDT 24
Peak memory 160716 kb
Host smart-ed1aad7c-0c46-4ca7-a011-54fb4be90310
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3961213779 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.3961213779
Directory /workspace/19.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.1622681543
Short name T97
Test name
Test status
Simulation time 336963190000 ps
CPU time 1039.96 seconds
Started Jul 05 04:33:29 PM PDT 24
Finished Jul 05 05:16:46 PM PDT 24
Peak memory 160764 kb
Host smart-61c10462-6aca-4270-b6ca-7ff5c38e9e24
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1622681543 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.1622681543
Directory /workspace/2.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.3019584239
Short name T94
Test name
Test status
Simulation time 336943710000 ps
CPU time 840.69 seconds
Started Jul 05 04:33:27 PM PDT 24
Finished Jul 05 05:07:56 PM PDT 24
Peak memory 160792 kb
Host smart-b653e6c4-215d-4c9b-99e3-bf36476ceb95
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3019584239 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.3019584239
Directory /workspace/20.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.1853976546
Short name T95
Test name
Test status
Simulation time 336696190000 ps
CPU time 875.43 seconds
Started Jul 05 04:33:23 PM PDT 24
Finished Jul 05 05:09:05 PM PDT 24
Peak memory 160796 kb
Host smart-86b99a00-514c-4458-9dd8-000979be4e4e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1853976546 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.1853976546
Directory /workspace/21.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.3053635157
Short name T19
Test name
Test status
Simulation time 336722010000 ps
CPU time 869.92 seconds
Started Jul 05 04:33:19 PM PDT 24
Finished Jul 05 05:08:47 PM PDT 24
Peak memory 160668 kb
Host smart-2b8797aa-7286-4e56-a73a-feb2dc7db1a7
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3053635157 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.3053635157
Directory /workspace/22.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.2160340971
Short name T71
Test name
Test status
Simulation time 336354830000 ps
CPU time 907.3 seconds
Started Jul 05 04:33:34 PM PDT 24
Finished Jul 05 05:10:51 PM PDT 24
Peak memory 160712 kb
Host smart-eb0f0056-d09a-4da6-978d-4422ef45da9c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2160340971 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.2160340971
Directory /workspace/23.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.2665832057
Short name T106
Test name
Test status
Simulation time 336793950000 ps
CPU time 847.75 seconds
Started Jul 05 04:33:27 PM PDT 24
Finished Jul 05 05:07:55 PM PDT 24
Peak memory 160804 kb
Host smart-13578f87-8686-479d-8890-62232bc74b48
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2665832057 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.2665832057
Directory /workspace/24.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.1168394563
Short name T107
Test name
Test status
Simulation time 336958770000 ps
CPU time 942.5 seconds
Started Jul 05 04:33:19 PM PDT 24
Finished Jul 05 05:12:59 PM PDT 24
Peak memory 160692 kb
Host smart-d43d8ab7-d15f-4666-b25e-02df7bdfd0cd
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1168394563 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.1168394563
Directory /workspace/25.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1060018447
Short name T14
Test name
Test status
Simulation time 336626590000 ps
CPU time 728.65 seconds
Started Jul 05 04:33:22 PM PDT 24
Finished Jul 05 05:03:31 PM PDT 24
Peak memory 160764 kb
Host smart-675cf3fd-0bd8-4b71-81d4-9ba5e1ccb75c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1060018447 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.1060018447
Directory /workspace/26.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.3362893925
Short name T109
Test name
Test status
Simulation time 336641410000 ps
CPU time 783.33 seconds
Started Jul 05 04:33:34 PM PDT 24
Finished Jul 05 05:05:31 PM PDT 24
Peak memory 160768 kb
Host smart-45931229-d801-4419-8c14-ab46b8d62d9f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3362893925 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.3362893925
Directory /workspace/27.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.1526475758
Short name T84
Test name
Test status
Simulation time 336552270000 ps
CPU time 990.47 seconds
Started Jul 05 04:33:24 PM PDT 24
Finished Jul 05 05:14:29 PM PDT 24
Peak memory 160740 kb
Host smart-bacbb31e-4d4a-43d2-a5eb-8063e028c4ac
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1526475758 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.1526475758
Directory /workspace/28.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.2717918446
Short name T17
Test name
Test status
Simulation time 336678190000 ps
CPU time 845.5 seconds
Started Jul 05 04:33:35 PM PDT 24
Finished Jul 05 05:08:50 PM PDT 24
Peak memory 160680 kb
Host smart-1ba8f0c8-f84f-4f9f-ac4e-faae30fd2ed0
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2717918446 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.2717918446
Directory /workspace/29.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.3721171847
Short name T105
Test name
Test status
Simulation time 336813210000 ps
CPU time 1039.21 seconds
Started Jul 05 04:33:22 PM PDT 24
Finished Jul 05 05:17:13 PM PDT 24
Peak memory 160772 kb
Host smart-628adf5e-8d6d-40f2-bc2e-b2f7fb0f195f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3721171847 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.3721171847
Directory /workspace/3.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.2883968046
Short name T103
Test name
Test status
Simulation time 336789770000 ps
CPU time 852.63 seconds
Started Jul 05 04:33:19 PM PDT 24
Finished Jul 05 05:08:14 PM PDT 24
Peak memory 160668 kb
Host smart-686de2b9-3242-4762-ba34-bbd12b683941
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2883968046 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.2883968046
Directory /workspace/30.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.1309955217
Short name T108
Test name
Test status
Simulation time 336521070000 ps
CPU time 823.38 seconds
Started Jul 05 04:33:33 PM PDT 24
Finished Jul 05 05:07:49 PM PDT 24
Peak memory 160716 kb
Host smart-cd11d7f3-9701-46e8-8eff-dc4886040f53
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1309955217 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.1309955217
Directory /workspace/31.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.3193022933
Short name T76
Test name
Test status
Simulation time 336328790000 ps
CPU time 822.45 seconds
Started Jul 05 04:33:22 PM PDT 24
Finished Jul 05 05:07:05 PM PDT 24
Peak memory 160728 kb
Host smart-6717970f-69fa-404e-855e-98864b68c383
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3193022933 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.3193022933
Directory /workspace/32.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.1440904351
Short name T98
Test name
Test status
Simulation time 336998750000 ps
CPU time 1043.55 seconds
Started Jul 05 04:33:19 PM PDT 24
Finished Jul 05 05:16:59 PM PDT 24
Peak memory 160772 kb
Host smart-7a927cd8-1f94-4d58-a1c8-9fb766da683d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1440904351 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.1440904351
Directory /workspace/33.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.3299084145
Short name T81
Test name
Test status
Simulation time 336369230000 ps
CPU time 809.26 seconds
Started Jul 05 04:33:15 PM PDT 24
Finished Jul 05 05:06:42 PM PDT 24
Peak memory 160776 kb
Host smart-b87d024f-8db9-4879-89f9-e35630c0413f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3299084145 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.3299084145
Directory /workspace/34.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.2466252992
Short name T74
Test name
Test status
Simulation time 336678670000 ps
CPU time 813.02 seconds
Started Jul 05 04:33:22 PM PDT 24
Finished Jul 05 05:06:44 PM PDT 24
Peak memory 160712 kb
Host smart-96ac16c3-bbfe-48e0-96aa-caf0dc1c3d68
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2466252992 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.2466252992
Directory /workspace/35.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.1649612309
Short name T18
Test name
Test status
Simulation time 336911830000 ps
CPU time 690.37 seconds
Started Jul 05 04:33:29 PM PDT 24
Finished Jul 05 05:02:03 PM PDT 24
Peak memory 160732 kb
Host smart-099d4503-e627-477e-bed8-faa1db71e203
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1649612309 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.1649612309
Directory /workspace/36.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.2707981738
Short name T102
Test name
Test status
Simulation time 336444510000 ps
CPU time 834.89 seconds
Started Jul 05 04:33:38 PM PDT 24
Finished Jul 05 05:07:52 PM PDT 24
Peak memory 160796 kb
Host smart-3efa0c60-f000-4827-9b8b-1293e414f588
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2707981738 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.2707981738
Directory /workspace/37.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.1372508457
Short name T72
Test name
Test status
Simulation time 336622450000 ps
CPU time 756.27 seconds
Started Jul 05 04:33:21 PM PDT 24
Finished Jul 05 05:04:32 PM PDT 24
Peak memory 160788 kb
Host smart-4a66feb2-e578-498b-95c1-d7b854efb5f2
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1372508457 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.1372508457
Directory /workspace/38.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.210203778
Short name T83
Test name
Test status
Simulation time 336316090000 ps
CPU time 927.89 seconds
Started Jul 05 04:33:35 PM PDT 24
Finished Jul 05 05:11:21 PM PDT 24
Peak memory 160780 kb
Host smart-e4b4982f-da97-4058-9635-9df031a76bc9
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=210203778 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.210203778
Directory /workspace/39.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.487914584
Short name T86
Test name
Test status
Simulation time 336700970000 ps
CPU time 997.54 seconds
Started Jul 05 04:33:25 PM PDT 24
Finished Jul 05 05:15:41 PM PDT 24
Peak memory 160768 kb
Host smart-3b1b55c9-0dec-4f40-9cf2-1bec16e978df
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=487914584 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.487914584
Directory /workspace/4.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.3994810901
Short name T88
Test name
Test status
Simulation time 336795630000 ps
CPU time 838.06 seconds
Started Jul 05 04:33:26 PM PDT 24
Finished Jul 05 05:08:18 PM PDT 24
Peak memory 160720 kb
Host smart-8fc5d3fa-f2f1-472e-89ef-0b4cbb75f5d3
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3994810901 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.3994810901
Directory /workspace/40.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.3522343774
Short name T75
Test name
Test status
Simulation time 336336010000 ps
CPU time 845.46 seconds
Started Jul 05 04:33:22 PM PDT 24
Finished Jul 05 05:08:50 PM PDT 24
Peak memory 160788 kb
Host smart-49c17ad0-f58d-48af-a702-92a24efc315d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3522343774 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.3522343774
Directory /workspace/41.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.1339992163
Short name T104
Test name
Test status
Simulation time 336700950000 ps
CPU time 836.4 seconds
Started Jul 05 04:33:38 PM PDT 24
Finished Jul 05 05:08:21 PM PDT 24
Peak memory 160720 kb
Host smart-3b5c1db5-2038-4a5f-b274-5c4bbae85f89
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1339992163 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.1339992163
Directory /workspace/42.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.338596075
Short name T15
Test name
Test status
Simulation time 336410890000 ps
CPU time 857.69 seconds
Started Jul 05 04:33:28 PM PDT 24
Finished Jul 05 05:09:18 PM PDT 24
Peak memory 160788 kb
Host smart-8b6c3d7e-62f2-447d-8160-c67d473c2ea9
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=338596075 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.338596075
Directory /workspace/43.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.2638287367
Short name T90
Test name
Test status
Simulation time 336470290000 ps
CPU time 849.06 seconds
Started Jul 05 04:33:26 PM PDT 24
Finished Jul 05 05:07:56 PM PDT 24
Peak memory 160792 kb
Host smart-f472842a-879b-436a-84f3-32e73781c5cc
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2638287367 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.2638287367
Directory /workspace/44.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.824514030
Short name T99
Test name
Test status
Simulation time 336437890000 ps
CPU time 765.08 seconds
Started Jul 05 04:33:23 PM PDT 24
Finished Jul 05 05:04:53 PM PDT 24
Peak memory 160788 kb
Host smart-e94fcfd6-1b13-4427-9c92-36822eb5d52e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=824514030 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.824514030
Directory /workspace/45.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.835542289
Short name T87
Test name
Test status
Simulation time 336820050000 ps
CPU time 971.84 seconds
Started Jul 05 04:33:22 PM PDT 24
Finished Jul 05 05:15:01 PM PDT 24
Peak memory 160700 kb
Host smart-8cfe027e-5435-4476-ada8-bfa46be999e7
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=835542289 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.835542289
Directory /workspace/46.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.2319917760
Short name T20
Test name
Test status
Simulation time 336477850000 ps
CPU time 825.99 seconds
Started Jul 05 04:33:22 PM PDT 24
Finished Jul 05 05:07:17 PM PDT 24
Peak memory 160712 kb
Host smart-98a7a4ff-2edd-48d9-815c-b1f54faa54b0
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2319917760 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.2319917760
Directory /workspace/47.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.3863450186
Short name T89
Test name
Test status
Simulation time 336526090000 ps
CPU time 776.22 seconds
Started Jul 05 04:33:35 PM PDT 24
Finished Jul 05 05:04:57 PM PDT 24
Peak memory 160796 kb
Host smart-f7055348-cc26-40b1-8a92-90cef8d7092b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3863450186 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.3863450186
Directory /workspace/48.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.2556636462
Short name T16
Test name
Test status
Simulation time 336520090000 ps
CPU time 824.4 seconds
Started Jul 05 04:33:35 PM PDT 24
Finished Jul 05 05:07:43 PM PDT 24
Peak memory 160796 kb
Host smart-5ac8a605-b038-4456-8c05-d3b8ddfff22f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2556636462 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.2556636462
Directory /workspace/49.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.2317310595
Short name T82
Test name
Test status
Simulation time 336548190000 ps
CPU time 850.39 seconds
Started Jul 05 04:33:21 PM PDT 24
Finished Jul 05 05:08:52 PM PDT 24
Peak memory 160708 kb
Host smart-0d431e27-0b99-4cf7-9a5a-f55bc810fc74
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2317310595 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.2317310595
Directory /workspace/5.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.635637222
Short name T92
Test name
Test status
Simulation time 336480930000 ps
CPU time 1027.5 seconds
Started Jul 05 04:33:22 PM PDT 24
Finished Jul 05 05:16:46 PM PDT 24
Peak memory 160776 kb
Host smart-9cd3f370-6f2d-4ce3-830a-e4648c64ff3a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=635637222 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.635637222
Directory /workspace/6.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.3729892338
Short name T100
Test name
Test status
Simulation time 336813790000 ps
CPU time 765.58 seconds
Started Jul 05 04:33:25 PM PDT 24
Finished Jul 05 05:04:46 PM PDT 24
Peak memory 160664 kb
Host smart-dfd25038-6c89-47e8-a84d-b59ec38445fb
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3729892338 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.3729892338
Directory /workspace/7.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.662614468
Short name T96
Test name
Test status
Simulation time 336636190000 ps
CPU time 1029.57 seconds
Started Jul 05 04:33:26 PM PDT 24
Finished Jul 05 05:16:32 PM PDT 24
Peak memory 160768 kb
Host smart-daa48989-d416-4bf6-8c57-fda69aa2c2ba
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=662614468 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.662614468
Directory /workspace/8.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.1269345153
Short name T85
Test name
Test status
Simulation time 336482070000 ps
CPU time 807.45 seconds
Started Jul 05 04:33:12 PM PDT 24
Finished Jul 05 05:06:53 PM PDT 24
Peak memory 160708 kb
Host smart-2f44353d-a865-488a-b54a-c4f842706bc5
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1269345153 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.1269345153
Directory /workspace/9.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.1304214463
Short name T185
Test name
Test status
Simulation time 336457390000 ps
CPU time 946.44 seconds
Started Jul 05 04:34:16 PM PDT 24
Finished Jul 05 05:13:45 PM PDT 24
Peak memory 160696 kb
Host smart-6637ce85-299d-4673-a752-a5607732f9dc
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1304214463 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.1304214463
Directory /workspace/0.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.263005539
Short name T191
Test name
Test status
Simulation time 336849250000 ps
CPU time 866.4 seconds
Started Jul 05 04:34:13 PM PDT 24
Finished Jul 05 05:10:03 PM PDT 24
Peak memory 160716 kb
Host smart-9c212fe1-c62a-4b0e-860c-fabdfab4e75e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=263005539 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.263005539
Directory /workspace/1.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.2358208446
Short name T195
Test name
Test status
Simulation time 336943310000 ps
CPU time 879.3 seconds
Started Jul 05 04:34:40 PM PDT 24
Finished Jul 05 05:10:15 PM PDT 24
Peak memory 160800 kb
Host smart-4b0af151-586c-4018-858c-4a938507c7a7
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2358208446 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.2358208446
Directory /workspace/10.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.2608956606
Short name T194
Test name
Test status
Simulation time 337156190000 ps
CPU time 840.27 seconds
Started Jul 05 04:34:29 PM PDT 24
Finished Jul 05 05:09:02 PM PDT 24
Peak memory 160796 kb
Host smart-9c58b6e4-ff08-4a51-a6b0-8ff11cfa7703
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2608956606 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.2608956606
Directory /workspace/11.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.277761771
Short name T197
Test name
Test status
Simulation time 336818790000 ps
CPU time 945.98 seconds
Started Jul 05 04:34:14 PM PDT 24
Finished Jul 05 05:13:02 PM PDT 24
Peak memory 160796 kb
Host smart-0af9fab2-1aa5-4c2e-a14b-ddf472897105
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=277761771 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.277761771
Directory /workspace/13.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.994333471
Short name T179
Test name
Test status
Simulation time 336673510000 ps
CPU time 672.75 seconds
Started Jul 05 04:34:12 PM PDT 24
Finished Jul 05 05:01:56 PM PDT 24
Peak memory 160720 kb
Host smart-5bd5d2d2-f623-44c5-ab8e-a22e7f4e164c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=994333471 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.994333471
Directory /workspace/14.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.3350715664
Short name T26
Test name
Test status
Simulation time 336959170000 ps
CPU time 902.46 seconds
Started Jul 05 04:34:27 PM PDT 24
Finished Jul 05 05:11:02 PM PDT 24
Peak memory 160804 kb
Host smart-e8f70663-71c1-4847-b2f7-b0bd576e0c16
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3350715664 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.3350715664
Directory /workspace/15.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.3828913583
Short name T176
Test name
Test status
Simulation time 336394710000 ps
CPU time 928.1 seconds
Started Jul 05 04:34:27 PM PDT 24
Finished Jul 05 05:12:34 PM PDT 24
Peak memory 160804 kb
Host smart-4d9ce984-e165-490c-9f98-e334cc43f4fc
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3828913583 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.3828913583
Directory /workspace/16.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.1236837027
Short name T190
Test name
Test status
Simulation time 336684550000 ps
CPU time 1037.96 seconds
Started Jul 05 04:34:09 PM PDT 24
Finished Jul 05 05:17:46 PM PDT 24
Peak memory 160800 kb
Host smart-3d08bcb4-6866-4797-bfe1-adfe3a9e25c9
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1236837027 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.1236837027
Directory /workspace/17.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.700489198
Short name T196
Test name
Test status
Simulation time 336710250000 ps
CPU time 696.61 seconds
Started Jul 05 04:34:12 PM PDT 24
Finished Jul 05 05:02:39 PM PDT 24
Peak memory 160748 kb
Host smart-d8fee9fb-ff8f-44be-bd2c-461321af9781
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=700489198 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.700489198
Directory /workspace/18.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.3389093559
Short name T162
Test name
Test status
Simulation time 337068990000 ps
CPU time 733.98 seconds
Started Jul 05 04:34:27 PM PDT 24
Finished Jul 05 05:04:43 PM PDT 24
Peak memory 160796 kb
Host smart-f23934aa-240e-4b2b-8f8a-ebed96b1194c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3389093559 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.3389093559
Directory /workspace/19.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.380283697
Short name T30
Test name
Test status
Simulation time 336521610000 ps
CPU time 740.11 seconds
Started Jul 05 04:34:29 PM PDT 24
Finished Jul 05 05:04:47 PM PDT 24
Peak memory 160796 kb
Host smart-61e72cb0-43de-448d-a0ab-cc9bdca3c298
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=380283697 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.380283697
Directory /workspace/2.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.617152288
Short name T164
Test name
Test status
Simulation time 336335790000 ps
CPU time 978.38 seconds
Started Jul 05 04:34:14 PM PDT 24
Finished Jul 05 05:14:59 PM PDT 24
Peak memory 160788 kb
Host smart-0770dc5a-7b51-4e29-9d1e-a252cd68bb57
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=617152288 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.617152288
Directory /workspace/20.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3437079759
Short name T188
Test name
Test status
Simulation time 336602750000 ps
CPU time 667.38 seconds
Started Jul 05 04:34:23 PM PDT 24
Finished Jul 05 05:02:00 PM PDT 24
Peak memory 160808 kb
Host smart-0b305671-104c-483d-9c3b-8f10c048507e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3437079759 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.3437079759
Directory /workspace/21.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.3907799718
Short name T165
Test name
Test status
Simulation time 336874210000 ps
CPU time 707.38 seconds
Started Jul 05 04:34:25 PM PDT 24
Finished Jul 05 05:03:13 PM PDT 24
Peak memory 160804 kb
Host smart-9e3cf824-1c69-4917-8279-a548401a9cf9
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3907799718 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.3907799718
Directory /workspace/22.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.2477951187
Short name T28
Test name
Test status
Simulation time 336916310000 ps
CPU time 932.43 seconds
Started Jul 05 04:34:14 PM PDT 24
Finished Jul 05 05:12:45 PM PDT 24
Peak memory 160796 kb
Host smart-e4783c75-91ba-49a5-8948-682e9a12471c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2477951187 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.2477951187
Directory /workspace/23.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.3671105881
Short name T24
Test name
Test status
Simulation time 336917170000 ps
CPU time 823.37 seconds
Started Jul 05 04:34:14 PM PDT 24
Finished Jul 05 05:08:26 PM PDT 24
Peak memory 160780 kb
Host smart-d7c42e33-ca37-4765-9e0f-e219a50390da
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3671105881 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.3671105881
Directory /workspace/24.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.4231247029
Short name T184
Test name
Test status
Simulation time 336530530000 ps
CPU time 939.78 seconds
Started Jul 05 04:34:13 PM PDT 24
Finished Jul 05 05:13:39 PM PDT 24
Peak memory 160696 kb
Host smart-da9c41f9-f850-4baa-b835-4e62114d40e6
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4231247029 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.4231247029
Directory /workspace/25.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.4160984269
Short name T173
Test name
Test status
Simulation time 336699230000 ps
CPU time 806.92 seconds
Started Jul 05 04:34:15 PM PDT 24
Finished Jul 05 05:08:02 PM PDT 24
Peak memory 160712 kb
Host smart-5bd68a31-57c6-4483-8479-174a291ff212
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4160984269 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.4160984269
Directory /workspace/26.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.3315908322
Short name T163
Test name
Test status
Simulation time 336655510000 ps
CPU time 645.86 seconds
Started Jul 05 04:34:17 PM PDT 24
Finished Jul 05 05:01:04 PM PDT 24
Peak memory 160792 kb
Host smart-7f22102f-5658-4fe2-b656-7d30a8958448
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3315908322 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.3315908322
Directory /workspace/27.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.897014515
Short name T182
Test name
Test status
Simulation time 336537010000 ps
CPU time 839.75 seconds
Started Jul 05 04:34:29 PM PDT 24
Finished Jul 05 05:09:13 PM PDT 24
Peak memory 160676 kb
Host smart-5486a310-7d72-400b-a3bb-1fe53dddf41f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=897014515 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.897014515
Directory /workspace/28.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.777783679
Short name T171
Test name
Test status
Simulation time 336883530000 ps
CPU time 844.72 seconds
Started Jul 05 04:34:12 PM PDT 24
Finished Jul 05 05:08:38 PM PDT 24
Peak memory 160796 kb
Host smart-1734be89-3229-4e2a-b589-54a7c72113c4
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=777783679 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.777783679
Directory /workspace/29.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.528368169
Short name T25
Test name
Test status
Simulation time 336555770000 ps
CPU time 826.8 seconds
Started Jul 05 04:34:26 PM PDT 24
Finished Jul 05 05:07:51 PM PDT 24
Peak memory 160772 kb
Host smart-68519079-622d-43fd-bcae-bf7b7e94d89c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=528368169 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.528368169
Directory /workspace/3.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.377549245
Short name T199
Test name
Test status
Simulation time 336725330000 ps
CPU time 855.92 seconds
Started Jul 05 04:34:35 PM PDT 24
Finished Jul 05 05:09:06 PM PDT 24
Peak memory 160748 kb
Host smart-a5cb3cb4-9f07-4d74-92d9-df7d5fea1672
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=377549245 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.377549245
Directory /workspace/30.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.1798308450
Short name T180
Test name
Test status
Simulation time 336668470000 ps
CPU time 940.98 seconds
Started Jul 05 04:34:18 PM PDT 24
Finished Jul 05 05:13:55 PM PDT 24
Peak memory 160696 kb
Host smart-942336ca-4cba-482d-80e4-8f17612494b8
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1798308450 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.1798308450
Directory /workspace/31.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.4183456178
Short name T178
Test name
Test status
Simulation time 336897850000 ps
CPU time 822.74 seconds
Started Jul 05 04:34:13 PM PDT 24
Finished Jul 05 05:08:20 PM PDT 24
Peak memory 160720 kb
Host smart-4172af68-458d-478c-9a19-2ee3340da40a
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4183456178 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.4183456178
Directory /workspace/32.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.2398639612
Short name T187
Test name
Test status
Simulation time 336375130000 ps
CPU time 631.69 seconds
Started Jul 05 04:34:13 PM PDT 24
Finished Jul 05 05:00:38 PM PDT 24
Peak memory 160712 kb
Host smart-6873bbf0-a638-4080-bc86-653353726872
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2398639612 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.2398639612
Directory /workspace/33.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.3329847906
Short name T27
Test name
Test status
Simulation time 336447650000 ps
CPU time 1041.15 seconds
Started Jul 05 04:34:08 PM PDT 24
Finished Jul 05 05:17:43 PM PDT 24
Peak memory 160800 kb
Host smart-24b0a5a4-2b93-4440-8df4-2b5f817f0c2e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3329847906 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.3329847906
Directory /workspace/34.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.1758555346
Short name T183
Test name
Test status
Simulation time 337102990000 ps
CPU time 818.17 seconds
Started Jul 05 04:34:35 PM PDT 24
Finished Jul 05 05:08:16 PM PDT 24
Peak memory 160732 kb
Host smart-1f87d49c-d89e-4cf4-8017-ab564da31c55
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1758555346 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.1758555346
Directory /workspace/35.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.805291949
Short name T168
Test name
Test status
Simulation time 336780910000 ps
CPU time 992 seconds
Started Jul 05 04:34:12 PM PDT 24
Finished Jul 05 05:16:16 PM PDT 24
Peak memory 160704 kb
Host smart-2f927193-beda-4b3f-961e-e6b4b2dd81fb
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=805291949 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.805291949
Directory /workspace/36.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.3931761048
Short name T166
Test name
Test status
Simulation time 336811690000 ps
CPU time 711.74 seconds
Started Jul 05 04:34:28 PM PDT 24
Finished Jul 05 05:03:45 PM PDT 24
Peak memory 160796 kb
Host smart-8ce10cad-8eae-4fca-813c-f19350b9d716
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3931761048 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.3931761048
Directory /workspace/37.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.1272311346
Short name T29
Test name
Test status
Simulation time 336946710000 ps
CPU time 891.62 seconds
Started Jul 05 04:34:19 PM PDT 24
Finished Jul 05 05:10:30 PM PDT 24
Peak memory 160804 kb
Host smart-82d68037-1325-408e-8e77-0716579814ed
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1272311346 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.1272311346
Directory /workspace/38.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.3976592885
Short name T177
Test name
Test status
Simulation time 336643090000 ps
CPU time 777.83 seconds
Started Jul 05 04:34:23 PM PDT 24
Finished Jul 05 05:06:14 PM PDT 24
Peak memory 160772 kb
Host smart-c88d96ca-d37b-4ddf-b18f-a7724ab66cdc
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3976592885 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.3976592885
Directory /workspace/39.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.3796433153
Short name T198
Test name
Test status
Simulation time 336615130000 ps
CPU time 760.36 seconds
Started Jul 05 04:34:12 PM PDT 24
Finished Jul 05 05:05:13 PM PDT 24
Peak memory 160788 kb
Host smart-e0d0bc77-03bb-480f-8447-e98790d2384b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3796433153 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.3796433153
Directory /workspace/4.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.252556362
Short name T186
Test name
Test status
Simulation time 336683970000 ps
CPU time 846.18 seconds
Started Jul 05 04:34:13 PM PDT 24
Finished Jul 05 05:09:02 PM PDT 24
Peak memory 160796 kb
Host smart-c2fb31aa-b6fa-4e0e-a7b0-6681f18f09a5
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=252556362 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.252556362
Directory /workspace/40.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.2749519552
Short name T189
Test name
Test status
Simulation time 336562930000 ps
CPU time 851.64 seconds
Started Jul 05 04:34:18 PM PDT 24
Finished Jul 05 05:08:57 PM PDT 24
Peak memory 160808 kb
Host smart-c26efe04-5175-4e30-94ae-c5aec9ad2f32
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2749519552 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.2749519552
Directory /workspace/41.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.3013974685
Short name T192
Test name
Test status
Simulation time 336480490000 ps
CPU time 679.22 seconds
Started Jul 05 04:34:11 PM PDT 24
Finished Jul 05 05:01:51 PM PDT 24
Peak memory 160800 kb
Host smart-61399008-b199-4227-bb5c-a29970478773
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3013974685 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.3013974685
Directory /workspace/42.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.2546245253
Short name T161
Test name
Test status
Simulation time 337111330000 ps
CPU time 906.84 seconds
Started Jul 05 04:34:18 PM PDT 24
Finished Jul 05 05:11:52 PM PDT 24
Peak memory 160716 kb
Host smart-913ed113-3560-4e4e-af30-0ddb3df7f7ed
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2546245253 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.2546245253
Directory /workspace/43.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.3597958022
Short name T172
Test name
Test status
Simulation time 337066490000 ps
CPU time 793.67 seconds
Started Jul 05 04:34:19 PM PDT 24
Finished Jul 05 05:06:29 PM PDT 24
Peak memory 160792 kb
Host smart-98a99aca-32e6-492d-a016-f0ba00574e4c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3597958022 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.3597958022
Directory /workspace/44.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.943457003
Short name T181
Test name
Test status
Simulation time 337010610000 ps
CPU time 913.65 seconds
Started Jul 05 04:34:11 PM PDT 24
Finished Jul 05 05:12:05 PM PDT 24
Peak memory 160800 kb
Host smart-3d159b83-6ce3-417f-bc35-57cef557e32a
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=943457003 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.943457003
Directory /workspace/45.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.1016412021
Short name T169
Test name
Test status
Simulation time 337019130000 ps
CPU time 898.68 seconds
Started Jul 05 04:34:32 PM PDT 24
Finished Jul 05 05:11:05 PM PDT 24
Peak memory 160800 kb
Host smart-f3520e20-3e04-4e1b-bda4-38560ef62af4
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1016412021 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.1016412021
Directory /workspace/46.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.1825842456
Short name T167
Test name
Test status
Simulation time 336892510000 ps
CPU time 846.46 seconds
Started Jul 05 04:34:13 PM PDT 24
Finished Jul 05 05:09:48 PM PDT 24
Peak memory 160792 kb
Host smart-ce1dd9cf-fe07-4e9f-a22e-14f181033708
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1825842456 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.1825842456
Directory /workspace/47.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.3630688995
Short name T174
Test name
Test status
Simulation time 336441170000 ps
CPU time 538.5 seconds
Started Jul 05 04:34:25 PM PDT 24
Finished Jul 05 04:57:36 PM PDT 24
Peak memory 160796 kb
Host smart-65482e0d-d065-4217-8fd3-1c7bb091ce39
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3630688995 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.3630688995
Directory /workspace/48.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.2612317647
Short name T22
Test name
Test status
Simulation time 336617350000 ps
CPU time 807.62 seconds
Started Jul 05 04:34:24 PM PDT 24
Finished Jul 05 05:07:57 PM PDT 24
Peak memory 160716 kb
Host smart-e4ebcaee-50d9-4d21-a6ae-2eec46d15a88
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2612317647 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.2612317647
Directory /workspace/49.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.1514316143
Short name T193
Test name
Test status
Simulation time 336953290000 ps
CPU time 822.37 seconds
Started Jul 05 04:34:29 PM PDT 24
Finished Jul 05 05:08:22 PM PDT 24
Peak memory 160784 kb
Host smart-63d1085a-b6e9-4917-8739-b793e2118a71
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1514316143 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.1514316143
Directory /workspace/5.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.6012025
Short name T170
Test name
Test status
Simulation time 336402430000 ps
CPU time 908.98 seconds
Started Jul 05 04:34:14 PM PDT 24
Finished Jul 05 05:11:48 PM PDT 24
Peak memory 160792 kb
Host smart-6443cdc4-f8ce-40e4-bb51-f2649d4778ba
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=6012025 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.6012025
Directory /workspace/6.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.2598606875
Short name T200
Test name
Test status
Simulation time 336783530000 ps
CPU time 806.65 seconds
Started Jul 05 04:34:14 PM PDT 24
Finished Jul 05 05:08:00 PM PDT 24
Peak memory 160780 kb
Host smart-4e4377eb-b413-4b3e-b8cc-fdffde1740c1
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2598606875 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.2598606875
Directory /workspace/7.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.2656367871
Short name T21
Test name
Test status
Simulation time 336411170000 ps
CPU time 978.82 seconds
Started Jul 05 04:34:12 PM PDT 24
Finished Jul 05 05:15:56 PM PDT 24
Peak memory 160704 kb
Host smart-e8da6f17-9edf-451f-8540-2f16b2bda0ab
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2656367871 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.2656367871
Directory /workspace/8.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.3699622659
Short name T175
Test name
Test status
Simulation time 336738110000 ps
CPU time 835.66 seconds
Started Jul 05 04:34:14 PM PDT 24
Finished Jul 05 05:09:06 PM PDT 24
Peak memory 160680 kb
Host smart-20d75a02-6ac4-438b-b02e-b6610f0f7acf
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3699622659 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.3699622659
Directory /workspace/9.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.896711359
Short name T132
Test name
Test status
Simulation time 1545250000 ps
CPU time 5.67 seconds
Started Jul 05 04:33:28 PM PDT 24
Finished Jul 05 04:33:45 PM PDT 24
Peak memory 164876 kb
Host smart-334a4e3f-2e87-4740-8306-3e77de96c001
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=896711359 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.896711359
Directory /workspace/0.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.984518712
Short name T130
Test name
Test status
Simulation time 1275990000 ps
CPU time 4.97 seconds
Started Jul 05 04:33:45 PM PDT 24
Finished Jul 05 04:33:58 PM PDT 24
Peak memory 164932 kb
Host smart-b76d3456-0543-4060-b915-12d4e523f042
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=984518712 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.984518712
Directory /workspace/1.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.1432951559
Short name T117
Test name
Test status
Simulation time 1415670000 ps
CPU time 4.48 seconds
Started Jul 05 04:33:41 PM PDT 24
Finished Jul 05 04:33:52 PM PDT 24
Peak memory 164888 kb
Host smart-fb5d21c2-dd32-43ec-b90c-f9a4f5193972
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1432951559 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.1432951559
Directory /workspace/10.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.232265155
Short name T155
Test name
Test status
Simulation time 1438030000 ps
CPU time 3.18 seconds
Started Jul 05 04:33:45 PM PDT 24
Finished Jul 05 04:33:55 PM PDT 24
Peak memory 164916 kb
Host smart-2bd6aba7-2b32-4cfe-953b-a7c9593a7246
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=232265155 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.232265155
Directory /workspace/11.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.1726597658
Short name T128
Test name
Test status
Simulation time 1547530000 ps
CPU time 4.68 seconds
Started Jul 05 04:33:44 PM PDT 24
Finished Jul 05 04:33:56 PM PDT 24
Peak memory 164880 kb
Host smart-4ef47762-c4c7-468d-84f1-ccd5f0a7ac80
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1726597658 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.1726597658
Directory /workspace/12.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.2933567741
Short name T157
Test name
Test status
Simulation time 1488390000 ps
CPU time 4.91 seconds
Started Jul 05 04:33:43 PM PDT 24
Finished Jul 05 04:33:57 PM PDT 24
Peak memory 164804 kb
Host smart-ebcb7ca2-0c3d-4d34-abb0-885cef62cd80
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2933567741 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.2933567741
Directory /workspace/13.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.3600268550
Short name T129
Test name
Test status
Simulation time 1574110000 ps
CPU time 4.64 seconds
Started Jul 05 04:34:05 PM PDT 24
Finished Jul 05 04:34:19 PM PDT 24
Peak memory 166416 kb
Host smart-40f9adc8-885e-4fd4-8765-96fe19a93e8d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3600268550 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.3600268550
Directory /workspace/14.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.3986712466
Short name T142
Test name
Test status
Simulation time 1290590000 ps
CPU time 3.85 seconds
Started Jul 05 04:33:44 PM PDT 24
Finished Jul 05 04:33:55 PM PDT 24
Peak memory 164832 kb
Host smart-cb146ae7-e8af-4b7e-9175-cdd8d14a795c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3986712466 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.3986712466
Directory /workspace/15.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.3439949088
Short name T152
Test name
Test status
Simulation time 1455490000 ps
CPU time 3.46 seconds
Started Jul 05 04:33:45 PM PDT 24
Finished Jul 05 04:33:55 PM PDT 24
Peak memory 164468 kb
Host smart-b9a91100-614c-4758-a5bb-b610fb2b6105
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3439949088 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.3439949088
Directory /workspace/16.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.1071256394
Short name T136
Test name
Test status
Simulation time 1329250000 ps
CPU time 3.64 seconds
Started Jul 05 04:33:45 PM PDT 24
Finished Jul 05 04:33:56 PM PDT 24
Peak memory 164884 kb
Host smart-8146a8ad-f4ad-4cee-9ee1-146ccbc6b8cd
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1071256394 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.1071256394
Directory /workspace/17.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.1788100409
Short name T113
Test name
Test status
Simulation time 1441750000 ps
CPU time 5.63 seconds
Started Jul 05 04:33:43 PM PDT 24
Finished Jul 05 04:33:58 PM PDT 24
Peak memory 164836 kb
Host smart-471c62c3-6162-4478-aba6-6fbbb3155dc3
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1788100409 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.1788100409
Directory /workspace/18.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.1714689914
Short name T151
Test name
Test status
Simulation time 1495910000 ps
CPU time 4.15 seconds
Started Jul 05 04:33:45 PM PDT 24
Finished Jul 05 04:33:57 PM PDT 24
Peak memory 166476 kb
Host smart-27245ae6-837b-49ac-ac51-63467a65b5f3
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1714689914 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.1714689914
Directory /workspace/19.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.174359535
Short name T154
Test name
Test status
Simulation time 1099890000 ps
CPU time 2.59 seconds
Started Jul 05 04:33:48 PM PDT 24
Finished Jul 05 04:33:55 PM PDT 24
Peak memory 164932 kb
Host smart-61ba0f47-19c2-4907-9567-dc61025f983f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=174359535 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.174359535
Directory /workspace/2.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.2465651385
Short name T153
Test name
Test status
Simulation time 1448950000 ps
CPU time 4.24 seconds
Started Jul 05 04:33:44 PM PDT 24
Finished Jul 05 04:33:56 PM PDT 24
Peak memory 164776 kb
Host smart-7e99fcfd-eeb8-4a73-a066-2e22c227c888
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2465651385 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.2465651385
Directory /workspace/20.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3848429275
Short name T114
Test name
Test status
Simulation time 1408770000 ps
CPU time 2.91 seconds
Started Jul 05 04:33:46 PM PDT 24
Finished Jul 05 04:33:59 PM PDT 24
Peak memory 166408 kb
Host smart-83056b76-d6bb-41d0-9b22-005c6b542f74
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3848429275 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.3848429275
Directory /workspace/21.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.3324109920
Short name T144
Test name
Test status
Simulation time 1366430000 ps
CPU time 3.59 seconds
Started Jul 05 04:33:43 PM PDT 24
Finished Jul 05 04:33:52 PM PDT 24
Peak memory 166388 kb
Host smart-6111edbf-2e7d-4309-9756-2ab1e5616ea9
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3324109920 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.3324109920
Directory /workspace/22.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.1549054937
Short name T125
Test name
Test status
Simulation time 1414530000 ps
CPU time 5.44 seconds
Started Jul 05 04:33:43 PM PDT 24
Finished Jul 05 04:33:57 PM PDT 24
Peak memory 165492 kb
Host smart-ad686561-6799-408e-ba5c-7bed0d8a95af
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1549054937 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.1549054937
Directory /workspace/23.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.212760548
Short name T146
Test name
Test status
Simulation time 1306190000 ps
CPU time 3.48 seconds
Started Jul 05 04:33:47 PM PDT 24
Finished Jul 05 04:33:57 PM PDT 24
Peak memory 164768 kb
Host smart-16dca626-09cd-4ab0-9c5b-a40c085fd9ad
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=212760548 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.212760548
Directory /workspace/24.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.3683366301
Short name T119
Test name
Test status
Simulation time 1312890000 ps
CPU time 6 seconds
Started Jul 05 04:33:43 PM PDT 24
Finished Jul 05 04:33:58 PM PDT 24
Peak memory 164816 kb
Host smart-40176f8e-3b9f-4e31-a9ee-0a912985d7f5
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3683366301 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.3683366301
Directory /workspace/25.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.3033224356
Short name T120
Test name
Test status
Simulation time 1080570000 ps
CPU time 2.26 seconds
Started Jul 05 04:33:52 PM PDT 24
Finished Jul 05 04:33:58 PM PDT 24
Peak memory 166476 kb
Host smart-e8831e93-99bd-404d-a83c-28e0491c24b4
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3033224356 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.3033224356
Directory /workspace/26.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.4033047738
Short name T118
Test name
Test status
Simulation time 1425790000 ps
CPU time 3.88 seconds
Started Jul 05 04:33:43 PM PDT 24
Finished Jul 05 04:33:54 PM PDT 24
Peak memory 164888 kb
Host smart-3b174ddc-cfac-4060-be73-a4b842a03e82
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4033047738 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.4033047738
Directory /workspace/27.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.3835973569
Short name T159
Test name
Test status
Simulation time 1510850000 ps
CPU time 3.88 seconds
Started Jul 05 04:34:05 PM PDT 24
Finished Jul 05 04:34:17 PM PDT 24
Peak memory 166424 kb
Host smart-ddd7ada6-83a5-4742-a3e5-d857f8483d26
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3835973569 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.3835973569
Directory /workspace/28.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.3809453646
Short name T112
Test name
Test status
Simulation time 1263050000 ps
CPU time 3.75 seconds
Started Jul 05 04:33:44 PM PDT 24
Finished Jul 05 04:33:54 PM PDT 24
Peak memory 164276 kb
Host smart-15a03cc5-93e0-4432-b9c5-b57b924840f1
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3809453646 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.3809453646
Directory /workspace/29.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.1207671429
Short name T111
Test name
Test status
Simulation time 1376550000 ps
CPU time 3.34 seconds
Started Jul 05 04:33:45 PM PDT 24
Finished Jul 05 04:33:55 PM PDT 24
Peak memory 164572 kb
Host smart-95f0ee94-f099-4eea-bec1-7b18eacb3f1b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1207671429 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.1207671429
Directory /workspace/3.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.2139817566
Short name T143
Test name
Test status
Simulation time 1362790000 ps
CPU time 3.45 seconds
Started Jul 05 04:33:56 PM PDT 24
Finished Jul 05 04:34:06 PM PDT 24
Peak memory 166456 kb
Host smart-cbb02fa4-f59a-4a83-873a-a1557b3f2afb
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2139817566 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.2139817566
Directory /workspace/30.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.572869542
Short name T139
Test name
Test status
Simulation time 1645510000 ps
CPU time 3.61 seconds
Started Jul 05 04:33:49 PM PDT 24
Finished Jul 05 04:33:58 PM PDT 24
Peak memory 164940 kb
Host smart-38c221f9-9397-4532-96fe-59a541921b9b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=572869542 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.572869542
Directory /workspace/31.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.3641784312
Short name T160
Test name
Test status
Simulation time 1551770000 ps
CPU time 3.68 seconds
Started Jul 05 04:33:46 PM PDT 24
Finished Jul 05 04:33:57 PM PDT 24
Peak memory 164888 kb
Host smart-2aff5a3a-4f44-4a59-9688-f5a3a86457f4
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3641784312 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.3641784312
Directory /workspace/32.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.2848021101
Short name T126
Test name
Test status
Simulation time 1597570000 ps
CPU time 3.22 seconds
Started Jul 05 04:34:02 PM PDT 24
Finished Jul 05 04:34:12 PM PDT 24
Peak memory 166452 kb
Host smart-b71f07db-9c04-420d-b59a-2a601e6eda01
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2848021101 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.2848021101
Directory /workspace/33.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.459284060
Short name T145
Test name
Test status
Simulation time 1243150000 ps
CPU time 3.35 seconds
Started Jul 05 04:33:47 PM PDT 24
Finished Jul 05 04:33:57 PM PDT 24
Peak memory 164768 kb
Host smart-d6e40f23-0e95-4eef-9744-6c140c3eb7da
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=459284060 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.459284060
Directory /workspace/34.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.3814808715
Short name T158
Test name
Test status
Simulation time 1594450000 ps
CPU time 3.36 seconds
Started Jul 05 04:33:52 PM PDT 24
Finished Jul 05 04:34:01 PM PDT 24
Peak memory 166416 kb
Host smart-8638b76d-0d9a-4540-8fbb-eb950cf7884d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3814808715 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.3814808715
Directory /workspace/35.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.1433094059
Short name T140
Test name
Test status
Simulation time 1489830000 ps
CPU time 3.38 seconds
Started Jul 05 04:33:58 PM PDT 24
Finished Jul 05 04:34:08 PM PDT 24
Peak memory 166392 kb
Host smart-d0f2f807-bb9d-46aa-a93b-a522a1e11916
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1433094059 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.1433094059
Directory /workspace/36.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.2844375532
Short name T148
Test name
Test status
Simulation time 1571370000 ps
CPU time 6.24 seconds
Started Jul 05 04:33:45 PM PDT 24
Finished Jul 05 04:34:00 PM PDT 24
Peak memory 164908 kb
Host smart-16544c69-3277-4903-bae0-9009bb532604
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2844375532 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.2844375532
Directory /workspace/37.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.3196909445
Short name T123
Test name
Test status
Simulation time 1523790000 ps
CPU time 3.21 seconds
Started Jul 05 04:33:59 PM PDT 24
Finished Jul 05 04:34:09 PM PDT 24
Peak memory 166472 kb
Host smart-97050cf3-b18c-49d5-9b20-4b3de7886559
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3196909445 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.3196909445
Directory /workspace/38.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.1134181052
Short name T138
Test name
Test status
Simulation time 1458930000 ps
CPU time 5.11 seconds
Started Jul 05 04:33:59 PM PDT 24
Finished Jul 05 04:34:13 PM PDT 24
Peak memory 166416 kb
Host smart-ee638397-e1fd-43ca-9638-4603cdcf045a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1134181052 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.1134181052
Directory /workspace/39.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.2654117203
Short name T116
Test name
Test status
Simulation time 1084550000 ps
CPU time 3.25 seconds
Started Jul 05 04:33:46 PM PDT 24
Finished Jul 05 04:33:55 PM PDT 24
Peak memory 164884 kb
Host smart-410dd3bf-856c-49de-8389-94fc296834b9
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2654117203 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.2654117203
Directory /workspace/4.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.2680862408
Short name T135
Test name
Test status
Simulation time 1218190000 ps
CPU time 3.02 seconds
Started Jul 05 04:33:51 PM PDT 24
Finished Jul 05 04:33:58 PM PDT 24
Peak memory 164884 kb
Host smart-75464eaa-17d6-47df-ba8e-dec19230bcf6
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2680862408 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.2680862408
Directory /workspace/40.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.3692849980
Short name T122
Test name
Test status
Simulation time 1333450000 ps
CPU time 4.39 seconds
Started Jul 05 04:33:54 PM PDT 24
Finished Jul 05 04:34:05 PM PDT 24
Peak memory 166472 kb
Host smart-52576041-5852-41f7-b6ce-5b26a0a3b655
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3692849980 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.3692849980
Directory /workspace/41.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.3760669784
Short name T149
Test name
Test status
Simulation time 1404510000 ps
CPU time 3.44 seconds
Started Jul 05 04:34:17 PM PDT 24
Finished Jul 05 04:34:29 PM PDT 24
Peak memory 166476 kb
Host smart-112ae972-a629-47eb-9889-953b2ccec0fd
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3760669784 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.3760669784
Directory /workspace/42.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.3620891683
Short name T115
Test name
Test status
Simulation time 1462250000 ps
CPU time 3.16 seconds
Started Jul 05 04:34:02 PM PDT 24
Finished Jul 05 04:34:12 PM PDT 24
Peak memory 164868 kb
Host smart-960685ac-efef-4618-8591-72a3e1685846
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3620891683 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.3620891683
Directory /workspace/43.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.830502138
Short name T133
Test name
Test status
Simulation time 1565330000 ps
CPU time 4.14 seconds
Started Jul 05 04:33:47 PM PDT 24
Finished Jul 05 04:33:58 PM PDT 24
Peak memory 164940 kb
Host smart-64258330-77b0-4e19-b14c-b3b444a75681
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=830502138 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.830502138
Directory /workspace/44.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.1836411691
Short name T156
Test name
Test status
Simulation time 1350930000 ps
CPU time 4.7 seconds
Started Jul 05 04:33:43 PM PDT 24
Finished Jul 05 04:33:56 PM PDT 24
Peak memory 163888 kb
Host smart-d19d950a-4411-4dc0-ba77-6ac526342b67
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1836411691 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.1836411691
Directory /workspace/45.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.355634326
Short name T141
Test name
Test status
Simulation time 1384830000 ps
CPU time 3.63 seconds
Started Jul 05 04:33:46 PM PDT 24
Finished Jul 05 04:33:57 PM PDT 24
Peak memory 164924 kb
Host smart-3ce4afb5-6725-4a32-b2f1-a7655a05e935
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=355634326 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.355634326
Directory /workspace/46.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.4044228877
Short name T124
Test name
Test status
Simulation time 1303010000 ps
CPU time 3.75 seconds
Started Jul 05 04:34:00 PM PDT 24
Finished Jul 05 04:34:11 PM PDT 24
Peak memory 166488 kb
Host smart-cf3a30eb-5fe8-465b-b2b1-5ada887892fd
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4044228877 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.4044228877
Directory /workspace/47.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.134645625
Short name T134
Test name
Test status
Simulation time 1548710000 ps
CPU time 3.72 seconds
Started Jul 05 04:34:04 PM PDT 24
Finished Jul 05 04:34:15 PM PDT 24
Peak memory 164960 kb
Host smart-d324451c-1d74-4d9a-9fb1-031763f194f0
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=134645625 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.134645625
Directory /workspace/48.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.2673129684
Short name T127
Test name
Test status
Simulation time 1542870000 ps
CPU time 5.41 seconds
Started Jul 05 04:33:43 PM PDT 24
Finished Jul 05 04:33:57 PM PDT 24
Peak memory 164880 kb
Host smart-ff8948a0-570f-4a48-bc8a-0aa77f2d6614
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2673129684 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.2673129684
Directory /workspace/49.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.2917327939
Short name T121
Test name
Test status
Simulation time 1571230000 ps
CPU time 4.85 seconds
Started Jul 05 04:33:43 PM PDT 24
Finished Jul 05 04:33:55 PM PDT 24
Peak memory 164860 kb
Host smart-2a950519-608c-4c06-917d-85eeb32c096b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2917327939 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.2917327939
Directory /workspace/5.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.1803030618
Short name T137
Test name
Test status
Simulation time 1426510000 ps
CPU time 4.83 seconds
Started Jul 05 04:33:40 PM PDT 24
Finished Jul 05 04:33:51 PM PDT 24
Peak memory 164940 kb
Host smart-e97c45dc-a6ac-4823-bf84-4e37432c6520
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1803030618 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.1803030618
Directory /workspace/6.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.1343109505
Short name T147
Test name
Test status
Simulation time 1165090000 ps
CPU time 3.51 seconds
Started Jul 05 04:33:47 PM PDT 24
Finished Jul 05 04:33:57 PM PDT 24
Peak memory 164936 kb
Host smart-88e01e78-96d1-4095-8744-9da1b12897b5
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1343109505 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.1343109505
Directory /workspace/7.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1406477111
Short name T150
Test name
Test status
Simulation time 1563390000 ps
CPU time 4.63 seconds
Started Jul 05 04:33:44 PM PDT 24
Finished Jul 05 04:33:56 PM PDT 24
Peak memory 164396 kb
Host smart-d3df8670-49b8-4fb4-9fd5-38074cfbccbc
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1406477111 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.1406477111
Directory /workspace/8.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.3467056390
Short name T131
Test name
Test status
Simulation time 1417970000 ps
CPU time 3.45 seconds
Started Jul 05 04:33:44 PM PDT 24
Finished Jul 05 04:33:54 PM PDT 24
Peak memory 164900 kb
Host smart-abf2ac8e-efef-4507-a378-aa45cc8c14f9
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3467056390 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.3467056390
Directory /workspace/9.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.1821933980
Short name T52
Test name
Test status
Simulation time 1364090000 ps
CPU time 3.43 seconds
Started Jul 05 04:33:22 PM PDT 24
Finished Jul 05 04:33:35 PM PDT 24
Peak memory 164940 kb
Host smart-b401f765-08fb-4162-aba6-7164043065cb
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1821933980 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.1821933980
Directory /workspace/1.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.4036852522
Short name T12
Test name
Test status
Simulation time 1597990000 ps
CPU time 5.37 seconds
Started Jul 05 04:33:35 PM PDT 24
Finished Jul 05 04:33:48 PM PDT 24
Peak memory 166472 kb
Host smart-4ac370ab-95aa-44c0-9239-4a34254f0051
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4036852522 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.4036852522
Directory /workspace/10.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.2769235412
Short name T2
Test name
Test status
Simulation time 1498090000 ps
CPU time 5.45 seconds
Started Jul 05 04:33:39 PM PDT 24
Finished Jul 05 04:33:52 PM PDT 24
Peak memory 166416 kb
Host smart-a85b05ec-b3d3-4972-bef4-470d7ab0c2f3
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2769235412 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.2769235412
Directory /workspace/11.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.4128047900
Short name T46
Test name
Test status
Simulation time 1484490000 ps
CPU time 4.53 seconds
Started Jul 05 04:33:19 PM PDT 24
Finished Jul 05 04:33:35 PM PDT 24
Peak memory 164940 kb
Host smart-1859c727-2857-4f2f-9e79-aab0ed9147fe
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4128047900 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.4128047900
Directory /workspace/12.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.2663724587
Short name T64
Test name
Test status
Simulation time 1116490000 ps
CPU time 2.35 seconds
Started Jul 05 04:33:39 PM PDT 24
Finished Jul 05 04:33:45 PM PDT 24
Peak memory 166408 kb
Host smart-5a4a9760-c329-4b03-b207-40c74c7e23b5
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2663724587 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.2663724587
Directory /workspace/13.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.1418262492
Short name T34
Test name
Test status
Simulation time 1202710000 ps
CPU time 3.01 seconds
Started Jul 05 04:33:20 PM PDT 24
Finished Jul 05 04:33:33 PM PDT 24
Peak memory 164876 kb
Host smart-b5faf69d-0abb-443a-9f04-e8aef7464f21
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1418262492 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.1418262492
Directory /workspace/14.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.2497397826
Short name T65
Test name
Test status
Simulation time 1080750000 ps
CPU time 4.25 seconds
Started Jul 05 04:33:42 PM PDT 24
Finished Jul 05 04:33:52 PM PDT 24
Peak memory 166500 kb
Host smart-9eca6f1e-6574-442d-ad73-59027bcc5f1d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2497397826 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.2497397826
Directory /workspace/15.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.3983348076
Short name T7
Test name
Test status
Simulation time 1520090000 ps
CPU time 4.14 seconds
Started Jul 05 04:33:27 PM PDT 24
Finished Jul 05 04:33:40 PM PDT 24
Peak memory 164860 kb
Host smart-a9cdef26-d712-4d95-af31-3773fcdb2a25
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3983348076 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.3983348076
Directory /workspace/16.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.2078000615
Short name T60
Test name
Test status
Simulation time 1073150000 ps
CPU time 3.19 seconds
Started Jul 05 04:33:40 PM PDT 24
Finished Jul 05 04:33:47 PM PDT 24
Peak memory 166388 kb
Host smart-091c12f2-e7fc-47b1-9f9e-a41be9ea81c7
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2078000615 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.2078000615
Directory /workspace/17.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.344694344
Short name T70
Test name
Test status
Simulation time 1237930000 ps
CPU time 3.17 seconds
Started Jul 05 04:33:37 PM PDT 24
Finished Jul 05 04:33:45 PM PDT 24
Peak memory 164900 kb
Host smart-e928a9f7-fe32-48ef-8741-8a6ee161e702
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=344694344 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.344694344
Directory /workspace/18.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.2375741148
Short name T33
Test name
Test status
Simulation time 1496750000 ps
CPU time 3.19 seconds
Started Jul 05 04:33:43 PM PDT 24
Finished Jul 05 04:33:51 PM PDT 24
Peak memory 166476 kb
Host smart-b6bf34df-8f43-449d-b93e-967410e9ca17
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2375741148 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.2375741148
Directory /workspace/19.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.374513776
Short name T43
Test name
Test status
Simulation time 1361910000 ps
CPU time 2.97 seconds
Started Jul 05 04:33:38 PM PDT 24
Finished Jul 05 04:33:45 PM PDT 24
Peak memory 164936 kb
Host smart-04ed8bfa-a714-4712-a3c7-a8723f7459d2
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=374513776 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.374513776
Directory /workspace/2.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.2229469365
Short name T62
Test name
Test status
Simulation time 1584850000 ps
CPU time 4.66 seconds
Started Jul 05 04:33:39 PM PDT 24
Finished Jul 05 04:33:50 PM PDT 24
Peak memory 164808 kb
Host smart-33da637e-116f-465c-99d0-2881b83fc52a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2229469365 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.2229469365
Directory /workspace/20.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.1541313283
Short name T42
Test name
Test status
Simulation time 1631990000 ps
CPU time 4.46 seconds
Started Jul 05 04:33:28 PM PDT 24
Finished Jul 05 04:33:42 PM PDT 24
Peak memory 164836 kb
Host smart-2be28fae-71ce-4363-954e-9e561692f38a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1541313283 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.1541313283
Directory /workspace/21.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.2577382376
Short name T45
Test name
Test status
Simulation time 1566950000 ps
CPU time 6.12 seconds
Started Jul 05 04:33:26 PM PDT 24
Finished Jul 05 04:33:44 PM PDT 24
Peak memory 164816 kb
Host smart-908c957f-ad7f-4993-b6f7-fbb2840fb1b8
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2577382376 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.2577382376
Directory /workspace/22.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.3818628188
Short name T32
Test name
Test status
Simulation time 1355930000 ps
CPU time 4.13 seconds
Started Jul 05 04:33:33 PM PDT 24
Finished Jul 05 04:33:43 PM PDT 24
Peak memory 166488 kb
Host smart-ac16b5b2-761d-42f8-8b2d-4042bf7100a9
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3818628188 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.3818628188
Directory /workspace/23.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.2152806902
Short name T63
Test name
Test status
Simulation time 1429610000 ps
CPU time 3.51 seconds
Started Jul 05 04:33:28 PM PDT 24
Finished Jul 05 04:33:39 PM PDT 24
Peak memory 164776 kb
Host smart-a4ec1a9e-ea3e-4dfe-9d2b-077e7955dde6
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2152806902 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.2152806902
Directory /workspace/24.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.1869381026
Short name T35
Test name
Test status
Simulation time 1499350000 ps
CPU time 3.52 seconds
Started Jul 05 04:33:40 PM PDT 24
Finished Jul 05 04:33:48 PM PDT 24
Peak memory 166336 kb
Host smart-11eaaaf6-5edf-4aee-a0b9-3106407f3e7b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1869381026 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.1869381026
Directory /workspace/25.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.709129732
Short name T3
Test name
Test status
Simulation time 1416030000 ps
CPU time 4.17 seconds
Started Jul 05 04:33:38 PM PDT 24
Finished Jul 05 04:33:48 PM PDT 24
Peak memory 164868 kb
Host smart-cf5f55fe-74df-49a5-b297-0796372f13bf
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=709129732 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.709129732
Directory /workspace/26.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.824247437
Short name T61
Test name
Test status
Simulation time 1482950000 ps
CPU time 4.43 seconds
Started Jul 05 04:33:41 PM PDT 24
Finished Jul 05 04:33:52 PM PDT 24
Peak memory 164848 kb
Host smart-7ad110f0-9477-40e4-9dac-139fd2993243
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=824247437 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.824247437
Directory /workspace/27.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.4248082930
Short name T40
Test name
Test status
Simulation time 1128330000 ps
CPU time 2.91 seconds
Started Jul 05 04:33:26 PM PDT 24
Finished Jul 05 04:33:37 PM PDT 24
Peak memory 164880 kb
Host smart-3e1d3716-aad0-44cc-a0d8-714ecbd26386
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4248082930 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.4248082930
Directory /workspace/28.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.4261544648
Short name T47
Test name
Test status
Simulation time 1420530000 ps
CPU time 3.5 seconds
Started Jul 05 04:33:40 PM PDT 24
Finished Jul 05 04:33:49 PM PDT 24
Peak memory 166476 kb
Host smart-eb29fc06-c0ed-414c-ac03-70f0122b0813
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4261544648 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.4261544648
Directory /workspace/29.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.281260664
Short name T58
Test name
Test status
Simulation time 1490090000 ps
CPU time 4.39 seconds
Started Jul 05 04:33:33 PM PDT 24
Finished Jul 05 04:33:44 PM PDT 24
Peak memory 164932 kb
Host smart-e13da511-e110-46f2-95c9-0b44d8d0cbd6
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=281260664 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.281260664
Directory /workspace/3.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.681922191
Short name T10
Test name
Test status
Simulation time 1600010000 ps
CPU time 5.08 seconds
Started Jul 05 04:33:41 PM PDT 24
Finished Jul 05 04:33:53 PM PDT 24
Peak memory 164880 kb
Host smart-12e2f56f-441e-4f19-9cd9-54236856a7c5
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=681922191 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.681922191
Directory /workspace/30.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.2269773938
Short name T41
Test name
Test status
Simulation time 1102010000 ps
CPU time 4.42 seconds
Started Jul 05 04:33:42 PM PDT 24
Finished Jul 05 04:33:52 PM PDT 24
Peak memory 164924 kb
Host smart-11b49b11-7e25-49eb-992b-5b4a411226cf
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2269773938 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.2269773938
Directory /workspace/31.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.1913601194
Short name T11
Test name
Test status
Simulation time 1318130000 ps
CPU time 4.43 seconds
Started Jul 05 04:33:32 PM PDT 24
Finished Jul 05 04:33:44 PM PDT 24
Peak memory 164864 kb
Host smart-15f7155a-e241-43c8-adfe-5ddb1e23d635
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1913601194 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.1913601194
Directory /workspace/32.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.2994252867
Short name T57
Test name
Test status
Simulation time 1210970000 ps
CPU time 4.02 seconds
Started Jul 05 04:33:45 PM PDT 24
Finished Jul 05 04:33:57 PM PDT 24
Peak memory 166416 kb
Host smart-b92284c1-e2fe-48c5-a04c-078e56cac3bb
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2994252867 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.2994252867
Directory /workspace/33.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.1853630764
Short name T67
Test name
Test status
Simulation time 1529770000 ps
CPU time 3.91 seconds
Started Jul 05 04:33:31 PM PDT 24
Finished Jul 05 04:33:42 PM PDT 24
Peak memory 164828 kb
Host smart-bc4d14fe-c184-45d1-9c51-2f35b2385979
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1853630764 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.1853630764
Directory /workspace/34.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.4237746298
Short name T48
Test name
Test status
Simulation time 1120830000 ps
CPU time 2.91 seconds
Started Jul 05 04:33:44 PM PDT 24
Finished Jul 05 04:33:52 PM PDT 24
Peak memory 166492 kb
Host smart-ddbadb1b-6d39-4787-81f8-7b6da0385b26
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4237746298 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.4237746298
Directory /workspace/35.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.3159650273
Short name T31
Test name
Test status
Simulation time 1458090000 ps
CPU time 4.92 seconds
Started Jul 05 04:33:41 PM PDT 24
Finished Jul 05 04:33:53 PM PDT 24
Peak memory 166408 kb
Host smart-2a7d96c5-fb84-4d29-ac5b-47731a24302f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3159650273 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.3159650273
Directory /workspace/36.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.4055211038
Short name T51
Test name
Test status
Simulation time 1395970000 ps
CPU time 3.18 seconds
Started Jul 05 04:33:35 PM PDT 24
Finished Jul 05 04:33:43 PM PDT 24
Peak memory 166468 kb
Host smart-ac01a6ec-5212-44a3-9fe4-67ad72407625
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4055211038 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.4055211038
Directory /workspace/37.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.355986422
Short name T39
Test name
Test status
Simulation time 1477650000 ps
CPU time 3.99 seconds
Started Jul 05 04:33:41 PM PDT 24
Finished Jul 05 04:33:50 PM PDT 24
Peak memory 164848 kb
Host smart-16758010-d227-4b5c-8dcf-a76e5bd6fc6b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=355986422 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.355986422
Directory /workspace/38.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.4054039996
Short name T13
Test name
Test status
Simulation time 1485250000 ps
CPU time 3.39 seconds
Started Jul 05 04:33:42 PM PDT 24
Finished Jul 05 04:33:51 PM PDT 24
Peak memory 166480 kb
Host smart-0ace004f-495f-4c19-82c2-eda7af7df8c6
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4054039996 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.4054039996
Directory /workspace/39.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.474376475
Short name T50
Test name
Test status
Simulation time 1534590000 ps
CPU time 5.8 seconds
Started Jul 05 04:33:24 PM PDT 24
Finished Jul 05 04:33:42 PM PDT 24
Peak memory 164876 kb
Host smart-942b8a76-ac7b-4149-94a1-99cb8258bd93
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=474376475 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.474376475
Directory /workspace/4.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.729866311
Short name T53
Test name
Test status
Simulation time 1565070000 ps
CPU time 3.73 seconds
Started Jul 05 04:33:32 PM PDT 24
Finished Jul 05 04:33:42 PM PDT 24
Peak memory 164940 kb
Host smart-360ec195-33bd-4ee5-bdaf-c0f5d8ecd98d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=729866311 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.729866311
Directory /workspace/40.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.1651363303
Short name T36
Test name
Test status
Simulation time 1334910000 ps
CPU time 4.84 seconds
Started Jul 05 04:33:41 PM PDT 24
Finished Jul 05 04:33:52 PM PDT 24
Peak memory 164868 kb
Host smart-cf8438f2-a2f5-4a82-9467-46ed67f0ba9a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1651363303 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.1651363303
Directory /workspace/41.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.2775253010
Short name T69
Test name
Test status
Simulation time 1414910000 ps
CPU time 4.34 seconds
Started Jul 05 04:33:31 PM PDT 24
Finished Jul 05 04:33:43 PM PDT 24
Peak memory 164804 kb
Host smart-de58c43e-95c0-45ef-8d5d-a844d6e9a142
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2775253010 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.2775253010
Directory /workspace/42.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.696796807
Short name T8
Test name
Test status
Simulation time 1436750000 ps
CPU time 3.78 seconds
Started Jul 05 04:33:45 PM PDT 24
Finished Jul 05 04:33:56 PM PDT 24
Peak memory 164940 kb
Host smart-a5ce7708-b5ff-428e-a6d5-fb18b20a487d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=696796807 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.696796807
Directory /workspace/43.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.1286709639
Short name T55
Test name
Test status
Simulation time 1218430000 ps
CPU time 2.85 seconds
Started Jul 05 04:34:10 PM PDT 24
Finished Jul 05 04:34:21 PM PDT 24
Peak memory 166472 kb
Host smart-7609b9b2-522f-4d42-a85c-48303141f806
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1286709639 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.1286709639
Directory /workspace/44.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.3647301498
Short name T38
Test name
Test status
Simulation time 1185470000 ps
CPU time 3.59 seconds
Started Jul 05 04:33:41 PM PDT 24
Finished Jul 05 04:33:50 PM PDT 24
Peak memory 164936 kb
Host smart-ec759631-b86e-4df9-837c-19ac29f139b0
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3647301498 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.3647301498
Directory /workspace/45.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.4050600024
Short name T44
Test name
Test status
Simulation time 1413890000 ps
CPU time 3.32 seconds
Started Jul 05 04:33:31 PM PDT 24
Finished Jul 05 04:33:41 PM PDT 24
Peak memory 164852 kb
Host smart-b8f05aa9-775c-40d1-a65a-62c471675d83
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4050600024 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.4050600024
Directory /workspace/46.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.1072913443
Short name T68
Test name
Test status
Simulation time 1577130000 ps
CPU time 3.41 seconds
Started Jul 05 04:33:44 PM PDT 24
Finished Jul 05 04:33:54 PM PDT 24
Peak memory 166472 kb
Host smart-09e5f7b6-6f7f-42fb-b232-3d7d87dff062
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1072913443 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.1072913443
Directory /workspace/47.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.2736937436
Short name T49
Test name
Test status
Simulation time 1304310000 ps
CPU time 2.91 seconds
Started Jul 05 04:33:42 PM PDT 24
Finished Jul 05 04:33:49 PM PDT 24
Peak memory 166464 kb
Host smart-97aa320e-1f3d-4115-84ce-804ac1a445de
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2736937436 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.2736937436
Directory /workspace/48.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.1935493286
Short name T37
Test name
Test status
Simulation time 1452370000 ps
CPU time 3.89 seconds
Started Jul 05 04:33:40 PM PDT 24
Finished Jul 05 04:33:49 PM PDT 24
Peak memory 164828 kb
Host smart-2d29b5d9-814d-426b-bcc7-538d59e7cd31
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1935493286 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.1935493286
Directory /workspace/49.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.3496877755
Short name T1
Test name
Test status
Simulation time 1376530000 ps
CPU time 3.68 seconds
Started Jul 05 04:33:22 PM PDT 24
Finished Jul 05 04:33:36 PM PDT 24
Peak memory 164824 kb
Host smart-5bdc109b-1e00-4d7c-81d7-c47246e9aa1e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3496877755 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.3496877755
Directory /workspace/5.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.1932509152
Short name T56
Test name
Test status
Simulation time 1514790000 ps
CPU time 3.25 seconds
Started Jul 05 04:33:20 PM PDT 24
Finished Jul 05 04:33:33 PM PDT 24
Peak memory 164908 kb
Host smart-35cf1cd9-407f-4113-9523-a8db615f23db
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1932509152 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.1932509152
Directory /workspace/6.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.1402964754
Short name T59
Test name
Test status
Simulation time 1362410000 ps
CPU time 3.55 seconds
Started Jul 05 04:33:42 PM PDT 24
Finished Jul 05 04:33:51 PM PDT 24
Peak memory 164856 kb
Host smart-6903f7a7-022b-4173-8e75-f87c1b336970
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1402964754 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.1402964754
Directory /workspace/7.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.3821914941
Short name T54
Test name
Test status
Simulation time 1456450000 ps
CPU time 3.21 seconds
Started Jul 05 04:33:39 PM PDT 24
Finished Jul 05 04:33:47 PM PDT 24
Peak memory 164852 kb
Host smart-50a2dbf4-ee0f-4723-ad14-e27f6d409e9a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3821914941 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.3821914941
Directory /workspace/8.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.1140648526
Short name T66
Test name
Test status
Simulation time 1389230000 ps
CPU time 4.45 seconds
Started Jul 05 04:33:26 PM PDT 24
Finished Jul 05 04:33:41 PM PDT 24
Peak memory 164944 kb
Host smart-a11868e4-ec8e-4ed5-bd00-e1043276bc1d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1140648526 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.1140648526
Directory /workspace/9.prim_lfsr_gal_smoke/latest
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