Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.31 100.00 96.55 100.00 100.00 95.00


Total tests in report: 200
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
87.31 87.31 100.00 100.00 96.55 96.55 100.00 100.00 100.00 100.00 40.00 40.00 /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.3908993621
96.81 9.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 87.50 47.50 /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.3017195717
98.31 1.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 95.00 7.50 /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.3228933786

Tests that do not contribute to grading

Name
/workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.4155461312
/workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.4105009726
/workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.3755918742
/workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.3562104317
/workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.3936664362
/workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.2137484250
/workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.2135079623
/workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.539739430
/workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.1594964358
/workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.2109541391
/workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.2839391868
/workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.4023154523
/workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.1672216985
/workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.2567521772
/workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.4191102601
/workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.2833932419
/workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.3146936123
/workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.412533318
/workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1387226198
/workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.4001029884
/workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.3627215115
/workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.3717954938
/workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.3550045560
/workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.4145220173
/workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.2151656848
/workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.2925037262
/workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.2401632643
/workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.2315408371
/workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.1583595724
/workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.2995040264
/workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.2043708076
/workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.4201557442
/workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.3335969103
/workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.2418777370
/workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.366173873
/workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.2962804464
/workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.1153562022
/workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.2486904310
/workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.3178082393
/workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.3578315279
/workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.2564637950
/workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.586322827
/workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.3322687310
/workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.2543218025
/workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.3423167122
/workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.2933674288
/workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.3673070691
/workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.2933128866
/workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.510043832
/workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.216888954
/workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.3394832587
/workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.3668685054
/workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.1718080743
/workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.3935137802
/workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.2808765682
/workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.4128275662
/workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.2261788357
/workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.2611782240
/workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.1065789453
/workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.3403303310
/workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.2218878515
/workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.800040825
/workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3574420389
/workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.151304666
/workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.1550179106
/workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.1137080189
/workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.635441254
/workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.2365207009
/workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.691517713
/workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.2714951871
/workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.1399553308
/workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.577746543
/workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.1274253289
/workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.410791391
/workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.2828812289
/workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.3052430016
/workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.800321838
/workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.761921725
/workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.1109323498
/workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.1219533837
/workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.1605584625
/workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.3925580865
/workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.895160858
/workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.931462573
/workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.1050236734
/workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.4080449452
/workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.2567651338
/workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.3704723046
/workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.183642825
/workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.555364627
/workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.917516416
/workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1330568672
/workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.3487934811
/workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.3881471790
/workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.3420536516
/workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.3403737209
/workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.1368460796
/workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.4103995507
/workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.2813961264
/workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.1994116096
/workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.1366013845
/workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.843297197
/workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.3703355141
/workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.2683292626
/workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.1268215294
/workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.807554018
/workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.651099469
/workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.3166095291
/workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.590847925
/workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.674199380
/workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.1495840440
/workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.3087829583
/workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3688750717
/workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.1464159255
/workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.2009260944
/workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.3939131381
/workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.111070868
/workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.3558049614
/workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.2465746243
/workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.2810789445
/workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.1258582002
/workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.3223525206
/workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.2815247225
/workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.1246035463
/workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.1065511422
/workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.3836607953
/workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.1947496373
/workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.3394566487
/workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.216348949
/workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1801105303
/workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.1176920720
/workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.2375612198
/workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.544955843
/workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.1336050090
/workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.1928306441
/workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.1812360032
/workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1497338955
/workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.1462676386
/workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.3149747780
/workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.324610072
/workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.1541352429
/workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.48762485
/workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.1742882621
/workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.661956205
/workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.437228171
/workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.2156449662
/workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.2288649900
/workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.3180179226
/workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.2551293166
/workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.2581806486
/workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.1750660341
/workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.2243826404
/workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.1386440084
/workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.92203028
/workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.711666628
/workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.1252904032
/workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.1206294414
/workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.3172973385
/workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.412034741
/workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.2960094991
/workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.3114530524
/workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.2685244830
/workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.2364147806
/workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.2246104845
/workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.3501008237
/workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.1118987175
/workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.1177872618
/workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.2008941015
/workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.2485671780
/workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.1229694250
/workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.2101131494
/workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.107550349
/workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.2573720928
/workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.2167846609
/workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.4035462859
/workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.3867814800
/workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.562517048
/workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.4251151572
/workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.3697315462
/workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.3371753677
/workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.4138343592
/workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.3947423459
/workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.1755121719
/workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.3795786359
/workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.1355911446
/workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.3640480346
/workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.506446858
/workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.2610661008
/workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.521948553
/workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.2868496849
/workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.1610842689
/workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.812097469
/workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.1040209970
/workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.4209008016
/workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.2908503771
/workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.3255674961
/workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.2383383346



Total test records in report: 200
tests.html | tests1.html | tests2.html | tests3.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.3255674961 Jul 06 04:23:58 PM PDT 24 Jul 06 04:24:09 PM PDT 24 1568770000 ps
T2 /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.2868496849 Jul 06 04:21:07 PM PDT 24 Jul 06 04:21:16 PM PDT 24 1302370000 ps
T3 /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.1755121719 Jul 06 04:23:30 PM PDT 24 Jul 06 04:23:37 PM PDT 24 944850000 ps
T4 /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.4138343592 Jul 06 04:23:16 PM PDT 24 Jul 06 04:23:24 PM PDT 24 1305370000 ps
T8 /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.1229694250 Jul 06 04:22:59 PM PDT 24 Jul 06 04:23:06 PM PDT 24 1313830000 ps
T9 /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.1040209970 Jul 06 04:23:43 PM PDT 24 Jul 06 04:23:52 PM PDT 24 1517890000 ps
T10 /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.4251151572 Jul 06 04:23:17 PM PDT 24 Jul 06 04:23:25 PM PDT 24 1584670000 ps
T11 /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.1252904032 Jul 06 04:23:20 PM PDT 24 Jul 06 04:23:29 PM PDT 24 1335570000 ps
T12 /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.812097469 Jul 06 04:23:36 PM PDT 24 Jul 06 04:23:45 PM PDT 24 1462370000 ps
T13 /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.3908993621 Jul 06 04:23:26 PM PDT 24 Jul 06 04:23:34 PM PDT 24 1512130000 ps
T31 /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.3947423459 Jul 06 04:23:11 PM PDT 24 Jul 06 04:23:18 PM PDT 24 1431150000 ps
T32 /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.2573720928 Jul 06 04:21:55 PM PDT 24 Jul 06 04:22:04 PM PDT 24 1306610000 ps
T33 /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.1610842689 Jul 06 04:21:47 PM PDT 24 Jul 06 04:21:57 PM PDT 24 1578230000 ps
T34 /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.3795786359 Jul 06 04:19:23 PM PDT 24 Jul 06 04:19:33 PM PDT 24 1495050000 ps
T35 /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.2908503771 Jul 06 04:23:37 PM PDT 24 Jul 06 04:23:45 PM PDT 24 1419150000 ps
T36 /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.3172973385 Jul 06 04:21:55 PM PDT 24 Jul 06 04:22:03 PM PDT 24 1362410000 ps
T37 /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.2243826404 Jul 06 04:21:44 PM PDT 24 Jul 06 04:21:54 PM PDT 24 1443590000 ps
T38 /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.4035462859 Jul 06 04:19:28 PM PDT 24 Jul 06 04:19:38 PM PDT 24 1295390000 ps
T39 /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.3697315462 Jul 06 04:23:43 PM PDT 24 Jul 06 04:23:55 PM PDT 24 1567310000 ps
T40 /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.3114530524 Jul 06 04:23:28 PM PDT 24 Jul 06 04:23:37 PM PDT 24 1520610000 ps
T41 /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.1118987175 Jul 06 04:23:36 PM PDT 24 Jul 06 04:23:45 PM PDT 24 1376190000 ps
T42 /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.4209008016 Jul 06 04:23:25 PM PDT 24 Jul 06 04:23:32 PM PDT 24 1307770000 ps
T43 /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.3867814800 Jul 06 04:23:26 PM PDT 24 Jul 06 04:23:34 PM PDT 24 1633070000 ps
T44 /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.711666628 Jul 06 04:23:29 PM PDT 24 Jul 06 04:23:38 PM PDT 24 1462690000 ps
T45 /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.2485671780 Jul 06 04:21:26 PM PDT 24 Jul 06 04:21:33 PM PDT 24 1493110000 ps
T46 /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.412034741 Jul 06 04:23:27 PM PDT 24 Jul 06 04:23:34 PM PDT 24 1241690000 ps
T47 /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.506446858 Jul 06 04:22:00 PM PDT 24 Jul 06 04:22:08 PM PDT 24 1338170000 ps
T48 /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.2383383346 Jul 06 04:23:20 PM PDT 24 Jul 06 04:23:28 PM PDT 24 1506710000 ps
T49 /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.521948553 Jul 06 04:23:43 PM PDT 24 Jul 06 04:23:53 PM PDT 24 1405330000 ps
T50 /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.1355911446 Jul 06 04:23:43 PM PDT 24 Jul 06 04:23:55 PM PDT 24 1509730000 ps
T51 /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.1206294414 Jul 06 04:23:32 PM PDT 24 Jul 06 04:23:42 PM PDT 24 1489350000 ps
T52 /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.2246104845 Jul 06 04:19:32 PM PDT 24 Jul 06 04:19:41 PM PDT 24 1418810000 ps
T53 /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.2581806486 Jul 06 04:23:29 PM PDT 24 Jul 06 04:23:38 PM PDT 24 1488690000 ps
T54 /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.562517048 Jul 06 04:23:43 PM PDT 24 Jul 06 04:23:55 PM PDT 24 1390770000 ps
T55 /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.2167846609 Jul 06 04:23:26 PM PDT 24 Jul 06 04:23:34 PM PDT 24 1544270000 ps
T56 /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.92203028 Jul 06 04:23:28 PM PDT 24 Jul 06 04:23:37 PM PDT 24 1507130000 ps
T57 /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.2610661008 Jul 06 04:23:18 PM PDT 24 Jul 06 04:23:26 PM PDT 24 1483410000 ps
T58 /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.2960094991 Jul 06 04:21:38 PM PDT 24 Jul 06 04:21:47 PM PDT 24 1355890000 ps
T59 /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.1177872618 Jul 06 04:19:28 PM PDT 24 Jul 06 04:19:38 PM PDT 24 1464990000 ps
T60 /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.1750660341 Jul 06 04:23:04 PM PDT 24 Jul 06 04:23:12 PM PDT 24 1505150000 ps
T61 /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.2685244830 Jul 06 04:23:41 PM PDT 24 Jul 06 04:23:51 PM PDT 24 1373010000 ps
T62 /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.3640480346 Jul 06 04:20:10 PM PDT 24 Jul 06 04:20:20 PM PDT 24 1379770000 ps
T63 /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.1386440084 Jul 06 04:22:00 PM PDT 24 Jul 06 04:22:11 PM PDT 24 1569650000 ps
T64 /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.2101131494 Jul 06 04:20:25 PM PDT 24 Jul 06 04:20:35 PM PDT 24 1449850000 ps
T65 /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.3371753677 Jul 06 04:23:44 PM PDT 24 Jul 06 04:23:55 PM PDT 24 1576210000 ps
T66 /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.2008941015 Jul 06 04:23:30 PM PDT 24 Jul 06 04:23:40 PM PDT 24 1340490000 ps
T67 /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.2364147806 Jul 06 04:23:30 PM PDT 24 Jul 06 04:23:39 PM PDT 24 1434090000 ps
T68 /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.2551293166 Jul 06 04:19:32 PM PDT 24 Jul 06 04:19:41 PM PDT 24 1397030000 ps
T69 /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.107550349 Jul 06 04:23:43 PM PDT 24 Jul 06 04:23:54 PM PDT 24 1414310000 ps
T70 /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.3501008237 Jul 06 04:21:49 PM PDT 24 Jul 06 04:21:56 PM PDT 24 1342290000 ps
T5 /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1387226198 Jul 06 05:14:39 PM PDT 24 Jul 06 05:48:10 PM PDT 24 336482310000 ps
T6 /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.3017195717 Jul 06 05:14:35 PM PDT 24 Jul 06 05:42:10 PM PDT 24 336350870000 ps
T7 /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.2995040264 Jul 06 05:15:03 PM PDT 24 Jul 06 05:43:19 PM PDT 24 336569770000 ps
T14 /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.3578315279 Jul 06 05:14:43 PM PDT 24 Jul 06 05:56:15 PM PDT 24 336736270000 ps
T15 /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.4001029884 Jul 06 05:14:38 PM PDT 24 Jul 06 05:43:48 PM PDT 24 336690690000 ps
T16 /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.2925037262 Jul 06 05:14:46 PM PDT 24 Jul 06 05:48:18 PM PDT 24 336483030000 ps
T17 /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.2962804464 Jul 06 05:14:41 PM PDT 24 Jul 06 05:50:47 PM PDT 24 336513890000 ps
T18 /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.3178082393 Jul 06 05:14:40 PM PDT 24 Jul 06 05:44:51 PM PDT 24 337004510000 ps
T19 /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.2933128866 Jul 06 05:14:35 PM PDT 24 Jul 06 05:49:31 PM PDT 24 336564090000 ps
T20 /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.3146936123 Jul 06 05:14:34 PM PDT 24 Jul 06 05:48:30 PM PDT 24 336967390000 ps
T71 /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.1594964358 Jul 06 05:14:38 PM PDT 24 Jul 06 05:44:22 PM PDT 24 336652390000 ps
T72 /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.2833932419 Jul 06 05:14:41 PM PDT 24 Jul 06 05:46:39 PM PDT 24 336991830000 ps
T73 /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.3562104317 Jul 06 05:14:31 PM PDT 24 Jul 06 05:46:44 PM PDT 24 336602310000 ps
T74 /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.2137484250 Jul 06 05:14:42 PM PDT 24 Jul 06 05:44:43 PM PDT 24 336491030000 ps
T75 /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.3423167122 Jul 06 05:14:31 PM PDT 24 Jul 06 05:47:43 PM PDT 24 336746230000 ps
T76 /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.3755918742 Jul 06 05:14:36 PM PDT 24 Jul 06 05:50:50 PM PDT 24 337085050000 ps
T77 /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.2135079623 Jul 06 05:14:32 PM PDT 24 Jul 06 05:49:44 PM PDT 24 336732630000 ps
T78 /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.2109541391 Jul 06 05:14:41 PM PDT 24 Jul 06 05:47:00 PM PDT 24 336459910000 ps
T79 /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.4105009726 Jul 06 05:14:38 PM PDT 24 Jul 06 05:44:50 PM PDT 24 336778490000 ps
T80 /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.1672216985 Jul 06 05:14:39 PM PDT 24 Jul 06 05:48:31 PM PDT 24 337200830000 ps
T81 /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.1583595724 Jul 06 05:14:47 PM PDT 24 Jul 06 05:43:48 PM PDT 24 336890430000 ps
T82 /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.3936664362 Jul 06 05:14:35 PM PDT 24 Jul 06 05:45:34 PM PDT 24 336651030000 ps
T83 /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.366173873 Jul 06 05:14:42 PM PDT 24 Jul 06 05:44:09 PM PDT 24 337190570000 ps
T84 /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.3335969103 Jul 06 05:14:42 PM PDT 24 Jul 06 05:49:34 PM PDT 24 336765810000 ps
T85 /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.2043708076 Jul 06 05:14:42 PM PDT 24 Jul 06 05:44:46 PM PDT 24 336831230000 ps
T86 /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.4201557442 Jul 06 05:14:40 PM PDT 24 Jul 06 05:50:26 PM PDT 24 336767830000 ps
T87 /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.2933674288 Jul 06 05:14:36 PM PDT 24 Jul 06 05:46:49 PM PDT 24 337007230000 ps
T88 /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.412533318 Jul 06 05:14:42 PM PDT 24 Jul 06 05:46:00 PM PDT 24 336788790000 ps
T89 /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.1153562022 Jul 06 05:14:43 PM PDT 24 Jul 06 05:42:24 PM PDT 24 336657490000 ps
T90 /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.586322827 Jul 06 05:14:45 PM PDT 24 Jul 06 05:46:57 PM PDT 24 336795070000 ps
T91 /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.2401632643 Jul 06 05:14:41 PM PDT 24 Jul 06 05:45:08 PM PDT 24 336706190000 ps
T92 /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.2543218025 Jul 06 05:14:42 PM PDT 24 Jul 06 05:53:06 PM PDT 24 337095170000 ps
T93 /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.2151656848 Jul 06 05:14:35 PM PDT 24 Jul 06 05:40:37 PM PDT 24 336727530000 ps
T94 /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.3627215115 Jul 06 05:14:45 PM PDT 24 Jul 06 05:43:45 PM PDT 24 336628970000 ps
T95 /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.4155461312 Jul 06 05:14:38 PM PDT 24 Jul 06 05:47:33 PM PDT 24 336342890000 ps
T96 /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.3322687310 Jul 06 05:14:48 PM PDT 24 Jul 06 05:42:52 PM PDT 24 336690190000 ps
T97 /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.510043832 Jul 06 05:14:36 PM PDT 24 Jul 06 05:52:19 PM PDT 24 336732530000 ps
T98 /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.3673070691 Jul 06 05:14:38 PM PDT 24 Jul 06 05:45:19 PM PDT 24 336592230000 ps
T99 /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.4145220173 Jul 06 05:14:42 PM PDT 24 Jul 06 05:44:22 PM PDT 24 336888190000 ps
T100 /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.4023154523 Jul 06 05:14:46 PM PDT 24 Jul 06 05:47:40 PM PDT 24 336766810000 ps
T101 /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.2418777370 Jul 06 05:14:34 PM PDT 24 Jul 06 05:55:12 PM PDT 24 336899510000 ps
T102 /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.2315408371 Jul 06 05:14:48 PM PDT 24 Jul 06 05:46:06 PM PDT 24 336963470000 ps
T103 /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.4191102601 Jul 06 05:14:40 PM PDT 24 Jul 06 05:48:22 PM PDT 24 337032730000 ps
T104 /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.2567521772 Jul 06 05:14:39 PM PDT 24 Jul 06 05:45:20 PM PDT 24 336649250000 ps
T105 /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.2486904310 Jul 06 05:14:41 PM PDT 24 Jul 06 05:45:37 PM PDT 24 336794750000 ps
T106 /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.2564637950 Jul 06 05:14:45 PM PDT 24 Jul 06 05:45:13 PM PDT 24 336492070000 ps
T107 /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.3717954938 Jul 06 05:14:36 PM PDT 24 Jul 06 05:44:38 PM PDT 24 336939930000 ps
T108 /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.2839391868 Jul 06 05:14:41 PM PDT 24 Jul 06 05:43:18 PM PDT 24 336980650000 ps
T109 /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.3550045560 Jul 06 05:14:42 PM PDT 24 Jul 06 05:48:10 PM PDT 24 337056710000 ps
T110 /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.539739430 Jul 06 05:14:40 PM PDT 24 Jul 06 05:47:20 PM PDT 24 336838450000 ps
T111 /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.324610072 Jul 06 05:17:18 PM PDT 24 Jul 06 05:17:28 PM PDT 24 1602150000 ps
T112 /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.3703355141 Jul 06 05:17:20 PM PDT 24 Jul 06 05:17:28 PM PDT 24 1300210000 ps
T113 /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.807554018 Jul 06 05:17:15 PM PDT 24 Jul 06 05:17:24 PM PDT 24 1346330000 ps
T114 /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.1268215294 Jul 06 05:17:19 PM PDT 24 Jul 06 05:17:27 PM PDT 24 1492510000 ps
T115 /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.1065511422 Jul 06 05:17:12 PM PDT 24 Jul 06 05:17:22 PM PDT 24 1350750000 ps
T116 /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.1246035463 Jul 06 05:17:14 PM PDT 24 Jul 06 05:17:22 PM PDT 24 1500830000 ps
T117 /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.3166095291 Jul 06 05:17:03 PM PDT 24 Jul 06 05:17:14 PM PDT 24 1468950000 ps
T118 /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.2288649900 Jul 06 05:17:14 PM PDT 24 Jul 06 05:17:23 PM PDT 24 1324550000 ps
T119 /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.1495840440 Jul 06 05:17:10 PM PDT 24 Jul 06 05:17:18 PM PDT 24 1196830000 ps
T120 /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.2813961264 Jul 06 05:17:16 PM PDT 24 Jul 06 05:17:25 PM PDT 24 1514150000 ps
T121 /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.1994116096 Jul 06 05:17:07 PM PDT 24 Jul 06 05:17:19 PM PDT 24 1485170000 ps
T122 /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.1176920720 Jul 06 05:17:05 PM PDT 24 Jul 06 05:17:17 PM PDT 24 1562090000 ps
T123 /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.3836607953 Jul 06 05:17:08 PM PDT 24 Jul 06 05:17:19 PM PDT 24 1557690000 ps
T124 /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.3939131381 Jul 06 05:17:12 PM PDT 24 Jul 06 05:17:22 PM PDT 24 1613710000 ps
T125 /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.3180179226 Jul 06 05:17:04 PM PDT 24 Jul 06 05:17:13 PM PDT 24 1382550000 ps
T126 /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.216348949 Jul 06 05:17:07 PM PDT 24 Jul 06 05:17:17 PM PDT 24 1561650000 ps
T127 /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.1541352429 Jul 06 05:17:12 PM PDT 24 Jul 06 05:17:21 PM PDT 24 1243170000 ps
T128 /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1801105303 Jul 06 05:17:14 PM PDT 24 Jul 06 05:17:24 PM PDT 24 1402890000 ps
T129 /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.1928306441 Jul 06 05:17:10 PM PDT 24 Jul 06 05:17:21 PM PDT 24 1533770000 ps
T130 /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1497338955 Jul 06 05:17:21 PM PDT 24 Jul 06 05:17:31 PM PDT 24 1520130000 ps
T131 /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.3223525206 Jul 06 05:17:06 PM PDT 24 Jul 06 05:17:16 PM PDT 24 1417570000 ps
T132 /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.674199380 Jul 06 05:17:07 PM PDT 24 Jul 06 05:17:17 PM PDT 24 1216650000 ps
T133 /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.2683292626 Jul 06 05:17:14 PM PDT 24 Jul 06 05:17:24 PM PDT 24 1512410000 ps
T134 /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.3394566487 Jul 06 05:17:09 PM PDT 24 Jul 06 05:17:20 PM PDT 24 1495430000 ps
T135 /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.661956205 Jul 06 05:17:05 PM PDT 24 Jul 06 05:17:16 PM PDT 24 1467710000 ps
T136 /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.590847925 Jul 06 05:17:08 PM PDT 24 Jul 06 05:17:17 PM PDT 24 1338470000 ps
T137 /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3688750717 Jul 06 05:17:07 PM PDT 24 Jul 06 05:17:16 PM PDT 24 1557810000 ps
T138 /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.437228171 Jul 06 05:17:06 PM PDT 24 Jul 06 05:17:16 PM PDT 24 1487290000 ps
T139 /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.1812360032 Jul 06 05:17:16 PM PDT 24 Jul 06 05:17:25 PM PDT 24 1358410000 ps
T140 /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.1462676386 Jul 06 05:17:02 PM PDT 24 Jul 06 05:17:11 PM PDT 24 1527930000 ps
T141 /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.2156449662 Jul 06 05:17:04 PM PDT 24 Jul 06 05:17:16 PM PDT 24 1564270000 ps
T142 /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.3149747780 Jul 06 05:17:09 PM PDT 24 Jul 06 05:17:20 PM PDT 24 1642070000 ps
T143 /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.48762485 Jul 06 05:17:15 PM PDT 24 Jul 06 05:17:24 PM PDT 24 1387850000 ps
T144 /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.1366013845 Jul 06 05:17:06 PM PDT 24 Jul 06 05:17:16 PM PDT 24 1637630000 ps
T145 /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.2810789445 Jul 06 05:17:00 PM PDT 24 Jul 06 05:17:11 PM PDT 24 1452090000 ps
T146 /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.1947496373 Jul 06 05:17:23 PM PDT 24 Jul 06 05:17:32 PM PDT 24 1515870000 ps
T147 /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.1742882621 Jul 06 05:17:09 PM PDT 24 Jul 06 05:17:23 PM PDT 24 1512810000 ps
T148 /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.2009260944 Jul 06 05:17:06 PM PDT 24 Jul 06 05:17:19 PM PDT 24 1493930000 ps
T149 /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.3558049614 Jul 06 05:17:05 PM PDT 24 Jul 06 05:17:18 PM PDT 24 1581890000 ps
T150 /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.843297197 Jul 06 05:17:04 PM PDT 24 Jul 06 05:17:16 PM PDT 24 1554770000 ps
T151 /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.3087829583 Jul 06 05:17:00 PM PDT 24 Jul 06 05:17:09 PM PDT 24 1326510000 ps
T152 /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.1464159255 Jul 06 05:17:38 PM PDT 24 Jul 06 05:17:46 PM PDT 24 1622390000 ps
T153 /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.1258582002 Jul 06 05:17:02 PM PDT 24 Jul 06 05:17:14 PM PDT 24 1530730000 ps
T154 /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.2465746243 Jul 06 05:17:10 PM PDT 24 Jul 06 05:17:21 PM PDT 24 1484070000 ps
T155 /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.544955843 Jul 06 05:17:02 PM PDT 24 Jul 06 05:17:12 PM PDT 24 1470050000 ps
T156 /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.1336050090 Jul 06 05:17:05 PM PDT 24 Jul 06 05:17:18 PM PDT 24 1539250000 ps
T157 /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.2815247225 Jul 06 05:17:07 PM PDT 24 Jul 06 05:17:17 PM PDT 24 1370390000 ps
T158 /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.2375612198 Jul 06 05:17:00 PM PDT 24 Jul 06 05:17:11 PM PDT 24 1519370000 ps
T159 /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.111070868 Jul 06 05:17:07 PM PDT 24 Jul 06 05:17:19 PM PDT 24 1504790000 ps
T160 /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.651099469 Jul 06 05:17:06 PM PDT 24 Jul 06 05:17:16 PM PDT 24 1365970000 ps
T21 /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.2365207009 Jul 06 05:17:23 PM PDT 24 Jul 06 05:52:13 PM PDT 24 336934650000 ps
T22 /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.3881471790 Jul 06 05:17:08 PM PDT 24 Jul 06 05:52:55 PM PDT 24 336669450000 ps
T23 /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.1050236734 Jul 06 05:17:12 PM PDT 24 Jul 06 05:46:31 PM PDT 24 336724370000 ps
T24 /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.3704723046 Jul 06 05:17:17 PM PDT 24 Jul 06 05:48:23 PM PDT 24 336834330000 ps
T25 /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.1065789453 Jul 06 05:17:22 PM PDT 24 Jul 06 05:50:11 PM PDT 24 336979950000 ps
T26 /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.3228933786 Jul 06 05:17:20 PM PDT 24 Jul 06 05:50:33 PM PDT 24 336913370000 ps
T27 /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.3935137802 Jul 06 05:17:11 PM PDT 24 Jul 06 05:52:12 PM PDT 24 336919730000 ps
T28 /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.2828812289 Jul 06 05:17:19 PM PDT 24 Jul 06 05:46:04 PM PDT 24 336585490000 ps
T29 /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.577746543 Jul 06 05:17:17 PM PDT 24 Jul 06 05:51:48 PM PDT 24 336862390000 ps
T30 /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.2261788357 Jul 06 05:17:43 PM PDT 24 Jul 06 05:42:46 PM PDT 24 336961610000 ps
T161 /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.151304666 Jul 06 05:17:22 PM PDT 24 Jul 06 05:43:16 PM PDT 24 336320670000 ps
T162 /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.3403737209 Jul 06 05:17:05 PM PDT 24 Jul 06 05:47:45 PM PDT 24 336723790000 ps
T163 /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.216888954 Jul 06 05:17:11 PM PDT 24 Jul 06 05:47:56 PM PDT 24 336323370000 ps
T164 /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.1605584625 Jul 06 05:17:12 PM PDT 24 Jul 06 05:51:24 PM PDT 24 336892770000 ps
T165 /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.4103995507 Jul 06 05:17:25 PM PDT 24 Jul 06 05:50:07 PM PDT 24 337068790000 ps
T166 /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.4128275662 Jul 06 05:17:12 PM PDT 24 Jul 06 05:58:14 PM PDT 24 336986690000 ps
T167 /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.3403303310 Jul 06 05:17:20 PM PDT 24 Jul 06 05:51:24 PM PDT 24 337057450000 ps
T168 /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.1109323498 Jul 06 05:17:15 PM PDT 24 Jul 06 05:55:32 PM PDT 24 336672510000 ps
T169 /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.3487934811 Jul 06 05:17:14 PM PDT 24 Jul 06 05:53:37 PM PDT 24 336438070000 ps
T170 /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.2611782240 Jul 06 05:17:21 PM PDT 24 Jul 06 05:52:15 PM PDT 24 336561430000 ps
T171 /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.1274253289 Jul 06 05:17:06 PM PDT 24 Jul 06 05:47:29 PM PDT 24 336778570000 ps
T172 /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.410791391 Jul 06 05:17:17 PM PDT 24 Jul 06 05:47:43 PM PDT 24 336421650000 ps
T173 /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.691517713 Jul 06 05:17:13 PM PDT 24 Jul 06 05:49:12 PM PDT 24 336333770000 ps
T174 /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.2714951871 Jul 06 05:17:26 PM PDT 24 Jul 06 05:45:51 PM PDT 24 336476310000 ps
T175 /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1330568672 Jul 06 05:17:18 PM PDT 24 Jul 06 05:48:53 PM PDT 24 336607070000 ps
T176 /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.1368460796 Jul 06 05:17:16 PM PDT 24 Jul 06 05:47:20 PM PDT 24 336531490000 ps
T177 /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.761921725 Jul 06 05:17:29 PM PDT 24 Jul 06 05:49:28 PM PDT 24 336941670000 ps
T178 /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.2218878515 Jul 06 05:17:12 PM PDT 24 Jul 06 05:58:47 PM PDT 24 336706290000 ps
T179 /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.183642825 Jul 06 05:17:20 PM PDT 24 Jul 06 05:47:21 PM PDT 24 337032910000 ps
T180 /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.3420536516 Jul 06 05:17:23 PM PDT 24 Jul 06 05:45:32 PM PDT 24 336518850000 ps
T181 /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.800321838 Jul 06 05:17:25 PM PDT 24 Jul 06 05:51:49 PM PDT 24 336566930000 ps
T182 /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.800040825 Jul 06 05:17:19 PM PDT 24 Jul 06 05:48:16 PM PDT 24 336665570000 ps
T183 /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.3668685054 Jul 06 05:17:09 PM PDT 24 Jul 06 05:51:00 PM PDT 24 336512350000 ps
T184 /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.3052430016 Jul 06 05:17:16 PM PDT 24 Jul 06 05:49:45 PM PDT 24 336481470000 ps
T185 /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.2567651338 Jul 06 05:17:17 PM PDT 24 Jul 06 05:48:35 PM PDT 24 336541990000 ps
T186 /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.1399553308 Jul 06 05:17:14 PM PDT 24 Jul 06 05:54:37 PM PDT 24 336708690000 ps
T187 /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.3394832587 Jul 06 05:17:21 PM PDT 24 Jul 06 05:54:07 PM PDT 24 336583970000 ps
T188 /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.1718080743 Jul 06 05:17:09 PM PDT 24 Jul 06 05:49:16 PM PDT 24 336754330000 ps
T189 /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.1219533837 Jul 06 05:17:24 PM PDT 24 Jul 06 05:51:46 PM PDT 24 336364610000 ps
T190 /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.895160858 Jul 06 05:17:20 PM PDT 24 Jul 06 05:43:31 PM PDT 24 336543090000 ps
T191 /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.635441254 Jul 06 05:17:09 PM PDT 24 Jul 06 05:51:34 PM PDT 24 337114170000 ps
T192 /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.2808765682 Jul 06 05:17:23 PM PDT 24 Jul 06 05:44:20 PM PDT 24 337054770000 ps
T193 /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.917516416 Jul 06 05:17:22 PM PDT 24 Jul 06 05:55:44 PM PDT 24 336434790000 ps
T194 /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.4080449452 Jul 06 05:17:14 PM PDT 24 Jul 06 05:58:07 PM PDT 24 336604070000 ps
T195 /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.3925580865 Jul 06 05:17:22 PM PDT 24 Jul 06 05:55:59 PM PDT 24 336892190000 ps
T196 /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.931462573 Jul 06 05:17:10 PM PDT 24 Jul 06 05:55:08 PM PDT 24 336348010000 ps
T197 /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.555364627 Jul 06 05:17:20 PM PDT 24 Jul 06 05:49:44 PM PDT 24 336795830000 ps
T198 /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.1550179106 Jul 06 05:17:09 PM PDT 24 Jul 06 05:52:38 PM PDT 24 336855430000 ps
T199 /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3574420389 Jul 06 05:17:12 PM PDT 24 Jul 06 05:50:57 PM PDT 24 336927290000 ps
T200 /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.1137080189 Jul 06 05:17:15 PM PDT 24 Jul 06 05:58:41 PM PDT 24 337150210000 ps

Test location /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.3908993621
Short name T13
Test name
Test status
Simulation time 1512130000 ps
CPU time 3.26 seconds
Started Jul 06 04:23:26 PM PDT 24
Finished Jul 06 04:23:34 PM PDT 24
Peak memory 163772 kb
Host smart-915bb50f-ce9a-43dc-92ac-66a4065239b4
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3908993621 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.3908993621
Directory /workspace/32.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.3017195717
Short name T6
Test name
Test status
Simulation time 336350870000 ps
CPU time 656.81 seconds
Started Jul 06 05:14:35 PM PDT 24
Finished Jul 06 05:42:10 PM PDT 24
Peak memory 160796 kb
Host smart-ca04f7eb-9a13-4432-839e-580feb9f6a72
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3017195717 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.3017195717
Directory /workspace/20.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.3228933786
Short name T26
Test name
Test status
Simulation time 336913370000 ps
CPU time 813.17 seconds
Started Jul 06 05:17:20 PM PDT 24
Finished Jul 06 05:50:33 PM PDT 24
Peak memory 160784 kb
Host smart-99989d23-eb48-4ddf-aa66-2acc5a46d98b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3228933786 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.3228933786
Directory /workspace/12.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.4155461312
Short name T95
Test name
Test status
Simulation time 336342890000 ps
CPU time 801.32 seconds
Started Jul 06 05:14:38 PM PDT 24
Finished Jul 06 05:47:33 PM PDT 24
Peak memory 160792 kb
Host smart-faf627ab-193c-45dc-97af-c6d5a760d8ff
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4155461312 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.4155461312
Directory /workspace/0.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.4105009726
Short name T79
Test name
Test status
Simulation time 336778490000 ps
CPU time 737.51 seconds
Started Jul 06 05:14:38 PM PDT 24
Finished Jul 06 05:44:50 PM PDT 24
Peak memory 160788 kb
Host smart-37b1dc86-fada-4076-b692-dc7c4b1b7994
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4105009726 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.4105009726
Directory /workspace/1.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.3755918742
Short name T76
Test name
Test status
Simulation time 337085050000 ps
CPU time 868.4 seconds
Started Jul 06 05:14:36 PM PDT 24
Finished Jul 06 05:50:50 PM PDT 24
Peak memory 160704 kb
Host smart-dbd74749-3173-4e54-8804-cddd05a2b19f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3755918742 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.3755918742
Directory /workspace/10.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.3562104317
Short name T73
Test name
Test status
Simulation time 336602310000 ps
CPU time 800.9 seconds
Started Jul 06 05:14:31 PM PDT 24
Finished Jul 06 05:46:44 PM PDT 24
Peak memory 160708 kb
Host smart-6963b158-f5d6-4078-a3c8-e499ed5dd0f6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3562104317 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.3562104317
Directory /workspace/11.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.3936664362
Short name T82
Test name
Test status
Simulation time 336651030000 ps
CPU time 760.33 seconds
Started Jul 06 05:14:35 PM PDT 24
Finished Jul 06 05:45:34 PM PDT 24
Peak memory 160740 kb
Host smart-15ba6fd9-7eb1-47c7-9625-a6778ad0eb27
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3936664362 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.3936664362
Directory /workspace/12.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.2137484250
Short name T74
Test name
Test status
Simulation time 336491030000 ps
CPU time 737.13 seconds
Started Jul 06 05:14:42 PM PDT 24
Finished Jul 06 05:44:43 PM PDT 24
Peak memory 160800 kb
Host smart-a328958d-744a-4dcc-95d4-f9768386867b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2137484250 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.2137484250
Directory /workspace/13.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.2135079623
Short name T77
Test name
Test status
Simulation time 336732630000 ps
CPU time 862.25 seconds
Started Jul 06 05:14:32 PM PDT 24
Finished Jul 06 05:49:44 PM PDT 24
Peak memory 160800 kb
Host smart-ab775631-07ed-462f-b647-c156dd6959cb
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2135079623 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.2135079623
Directory /workspace/14.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.539739430
Short name T110
Test name
Test status
Simulation time 336838450000 ps
CPU time 812.46 seconds
Started Jul 06 05:14:40 PM PDT 24
Finished Jul 06 05:47:20 PM PDT 24
Peak memory 160768 kb
Host smart-e55a1984-feb9-416b-8df3-0780bb5822e1
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=539739430 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.539739430
Directory /workspace/15.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.1594964358
Short name T71
Test name
Test status
Simulation time 336652390000 ps
CPU time 730.01 seconds
Started Jul 06 05:14:38 PM PDT 24
Finished Jul 06 05:44:22 PM PDT 24
Peak memory 160808 kb
Host smart-5da93cdb-6d6b-4e92-9954-181e87e8c9f2
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1594964358 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.1594964358
Directory /workspace/16.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.2109541391
Short name T78
Test name
Test status
Simulation time 336459910000 ps
CPU time 797.77 seconds
Started Jul 06 05:14:41 PM PDT 24
Finished Jul 06 05:47:00 PM PDT 24
Peak memory 160776 kb
Host smart-bd19c468-3ce6-4059-ac38-3fca6ecb2980
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2109541391 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.2109541391
Directory /workspace/17.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.2839391868
Short name T108
Test name
Test status
Simulation time 336980650000 ps
CPU time 699.92 seconds
Started Jul 06 05:14:41 PM PDT 24
Finished Jul 06 05:43:18 PM PDT 24
Peak memory 160724 kb
Host smart-f1aa2249-6a6d-4591-baad-03abdd4a83e1
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2839391868 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.2839391868
Directory /workspace/18.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.4023154523
Short name T100
Test name
Test status
Simulation time 336766810000 ps
CPU time 799.43 seconds
Started Jul 06 05:14:46 PM PDT 24
Finished Jul 06 05:47:40 PM PDT 24
Peak memory 160800 kb
Host smart-eb3691ab-c805-4465-8719-a3c8b163f376
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4023154523 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.4023154523
Directory /workspace/19.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.1672216985
Short name T80
Test name
Test status
Simulation time 337200830000 ps
CPU time 820.02 seconds
Started Jul 06 05:14:39 PM PDT 24
Finished Jul 06 05:48:31 PM PDT 24
Peak memory 160792 kb
Host smart-adc08fcf-fb55-4ed2-9f18-34e57d4f4cb3
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1672216985 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.1672216985
Directory /workspace/2.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.2567521772
Short name T104
Test name
Test status
Simulation time 336649250000 ps
CPU time 752.82 seconds
Started Jul 06 05:14:39 PM PDT 24
Finished Jul 06 05:45:20 PM PDT 24
Peak memory 160792 kb
Host smart-32999223-2343-4c07-8a40-50e1d6f9d2f3
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2567521772 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.2567521772
Directory /workspace/21.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.4191102601
Short name T103
Test name
Test status
Simulation time 337032730000 ps
CPU time 814.54 seconds
Started Jul 06 05:14:40 PM PDT 24
Finished Jul 06 05:48:22 PM PDT 24
Peak memory 160764 kb
Host smart-d48bcfea-2f55-41bb-9a78-3641ecf605dd
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4191102601 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.4191102601
Directory /workspace/22.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.2833932419
Short name T72
Test name
Test status
Simulation time 336991830000 ps
CPU time 793.76 seconds
Started Jul 06 05:14:41 PM PDT 24
Finished Jul 06 05:46:39 PM PDT 24
Peak memory 160780 kb
Host smart-5ba6da0c-a040-41c3-bb7e-284b6285b24c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2833932419 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.2833932419
Directory /workspace/23.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.3146936123
Short name T20
Test name
Test status
Simulation time 336967390000 ps
CPU time 837.23 seconds
Started Jul 06 05:14:34 PM PDT 24
Finished Jul 06 05:48:30 PM PDT 24
Peak memory 160788 kb
Host smart-1729ddc5-d6ed-4294-b2fe-bea65e2a9b97
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3146936123 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.3146936123
Directory /workspace/24.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.412533318
Short name T88
Test name
Test status
Simulation time 336788790000 ps
CPU time 759.71 seconds
Started Jul 06 05:14:42 PM PDT 24
Finished Jul 06 05:46:00 PM PDT 24
Peak memory 160776 kb
Host smart-e8b9ed61-5d81-4feb-a727-96b4c2b6c68f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=412533318 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.412533318
Directory /workspace/25.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1387226198
Short name T5
Test name
Test status
Simulation time 336482310000 ps
CPU time 825.78 seconds
Started Jul 06 05:14:39 PM PDT 24
Finished Jul 06 05:48:10 PM PDT 24
Peak memory 160732 kb
Host smart-9e7c1617-987e-414d-95c1-8d44b009dd90
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1387226198 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.1387226198
Directory /workspace/26.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.4001029884
Short name T15
Test name
Test status
Simulation time 336690690000 ps
CPU time 715.92 seconds
Started Jul 06 05:14:38 PM PDT 24
Finished Jul 06 05:43:48 PM PDT 24
Peak memory 160796 kb
Host smart-85981d20-2d01-4196-a820-280b89d6727f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4001029884 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.4001029884
Directory /workspace/27.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.3627215115
Short name T94
Test name
Test status
Simulation time 336628970000 ps
CPU time 712.59 seconds
Started Jul 06 05:14:45 PM PDT 24
Finished Jul 06 05:43:45 PM PDT 24
Peak memory 160780 kb
Host smart-9d0001bf-20f0-42a1-934e-22155bb77c36
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3627215115 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.3627215115
Directory /workspace/28.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.3717954938
Short name T107
Test name
Test status
Simulation time 336939930000 ps
CPU time 735.92 seconds
Started Jul 06 05:14:36 PM PDT 24
Finished Jul 06 05:44:38 PM PDT 24
Peak memory 160708 kb
Host smart-616be012-d604-4c38-9342-181415d8b34f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3717954938 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.3717954938
Directory /workspace/29.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.3550045560
Short name T109
Test name
Test status
Simulation time 337056710000 ps
CPU time 801.27 seconds
Started Jul 06 05:14:42 PM PDT 24
Finished Jul 06 05:48:10 PM PDT 24
Peak memory 160744 kb
Host smart-bc8dfaeb-7c6d-4e1e-a572-68ab64f6e42f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3550045560 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.3550045560
Directory /workspace/3.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.4145220173
Short name T99
Test name
Test status
Simulation time 336888190000 ps
CPU time 726.17 seconds
Started Jul 06 05:14:42 PM PDT 24
Finished Jul 06 05:44:22 PM PDT 24
Peak memory 160820 kb
Host smart-397c6216-b17f-4f91-893d-37830b128092
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4145220173 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.4145220173
Directory /workspace/30.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.2151656848
Short name T93
Test name
Test status
Simulation time 336727530000 ps
CPU time 614.86 seconds
Started Jul 06 05:14:35 PM PDT 24
Finished Jul 06 05:40:37 PM PDT 24
Peak memory 160792 kb
Host smart-3d76f935-dbb4-41e8-9894-54a0f68a8b66
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2151656848 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.2151656848
Directory /workspace/31.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.2925037262
Short name T16
Test name
Test status
Simulation time 336483030000 ps
CPU time 812.41 seconds
Started Jul 06 05:14:46 PM PDT 24
Finished Jul 06 05:48:18 PM PDT 24
Peak memory 160800 kb
Host smart-29e2afaa-db9e-4995-99aa-8240545cb03a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2925037262 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.2925037262
Directory /workspace/32.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.2401632643
Short name T91
Test name
Test status
Simulation time 336706190000 ps
CPU time 754.63 seconds
Started Jul 06 05:14:41 PM PDT 24
Finished Jul 06 05:45:08 PM PDT 24
Peak memory 160788 kb
Host smart-fc7b692a-d5d6-4d84-935c-4cfc661ac58a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2401632643 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.2401632643
Directory /workspace/33.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.2315408371
Short name T102
Test name
Test status
Simulation time 336963470000 ps
CPU time 761.94 seconds
Started Jul 06 05:14:48 PM PDT 24
Finished Jul 06 05:46:06 PM PDT 24
Peak memory 160808 kb
Host smart-3b97c632-7abd-4821-bfb9-51190eeea550
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2315408371 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.2315408371
Directory /workspace/34.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.1583595724
Short name T81
Test name
Test status
Simulation time 336890430000 ps
CPU time 713 seconds
Started Jul 06 05:14:47 PM PDT 24
Finished Jul 06 05:43:48 PM PDT 24
Peak memory 160808 kb
Host smart-7675b731-c51c-4720-8803-a311b90d1bbe
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1583595724 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.1583595724
Directory /workspace/35.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.2995040264
Short name T7
Test name
Test status
Simulation time 336569770000 ps
CPU time 684.85 seconds
Started Jul 06 05:15:03 PM PDT 24
Finished Jul 06 05:43:19 PM PDT 24
Peak memory 160796 kb
Host smart-866f222b-27fb-4407-8706-81c514a6d071
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2995040264 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.2995040264
Directory /workspace/36.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.2043708076
Short name T85
Test name
Test status
Simulation time 336831230000 ps
CPU time 734.57 seconds
Started Jul 06 05:14:42 PM PDT 24
Finished Jul 06 05:44:46 PM PDT 24
Peak memory 160812 kb
Host smart-ed45b327-f8da-405f-a7f4-fda30b1d1d27
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2043708076 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.2043708076
Directory /workspace/37.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.4201557442
Short name T86
Test name
Test status
Simulation time 336767830000 ps
CPU time 877.18 seconds
Started Jul 06 05:14:40 PM PDT 24
Finished Jul 06 05:50:26 PM PDT 24
Peak memory 160792 kb
Host smart-653601ab-d49f-4a54-b606-60cbb6888ed2
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4201557442 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.4201557442
Directory /workspace/38.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.3335969103
Short name T84
Test name
Test status
Simulation time 336765810000 ps
CPU time 853.69 seconds
Started Jul 06 05:14:42 PM PDT 24
Finished Jul 06 05:49:34 PM PDT 24
Peak memory 160732 kb
Host smart-463b9772-0d64-4063-91c0-af74fb1dbfee
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3335969103 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.3335969103
Directory /workspace/39.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.2418777370
Short name T101
Test name
Test status
Simulation time 336899510000 ps
CPU time 970.13 seconds
Started Jul 06 05:14:34 PM PDT 24
Finished Jul 06 05:55:12 PM PDT 24
Peak memory 160788 kb
Host smart-11e1a202-a62e-4d11-838e-a25180936f0a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2418777370 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.2418777370
Directory /workspace/4.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.366173873
Short name T83
Test name
Test status
Simulation time 337190570000 ps
CPU time 722.22 seconds
Started Jul 06 05:14:42 PM PDT 24
Finished Jul 06 05:44:09 PM PDT 24
Peak memory 160756 kb
Host smart-4c9558e5-501a-4d8d-89ea-fea049daffa7
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=366173873 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.366173873
Directory /workspace/40.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.2962804464
Short name T17
Test name
Test status
Simulation time 336513890000 ps
CPU time 875.06 seconds
Started Jul 06 05:14:41 PM PDT 24
Finished Jul 06 05:50:47 PM PDT 24
Peak memory 160704 kb
Host smart-036bf96e-3e7e-4e6f-87b2-ce97b3d01ac7
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2962804464 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.2962804464
Directory /workspace/41.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.1153562022
Short name T89
Test name
Test status
Simulation time 336657490000 ps
CPU time 663.23 seconds
Started Jul 06 05:14:43 PM PDT 24
Finished Jul 06 05:42:24 PM PDT 24
Peak memory 160796 kb
Host smart-46ea14c9-6878-4c6e-9ae9-9a792af59b48
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1153562022 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.1153562022
Directory /workspace/42.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.2486904310
Short name T105
Test name
Test status
Simulation time 336794750000 ps
CPU time 762.54 seconds
Started Jul 06 05:14:41 PM PDT 24
Finished Jul 06 05:45:37 PM PDT 24
Peak memory 160792 kb
Host smart-31b95869-fa87-4847-bc4b-f53adfeadced
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2486904310 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.2486904310
Directory /workspace/43.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.3178082393
Short name T18
Test name
Test status
Simulation time 337004510000 ps
CPU time 744.38 seconds
Started Jul 06 05:14:40 PM PDT 24
Finished Jul 06 05:44:51 PM PDT 24
Peak memory 160792 kb
Host smart-904ce1f9-4d09-4dab-b5bd-d13e0cd87341
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3178082393 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.3178082393
Directory /workspace/44.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.3578315279
Short name T14
Test name
Test status
Simulation time 336736270000 ps
CPU time 967.27 seconds
Started Jul 06 05:14:43 PM PDT 24
Finished Jul 06 05:56:15 PM PDT 24
Peak memory 160788 kb
Host smart-799e5fea-1f27-4220-8404-a132690e0f88
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3578315279 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.3578315279
Directory /workspace/45.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.2564637950
Short name T106
Test name
Test status
Simulation time 336492070000 ps
CPU time 751.41 seconds
Started Jul 06 05:14:45 PM PDT 24
Finished Jul 06 05:45:13 PM PDT 24
Peak memory 160808 kb
Host smart-bd9ca503-7aa6-4050-8cc9-44c1371a9c26
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2564637950 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.2564637950
Directory /workspace/46.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.586322827
Short name T90
Test name
Test status
Simulation time 336795070000 ps
CPU time 786.14 seconds
Started Jul 06 05:14:45 PM PDT 24
Finished Jul 06 05:46:57 PM PDT 24
Peak memory 160768 kb
Host smart-35bf96d5-374e-4fea-b770-c6dd5787671b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=586322827 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.586322827
Directory /workspace/47.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.3322687310
Short name T96
Test name
Test status
Simulation time 336690190000 ps
CPU time 685.51 seconds
Started Jul 06 05:14:48 PM PDT 24
Finished Jul 06 05:42:52 PM PDT 24
Peak memory 160800 kb
Host smart-75ffa80a-de04-4730-bae1-741d490a5cb3
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3322687310 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.3322687310
Directory /workspace/48.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.2543218025
Short name T92
Test name
Test status
Simulation time 337095170000 ps
CPU time 933.5 seconds
Started Jul 06 05:14:42 PM PDT 24
Finished Jul 06 05:53:06 PM PDT 24
Peak memory 160792 kb
Host smart-4d84cd06-74d1-48cf-b77a-7446de8be253
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2543218025 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.2543218025
Directory /workspace/49.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.3423167122
Short name T75
Test name
Test status
Simulation time 336746230000 ps
CPU time 821.42 seconds
Started Jul 06 05:14:31 PM PDT 24
Finished Jul 06 05:47:43 PM PDT 24
Peak memory 160732 kb
Host smart-4096d226-06f3-4b4d-9379-8630de7f9304
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3423167122 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.3423167122
Directory /workspace/5.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.2933674288
Short name T87
Test name
Test status
Simulation time 337007230000 ps
CPU time 794.1 seconds
Started Jul 06 05:14:36 PM PDT 24
Finished Jul 06 05:46:49 PM PDT 24
Peak memory 160724 kb
Host smart-cf380e64-b102-4e88-a35b-4442d3efb286
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2933674288 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.2933674288
Directory /workspace/6.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.3673070691
Short name T98
Test name
Test status
Simulation time 336592230000 ps
CPU time 760.58 seconds
Started Jul 06 05:14:38 PM PDT 24
Finished Jul 06 05:45:19 PM PDT 24
Peak memory 160792 kb
Host smart-4a423129-ea30-411b-bcf1-8f6079226aa1
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3673070691 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.3673070691
Directory /workspace/7.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.2933128866
Short name T19
Test name
Test status
Simulation time 336564090000 ps
CPU time 858.16 seconds
Started Jul 06 05:14:35 PM PDT 24
Finished Jul 06 05:49:31 PM PDT 24
Peak memory 160732 kb
Host smart-9f12583b-e794-481d-98f6-4b1a8ed08c61
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2933128866 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.2933128866
Directory /workspace/8.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.510043832
Short name T97
Test name
Test status
Simulation time 336732530000 ps
CPU time 908.34 seconds
Started Jul 06 05:14:36 PM PDT 24
Finished Jul 06 05:52:19 PM PDT 24
Peak memory 160772 kb
Host smart-0d6e8b02-4026-44be-acce-0df2212d5d22
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=510043832 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.510043832
Directory /workspace/9.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.216888954
Short name T163
Test name
Test status
Simulation time 336323370000 ps
CPU time 743.23 seconds
Started Jul 06 05:17:11 PM PDT 24
Finished Jul 06 05:47:56 PM PDT 24
Peak memory 160760 kb
Host smart-d24205e7-ee89-4adb-bbc8-f47d81f0c070
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=216888954 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.216888954
Directory /workspace/0.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.3394832587
Short name T187
Test name
Test status
Simulation time 336583970000 ps
CPU time 899.62 seconds
Started Jul 06 05:17:21 PM PDT 24
Finished Jul 06 05:54:07 PM PDT 24
Peak memory 160800 kb
Host smart-898cc2e1-4994-4f2b-98c5-437d39e129cd
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3394832587 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.3394832587
Directory /workspace/1.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.3668685054
Short name T183
Test name
Test status
Simulation time 336512350000 ps
CPU time 835.65 seconds
Started Jul 06 05:17:09 PM PDT 24
Finished Jul 06 05:51:00 PM PDT 24
Peak memory 160792 kb
Host smart-b168d74c-c51d-41e2-a06b-b97c3be06586
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3668685054 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.3668685054
Directory /workspace/10.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.1718080743
Short name T188
Test name
Test status
Simulation time 336754330000 ps
CPU time 781.42 seconds
Started Jul 06 05:17:09 PM PDT 24
Finished Jul 06 05:49:16 PM PDT 24
Peak memory 160788 kb
Host smart-826e4337-9750-4053-af34-64f9f449c991
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1718080743 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.1718080743
Directory /workspace/11.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.3935137802
Short name T27
Test name
Test status
Simulation time 336919730000 ps
CPU time 862.22 seconds
Started Jul 06 05:17:11 PM PDT 24
Finished Jul 06 05:52:12 PM PDT 24
Peak memory 160736 kb
Host smart-45f91f40-619f-448e-9d09-ad716d3466a6
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3935137802 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.3935137802
Directory /workspace/13.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.2808765682
Short name T192
Test name
Test status
Simulation time 337054770000 ps
CPU time 650.38 seconds
Started Jul 06 05:17:23 PM PDT 24
Finished Jul 06 05:44:20 PM PDT 24
Peak memory 160664 kb
Host smart-f1f9bbb8-62de-468c-a45c-d7bf2da2ea04
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2808765682 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.2808765682
Directory /workspace/14.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.4128275662
Short name T166
Test name
Test status
Simulation time 336986690000 ps
CPU time 961.43 seconds
Started Jul 06 05:17:12 PM PDT 24
Finished Jul 06 05:58:14 PM PDT 24
Peak memory 160792 kb
Host smart-9b38ae1a-dede-4e5c-9111-4ec57bc6cf8d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4128275662 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.4128275662
Directory /workspace/15.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.2261788357
Short name T30
Test name
Test status
Simulation time 336961610000 ps
CPU time 593.78 seconds
Started Jul 06 05:17:43 PM PDT 24
Finished Jul 06 05:42:46 PM PDT 24
Peak memory 160764 kb
Host smart-bad9a9b4-1aca-46ab-a2c7-dd2b33aec1f1
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2261788357 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.2261788357
Directory /workspace/16.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.2611782240
Short name T170
Test name
Test status
Simulation time 336561430000 ps
CPU time 855.85 seconds
Started Jul 06 05:17:21 PM PDT 24
Finished Jul 06 05:52:15 PM PDT 24
Peak memory 160804 kb
Host smart-6d3d2ac9-eb0b-448b-b7e8-a0e5b3f07e80
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2611782240 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.2611782240
Directory /workspace/17.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.1065789453
Short name T25
Test name
Test status
Simulation time 336979950000 ps
CPU time 790.19 seconds
Started Jul 06 05:17:22 PM PDT 24
Finished Jul 06 05:50:11 PM PDT 24
Peak memory 160756 kb
Host smart-8e9a9cd7-fe28-4d82-be95-7cd605a03de8
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1065789453 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.1065789453
Directory /workspace/18.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.3403303310
Short name T167
Test name
Test status
Simulation time 337057450000 ps
CPU time 824.41 seconds
Started Jul 06 05:17:20 PM PDT 24
Finished Jul 06 05:51:24 PM PDT 24
Peak memory 160772 kb
Host smart-a0d22d8b-1f0f-434f-90e3-73fc9a6b4df7
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3403303310 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.3403303310
Directory /workspace/19.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.2218878515
Short name T178
Test name
Test status
Simulation time 336706290000 ps
CPU time 975.93 seconds
Started Jul 06 05:17:12 PM PDT 24
Finished Jul 06 05:58:47 PM PDT 24
Peak memory 160792 kb
Host smart-8ebd2315-8040-4686-a96a-41e067a57bbe
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2218878515 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.2218878515
Directory /workspace/2.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.800040825
Short name T182
Test name
Test status
Simulation time 336665570000 ps
CPU time 758.83 seconds
Started Jul 06 05:17:19 PM PDT 24
Finished Jul 06 05:48:16 PM PDT 24
Peak memory 160736 kb
Host smart-bc5e6983-ecdc-4257-8b90-9c016dd34f47
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=800040825 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.800040825
Directory /workspace/20.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3574420389
Short name T199
Test name
Test status
Simulation time 336927290000 ps
CPU time 819.01 seconds
Started Jul 06 05:17:12 PM PDT 24
Finished Jul 06 05:50:57 PM PDT 24
Peak memory 160768 kb
Host smart-064633e8-1f3f-41e1-af6d-f2817122da78
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3574420389 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.3574420389
Directory /workspace/21.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.151304666
Short name T161
Test name
Test status
Simulation time 336320670000 ps
CPU time 623.46 seconds
Started Jul 06 05:17:22 PM PDT 24
Finished Jul 06 05:43:16 PM PDT 24
Peak memory 160804 kb
Host smart-e502eb78-c459-474a-9ec1-f4903f5e3b4d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=151304666 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.151304666
Directory /workspace/22.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.1550179106
Short name T198
Test name
Test status
Simulation time 336855430000 ps
CPU time 871.1 seconds
Started Jul 06 05:17:09 PM PDT 24
Finished Jul 06 05:52:38 PM PDT 24
Peak memory 160796 kb
Host smart-f1c16d86-8a1f-409a-93f4-0f789867329c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1550179106 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.1550179106
Directory /workspace/23.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.1137080189
Short name T200
Test name
Test status
Simulation time 337150210000 ps
CPU time 972.56 seconds
Started Jul 06 05:17:15 PM PDT 24
Finished Jul 06 05:58:41 PM PDT 24
Peak memory 160792 kb
Host smart-26400e73-8f7a-4a25-80f8-4f65b3754db9
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1137080189 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.1137080189
Directory /workspace/24.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.635441254
Short name T191
Test name
Test status
Simulation time 337114170000 ps
CPU time 847.79 seconds
Started Jul 06 05:17:09 PM PDT 24
Finished Jul 06 05:51:34 PM PDT 24
Peak memory 160792 kb
Host smart-36c28a43-9ca1-4689-8522-97ebb14bba22
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=635441254 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.635441254
Directory /workspace/25.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.2365207009
Short name T21
Test name
Test status
Simulation time 336934650000 ps
CPU time 850.76 seconds
Started Jul 06 05:17:23 PM PDT 24
Finished Jul 06 05:52:13 PM PDT 24
Peak memory 160720 kb
Host smart-86e0658f-ea6f-44c2-abbf-a275786ede04
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2365207009 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.2365207009
Directory /workspace/26.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.691517713
Short name T173
Test name
Test status
Simulation time 336333770000 ps
CPU time 760.26 seconds
Started Jul 06 05:17:13 PM PDT 24
Finished Jul 06 05:49:12 PM PDT 24
Peak memory 160796 kb
Host smart-9182ad05-7cee-4284-8e53-18d4b09cf3f7
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=691517713 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.691517713
Directory /workspace/27.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.2714951871
Short name T174
Test name
Test status
Simulation time 336476310000 ps
CPU time 699.87 seconds
Started Jul 06 05:17:26 PM PDT 24
Finished Jul 06 05:45:51 PM PDT 24
Peak memory 160800 kb
Host smart-620ecb4c-091c-4d52-819f-0b1c089c102d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2714951871 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.2714951871
Directory /workspace/28.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.1399553308
Short name T186
Test name
Test status
Simulation time 336708690000 ps
CPU time 907.7 seconds
Started Jul 06 05:17:14 PM PDT 24
Finished Jul 06 05:54:37 PM PDT 24
Peak memory 160776 kb
Host smart-f25402ba-01e1-4d7f-ba96-fd7afa1e2d77
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1399553308 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.1399553308
Directory /workspace/29.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.577746543
Short name T29
Test name
Test status
Simulation time 336862390000 ps
CPU time 853.7 seconds
Started Jul 06 05:17:17 PM PDT 24
Finished Jul 06 05:51:48 PM PDT 24
Peak memory 160780 kb
Host smart-26f94cfc-9d63-4333-a9c6-ad3d5dba4309
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=577746543 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.577746543
Directory /workspace/3.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.1274253289
Short name T171
Test name
Test status
Simulation time 336778570000 ps
CPU time 743.09 seconds
Started Jul 06 05:17:06 PM PDT 24
Finished Jul 06 05:47:29 PM PDT 24
Peak memory 160800 kb
Host smart-d43ab4f7-b409-4ca5-a359-39c27e689eb6
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1274253289 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.1274253289
Directory /workspace/30.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.410791391
Short name T172
Test name
Test status
Simulation time 336421650000 ps
CPU time 745.08 seconds
Started Jul 06 05:17:17 PM PDT 24
Finished Jul 06 05:47:43 PM PDT 24
Peak memory 160796 kb
Host smart-21f7df15-83d6-4beb-9af4-e8049de44a46
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=410791391 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.410791391
Directory /workspace/31.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.2828812289
Short name T28
Test name
Test status
Simulation time 336585490000 ps
CPU time 706.56 seconds
Started Jul 06 05:17:19 PM PDT 24
Finished Jul 06 05:46:04 PM PDT 24
Peak memory 160800 kb
Host smart-aea3e4cd-cddf-46c8-a26d-eb995491fb02
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2828812289 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.2828812289
Directory /workspace/32.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.3052430016
Short name T184
Test name
Test status
Simulation time 336481470000 ps
CPU time 768.88 seconds
Started Jul 06 05:17:16 PM PDT 24
Finished Jul 06 05:49:45 PM PDT 24
Peak memory 160796 kb
Host smart-29e0eed1-1648-4a28-938e-e9a5884cf29d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3052430016 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.3052430016
Directory /workspace/33.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.800321838
Short name T181
Test name
Test status
Simulation time 336566930000 ps
CPU time 851.04 seconds
Started Jul 06 05:17:25 PM PDT 24
Finished Jul 06 05:51:49 PM PDT 24
Peak memory 160796 kb
Host smart-2472c71e-e114-4b95-b8e1-8d118fe2bf7c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=800321838 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.800321838
Directory /workspace/34.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.761921725
Short name T177
Test name
Test status
Simulation time 336941670000 ps
CPU time 788.53 seconds
Started Jul 06 05:17:29 PM PDT 24
Finished Jul 06 05:49:28 PM PDT 24
Peak memory 160808 kb
Host smart-a09492c5-a62c-4caa-89ff-5d8e2fe804a8
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=761921725 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.761921725
Directory /workspace/35.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.1109323498
Short name T168
Test name
Test status
Simulation time 336672510000 ps
CPU time 926.92 seconds
Started Jul 06 05:17:15 PM PDT 24
Finished Jul 06 05:55:32 PM PDT 24
Peak memory 160796 kb
Host smart-09767124-c9f1-4a62-aa53-446d447e3c7c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1109323498 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.1109323498
Directory /workspace/36.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.1219533837
Short name T189
Test name
Test status
Simulation time 336364610000 ps
CPU time 847.71 seconds
Started Jul 06 05:17:24 PM PDT 24
Finished Jul 06 05:51:46 PM PDT 24
Peak memory 160804 kb
Host smart-b0697d6f-9328-4d44-9195-45cf78402b22
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1219533837 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.1219533837
Directory /workspace/37.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.1605584625
Short name T164
Test name
Test status
Simulation time 336892770000 ps
CPU time 838.22 seconds
Started Jul 06 05:17:12 PM PDT 24
Finished Jul 06 05:51:24 PM PDT 24
Peak memory 160780 kb
Host smart-6a230bcc-4ba2-49d8-a56d-49980a693ed8
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1605584625 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.1605584625
Directory /workspace/38.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.3925580865
Short name T195
Test name
Test status
Simulation time 336892190000 ps
CPU time 932.88 seconds
Started Jul 06 05:17:22 PM PDT 24
Finished Jul 06 05:55:59 PM PDT 24
Peak memory 160800 kb
Host smart-7f455c6e-1088-4de3-b3ca-37577c8cb8ab
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3925580865 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.3925580865
Directory /workspace/39.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.895160858
Short name T190
Test name
Test status
Simulation time 336543090000 ps
CPU time 629.96 seconds
Started Jul 06 05:17:20 PM PDT 24
Finished Jul 06 05:43:31 PM PDT 24
Peak memory 160808 kb
Host smart-232daa89-971f-4083-b504-e98808750d3e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=895160858 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.895160858
Directory /workspace/4.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.931462573
Short name T196
Test name
Test status
Simulation time 336348010000 ps
CPU time 912.2 seconds
Started Jul 06 05:17:10 PM PDT 24
Finished Jul 06 05:55:08 PM PDT 24
Peak memory 160776 kb
Host smart-36a45317-d342-42c3-b2a3-00591e6a86b2
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=931462573 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.931462573
Directory /workspace/40.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.1050236734
Short name T23
Test name
Test status
Simulation time 336724370000 ps
CPU time 708.82 seconds
Started Jul 06 05:17:12 PM PDT 24
Finished Jul 06 05:46:31 PM PDT 24
Peak memory 160788 kb
Host smart-6c01ccff-8a28-4129-8b73-4f092d342259
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1050236734 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.1050236734
Directory /workspace/41.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.4080449452
Short name T194
Test name
Test status
Simulation time 336604070000 ps
CPU time 945.67 seconds
Started Jul 06 05:17:14 PM PDT 24
Finished Jul 06 05:58:07 PM PDT 24
Peak memory 160792 kb
Host smart-b4a2ef74-ae0d-4c89-8bd2-6140264a7fde
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4080449452 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.4080449452
Directory /workspace/42.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.2567651338
Short name T185
Test name
Test status
Simulation time 336541990000 ps
CPU time 766.77 seconds
Started Jul 06 05:17:17 PM PDT 24
Finished Jul 06 05:48:35 PM PDT 24
Peak memory 160812 kb
Host smart-e6a3fddd-cd6c-4046-a391-b1c63ee95d30
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2567651338 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.2567651338
Directory /workspace/43.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.3704723046
Short name T24
Test name
Test status
Simulation time 336834330000 ps
CPU time 763.86 seconds
Started Jul 06 05:17:17 PM PDT 24
Finished Jul 06 05:48:23 PM PDT 24
Peak memory 160756 kb
Host smart-194f80d5-bd85-442e-9bd8-1223c068aade
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3704723046 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.3704723046
Directory /workspace/44.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.183642825
Short name T179
Test name
Test status
Simulation time 337032910000 ps
CPU time 732.85 seconds
Started Jul 06 05:17:20 PM PDT 24
Finished Jul 06 05:47:21 PM PDT 24
Peak memory 160796 kb
Host smart-74dd77d3-f3e0-45b6-9636-b95dd39d4fe0
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=183642825 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.183642825
Directory /workspace/45.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.555364627
Short name T197
Test name
Test status
Simulation time 336795830000 ps
CPU time 790.11 seconds
Started Jul 06 05:17:20 PM PDT 24
Finished Jul 06 05:49:44 PM PDT 24
Peak memory 160796 kb
Host smart-6d5749f7-8d07-410d-9ec4-7dec677886ed
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=555364627 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.555364627
Directory /workspace/46.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.917516416
Short name T193
Test name
Test status
Simulation time 336434790000 ps
CPU time 930.59 seconds
Started Jul 06 05:17:22 PM PDT 24
Finished Jul 06 05:55:44 PM PDT 24
Peak memory 160796 kb
Host smart-c8a9ad79-17a3-4f92-b4c9-e822547e9103
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=917516416 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.917516416
Directory /workspace/47.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1330568672
Short name T175
Test name
Test status
Simulation time 336607070000 ps
CPU time 750.51 seconds
Started Jul 06 05:17:18 PM PDT 24
Finished Jul 06 05:48:53 PM PDT 24
Peak memory 160796 kb
Host smart-fca55c08-b1d3-451c-b2e7-9e83c9fb2a32
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1330568672 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.1330568672
Directory /workspace/48.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.3487934811
Short name T169
Test name
Test status
Simulation time 336438070000 ps
CPU time 890.55 seconds
Started Jul 06 05:17:14 PM PDT 24
Finished Jul 06 05:53:37 PM PDT 24
Peak memory 160804 kb
Host smart-9106908b-fdca-4fd1-8b4e-82a9cb970f2b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3487934811 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.3487934811
Directory /workspace/49.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.3881471790
Short name T22
Test name
Test status
Simulation time 336669450000 ps
CPU time 849.79 seconds
Started Jul 06 05:17:08 PM PDT 24
Finished Jul 06 05:52:55 PM PDT 24
Peak memory 160700 kb
Host smart-aff60611-799a-4fae-a409-ffc12f0a7629
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3881471790 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.3881471790
Directory /workspace/5.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.3420536516
Short name T180
Test name
Test status
Simulation time 336518850000 ps
CPU time 682.6 seconds
Started Jul 06 05:17:23 PM PDT 24
Finished Jul 06 05:45:32 PM PDT 24
Peak memory 160796 kb
Host smart-1a550323-b0f4-40ab-a3f8-0e8ae71adc96
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3420536516 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.3420536516
Directory /workspace/6.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.3403737209
Short name T162
Test name
Test status
Simulation time 336723790000 ps
CPU time 753.34 seconds
Started Jul 06 05:17:05 PM PDT 24
Finished Jul 06 05:47:45 PM PDT 24
Peak memory 160792 kb
Host smart-cb528baa-4a50-4fdb-8f35-8546b25f279f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3403737209 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.3403737209
Directory /workspace/7.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.1368460796
Short name T176
Test name
Test status
Simulation time 336531490000 ps
CPU time 738.66 seconds
Started Jul 06 05:17:16 PM PDT 24
Finished Jul 06 05:47:20 PM PDT 24
Peak memory 160796 kb
Host smart-00655f14-ea57-4cd7-96f6-1c51e8437a60
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1368460796 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.1368460796
Directory /workspace/8.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.4103995507
Short name T165
Test name
Test status
Simulation time 337068790000 ps
CPU time 788.63 seconds
Started Jul 06 05:17:25 PM PDT 24
Finished Jul 06 05:50:07 PM PDT 24
Peak memory 160748 kb
Host smart-35175228-636d-4b4b-9770-e192adb02852
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4103995507 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.4103995507
Directory /workspace/9.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.2813961264
Short name T120
Test name
Test status
Simulation time 1514150000 ps
CPU time 3.78 seconds
Started Jul 06 05:17:16 PM PDT 24
Finished Jul 06 05:17:25 PM PDT 24
Peak memory 164900 kb
Host smart-ba57fb31-cf1b-4fce-8b50-e4d8038982ec
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2813961264 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.2813961264
Directory /workspace/0.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.1994116096
Short name T121
Test name
Test status
Simulation time 1485170000 ps
CPU time 4.24 seconds
Started Jul 06 05:17:07 PM PDT 24
Finished Jul 06 05:17:19 PM PDT 24
Peak memory 164944 kb
Host smart-5ccbe7dc-d0a1-4c6d-b797-701f8a63da1d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1994116096 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.1994116096
Directory /workspace/1.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.1366013845
Short name T144
Test name
Test status
Simulation time 1637630000 ps
CPU time 4.16 seconds
Started Jul 06 05:17:06 PM PDT 24
Finished Jul 06 05:17:16 PM PDT 24
Peak memory 166488 kb
Host smart-c48466ee-fdcb-4556-b51e-294bb25611a4
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1366013845 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.1366013845
Directory /workspace/10.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.843297197
Short name T150
Test name
Test status
Simulation time 1554770000 ps
CPU time 5.09 seconds
Started Jul 06 05:17:04 PM PDT 24
Finished Jul 06 05:17:16 PM PDT 24
Peak memory 164948 kb
Host smart-fc078475-3c11-4472-abe4-7e1fbec08fd0
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=843297197 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.843297197
Directory /workspace/11.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.3703355141
Short name T112
Test name
Test status
Simulation time 1300210000 ps
CPU time 3.76 seconds
Started Jul 06 05:17:20 PM PDT 24
Finished Jul 06 05:17:28 PM PDT 24
Peak memory 164916 kb
Host smart-2dd8c058-8090-4ef6-a295-76852a6a7feb
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3703355141 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.3703355141
Directory /workspace/12.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.2683292626
Short name T133
Test name
Test status
Simulation time 1512410000 ps
CPU time 4.34 seconds
Started Jul 06 05:17:14 PM PDT 24
Finished Jul 06 05:17:24 PM PDT 24
Peak memory 164976 kb
Host smart-8f08659e-c19e-4966-810d-3cd33095a866
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2683292626 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.2683292626
Directory /workspace/13.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.1268215294
Short name T114
Test name
Test status
Simulation time 1492510000 ps
CPU time 3.39 seconds
Started Jul 06 05:17:19 PM PDT 24
Finished Jul 06 05:17:27 PM PDT 24
Peak memory 164904 kb
Host smart-d42115be-7286-4355-9f38-c97359177792
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1268215294 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.1268215294
Directory /workspace/14.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.807554018
Short name T113
Test name
Test status
Simulation time 1346330000 ps
CPU time 4.01 seconds
Started Jul 06 05:17:15 PM PDT 24
Finished Jul 06 05:17:24 PM PDT 24
Peak memory 164972 kb
Host smart-280b5daf-aa9e-453c-a22e-d4146f538cb4
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=807554018 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.807554018
Directory /workspace/15.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.651099469
Short name T160
Test name
Test status
Simulation time 1365970000 ps
CPU time 4 seconds
Started Jul 06 05:17:06 PM PDT 24
Finished Jul 06 05:17:16 PM PDT 24
Peak memory 164972 kb
Host smart-2b6dab5e-3c61-403a-8e2e-cbf4cfb24f43
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=651099469 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.651099469
Directory /workspace/16.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.3166095291
Short name T117
Test name
Test status
Simulation time 1468950000 ps
CPU time 4.83 seconds
Started Jul 06 05:17:03 PM PDT 24
Finished Jul 06 05:17:14 PM PDT 24
Peak memory 166488 kb
Host smart-92e03de6-c3a9-47c4-b96c-df9364a66d3b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3166095291 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.3166095291
Directory /workspace/17.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.590847925
Short name T136
Test name
Test status
Simulation time 1338470000 ps
CPU time 3.47 seconds
Started Jul 06 05:17:08 PM PDT 24
Finished Jul 06 05:17:17 PM PDT 24
Peak memory 164900 kb
Host smart-e4a3b335-e059-42f4-9d00-dfdd475ea148
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=590847925 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.590847925
Directory /workspace/18.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.674199380
Short name T132
Test name
Test status
Simulation time 1216650000 ps
CPU time 3.7 seconds
Started Jul 06 05:17:07 PM PDT 24
Finished Jul 06 05:17:17 PM PDT 24
Peak memory 164968 kb
Host smart-6f483d59-eac3-4d61-af7f-0945a4987ef9
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=674199380 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.674199380
Directory /workspace/19.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.1495840440
Short name T119
Test name
Test status
Simulation time 1196830000 ps
CPU time 2.93 seconds
Started Jul 06 05:17:10 PM PDT 24
Finished Jul 06 05:17:18 PM PDT 24
Peak memory 164888 kb
Host smart-46640727-44ea-45d6-860a-b1645630be36
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1495840440 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.1495840440
Directory /workspace/2.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.3087829583
Short name T151
Test name
Test status
Simulation time 1326510000 ps
CPU time 3.75 seconds
Started Jul 06 05:17:00 PM PDT 24
Finished Jul 06 05:17:09 PM PDT 24
Peak memory 166484 kb
Host smart-461c18fa-668d-4e2c-977f-cce1126bc589
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3087829583 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.3087829583
Directory /workspace/20.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3688750717
Short name T137
Test name
Test status
Simulation time 1557810000 ps
CPU time 3.56 seconds
Started Jul 06 05:17:07 PM PDT 24
Finished Jul 06 05:17:16 PM PDT 24
Peak memory 164916 kb
Host smart-b55efe4c-e40a-49ef-957d-acf895675c5f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3688750717 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.3688750717
Directory /workspace/21.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.1464159255
Short name T152
Test name
Test status
Simulation time 1622390000 ps
CPU time 3.53 seconds
Started Jul 06 05:17:38 PM PDT 24
Finished Jul 06 05:17:46 PM PDT 24
Peak memory 164916 kb
Host smart-d3b17bb3-e8b3-4f97-951a-30d48d5cda82
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1464159255 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.1464159255
Directory /workspace/22.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.2009260944
Short name T148
Test name
Test status
Simulation time 1493930000 ps
CPU time 5.4 seconds
Started Jul 06 05:17:06 PM PDT 24
Finished Jul 06 05:17:19 PM PDT 24
Peak memory 164872 kb
Host smart-bcbea859-b0e9-4223-9189-68fcae117370
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2009260944 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.2009260944
Directory /workspace/23.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.3939131381
Short name T124
Test name
Test status
Simulation time 1613710000 ps
CPU time 4.19 seconds
Started Jul 06 05:17:12 PM PDT 24
Finished Jul 06 05:17:22 PM PDT 24
Peak memory 164900 kb
Host smart-50f7e731-0e21-481b-b42e-e6442618a1ee
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3939131381 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.3939131381
Directory /workspace/24.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.111070868
Short name T159
Test name
Test status
Simulation time 1504790000 ps
CPU time 4.53 seconds
Started Jul 06 05:17:07 PM PDT 24
Finished Jul 06 05:17:19 PM PDT 24
Peak memory 164948 kb
Host smart-5fc98738-a85c-4344-879d-13b33f9d80bd
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=111070868 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.111070868
Directory /workspace/25.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.3558049614
Short name T149
Test name
Test status
Simulation time 1581890000 ps
CPU time 5.25 seconds
Started Jul 06 05:17:05 PM PDT 24
Finished Jul 06 05:17:18 PM PDT 24
Peak memory 166436 kb
Host smart-da0a405d-457f-4295-a8cd-cca4de8c97fe
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3558049614 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.3558049614
Directory /workspace/26.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.2465746243
Short name T154
Test name
Test status
Simulation time 1484070000 ps
CPU time 4.34 seconds
Started Jul 06 05:17:10 PM PDT 24
Finished Jul 06 05:17:21 PM PDT 24
Peak memory 164976 kb
Host smart-1854eea3-6c97-4a1a-9350-96cacd6a53e3
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2465746243 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.2465746243
Directory /workspace/27.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.2810789445
Short name T145
Test name
Test status
Simulation time 1452090000 ps
CPU time 4.95 seconds
Started Jul 06 05:17:00 PM PDT 24
Finished Jul 06 05:17:11 PM PDT 24
Peak memory 166480 kb
Host smart-b23fc4d2-e477-420b-a1ff-db0e1592fb4f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2810789445 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.2810789445
Directory /workspace/28.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.1258582002
Short name T153
Test name
Test status
Simulation time 1530730000 ps
CPU time 5.18 seconds
Started Jul 06 05:17:02 PM PDT 24
Finished Jul 06 05:17:14 PM PDT 24
Peak memory 166480 kb
Host smart-c942a574-5ccf-489e-9884-58427a0072ed
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1258582002 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.1258582002
Directory /workspace/29.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.3223525206
Short name T131
Test name
Test status
Simulation time 1417570000 ps
CPU time 3.96 seconds
Started Jul 06 05:17:06 PM PDT 24
Finished Jul 06 05:17:16 PM PDT 24
Peak memory 164968 kb
Host smart-c4cbae84-27ca-4d60-8201-803b05333695
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3223525206 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.3223525206
Directory /workspace/3.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.2815247225
Short name T157
Test name
Test status
Simulation time 1370390000 ps
CPU time 3.71 seconds
Started Jul 06 05:17:07 PM PDT 24
Finished Jul 06 05:17:17 PM PDT 24
Peak memory 164976 kb
Host smart-66e9b4fe-968d-4bb7-a342-b5a1b033bb99
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2815247225 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.2815247225
Directory /workspace/30.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.1246035463
Short name T116
Test name
Test status
Simulation time 1500830000 ps
CPU time 3.75 seconds
Started Jul 06 05:17:14 PM PDT 24
Finished Jul 06 05:17:22 PM PDT 24
Peak memory 164980 kb
Host smart-96026ed9-048d-4401-8dc9-41d605c485f1
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1246035463 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.1246035463
Directory /workspace/31.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.1065511422
Short name T115
Test name
Test status
Simulation time 1350750000 ps
CPU time 3.86 seconds
Started Jul 06 05:17:12 PM PDT 24
Finished Jul 06 05:17:22 PM PDT 24
Peak memory 166488 kb
Host smart-004d824f-10b4-4445-9913-65c83229cd72
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1065511422 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.1065511422
Directory /workspace/32.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.3836607953
Short name T123
Test name
Test status
Simulation time 1557690000 ps
CPU time 4.44 seconds
Started Jul 06 05:17:08 PM PDT 24
Finished Jul 06 05:17:19 PM PDT 24
Peak memory 164900 kb
Host smart-d46f7600-8ee7-45a5-bfce-2223ca3705c4
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3836607953 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.3836607953
Directory /workspace/33.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.1947496373
Short name T146
Test name
Test status
Simulation time 1515870000 ps
CPU time 4.06 seconds
Started Jul 06 05:17:23 PM PDT 24
Finished Jul 06 05:17:32 PM PDT 24
Peak memory 164916 kb
Host smart-11ea640f-8f2d-432a-bdbb-ded092a1056f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1947496373 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.1947496373
Directory /workspace/34.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.3394566487
Short name T134
Test name
Test status
Simulation time 1495430000 ps
CPU time 4.16 seconds
Started Jul 06 05:17:09 PM PDT 24
Finished Jul 06 05:17:20 PM PDT 24
Peak memory 164888 kb
Host smart-098123aa-a933-425e-87bb-abd1f376e921
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3394566487 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.3394566487
Directory /workspace/35.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.216348949
Short name T126
Test name
Test status
Simulation time 1561650000 ps
CPU time 3.83 seconds
Started Jul 06 05:17:07 PM PDT 24
Finished Jul 06 05:17:17 PM PDT 24
Peak memory 164968 kb
Host smart-20cb0b47-fa1e-4a95-9406-83e2f09d8372
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=216348949 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.216348949
Directory /workspace/36.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1801105303
Short name T128
Test name
Test status
Simulation time 1402890000 ps
CPU time 4.11 seconds
Started Jul 06 05:17:14 PM PDT 24
Finished Jul 06 05:17:24 PM PDT 24
Peak memory 164972 kb
Host smart-9645d2f2-30a3-4a2d-a91d-4dc82ee2dd7e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1801105303 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.1801105303
Directory /workspace/37.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.1176920720
Short name T122
Test name
Test status
Simulation time 1562090000 ps
CPU time 5.3 seconds
Started Jul 06 05:17:05 PM PDT 24
Finished Jul 06 05:17:17 PM PDT 24
Peak memory 166488 kb
Host smart-1a9e196e-8506-4234-8d44-94d912a5e5f5
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1176920720 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.1176920720
Directory /workspace/38.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.2375612198
Short name T158
Test name
Test status
Simulation time 1519370000 ps
CPU time 5.09 seconds
Started Jul 06 05:17:00 PM PDT 24
Finished Jul 06 05:17:11 PM PDT 24
Peak memory 164940 kb
Host smart-7cf5aeff-87b0-450d-9e2b-7f05a55ea69a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2375612198 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.2375612198
Directory /workspace/39.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.544955843
Short name T155
Test name
Test status
Simulation time 1470050000 ps
CPU time 4.44 seconds
Started Jul 06 05:17:02 PM PDT 24
Finished Jul 06 05:17:12 PM PDT 24
Peak memory 164964 kb
Host smart-570fedc8-18dd-4cf7-b138-dd77a48b4003
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=544955843 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.544955843
Directory /workspace/4.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.1336050090
Short name T156
Test name
Test status
Simulation time 1539250000 ps
CPU time 5.34 seconds
Started Jul 06 05:17:05 PM PDT 24
Finished Jul 06 05:17:18 PM PDT 24
Peak memory 164940 kb
Host smart-d6ea6636-5955-4167-bd04-c3dbf8258a34
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1336050090 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.1336050090
Directory /workspace/40.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.1928306441
Short name T129
Test name
Test status
Simulation time 1533770000 ps
CPU time 4.7 seconds
Started Jul 06 05:17:10 PM PDT 24
Finished Jul 06 05:17:21 PM PDT 24
Peak memory 166484 kb
Host smart-30826767-24b5-4341-8a57-b833fb8b7b10
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1928306441 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.1928306441
Directory /workspace/41.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.1812360032
Short name T139
Test name
Test status
Simulation time 1358410000 ps
CPU time 4 seconds
Started Jul 06 05:17:16 PM PDT 24
Finished Jul 06 05:17:25 PM PDT 24
Peak memory 164976 kb
Host smart-98cdea44-d7a1-4d9f-bae2-73f1ea6c1484
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1812360032 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.1812360032
Directory /workspace/42.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1497338955
Short name T130
Test name
Test status
Simulation time 1520130000 ps
CPU time 4.28 seconds
Started Jul 06 05:17:21 PM PDT 24
Finished Jul 06 05:17:31 PM PDT 24
Peak memory 164876 kb
Host smart-e1a036b5-e864-4951-8542-a13688904b4f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1497338955 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.1497338955
Directory /workspace/43.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.1462676386
Short name T140
Test name
Test status
Simulation time 1527930000 ps
CPU time 3.39 seconds
Started Jul 06 05:17:02 PM PDT 24
Finished Jul 06 05:17:11 PM PDT 24
Peak memory 166512 kb
Host smart-13689aaf-d11c-41eb-837c-82f59d9341b1
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1462676386 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.1462676386
Directory /workspace/44.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.3149747780
Short name T142
Test name
Test status
Simulation time 1642070000 ps
CPU time 4.18 seconds
Started Jul 06 05:17:09 PM PDT 24
Finished Jul 06 05:17:20 PM PDT 24
Peak memory 164952 kb
Host smart-02b0c528-3ed9-4890-bab6-8dd57b093f5f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3149747780 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.3149747780
Directory /workspace/45.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.324610072
Short name T111
Test name
Test status
Simulation time 1602150000 ps
CPU time 4.38 seconds
Started Jul 06 05:17:18 PM PDT 24
Finished Jul 06 05:17:28 PM PDT 24
Peak memory 164916 kb
Host smart-21f0a5b7-5e68-46d5-8ecd-d06e09a57c5e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=324610072 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.324610072
Directory /workspace/46.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.1541352429
Short name T127
Test name
Test status
Simulation time 1243170000 ps
CPU time 3.73 seconds
Started Jul 06 05:17:12 PM PDT 24
Finished Jul 06 05:17:21 PM PDT 24
Peak memory 166488 kb
Host smart-84005cd5-b377-40d7-be8c-6bffca52f3c0
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1541352429 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.1541352429
Directory /workspace/47.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.48762485
Short name T143
Test name
Test status
Simulation time 1387850000 ps
CPU time 3.73 seconds
Started Jul 06 05:17:15 PM PDT 24
Finished Jul 06 05:17:24 PM PDT 24
Peak memory 164912 kb
Host smart-04aee3a0-c1c1-44e1-b712-240643c94086
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=48762485 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.48762485
Directory /workspace/48.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.1742882621
Short name T147
Test name
Test status
Simulation time 1512810000 ps
CPU time 5.62 seconds
Started Jul 06 05:17:09 PM PDT 24
Finished Jul 06 05:17:23 PM PDT 24
Peak memory 164944 kb
Host smart-74b19264-8df0-4117-8e9e-280966b328fb
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1742882621 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.1742882621
Directory /workspace/49.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.661956205
Short name T135
Test name
Test status
Simulation time 1467710000 ps
CPU time 4.71 seconds
Started Jul 06 05:17:05 PM PDT 24
Finished Jul 06 05:17:16 PM PDT 24
Peak memory 164928 kb
Host smart-1b7754b8-ee6e-4e9b-9f23-366b9ab65364
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=661956205 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.661956205
Directory /workspace/5.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.437228171
Short name T138
Test name
Test status
Simulation time 1487290000 ps
CPU time 4.3 seconds
Started Jul 06 05:17:06 PM PDT 24
Finished Jul 06 05:17:16 PM PDT 24
Peak memory 164964 kb
Host smart-c7046bce-0423-4983-8a8a-3fda163112ea
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=437228171 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.437228171
Directory /workspace/6.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.2156449662
Short name T141
Test name
Test status
Simulation time 1564270000 ps
CPU time 5.19 seconds
Started Jul 06 05:17:04 PM PDT 24
Finished Jul 06 05:17:16 PM PDT 24
Peak memory 164948 kb
Host smart-a54643ff-bffc-4365-844a-920fb3e16f25
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2156449662 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.2156449662
Directory /workspace/7.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.2288649900
Short name T118
Test name
Test status
Simulation time 1324550000 ps
CPU time 4.05 seconds
Started Jul 06 05:17:14 PM PDT 24
Finished Jul 06 05:17:23 PM PDT 24
Peak memory 164972 kb
Host smart-6ba4d1b0-22ea-47e6-9193-43698c89341c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2288649900 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.2288649900
Directory /workspace/8.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.3180179226
Short name T125
Test name
Test status
Simulation time 1382550000 ps
CPU time 4.22 seconds
Started Jul 06 05:17:04 PM PDT 24
Finished Jul 06 05:17:13 PM PDT 24
Peak memory 164872 kb
Host smart-0babe596-06f3-4fe3-8784-f4d0595671bc
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3180179226 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.3180179226
Directory /workspace/9.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.2551293166
Short name T68
Test name
Test status
Simulation time 1397030000 ps
CPU time 3.89 seconds
Started Jul 06 04:19:32 PM PDT 24
Finished Jul 06 04:19:41 PM PDT 24
Peak memory 164816 kb
Host smart-98635697-5ce7-48d3-bb36-f1db8e67f910
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2551293166 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.2551293166
Directory /workspace/0.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.2581806486
Short name T53
Test name
Test status
Simulation time 1488690000 ps
CPU time 3.91 seconds
Started Jul 06 04:23:29 PM PDT 24
Finished Jul 06 04:23:38 PM PDT 24
Peak memory 164584 kb
Host smart-e7c470e4-3ba1-41e2-bd4d-7b9eeb3ecaed
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2581806486 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.2581806486
Directory /workspace/1.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.1750660341
Short name T60
Test name
Test status
Simulation time 1505150000 ps
CPU time 3.68 seconds
Started Jul 06 04:23:04 PM PDT 24
Finished Jul 06 04:23:12 PM PDT 24
Peak memory 164756 kb
Host smart-3c8a2614-7e55-42a0-9e62-493058b304ec
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1750660341 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.1750660341
Directory /workspace/10.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.2243826404
Short name T37
Test name
Test status
Simulation time 1443590000 ps
CPU time 4.55 seconds
Started Jul 06 04:21:44 PM PDT 24
Finished Jul 06 04:21:54 PM PDT 24
Peak memory 164776 kb
Host smart-cb9206ad-0aaa-4497-8486-c7018e66b068
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2243826404 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.2243826404
Directory /workspace/11.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.1386440084
Short name T63
Test name
Test status
Simulation time 1569650000 ps
CPU time 4.89 seconds
Started Jul 06 04:22:00 PM PDT 24
Finished Jul 06 04:22:11 PM PDT 24
Peak memory 164816 kb
Host smart-e5ae9620-1ef0-4a95-8a3f-67951959caa7
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1386440084 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.1386440084
Directory /workspace/12.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.92203028
Short name T56
Test name
Test status
Simulation time 1507130000 ps
CPU time 3.68 seconds
Started Jul 06 04:23:28 PM PDT 24
Finished Jul 06 04:23:37 PM PDT 24
Peak memory 164584 kb
Host smart-03bc821f-f151-4fda-9104-70bb20a1d480
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=92203028 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.92203028
Directory /workspace/13.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.711666628
Short name T44
Test name
Test status
Simulation time 1462690000 ps
CPU time 3.87 seconds
Started Jul 06 04:23:29 PM PDT 24
Finished Jul 06 04:23:38 PM PDT 24
Peak memory 164584 kb
Host smart-4c7a1d2f-977c-4f0a-8f12-76b5d8cb5a36
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=711666628 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.711666628
Directory /workspace/14.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.1252904032
Short name T11
Test name
Test status
Simulation time 1335570000 ps
CPU time 4.04 seconds
Started Jul 06 04:23:20 PM PDT 24
Finished Jul 06 04:23:29 PM PDT 24
Peak memory 164796 kb
Host smart-9beffe31-cd93-4c47-87c8-e4561be76879
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1252904032 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.1252904032
Directory /workspace/15.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.1206294414
Short name T51
Test name
Test status
Simulation time 1489350000 ps
CPU time 4.34 seconds
Started Jul 06 04:23:32 PM PDT 24
Finished Jul 06 04:23:42 PM PDT 24
Peak memory 164956 kb
Host smart-745d9917-e9f7-4208-a5f7-4b2ed8841756
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1206294414 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.1206294414
Directory /workspace/16.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.3172973385
Short name T36
Test name
Test status
Simulation time 1362410000 ps
CPU time 3.75 seconds
Started Jul 06 04:21:55 PM PDT 24
Finished Jul 06 04:22:03 PM PDT 24
Peak memory 166372 kb
Host smart-2c051fd5-533e-46ba-90b6-51a636f15d9a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3172973385 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.3172973385
Directory /workspace/17.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.412034741
Short name T46
Test name
Test status
Simulation time 1241690000 ps
CPU time 3.19 seconds
Started Jul 06 04:23:27 PM PDT 24
Finished Jul 06 04:23:34 PM PDT 24
Peak memory 164576 kb
Host smart-2a3be6ee-b899-416b-a5ee-f52c879592d7
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=412034741 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.412034741
Directory /workspace/18.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.2960094991
Short name T58
Test name
Test status
Simulation time 1355890000 ps
CPU time 4.18 seconds
Started Jul 06 04:21:38 PM PDT 24
Finished Jul 06 04:21:47 PM PDT 24
Peak memory 164824 kb
Host smart-77d07827-94b9-4483-a9fd-bbab6664c92a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2960094991 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.2960094991
Directory /workspace/19.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.3114530524
Short name T40
Test name
Test status
Simulation time 1520610000 ps
CPU time 3.74 seconds
Started Jul 06 04:23:28 PM PDT 24
Finished Jul 06 04:23:37 PM PDT 24
Peak memory 164584 kb
Host smart-278716d0-0f4f-47a0-b8aa-22f5a0ad115d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3114530524 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.3114530524
Directory /workspace/2.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.2685244830
Short name T61
Test name
Test status
Simulation time 1373010000 ps
CPU time 4.47 seconds
Started Jul 06 04:23:41 PM PDT 24
Finished Jul 06 04:23:51 PM PDT 24
Peak memory 164932 kb
Host smart-2d070b10-8c46-4fd9-bc52-d081370e408f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2685244830 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.2685244830
Directory /workspace/20.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.2364147806
Short name T67
Test name
Test status
Simulation time 1434090000 ps
CPU time 3.69 seconds
Started Jul 06 04:23:30 PM PDT 24
Finished Jul 06 04:23:39 PM PDT 24
Peak memory 164304 kb
Host smart-3d5419f1-456a-4feb-8470-13df4b7e22dc
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2364147806 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.2364147806
Directory /workspace/21.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.2246104845
Short name T52
Test name
Test status
Simulation time 1418810000 ps
CPU time 4.27 seconds
Started Jul 06 04:19:32 PM PDT 24
Finished Jul 06 04:19:41 PM PDT 24
Peak memory 164812 kb
Host smart-ffe0c427-39cd-40b6-96e8-e6a05eaaaac8
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2246104845 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.2246104845
Directory /workspace/22.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.3501008237
Short name T70
Test name
Test status
Simulation time 1342290000 ps
CPU time 3.28 seconds
Started Jul 06 04:21:49 PM PDT 24
Finished Jul 06 04:21:56 PM PDT 24
Peak memory 164752 kb
Host smart-edc26fb7-2892-4d5f-987f-51e01a327b6a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3501008237 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.3501008237
Directory /workspace/23.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.1118987175
Short name T41
Test name
Test status
Simulation time 1376190000 ps
CPU time 3.73 seconds
Started Jul 06 04:23:36 PM PDT 24
Finished Jul 06 04:23:45 PM PDT 24
Peak memory 164372 kb
Host smart-a2ad698e-ebeb-467d-8f5f-ff62c6497304
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1118987175 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.1118987175
Directory /workspace/24.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.1177872618
Short name T59
Test name
Test status
Simulation time 1464990000 ps
CPU time 4.56 seconds
Started Jul 06 04:19:28 PM PDT 24
Finished Jul 06 04:19:38 PM PDT 24
Peak memory 164776 kb
Host smart-5a2aafd6-4c58-4a7f-add5-759e30edaf6e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1177872618 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.1177872618
Directory /workspace/25.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.2008941015
Short name T66
Test name
Test status
Simulation time 1340490000 ps
CPU time 3.91 seconds
Started Jul 06 04:23:30 PM PDT 24
Finished Jul 06 04:23:40 PM PDT 24
Peak memory 164364 kb
Host smart-c689cbfb-366d-42ea-9671-0c44d4b8c6a3
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2008941015 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.2008941015
Directory /workspace/26.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.2485671780
Short name T45
Test name
Test status
Simulation time 1493110000 ps
CPU time 3.16 seconds
Started Jul 06 04:21:26 PM PDT 24
Finished Jul 06 04:21:33 PM PDT 24
Peak memory 165036 kb
Host smart-13edc620-9586-4025-aabe-1ae85d71a3b8
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2485671780 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.2485671780
Directory /workspace/27.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.1229694250
Short name T8
Test name
Test status
Simulation time 1313830000 ps
CPU time 2.79 seconds
Started Jul 06 04:22:59 PM PDT 24
Finished Jul 06 04:23:06 PM PDT 24
Peak memory 164340 kb
Host smart-e2638068-814b-466d-aa4e-b4ba9966b5ec
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1229694250 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.1229694250
Directory /workspace/28.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.2101131494
Short name T64
Test name
Test status
Simulation time 1449850000 ps
CPU time 4.31 seconds
Started Jul 06 04:20:25 PM PDT 24
Finished Jul 06 04:20:35 PM PDT 24
Peak memory 164776 kb
Host smart-a50f0fbc-7974-410a-8db8-03af5c3b0f08
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2101131494 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.2101131494
Directory /workspace/29.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.107550349
Short name T69
Test name
Test status
Simulation time 1414310000 ps
CPU time 4.46 seconds
Started Jul 06 04:23:43 PM PDT 24
Finished Jul 06 04:23:54 PM PDT 24
Peak memory 164624 kb
Host smart-8177124b-e9d0-4790-a080-553dcbe0054d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=107550349 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.107550349
Directory /workspace/3.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.2573720928
Short name T32
Test name
Test status
Simulation time 1306610000 ps
CPU time 4.1 seconds
Started Jul 06 04:21:55 PM PDT 24
Finished Jul 06 04:22:04 PM PDT 24
Peak memory 166372 kb
Host smart-ffc260df-804b-4212-902f-11f4a53050cf
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2573720928 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.2573720928
Directory /workspace/30.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.2167846609
Short name T55
Test name
Test status
Simulation time 1544270000 ps
CPU time 3.46 seconds
Started Jul 06 04:23:26 PM PDT 24
Finished Jul 06 04:23:34 PM PDT 24
Peak memory 163176 kb
Host smart-b0bb1bd1-4602-4db0-8c1b-3017796f3997
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2167846609 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.2167846609
Directory /workspace/31.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.4035462859
Short name T38
Test name
Test status
Simulation time 1295390000 ps
CPU time 4.29 seconds
Started Jul 06 04:19:28 PM PDT 24
Finished Jul 06 04:19:38 PM PDT 24
Peak memory 164740 kb
Host smart-48f41cac-14ae-4c1f-9386-7d89a3a4a166
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4035462859 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.4035462859
Directory /workspace/33.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.3867814800
Short name T43
Test name
Test status
Simulation time 1633070000 ps
CPU time 3.55 seconds
Started Jul 06 04:23:26 PM PDT 24
Finished Jul 06 04:23:34 PM PDT 24
Peak memory 163044 kb
Host smart-4f116cb5-0828-4df6-a062-3072a0da630c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3867814800 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.3867814800
Directory /workspace/34.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.562517048
Short name T54
Test name
Test status
Simulation time 1390770000 ps
CPU time 4.06 seconds
Started Jul 06 04:23:43 PM PDT 24
Finished Jul 06 04:23:55 PM PDT 24
Peak memory 163096 kb
Host smart-9cc3e9b2-58da-4000-b656-a5dd8db7e167
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=562517048 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.562517048
Directory /workspace/35.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.4251151572
Short name T10
Test name
Test status
Simulation time 1584670000 ps
CPU time 3.67 seconds
Started Jul 06 04:23:17 PM PDT 24
Finished Jul 06 04:23:25 PM PDT 24
Peak memory 164548 kb
Host smart-42824048-b7f5-4187-a96e-f95cf91b6ed9
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4251151572 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.4251151572
Directory /workspace/36.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.3697315462
Short name T39
Test name
Test status
Simulation time 1567310000 ps
CPU time 4.27 seconds
Started Jul 06 04:23:43 PM PDT 24
Finished Jul 06 04:23:55 PM PDT 24
Peak memory 162676 kb
Host smart-7f818acb-e4cd-4f2b-bae1-1eb289d71ec1
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3697315462 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.3697315462
Directory /workspace/37.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.3371753677
Short name T65
Test name
Test status
Simulation time 1576210000 ps
CPU time 4.26 seconds
Started Jul 06 04:23:44 PM PDT 24
Finished Jul 06 04:23:55 PM PDT 24
Peak memory 164052 kb
Host smart-d72cd90a-9d9b-4762-a6ed-36324d69bf12
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3371753677 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.3371753677
Directory /workspace/38.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.4138343592
Short name T4
Test name
Test status
Simulation time 1305370000 ps
CPU time 3.16 seconds
Started Jul 06 04:23:16 PM PDT 24
Finished Jul 06 04:23:24 PM PDT 24
Peak memory 164548 kb
Host smart-e9ba71e9-1b9e-4f08-800b-802daaf84236
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4138343592 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.4138343592
Directory /workspace/39.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.3947423459
Short name T31
Test name
Test status
Simulation time 1431150000 ps
CPU time 3.04 seconds
Started Jul 06 04:23:11 PM PDT 24
Finished Jul 06 04:23:18 PM PDT 24
Peak memory 164340 kb
Host smart-bebed8d4-dda3-4e9a-a2d3-56a4a9d3a0db
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3947423459 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.3947423459
Directory /workspace/4.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.1755121719
Short name T3
Test name
Test status
Simulation time 944850000 ps
CPU time 2.85 seconds
Started Jul 06 04:23:30 PM PDT 24
Finished Jul 06 04:23:37 PM PDT 24
Peak memory 166016 kb
Host smart-de4be9d0-f979-4f39-9277-ae7be34106b0
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1755121719 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.1755121719
Directory /workspace/40.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.3795786359
Short name T34
Test name
Test status
Simulation time 1495050000 ps
CPU time 4.84 seconds
Started Jul 06 04:19:23 PM PDT 24
Finished Jul 06 04:19:33 PM PDT 24
Peak memory 164784 kb
Host smart-96e72ae0-c788-45cc-9664-d0a422601906
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3795786359 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.3795786359
Directory /workspace/41.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.1355911446
Short name T50
Test name
Test status
Simulation time 1509730000 ps
CPU time 4.29 seconds
Started Jul 06 04:23:43 PM PDT 24
Finished Jul 06 04:23:55 PM PDT 24
Peak memory 162836 kb
Host smart-6d998182-d7a8-4031-9a50-4d9662182c9b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1355911446 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.1355911446
Directory /workspace/42.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.3640480346
Short name T62
Test name
Test status
Simulation time 1379770000 ps
CPU time 4.33 seconds
Started Jul 06 04:20:10 PM PDT 24
Finished Jul 06 04:20:20 PM PDT 24
Peak memory 164776 kb
Host smart-fc6db06f-6ada-487d-9d6e-88c244c411a7
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3640480346 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.3640480346
Directory /workspace/43.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.506446858
Short name T47
Test name
Test status
Simulation time 1338170000 ps
CPU time 3.92 seconds
Started Jul 06 04:22:00 PM PDT 24
Finished Jul 06 04:22:08 PM PDT 24
Peak memory 164752 kb
Host smart-2c491992-471c-43cc-b605-a7917b33454c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=506446858 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.506446858
Directory /workspace/44.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.2610661008
Short name T57
Test name
Test status
Simulation time 1483410000 ps
CPU time 3.62 seconds
Started Jul 06 04:23:18 PM PDT 24
Finished Jul 06 04:23:26 PM PDT 24
Peak memory 164324 kb
Host smart-2b3c8ea2-41a2-445f-a6d7-f37cb1e37c07
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2610661008 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.2610661008
Directory /workspace/45.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.521948553
Short name T49
Test name
Test status
Simulation time 1405330000 ps
CPU time 4.19 seconds
Started Jul 06 04:23:43 PM PDT 24
Finished Jul 06 04:23:53 PM PDT 24
Peak memory 164620 kb
Host smart-0c630372-5678-438d-948b-64b2faa25a76
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=521948553 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.521948553
Directory /workspace/46.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.2868496849
Short name T2
Test name
Test status
Simulation time 1302370000 ps
CPU time 3.93 seconds
Started Jul 06 04:21:07 PM PDT 24
Finished Jul 06 04:21:16 PM PDT 24
Peak memory 164796 kb
Host smart-d8b16f2d-03a9-454d-9f64-fea1269561d9
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2868496849 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.2868496849
Directory /workspace/47.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.1610842689
Short name T33
Test name
Test status
Simulation time 1578230000 ps
CPU time 4.17 seconds
Started Jul 06 04:21:47 PM PDT 24
Finished Jul 06 04:21:57 PM PDT 24
Peak memory 164824 kb
Host smart-f99462c6-1cf2-445e-9790-f79d46f9f174
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1610842689 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.1610842689
Directory /workspace/48.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.812097469
Short name T12
Test name
Test status
Simulation time 1462370000 ps
CPU time 3.61 seconds
Started Jul 06 04:23:36 PM PDT 24
Finished Jul 06 04:23:45 PM PDT 24
Peak memory 164544 kb
Host smart-86ff136c-3172-47dd-ad0e-eaf5ad3ec04a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=812097469 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.812097469
Directory /workspace/49.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.1040209970
Short name T9
Test name
Test status
Simulation time 1517890000 ps
CPU time 3.41 seconds
Started Jul 06 04:23:43 PM PDT 24
Finished Jul 06 04:23:52 PM PDT 24
Peak memory 164572 kb
Host smart-8b353a2a-2ed3-497f-be33-d006668800dd
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1040209970 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.1040209970
Directory /workspace/5.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.4209008016
Short name T42
Test name
Test status
Simulation time 1307770000 ps
CPU time 3 seconds
Started Jul 06 04:23:25 PM PDT 24
Finished Jul 06 04:23:32 PM PDT 24
Peak memory 164384 kb
Host smart-13971466-6b9d-45ec-94f9-5e406d1b5f8b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4209008016 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.4209008016
Directory /workspace/6.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.2908503771
Short name T35
Test name
Test status
Simulation time 1419150000 ps
CPU time 3.74 seconds
Started Jul 06 04:23:37 PM PDT 24
Finished Jul 06 04:23:45 PM PDT 24
Peak memory 164544 kb
Host smart-aeb3c24c-00ae-4d95-ba96-5ae9d3005647
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2908503771 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.2908503771
Directory /workspace/7.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.3255674961
Short name T1
Test name
Test status
Simulation time 1568770000 ps
CPU time 4.84 seconds
Started Jul 06 04:23:58 PM PDT 24
Finished Jul 06 04:24:09 PM PDT 24
Peak memory 164460 kb
Host smart-8a5a11a0-0454-4f45-8cbd-e0c7f2f88f48
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3255674961 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.3255674961
Directory /workspace/8.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.2383383346
Short name T48
Test name
Test status
Simulation time 1506710000 ps
CPU time 3.14 seconds
Started Jul 06 04:23:20 PM PDT 24
Finished Jul 06 04:23:28 PM PDT 24
Peak memory 164340 kb
Host smart-1e1de587-9d17-4369-be84-8c6f5196e7bb
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2383383346 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.2383383346
Directory /workspace/9.prim_lfsr_gal_smoke/latest
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