Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.31 100.00 96.55 100.00 100.00 95.00


Total tests in report: 200
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
87.31 87.31 100.00 100.00 96.55 96.55 100.00 100.00 100.00 100.00 40.00 40.00 /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.3232176957
96.81 9.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 87.50 47.50 /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.2388427184
98.31 1.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 95.00 7.50 /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.3472457476

Tests that do not contribute to grading

Name
/workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.1762396735
/workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.4205840541
/workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.932951108
/workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.3934343638
/workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.64966515
/workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.3415911988
/workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.1496538190
/workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.2077326498
/workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.4128538783
/workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.1199033796
/workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.3039177942
/workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.1400740768
/workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.1149646497
/workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.3363217787
/workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.205941256
/workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.3111473724
/workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.2046812531
/workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.4021631768
/workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1303617153
/workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.2160722750
/workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.276700543
/workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.4235758119
/workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.1899143442
/workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.305388364
/workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.2521045152
/workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.2009554978
/workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.1760669363
/workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.4221511720
/workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.2729442592
/workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.1664636703
/workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.2002173272
/workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.1462080163
/workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.3273960656
/workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.1873376922
/workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.3572996563
/workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.1877225029
/workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.141197629
/workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.409206176
/workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.2867247338
/workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.2889882979
/workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.3470343698
/workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.3098605465
/workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.1126922668
/workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.4071887040
/workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.2157459770
/workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.2225502744
/workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.1837629995
/workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.322880545
/workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.2299899950
/workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.851358805
/workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.2414950828
/workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.2897076336
/workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.1578348735
/workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.3103562921
/workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.2781978556
/workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.2276335089
/workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.972063361
/workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.4012566252
/workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.784285592
/workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.3501091218
/workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.1094463610
/workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.999593937
/workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3272607813
/workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.811485946
/workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.1620668822
/workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.2435526178
/workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.1270199370
/workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.2213164893
/workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.2273867943
/workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.701514574
/workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.2370717411
/workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.1967406666
/workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.79205679
/workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.4225461891
/workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.744404152
/workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.3309711382
/workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.1780456290
/workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.3210725695
/workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.3031909691
/workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.982727236
/workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.1633965914
/workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.2377887976
/workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.2381225282
/workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.3086697401
/workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.2353586722
/workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.2368129626
/workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.3773240743
/workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.2561022428
/workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.3664990341
/workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.2229210775
/workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.842628534
/workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1674165300
/workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.3359129665
/workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.1307585097
/workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.1666711606
/workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.3476637109
/workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.169200519
/workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.3113212259
/workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.2786122399
/workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.1040040865
/workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.2449520301
/workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.67678832
/workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.1046535693
/workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.1194187979
/workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.4255655469
/workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.1494385797
/workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.2302404555
/workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.676050509
/workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.4200105972
/workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.1021252383
/workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.2543875329
/workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.2449905007
/workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.31059324
/workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.1212710421
/workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.599012356
/workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.2296659630
/workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.3646287167
/workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.3159229176
/workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.3181477259
/workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.1763347021
/workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.1204849636
/workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.726985539
/workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.3425655475
/workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.99178585
/workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.381141225
/workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.1279248565
/workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.2349671785
/workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.1263950453
/workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.4215393507
/workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1024225445
/workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.3579834740
/workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.2530909054
/workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.113099952
/workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.3778172911
/workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.178060172
/workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.1835129593
/workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.3796821773
/workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.2671374703
/workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.637184993
/workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.1541066471
/workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.3860733767
/workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.2699849529
/workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.1809769420
/workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.2434363911
/workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.3601878055
/workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.599853928
/workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1978457058
/workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.1200133530
/workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.2622392612
/workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.1484151150
/workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.2699097381
/workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.2211208888
/workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.2364565375
/workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.4186524893
/workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.1566240931
/workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.4179824720
/workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.941412259
/workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.484937116
/workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.2087501237
/workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.1375661859
/workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.335471085
/workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.1435552329
/workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.1103411925
/workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.1593973522
/workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.3595878769
/workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.1037930526
/workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.3519014097
/workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.3569164638
/workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.4201366978
/workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.539742110
/workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.138177932
/workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.2058132260
/workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.1700545597
/workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.507553579
/workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.3590650848
/workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.1043856746
/workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.429562497
/workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.1512931141
/workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.1277776977
/workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.1212385430
/workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.3627918785
/workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.751393993
/workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.2324445088
/workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.47440894
/workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.648804649
/workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.3030445939
/workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.3892417532
/workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.4042202246
/workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.820179308
/workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.3540140477
/workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.3098688781
/workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.474853027
/workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.3292432222
/workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.3513739680
/workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.1709071856
/workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.4262378885
/workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.2204474570



Total test records in report: 200
tests.html | tests1.html | tests2.html | tests3.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.507553579 Jul 07 04:30:24 PM PDT 24 Jul 07 04:30:34 PM PDT 24 1457330000 ps
T2 /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.4262378885 Jul 07 04:30:50 PM PDT 24 Jul 07 04:31:00 PM PDT 24 1475310000 ps
T3 /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.3232176957 Jul 07 04:30:41 PM PDT 24 Jul 07 04:30:52 PM PDT 24 1526870000 ps
T7 /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.3292432222 Jul 07 04:30:40 PM PDT 24 Jul 07 04:30:47 PM PDT 24 1463430000 ps
T8 /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.4201366978 Jul 07 04:30:33 PM PDT 24 Jul 07 04:30:43 PM PDT 24 1628270000 ps
T9 /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.2699097381 Jul 07 04:30:19 PM PDT 24 Jul 07 04:30:27 PM PDT 24 1464310000 ps
T10 /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.2204474570 Jul 07 04:30:29 PM PDT 24 Jul 07 04:30:36 PM PDT 24 1320130000 ps
T11 /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.3098688781 Jul 07 04:30:43 PM PDT 24 Jul 07 04:30:52 PM PDT 24 1394710000 ps
T12 /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.1212385430 Jul 07 04:30:32 PM PDT 24 Jul 07 04:30:39 PM PDT 24 1455970000 ps
T13 /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.941412259 Jul 07 04:30:23 PM PDT 24 Jul 07 04:30:31 PM PDT 24 1553710000 ps
T31 /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.2058132260 Jul 07 04:30:56 PM PDT 24 Jul 07 04:31:05 PM PDT 24 1532890000 ps
T32 /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.1566240931 Jul 07 04:30:39 PM PDT 24 Jul 07 04:30:47 PM PDT 24 1608690000 ps
T33 /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.3030445939 Jul 07 04:31:01 PM PDT 24 Jul 07 04:31:09 PM PDT 24 1431490000 ps
T34 /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.1043856746 Jul 07 04:30:33 PM PDT 24 Jul 07 04:30:40 PM PDT 24 1323950000 ps
T35 /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.3627918785 Jul 07 04:30:23 PM PDT 24 Jul 07 04:30:32 PM PDT 24 1498050000 ps
T36 /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.429562497 Jul 07 04:30:34 PM PDT 24 Jul 07 04:30:47 PM PDT 24 1535090000 ps
T37 /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.2211208888 Jul 07 04:30:20 PM PDT 24 Jul 07 04:30:27 PM PDT 24 1498730000 ps
T38 /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.1103411925 Jul 07 04:30:20 PM PDT 24 Jul 07 04:30:27 PM PDT 24 1542730000 ps
T39 /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.1593973522 Jul 07 04:30:33 PM PDT 24 Jul 07 04:30:41 PM PDT 24 1550990000 ps
T40 /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.539742110 Jul 07 04:30:26 PM PDT 24 Jul 07 04:30:33 PM PDT 24 1138810000 ps
T41 /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.47440894 Jul 07 04:30:29 PM PDT 24 Jul 07 04:30:35 PM PDT 24 1355430000 ps
T42 /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.2324445088 Jul 07 04:30:46 PM PDT 24 Jul 07 04:30:55 PM PDT 24 1572410000 ps
T43 /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.820179308 Jul 07 04:30:48 PM PDT 24 Jul 07 04:30:56 PM PDT 24 1538270000 ps
T44 /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.2622392612 Jul 07 04:30:49 PM PDT 24 Jul 07 04:31:02 PM PDT 24 1410470000 ps
T45 /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.1709071856 Jul 07 04:30:22 PM PDT 24 Jul 07 04:30:30 PM PDT 24 1470510000 ps
T46 /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.4042202246 Jul 07 04:30:44 PM PDT 24 Jul 07 04:30:52 PM PDT 24 1439130000 ps
T47 /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.4186524893 Jul 07 04:30:33 PM PDT 24 Jul 07 04:30:40 PM PDT 24 1434470000 ps
T48 /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.1375661859 Jul 07 04:30:25 PM PDT 24 Jul 07 04:30:34 PM PDT 24 1595830000 ps
T49 /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.2087501237 Jul 07 04:30:22 PM PDT 24 Jul 07 04:30:30 PM PDT 24 1649270000 ps
T50 /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.1700545597 Jul 07 04:30:49 PM PDT 24 Jul 07 04:30:57 PM PDT 24 1548090000 ps
T51 /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.138177932 Jul 07 04:30:41 PM PDT 24 Jul 07 04:30:48 PM PDT 24 1449450000 ps
T52 /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.4179824720 Jul 07 04:30:19 PM PDT 24 Jul 07 04:30:27 PM PDT 24 1511450000 ps
T53 /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.3569164638 Jul 07 04:31:06 PM PDT 24 Jul 07 04:31:14 PM PDT 24 1303670000 ps
T54 /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.3595878769 Jul 07 04:30:25 PM PDT 24 Jul 07 04:30:34 PM PDT 24 1433410000 ps
T55 /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.3513739680 Jul 07 04:30:30 PM PDT 24 Jul 07 04:30:44 PM PDT 24 1509770000 ps
T56 /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.3519014097 Jul 07 04:30:49 PM PDT 24 Jul 07 04:30:57 PM PDT 24 1526630000 ps
T57 /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.474853027 Jul 07 04:30:40 PM PDT 24 Jul 07 04:30:49 PM PDT 24 1436130000 ps
T58 /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.1277776977 Jul 07 04:30:22 PM PDT 24 Jul 07 04:30:29 PM PDT 24 1430870000 ps
T59 /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.3540140477 Jul 07 04:30:55 PM PDT 24 Jul 07 04:31:06 PM PDT 24 1585910000 ps
T60 /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.1512931141 Jul 07 04:30:48 PM PDT 24 Jul 07 04:30:54 PM PDT 24 1499090000 ps
T61 /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.751393993 Jul 07 04:30:56 PM PDT 24 Jul 07 04:31:03 PM PDT 24 1493830000 ps
T62 /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.3892417532 Jul 07 04:30:19 PM PDT 24 Jul 07 04:30:26 PM PDT 24 1571190000 ps
T63 /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.1484151150 Jul 07 04:30:26 PM PDT 24 Jul 07 04:30:33 PM PDT 24 1539950000 ps
T64 /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.335471085 Jul 07 04:30:16 PM PDT 24 Jul 07 04:30:25 PM PDT 24 1622430000 ps
T65 /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.1435552329 Jul 07 04:30:50 PM PDT 24 Jul 07 04:30:58 PM PDT 24 1427950000 ps
T66 /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.648804649 Jul 07 04:30:46 PM PDT 24 Jul 07 04:30:54 PM PDT 24 1503650000 ps
T67 /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.1037930526 Jul 07 04:30:27 PM PDT 24 Jul 07 04:30:40 PM PDT 24 1415330000 ps
T68 /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.2364565375 Jul 07 04:30:28 PM PDT 24 Jul 07 04:30:34 PM PDT 24 1427510000 ps
T69 /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.484937116 Jul 07 04:30:55 PM PDT 24 Jul 07 04:31:07 PM PDT 24 1482390000 ps
T70 /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.3590650848 Jul 07 04:30:42 PM PDT 24 Jul 07 04:30:49 PM PDT 24 1312910000 ps
T4 /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.3098605465 Jul 07 04:30:15 PM PDT 24 Jul 07 05:03:14 PM PDT 24 336668750000 ps
T5 /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.322880545 Jul 07 04:30:35 PM PDT 24 Jul 07 05:02:15 PM PDT 24 336793750000 ps
T6 /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.1462080163 Jul 07 04:30:18 PM PDT 24 Jul 07 05:13:53 PM PDT 24 337041310000 ps
T14 /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.3415911988 Jul 07 04:31:09 PM PDT 24 Jul 07 04:58:32 PM PDT 24 336789930000 ps
T15 /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.4071887040 Jul 07 04:30:27 PM PDT 24 Jul 07 04:59:45 PM PDT 24 337096230000 ps
T16 /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.4021631768 Jul 07 04:30:37 PM PDT 24 Jul 07 05:09:37 PM PDT 24 336963710000 ps
T17 /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.1837629995 Jul 07 04:30:20 PM PDT 24 Jul 07 05:04:15 PM PDT 24 336362990000 ps
T18 /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.2388427184 Jul 07 04:30:33 PM PDT 24 Jul 07 04:59:15 PM PDT 24 336544430000 ps
T19 /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.2160722750 Jul 07 04:30:23 PM PDT 24 Jul 07 05:00:07 PM PDT 24 336445650000 ps
T20 /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.3273960656 Jul 07 04:30:28 PM PDT 24 Jul 07 05:14:09 PM PDT 24 336768870000 ps
T71 /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.3934343638 Jul 07 04:30:19 PM PDT 24 Jul 07 05:14:00 PM PDT 24 337067770000 ps
T72 /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.1149646497 Jul 07 04:30:31 PM PDT 24 Jul 07 05:01:06 PM PDT 24 336699630000 ps
T73 /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.4235758119 Jul 07 04:30:28 PM PDT 24 Jul 07 05:14:23 PM PDT 24 336899890000 ps
T74 /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.2009554978 Jul 07 04:30:27 PM PDT 24 Jul 07 05:12:39 PM PDT 24 336389370000 ps
T75 /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1303617153 Jul 07 04:30:18 PM PDT 24 Jul 07 05:16:14 PM PDT 24 336955270000 ps
T76 /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.305388364 Jul 07 04:30:22 PM PDT 24 Jul 07 04:59:06 PM PDT 24 336905810000 ps
T77 /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.2729442592 Jul 07 04:30:21 PM PDT 24 Jul 07 04:58:53 PM PDT 24 337075510000 ps
T78 /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.4128538783 Jul 07 04:30:18 PM PDT 24 Jul 07 05:13:53 PM PDT 24 336867250000 ps
T79 /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.1496538190 Jul 07 04:30:24 PM PDT 24 Jul 07 05:01:34 PM PDT 24 336441410000 ps
T80 /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.205941256 Jul 07 04:30:39 PM PDT 24 Jul 07 05:09:36 PM PDT 24 337101390000 ps
T81 /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.3363217787 Jul 07 04:30:16 PM PDT 24 Jul 07 05:13:43 PM PDT 24 336980290000 ps
T82 /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.1199033796 Jul 07 04:30:21 PM PDT 24 Jul 07 05:00:59 PM PDT 24 336943310000 ps
T83 /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.2889882979 Jul 07 04:30:44 PM PDT 24 Jul 07 05:15:05 PM PDT 24 336972750000 ps
T84 /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.3572996563 Jul 07 04:30:47 PM PDT 24 Jul 07 05:04:04 PM PDT 24 336830670000 ps
T85 /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.1873376922 Jul 07 04:30:34 PM PDT 24 Jul 07 05:09:17 PM PDT 24 336457750000 ps
T86 /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.2046812531 Jul 07 04:30:23 PM PDT 24 Jul 07 05:08:40 PM PDT 24 337040870000 ps
T87 /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.4221511720 Jul 07 04:30:16 PM PDT 24 Jul 07 05:14:29 PM PDT 24 336970530000 ps
T88 /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.409206176 Jul 07 04:30:17 PM PDT 24 Jul 07 04:59:41 PM PDT 24 336477810000 ps
T89 /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.2299899950 Jul 07 04:30:16 PM PDT 24 Jul 07 05:14:50 PM PDT 24 336395390000 ps
T90 /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.3039177942 Jul 07 04:30:24 PM PDT 24 Jul 07 05:02:52 PM PDT 24 336789090000 ps
T91 /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.1400740768 Jul 07 04:30:20 PM PDT 24 Jul 07 04:57:37 PM PDT 24 336795610000 ps
T92 /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.2157459770 Jul 07 04:30:56 PM PDT 24 Jul 07 05:05:07 PM PDT 24 336862910000 ps
T93 /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.4205840541 Jul 07 04:30:16 PM PDT 24 Jul 07 05:15:28 PM PDT 24 337089390000 ps
T94 /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.1760669363 Jul 07 04:30:27 PM PDT 24 Jul 07 05:07:36 PM PDT 24 336413470000 ps
T95 /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.141197629 Jul 07 04:30:29 PM PDT 24 Jul 07 04:57:01 PM PDT 24 336407510000 ps
T96 /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.64966515 Jul 07 04:30:25 PM PDT 24 Jul 07 04:59:40 PM PDT 24 337007750000 ps
T97 /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.3111473724 Jul 07 04:30:27 PM PDT 24 Jul 07 05:14:50 PM PDT 24 336737330000 ps
T98 /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.2521045152 Jul 07 04:30:28 PM PDT 24 Jul 07 05:12:43 PM PDT 24 337100030000 ps
T99 /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.2077326498 Jul 07 04:30:23 PM PDT 24 Jul 07 04:59:41 PM PDT 24 336416510000 ps
T100 /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.276700543 Jul 07 04:30:16 PM PDT 24 Jul 07 05:15:52 PM PDT 24 336947090000 ps
T101 /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.1877225029 Jul 07 04:30:25 PM PDT 24 Jul 07 05:03:48 PM PDT 24 336572690000 ps
T102 /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.1762396735 Jul 07 04:30:27 PM PDT 24 Jul 07 04:59:08 PM PDT 24 336448410000 ps
T103 /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.1899143442 Jul 07 04:30:15 PM PDT 24 Jul 07 05:03:18 PM PDT 24 337105570000 ps
T104 /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.2867247338 Jul 07 04:30:25 PM PDT 24 Jul 07 04:59:23 PM PDT 24 336763610000 ps
T105 /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.1664636703 Jul 07 04:30:17 PM PDT 24 Jul 07 05:13:44 PM PDT 24 336315010000 ps
T106 /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.932951108 Jul 07 04:30:33 PM PDT 24 Jul 07 05:15:41 PM PDT 24 336513230000 ps
T107 /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.1126922668 Jul 07 04:30:21 PM PDT 24 Jul 07 04:58:48 PM PDT 24 336938890000 ps
T108 /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.2225502744 Jul 07 04:31:50 PM PDT 24 Jul 07 05:01:30 PM PDT 24 336498010000 ps
T109 /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.3470343698 Jul 07 04:30:21 PM PDT 24 Jul 07 05:00:34 PM PDT 24 336924510000 ps
T110 /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.2002173272 Jul 07 04:30:17 PM PDT 24 Jul 07 05:13:40 PM PDT 24 336912530000 ps
T111 /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.3601878055 Jul 07 04:37:58 PM PDT 24 Jul 07 04:38:09 PM PDT 24 1492270000 ps
T112 /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.3159229176 Jul 07 04:37:50 PM PDT 24 Jul 07 04:38:00 PM PDT 24 1400210000 ps
T113 /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.1494385797 Jul 07 04:38:03 PM PDT 24 Jul 07 04:38:14 PM PDT 24 1567590000 ps
T114 /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.178060172 Jul 07 04:38:19 PM PDT 24 Jul 07 04:38:27 PM PDT 24 1406330000 ps
T115 /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.1763347021 Jul 07 04:37:57 PM PDT 24 Jul 07 04:38:08 PM PDT 24 1489490000 ps
T116 /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.1835129593 Jul 07 04:37:59 PM PDT 24 Jul 07 04:38:08 PM PDT 24 1426750000 ps
T117 /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.1809769420 Jul 07 04:38:07 PM PDT 24 Jul 07 04:38:15 PM PDT 24 1489130000 ps
T118 /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.2543875329 Jul 07 04:37:54 PM PDT 24 Jul 07 04:38:06 PM PDT 24 1510810000 ps
T119 /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.31059324 Jul 07 04:38:02 PM PDT 24 Jul 07 04:38:13 PM PDT 24 1403290000 ps
T120 /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.1194187979 Jul 07 04:38:00 PM PDT 24 Jul 07 04:38:12 PM PDT 24 1393090000 ps
T121 /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.3778172911 Jul 07 04:37:58 PM PDT 24 Jul 07 04:38:08 PM PDT 24 1490170000 ps
T122 /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.1200133530 Jul 07 04:37:57 PM PDT 24 Jul 07 04:38:08 PM PDT 24 1463570000 ps
T123 /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.1212710421 Jul 07 04:37:57 PM PDT 24 Jul 07 04:38:03 PM PDT 24 1297110000 ps
T124 /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.1040040865 Jul 07 04:37:55 PM PDT 24 Jul 07 04:38:04 PM PDT 24 1515890000 ps
T125 /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.2449905007 Jul 07 04:37:53 PM PDT 24 Jul 07 04:38:06 PM PDT 24 1547810000 ps
T126 /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.4255655469 Jul 07 04:37:55 PM PDT 24 Jul 07 04:38:07 PM PDT 24 1492730000 ps
T127 /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.2349671785 Jul 07 04:38:03 PM PDT 24 Jul 07 04:38:12 PM PDT 24 1323090000 ps
T128 /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.2671374703 Jul 07 04:37:52 PM PDT 24 Jul 07 04:38:02 PM PDT 24 1527930000 ps
T129 /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.2699849529 Jul 07 04:37:55 PM PDT 24 Jul 07 04:38:07 PM PDT 24 1514870000 ps
T130 /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1024225445 Jul 07 04:37:55 PM PDT 24 Jul 07 04:38:02 PM PDT 24 1003730000 ps
T131 /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.2302404555 Jul 07 04:37:45 PM PDT 24 Jul 07 04:37:53 PM PDT 24 1440410000 ps
T132 /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.726985539 Jul 07 04:37:49 PM PDT 24 Jul 07 04:37:55 PM PDT 24 1333510000 ps
T133 /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.1263950453 Jul 07 04:38:00 PM PDT 24 Jul 07 04:38:11 PM PDT 24 1520410000 ps
T134 /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.2434363911 Jul 07 04:38:11 PM PDT 24 Jul 07 04:38:22 PM PDT 24 1528950000 ps
T135 /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.3860733767 Jul 07 04:37:52 PM PDT 24 Jul 07 04:38:01 PM PDT 24 1415930000 ps
T136 /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.1541066471 Jul 07 04:37:44 PM PDT 24 Jul 07 04:37:53 PM PDT 24 1396270000 ps
T137 /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.1279248565 Jul 07 04:37:46 PM PDT 24 Jul 07 04:37:56 PM PDT 24 1592630000 ps
T138 /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.3646287167 Jul 07 04:37:58 PM PDT 24 Jul 07 04:38:08 PM PDT 24 1579850000 ps
T139 /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.4215393507 Jul 07 04:37:53 PM PDT 24 Jul 07 04:38:01 PM PDT 24 1433390000 ps
T140 /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.599853928 Jul 07 04:37:52 PM PDT 24 Jul 07 04:38:02 PM PDT 24 1307570000 ps
T141 /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.2786122399 Jul 07 04:37:46 PM PDT 24 Jul 07 04:37:56 PM PDT 24 1487370000 ps
T142 /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.2296659630 Jul 07 04:38:00 PM PDT 24 Jul 07 04:38:10 PM PDT 24 1313410000 ps
T143 /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1978457058 Jul 07 04:37:57 PM PDT 24 Jul 07 04:38:08 PM PDT 24 1496310000 ps
T144 /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.1046535693 Jul 07 04:38:02 PM PDT 24 Jul 07 04:38:13 PM PDT 24 1455310000 ps
T145 /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.4200105972 Jul 07 04:37:43 PM PDT 24 Jul 07 04:37:54 PM PDT 24 1347650000 ps
T146 /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.676050509 Jul 07 04:37:56 PM PDT 24 Jul 07 04:38:04 PM PDT 24 1553610000 ps
T147 /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.637184993 Jul 07 04:38:00 PM PDT 24 Jul 07 04:38:12 PM PDT 24 1456050000 ps
T148 /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.3425655475 Jul 07 04:37:58 PM PDT 24 Jul 07 04:38:06 PM PDT 24 1361730000 ps
T149 /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.113099952 Jul 07 04:37:57 PM PDT 24 Jul 07 04:38:05 PM PDT 24 1453290000 ps
T150 /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.1021252383 Jul 07 04:37:54 PM PDT 24 Jul 07 04:38:04 PM PDT 24 1585710000 ps
T151 /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.381141225 Jul 07 04:38:00 PM PDT 24 Jul 07 04:38:13 PM PDT 24 1648410000 ps
T152 /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.3181477259 Jul 07 04:37:46 PM PDT 24 Jul 07 04:37:57 PM PDT 24 1564630000 ps
T153 /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.67678832 Jul 07 04:37:59 PM PDT 24 Jul 07 04:38:08 PM PDT 24 1143050000 ps
T154 /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.3796821773 Jul 07 04:37:42 PM PDT 24 Jul 07 04:37:49 PM PDT 24 988410000 ps
T155 /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.99178585 Jul 07 04:38:02 PM PDT 24 Jul 07 04:38:12 PM PDT 24 1595390000 ps
T156 /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.1204849636 Jul 07 04:38:00 PM PDT 24 Jul 07 04:38:10 PM PDT 24 1482570000 ps
T157 /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.3579834740 Jul 07 04:38:01 PM PDT 24 Jul 07 04:38:10 PM PDT 24 1547630000 ps
T158 /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.599012356 Jul 07 04:37:47 PM PDT 24 Jul 07 04:37:54 PM PDT 24 1531030000 ps
T159 /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.2449520301 Jul 07 04:37:57 PM PDT 24 Jul 07 04:38:08 PM PDT 24 1556850000 ps
T160 /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.2530909054 Jul 07 04:37:46 PM PDT 24 Jul 07 04:37:56 PM PDT 24 1476210000 ps
T21 /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.2897076336 Jul 07 05:49:13 PM PDT 24 Jul 07 06:22:20 PM PDT 24 336976630000 ps
T22 /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.3031909691 Jul 07 05:49:19 PM PDT 24 Jul 07 06:18:54 PM PDT 24 336343750000 ps
T23 /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.999593937 Jul 07 05:49:18 PM PDT 24 Jul 07 06:23:54 PM PDT 24 336719970000 ps
T24 /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.1666711606 Jul 07 05:49:16 PM PDT 24 Jul 07 06:24:34 PM PDT 24 336787050000 ps
T25 /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.1307585097 Jul 07 05:49:16 PM PDT 24 Jul 07 06:16:02 PM PDT 24 336460970000 ps
T26 /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.3210725695 Jul 07 05:49:25 PM PDT 24 Jul 07 06:22:30 PM PDT 24 337065650000 ps
T27 /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.3472457476 Jul 07 05:49:16 PM PDT 24 Jul 07 06:29:12 PM PDT 24 336436650000 ps
T28 /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.3476637109 Jul 07 05:49:14 PM PDT 24 Jul 07 06:19:07 PM PDT 24 336494410000 ps
T29 /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.2273867943 Jul 07 05:49:18 PM PDT 24 Jul 07 06:24:00 PM PDT 24 336618090000 ps
T30 /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.2370717411 Jul 07 05:49:18 PM PDT 24 Jul 07 06:20:20 PM PDT 24 336447650000 ps
T161 /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.811485946 Jul 07 05:49:25 PM PDT 24 Jul 07 06:22:31 PM PDT 24 337126070000 ps
T162 /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.3309711382 Jul 07 05:49:20 PM PDT 24 Jul 07 06:23:34 PM PDT 24 336927650000 ps
T163 /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.2781978556 Jul 07 05:49:16 PM PDT 24 Jul 07 06:22:20 PM PDT 24 337036410000 ps
T164 /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.79205679 Jul 07 05:49:24 PM PDT 24 Jul 07 06:33:58 PM PDT 24 337041890000 ps
T165 /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.842628534 Jul 07 05:49:24 PM PDT 24 Jul 07 06:33:50 PM PDT 24 336601850000 ps
T166 /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.3086697401 Jul 07 05:49:22 PM PDT 24 Jul 07 06:24:19 PM PDT 24 336659730000 ps
T167 /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.169200519 Jul 07 05:49:16 PM PDT 24 Jul 07 06:20:17 PM PDT 24 336861630000 ps
T168 /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.3664990341 Jul 07 05:49:18 PM PDT 24 Jul 07 06:23:47 PM PDT 24 336821050000 ps
T169 /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.972063361 Jul 07 05:49:12 PM PDT 24 Jul 07 06:19:46 PM PDT 24 336451690000 ps
T170 /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.784285592 Jul 07 05:49:18 PM PDT 24 Jul 07 06:22:50 PM PDT 24 336374610000 ps
T171 /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.4012566252 Jul 07 05:49:18 PM PDT 24 Jul 07 06:24:40 PM PDT 24 336401050000 ps
T172 /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.2414950828 Jul 07 05:49:13 PM PDT 24 Jul 07 06:20:55 PM PDT 24 336529930000 ps
T173 /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.1620668822 Jul 07 05:49:18 PM PDT 24 Jul 07 06:24:12 PM PDT 24 336737010000 ps
T174 /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.4225461891 Jul 07 05:49:20 PM PDT 24 Jul 07 06:22:57 PM PDT 24 336839050000 ps
T175 /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.982727236 Jul 07 05:49:23 PM PDT 24 Jul 07 06:21:41 PM PDT 24 336500730000 ps
T176 /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.2381225282 Jul 07 05:49:14 PM PDT 24 Jul 07 06:23:23 PM PDT 24 336551690000 ps
T177 /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.3773240743 Jul 07 05:49:18 PM PDT 24 Jul 07 06:25:11 PM PDT 24 336384370000 ps
T178 /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.701514574 Jul 07 05:49:17 PM PDT 24 Jul 07 06:17:56 PM PDT 24 336645830000 ps
T179 /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.1633965914 Jul 07 05:49:24 PM PDT 24 Jul 07 06:34:00 PM PDT 24 337133510000 ps
T180 /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.2213164893 Jul 07 05:49:22 PM PDT 24 Jul 07 06:29:19 PM PDT 24 336623570000 ps
T181 /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.1094463610 Jul 07 05:49:16 PM PDT 24 Jul 07 06:29:00 PM PDT 24 336929450000 ps
T182 /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.3103562921 Jul 07 05:49:14 PM PDT 24 Jul 07 06:23:26 PM PDT 24 336411630000 ps
T183 /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.2377887976 Jul 07 05:49:18 PM PDT 24 Jul 07 06:20:47 PM PDT 24 337066250000 ps
T184 /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.744404152 Jul 07 05:49:20 PM PDT 24 Jul 07 06:24:28 PM PDT 24 336350430000 ps
T185 /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.3359129665 Jul 07 05:49:22 PM PDT 24 Jul 07 06:15:19 PM PDT 24 336544710000 ps
T186 /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.1578348735 Jul 07 05:49:17 PM PDT 24 Jul 07 06:21:42 PM PDT 24 336652950000 ps
T187 /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.2353586722 Jul 07 05:49:18 PM PDT 24 Jul 07 06:26:17 PM PDT 24 336513690000 ps
T188 /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.1780456290 Jul 07 05:49:18 PM PDT 24 Jul 07 06:18:01 PM PDT 24 336775570000 ps
T189 /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.3501091218 Jul 07 05:49:24 PM PDT 24 Jul 07 06:33:52 PM PDT 24 336375350000 ps
T190 /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.1270199370 Jul 07 05:49:23 PM PDT 24 Jul 07 06:21:35 PM PDT 24 336893470000 ps
T191 /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.3113212259 Jul 07 05:49:13 PM PDT 24 Jul 07 06:22:03 PM PDT 24 337142830000 ps
T192 /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.2368129626 Jul 07 05:49:25 PM PDT 24 Jul 07 06:22:40 PM PDT 24 336861850000 ps
T193 /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.2276335089 Jul 07 05:49:14 PM PDT 24 Jul 07 06:21:14 PM PDT 24 336679730000 ps
T194 /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.1967406666 Jul 07 05:49:16 PM PDT 24 Jul 07 06:18:02 PM PDT 24 336487470000 ps
T195 /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.851358805 Jul 07 05:49:11 PM PDT 24 Jul 07 06:15:11 PM PDT 24 336951010000 ps
T196 /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.2561022428 Jul 07 05:49:18 PM PDT 24 Jul 07 06:25:33 PM PDT 24 336859670000 ps
T197 /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.2229210775 Jul 07 05:49:16 PM PDT 24 Jul 07 06:21:19 PM PDT 24 336720830000 ps
T198 /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3272607813 Jul 07 05:49:24 PM PDT 24 Jul 07 06:33:47 PM PDT 24 336782290000 ps
T199 /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.2435526178 Jul 07 05:49:21 PM PDT 24 Jul 07 06:20:31 PM PDT 24 336579990000 ps
T200 /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1674165300 Jul 07 05:49:23 PM PDT 24 Jul 07 06:24:02 PM PDT 24 336620230000 ps

Test location /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.3232176957
Short name T3
Test name
Test status
Simulation time 1526870000 ps
CPU time 4.74 seconds
Started Jul 07 04:30:41 PM PDT 24
Finished Jul 07 04:30:52 PM PDT 24
Peak memory 164720 kb
Host smart-5e74b61d-88f6-49da-8839-86426dc3626d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3232176957 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.3232176957
Directory /workspace/10.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.2388427184
Short name T18
Test name
Test status
Simulation time 336544430000 ps
CPU time 690.71 seconds
Started Jul 07 04:30:33 PM PDT 24
Finished Jul 07 04:59:15 PM PDT 24
Peak memory 160632 kb
Host smart-da471e1b-fc10-4c3b-8387-dbda381a65ef
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2388427184 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.2388427184
Directory /workspace/10.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.3472457476
Short name T27
Test name
Test status
Simulation time 336436650000 ps
CPU time 938.83 seconds
Started Jul 07 05:49:16 PM PDT 24
Finished Jul 07 06:29:12 PM PDT 24
Peak memory 160204 kb
Host smart-b84da834-fb85-43af-afb7-e72cd2350795
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3472457476 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.3472457476
Directory /workspace/1.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.1762396735
Short name T102
Test name
Test status
Simulation time 336448410000 ps
CPU time 706.98 seconds
Started Jul 07 04:30:27 PM PDT 24
Finished Jul 07 04:59:08 PM PDT 24
Peak memory 160636 kb
Host smart-cca525e4-7f5f-4913-90dc-884335302e97
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1762396735 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.1762396735
Directory /workspace/0.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.4205840541
Short name T93
Test name
Test status
Simulation time 337089390000 ps
CPU time 1098.15 seconds
Started Jul 07 04:30:16 PM PDT 24
Finished Jul 07 05:15:28 PM PDT 24
Peak memory 160632 kb
Host smart-c37b9494-d096-410d-921c-0752a9c4b160
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4205840541 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.4205840541
Directory /workspace/1.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.932951108
Short name T106
Test name
Test status
Simulation time 336513230000 ps
CPU time 1080.94 seconds
Started Jul 07 04:30:33 PM PDT 24
Finished Jul 07 05:15:41 PM PDT 24
Peak memory 160632 kb
Host smart-b4beaa95-a795-4c11-ac15-29bfcd372690
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=932951108 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.932951108
Directory /workspace/11.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.3934343638
Short name T71
Test name
Test status
Simulation time 337067770000 ps
CPU time 1046.68 seconds
Started Jul 07 04:30:19 PM PDT 24
Finished Jul 07 05:14:00 PM PDT 24
Peak memory 160760 kb
Host smart-e57e0faa-0a7b-43cf-9742-6dced70ff8aa
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3934343638 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.3934343638
Directory /workspace/12.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.64966515
Short name T96
Test name
Test status
Simulation time 337007750000 ps
CPU time 713.88 seconds
Started Jul 07 04:30:25 PM PDT 24
Finished Jul 07 04:59:40 PM PDT 24
Peak memory 160616 kb
Host smart-da39b440-7baa-4dad-a828-ab6595638b35
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=64966515 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.64966515
Directory /workspace/13.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.3415911988
Short name T14
Test name
Test status
Simulation time 336789930000 ps
CPU time 672.59 seconds
Started Jul 07 04:31:09 PM PDT 24
Finished Jul 07 04:58:32 PM PDT 24
Peak memory 159768 kb
Host smart-ce1daf70-5943-45c8-9d23-99bea430c5a2
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3415911988 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.3415911988
Directory /workspace/14.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.1496538190
Short name T79
Test name
Test status
Simulation time 336441410000 ps
CPU time 760.49 seconds
Started Jul 07 04:30:24 PM PDT 24
Finished Jul 07 05:01:34 PM PDT 24
Peak memory 160760 kb
Host smart-6d2fadf8-dfa9-4174-b291-cfb5e5c09dbb
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1496538190 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.1496538190
Directory /workspace/15.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.2077326498
Short name T99
Test name
Test status
Simulation time 336416510000 ps
CPU time 714.19 seconds
Started Jul 07 04:30:23 PM PDT 24
Finished Jul 07 04:59:41 PM PDT 24
Peak memory 160644 kb
Host smart-052436f7-583f-4d83-8900-8c90ffbfaa98
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2077326498 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.2077326498
Directory /workspace/16.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.4128538783
Short name T78
Test name
Test status
Simulation time 336867250000 ps
CPU time 1047.01 seconds
Started Jul 07 04:30:18 PM PDT 24
Finished Jul 07 05:13:53 PM PDT 24
Peak memory 160760 kb
Host smart-e55a23d5-7fb2-4a96-a351-a39c3e2499e4
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4128538783 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.4128538783
Directory /workspace/17.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.1199033796
Short name T82
Test name
Test status
Simulation time 336943310000 ps
CPU time 745.18 seconds
Started Jul 07 04:30:21 PM PDT 24
Finished Jul 07 05:00:59 PM PDT 24
Peak memory 160644 kb
Host smart-27665d8b-373b-45b3-ab24-5f7adc93c516
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1199033796 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.1199033796
Directory /workspace/18.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.3039177942
Short name T90
Test name
Test status
Simulation time 336789090000 ps
CPU time 801.5 seconds
Started Jul 07 04:30:24 PM PDT 24
Finished Jul 07 05:02:52 PM PDT 24
Peak memory 160968 kb
Host smart-504f03dc-fb45-4934-bbb3-9a630365a3cf
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3039177942 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.3039177942
Directory /workspace/19.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.1400740768
Short name T91
Test name
Test status
Simulation time 336795610000 ps
CPU time 673.55 seconds
Started Jul 07 04:30:20 PM PDT 24
Finished Jul 07 04:57:37 PM PDT 24
Peak memory 160636 kb
Host smart-d34d7754-1435-4ac2-b25f-d3f047b4e470
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1400740768 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.1400740768
Directory /workspace/2.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.1149646497
Short name T72
Test name
Test status
Simulation time 336699630000 ps
CPU time 742.62 seconds
Started Jul 07 04:30:31 PM PDT 24
Finished Jul 07 05:01:06 PM PDT 24
Peak memory 160644 kb
Host smart-376176f9-410f-4c60-971d-0ba1f8e5ee94
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1149646497 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.1149646497
Directory /workspace/20.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.3363217787
Short name T81
Test name
Test status
Simulation time 336980290000 ps
CPU time 1047.78 seconds
Started Jul 07 04:30:16 PM PDT 24
Finished Jul 07 05:13:43 PM PDT 24
Peak memory 160760 kb
Host smart-bac4c766-617c-4e36-b350-81944b46bf59
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3363217787 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.3363217787
Directory /workspace/21.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.205941256
Short name T80
Test name
Test status
Simulation time 337101390000 ps
CPU time 932.94 seconds
Started Jul 07 04:30:39 PM PDT 24
Finished Jul 07 05:09:36 PM PDT 24
Peak memory 160608 kb
Host smart-a78a735e-15a1-4e3c-97d8-a05b2a2c91d4
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=205941256 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.205941256
Directory /workspace/22.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.3111473724
Short name T97
Test name
Test status
Simulation time 336737330000 ps
CPU time 1085.77 seconds
Started Jul 07 04:30:27 PM PDT 24
Finished Jul 07 05:14:50 PM PDT 24
Peak memory 160640 kb
Host smart-66013e74-3856-4cd8-a086-4419cc51f1c5
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3111473724 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.3111473724
Directory /workspace/23.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.2046812531
Short name T86
Test name
Test status
Simulation time 337040870000 ps
CPU time 930.58 seconds
Started Jul 07 04:30:23 PM PDT 24
Finished Jul 07 05:08:40 PM PDT 24
Peak memory 160616 kb
Host smart-6870b9fb-39d9-4d1e-95dc-90176d10e5ee
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2046812531 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.2046812531
Directory /workspace/24.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.4021631768
Short name T16
Test name
Test status
Simulation time 336963710000 ps
CPU time 944.83 seconds
Started Jul 07 04:30:37 PM PDT 24
Finished Jul 07 05:09:37 PM PDT 24
Peak memory 160616 kb
Host smart-430faba1-8dd1-466c-aeba-7c24ce2a319b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4021631768 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.4021631768
Directory /workspace/25.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1303617153
Short name T75
Test name
Test status
Simulation time 336955270000 ps
CPU time 1112.46 seconds
Started Jul 07 04:30:18 PM PDT 24
Finished Jul 07 05:16:14 PM PDT 24
Peak memory 160640 kb
Host smart-29632a44-c3b5-4b99-adaf-559655ba435f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1303617153 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.1303617153
Directory /workspace/26.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.2160722750
Short name T19
Test name
Test status
Simulation time 336445650000 ps
CPU time 714.24 seconds
Started Jul 07 04:30:23 PM PDT 24
Finished Jul 07 05:00:07 PM PDT 24
Peak memory 160656 kb
Host smart-1c08c4d0-71ca-4d48-81d2-51763f80e2d3
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2160722750 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.2160722750
Directory /workspace/27.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.276700543
Short name T100
Test name
Test status
Simulation time 336947090000 ps
CPU time 1093.64 seconds
Started Jul 07 04:30:16 PM PDT 24
Finished Jul 07 05:15:52 PM PDT 24
Peak memory 160632 kb
Host smart-a8823a56-763d-4fe7-bd69-d86f2952c5bf
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=276700543 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.276700543
Directory /workspace/28.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.4235758119
Short name T73
Test name
Test status
Simulation time 336899890000 ps
CPU time 1074.75 seconds
Started Jul 07 04:30:28 PM PDT 24
Finished Jul 07 05:14:23 PM PDT 24
Peak memory 160640 kb
Host smart-af6b5d68-4809-4c74-8404-b2901f9d3523
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4235758119 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.4235758119
Directory /workspace/29.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.1899143442
Short name T103
Test name
Test status
Simulation time 337105570000 ps
CPU time 807.05 seconds
Started Jul 07 04:30:15 PM PDT 24
Finished Jul 07 05:03:18 PM PDT 24
Peak memory 160636 kb
Host smart-0176bec4-a575-4bf8-bd87-358837ea20cc
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1899143442 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.1899143442
Directory /workspace/3.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.305388364
Short name T76
Test name
Test status
Simulation time 336905810000 ps
CPU time 704.49 seconds
Started Jul 07 04:30:22 PM PDT 24
Finished Jul 07 04:59:06 PM PDT 24
Peak memory 160592 kb
Host smart-375045a4-dbe1-4491-a277-7da7a4437d31
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=305388364 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.305388364
Directory /workspace/30.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.2521045152
Short name T98
Test name
Test status
Simulation time 337100030000 ps
CPU time 1034.6 seconds
Started Jul 07 04:30:28 PM PDT 24
Finished Jul 07 05:12:43 PM PDT 24
Peak memory 160640 kb
Host smart-ac84e1e0-2384-4c7c-84cf-340452feccb5
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2521045152 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.2521045152
Directory /workspace/31.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.2009554978
Short name T74
Test name
Test status
Simulation time 336389370000 ps
CPU time 1027.09 seconds
Started Jul 07 04:30:27 PM PDT 24
Finished Jul 07 05:12:39 PM PDT 24
Peak memory 160640 kb
Host smart-939ad5f1-a0d1-4c19-8326-2e59b0a82e0e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2009554978 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.2009554978
Directory /workspace/32.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.1760669363
Short name T94
Test name
Test status
Simulation time 336413470000 ps
CPU time 880.7 seconds
Started Jul 07 04:30:27 PM PDT 24
Finished Jul 07 05:07:36 PM PDT 24
Peak memory 160616 kb
Host smart-3ff31e61-179f-4b72-aea8-0d41a2b4d6cb
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1760669363 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.1760669363
Directory /workspace/33.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.4221511720
Short name T87
Test name
Test status
Simulation time 336970530000 ps
CPU time 1055.97 seconds
Started Jul 07 04:30:16 PM PDT 24
Finished Jul 07 05:14:29 PM PDT 24
Peak memory 160640 kb
Host smart-2fdf98e2-8d44-4ea1-94da-561a415298f1
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4221511720 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.4221511720
Directory /workspace/34.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.2729442592
Short name T77
Test name
Test status
Simulation time 337075510000 ps
CPU time 692.8 seconds
Started Jul 07 04:30:21 PM PDT 24
Finished Jul 07 04:58:53 PM PDT 24
Peak memory 160636 kb
Host smart-40b99f39-9baf-45b2-8764-1183427b6516
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2729442592 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.2729442592
Directory /workspace/35.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.1664636703
Short name T105
Test name
Test status
Simulation time 336315010000 ps
CPU time 1040.8 seconds
Started Jul 07 04:30:17 PM PDT 24
Finished Jul 07 05:13:44 PM PDT 24
Peak memory 160760 kb
Host smart-3e44d669-d481-4df3-ada2-7817020f7071
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1664636703 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.1664636703
Directory /workspace/36.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.2002173272
Short name T110
Test name
Test status
Simulation time 336912530000 ps
CPU time 1039.8 seconds
Started Jul 07 04:30:17 PM PDT 24
Finished Jul 07 05:13:40 PM PDT 24
Peak memory 160760 kb
Host smart-64e7c4df-107c-484b-8943-5aae12b55bc6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2002173272 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.2002173272
Directory /workspace/37.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.1462080163
Short name T6
Test name
Test status
Simulation time 337041310000 ps
CPU time 1041.18 seconds
Started Jul 07 04:30:18 PM PDT 24
Finished Jul 07 05:13:53 PM PDT 24
Peak memory 160760 kb
Host smart-9a513dd0-e858-484b-a7a0-507f777f0da9
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1462080163 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.1462080163
Directory /workspace/38.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.3273960656
Short name T20
Test name
Test status
Simulation time 336768870000 ps
CPU time 1067.5 seconds
Started Jul 07 04:30:28 PM PDT 24
Finished Jul 07 05:14:09 PM PDT 24
Peak memory 160640 kb
Host smart-fb0678e4-b50f-45be-a2c8-efa9f5b2cc23
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3273960656 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.3273960656
Directory /workspace/39.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.1873376922
Short name T85
Test name
Test status
Simulation time 336457750000 ps
CPU time 938.86 seconds
Started Jul 07 04:30:34 PM PDT 24
Finished Jul 07 05:09:17 PM PDT 24
Peak memory 160608 kb
Host smart-5338873a-dd88-4da5-95ae-25b541a4cb80
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1873376922 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.1873376922
Directory /workspace/4.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.3572996563
Short name T84
Test name
Test status
Simulation time 336830670000 ps
CPU time 822.67 seconds
Started Jul 07 04:30:47 PM PDT 24
Finished Jul 07 05:04:04 PM PDT 24
Peak memory 160640 kb
Host smart-f5b3f4a5-2aa9-4ba4-913f-05c4c9d03b75
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3572996563 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.3572996563
Directory /workspace/40.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.1877225029
Short name T101
Test name
Test status
Simulation time 336572690000 ps
CPU time 827.27 seconds
Started Jul 07 04:30:25 PM PDT 24
Finished Jul 07 05:03:48 PM PDT 24
Peak memory 160960 kb
Host smart-133b8d03-259b-4541-ba6c-0ca116c7e4cb
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1877225029 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.1877225029
Directory /workspace/41.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.141197629
Short name T95
Test name
Test status
Simulation time 336407510000 ps
CPU time 633.88 seconds
Started Jul 07 04:30:29 PM PDT 24
Finished Jul 07 04:57:01 PM PDT 24
Peak memory 160552 kb
Host smart-b2208a11-7457-4207-9bf6-a7dc3d421fc4
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=141197629 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.141197629
Directory /workspace/42.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.409206176
Short name T88
Test name
Test status
Simulation time 336477810000 ps
CPU time 711.49 seconds
Started Jul 07 04:30:17 PM PDT 24
Finished Jul 07 04:59:41 PM PDT 24
Peak memory 160632 kb
Host smart-97bd2b55-823b-49c4-8e3d-0e18f411556c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=409206176 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.409206176
Directory /workspace/43.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.2867247338
Short name T104
Test name
Test status
Simulation time 336763610000 ps
CPU time 719.16 seconds
Started Jul 07 04:30:25 PM PDT 24
Finished Jul 07 04:59:23 PM PDT 24
Peak memory 160696 kb
Host smart-fc4bb405-51aa-4d45-90c9-28b225d7526d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2867247338 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.2867247338
Directory /workspace/44.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.2889882979
Short name T83
Test name
Test status
Simulation time 336972750000 ps
CPU time 1089.18 seconds
Started Jul 07 04:30:44 PM PDT 24
Finished Jul 07 05:15:05 PM PDT 24
Peak memory 160640 kb
Host smart-1a4cd234-9e72-4cab-892c-cdccbb1ea811
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2889882979 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.2889882979
Directory /workspace/45.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.3470343698
Short name T109
Test name
Test status
Simulation time 336924510000 ps
CPU time 746.95 seconds
Started Jul 07 04:30:21 PM PDT 24
Finished Jul 07 05:00:34 PM PDT 24
Peak memory 160644 kb
Host smart-251f2af2-cf36-451c-a8bf-a43bc020a7b2
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3470343698 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.3470343698
Directory /workspace/46.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.3098605465
Short name T4
Test name
Test status
Simulation time 336668750000 ps
CPU time 811.46 seconds
Started Jul 07 04:30:15 PM PDT 24
Finished Jul 07 05:03:14 PM PDT 24
Peak memory 160644 kb
Host smart-edafb230-e7cb-423f-a574-6b1fd18cbbc6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3098605465 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.3098605465
Directory /workspace/47.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.1126922668
Short name T107
Test name
Test status
Simulation time 336938890000 ps
CPU time 689.41 seconds
Started Jul 07 04:30:21 PM PDT 24
Finished Jul 07 04:58:48 PM PDT 24
Peak memory 160640 kb
Host smart-52aa1ea2-a9b6-444e-a754-80659042b44a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1126922668 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.1126922668
Directory /workspace/48.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.4071887040
Short name T15
Test name
Test status
Simulation time 337096230000 ps
CPU time 700.14 seconds
Started Jul 07 04:30:27 PM PDT 24
Finished Jul 07 04:59:45 PM PDT 24
Peak memory 160656 kb
Host smart-4ae737d9-5056-4045-90ef-e82743664a7b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4071887040 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.4071887040
Directory /workspace/49.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.2157459770
Short name T92
Test name
Test status
Simulation time 336862910000 ps
CPU time 845.4 seconds
Started Jul 07 04:30:56 PM PDT 24
Finished Jul 07 05:05:07 PM PDT 24
Peak memory 160632 kb
Host smart-934b2887-037a-46a3-afd9-ccb8fe6727c2
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2157459770 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.2157459770
Directory /workspace/5.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.2225502744
Short name T108
Test name
Test status
Simulation time 336498010000 ps
CPU time 719.36 seconds
Started Jul 07 04:31:50 PM PDT 24
Finished Jul 07 05:01:30 PM PDT 24
Peak memory 160256 kb
Host smart-5005c90f-7ca4-4724-9707-013f38219790
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2225502744 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.2225502744
Directory /workspace/6.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.1837629995
Short name T17
Test name
Test status
Simulation time 336362990000 ps
CPU time 842.12 seconds
Started Jul 07 04:30:20 PM PDT 24
Finished Jul 07 05:04:15 PM PDT 24
Peak memory 160632 kb
Host smart-66261517-1bf7-407c-8ece-48995ed4dc96
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1837629995 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.1837629995
Directory /workspace/7.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.322880545
Short name T5
Test name
Test status
Simulation time 336793750000 ps
CPU time 782.57 seconds
Started Jul 07 04:30:35 PM PDT 24
Finished Jul 07 05:02:15 PM PDT 24
Peak memory 160592 kb
Host smart-6e3d5cb5-a217-4c97-bdcc-4e37e3390642
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=322880545 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.322880545
Directory /workspace/8.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.2299899950
Short name T89
Test name
Test status
Simulation time 336395390000 ps
CPU time 1067.71 seconds
Started Jul 07 04:30:16 PM PDT 24
Finished Jul 07 05:14:50 PM PDT 24
Peak memory 160632 kb
Host smart-ce7ac2f1-7391-47ad-a8ca-cf644f06739b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2299899950 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.2299899950
Directory /workspace/9.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.851358805
Short name T195
Test name
Test status
Simulation time 336951010000 ps
CPU time 630.87 seconds
Started Jul 07 05:49:11 PM PDT 24
Finished Jul 07 06:15:11 PM PDT 24
Peak memory 160804 kb
Host smart-34513e50-15a4-4bda-983b-f45ea8c05624
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=851358805 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.851358805
Directory /workspace/0.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.2414950828
Short name T172
Test name
Test status
Simulation time 336529930000 ps
CPU time 777.89 seconds
Started Jul 07 05:49:13 PM PDT 24
Finished Jul 07 06:20:55 PM PDT 24
Peak memory 160804 kb
Host smart-2a14c022-9feb-46fb-9ea7-dc4d2bfc2dd4
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2414950828 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.2414950828
Directory /workspace/10.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.2897076336
Short name T21
Test name
Test status
Simulation time 336976630000 ps
CPU time 822.47 seconds
Started Jul 07 05:49:13 PM PDT 24
Finished Jul 07 06:22:20 PM PDT 24
Peak memory 160796 kb
Host smart-078e9a53-0d66-477b-879b-3016bc8ff821
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2897076336 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.2897076336
Directory /workspace/11.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.1578348735
Short name T186
Test name
Test status
Simulation time 336652950000 ps
CPU time 789.55 seconds
Started Jul 07 05:49:17 PM PDT 24
Finished Jul 07 06:21:42 PM PDT 24
Peak memory 160820 kb
Host smart-1331a101-96c3-49b2-b314-2c1218bce605
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1578348735 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.1578348735
Directory /workspace/12.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.3103562921
Short name T182
Test name
Test status
Simulation time 336411630000 ps
CPU time 845.07 seconds
Started Jul 07 05:49:14 PM PDT 24
Finished Jul 07 06:23:26 PM PDT 24
Peak memory 160820 kb
Host smart-e62f48f8-f61e-4323-90a3-6baa010429e4
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3103562921 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.3103562921
Directory /workspace/13.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.2781978556
Short name T163
Test name
Test status
Simulation time 337036410000 ps
CPU time 802.14 seconds
Started Jul 07 05:49:16 PM PDT 24
Finished Jul 07 06:22:20 PM PDT 24
Peak memory 160816 kb
Host smart-f50ced3d-2817-4917-b80e-4a4a4e036b07
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2781978556 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.2781978556
Directory /workspace/14.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.2276335089
Short name T193
Test name
Test status
Simulation time 336679730000 ps
CPU time 796.16 seconds
Started Jul 07 05:49:14 PM PDT 24
Finished Jul 07 06:21:14 PM PDT 24
Peak memory 160788 kb
Host smart-9c4ce229-5a1b-42f6-adcf-c194224a0680
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2276335089 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.2276335089
Directory /workspace/15.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.972063361
Short name T169
Test name
Test status
Simulation time 336451690000 ps
CPU time 747.16 seconds
Started Jul 07 05:49:12 PM PDT 24
Finished Jul 07 06:19:46 PM PDT 24
Peak memory 160816 kb
Host smart-6f949bfd-c504-465f-92fa-348218d2fa04
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=972063361 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.972063361
Directory /workspace/16.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.4012566252
Short name T171
Test name
Test status
Simulation time 336401050000 ps
CPU time 851.37 seconds
Started Jul 07 05:49:18 PM PDT 24
Finished Jul 07 06:24:40 PM PDT 24
Peak memory 160804 kb
Host smart-63b19060-e532-48e3-9c4e-825bdab04821
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4012566252 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.4012566252
Directory /workspace/17.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.784285592
Short name T170
Test name
Test status
Simulation time 336374610000 ps
CPU time 839.85 seconds
Started Jul 07 05:49:18 PM PDT 24
Finished Jul 07 06:22:50 PM PDT 24
Peak memory 160808 kb
Host smart-3a98c0e3-c3e6-4712-9b8c-05176438dae4
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=784285592 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.784285592
Directory /workspace/18.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.3501091218
Short name T189
Test name
Test status
Simulation time 336375350000 ps
CPU time 1043.52 seconds
Started Jul 07 05:49:24 PM PDT 24
Finished Jul 07 06:33:52 PM PDT 24
Peak memory 160840 kb
Host smart-813d61f8-4938-4c8e-9790-8f1f72cf48e6
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3501091218 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.3501091218
Directory /workspace/19.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.1094463610
Short name T181
Test name
Test status
Simulation time 336929450000 ps
CPU time 933.96 seconds
Started Jul 07 05:49:16 PM PDT 24
Finished Jul 07 06:29:00 PM PDT 24
Peak memory 160300 kb
Host smart-c0f97c77-95b3-4aa9-9889-fb85600c16bc
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1094463610 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.1094463610
Directory /workspace/2.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.999593937
Short name T23
Test name
Test status
Simulation time 336719970000 ps
CPU time 853.56 seconds
Started Jul 07 05:49:18 PM PDT 24
Finished Jul 07 06:23:54 PM PDT 24
Peak memory 160836 kb
Host smart-633755d4-c708-43e2-921d-d9914e380a23
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=999593937 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.999593937
Directory /workspace/20.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3272607813
Short name T198
Test name
Test status
Simulation time 336782290000 ps
CPU time 1055.26 seconds
Started Jul 07 05:49:24 PM PDT 24
Finished Jul 07 06:33:47 PM PDT 24
Peak memory 160624 kb
Host smart-20d86c50-7a43-4771-bbcb-bf368ace3581
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3272607813 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.3272607813
Directory /workspace/21.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.811485946
Short name T161
Test name
Test status
Simulation time 337126070000 ps
CPU time 795.72 seconds
Started Jul 07 05:49:25 PM PDT 24
Finished Jul 07 06:22:31 PM PDT 24
Peak memory 160792 kb
Host smart-8c579c0b-7d57-4ecd-a10c-e635196c9eb2
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=811485946 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.811485946
Directory /workspace/22.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.1620668822
Short name T173
Test name
Test status
Simulation time 336737010000 ps
CPU time 854.47 seconds
Started Jul 07 05:49:18 PM PDT 24
Finished Jul 07 06:24:12 PM PDT 24
Peak memory 160840 kb
Host smart-bef609db-0c4c-4b7d-a696-941b398b99de
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1620668822 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.1620668822
Directory /workspace/23.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.2435526178
Short name T199
Test name
Test status
Simulation time 336579990000 ps
CPU time 780.56 seconds
Started Jul 07 05:49:21 PM PDT 24
Finished Jul 07 06:20:31 PM PDT 24
Peak memory 160808 kb
Host smart-bbc60670-17de-4b90-8f78-cc887c646085
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2435526178 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.2435526178
Directory /workspace/24.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.1270199370
Short name T190
Test name
Test status
Simulation time 336893470000 ps
CPU time 778.13 seconds
Started Jul 07 05:49:23 PM PDT 24
Finished Jul 07 06:21:35 PM PDT 24
Peak memory 160812 kb
Host smart-dce55cb3-86a2-4630-a1cd-49f6332c5e71
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1270199370 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.1270199370
Directory /workspace/25.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.2213164893
Short name T180
Test name
Test status
Simulation time 336623570000 ps
CPU time 938.15 seconds
Started Jul 07 05:49:22 PM PDT 24
Finished Jul 07 06:29:19 PM PDT 24
Peak memory 160824 kb
Host smart-bbf09511-3755-480f-9853-ed4494303287
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2213164893 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.2213164893
Directory /workspace/26.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.2273867943
Short name T29
Test name
Test status
Simulation time 336618090000 ps
CPU time 846 seconds
Started Jul 07 05:49:18 PM PDT 24
Finished Jul 07 06:24:00 PM PDT 24
Peak memory 160808 kb
Host smart-119fe249-3346-4ba7-9013-2ae7b4694dfa
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2273867943 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.2273867943
Directory /workspace/27.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.701514574
Short name T178
Test name
Test status
Simulation time 336645830000 ps
CPU time 707.7 seconds
Started Jul 07 05:49:17 PM PDT 24
Finished Jul 07 06:17:56 PM PDT 24
Peak memory 160816 kb
Host smart-47bfeb50-caa5-49d3-8a48-a5d301bb1bc4
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=701514574 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.701514574
Directory /workspace/28.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.2370717411
Short name T30
Test name
Test status
Simulation time 336447650000 ps
CPU time 761.65 seconds
Started Jul 07 05:49:18 PM PDT 24
Finished Jul 07 06:20:20 PM PDT 24
Peak memory 160808 kb
Host smart-e7739c46-1d2e-428d-a36f-787a61b61958
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2370717411 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.2370717411
Directory /workspace/29.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.1967406666
Short name T194
Test name
Test status
Simulation time 336487470000 ps
CPU time 702.3 seconds
Started Jul 07 05:49:16 PM PDT 24
Finished Jul 07 06:18:02 PM PDT 24
Peak memory 160800 kb
Host smart-a75b286f-8d3c-40bf-8f66-6d1611c297cc
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1967406666 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.1967406666
Directory /workspace/3.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.79205679
Short name T164
Test name
Test status
Simulation time 337041890000 ps
CPU time 1048.86 seconds
Started Jul 07 05:49:24 PM PDT 24
Finished Jul 07 06:33:58 PM PDT 24
Peak memory 160704 kb
Host smart-8658de91-06db-4160-9fd3-161110b05c37
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=79205679 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.79205679
Directory /workspace/30.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.4225461891
Short name T174
Test name
Test status
Simulation time 336839050000 ps
CPU time 815.2 seconds
Started Jul 07 05:49:20 PM PDT 24
Finished Jul 07 06:22:57 PM PDT 24
Peak memory 160816 kb
Host smart-559ac279-4111-451c-a240-cbac4cead38b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4225461891 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.4225461891
Directory /workspace/31.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.744404152
Short name T184
Test name
Test status
Simulation time 336350430000 ps
CPU time 868.94 seconds
Started Jul 07 05:49:20 PM PDT 24
Finished Jul 07 06:24:28 PM PDT 24
Peak memory 160804 kb
Host smart-91e104b7-3075-487e-887d-f471351f327e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=744404152 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.744404152
Directory /workspace/32.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.3309711382
Short name T162
Test name
Test status
Simulation time 336927650000 ps
CPU time 846.8 seconds
Started Jul 07 05:49:20 PM PDT 24
Finished Jul 07 06:23:34 PM PDT 24
Peak memory 160840 kb
Host smart-d14f141c-c56b-4f02-bd75-1b520d90d467
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3309711382 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.3309711382
Directory /workspace/33.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.1780456290
Short name T188
Test name
Test status
Simulation time 336775570000 ps
CPU time 702.57 seconds
Started Jul 07 05:49:18 PM PDT 24
Finished Jul 07 06:18:01 PM PDT 24
Peak memory 160828 kb
Host smart-791148f7-6eb3-4549-a8d6-4a92a4056aee
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1780456290 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.1780456290
Directory /workspace/34.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.3210725695
Short name T26
Test name
Test status
Simulation time 337065650000 ps
CPU time 797.11 seconds
Started Jul 07 05:49:25 PM PDT 24
Finished Jul 07 06:22:30 PM PDT 24
Peak memory 160800 kb
Host smart-b8cee3dd-16d4-4161-be7f-7bcdb94440f0
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3210725695 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.3210725695
Directory /workspace/35.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.3031909691
Short name T22
Test name
Test status
Simulation time 336343750000 ps
CPU time 732.35 seconds
Started Jul 07 05:49:19 PM PDT 24
Finished Jul 07 06:18:54 PM PDT 24
Peak memory 160824 kb
Host smart-cb8c0ca9-5327-439c-a115-c3a211c192d2
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3031909691 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.3031909691
Directory /workspace/36.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.982727236
Short name T175
Test name
Test status
Simulation time 336500730000 ps
CPU time 786.59 seconds
Started Jul 07 05:49:23 PM PDT 24
Finished Jul 07 06:21:41 PM PDT 24
Peak memory 160804 kb
Host smart-ed2c804b-2cac-48de-acbd-e07e7e456578
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=982727236 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.982727236
Directory /workspace/37.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.1633965914
Short name T179
Test name
Test status
Simulation time 337133510000 ps
CPU time 1051.36 seconds
Started Jul 07 05:49:24 PM PDT 24
Finished Jul 07 06:34:00 PM PDT 24
Peak memory 160840 kb
Host smart-dd5a010c-39fb-4755-b06d-72caeda2e1f5
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1633965914 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.1633965914
Directory /workspace/38.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.2377887976
Short name T183
Test name
Test status
Simulation time 337066250000 ps
CPU time 779.73 seconds
Started Jul 07 05:49:18 PM PDT 24
Finished Jul 07 06:20:47 PM PDT 24
Peak memory 160816 kb
Host smart-04a5203f-89d7-4320-956b-b3d687d5fd96
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2377887976 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.2377887976
Directory /workspace/39.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.2381225282
Short name T176
Test name
Test status
Simulation time 336551690000 ps
CPU time 841.4 seconds
Started Jul 07 05:49:14 PM PDT 24
Finished Jul 07 06:23:23 PM PDT 24
Peak memory 160812 kb
Host smart-d908409d-a549-469a-becf-fa1b5885107f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2381225282 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.2381225282
Directory /workspace/4.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.3086697401
Short name T166
Test name
Test status
Simulation time 336659730000 ps
CPU time 836.01 seconds
Started Jul 07 05:49:22 PM PDT 24
Finished Jul 07 06:24:19 PM PDT 24
Peak memory 160788 kb
Host smart-f82c2b60-a9f7-4b80-9594-57c69c8c6ae3
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3086697401 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.3086697401
Directory /workspace/40.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.2353586722
Short name T187
Test name
Test status
Simulation time 336513690000 ps
CPU time 903.07 seconds
Started Jul 07 05:49:18 PM PDT 24
Finished Jul 07 06:26:17 PM PDT 24
Peak memory 160804 kb
Host smart-7f63d4cc-a72a-43a6-b69f-499246455c75
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2353586722 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.2353586722
Directory /workspace/41.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.2368129626
Short name T192
Test name
Test status
Simulation time 336861850000 ps
CPU time 800.75 seconds
Started Jul 07 05:49:25 PM PDT 24
Finished Jul 07 06:22:40 PM PDT 24
Peak memory 160800 kb
Host smart-81bf1d5a-5cff-4724-a976-39942d395b03
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2368129626 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.2368129626
Directory /workspace/42.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.3773240743
Short name T177
Test name
Test status
Simulation time 336384370000 ps
CPU time 878.45 seconds
Started Jul 07 05:49:18 PM PDT 24
Finished Jul 07 06:25:11 PM PDT 24
Peak memory 160972 kb
Host smart-a2112821-6754-4085-999e-fd48c6847b33
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3773240743 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.3773240743
Directory /workspace/43.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.2561022428
Short name T196
Test name
Test status
Simulation time 336859670000 ps
CPU time 887.56 seconds
Started Jul 07 05:49:18 PM PDT 24
Finished Jul 07 06:25:33 PM PDT 24
Peak memory 160972 kb
Host smart-db8f703b-1ffd-44a3-a206-b4cf4761e148
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2561022428 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.2561022428
Directory /workspace/44.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.3664990341
Short name T168
Test name
Test status
Simulation time 336821050000 ps
CPU time 856.79 seconds
Started Jul 07 05:49:18 PM PDT 24
Finished Jul 07 06:23:47 PM PDT 24
Peak memory 160824 kb
Host smart-f3bf86e3-a0e2-4b88-b2b6-9ce490f07658
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3664990341 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.3664990341
Directory /workspace/45.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.2229210775
Short name T197
Test name
Test status
Simulation time 336720830000 ps
CPU time 783.17 seconds
Started Jul 07 05:49:16 PM PDT 24
Finished Jul 07 06:21:19 PM PDT 24
Peak memory 160796 kb
Host smart-67dedcec-9e40-4e28-aed8-ec83ea620b82
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2229210775 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.2229210775
Directory /workspace/46.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.842628534
Short name T165
Test name
Test status
Simulation time 336601850000 ps
CPU time 1036.14 seconds
Started Jul 07 05:49:24 PM PDT 24
Finished Jul 07 06:33:50 PM PDT 24
Peak memory 160832 kb
Host smart-1ff42b34-f323-4176-af75-dc036af8d44d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=842628534 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.842628534
Directory /workspace/47.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1674165300
Short name T200
Test name
Test status
Simulation time 336620230000 ps
CPU time 836.2 seconds
Started Jul 07 05:49:23 PM PDT 24
Finished Jul 07 06:24:02 PM PDT 24
Peak memory 160788 kb
Host smart-7cfbe881-438c-4c78-bde3-53ec7c7c7964
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1674165300 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.1674165300
Directory /workspace/48.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.3359129665
Short name T185
Test name
Test status
Simulation time 336544710000 ps
CPU time 625.15 seconds
Started Jul 07 05:49:22 PM PDT 24
Finished Jul 07 06:15:19 PM PDT 24
Peak memory 160812 kb
Host smart-f8a31a45-51d8-4112-8853-dbc8f5ecdd65
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3359129665 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.3359129665
Directory /workspace/49.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.1307585097
Short name T25
Test name
Test status
Simulation time 336460970000 ps
CPU time 646.87 seconds
Started Jul 07 05:49:16 PM PDT 24
Finished Jul 07 06:16:02 PM PDT 24
Peak memory 160752 kb
Host smart-0d30408b-fae4-4838-97d6-21de8c5fc226
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1307585097 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.1307585097
Directory /workspace/5.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.1666711606
Short name T24
Test name
Test status
Simulation time 336787050000 ps
CPU time 869.6 seconds
Started Jul 07 05:49:16 PM PDT 24
Finished Jul 07 06:24:34 PM PDT 24
Peak memory 160812 kb
Host smart-4deef3e6-2170-4c57-8692-5dc165bc0cab
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1666711606 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.1666711606
Directory /workspace/6.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.3476637109
Short name T28
Test name
Test status
Simulation time 336494410000 ps
CPU time 739.5 seconds
Started Jul 07 05:49:14 PM PDT 24
Finished Jul 07 06:19:07 PM PDT 24
Peak memory 160792 kb
Host smart-a53873a2-7510-43dc-a5a0-2c5ddbe5ea42
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3476637109 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.3476637109
Directory /workspace/7.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.169200519
Short name T167
Test name
Test status
Simulation time 336861630000 ps
CPU time 754.3 seconds
Started Jul 07 05:49:16 PM PDT 24
Finished Jul 07 06:20:17 PM PDT 24
Peak memory 160728 kb
Host smart-c4e6d7d1-4368-452f-bcaf-2253b606012d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=169200519 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.169200519
Directory /workspace/8.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.3113212259
Short name T191
Test name
Test status
Simulation time 337142830000 ps
CPU time 813.21 seconds
Started Jul 07 05:49:13 PM PDT 24
Finished Jul 07 06:22:03 PM PDT 24
Peak memory 160816 kb
Host smart-bb6e69fb-5b8d-4cc9-9b2d-f4495ecb73d8
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3113212259 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.3113212259
Directory /workspace/9.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.2786122399
Short name T141
Test name
Test status
Simulation time 1487370000 ps
CPU time 4.57 seconds
Started Jul 07 04:37:46 PM PDT 24
Finished Jul 07 04:37:56 PM PDT 24
Peak memory 164744 kb
Host smart-b477ec7e-4258-4841-8906-5f71f669dd1b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2786122399 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.2786122399
Directory /workspace/0.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.1040040865
Short name T124
Test name
Test status
Simulation time 1515890000 ps
CPU time 4.1 seconds
Started Jul 07 04:37:55 PM PDT 24
Finished Jul 07 04:38:04 PM PDT 24
Peak memory 165088 kb
Host smart-d173bc6e-5d67-40c9-9a20-1f6a56d0c19e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1040040865 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.1040040865
Directory /workspace/1.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.2449520301
Short name T159
Test name
Test status
Simulation time 1556850000 ps
CPU time 4.86 seconds
Started Jul 07 04:37:57 PM PDT 24
Finished Jul 07 04:38:08 PM PDT 24
Peak memory 164756 kb
Host smart-a7ffd9f3-7be0-4765-b1dc-7983c0773779
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2449520301 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.2449520301
Directory /workspace/10.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.67678832
Short name T153
Test name
Test status
Simulation time 1143050000 ps
CPU time 4.02 seconds
Started Jul 07 04:37:59 PM PDT 24
Finished Jul 07 04:38:08 PM PDT 24
Peak memory 164616 kb
Host smart-62cd0273-fe52-465a-90cb-343556e3f3a7
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=67678832 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.67678832
Directory /workspace/11.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.1046535693
Short name T144
Test name
Test status
Simulation time 1455310000 ps
CPU time 4.78 seconds
Started Jul 07 04:38:02 PM PDT 24
Finished Jul 07 04:38:13 PM PDT 24
Peak memory 164396 kb
Host smart-365581eb-967f-4380-b33d-c7bdfc33378d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1046535693 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.1046535693
Directory /workspace/12.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.1194187979
Short name T120
Test name
Test status
Simulation time 1393090000 ps
CPU time 5.17 seconds
Started Jul 07 04:38:00 PM PDT 24
Finished Jul 07 04:38:12 PM PDT 24
Peak memory 164848 kb
Host smart-6c0035a4-9b51-4a26-b468-e728c1468908
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1194187979 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.1194187979
Directory /workspace/13.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.4255655469
Short name T126
Test name
Test status
Simulation time 1492730000 ps
CPU time 5.11 seconds
Started Jul 07 04:37:55 PM PDT 24
Finished Jul 07 04:38:07 PM PDT 24
Peak memory 164708 kb
Host smart-e5f0ea48-7a17-49a5-bbb2-6aa88c1f6554
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4255655469 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.4255655469
Directory /workspace/14.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.1494385797
Short name T113
Test name
Test status
Simulation time 1567590000 ps
CPU time 5.04 seconds
Started Jul 07 04:38:03 PM PDT 24
Finished Jul 07 04:38:14 PM PDT 24
Peak memory 164352 kb
Host smart-fe8ab9cb-22f2-49ec-b184-fc30d798135a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1494385797 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.1494385797
Directory /workspace/15.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.2302404555
Short name T131
Test name
Test status
Simulation time 1440410000 ps
CPU time 3.67 seconds
Started Jul 07 04:37:45 PM PDT 24
Finished Jul 07 04:37:53 PM PDT 24
Peak memory 164728 kb
Host smart-0ddbd4a0-7966-4072-adb4-d494e4b8c777
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2302404555 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.2302404555
Directory /workspace/16.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.676050509
Short name T146
Test name
Test status
Simulation time 1553610000 ps
CPU time 3.97 seconds
Started Jul 07 04:37:56 PM PDT 24
Finished Jul 07 04:38:04 PM PDT 24
Peak memory 164748 kb
Host smart-4ba12ef0-9573-4025-b224-f8d195b89b48
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=676050509 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.676050509
Directory /workspace/17.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.4200105972
Short name T145
Test name
Test status
Simulation time 1347650000 ps
CPU time 4.76 seconds
Started Jul 07 04:37:43 PM PDT 24
Finished Jul 07 04:37:54 PM PDT 24
Peak memory 164768 kb
Host smart-7949629a-0747-4bb8-94a3-94feebbb95d7
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4200105972 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.4200105972
Directory /workspace/18.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.1021252383
Short name T150
Test name
Test status
Simulation time 1585710000 ps
CPU time 4.69 seconds
Started Jul 07 04:37:54 PM PDT 24
Finished Jul 07 04:38:04 PM PDT 24
Peak memory 164748 kb
Host smart-5cea2116-e68c-447d-80d2-91f80c256d60
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1021252383 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.1021252383
Directory /workspace/19.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.2543875329
Short name T118
Test name
Test status
Simulation time 1510810000 ps
CPU time 5.43 seconds
Started Jul 07 04:37:54 PM PDT 24
Finished Jul 07 04:38:06 PM PDT 24
Peak memory 164708 kb
Host smart-1b054b04-86f6-414b-a481-9c02a0b482e8
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2543875329 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.2543875329
Directory /workspace/2.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.2449905007
Short name T125
Test name
Test status
Simulation time 1547810000 ps
CPU time 6.27 seconds
Started Jul 07 04:37:53 PM PDT 24
Finished Jul 07 04:38:06 PM PDT 24
Peak memory 164764 kb
Host smart-80ce8703-4f24-4697-9346-68874a3b23c7
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2449905007 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.2449905007
Directory /workspace/20.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.31059324
Short name T119
Test name
Test status
Simulation time 1403290000 ps
CPU time 4.87 seconds
Started Jul 07 04:38:02 PM PDT 24
Finished Jul 07 04:38:13 PM PDT 24
Peak memory 164704 kb
Host smart-2ccc90c1-3407-4273-82e1-9da79bdd88bf
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=31059324 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.31059324
Directory /workspace/21.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.1212710421
Short name T123
Test name
Test status
Simulation time 1297110000 ps
CPU time 2.76 seconds
Started Jul 07 04:37:57 PM PDT 24
Finished Jul 07 04:38:03 PM PDT 24
Peak memory 164768 kb
Host smart-b8b25145-8096-4bb6-be21-33b725c5f1e3
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1212710421 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.1212710421
Directory /workspace/22.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.599012356
Short name T158
Test name
Test status
Simulation time 1531030000 ps
CPU time 3.32 seconds
Started Jul 07 04:37:47 PM PDT 24
Finished Jul 07 04:37:54 PM PDT 24
Peak memory 164764 kb
Host smart-cfaeec29-cd9c-4da5-9029-957d9addb366
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=599012356 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.599012356
Directory /workspace/23.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.2296659630
Short name T142
Test name
Test status
Simulation time 1313410000 ps
CPU time 4.48 seconds
Started Jul 07 04:38:00 PM PDT 24
Finished Jul 07 04:38:10 PM PDT 24
Peak memory 164780 kb
Host smart-e7fb6a9f-ebae-4f28-a8da-cf9fa8d7b17a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2296659630 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.2296659630
Directory /workspace/24.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.3646287167
Short name T138
Test name
Test status
Simulation time 1579850000 ps
CPU time 4.54 seconds
Started Jul 07 04:37:58 PM PDT 24
Finished Jul 07 04:38:08 PM PDT 24
Peak memory 164784 kb
Host smart-394564cf-301f-47d4-a941-6ff4a2911fa6
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3646287167 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.3646287167
Directory /workspace/25.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.3159229176
Short name T112
Test name
Test status
Simulation time 1400210000 ps
CPU time 4.16 seconds
Started Jul 07 04:37:50 PM PDT 24
Finished Jul 07 04:38:00 PM PDT 24
Peak memory 164772 kb
Host smart-ed5bbd49-3fc0-4e3c-8b1d-effdfea3b86e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3159229176 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.3159229176
Directory /workspace/26.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.3181477259
Short name T152
Test name
Test status
Simulation time 1564630000 ps
CPU time 5.19 seconds
Started Jul 07 04:37:46 PM PDT 24
Finished Jul 07 04:37:57 PM PDT 24
Peak memory 164800 kb
Host smart-d347dc09-25ce-45a2-b89d-21661dd46a78
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3181477259 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.3181477259
Directory /workspace/27.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.1763347021
Short name T115
Test name
Test status
Simulation time 1489490000 ps
CPU time 4.92 seconds
Started Jul 07 04:37:57 PM PDT 24
Finished Jul 07 04:38:08 PM PDT 24
Peak memory 164784 kb
Host smart-7b8934bf-37e6-4125-9407-cc97401af15f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1763347021 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.1763347021
Directory /workspace/28.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.1204849636
Short name T156
Test name
Test status
Simulation time 1482570000 ps
CPU time 4.89 seconds
Started Jul 07 04:38:00 PM PDT 24
Finished Jul 07 04:38:10 PM PDT 24
Peak memory 164352 kb
Host smart-706bdf54-888b-4bdf-98cd-190bfd718a26
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1204849636 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.1204849636
Directory /workspace/29.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.726985539
Short name T132
Test name
Test status
Simulation time 1333510000 ps
CPU time 2.82 seconds
Started Jul 07 04:37:49 PM PDT 24
Finished Jul 07 04:37:55 PM PDT 24
Peak memory 164704 kb
Host smart-3b97ef44-a4f4-48f7-ae60-814fcb035528
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=726985539 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.726985539
Directory /workspace/3.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.3425655475
Short name T148
Test name
Test status
Simulation time 1361730000 ps
CPU time 3.44 seconds
Started Jul 07 04:37:58 PM PDT 24
Finished Jul 07 04:38:06 PM PDT 24
Peak memory 164772 kb
Host smart-c8513ec2-103d-4f77-bd08-ae4db26f8023
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3425655475 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.3425655475
Directory /workspace/30.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.99178585
Short name T155
Test name
Test status
Simulation time 1595390000 ps
CPU time 4.69 seconds
Started Jul 07 04:38:02 PM PDT 24
Finished Jul 07 04:38:12 PM PDT 24
Peak memory 164704 kb
Host smart-8ebd9b7e-ae33-436d-8578-6a9e4237dbff
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=99178585 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.99178585
Directory /workspace/31.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.381141225
Short name T151
Test name
Test status
Simulation time 1648410000 ps
CPU time 6.06 seconds
Started Jul 07 04:38:00 PM PDT 24
Finished Jul 07 04:38:13 PM PDT 24
Peak memory 164900 kb
Host smart-f54d81d7-e2a7-4e16-8869-532461e0653c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=381141225 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.381141225
Directory /workspace/32.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.1279248565
Short name T137
Test name
Test status
Simulation time 1592630000 ps
CPU time 4.23 seconds
Started Jul 07 04:37:46 PM PDT 24
Finished Jul 07 04:37:56 PM PDT 24
Peak memory 164396 kb
Host smart-c0194b10-35f2-486e-be1e-56ca4129e709
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1279248565 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.1279248565
Directory /workspace/33.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.2349671785
Short name T127
Test name
Test status
Simulation time 1323090000 ps
CPU time 4.06 seconds
Started Jul 07 04:38:03 PM PDT 24
Finished Jul 07 04:38:12 PM PDT 24
Peak memory 164780 kb
Host smart-2edd6ae2-6c1a-484e-8a61-3c23df12be92
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2349671785 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.2349671785
Directory /workspace/34.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.1263950453
Short name T133
Test name
Test status
Simulation time 1520410000 ps
CPU time 4.78 seconds
Started Jul 07 04:38:00 PM PDT 24
Finished Jul 07 04:38:11 PM PDT 24
Peak memory 164352 kb
Host smart-29a0b150-7746-4c4b-8281-dd17d277904b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1263950453 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.1263950453
Directory /workspace/35.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.4215393507
Short name T139
Test name
Test status
Simulation time 1433390000 ps
CPU time 3.23 seconds
Started Jul 07 04:37:53 PM PDT 24
Finished Jul 07 04:38:01 PM PDT 24
Peak memory 164772 kb
Host smart-66834832-5507-4746-bdb6-d9b31a208392
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4215393507 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.4215393507
Directory /workspace/36.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1024225445
Short name T130
Test name
Test status
Simulation time 1003730000 ps
CPU time 3.41 seconds
Started Jul 07 04:37:55 PM PDT 24
Finished Jul 07 04:38:02 PM PDT 24
Peak memory 164768 kb
Host smart-aad65ce7-c357-4217-9c29-2084d1dbd7b3
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1024225445 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.1024225445
Directory /workspace/37.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.3579834740
Short name T157
Test name
Test status
Simulation time 1547630000 ps
CPU time 3.99 seconds
Started Jul 07 04:38:01 PM PDT 24
Finished Jul 07 04:38:10 PM PDT 24
Peak memory 164752 kb
Host smart-5105ef90-790b-4b57-9f48-8d382bba470a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3579834740 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.3579834740
Directory /workspace/38.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.2530909054
Short name T160
Test name
Test status
Simulation time 1476210000 ps
CPU time 4.35 seconds
Started Jul 07 04:37:46 PM PDT 24
Finished Jul 07 04:37:56 PM PDT 24
Peak memory 164720 kb
Host smart-bf6b8fe0-e0c8-40de-9657-d64a121a5de6
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2530909054 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.2530909054
Directory /workspace/39.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.113099952
Short name T149
Test name
Test status
Simulation time 1453290000 ps
CPU time 3.43 seconds
Started Jul 07 04:37:57 PM PDT 24
Finished Jul 07 04:38:05 PM PDT 24
Peak memory 164464 kb
Host smart-0dfc2cdf-ef31-4b20-87ae-83e9a6f9c19d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=113099952 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.113099952
Directory /workspace/4.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.3778172911
Short name T121
Test name
Test status
Simulation time 1490170000 ps
CPU time 4.68 seconds
Started Jul 07 04:37:58 PM PDT 24
Finished Jul 07 04:38:08 PM PDT 24
Peak memory 164352 kb
Host smart-b6d9d1bb-5742-4464-8e3d-29f69d51f06d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3778172911 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.3778172911
Directory /workspace/40.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.178060172
Short name T114
Test name
Test status
Simulation time 1406330000 ps
CPU time 3.36 seconds
Started Jul 07 04:38:19 PM PDT 24
Finished Jul 07 04:38:27 PM PDT 24
Peak memory 164536 kb
Host smart-fd90173f-2b4d-48ec-9fad-9b791a2f8266
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=178060172 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.178060172
Directory /workspace/41.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.1835129593
Short name T116
Test name
Test status
Simulation time 1426750000 ps
CPU time 3.65 seconds
Started Jul 07 04:37:59 PM PDT 24
Finished Jul 07 04:38:08 PM PDT 24
Peak memory 164752 kb
Host smart-5564fd3a-9e11-451f-b503-9e88a4cbf0bd
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1835129593 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.1835129593
Directory /workspace/42.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.3796821773
Short name T154
Test name
Test status
Simulation time 988410000 ps
CPU time 2.85 seconds
Started Jul 07 04:37:42 PM PDT 24
Finished Jul 07 04:37:49 PM PDT 24
Peak memory 164744 kb
Host smart-f122b6a6-e284-404e-9bbc-418649206fdc
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3796821773 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.3796821773
Directory /workspace/43.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.2671374703
Short name T128
Test name
Test status
Simulation time 1527930000 ps
CPU time 4.94 seconds
Started Jul 07 04:37:52 PM PDT 24
Finished Jul 07 04:38:02 PM PDT 24
Peak memory 164772 kb
Host smart-eb9a36ee-1d8a-40cd-ba27-a86e19f594a0
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2671374703 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.2671374703
Directory /workspace/44.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.637184993
Short name T147
Test name
Test status
Simulation time 1456050000 ps
CPU time 5.32 seconds
Started Jul 07 04:38:00 PM PDT 24
Finished Jul 07 04:38:12 PM PDT 24
Peak memory 164900 kb
Host smart-c33d5e16-6025-484d-9c58-55a81cd849c4
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=637184993 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.637184993
Directory /workspace/45.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.1541066471
Short name T136
Test name
Test status
Simulation time 1396270000 ps
CPU time 4.37 seconds
Started Jul 07 04:37:44 PM PDT 24
Finished Jul 07 04:37:53 PM PDT 24
Peak memory 164772 kb
Host smart-188b1d33-5d24-46c9-a1f1-ca157a8dcfc1
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1541066471 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.1541066471
Directory /workspace/46.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.3860733767
Short name T135
Test name
Test status
Simulation time 1415930000 ps
CPU time 4.24 seconds
Started Jul 07 04:37:52 PM PDT 24
Finished Jul 07 04:38:01 PM PDT 24
Peak memory 164768 kb
Host smart-6d30dabb-3dbb-429d-875e-d35a00e6123b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3860733767 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.3860733767
Directory /workspace/47.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.2699849529
Short name T129
Test name
Test status
Simulation time 1514870000 ps
CPU time 5.2 seconds
Started Jul 07 04:37:55 PM PDT 24
Finished Jul 07 04:38:07 PM PDT 24
Peak memory 164848 kb
Host smart-26892eac-5b48-4cb3-b0d0-bd268df5667e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2699849529 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.2699849529
Directory /workspace/48.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.1809769420
Short name T117
Test name
Test status
Simulation time 1489130000 ps
CPU time 3.56 seconds
Started Jul 07 04:38:07 PM PDT 24
Finished Jul 07 04:38:15 PM PDT 24
Peak memory 164752 kb
Host smart-ae16ac8e-4198-4cd2-a56b-17e853f06ddc
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1809769420 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.1809769420
Directory /workspace/49.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.2434363911
Short name T134
Test name
Test status
Simulation time 1528950000 ps
CPU time 4.9 seconds
Started Jul 07 04:38:11 PM PDT 24
Finished Jul 07 04:38:22 PM PDT 24
Peak memory 164768 kb
Host smart-3c1c4cb3-c19a-41b9-bc3f-c720cb0ab0d5
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2434363911 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.2434363911
Directory /workspace/5.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.3601878055
Short name T111
Test name
Test status
Simulation time 1492270000 ps
CPU time 5 seconds
Started Jul 07 04:37:58 PM PDT 24
Finished Jul 07 04:38:09 PM PDT 24
Peak memory 164352 kb
Host smart-d9c1929a-14bd-429f-bf37-6e722aed5afc
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3601878055 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.3601878055
Directory /workspace/6.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.599853928
Short name T140
Test name
Test status
Simulation time 1307570000 ps
CPU time 4.26 seconds
Started Jul 07 04:37:52 PM PDT 24
Finished Jul 07 04:38:02 PM PDT 24
Peak memory 164696 kb
Host smart-17eb7b28-28e4-4f36-a535-6bdacf47491c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=599853928 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.599853928
Directory /workspace/7.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1978457058
Short name T143
Test name
Test status
Simulation time 1496310000 ps
CPU time 4.8 seconds
Started Jul 07 04:37:57 PM PDT 24
Finished Jul 07 04:38:08 PM PDT 24
Peak memory 165620 kb
Host smart-97b39674-aaac-4f01-84f1-e7190d8fa851
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1978457058 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.1978457058
Directory /workspace/8.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.1200133530
Short name T122
Test name
Test status
Simulation time 1463570000 ps
CPU time 5 seconds
Started Jul 07 04:37:57 PM PDT 24
Finished Jul 07 04:38:08 PM PDT 24
Peak memory 164352 kb
Host smart-3002dd62-a0bd-4745-8a18-f45c3a6050da
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1200133530 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.1200133530
Directory /workspace/9.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.2622392612
Short name T44
Test name
Test status
Simulation time 1410470000 ps
CPU time 5.35 seconds
Started Jul 07 04:30:49 PM PDT 24
Finished Jul 07 04:31:02 PM PDT 24
Peak memory 164896 kb
Host smart-bb4d0f3d-e9b5-4dd9-a1c1-0d2895375fd6
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2622392612 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.2622392612
Directory /workspace/0.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.1484151150
Short name T63
Test name
Test status
Simulation time 1539950000 ps
CPU time 3.23 seconds
Started Jul 07 04:30:26 PM PDT 24
Finished Jul 07 04:30:33 PM PDT 24
Peak memory 164752 kb
Host smart-9d7d081c-69fd-43ec-8b8e-87934e470473
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1484151150 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.1484151150
Directory /workspace/1.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.2699097381
Short name T9
Test name
Test status
Simulation time 1464310000 ps
CPU time 3.49 seconds
Started Jul 07 04:30:19 PM PDT 24
Finished Jul 07 04:30:27 PM PDT 24
Peak memory 164764 kb
Host smart-91c2872d-d79e-43d1-920d-25a17648c2ca
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2699097381 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.2699097381
Directory /workspace/11.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.2211208888
Short name T37
Test name
Test status
Simulation time 1498730000 ps
CPU time 3.04 seconds
Started Jul 07 04:30:20 PM PDT 24
Finished Jul 07 04:30:27 PM PDT 24
Peak memory 164756 kb
Host smart-83bae5f8-3786-4b10-a1ae-f19db6ef37d7
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2211208888 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.2211208888
Directory /workspace/12.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.2364565375
Short name T68
Test name
Test status
Simulation time 1427510000 ps
CPU time 2.89 seconds
Started Jul 07 04:30:28 PM PDT 24
Finished Jul 07 04:30:34 PM PDT 24
Peak memory 164756 kb
Host smart-dee32e07-0025-40ab-bf29-b5992c442ae1
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2364565375 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.2364565375
Directory /workspace/13.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.4186524893
Short name T47
Test name
Test status
Simulation time 1434470000 ps
CPU time 3.08 seconds
Started Jul 07 04:30:33 PM PDT 24
Finished Jul 07 04:30:40 PM PDT 24
Peak memory 164744 kb
Host smart-8f1595f5-e8e9-44be-a527-4f38b892aece
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4186524893 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.4186524893
Directory /workspace/14.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.1566240931
Short name T32
Test name
Test status
Simulation time 1608690000 ps
CPU time 3.44 seconds
Started Jul 07 04:30:39 PM PDT 24
Finished Jul 07 04:30:47 PM PDT 24
Peak memory 164768 kb
Host smart-f054aaac-5913-41b7-9c27-9e17f57a0402
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1566240931 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.1566240931
Directory /workspace/15.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.4179824720
Short name T52
Test name
Test status
Simulation time 1511450000 ps
CPU time 3.18 seconds
Started Jul 07 04:30:19 PM PDT 24
Finished Jul 07 04:30:27 PM PDT 24
Peak memory 164728 kb
Host smart-3533005d-9fc5-45c1-b73b-66f793cf9863
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4179824720 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.4179824720
Directory /workspace/16.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.941412259
Short name T13
Test name
Test status
Simulation time 1553710000 ps
CPU time 3.15 seconds
Started Jul 07 04:30:23 PM PDT 24
Finished Jul 07 04:30:31 PM PDT 24
Peak memory 164756 kb
Host smart-47ebc7f5-70ea-4271-b76d-84a2dc15cc11
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=941412259 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.941412259
Directory /workspace/17.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.484937116
Short name T69
Test name
Test status
Simulation time 1482390000 ps
CPU time 5.66 seconds
Started Jul 07 04:30:55 PM PDT 24
Finished Jul 07 04:31:07 PM PDT 24
Peak memory 164896 kb
Host smart-5e6c487c-331d-4f79-970c-a0b091893e64
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=484937116 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.484937116
Directory /workspace/18.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.2087501237
Short name T49
Test name
Test status
Simulation time 1649270000 ps
CPU time 3.52 seconds
Started Jul 07 04:30:22 PM PDT 24
Finished Jul 07 04:30:30 PM PDT 24
Peak memory 164768 kb
Host smart-95a3716c-77f9-497a-b06e-f18516663a77
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2087501237 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.2087501237
Directory /workspace/19.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.1375661859
Short name T48
Test name
Test status
Simulation time 1595830000 ps
CPU time 3.78 seconds
Started Jul 07 04:30:25 PM PDT 24
Finished Jul 07 04:30:34 PM PDT 24
Peak memory 164772 kb
Host smart-453b388a-f73c-448c-8a56-9f238274e533
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1375661859 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.1375661859
Directory /workspace/2.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.335471085
Short name T64
Test name
Test status
Simulation time 1622430000 ps
CPU time 3.69 seconds
Started Jul 07 04:30:16 PM PDT 24
Finished Jul 07 04:30:25 PM PDT 24
Peak memory 164744 kb
Host smart-0ef0b5e8-ebe7-4547-b42e-42381ef4ba11
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=335471085 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.335471085
Directory /workspace/20.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.1435552329
Short name T65
Test name
Test status
Simulation time 1427950000 ps
CPU time 3.09 seconds
Started Jul 07 04:30:50 PM PDT 24
Finished Jul 07 04:30:58 PM PDT 24
Peak memory 164768 kb
Host smart-3fadcd05-88cf-4425-9d38-95e105e31cce
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1435552329 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.1435552329
Directory /workspace/21.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.1103411925
Short name T38
Test name
Test status
Simulation time 1542730000 ps
CPU time 3.25 seconds
Started Jul 07 04:30:20 PM PDT 24
Finished Jul 07 04:30:27 PM PDT 24
Peak memory 164768 kb
Host smart-6c53981f-de37-4185-93d7-cc0f99c3723d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1103411925 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.1103411925
Directory /workspace/22.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.1593973522
Short name T39
Test name
Test status
Simulation time 1550990000 ps
CPU time 3.53 seconds
Started Jul 07 04:30:33 PM PDT 24
Finished Jul 07 04:30:41 PM PDT 24
Peak memory 164768 kb
Host smart-9ba57128-34d1-4c3d-97d3-92a5d0aed6fe
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1593973522 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.1593973522
Directory /workspace/23.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.3595878769
Short name T54
Test name
Test status
Simulation time 1433410000 ps
CPU time 3.86 seconds
Started Jul 07 04:30:25 PM PDT 24
Finished Jul 07 04:30:34 PM PDT 24
Peak memory 164756 kb
Host smart-fb4c5ff7-0794-4a71-b0ca-93aa3026e966
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3595878769 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.3595878769
Directory /workspace/24.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.1037930526
Short name T67
Test name
Test status
Simulation time 1415330000 ps
CPU time 5.78 seconds
Started Jul 07 04:30:27 PM PDT 24
Finished Jul 07 04:30:40 PM PDT 24
Peak memory 164772 kb
Host smart-58c51f93-2979-4f36-b74c-c4c11ba8e6f1
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1037930526 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.1037930526
Directory /workspace/25.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.3519014097
Short name T56
Test name
Test status
Simulation time 1526630000 ps
CPU time 3.66 seconds
Started Jul 07 04:30:49 PM PDT 24
Finished Jul 07 04:30:57 PM PDT 24
Peak memory 164764 kb
Host smart-05616ac0-28a9-419c-8703-f6e800f54941
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3519014097 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.3519014097
Directory /workspace/26.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.3569164638
Short name T53
Test name
Test status
Simulation time 1303670000 ps
CPU time 3.54 seconds
Started Jul 07 04:31:06 PM PDT 24
Finished Jul 07 04:31:14 PM PDT 24
Peak memory 164724 kb
Host smart-caaac0ab-02b1-40c9-a33f-eb3b3845f211
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3569164638 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.3569164638
Directory /workspace/27.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.4201366978
Short name T8
Test name
Test status
Simulation time 1628270000 ps
CPU time 4.2 seconds
Started Jul 07 04:30:33 PM PDT 24
Finished Jul 07 04:30:43 PM PDT 24
Peak memory 164772 kb
Host smart-2e6c67b2-696a-4f3e-be10-4ccbb96b10c9
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4201366978 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.4201366978
Directory /workspace/28.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.539742110
Short name T40
Test name
Test status
Simulation time 1138810000 ps
CPU time 3.09 seconds
Started Jul 07 04:30:26 PM PDT 24
Finished Jul 07 04:30:33 PM PDT 24
Peak memory 164764 kb
Host smart-027166f8-c59a-4b2a-905a-c685d86d70ec
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=539742110 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.539742110
Directory /workspace/29.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.138177932
Short name T51
Test name
Test status
Simulation time 1449450000 ps
CPU time 3.08 seconds
Started Jul 07 04:30:41 PM PDT 24
Finished Jul 07 04:30:48 PM PDT 24
Peak memory 164652 kb
Host smart-ccc78275-d634-4881-8bba-702f57feec88
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=138177932 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.138177932
Directory /workspace/3.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.2058132260
Short name T31
Test name
Test status
Simulation time 1532890000 ps
CPU time 3.58 seconds
Started Jul 07 04:30:56 PM PDT 24
Finished Jul 07 04:31:05 PM PDT 24
Peak memory 164780 kb
Host smart-bc5dc61a-25fc-41d4-a6cd-fa0d76f697bb
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2058132260 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.2058132260
Directory /workspace/30.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.1700545597
Short name T50
Test name
Test status
Simulation time 1548090000 ps
CPU time 3.74 seconds
Started Jul 07 04:30:49 PM PDT 24
Finished Jul 07 04:30:57 PM PDT 24
Peak memory 164772 kb
Host smart-2913d504-80a5-4076-a614-3f200b890b32
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1700545597 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.1700545597
Directory /workspace/31.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.507553579
Short name T1
Test name
Test status
Simulation time 1457330000 ps
CPU time 4.35 seconds
Started Jul 07 04:30:24 PM PDT 24
Finished Jul 07 04:30:34 PM PDT 24
Peak memory 164740 kb
Host smart-61e76878-9598-4c5e-ba9a-878cd12e5a5a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=507553579 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.507553579
Directory /workspace/32.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.3590650848
Short name T70
Test name
Test status
Simulation time 1312910000 ps
CPU time 3.04 seconds
Started Jul 07 04:30:42 PM PDT 24
Finished Jul 07 04:30:49 PM PDT 24
Peak memory 164768 kb
Host smart-18a18030-e295-4f07-85ba-8431682b3553
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3590650848 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.3590650848
Directory /workspace/33.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.1043856746
Short name T34
Test name
Test status
Simulation time 1323950000 ps
CPU time 2.9 seconds
Started Jul 07 04:30:33 PM PDT 24
Finished Jul 07 04:30:40 PM PDT 24
Peak memory 164768 kb
Host smart-bb215a50-4625-433a-9d3e-dbebaafcfb0e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1043856746 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.1043856746
Directory /workspace/34.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.429562497
Short name T36
Test name
Test status
Simulation time 1535090000 ps
CPU time 3.55 seconds
Started Jul 07 04:30:34 PM PDT 24
Finished Jul 07 04:30:47 PM PDT 24
Peak memory 164724 kb
Host smart-02227af0-4f2e-432d-a97b-e62efa4734ba
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=429562497 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.429562497
Directory /workspace/35.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.1512931141
Short name T60
Test name
Test status
Simulation time 1499090000 ps
CPU time 2.79 seconds
Started Jul 07 04:30:48 PM PDT 24
Finished Jul 07 04:30:54 PM PDT 24
Peak memory 164756 kb
Host smart-d90de056-06bc-4ffd-bd66-54633bc1d9e3
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1512931141 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.1512931141
Directory /workspace/36.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.1277776977
Short name T58
Test name
Test status
Simulation time 1430870000 ps
CPU time 3.16 seconds
Started Jul 07 04:30:22 PM PDT 24
Finished Jul 07 04:30:29 PM PDT 24
Peak memory 164768 kb
Host smart-e3f96cde-1142-4f09-a49c-30220d6fe698
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1277776977 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.1277776977
Directory /workspace/37.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.1212385430
Short name T12
Test name
Test status
Simulation time 1455970000 ps
CPU time 3.19 seconds
Started Jul 07 04:30:32 PM PDT 24
Finished Jul 07 04:30:39 PM PDT 24
Peak memory 164796 kb
Host smart-80193287-6b1b-47ff-a51e-782dd80d7758
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1212385430 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.1212385430
Directory /workspace/38.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.3627918785
Short name T35
Test name
Test status
Simulation time 1498050000 ps
CPU time 4.04 seconds
Started Jul 07 04:30:23 PM PDT 24
Finished Jul 07 04:30:32 PM PDT 24
Peak memory 164736 kb
Host smart-90b7ed03-4f6e-4f2e-a87f-41ecd87526c9
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3627918785 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.3627918785
Directory /workspace/39.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.751393993
Short name T61
Test name
Test status
Simulation time 1493830000 ps
CPU time 3.09 seconds
Started Jul 07 04:30:56 PM PDT 24
Finished Jul 07 04:31:03 PM PDT 24
Peak memory 164696 kb
Host smart-e2fe2519-fbcf-474f-b988-3cd256a12eb0
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=751393993 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.751393993
Directory /workspace/4.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.2324445088
Short name T42
Test name
Test status
Simulation time 1572410000 ps
CPU time 4.03 seconds
Started Jul 07 04:30:46 PM PDT 24
Finished Jul 07 04:30:55 PM PDT 24
Peak memory 164772 kb
Host smart-04df6d11-3867-441a-a03f-be3cf8b8bfee
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2324445088 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.2324445088
Directory /workspace/40.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.47440894
Short name T41
Test name
Test status
Simulation time 1355430000 ps
CPU time 2.79 seconds
Started Jul 07 04:30:29 PM PDT 24
Finished Jul 07 04:30:35 PM PDT 24
Peak memory 164652 kb
Host smart-48e41c08-57e7-49b8-b56d-b7016b7c2512
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=47440894 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.47440894
Directory /workspace/41.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.648804649
Short name T66
Test name
Test status
Simulation time 1503650000 ps
CPU time 3.47 seconds
Started Jul 07 04:30:46 PM PDT 24
Finished Jul 07 04:30:54 PM PDT 24
Peak memory 164764 kb
Host smart-1b855f79-6a86-453b-8880-9a6c1e1f6997
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=648804649 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.648804649
Directory /workspace/42.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.3030445939
Short name T33
Test name
Test status
Simulation time 1431490000 ps
CPU time 3.31 seconds
Started Jul 07 04:31:01 PM PDT 24
Finished Jul 07 04:31:09 PM PDT 24
Peak memory 164392 kb
Host smart-90a28318-c612-4b5c-9283-ad5a17a7d852
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3030445939 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.3030445939
Directory /workspace/43.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.3892417532
Short name T62
Test name
Test status
Simulation time 1571190000 ps
CPU time 3.06 seconds
Started Jul 07 04:30:19 PM PDT 24
Finished Jul 07 04:30:26 PM PDT 24
Peak memory 164768 kb
Host smart-83bc6c5a-97b2-4de1-89c6-3643fdad9f89
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3892417532 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.3892417532
Directory /workspace/44.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.4042202246
Short name T46
Test name
Test status
Simulation time 1439130000 ps
CPU time 3.32 seconds
Started Jul 07 04:30:44 PM PDT 24
Finished Jul 07 04:30:52 PM PDT 24
Peak memory 164752 kb
Host smart-6de1c344-6edf-497d-8919-bd43205bf975
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4042202246 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.4042202246
Directory /workspace/45.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.820179308
Short name T43
Test name
Test status
Simulation time 1538270000 ps
CPU time 3.43 seconds
Started Jul 07 04:30:48 PM PDT 24
Finished Jul 07 04:30:56 PM PDT 24
Peak memory 164684 kb
Host smart-64aff298-0c2e-4d92-bdfa-25db596740ac
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=820179308 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.820179308
Directory /workspace/46.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.3540140477
Short name T59
Test name
Test status
Simulation time 1585910000 ps
CPU time 4.76 seconds
Started Jul 07 04:30:55 PM PDT 24
Finished Jul 07 04:31:06 PM PDT 24
Peak memory 164772 kb
Host smart-323c687c-c81e-4280-b4e1-8cc5893e9377
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3540140477 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.3540140477
Directory /workspace/47.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.3098688781
Short name T11
Test name
Test status
Simulation time 1394710000 ps
CPU time 3.79 seconds
Started Jul 07 04:30:43 PM PDT 24
Finished Jul 07 04:30:52 PM PDT 24
Peak memory 164772 kb
Host smart-d2c1b00a-f5b1-4160-a298-d846cb0eed9d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3098688781 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.3098688781
Directory /workspace/48.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.474853027
Short name T57
Test name
Test status
Simulation time 1436130000 ps
CPU time 4.03 seconds
Started Jul 07 04:30:40 PM PDT 24
Finished Jul 07 04:30:49 PM PDT 24
Peak memory 164716 kb
Host smart-edbb0f48-b968-40d7-aced-d992bf752af9
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=474853027 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.474853027
Directory /workspace/49.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.3292432222
Short name T7
Test name
Test status
Simulation time 1463430000 ps
CPU time 3.04 seconds
Started Jul 07 04:30:40 PM PDT 24
Finished Jul 07 04:30:47 PM PDT 24
Peak memory 164772 kb
Host smart-d8493aa0-dac9-4210-89d8-d8f55feb63de
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3292432222 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.3292432222
Directory /workspace/5.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.3513739680
Short name T55
Test name
Test status
Simulation time 1509770000 ps
CPU time 6.29 seconds
Started Jul 07 04:30:30 PM PDT 24
Finished Jul 07 04:30:44 PM PDT 24
Peak memory 164772 kb
Host smart-06c7ec3d-8d15-4f12-bd58-da6af1e54bca
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3513739680 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.3513739680
Directory /workspace/6.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.1709071856
Short name T45
Test name
Test status
Simulation time 1470510000 ps
CPU time 3.47 seconds
Started Jul 07 04:30:22 PM PDT 24
Finished Jul 07 04:30:30 PM PDT 24
Peak memory 164864 kb
Host smart-08671a2b-6201-4a51-aea1-1f46b31bce74
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1709071856 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.1709071856
Directory /workspace/7.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.4262378885
Short name T2
Test name
Test status
Simulation time 1475310000 ps
CPU time 4.23 seconds
Started Jul 07 04:30:50 PM PDT 24
Finished Jul 07 04:31:00 PM PDT 24
Peak memory 164728 kb
Host smart-ed50f6d1-debf-4501-a7de-18d789ec6b44
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4262378885 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.4262378885
Directory /workspace/8.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.2204474570
Short name T10
Test name
Test status
Simulation time 1320130000 ps
CPU time 3.17 seconds
Started Jul 07 04:30:29 PM PDT 24
Finished Jul 07 04:30:36 PM PDT 24
Peak memory 164736 kb
Host smart-ccda90b6-f071-42e7-b34c-9b8c699f1379
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2204474570 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.2204474570
Directory /workspace/9.prim_lfsr_gal_smoke/latest
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