Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.31 100.00 96.55 100.00 100.00 95.00


Total tests in report: 200
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
87.31 87.31 100.00 100.00 96.55 96.55 100.00 100.00 100.00 100.00 40.00 40.00 /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.1586352374
96.81 9.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 87.50 47.50 /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.3756826270
98.31 1.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 95.00 7.50 /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.3031272310

Tests that do not contribute to grading

Name
/workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.3762518647
/workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.1794380615
/workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.1617454887
/workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.1899042579
/workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.4184670016
/workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.2364103267
/workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.2422593230
/workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.1215958075
/workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.1684102186
/workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.2689759207
/workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2799350403
/workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.1660587441
/workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.1803315096
/workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.4087362520
/workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.1360904649
/workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.710811898
/workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.2951286357
/workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.3255709742
/workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1875089508
/workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.1257383024
/workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.3101590852
/workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.4281149239
/workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.1296863631
/workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3404745507
/workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.2319573673
/workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.1495780805
/workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.3919996759
/workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.2477515606
/workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.669765869
/workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.4157007815
/workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.1101962631
/workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.591941809
/workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.2587575720
/workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.2988891353
/workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.161396693
/workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.329783303
/workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.1071314741
/workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.908313667
/workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.3417424021
/workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.3110431101
/workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.3275477982
/workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.1247649777
/workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.2454811276
/workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.2857720125
/workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.2707953701
/workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.366769517
/workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.589173750
/workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.2168606689
/workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.683748151
/workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.565117787
/workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.449735738
/workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.3867604488
/workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.2371371761
/workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.3893638756
/workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.1498417230
/workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.3421499663
/workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.2967461619
/workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.496302274
/workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.2689917561
/workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.1568350276
/workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.2787498995
/workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.935736970
/workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.2950677451
/workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.2283604247
/workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.1707981819
/workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.3672389662
/workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.2435065105
/workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.1520121355
/workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.3774937561
/workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.3890910562
/workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.3530278954
/workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.770081197
/workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.1357924518
/workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.704613010
/workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.555133635
/workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.3508302259
/workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.3403167569
/workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.3323769886
/workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.174802145
/workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.1715576070
/workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.1118105277
/workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.4125554235
/workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.3937434236
/workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.3482443394
/workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.1224868568
/workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.3644920631
/workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.3358053136
/workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.2582769044
/workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.2595682910
/workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.1315323430
/workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.3541178297
/workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.2816920918
/workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.275638033
/workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.4040794353
/workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.447303355
/workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.657434840
/workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.248563878
/workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.2697625952
/workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.2812936077
/workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.3569081917
/workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.4205542699
/workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.2306616578
/workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.2083322625
/workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.3904362566
/workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.3593268771
/workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.1472560784
/workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.3339105238
/workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.2603820077
/workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.1371270487
/workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.556804388
/workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.95714107
/workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.4103402413
/workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.4060914841
/workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.203779751
/workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.1369803020
/workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.1452651883
/workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.2632636053
/workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2019427665
/workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.3552414955
/workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.3173791693
/workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.963496238
/workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.1449117267
/workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.96698626
/workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.1111668882
/workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.4175820278
/workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.356073335
/workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.1827185528
/workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.4103207163
/workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.763168621
/workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.739145966
/workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.4025444815
/workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.3132796725
/workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.107005965
/workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.2249398598
/workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.2837173926
/workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.2813884649
/workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1372867698
/workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.4290540369
/workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.1268748858
/workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.1891866852
/workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.3308421473
/workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.431381379
/workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.1828888405
/workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.2908681335
/workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.1899814823
/workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.3171832161
/workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.3011979032
/workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.614801757
/workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.3435778941
/workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.2569752524
/workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.3070137480
/workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.1122120777
/workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.1656282313
/workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.3901170909
/workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.3675518890
/workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.759960268
/workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.283333239
/workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.4155571594
/workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.3115868526
/workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.1068267689
/workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.4249535454
/workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.1779802828
/workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.3456468980
/workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.3692187328
/workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.4149179179
/workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.2483997142
/workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.4261930098
/workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.2409139725
/workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.972335579
/workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.2597453857
/workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.914574886
/workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.1647581019
/workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.22031689
/workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.3756045105
/workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.3520667449
/workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.2866449141
/workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.1923957655
/workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.4084632554
/workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.2298172985
/workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.1153373546
/workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.612608477
/workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.1181058293
/workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.1988073590
/workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.1817232879
/workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.3514522318
/workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.817819798
/workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.2137518169
/workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.907054355
/workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.2719550286
/workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.634956787
/workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.2427530373
/workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.1449524598
/workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.4029944167
/workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.357798969
/workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.4232137695
/workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.3855774360
/workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.3076057283



Total test records in report: 200
tests.html | tests1.html | tests2.html | tests3.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.1449524598 Jul 09 04:51:29 PM PDT 24 Jul 09 04:51:35 PM PDT 24 1004930000 ps
T2 /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.2409139725 Jul 09 04:51:23 PM PDT 24 Jul 09 04:51:32 PM PDT 24 1297690000 ps
T3 /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.1068267689 Jul 09 04:51:17 PM PDT 24 Jul 09 04:51:30 PM PDT 24 1558610000 ps
T4 /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.3115868526 Jul 09 04:51:15 PM PDT 24 Jul 09 04:51:28 PM PDT 24 1541650000 ps
T8 /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.3076057283 Jul 09 04:51:20 PM PDT 24 Jul 09 04:51:29 PM PDT 24 1375030000 ps
T9 /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.3456468980 Jul 09 04:51:34 PM PDT 24 Jul 09 04:51:47 PM PDT 24 1623190000 ps
T10 /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.1586352374 Jul 09 04:51:25 PM PDT 24 Jul 09 04:51:35 PM PDT 24 1525070000 ps
T11 /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.1122120777 Jul 09 04:51:17 PM PDT 24 Jul 09 04:51:29 PM PDT 24 1458910000 ps
T12 /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.3675518890 Jul 09 04:51:27 PM PDT 24 Jul 09 04:51:37 PM PDT 24 1531710000 ps
T13 /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.1153373546 Jul 09 04:51:39 PM PDT 24 Jul 09 04:51:48 PM PDT 24 1316090000 ps
T31 /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.2298172985 Jul 09 04:51:32 PM PDT 24 Jul 09 04:51:39 PM PDT 24 1241450000 ps
T32 /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.1923957655 Jul 09 04:51:30 PM PDT 24 Jul 09 04:51:37 PM PDT 24 1311590000 ps
T33 /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.817819798 Jul 09 04:51:37 PM PDT 24 Jul 09 04:51:49 PM PDT 24 1599890000 ps
T34 /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.907054355 Jul 09 04:51:38 PM PDT 24 Jul 09 04:51:49 PM PDT 24 1526570000 ps
T35 /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.4232137695 Jul 09 04:51:31 PM PDT 24 Jul 09 04:51:39 PM PDT 24 1424330000 ps
T36 /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.1779802828 Jul 09 04:51:31 PM PDT 24 Jul 09 04:51:42 PM PDT 24 1497350000 ps
T37 /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.1656282313 Jul 09 04:51:23 PM PDT 24 Jul 09 04:51:32 PM PDT 24 1452650000 ps
T38 /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.3435778941 Jul 09 04:51:25 PM PDT 24 Jul 09 04:51:33 PM PDT 24 1186370000 ps
T39 /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.1181058293 Jul 09 04:51:22 PM PDT 24 Jul 09 04:51:33 PM PDT 24 1570350000 ps
T40 /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.2597453857 Jul 09 04:51:24 PM PDT 24 Jul 09 04:51:33 PM PDT 24 1441930000 ps
T41 /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.3520667449 Jul 09 04:51:38 PM PDT 24 Jul 09 04:51:49 PM PDT 24 1289450000 ps
T42 /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.2719550286 Jul 09 04:51:28 PM PDT 24 Jul 09 04:51:39 PM PDT 24 1464310000 ps
T43 /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.1988073590 Jul 09 04:51:32 PM PDT 24 Jul 09 04:51:42 PM PDT 24 1512950000 ps
T44 /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.3901170909 Jul 09 04:51:17 PM PDT 24 Jul 09 04:51:27 PM PDT 24 1634250000 ps
T45 /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.4249535454 Jul 09 04:51:16 PM PDT 24 Jul 09 04:51:24 PM PDT 24 1358350000 ps
T46 /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.972335579 Jul 09 04:51:17 PM PDT 24 Jul 09 04:51:28 PM PDT 24 1449570000 ps
T47 /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.4155571594 Jul 09 04:51:14 PM PDT 24 Jul 09 04:51:25 PM PDT 24 1416830000 ps
T48 /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.759960268 Jul 09 04:51:27 PM PDT 24 Jul 09 04:51:38 PM PDT 24 1478030000 ps
T49 /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.3756045105 Jul 09 04:51:21 PM PDT 24 Jul 09 04:51:29 PM PDT 24 1216850000 ps
T50 /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.612608477 Jul 09 04:51:47 PM PDT 24 Jul 09 04:51:58 PM PDT 24 1467270000 ps
T51 /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.1647581019 Jul 09 04:51:24 PM PDT 24 Jul 09 04:51:33 PM PDT 24 1495190000 ps
T52 /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.2483997142 Jul 09 04:51:20 PM PDT 24 Jul 09 04:51:31 PM PDT 24 1587710000 ps
T53 /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.2137518169 Jul 09 04:51:28 PM PDT 24 Jul 09 04:51:39 PM PDT 24 1462310000 ps
T54 /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.357798969 Jul 09 04:51:11 PM PDT 24 Jul 09 04:51:23 PM PDT 24 1267870000 ps
T55 /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.3692187328 Jul 09 04:51:32 PM PDT 24 Jul 09 04:51:42 PM PDT 24 1476570000 ps
T56 /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.3070137480 Jul 09 04:51:23 PM PDT 24 Jul 09 04:51:34 PM PDT 24 1618610000 ps
T57 /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.4261930098 Jul 09 04:51:33 PM PDT 24 Jul 09 04:51:46 PM PDT 24 1518870000 ps
T58 /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.22031689 Jul 09 04:51:31 PM PDT 24 Jul 09 04:51:40 PM PDT 24 1539810000 ps
T59 /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.914574886 Jul 09 04:51:36 PM PDT 24 Jul 09 04:51:48 PM PDT 24 1506650000 ps
T60 /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.4084632554 Jul 09 04:51:38 PM PDT 24 Jul 09 04:51:53 PM PDT 24 1441890000 ps
T61 /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.634956787 Jul 09 04:51:21 PM PDT 24 Jul 09 04:51:29 PM PDT 24 1520710000 ps
T62 /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.283333239 Jul 09 04:51:33 PM PDT 24 Jul 09 04:51:46 PM PDT 24 1522550000 ps
T63 /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.2569752524 Jul 09 04:51:26 PM PDT 24 Jul 09 04:51:36 PM PDT 24 1212950000 ps
T64 /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.3514522318 Jul 09 04:51:22 PM PDT 24 Jul 09 04:51:32 PM PDT 24 1484370000 ps
T65 /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.4029944167 Jul 09 04:51:26 PM PDT 24 Jul 09 04:51:34 PM PDT 24 1254870000 ps
T66 /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.2427530373 Jul 09 04:51:22 PM PDT 24 Jul 09 04:51:31 PM PDT 24 1349370000 ps
T67 /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.3855774360 Jul 09 04:51:30 PM PDT 24 Jul 09 04:51:42 PM PDT 24 1514570000 ps
T68 /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.2866449141 Jul 09 04:51:26 PM PDT 24 Jul 09 04:51:37 PM PDT 24 1475210000 ps
T69 /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.1817232879 Jul 09 04:51:25 PM PDT 24 Jul 09 04:51:35 PM PDT 24 1589450000 ps
T70 /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.4149179179 Jul 09 04:51:14 PM PDT 24 Jul 09 04:51:24 PM PDT 24 1529010000 ps
T5 /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.669765869 Jul 09 04:51:41 PM PDT 24 Jul 09 05:25:44 PM PDT 24 336473650000 ps
T6 /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.1247649777 Jul 09 04:51:17 PM PDT 24 Jul 09 05:25:31 PM PDT 24 336598430000 ps
T7 /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.3756826270 Jul 09 04:51:13 PM PDT 24 Jul 09 05:22:51 PM PDT 24 336899930000 ps
T14 /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.3110431101 Jul 09 04:51:17 PM PDT 24 Jul 09 05:22:49 PM PDT 24 336704170000 ps
T15 /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.908313667 Jul 09 04:51:20 PM PDT 24 Jul 09 05:28:56 PM PDT 24 336969790000 ps
T16 /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.1684102186 Jul 09 04:51:11 PM PDT 24 Jul 09 05:25:25 PM PDT 24 336770730000 ps
T17 /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1875089508 Jul 09 04:51:14 PM PDT 24 Jul 09 05:21:15 PM PDT 24 336341330000 ps
T18 /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.3255709742 Jul 09 04:51:14 PM PDT 24 Jul 09 05:27:25 PM PDT 24 336875830000 ps
T19 /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.329783303 Jul 09 04:51:15 PM PDT 24 Jul 09 05:23:59 PM PDT 24 336715210000 ps
T20 /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2799350403 Jul 09 04:51:16 PM PDT 24 Jul 09 05:23:26 PM PDT 24 337041810000 ps
T71 /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.1803315096 Jul 09 04:51:23 PM PDT 24 Jul 09 05:20:11 PM PDT 24 336589390000 ps
T72 /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.1660587441 Jul 09 04:51:27 PM PDT 24 Jul 09 05:27:22 PM PDT 24 336617210000 ps
T73 /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.2168606689 Jul 09 04:51:11 PM PDT 24 Jul 09 05:22:42 PM PDT 24 336319850000 ps
T74 /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.2477515606 Jul 09 04:51:30 PM PDT 24 Jul 09 05:28:56 PM PDT 24 336958010000 ps
T75 /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.589173750 Jul 09 04:51:10 PM PDT 24 Jul 09 05:23:58 PM PDT 24 337133970000 ps
T76 /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.4184670016 Jul 09 04:51:38 PM PDT 24 Jul 09 05:18:38 PM PDT 24 336744770000 ps
T77 /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.366769517 Jul 09 04:51:13 PM PDT 24 Jul 09 05:21:51 PM PDT 24 336851770000 ps
T78 /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.2422593230 Jul 09 04:51:11 PM PDT 24 Jul 09 05:27:29 PM PDT 24 336878290000 ps
T79 /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.3919996759 Jul 09 04:51:20 PM PDT 24 Jul 09 05:22:51 PM PDT 24 336620690000 ps
T80 /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.4281149239 Jul 09 04:51:16 PM PDT 24 Jul 09 05:21:54 PM PDT 24 336602230000 ps
T81 /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.1257383024 Jul 09 04:51:14 PM PDT 24 Jul 09 05:25:31 PM PDT 24 336428850000 ps
T82 /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.1899042579 Jul 09 04:51:15 PM PDT 24 Jul 09 05:25:32 PM PDT 24 337054850000 ps
T83 /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.2857720125 Jul 09 04:51:28 PM PDT 24 Jul 09 05:22:53 PM PDT 24 336827370000 ps
T84 /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.161396693 Jul 09 04:51:19 PM PDT 24 Jul 09 05:23:03 PM PDT 24 336550310000 ps
T85 /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.1794380615 Jul 09 04:51:15 PM PDT 24 Jul 09 05:21:58 PM PDT 24 336819670000 ps
T86 /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.591941809 Jul 09 04:51:28 PM PDT 24 Jul 09 05:24:27 PM PDT 24 336552690000 ps
T87 /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.1495780805 Jul 09 04:51:16 PM PDT 24 Jul 09 05:24:21 PM PDT 24 336676490000 ps
T88 /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.1071314741 Jul 09 04:51:26 PM PDT 24 Jul 09 05:28:39 PM PDT 24 337061970000 ps
T89 /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.2319573673 Jul 09 04:51:19 PM PDT 24 Jul 09 05:25:46 PM PDT 24 336566670000 ps
T90 /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.1215958075 Jul 09 04:51:20 PM PDT 24 Jul 09 05:23:29 PM PDT 24 336950450000 ps
T91 /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.4157007815 Jul 09 04:51:32 PM PDT 24 Jul 09 05:24:26 PM PDT 24 336926590000 ps
T92 /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.4087362520 Jul 09 04:51:14 PM PDT 24 Jul 09 05:24:15 PM PDT 24 336801790000 ps
T93 /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.2364103267 Jul 09 04:51:11 PM PDT 24 Jul 09 05:22:06 PM PDT 24 336446030000 ps
T94 /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.3275477982 Jul 09 04:51:15 PM PDT 24 Jul 09 05:24:08 PM PDT 24 336312130000 ps
T95 /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.1617454887 Jul 09 04:51:12 PM PDT 24 Jul 09 05:27:30 PM PDT 24 336649310000 ps
T96 /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3404745507 Jul 09 04:51:24 PM PDT 24 Jul 09 05:24:23 PM PDT 24 336997310000 ps
T97 /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.1360904649 Jul 09 04:51:16 PM PDT 24 Jul 09 05:24:53 PM PDT 24 336767630000 ps
T98 /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.2707953701 Jul 09 04:51:22 PM PDT 24 Jul 09 05:26:57 PM PDT 24 337046890000 ps
T99 /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.710811898 Jul 09 04:51:38 PM PDT 24 Jul 09 05:18:29 PM PDT 24 336432410000 ps
T100 /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.2454811276 Jul 09 04:51:27 PM PDT 24 Jul 09 05:24:16 PM PDT 24 336582930000 ps
T101 /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.3417424021 Jul 09 04:51:24 PM PDT 24 Jul 09 05:27:51 PM PDT 24 336570210000 ps
T102 /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.2951286357 Jul 09 04:51:37 PM PDT 24 Jul 09 05:20:47 PM PDT 24 336335630000 ps
T103 /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.1296863631 Jul 09 04:51:22 PM PDT 24 Jul 09 05:20:38 PM PDT 24 336702650000 ps
T104 /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.3101590852 Jul 09 04:51:44 PM PDT 24 Jul 09 05:21:07 PM PDT 24 336784810000 ps
T105 /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.683748151 Jul 09 04:51:23 PM PDT 24 Jul 09 05:26:53 PM PDT 24 336413850000 ps
T106 /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.2689759207 Jul 09 04:51:18 PM PDT 24 Jul 09 05:23:56 PM PDT 24 336984590000 ps
T107 /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.3762518647 Jul 09 04:51:10 PM PDT 24 Jul 09 05:25:16 PM PDT 24 336880990000 ps
T108 /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.1101962631 Jul 09 04:51:15 PM PDT 24 Jul 09 05:22:54 PM PDT 24 336492130000 ps
T109 /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.2988891353 Jul 09 04:51:09 PM PDT 24 Jul 09 05:20:40 PM PDT 24 336688350000 ps
T110 /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.2587575720 Jul 09 04:51:16 PM PDT 24 Jul 09 05:25:18 PM PDT 24 337027310000 ps
T111 /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.203779751 Jul 09 04:51:34 PM PDT 24 Jul 09 04:51:45 PM PDT 24 1367590000 ps
T112 /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.2603820077 Jul 09 04:51:41 PM PDT 24 Jul 09 04:51:52 PM PDT 24 1524730000 ps
T113 /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.2908681335 Jul 09 04:51:38 PM PDT 24 Jul 09 04:51:48 PM PDT 24 1334630000 ps
T114 /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.1899814823 Jul 09 04:51:39 PM PDT 24 Jul 09 04:51:51 PM PDT 24 1491530000 ps
T115 /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2019427665 Jul 09 04:51:32 PM PDT 24 Jul 09 04:51:39 PM PDT 24 1342950000 ps
T116 /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.4103207163 Jul 09 04:51:38 PM PDT 24 Jul 09 04:51:49 PM PDT 24 1503350000 ps
T117 /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.1828888405 Jul 09 04:51:44 PM PDT 24 Jul 09 04:51:58 PM PDT 24 1584130000 ps
T118 /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.2083322625 Jul 09 04:51:48 PM PDT 24 Jul 09 04:51:58 PM PDT 24 1453310000 ps
T119 /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1372867698 Jul 09 04:51:45 PM PDT 24 Jul 09 04:51:53 PM PDT 24 1353730000 ps
T120 /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.95714107 Jul 09 04:51:38 PM PDT 24 Jul 09 04:51:45 PM PDT 24 1502810000 ps
T121 /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.431381379 Jul 09 04:51:34 PM PDT 24 Jul 09 04:51:44 PM PDT 24 1446630000 ps
T122 /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.739145966 Jul 09 04:51:43 PM PDT 24 Jul 09 04:51:53 PM PDT 24 1429110000 ps
T123 /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.1268748858 Jul 09 04:51:30 PM PDT 24 Jul 09 04:51:39 PM PDT 24 1463070000 ps
T124 /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.2306616578 Jul 09 04:51:38 PM PDT 24 Jul 09 04:51:48 PM PDT 24 1501030000 ps
T125 /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.1452651883 Jul 09 04:51:43 PM PDT 24 Jul 09 04:51:55 PM PDT 24 1477490000 ps
T126 /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.3904362566 Jul 09 04:51:41 PM PDT 24 Jul 09 04:51:52 PM PDT 24 1437690000 ps
T127 /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.614801757 Jul 09 04:51:39 PM PDT 24 Jul 09 04:51:48 PM PDT 24 1562690000 ps
T128 /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.4103402413 Jul 09 04:51:48 PM PDT 24 Jul 09 04:51:59 PM PDT 24 1537650000 ps
T129 /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.2632636053 Jul 09 04:51:41 PM PDT 24 Jul 09 04:51:52 PM PDT 24 1582730000 ps
T130 /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.1369803020 Jul 09 04:51:43 PM PDT 24 Jul 09 04:51:53 PM PDT 24 1414410000 ps
T131 /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.1449117267 Jul 09 04:51:28 PM PDT 24 Jul 09 04:51:36 PM PDT 24 1481470000 ps
T132 /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.107005965 Jul 09 04:51:36 PM PDT 24 Jul 09 04:51:46 PM PDT 24 1458090000 ps
T133 /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.1111668882 Jul 09 04:51:31 PM PDT 24 Jul 09 04:51:41 PM PDT 24 1332710000 ps
T134 /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.4060914841 Jul 09 04:51:35 PM PDT 24 Jul 09 04:51:44 PM PDT 24 1342490000 ps
T135 /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.2812936077 Jul 09 04:51:36 PM PDT 24 Jul 09 04:51:44 PM PDT 24 1464310000 ps
T136 /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.2249398598 Jul 09 04:51:39 PM PDT 24 Jul 09 04:51:48 PM PDT 24 1293970000 ps
T137 /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.3569081917 Jul 09 04:51:28 PM PDT 24 Jul 09 04:51:38 PM PDT 24 1601030000 ps
T138 /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.3339105238 Jul 09 04:51:40 PM PDT 24 Jul 09 04:51:52 PM PDT 24 1571650000 ps
T139 /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.3308421473 Jul 09 04:51:46 PM PDT 24 Jul 09 04:51:54 PM PDT 24 1168270000 ps
T140 /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.3132796725 Jul 09 04:51:43 PM PDT 24 Jul 09 04:51:55 PM PDT 24 1556970000 ps
T141 /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.2837173926 Jul 09 04:51:40 PM PDT 24 Jul 09 04:51:51 PM PDT 24 1388910000 ps
T142 /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.963496238 Jul 09 04:51:45 PM PDT 24 Jul 09 04:51:57 PM PDT 24 1522850000 ps
T143 /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.3593268771 Jul 09 04:51:37 PM PDT 24 Jul 09 04:51:45 PM PDT 24 1385870000 ps
T144 /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.96698626 Jul 09 04:51:33 PM PDT 24 Jul 09 04:51:45 PM PDT 24 1449810000 ps
T145 /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.3552414955 Jul 09 04:51:52 PM PDT 24 Jul 09 04:52:02 PM PDT 24 1394630000 ps
T146 /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.3011979032 Jul 09 04:51:34 PM PDT 24 Jul 09 04:51:43 PM PDT 24 1599770000 ps
T147 /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.1472560784 Jul 09 04:51:33 PM PDT 24 Jul 09 04:51:45 PM PDT 24 1415290000 ps
T148 /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.356073335 Jul 09 04:51:33 PM PDT 24 Jul 09 04:51:43 PM PDT 24 1567730000 ps
T149 /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.1827185528 Jul 09 04:51:39 PM PDT 24 Jul 09 04:51:50 PM PDT 24 1469430000 ps
T150 /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.3173791693 Jul 09 04:51:47 PM PDT 24 Jul 09 04:51:56 PM PDT 24 1464310000 ps
T151 /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.1371270487 Jul 09 04:51:39 PM PDT 24 Jul 09 04:51:49 PM PDT 24 1425950000 ps
T152 /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.4025444815 Jul 09 04:51:39 PM PDT 24 Jul 09 04:51:51 PM PDT 24 1591670000 ps
T153 /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.2813884649 Jul 09 04:51:40 PM PDT 24 Jul 09 04:51:52 PM PDT 24 1476270000 ps
T154 /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.763168621 Jul 09 04:51:43 PM PDT 24 Jul 09 04:51:54 PM PDT 24 1462170000 ps
T155 /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.3171832161 Jul 09 04:51:28 PM PDT 24 Jul 09 04:51:39 PM PDT 24 1546670000 ps
T156 /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.4290540369 Jul 09 04:51:41 PM PDT 24 Jul 09 04:51:54 PM PDT 24 1296170000 ps
T157 /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.4205542699 Jul 09 04:51:34 PM PDT 24 Jul 09 04:51:44 PM PDT 24 1506410000 ps
T158 /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.556804388 Jul 09 04:51:41 PM PDT 24 Jul 09 04:51:53 PM PDT 24 1505330000 ps
T159 /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.1891866852 Jul 09 04:51:40 PM PDT 24 Jul 09 04:51:50 PM PDT 24 1456570000 ps
T160 /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.4175820278 Jul 09 04:51:39 PM PDT 24 Jul 09 04:51:49 PM PDT 24 1382830000 ps
T21 /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.2950677451 Jul 09 04:51:38 PM PDT 24 Jul 09 05:28:26 PM PDT 24 336765610000 ps
T22 /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.3482443394 Jul 09 04:51:48 PM PDT 24 Jul 09 05:27:48 PM PDT 24 336599610000 ps
T23 /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.1224868568 Jul 09 04:51:45 PM PDT 24 Jul 09 05:26:23 PM PDT 24 337161830000 ps
T24 /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.248563878 Jul 09 04:51:42 PM PDT 24 Jul 09 05:22:28 PM PDT 24 336665850000 ps
T25 /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.1498417230 Jul 09 04:51:43 PM PDT 24 Jul 09 05:22:27 PM PDT 24 336905630000 ps
T26 /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.2283604247 Jul 09 04:51:44 PM PDT 24 Jul 09 05:26:18 PM PDT 24 336882850000 ps
T27 /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.496302274 Jul 09 04:51:39 PM PDT 24 Jul 09 05:23:55 PM PDT 24 336309450000 ps
T28 /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.3031272310 Jul 09 04:51:43 PM PDT 24 Jul 09 05:22:39 PM PDT 24 337095950000 ps
T29 /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.2371371761 Jul 09 04:51:40 PM PDT 24 Jul 09 05:23:43 PM PDT 24 336503010000 ps
T30 /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.1715576070 Jul 09 04:51:44 PM PDT 24 Jul 09 05:20:41 PM PDT 24 336561390000 ps
T161 /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.2582769044 Jul 09 04:51:43 PM PDT 24 Jul 09 05:25:19 PM PDT 24 337021710000 ps
T162 /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.657434840 Jul 09 04:51:43 PM PDT 24 Jul 09 05:25:00 PM PDT 24 336621410000 ps
T163 /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.3890910562 Jul 09 04:51:38 PM PDT 24 Jul 09 05:25:57 PM PDT 24 336701190000 ps
T164 /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.174802145 Jul 09 04:51:46 PM PDT 24 Jul 09 05:22:33 PM PDT 24 336382050000 ps
T165 /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.704613010 Jul 09 04:51:40 PM PDT 24 Jul 09 05:25:03 PM PDT 24 336595350000 ps
T166 /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.2816920918 Jul 09 04:51:39 PM PDT 24 Jul 09 05:24:14 PM PDT 24 336747890000 ps
T167 /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.3937434236 Jul 09 04:51:42 PM PDT 24 Jul 09 05:24:36 PM PDT 24 336939930000 ps
T168 /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.565117787 Jul 09 04:51:37 PM PDT 24 Jul 09 05:16:28 PM PDT 24 336402030000 ps
T169 /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.3867604488 Jul 09 04:51:45 PM PDT 24 Jul 09 05:27:40 PM PDT 24 336897850000 ps
T170 /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.3644920631 Jul 09 04:51:40 PM PDT 24 Jul 09 05:23:08 PM PDT 24 336527050000 ps
T171 /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.447303355 Jul 09 04:51:44 PM PDT 24 Jul 09 05:24:07 PM PDT 24 337018550000 ps
T172 /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.2967461619 Jul 09 04:51:44 PM PDT 24 Jul 09 05:25:18 PM PDT 24 336458670000 ps
T173 /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.3358053136 Jul 09 04:51:44 PM PDT 24 Jul 09 05:13:29 PM PDT 24 336864410000 ps
T174 /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.935736970 Jul 09 04:51:47 PM PDT 24 Jul 09 05:23:09 PM PDT 24 336318270000 ps
T175 /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.4125554235 Jul 09 04:51:43 PM PDT 24 Jul 09 05:26:21 PM PDT 24 336775290000 ps
T176 /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.3774937561 Jul 09 04:51:46 PM PDT 24 Jul 09 05:21:38 PM PDT 24 336615430000 ps
T177 /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.3508302259 Jul 09 04:51:45 PM PDT 24 Jul 09 05:19:53 PM PDT 24 336789410000 ps
T178 /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.449735738 Jul 09 04:51:37 PM PDT 24 Jul 09 05:25:11 PM PDT 24 336712370000 ps
T179 /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.1357924518 Jul 09 04:51:41 PM PDT 24 Jul 09 05:25:02 PM PDT 24 336363150000 ps
T180 /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.2697625952 Jul 09 04:51:44 PM PDT 24 Jul 09 05:22:31 PM PDT 24 336710270000 ps
T181 /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.2595682910 Jul 09 04:52:03 PM PDT 24 Jul 09 05:20:39 PM PDT 24 336842610000 ps
T182 /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.1520121355 Jul 09 04:51:44 PM PDT 24 Jul 09 05:21:34 PM PDT 24 336673950000 ps
T183 /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.3403167569 Jul 09 04:51:40 PM PDT 24 Jul 09 05:21:46 PM PDT 24 336396630000 ps
T184 /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.1568350276 Jul 09 04:51:49 PM PDT 24 Jul 09 05:28:03 PM PDT 24 336519470000 ps
T185 /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.1707981819 Jul 09 04:51:31 PM PDT 24 Jul 09 05:25:38 PM PDT 24 336454950000 ps
T186 /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.2787498995 Jul 09 04:51:39 PM PDT 24 Jul 09 05:27:53 PM PDT 24 336847850000 ps
T187 /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.2435065105 Jul 09 04:51:53 PM PDT 24 Jul 09 05:26:47 PM PDT 24 336933670000 ps
T188 /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.555133635 Jul 09 04:51:44 PM PDT 24 Jul 09 05:26:10 PM PDT 24 336473390000 ps
T189 /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.3323769886 Jul 09 04:51:42 PM PDT 24 Jul 09 05:24:39 PM PDT 24 336782690000 ps
T190 /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.3421499663 Jul 09 04:51:51 PM PDT 24 Jul 09 05:21:39 PM PDT 24 336721450000 ps
T191 /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.2689917561 Jul 09 04:51:35 PM PDT 24 Jul 09 05:22:12 PM PDT 24 336820430000 ps
T192 /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.275638033 Jul 09 04:51:41 PM PDT 24 Jul 09 05:21:44 PM PDT 24 336496370000 ps
T193 /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.3893638756 Jul 09 04:51:46 PM PDT 24 Jul 09 05:21:27 PM PDT 24 336391470000 ps
T194 /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.770081197 Jul 09 04:51:39 PM PDT 24 Jul 09 05:26:26 PM PDT 24 337113630000 ps
T195 /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.4040794353 Jul 09 04:51:41 PM PDT 24 Jul 09 05:21:54 PM PDT 24 337091630000 ps
T196 /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.3672389662 Jul 09 04:51:41 PM PDT 24 Jul 09 05:28:10 PM PDT 24 336316310000 ps
T197 /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.1118105277 Jul 09 04:51:41 PM PDT 24 Jul 09 05:22:22 PM PDT 24 336948470000 ps
T198 /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.1315323430 Jul 09 04:51:51 PM PDT 24 Jul 09 05:24:26 PM PDT 24 336990750000 ps
T199 /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.3530278954 Jul 09 04:51:31 PM PDT 24 Jul 09 05:22:34 PM PDT 24 336608470000 ps
T200 /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.3541178297 Jul 09 04:51:47 PM PDT 24 Jul 09 05:17:31 PM PDT 24 336679330000 ps

Test location /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.1586352374
Short name T10
Test name
Test status
Simulation time 1525070000 ps
CPU time 4.59 seconds
Started Jul 09 04:51:25 PM PDT 24
Finished Jul 09 04:51:35 PM PDT 24
Peak memory 164908 kb
Host smart-c9c07684-8506-4279-bea6-01a778a771fd
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1586352374 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.1586352374
Directory /workspace/0.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.3756826270
Short name T7
Test name
Test status
Simulation time 336899930000 ps
CPU time 784.42 seconds
Started Jul 09 04:51:13 PM PDT 24
Finished Jul 09 05:22:51 PM PDT 24
Peak memory 160728 kb
Host smart-5ca35578-e33f-429b-a526-4eee7e40eaa9
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3756826270 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.3756826270
Directory /workspace/10.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.3031272310
Short name T28
Test name
Test status
Simulation time 337095950000 ps
CPU time 765.82 seconds
Started Jul 09 04:51:43 PM PDT 24
Finished Jul 09 05:22:39 PM PDT 24
Peak memory 160672 kb
Host smart-3c123947-7fe5-4c71-aa61-ce6adee50742
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3031272310 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.3031272310
Directory /workspace/11.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.3762518647
Short name T107
Test name
Test status
Simulation time 336880990000 ps
CPU time 839.96 seconds
Started Jul 09 04:51:10 PM PDT 24
Finished Jul 09 05:25:16 PM PDT 24
Peak memory 160720 kb
Host smart-7da5e154-16d8-4323-ae26-d38d6f2fb889
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3762518647 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.3762518647
Directory /workspace/0.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.1794380615
Short name T85
Test name
Test status
Simulation time 336819670000 ps
CPU time 761.84 seconds
Started Jul 09 04:51:15 PM PDT 24
Finished Jul 09 05:21:58 PM PDT 24
Peak memory 160684 kb
Host smart-567a90bf-6a88-4ce7-aeb2-abaffbc24e10
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1794380615 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.1794380615
Directory /workspace/1.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.1617454887
Short name T95
Test name
Test status
Simulation time 336649310000 ps
CPU time 883.4 seconds
Started Jul 09 04:51:12 PM PDT 24
Finished Jul 09 05:27:30 PM PDT 24
Peak memory 160624 kb
Host smart-60ab6f43-f74a-45ce-a9ee-a904eecca6b8
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1617454887 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.1617454887
Directory /workspace/11.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.1899042579
Short name T82
Test name
Test status
Simulation time 337054850000 ps
CPU time 847.86 seconds
Started Jul 09 04:51:15 PM PDT 24
Finished Jul 09 05:25:32 PM PDT 24
Peak memory 160620 kb
Host smart-a5efc308-8aa8-47b9-8014-6e4214e15372
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1899042579 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.1899042579
Directory /workspace/12.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.4184670016
Short name T76
Test name
Test status
Simulation time 336744770000 ps
CPU time 665.9 seconds
Started Jul 09 04:51:38 PM PDT 24
Finished Jul 09 05:18:38 PM PDT 24
Peak memory 160708 kb
Host smart-facf92a1-36b9-4f4b-8d88-147fc66253c5
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4184670016 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.4184670016
Directory /workspace/13.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.2364103267
Short name T93
Test name
Test status
Simulation time 336446030000 ps
CPU time 768.85 seconds
Started Jul 09 04:51:11 PM PDT 24
Finished Jul 09 05:22:06 PM PDT 24
Peak memory 160728 kb
Host smart-96029189-7846-45d9-9772-701b74f12d25
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2364103267 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.2364103267
Directory /workspace/14.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.2422593230
Short name T78
Test name
Test status
Simulation time 336878290000 ps
CPU time 895.1 seconds
Started Jul 09 04:51:11 PM PDT 24
Finished Jul 09 05:27:29 PM PDT 24
Peak memory 160700 kb
Host smart-d8f05bf1-d530-4c87-91ed-cbb0c820cc26
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2422593230 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.2422593230
Directory /workspace/15.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.1215958075
Short name T90
Test name
Test status
Simulation time 336950450000 ps
CPU time 802.71 seconds
Started Jul 09 04:51:20 PM PDT 24
Finished Jul 09 05:23:29 PM PDT 24
Peak memory 160804 kb
Host smart-bf3cfe37-b005-487e-bff8-84de96c005b6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1215958075 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.1215958075
Directory /workspace/16.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.1684102186
Short name T16
Test name
Test status
Simulation time 336770730000 ps
CPU time 853.24 seconds
Started Jul 09 04:51:11 PM PDT 24
Finished Jul 09 05:25:25 PM PDT 24
Peak memory 160688 kb
Host smart-18e30738-f214-41c5-bc69-44c127732d9e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1684102186 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.1684102186
Directory /workspace/17.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.2689759207
Short name T106
Test name
Test status
Simulation time 336984590000 ps
CPU time 810.44 seconds
Started Jul 09 04:51:18 PM PDT 24
Finished Jul 09 05:23:56 PM PDT 24
Peak memory 160708 kb
Host smart-63b3f8bd-769f-418e-8fc6-2464750216b0
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2689759207 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.2689759207
Directory /workspace/18.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2799350403
Short name T20
Test name
Test status
Simulation time 337041810000 ps
CPU time 804.84 seconds
Started Jul 09 04:51:16 PM PDT 24
Finished Jul 09 05:23:26 PM PDT 24
Peak memory 160808 kb
Host smart-b96f38da-5152-4b50-b406-4c0cacc42e3d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2799350403 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.2799350403
Directory /workspace/19.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.1660587441
Short name T72
Test name
Test status
Simulation time 336617210000 ps
CPU time 878.15 seconds
Started Jul 09 04:51:27 PM PDT 24
Finished Jul 09 05:27:22 PM PDT 24
Peak memory 160692 kb
Host smart-d6d9cdb8-aae7-4023-a996-c8be5e55e033
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1660587441 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.1660587441
Directory /workspace/2.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.1803315096
Short name T71
Test name
Test status
Simulation time 336589390000 ps
CPU time 709.98 seconds
Started Jul 09 04:51:23 PM PDT 24
Finished Jul 09 05:20:11 PM PDT 24
Peak memory 160804 kb
Host smart-ff16d4fb-3c78-4f1b-bc9c-e527e93486af
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1803315096 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.1803315096
Directory /workspace/20.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.4087362520
Short name T92
Test name
Test status
Simulation time 336801790000 ps
CPU time 824.76 seconds
Started Jul 09 04:51:14 PM PDT 24
Finished Jul 09 05:24:15 PM PDT 24
Peak memory 160728 kb
Host smart-19451ea3-88ff-4b11-8fde-8e1cb145ba8b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4087362520 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.4087362520
Directory /workspace/21.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.1360904649
Short name T97
Test name
Test status
Simulation time 336767630000 ps
CPU time 831.74 seconds
Started Jul 09 04:51:16 PM PDT 24
Finished Jul 09 05:24:53 PM PDT 24
Peak memory 160688 kb
Host smart-dd2baa15-1a1d-481f-9600-9845853ec078
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1360904649 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.1360904649
Directory /workspace/22.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.710811898
Short name T99
Test name
Test status
Simulation time 336432410000 ps
CPU time 665.74 seconds
Started Jul 09 04:51:38 PM PDT 24
Finished Jul 09 05:18:29 PM PDT 24
Peak memory 160720 kb
Host smart-e928a3e1-1921-4a6f-a6a3-35d2d6acb1be
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=710811898 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.710811898
Directory /workspace/23.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.2951286357
Short name T102
Test name
Test status
Simulation time 336335630000 ps
CPU time 727.67 seconds
Started Jul 09 04:51:37 PM PDT 24
Finished Jul 09 05:20:47 PM PDT 24
Peak memory 160728 kb
Host smart-58c66d13-5022-44be-bce8-4c83b20f049b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2951286357 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.2951286357
Directory /workspace/24.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.3255709742
Short name T18
Test name
Test status
Simulation time 336875830000 ps
CPU time 906.52 seconds
Started Jul 09 04:51:14 PM PDT 24
Finished Jul 09 05:27:25 PM PDT 24
Peak memory 160684 kb
Host smart-8d0c1ceb-6feb-4489-abac-57abdbb1a65a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3255709742 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.3255709742
Directory /workspace/25.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1875089508
Short name T17
Test name
Test status
Simulation time 336341330000 ps
CPU time 738.3 seconds
Started Jul 09 04:51:14 PM PDT 24
Finished Jul 09 05:21:15 PM PDT 24
Peak memory 160708 kb
Host smart-c68c4430-7f67-4b5b-84ef-975f9337b1b6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1875089508 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.1875089508
Directory /workspace/26.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.1257383024
Short name T81
Test name
Test status
Simulation time 336428850000 ps
CPU time 848.77 seconds
Started Jul 09 04:51:14 PM PDT 24
Finished Jul 09 05:25:31 PM PDT 24
Peak memory 160620 kb
Host smart-5f277301-5fae-4f40-b925-35b1b3c74210
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1257383024 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.1257383024
Directory /workspace/27.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.3101590852
Short name T104
Test name
Test status
Simulation time 336784810000 ps
CPU time 727.32 seconds
Started Jul 09 04:51:44 PM PDT 24
Finished Jul 09 05:21:07 PM PDT 24
Peak memory 160696 kb
Host smart-866bd937-fba9-44a4-92a2-9208912aa258
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3101590852 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.3101590852
Directory /workspace/28.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.4281149239
Short name T80
Test name
Test status
Simulation time 336602230000 ps
CPU time 764.23 seconds
Started Jul 09 04:51:16 PM PDT 24
Finished Jul 09 05:21:54 PM PDT 24
Peak memory 160808 kb
Host smart-ff690cc6-8e1e-4d8b-9750-dbdde3586275
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4281149239 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.4281149239
Directory /workspace/29.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.1296863631
Short name T103
Test name
Test status
Simulation time 336702650000 ps
CPU time 730.33 seconds
Started Jul 09 04:51:22 PM PDT 24
Finished Jul 09 05:20:38 PM PDT 24
Peak memory 160684 kb
Host smart-8add024e-eacf-468c-bf50-8211d2c61d88
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1296863631 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.1296863631
Directory /workspace/3.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3404745507
Short name T96
Test name
Test status
Simulation time 336997310000 ps
CPU time 821.8 seconds
Started Jul 09 04:51:24 PM PDT 24
Finished Jul 09 05:24:23 PM PDT 24
Peak memory 160712 kb
Host smart-8820b5db-18f8-4052-825a-bfa4dfd72673
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3404745507 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.3404745507
Directory /workspace/30.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.2319573673
Short name T89
Test name
Test status
Simulation time 336566670000 ps
CPU time 854.89 seconds
Started Jul 09 04:51:19 PM PDT 24
Finished Jul 09 05:25:46 PM PDT 24
Peak memory 160676 kb
Host smart-e4a8e895-936a-4361-9a9e-7aa7c0f3ff9a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2319573673 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.2319573673
Directory /workspace/31.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.1495780805
Short name T87
Test name
Test status
Simulation time 336676490000 ps
CPU time 815.21 seconds
Started Jul 09 04:51:16 PM PDT 24
Finished Jul 09 05:24:21 PM PDT 24
Peak memory 160920 kb
Host smart-74b0ed3c-bb35-4017-831e-a68cd5c8c702
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1495780805 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.1495780805
Directory /workspace/32.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.3919996759
Short name T79
Test name
Test status
Simulation time 336620690000 ps
CPU time 782.94 seconds
Started Jul 09 04:51:20 PM PDT 24
Finished Jul 09 05:22:51 PM PDT 24
Peak memory 160704 kb
Host smart-cfc883f2-50d1-41e5-9a96-06375dd99934
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3919996759 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.3919996759
Directory /workspace/33.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.2477515606
Short name T74
Test name
Test status
Simulation time 336958010000 ps
CPU time 921.76 seconds
Started Jul 09 04:51:30 PM PDT 24
Finished Jul 09 05:28:56 PM PDT 24
Peak memory 160812 kb
Host smart-c7166ba7-ce86-426a-8ac7-82a39bc9f4c8
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2477515606 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.2477515606
Directory /workspace/34.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.669765869
Short name T5
Test name
Test status
Simulation time 336473650000 ps
CPU time 847.59 seconds
Started Jul 09 04:51:41 PM PDT 24
Finished Jul 09 05:25:44 PM PDT 24
Peak memory 160676 kb
Host smart-ecd8f9b6-bd6f-456b-b3f7-71bc5f0b0313
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=669765869 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.669765869
Directory /workspace/35.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.4157007815
Short name T91
Test name
Test status
Simulation time 336926590000 ps
CPU time 815.91 seconds
Started Jul 09 04:51:32 PM PDT 24
Finished Jul 09 05:24:26 PM PDT 24
Peak memory 160728 kb
Host smart-fbf2411f-3333-4d2c-bebc-5872f26ca391
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4157007815 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.4157007815
Directory /workspace/36.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.1101962631
Short name T108
Test name
Test status
Simulation time 336492130000 ps
CPU time 785.35 seconds
Started Jul 09 04:51:15 PM PDT 24
Finished Jul 09 05:22:54 PM PDT 24
Peak memory 160700 kb
Host smart-aad47647-9fa5-4ea3-ab7c-496de693e3a1
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1101962631 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.1101962631
Directory /workspace/37.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.591941809
Short name T86
Test name
Test status
Simulation time 336552690000 ps
CPU time 817.4 seconds
Started Jul 09 04:51:28 PM PDT 24
Finished Jul 09 05:24:27 PM PDT 24
Peak memory 160720 kb
Host smart-27842bc6-f4b7-438e-a046-cc28ab2f00bf
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=591941809 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.591941809
Directory /workspace/38.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.2587575720
Short name T110
Test name
Test status
Simulation time 337027310000 ps
CPU time 841.96 seconds
Started Jul 09 04:51:16 PM PDT 24
Finished Jul 09 05:25:18 PM PDT 24
Peak memory 160688 kb
Host smart-33ec1426-bc85-4169-b047-a6fff1703084
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2587575720 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.2587575720
Directory /workspace/39.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.2988891353
Short name T109
Test name
Test status
Simulation time 336688350000 ps
CPU time 735.01 seconds
Started Jul 09 04:51:09 PM PDT 24
Finished Jul 09 05:20:40 PM PDT 24
Peak memory 160700 kb
Host smart-2282a094-3bfb-4960-a295-e0591bdf0ec5
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2988891353 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.2988891353
Directory /workspace/4.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.161396693
Short name T84
Test name
Test status
Simulation time 336550310000 ps
CPU time 791.43 seconds
Started Jul 09 04:51:19 PM PDT 24
Finished Jul 09 05:23:03 PM PDT 24
Peak memory 160704 kb
Host smart-99813cdc-2dcd-4703-aa38-4b7833486cb6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=161396693 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.161396693
Directory /workspace/40.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.329783303
Short name T19
Test name
Test status
Simulation time 336715210000 ps
CPU time 811.68 seconds
Started Jul 09 04:51:15 PM PDT 24
Finished Jul 09 05:23:59 PM PDT 24
Peak memory 160768 kb
Host smart-41a59360-a518-44b9-8066-882e26bff121
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=329783303 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.329783303
Directory /workspace/41.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.1071314741
Short name T88
Test name
Test status
Simulation time 337061970000 ps
CPU time 913.99 seconds
Started Jul 09 04:51:26 PM PDT 24
Finished Jul 09 05:28:39 PM PDT 24
Peak memory 160812 kb
Host smart-f7d47d58-a364-457e-9fd1-7462d7b1241d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1071314741 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.1071314741
Directory /workspace/42.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.908313667
Short name T15
Test name
Test status
Simulation time 336969790000 ps
CPU time 928.32 seconds
Started Jul 09 04:51:20 PM PDT 24
Finished Jul 09 05:28:56 PM PDT 24
Peak memory 160808 kb
Host smart-599e939f-4224-432a-ab40-3e412a0d5a3b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=908313667 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.908313667
Directory /workspace/43.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.3417424021
Short name T101
Test name
Test status
Simulation time 336570210000 ps
CPU time 885.78 seconds
Started Jul 09 04:51:24 PM PDT 24
Finished Jul 09 05:27:51 PM PDT 24
Peak memory 160624 kb
Host smart-1bd37f9f-cabb-4a46-8633-1a12df6e82fe
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3417424021 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.3417424021
Directory /workspace/44.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.3110431101
Short name T14
Test name
Test status
Simulation time 336704170000 ps
CPU time 787.5 seconds
Started Jul 09 04:51:17 PM PDT 24
Finished Jul 09 05:22:49 PM PDT 24
Peak memory 160680 kb
Host smart-6004865c-f373-4221-9df7-bba0d7998a85
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3110431101 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.3110431101
Directory /workspace/45.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.3275477982
Short name T94
Test name
Test status
Simulation time 336312130000 ps
CPU time 824.07 seconds
Started Jul 09 04:51:15 PM PDT 24
Finished Jul 09 05:24:08 PM PDT 24
Peak memory 160704 kb
Host smart-c0960447-fe38-489c-962c-a6e56fac554f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3275477982 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.3275477982
Directory /workspace/46.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.1247649777
Short name T6
Test name
Test status
Simulation time 336598430000 ps
CPU time 833.72 seconds
Started Jul 09 04:51:17 PM PDT 24
Finished Jul 09 05:25:31 PM PDT 24
Peak memory 160728 kb
Host smart-06429cfe-3e6d-4b9a-8bc0-9764394d3ed9
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1247649777 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.1247649777
Directory /workspace/47.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.2454811276
Short name T100
Test name
Test status
Simulation time 336582930000 ps
CPU time 817.23 seconds
Started Jul 09 04:51:27 PM PDT 24
Finished Jul 09 05:24:16 PM PDT 24
Peak memory 160656 kb
Host smart-b639116b-7982-4f8f-a32c-4a471e7e343f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2454811276 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.2454811276
Directory /workspace/48.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.2857720125
Short name T83
Test name
Test status
Simulation time 336827370000 ps
CPU time 778.93 seconds
Started Jul 09 04:51:28 PM PDT 24
Finished Jul 09 05:22:53 PM PDT 24
Peak memory 160712 kb
Host smart-47263cf5-fb55-4f08-9087-292629b79054
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2857720125 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.2857720125
Directory /workspace/49.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.2707953701
Short name T98
Test name
Test status
Simulation time 337046890000 ps
CPU time 864.12 seconds
Started Jul 09 04:51:22 PM PDT 24
Finished Jul 09 05:26:57 PM PDT 24
Peak memory 160656 kb
Host smart-f7751576-caf1-497d-9ed4-197683840a74
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2707953701 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.2707953701
Directory /workspace/5.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.366769517
Short name T77
Test name
Test status
Simulation time 336851770000 ps
CPU time 762.24 seconds
Started Jul 09 04:51:13 PM PDT 24
Finished Jul 09 05:21:51 PM PDT 24
Peak memory 160792 kb
Host smart-c789ea31-a412-4068-90b7-c6e28b4ea43b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=366769517 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.366769517
Directory /workspace/6.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.589173750
Short name T75
Test name
Test status
Simulation time 337133970000 ps
CPU time 814.57 seconds
Started Jul 09 04:51:10 PM PDT 24
Finished Jul 09 05:23:58 PM PDT 24
Peak memory 160692 kb
Host smart-78d0db1f-f81d-4f38-964c-42ad8a87935b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=589173750 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.589173750
Directory /workspace/7.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.2168606689
Short name T73
Test name
Test status
Simulation time 336319850000 ps
CPU time 782.99 seconds
Started Jul 09 04:51:11 PM PDT 24
Finished Jul 09 05:22:42 PM PDT 24
Peak memory 160772 kb
Host smart-5dbdf3dc-f009-4679-a35b-9f6ab486a84c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2168606689 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.2168606689
Directory /workspace/8.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.683748151
Short name T105
Test name
Test status
Simulation time 336413850000 ps
CPU time 859.6 seconds
Started Jul 09 04:51:23 PM PDT 24
Finished Jul 09 05:26:53 PM PDT 24
Peak memory 160648 kb
Host smart-98e7f59c-60dd-4b9f-8a6c-6c5232777053
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=683748151 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.683748151
Directory /workspace/9.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.565117787
Short name T168
Test name
Test status
Simulation time 336402030000 ps
CPU time 579.69 seconds
Started Jul 09 04:51:37 PM PDT 24
Finished Jul 09 05:16:28 PM PDT 24
Peak memory 160672 kb
Host smart-691f4b5b-96ae-4602-bc8b-3a96d9a54066
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=565117787 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.565117787
Directory /workspace/0.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.449735738
Short name T178
Test name
Test status
Simulation time 336712370000 ps
CPU time 836.94 seconds
Started Jul 09 04:51:37 PM PDT 24
Finished Jul 09 05:25:11 PM PDT 24
Peak memory 160792 kb
Host smart-84fa45cf-cd44-4957-92b0-88304229e481
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=449735738 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.449735738
Directory /workspace/1.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.3867604488
Short name T169
Test name
Test status
Simulation time 336897850000 ps
CPU time 899.62 seconds
Started Jul 09 04:51:45 PM PDT 24
Finished Jul 09 05:27:40 PM PDT 24
Peak memory 160696 kb
Host smart-948d64be-9ba5-4de4-a496-9bf429e02816
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3867604488 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.3867604488
Directory /workspace/10.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.2371371761
Short name T29
Test name
Test status
Simulation time 336503010000 ps
CPU time 796.05 seconds
Started Jul 09 04:51:40 PM PDT 24
Finished Jul 09 05:23:43 PM PDT 24
Peak memory 160716 kb
Host smart-8d4f3f79-af9f-48e5-9b19-746d6b651524
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2371371761 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.2371371761
Directory /workspace/12.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.3893638756
Short name T193
Test name
Test status
Simulation time 336391470000 ps
CPU time 723.38 seconds
Started Jul 09 04:51:46 PM PDT 24
Finished Jul 09 05:21:27 PM PDT 24
Peak memory 160692 kb
Host smart-b4ea648f-b70d-490f-bd7f-6acd7fc5c8e7
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3893638756 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.3893638756
Directory /workspace/13.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.1498417230
Short name T25
Test name
Test status
Simulation time 336905630000 ps
CPU time 755.79 seconds
Started Jul 09 04:51:43 PM PDT 24
Finished Jul 09 05:22:27 PM PDT 24
Peak memory 160692 kb
Host smart-fc846c7f-2c32-4bb9-ae42-f3f8deea922b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1498417230 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.1498417230
Directory /workspace/14.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.3421499663
Short name T190
Test name
Test status
Simulation time 336721450000 ps
CPU time 723.3 seconds
Started Jul 09 04:51:51 PM PDT 24
Finished Jul 09 05:21:39 PM PDT 24
Peak memory 160680 kb
Host smart-b43f1bf9-d9ca-41be-a623-2db11cf4f1a6
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3421499663 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.3421499663
Directory /workspace/15.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.2967461619
Short name T172
Test name
Test status
Simulation time 336458670000 ps
CPU time 816.41 seconds
Started Jul 09 04:51:44 PM PDT 24
Finished Jul 09 05:25:18 PM PDT 24
Peak memory 160732 kb
Host smart-70a0641c-4e80-465f-bcdc-8ad0453a0786
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2967461619 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.2967461619
Directory /workspace/16.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.496302274
Short name T27
Test name
Test status
Simulation time 336309450000 ps
CPU time 798.78 seconds
Started Jul 09 04:51:39 PM PDT 24
Finished Jul 09 05:23:55 PM PDT 24
Peak memory 160704 kb
Host smart-fe5c21cb-b500-4891-9bdd-8a926fca60a9
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=496302274 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.496302274
Directory /workspace/17.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.2689917561
Short name T191
Test name
Test status
Simulation time 336820430000 ps
CPU time 758.34 seconds
Started Jul 09 04:51:35 PM PDT 24
Finished Jul 09 05:22:12 PM PDT 24
Peak memory 160812 kb
Host smart-fec63bee-208d-4907-be16-b771ebcc2caf
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2689917561 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.2689917561
Directory /workspace/18.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.1568350276
Short name T184
Test name
Test status
Simulation time 336519470000 ps
CPU time 878.97 seconds
Started Jul 09 04:51:49 PM PDT 24
Finished Jul 09 05:28:03 PM PDT 24
Peak memory 160668 kb
Host smart-d8695917-a95b-4839-ac95-537fa6f9ddc8
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1568350276 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.1568350276
Directory /workspace/19.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.2787498995
Short name T186
Test name
Test status
Simulation time 336847850000 ps
CPU time 910.86 seconds
Started Jul 09 04:51:39 PM PDT 24
Finished Jul 09 05:27:53 PM PDT 24
Peak memory 160724 kb
Host smart-dc4883fb-5947-4b55-94a3-ce93081ef927
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2787498995 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.2787498995
Directory /workspace/2.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.935736970
Short name T174
Test name
Test status
Simulation time 336318270000 ps
CPU time 772.52 seconds
Started Jul 09 04:51:47 PM PDT 24
Finished Jul 09 05:23:09 PM PDT 24
Peak memory 160684 kb
Host smart-38b0132b-5526-440c-8592-35a1578afe72
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=935736970 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.935736970
Directory /workspace/20.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.2950677451
Short name T21
Test name
Test status
Simulation time 336765610000 ps
CPU time 891.98 seconds
Started Jul 09 04:51:38 PM PDT 24
Finished Jul 09 05:28:26 PM PDT 24
Peak memory 160628 kb
Host smart-fbb6eb02-9d5d-4018-bf1c-fdf245cd71a6
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2950677451 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.2950677451
Directory /workspace/21.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.2283604247
Short name T26
Test name
Test status
Simulation time 336882850000 ps
CPU time 834.23 seconds
Started Jul 09 04:51:44 PM PDT 24
Finished Jul 09 05:26:18 PM PDT 24
Peak memory 160704 kb
Host smart-7890c30c-3a87-4e0d-8731-ac9096820d08
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2283604247 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.2283604247
Directory /workspace/22.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.1707981819
Short name T185
Test name
Test status
Simulation time 336454950000 ps
CPU time 843.52 seconds
Started Jul 09 04:51:31 PM PDT 24
Finished Jul 09 05:25:38 PM PDT 24
Peak memory 160680 kb
Host smart-9c3ddbdd-00b1-4e62-a927-91f0dc05c51e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1707981819 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.1707981819
Directory /workspace/23.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.3672389662
Short name T196
Test name
Test status
Simulation time 336316310000 ps
CPU time 891.62 seconds
Started Jul 09 04:51:41 PM PDT 24
Finished Jul 09 05:28:10 PM PDT 24
Peak memory 160816 kb
Host smart-88adcc81-372c-4839-832e-0d64f9410aaa
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3672389662 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.3672389662
Directory /workspace/24.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.2435065105
Short name T187
Test name
Test status
Simulation time 336933670000 ps
CPU time 850.9 seconds
Started Jul 09 04:51:53 PM PDT 24
Finished Jul 09 05:26:47 PM PDT 24
Peak memory 160704 kb
Host smart-d3921d82-4960-4e81-8156-46802652bad2
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2435065105 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.2435065105
Directory /workspace/25.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.1520121355
Short name T182
Test name
Test status
Simulation time 336673950000 ps
CPU time 730.45 seconds
Started Jul 09 04:51:44 PM PDT 24
Finished Jul 09 05:21:34 PM PDT 24
Peak memory 160676 kb
Host smart-ac20ef71-c96e-4021-94c8-f47b1d64e198
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1520121355 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.1520121355
Directory /workspace/26.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.3774937561
Short name T176
Test name
Test status
Simulation time 336615430000 ps
CPU time 725.08 seconds
Started Jul 09 04:51:46 PM PDT 24
Finished Jul 09 05:21:38 PM PDT 24
Peak memory 160692 kb
Host smart-a5086245-ab9b-4228-bdfa-9a8497089587
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3774937561 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.3774937561
Directory /workspace/27.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.3890910562
Short name T163
Test name
Test status
Simulation time 336701190000 ps
CPU time 839.17 seconds
Started Jul 09 04:51:38 PM PDT 24
Finished Jul 09 05:25:57 PM PDT 24
Peak memory 160680 kb
Host smart-c40fb0c0-017a-410f-8d1e-e299fe84031e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3890910562 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.3890910562
Directory /workspace/28.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.3530278954
Short name T199
Test name
Test status
Simulation time 336608470000 ps
CPU time 763.45 seconds
Started Jul 09 04:51:31 PM PDT 24
Finished Jul 09 05:22:34 PM PDT 24
Peak memory 160676 kb
Host smart-ba10cb74-0baa-454f-bdf4-55fe1da24885
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3530278954 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.3530278954
Directory /workspace/29.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.770081197
Short name T194
Test name
Test status
Simulation time 337113630000 ps
CPU time 840.86 seconds
Started Jul 09 04:51:39 PM PDT 24
Finished Jul 09 05:26:26 PM PDT 24
Peak memory 160612 kb
Host smart-585ac55f-9ee6-4c2f-a0b8-fb3fd19681a6
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=770081197 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.770081197
Directory /workspace/3.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.1357924518
Short name T179
Test name
Test status
Simulation time 336363150000 ps
CPU time 819.1 seconds
Started Jul 09 04:51:41 PM PDT 24
Finished Jul 09 05:25:02 PM PDT 24
Peak memory 160828 kb
Host smart-683ad9f0-cc97-418e-bfdc-a61dc3aadf0e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1357924518 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.1357924518
Directory /workspace/30.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.704613010
Short name T165
Test name
Test status
Simulation time 336595350000 ps
CPU time 824.09 seconds
Started Jul 09 04:51:40 PM PDT 24
Finished Jul 09 05:25:03 PM PDT 24
Peak memory 160824 kb
Host smart-64bc2cfc-26a8-4afd-9095-3f3834e76d80
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=704613010 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.704613010
Directory /workspace/31.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.555133635
Short name T188
Test name
Test status
Simulation time 336473390000 ps
CPU time 834.8 seconds
Started Jul 09 04:51:44 PM PDT 24
Finished Jul 09 05:26:10 PM PDT 24
Peak memory 160672 kb
Host smart-f4c9b2f4-bd5b-481e-be8a-7869ef534f4e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=555133635 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.555133635
Directory /workspace/32.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.3508302259
Short name T177
Test name
Test status
Simulation time 336789410000 ps
CPU time 693.77 seconds
Started Jul 09 04:51:45 PM PDT 24
Finished Jul 09 05:19:53 PM PDT 24
Peak memory 160664 kb
Host smart-e657ab38-be6c-4ace-991f-07752aa0a14b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3508302259 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.3508302259
Directory /workspace/33.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.3403167569
Short name T183
Test name
Test status
Simulation time 336396630000 ps
CPU time 747 seconds
Started Jul 09 04:51:40 PM PDT 24
Finished Jul 09 05:21:46 PM PDT 24
Peak memory 160700 kb
Host smart-78a32a97-ef79-4eab-ae5f-45332fbc9277
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3403167569 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.3403167569
Directory /workspace/34.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.3323769886
Short name T189
Test name
Test status
Simulation time 336782690000 ps
CPU time 821.81 seconds
Started Jul 09 04:51:42 PM PDT 24
Finished Jul 09 05:24:39 PM PDT 24
Peak memory 160768 kb
Host smart-918c5e66-b3ad-4224-81df-90e4e56d72fa
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3323769886 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.3323769886
Directory /workspace/35.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.174802145
Short name T164
Test name
Test status
Simulation time 336382050000 ps
CPU time 752.23 seconds
Started Jul 09 04:51:46 PM PDT 24
Finished Jul 09 05:22:33 PM PDT 24
Peak memory 160684 kb
Host smart-bd742ba8-39de-4228-99fa-33ec26a68b25
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=174802145 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.174802145
Directory /workspace/36.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.1715576070
Short name T30
Test name
Test status
Simulation time 336561390000 ps
CPU time 707.46 seconds
Started Jul 09 04:51:44 PM PDT 24
Finished Jul 09 05:20:41 PM PDT 24
Peak memory 160712 kb
Host smart-50b11e13-d44b-42c1-a41c-7a8dcb842d6d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1715576070 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.1715576070
Directory /workspace/37.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.1118105277
Short name T197
Test name
Test status
Simulation time 336948470000 ps
CPU time 755.93 seconds
Started Jul 09 04:51:41 PM PDT 24
Finished Jul 09 05:22:22 PM PDT 24
Peak memory 160732 kb
Host smart-3ad9da12-a8e8-491c-9795-469a337d9edb
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1118105277 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.1118105277
Directory /workspace/38.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.4125554235
Short name T175
Test name
Test status
Simulation time 336775290000 ps
CPU time 843.07 seconds
Started Jul 09 04:51:43 PM PDT 24
Finished Jul 09 05:26:21 PM PDT 24
Peak memory 160680 kb
Host smart-521fd222-ed6b-47e6-8ad2-207f759a2bda
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4125554235 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.4125554235
Directory /workspace/39.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.3937434236
Short name T167
Test name
Test status
Simulation time 336939930000 ps
CPU time 808.25 seconds
Started Jul 09 04:51:42 PM PDT 24
Finished Jul 09 05:24:36 PM PDT 24
Peak memory 160916 kb
Host smart-e01b0dc7-ff2a-4190-9958-080f3799f4d4
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3937434236 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.3937434236
Directory /workspace/4.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.3482443394
Short name T22
Test name
Test status
Simulation time 336599610000 ps
CPU time 895.59 seconds
Started Jul 09 04:51:48 PM PDT 24
Finished Jul 09 05:27:48 PM PDT 24
Peak memory 160688 kb
Host smart-56ca4ca2-e662-4523-9fb0-d6e15dfdef6c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3482443394 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.3482443394
Directory /workspace/40.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.1224868568
Short name T23
Test name
Test status
Simulation time 337161830000 ps
CPU time 862.03 seconds
Started Jul 09 04:51:45 PM PDT 24
Finished Jul 09 05:26:23 PM PDT 24
Peak memory 160696 kb
Host smart-4e38fee8-81fc-4a1b-9411-5111bd147f63
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1224868568 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.1224868568
Directory /workspace/41.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.3644920631
Short name T170
Test name
Test status
Simulation time 336527050000 ps
CPU time 777.21 seconds
Started Jul 09 04:51:40 PM PDT 24
Finished Jul 09 05:23:08 PM PDT 24
Peak memory 160732 kb
Host smart-1bc51c35-cc2f-489b-b5d3-87933353fcb0
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3644920631 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.3644920631
Directory /workspace/42.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.3358053136
Short name T173
Test name
Test status
Simulation time 336864410000 ps
CPU time 506.59 seconds
Started Jul 09 04:51:44 PM PDT 24
Finished Jul 09 05:13:29 PM PDT 24
Peak memory 160812 kb
Host smart-1ab16100-93b4-4d62-b002-4967d97c422c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3358053136 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.3358053136
Directory /workspace/43.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.2582769044
Short name T161
Test name
Test status
Simulation time 337021710000 ps
CPU time 814.76 seconds
Started Jul 09 04:51:43 PM PDT 24
Finished Jul 09 05:25:19 PM PDT 24
Peak memory 160732 kb
Host smart-f9171bdc-6f23-4abf-b8f7-b014d173606c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2582769044 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.2582769044
Directory /workspace/44.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.2595682910
Short name T181
Test name
Test status
Simulation time 336842610000 ps
CPU time 703.23 seconds
Started Jul 09 04:52:03 PM PDT 24
Finished Jul 09 05:20:39 PM PDT 24
Peak memory 160732 kb
Host smart-a6c16769-0f2e-4928-b073-52caa04073b8
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2595682910 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.2595682910
Directory /workspace/45.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.1315323430
Short name T198
Test name
Test status
Simulation time 336990750000 ps
CPU time 808.85 seconds
Started Jul 09 04:51:51 PM PDT 24
Finished Jul 09 05:24:26 PM PDT 24
Peak memory 160672 kb
Host smart-8f406e09-b264-4c21-a212-d716e80cd5bb
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1315323430 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.1315323430
Directory /workspace/46.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.3541178297
Short name T200
Test name
Test status
Simulation time 336679330000 ps
CPU time 631.3 seconds
Started Jul 09 04:51:47 PM PDT 24
Finished Jul 09 05:17:31 PM PDT 24
Peak memory 160732 kb
Host smart-b48a3367-223f-4ff0-af76-8b785f4ac317
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3541178297 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.3541178297
Directory /workspace/47.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.2816920918
Short name T166
Test name
Test status
Simulation time 336747890000 ps
CPU time 807.6 seconds
Started Jul 09 04:51:39 PM PDT 24
Finished Jul 09 05:24:14 PM PDT 24
Peak memory 160712 kb
Host smart-72597da5-03bb-4f5f-ac4b-3475a84531e7
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2816920918 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.2816920918
Directory /workspace/48.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.275638033
Short name T192
Test name
Test status
Simulation time 336496370000 ps
CPU time 751.07 seconds
Started Jul 09 04:51:41 PM PDT 24
Finished Jul 09 05:21:44 PM PDT 24
Peak memory 160724 kb
Host smart-53400335-416e-4ab8-b5c6-3b46c902bd3e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=275638033 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.275638033
Directory /workspace/49.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.4040794353
Short name T195
Test name
Test status
Simulation time 337091630000 ps
CPU time 751.09 seconds
Started Jul 09 04:51:41 PM PDT 24
Finished Jul 09 05:21:54 PM PDT 24
Peak memory 160696 kb
Host smart-b6b36bcc-4de4-4504-a840-636fdb33c479
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4040794353 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.4040794353
Directory /workspace/5.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.447303355
Short name T171
Test name
Test status
Simulation time 337018550000 ps
CPU time 802.04 seconds
Started Jul 09 04:51:44 PM PDT 24
Finished Jul 09 05:24:07 PM PDT 24
Peak memory 160724 kb
Host smart-2b2270b9-068a-41f3-b7fe-fb341802cc1f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=447303355 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.447303355
Directory /workspace/6.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.657434840
Short name T162
Test name
Test status
Simulation time 336621410000 ps
CPU time 810.47 seconds
Started Jul 09 04:51:43 PM PDT 24
Finished Jul 09 05:25:00 PM PDT 24
Peak memory 160716 kb
Host smart-497a8f7c-f545-468f-92e1-4a81a55a89e9
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=657434840 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.657434840
Directory /workspace/7.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.248563878
Short name T24
Test name
Test status
Simulation time 336665850000 ps
CPU time 761.52 seconds
Started Jul 09 04:51:42 PM PDT 24
Finished Jul 09 05:22:28 PM PDT 24
Peak memory 160720 kb
Host smart-7ccf1409-29a5-4a57-aa28-d846c96c9921
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=248563878 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.248563878
Directory /workspace/8.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.2697625952
Short name T180
Test name
Test status
Simulation time 336710270000 ps
CPU time 761.64 seconds
Started Jul 09 04:51:44 PM PDT 24
Finished Jul 09 05:22:31 PM PDT 24
Peak memory 160664 kb
Host smart-29c16076-2f1e-4d4e-a4cc-23881fc98196
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2697625952 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.2697625952
Directory /workspace/9.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.2812936077
Short name T135
Test name
Test status
Simulation time 1464310000 ps
CPU time 3.65 seconds
Started Jul 09 04:51:36 PM PDT 24
Finished Jul 09 04:51:44 PM PDT 24
Peak memory 164836 kb
Host smart-71e3714b-4c21-4e79-a211-800ac5ff9f23
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2812936077 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.2812936077
Directory /workspace/0.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.3569081917
Short name T137
Test name
Test status
Simulation time 1601030000 ps
CPU time 4.37 seconds
Started Jul 09 04:51:28 PM PDT 24
Finished Jul 09 04:51:38 PM PDT 24
Peak memory 164876 kb
Host smart-610f8a56-eb73-48fe-94cb-10456c72fb24
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3569081917 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.3569081917
Directory /workspace/1.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.4205542699
Short name T157
Test name
Test status
Simulation time 1506410000 ps
CPU time 4.49 seconds
Started Jul 09 04:51:34 PM PDT 24
Finished Jul 09 04:51:44 PM PDT 24
Peak memory 164876 kb
Host smart-b05c119a-9b73-4088-81ec-fa286ac80eab
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4205542699 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.4205542699
Directory /workspace/10.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.2306616578
Short name T124
Test name
Test status
Simulation time 1501030000 ps
CPU time 4.05 seconds
Started Jul 09 04:51:38 PM PDT 24
Finished Jul 09 04:51:48 PM PDT 24
Peak memory 164820 kb
Host smart-22286adf-aeb9-43fc-afee-aaad0cdc2dc8
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2306616578 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.2306616578
Directory /workspace/11.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.2083322625
Short name T118
Test name
Test status
Simulation time 1453310000 ps
CPU time 3.87 seconds
Started Jul 09 04:51:48 PM PDT 24
Finished Jul 09 04:51:58 PM PDT 24
Peak memory 164820 kb
Host smart-82c70222-a02f-451b-9aec-cca4f1fecae5
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2083322625 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.2083322625
Directory /workspace/12.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.3904362566
Short name T126
Test name
Test status
Simulation time 1437690000 ps
CPU time 4.37 seconds
Started Jul 09 04:51:41 PM PDT 24
Finished Jul 09 04:51:52 PM PDT 24
Peak memory 164816 kb
Host smart-f0912109-a837-46bc-9450-bd12ee98192d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3904362566 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.3904362566
Directory /workspace/13.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.3593268771
Short name T143
Test name
Test status
Simulation time 1385870000 ps
CPU time 3.6 seconds
Started Jul 09 04:51:37 PM PDT 24
Finished Jul 09 04:51:45 PM PDT 24
Peak memory 164840 kb
Host smart-4c6165ab-1280-4b2a-a951-835c28979ca3
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3593268771 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.3593268771
Directory /workspace/14.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.1472560784
Short name T147
Test name
Test status
Simulation time 1415290000 ps
CPU time 5.02 seconds
Started Jul 09 04:51:33 PM PDT 24
Finished Jul 09 04:51:45 PM PDT 24
Peak memory 164756 kb
Host smart-632687c2-b456-4204-b77d-f1a5e92b58c4
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1472560784 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.1472560784
Directory /workspace/15.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.3339105238
Short name T138
Test name
Test status
Simulation time 1571650000 ps
CPU time 5.02 seconds
Started Jul 09 04:51:40 PM PDT 24
Finished Jul 09 04:51:52 PM PDT 24
Peak memory 164836 kb
Host smart-c7257935-18a3-4822-8dda-daffbac0c126
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3339105238 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.3339105238
Directory /workspace/16.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.2603820077
Short name T112
Test name
Test status
Simulation time 1524730000 ps
CPU time 4.44 seconds
Started Jul 09 04:51:41 PM PDT 24
Finished Jul 09 04:51:52 PM PDT 24
Peak memory 164836 kb
Host smart-03fad251-10c0-405a-859c-5ff15fbb8ef5
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2603820077 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.2603820077
Directory /workspace/17.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.1371270487
Short name T151
Test name
Test status
Simulation time 1425950000 ps
CPU time 4.02 seconds
Started Jul 09 04:51:39 PM PDT 24
Finished Jul 09 04:51:49 PM PDT 24
Peak memory 164816 kb
Host smart-d0ccfcfb-628d-4daf-9305-08a2f4c722d3
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1371270487 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.1371270487
Directory /workspace/18.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.556804388
Short name T158
Test name
Test status
Simulation time 1505330000 ps
CPU time 4.96 seconds
Started Jul 09 04:51:41 PM PDT 24
Finished Jul 09 04:51:53 PM PDT 24
Peak memory 164892 kb
Host smart-a5410be9-02a4-4d8a-a9d8-534720907d46
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=556804388 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.556804388
Directory /workspace/19.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.95714107
Short name T120
Test name
Test status
Simulation time 1502810000 ps
CPU time 3.45 seconds
Started Jul 09 04:51:38 PM PDT 24
Finished Jul 09 04:51:45 PM PDT 24
Peak memory 164772 kb
Host smart-9f83ce10-bf7f-4986-a701-1eecc066ceae
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=95714107 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.95714107
Directory /workspace/2.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.4103402413
Short name T128
Test name
Test status
Simulation time 1537650000 ps
CPU time 4.12 seconds
Started Jul 09 04:51:48 PM PDT 24
Finished Jul 09 04:51:59 PM PDT 24
Peak memory 164824 kb
Host smart-be9a8363-6678-40f4-8e7a-55961b626f52
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4103402413 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.4103402413
Directory /workspace/20.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.4060914841
Short name T134
Test name
Test status
Simulation time 1342490000 ps
CPU time 4.09 seconds
Started Jul 09 04:51:35 PM PDT 24
Finished Jul 09 04:51:44 PM PDT 24
Peak memory 164812 kb
Host smart-f44bc865-b405-4b5a-aa55-50632d3b78d0
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4060914841 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.4060914841
Directory /workspace/21.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.203779751
Short name T111
Test name
Test status
Simulation time 1367590000 ps
CPU time 5 seconds
Started Jul 09 04:51:34 PM PDT 24
Finished Jul 09 04:51:45 PM PDT 24
Peak memory 164768 kb
Host smart-63881eff-4d37-42ff-b9c9-128ffc767861
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=203779751 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.203779751
Directory /workspace/22.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.1369803020
Short name T130
Test name
Test status
Simulation time 1414410000 ps
CPU time 4.34 seconds
Started Jul 09 04:51:43 PM PDT 24
Finished Jul 09 04:51:53 PM PDT 24
Peak memory 164828 kb
Host smart-bbc46568-2225-4850-b2a9-d30583f18cd6
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1369803020 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.1369803020
Directory /workspace/23.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.1452651883
Short name T125
Test name
Test status
Simulation time 1477490000 ps
CPU time 4.78 seconds
Started Jul 09 04:51:43 PM PDT 24
Finished Jul 09 04:51:55 PM PDT 24
Peak memory 164828 kb
Host smart-237d7bb7-5ff1-4c31-a07e-38dd60d3d3b2
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1452651883 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.1452651883
Directory /workspace/24.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.2632636053
Short name T129
Test name
Test status
Simulation time 1582730000 ps
CPU time 4.63 seconds
Started Jul 09 04:51:41 PM PDT 24
Finished Jul 09 04:51:52 PM PDT 24
Peak memory 164812 kb
Host smart-18df887a-50c1-405a-9d00-f5957c174dc0
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2632636053 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.2632636053
Directory /workspace/25.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2019427665
Short name T115
Test name
Test status
Simulation time 1342950000 ps
CPU time 3.27 seconds
Started Jul 09 04:51:32 PM PDT 24
Finished Jul 09 04:51:39 PM PDT 24
Peak memory 164836 kb
Host smart-9382d711-3823-40c4-af77-3ca6e814e631
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2019427665 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.2019427665
Directory /workspace/26.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.3552414955
Short name T145
Test name
Test status
Simulation time 1394630000 ps
CPU time 4.67 seconds
Started Jul 09 04:51:52 PM PDT 24
Finished Jul 09 04:52:02 PM PDT 24
Peak memory 164788 kb
Host smart-77e7709a-e223-4626-82be-544464152d59
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3552414955 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.3552414955
Directory /workspace/27.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.3173791693
Short name T150
Test name
Test status
Simulation time 1464310000 ps
CPU time 3.55 seconds
Started Jul 09 04:51:47 PM PDT 24
Finished Jul 09 04:51:56 PM PDT 24
Peak memory 164836 kb
Host smart-1484ca76-8e8a-496d-b70c-2e94f69d07f5
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3173791693 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.3173791693
Directory /workspace/28.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.963496238
Short name T142
Test name
Test status
Simulation time 1522850000 ps
CPU time 4.33 seconds
Started Jul 09 04:51:45 PM PDT 24
Finished Jul 09 04:51:57 PM PDT 24
Peak memory 164816 kb
Host smart-1843a23e-78a1-4ccf-85bc-2fd139512fa1
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=963496238 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.963496238
Directory /workspace/29.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.1449117267
Short name T131
Test name
Test status
Simulation time 1481470000 ps
CPU time 3.39 seconds
Started Jul 09 04:51:28 PM PDT 24
Finished Jul 09 04:51:36 PM PDT 24
Peak memory 164848 kb
Host smart-246ea380-7367-44ec-a54b-b305498b5f7c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1449117267 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.1449117267
Directory /workspace/3.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.96698626
Short name T144
Test name
Test status
Simulation time 1449810000 ps
CPU time 5.23 seconds
Started Jul 09 04:51:33 PM PDT 24
Finished Jul 09 04:51:45 PM PDT 24
Peak memory 164560 kb
Host smart-ace685cf-13b7-46bc-93ab-827608a64180
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=96698626 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.96698626
Directory /workspace/30.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.1111668882
Short name T133
Test name
Test status
Simulation time 1332710000 ps
CPU time 4.64 seconds
Started Jul 09 04:51:31 PM PDT 24
Finished Jul 09 04:51:41 PM PDT 24
Peak memory 164836 kb
Host smart-ddab77e5-7aed-4bac-b45d-106d3fd44b6f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1111668882 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.1111668882
Directory /workspace/31.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.4175820278
Short name T160
Test name
Test status
Simulation time 1382830000 ps
CPU time 3.92 seconds
Started Jul 09 04:51:39 PM PDT 24
Finished Jul 09 04:51:49 PM PDT 24
Peak memory 164816 kb
Host smart-a161d6c9-e747-4187-ae41-672c94e3f380
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4175820278 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.4175820278
Directory /workspace/32.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.356073335
Short name T148
Test name
Test status
Simulation time 1567730000 ps
CPU time 4.41 seconds
Started Jul 09 04:51:33 PM PDT 24
Finished Jul 09 04:51:43 PM PDT 24
Peak memory 164804 kb
Host smart-a88fad9e-6366-48bc-83a7-272dab283041
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=356073335 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.356073335
Directory /workspace/33.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.1827185528
Short name T149
Test name
Test status
Simulation time 1469430000 ps
CPU time 4.29 seconds
Started Jul 09 04:51:39 PM PDT 24
Finished Jul 09 04:51:50 PM PDT 24
Peak memory 164820 kb
Host smart-d6394c3b-ac91-4dd3-b2ca-cdaa45b97044
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1827185528 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.1827185528
Directory /workspace/34.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.4103207163
Short name T116
Test name
Test status
Simulation time 1503350000 ps
CPU time 4.45 seconds
Started Jul 09 04:51:38 PM PDT 24
Finished Jul 09 04:51:49 PM PDT 24
Peak memory 164772 kb
Host smart-b98ed38d-1854-4dec-bd23-b29dacede6e4
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4103207163 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.4103207163
Directory /workspace/35.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.763168621
Short name T154
Test name
Test status
Simulation time 1462170000 ps
CPU time 4.42 seconds
Started Jul 09 04:51:43 PM PDT 24
Finished Jul 09 04:51:54 PM PDT 24
Peak memory 164824 kb
Host smart-ec32f200-76b8-47fb-b23b-3605734cac8f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=763168621 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.763168621
Directory /workspace/36.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.739145966
Short name T122
Test name
Test status
Simulation time 1429110000 ps
CPU time 4.13 seconds
Started Jul 09 04:51:43 PM PDT 24
Finished Jul 09 04:51:53 PM PDT 24
Peak memory 164816 kb
Host smart-fad59509-50d4-429a-89ca-0e4e5ee30e37
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=739145966 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.739145966
Directory /workspace/37.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.4025444815
Short name T152
Test name
Test status
Simulation time 1591670000 ps
CPU time 4.49 seconds
Started Jul 09 04:51:39 PM PDT 24
Finished Jul 09 04:51:51 PM PDT 24
Peak memory 164820 kb
Host smart-59b25333-7c51-48e0-a72b-441a2c17c10b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4025444815 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.4025444815
Directory /workspace/38.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.3132796725
Short name T140
Test name
Test status
Simulation time 1556970000 ps
CPU time 4.78 seconds
Started Jul 09 04:51:43 PM PDT 24
Finished Jul 09 04:51:55 PM PDT 24
Peak memory 164828 kb
Host smart-331979c8-cf5b-4fab-8586-69a8df986c85
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3132796725 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.3132796725
Directory /workspace/39.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.107005965
Short name T132
Test name
Test status
Simulation time 1458090000 ps
CPU time 4.11 seconds
Started Jul 09 04:51:36 PM PDT 24
Finished Jul 09 04:51:46 PM PDT 24
Peak memory 164760 kb
Host smart-a3b96965-b488-45c1-abdc-c0e44be8b0e4
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=107005965 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.107005965
Directory /workspace/4.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.2249398598
Short name T136
Test name
Test status
Simulation time 1293970000 ps
CPU time 4.01 seconds
Started Jul 09 04:51:39 PM PDT 24
Finished Jul 09 04:51:48 PM PDT 24
Peak memory 164816 kb
Host smart-7978b32a-cfd4-4866-b666-46efc858acce
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2249398598 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.2249398598
Directory /workspace/40.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.2837173926
Short name T141
Test name
Test status
Simulation time 1388910000 ps
CPU time 4.07 seconds
Started Jul 09 04:51:40 PM PDT 24
Finished Jul 09 04:51:51 PM PDT 24
Peak memory 164820 kb
Host smart-39a0bbca-f860-4b42-95a9-e9f0dbfd690f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2837173926 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.2837173926
Directory /workspace/41.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.2813884649
Short name T153
Test name
Test status
Simulation time 1476270000 ps
CPU time 4.9 seconds
Started Jul 09 04:51:40 PM PDT 24
Finished Jul 09 04:51:52 PM PDT 24
Peak memory 164912 kb
Host smart-2fdc7407-c4fa-4a55-8862-c996fb502e3e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2813884649 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.2813884649
Directory /workspace/42.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1372867698
Short name T119
Test name
Test status
Simulation time 1353730000 ps
CPU time 3.09 seconds
Started Jul 09 04:51:45 PM PDT 24
Finished Jul 09 04:51:53 PM PDT 24
Peak memory 164772 kb
Host smart-22f4291f-7e4d-46bb-9a46-4c8cda28e82f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1372867698 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.1372867698
Directory /workspace/43.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.4290540369
Short name T156
Test name
Test status
Simulation time 1296170000 ps
CPU time 5.07 seconds
Started Jul 09 04:51:41 PM PDT 24
Finished Jul 09 04:51:54 PM PDT 24
Peak memory 164840 kb
Host smart-83ff8627-3cce-4d76-b74a-0d6a2fd20418
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4290540369 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.4290540369
Directory /workspace/44.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.1268748858
Short name T123
Test name
Test status
Simulation time 1463070000 ps
CPU time 3.44 seconds
Started Jul 09 04:51:30 PM PDT 24
Finished Jul 09 04:51:39 PM PDT 24
Peak memory 164836 kb
Host smart-538c9c10-6935-49c4-893b-fa71948d8ba0
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1268748858 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.1268748858
Directory /workspace/45.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.1891866852
Short name T159
Test name
Test status
Simulation time 1456570000 ps
CPU time 3.94 seconds
Started Jul 09 04:51:40 PM PDT 24
Finished Jul 09 04:51:50 PM PDT 24
Peak memory 164864 kb
Host smart-f2c7f67b-78d6-4bd3-b407-f59bedf4a749
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1891866852 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.1891866852
Directory /workspace/46.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.3308421473
Short name T139
Test name
Test status
Simulation time 1168270000 ps
CPU time 3.12 seconds
Started Jul 09 04:51:46 PM PDT 24
Finished Jul 09 04:51:54 PM PDT 24
Peak memory 164816 kb
Host smart-decd69a9-bf9b-4274-ab99-5d50ac61db97
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3308421473 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.3308421473
Directory /workspace/47.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.431381379
Short name T121
Test name
Test status
Simulation time 1446630000 ps
CPU time 4.45 seconds
Started Jul 09 04:51:34 PM PDT 24
Finished Jul 09 04:51:44 PM PDT 24
Peak memory 164832 kb
Host smart-e50d0fc8-c1a0-4e47-b669-aad13362c1d8
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=431381379 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.431381379
Directory /workspace/48.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.1828888405
Short name T117
Test name
Test status
Simulation time 1584130000 ps
CPU time 5.24 seconds
Started Jul 09 04:51:44 PM PDT 24
Finished Jul 09 04:51:58 PM PDT 24
Peak memory 165008 kb
Host smart-809784b8-a2f1-4625-8224-0920ca75174e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1828888405 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.1828888405
Directory /workspace/49.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.2908681335
Short name T113
Test name
Test status
Simulation time 1334630000 ps
CPU time 4.04 seconds
Started Jul 09 04:51:38 PM PDT 24
Finished Jul 09 04:51:48 PM PDT 24
Peak memory 164836 kb
Host smart-0715e6a6-185c-4763-9a94-39d611228d7b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2908681335 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.2908681335
Directory /workspace/5.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.1899814823
Short name T114
Test name
Test status
Simulation time 1491530000 ps
CPU time 5.24 seconds
Started Jul 09 04:51:39 PM PDT 24
Finished Jul 09 04:51:51 PM PDT 24
Peak memory 164820 kb
Host smart-227ede3d-308c-4213-8e54-5927300bf7b4
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1899814823 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.1899814823
Directory /workspace/6.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.3171832161
Short name T155
Test name
Test status
Simulation time 1546670000 ps
CPU time 4.81 seconds
Started Jul 09 04:51:28 PM PDT 24
Finished Jul 09 04:51:39 PM PDT 24
Peak memory 164836 kb
Host smart-191b3644-0b03-4875-b769-1fe5c37b91ad
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3171832161 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.3171832161
Directory /workspace/7.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.3011979032
Short name T146
Test name
Test status
Simulation time 1599770000 ps
CPU time 3.8 seconds
Started Jul 09 04:51:34 PM PDT 24
Finished Jul 09 04:51:43 PM PDT 24
Peak memory 164836 kb
Host smart-42ddc67f-554c-4efa-ab32-bde6916b2722
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3011979032 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.3011979032
Directory /workspace/8.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.614801757
Short name T127
Test name
Test status
Simulation time 1562690000 ps
CPU time 3.72 seconds
Started Jul 09 04:51:39 PM PDT 24
Finished Jul 09 04:51:48 PM PDT 24
Peak memory 164772 kb
Host smart-5cd42b97-9460-45d5-9b05-2e6804ce98da
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=614801757 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.614801757
Directory /workspace/9.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.3435778941
Short name T38
Test name
Test status
Simulation time 1186370000 ps
CPU time 3.35 seconds
Started Jul 09 04:51:25 PM PDT 24
Finished Jul 09 04:51:33 PM PDT 24
Peak memory 164908 kb
Host smart-bbe2d59e-b94d-476e-89d7-4e821ae0c960
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3435778941 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.3435778941
Directory /workspace/1.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.2569752524
Short name T63
Test name
Test status
Simulation time 1212950000 ps
CPU time 4.07 seconds
Started Jul 09 04:51:26 PM PDT 24
Finished Jul 09 04:51:36 PM PDT 24
Peak memory 164820 kb
Host smart-3a8cbdb4-dcc6-4185-a6b5-c5851da14793
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2569752524 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.2569752524
Directory /workspace/10.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.3070137480
Short name T56
Test name
Test status
Simulation time 1618610000 ps
CPU time 4.88 seconds
Started Jul 09 04:51:23 PM PDT 24
Finished Jul 09 04:51:34 PM PDT 24
Peak memory 164808 kb
Host smart-fe9a0876-66d3-4fce-9aef-d40410911ca2
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3070137480 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.3070137480
Directory /workspace/11.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.1122120777
Short name T11
Test name
Test status
Simulation time 1458910000 ps
CPU time 4.86 seconds
Started Jul 09 04:51:17 PM PDT 24
Finished Jul 09 04:51:29 PM PDT 24
Peak memory 164820 kb
Host smart-caa54ad8-39af-43e4-a0e6-074d4ed07e20
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1122120777 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.1122120777
Directory /workspace/12.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.1656282313
Short name T37
Test name
Test status
Simulation time 1452650000 ps
CPU time 3.64 seconds
Started Jul 09 04:51:23 PM PDT 24
Finished Jul 09 04:51:32 PM PDT 24
Peak memory 164836 kb
Host smart-1ee71f1d-0f94-4b11-ae4b-4ad34589ce67
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1656282313 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.1656282313
Directory /workspace/13.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.3901170909
Short name T44
Test name
Test status
Simulation time 1634250000 ps
CPU time 4.39 seconds
Started Jul 09 04:51:17 PM PDT 24
Finished Jul 09 04:51:27 PM PDT 24
Peak memory 164872 kb
Host smart-2fdb9cbb-672d-406f-8892-218d93278abe
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3901170909 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.3901170909
Directory /workspace/14.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.3675518890
Short name T12
Test name
Test status
Simulation time 1531710000 ps
CPU time 4.33 seconds
Started Jul 09 04:51:27 PM PDT 24
Finished Jul 09 04:51:37 PM PDT 24
Peak memory 164836 kb
Host smart-281ebbb6-7e1d-4b00-a348-399d8f6d2e78
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3675518890 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.3675518890
Directory /workspace/15.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.759960268
Short name T48
Test name
Test status
Simulation time 1478030000 ps
CPU time 4.91 seconds
Started Jul 09 04:51:27 PM PDT 24
Finished Jul 09 04:51:38 PM PDT 24
Peak memory 164768 kb
Host smart-8fc70435-af51-49a5-9cad-7c233b557982
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=759960268 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.759960268
Directory /workspace/16.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.283333239
Short name T62
Test name
Test status
Simulation time 1522550000 ps
CPU time 5.31 seconds
Started Jul 09 04:51:33 PM PDT 24
Finished Jul 09 04:51:46 PM PDT 24
Peak memory 164592 kb
Host smart-8067f087-2c8a-47a4-b5e5-a4cc2547794e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=283333239 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.283333239
Directory /workspace/17.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.4155571594
Short name T47
Test name
Test status
Simulation time 1416830000 ps
CPU time 4.19 seconds
Started Jul 09 04:51:14 PM PDT 24
Finished Jul 09 04:51:25 PM PDT 24
Peak memory 164796 kb
Host smart-98e41124-d148-4190-9ed6-ca65d2ca0ecf
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4155571594 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.4155571594
Directory /workspace/18.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.3115868526
Short name T4
Test name
Test status
Simulation time 1541650000 ps
CPU time 5.23 seconds
Started Jul 09 04:51:15 PM PDT 24
Finished Jul 09 04:51:28 PM PDT 24
Peak memory 164812 kb
Host smart-c0fcd815-798a-4ea0-b6bc-80732769de08
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3115868526 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.3115868526
Directory /workspace/19.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.1068267689
Short name T3
Test name
Test status
Simulation time 1558610000 ps
CPU time 5.3 seconds
Started Jul 09 04:51:17 PM PDT 24
Finished Jul 09 04:51:30 PM PDT 24
Peak memory 164820 kb
Host smart-b9fe5dbe-d3c8-4f42-9757-2649b0309d5a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1068267689 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.1068267689
Directory /workspace/2.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.4249535454
Short name T45
Test name
Test status
Simulation time 1358350000 ps
CPU time 3.23 seconds
Started Jul 09 04:51:16 PM PDT 24
Finished Jul 09 04:51:24 PM PDT 24
Peak memory 164876 kb
Host smart-3d8be3df-4a05-46a2-9c3d-4eee485bf34c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4249535454 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.4249535454
Directory /workspace/20.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.1779802828
Short name T36
Test name
Test status
Simulation time 1497350000 ps
CPU time 4.59 seconds
Started Jul 09 04:51:31 PM PDT 24
Finished Jul 09 04:51:42 PM PDT 24
Peak memory 164816 kb
Host smart-702bc174-707e-4de9-babf-1a1908802bec
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1779802828 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.1779802828
Directory /workspace/21.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.3456468980
Short name T9
Test name
Test status
Simulation time 1623190000 ps
CPU time 5.52 seconds
Started Jul 09 04:51:34 PM PDT 24
Finished Jul 09 04:51:47 PM PDT 24
Peak memory 164772 kb
Host smart-2053e32b-6452-4b7e-b83a-0d37fa1ac8ad
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3456468980 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.3456468980
Directory /workspace/22.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.3692187328
Short name T55
Test name
Test status
Simulation time 1476570000 ps
CPU time 4.26 seconds
Started Jul 09 04:51:32 PM PDT 24
Finished Jul 09 04:51:42 PM PDT 24
Peak memory 164792 kb
Host smart-9597c486-8db9-4e6f-a1f0-5c1cb4835d05
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3692187328 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.3692187328
Directory /workspace/23.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.4149179179
Short name T70
Test name
Test status
Simulation time 1529010000 ps
CPU time 3.78 seconds
Started Jul 09 04:51:14 PM PDT 24
Finished Jul 09 04:51:24 PM PDT 24
Peak memory 164840 kb
Host smart-214040f9-59f5-4c34-a7bf-2d8395996981
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4149179179 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.4149179179
Directory /workspace/24.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.2483997142
Short name T52
Test name
Test status
Simulation time 1587710000 ps
CPU time 4.49 seconds
Started Jul 09 04:51:20 PM PDT 24
Finished Jul 09 04:51:31 PM PDT 24
Peak memory 164892 kb
Host smart-0c9d6b4c-e399-4416-9d5a-fd6c6c4ac8ef
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2483997142 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.2483997142
Directory /workspace/25.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.4261930098
Short name T57
Test name
Test status
Simulation time 1518870000 ps
CPU time 5.41 seconds
Started Jul 09 04:51:33 PM PDT 24
Finished Jul 09 04:51:46 PM PDT 24
Peak memory 164772 kb
Host smart-f9f90980-e934-458e-9df6-ef22e934686e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4261930098 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.4261930098
Directory /workspace/26.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.2409139725
Short name T2
Test name
Test status
Simulation time 1297690000 ps
CPU time 4.3 seconds
Started Jul 09 04:51:23 PM PDT 24
Finished Jul 09 04:51:32 PM PDT 24
Peak memory 164792 kb
Host smart-b04c6831-ac5c-43c6-8761-caa971dd0a20
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2409139725 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.2409139725
Directory /workspace/27.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.972335579
Short name T46
Test name
Test status
Simulation time 1449570000 ps
CPU time 4.55 seconds
Started Jul 09 04:51:17 PM PDT 24
Finished Jul 09 04:51:28 PM PDT 24
Peak memory 165000 kb
Host smart-6ca55de9-c2cb-4cd7-9312-88d15bd193a5
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=972335579 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.972335579
Directory /workspace/28.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.2597453857
Short name T40
Test name
Test status
Simulation time 1441930000 ps
CPU time 4.13 seconds
Started Jul 09 04:51:24 PM PDT 24
Finished Jul 09 04:51:33 PM PDT 24
Peak memory 164828 kb
Host smart-50554055-604f-4768-b515-0c3735674281
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2597453857 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.2597453857
Directory /workspace/29.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.914574886
Short name T59
Test name
Test status
Simulation time 1506650000 ps
CPU time 5.12 seconds
Started Jul 09 04:51:36 PM PDT 24
Finished Jul 09 04:51:48 PM PDT 24
Peak memory 164696 kb
Host smart-68563010-de21-4a9b-b407-1c120005357e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=914574886 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.914574886
Directory /workspace/3.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.1647581019
Short name T51
Test name
Test status
Simulation time 1495190000 ps
CPU time 4.1 seconds
Started Jul 09 04:51:24 PM PDT 24
Finished Jul 09 04:51:33 PM PDT 24
Peak memory 164812 kb
Host smart-634efb51-7bd2-4430-89e7-2253dce8c7f8
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1647581019 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.1647581019
Directory /workspace/30.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.22031689
Short name T58
Test name
Test status
Simulation time 1539810000 ps
CPU time 3.77 seconds
Started Jul 09 04:51:31 PM PDT 24
Finished Jul 09 04:51:40 PM PDT 24
Peak memory 164760 kb
Host smart-e2e0ac5b-4c04-4c3d-8685-3c4fb93d15fe
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=22031689 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.22031689
Directory /workspace/31.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.3756045105
Short name T49
Test name
Test status
Simulation time 1216850000 ps
CPU time 3.76 seconds
Started Jul 09 04:51:21 PM PDT 24
Finished Jul 09 04:51:29 PM PDT 24
Peak memory 164820 kb
Host smart-cb495de6-630c-4721-ae44-cdebd35b15ea
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3756045105 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.3756045105
Directory /workspace/32.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.3520667449
Short name T41
Test name
Test status
Simulation time 1289450000 ps
CPU time 4.42 seconds
Started Jul 09 04:51:38 PM PDT 24
Finished Jul 09 04:51:49 PM PDT 24
Peak memory 164836 kb
Host smart-30bd4b03-010f-486d-bc61-047468752186
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3520667449 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.3520667449
Directory /workspace/33.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.2866449141
Short name T68
Test name
Test status
Simulation time 1475210000 ps
CPU time 4.54 seconds
Started Jul 09 04:51:26 PM PDT 24
Finished Jul 09 04:51:37 PM PDT 24
Peak memory 164808 kb
Host smart-8a481303-3a68-4f1f-9d23-ef99afcc4d88
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2866449141 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.2866449141
Directory /workspace/34.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.1923957655
Short name T32
Test name
Test status
Simulation time 1311590000 ps
CPU time 2.99 seconds
Started Jul 09 04:51:30 PM PDT 24
Finished Jul 09 04:51:37 PM PDT 24
Peak memory 164836 kb
Host smart-8bbf8ad5-e797-4d1b-9e7a-685adcea9d35
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1923957655 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.1923957655
Directory /workspace/35.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.4084632554
Short name T60
Test name
Test status
Simulation time 1441890000 ps
CPU time 4.17 seconds
Started Jul 09 04:51:38 PM PDT 24
Finished Jul 09 04:51:53 PM PDT 24
Peak memory 164888 kb
Host smart-4c3ea38b-e094-49c1-abaa-269dccd3f7d7
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4084632554 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.4084632554
Directory /workspace/36.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.2298172985
Short name T31
Test name
Test status
Simulation time 1241450000 ps
CPU time 2.99 seconds
Started Jul 09 04:51:32 PM PDT 24
Finished Jul 09 04:51:39 PM PDT 24
Peak memory 164816 kb
Host smart-aaa656cc-b73a-4d09-afed-51442cefa2e8
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2298172985 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.2298172985
Directory /workspace/37.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.1153373546
Short name T13
Test name
Test status
Simulation time 1316090000 ps
CPU time 3.89 seconds
Started Jul 09 04:51:39 PM PDT 24
Finished Jul 09 04:51:48 PM PDT 24
Peak memory 164868 kb
Host smart-03f4fdd6-cae9-4e0e-b0be-0dca52e5b758
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1153373546 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.1153373546
Directory /workspace/38.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.612608477
Short name T50
Test name
Test status
Simulation time 1467270000 ps
CPU time 4.28 seconds
Started Jul 09 04:51:47 PM PDT 24
Finished Jul 09 04:51:58 PM PDT 24
Peak memory 164784 kb
Host smart-06f3d615-a3c6-4858-93a3-d8a957c1d5a4
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=612608477 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.612608477
Directory /workspace/39.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.1181058293
Short name T39
Test name
Test status
Simulation time 1570350000 ps
CPU time 4.79 seconds
Started Jul 09 04:51:22 PM PDT 24
Finished Jul 09 04:51:33 PM PDT 24
Peak memory 164792 kb
Host smart-3a877e27-e2d5-45b5-91d0-912ab33abc5d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1181058293 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.1181058293
Directory /workspace/4.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.1988073590
Short name T43
Test name
Test status
Simulation time 1512950000 ps
CPU time 4.45 seconds
Started Jul 09 04:51:32 PM PDT 24
Finished Jul 09 04:51:42 PM PDT 24
Peak memory 164788 kb
Host smart-2a45dbb9-6d0b-4bf6-8fad-c5bc5d280c87
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1988073590 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.1988073590
Directory /workspace/40.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.1817232879
Short name T69
Test name
Test status
Simulation time 1589450000 ps
CPU time 4.33 seconds
Started Jul 09 04:51:25 PM PDT 24
Finished Jul 09 04:51:35 PM PDT 24
Peak memory 164824 kb
Host smart-81aea0b2-1020-4608-9b0f-464cb8c95801
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1817232879 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.1817232879
Directory /workspace/41.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.3514522318
Short name T64
Test name
Test status
Simulation time 1484370000 ps
CPU time 4.75 seconds
Started Jul 09 04:51:22 PM PDT 24
Finished Jul 09 04:51:32 PM PDT 24
Peak memory 164836 kb
Host smart-bca179c7-43d8-4659-b196-634e9671b571
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3514522318 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.3514522318
Directory /workspace/42.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.817819798
Short name T33
Test name
Test status
Simulation time 1599890000 ps
CPU time 5.33 seconds
Started Jul 09 04:51:37 PM PDT 24
Finished Jul 09 04:51:49 PM PDT 24
Peak memory 164832 kb
Host smart-576e07f0-edf5-408c-ac8a-035644b8626c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=817819798 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.817819798
Directory /workspace/43.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.2137518169
Short name T53
Test name
Test status
Simulation time 1462310000 ps
CPU time 4.51 seconds
Started Jul 09 04:51:28 PM PDT 24
Finished Jul 09 04:51:39 PM PDT 24
Peak memory 164804 kb
Host smart-c9eacc03-cdeb-4fdc-8044-18f353b1373c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2137518169 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.2137518169
Directory /workspace/44.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.907054355
Short name T34
Test name
Test status
Simulation time 1526570000 ps
CPU time 4.2 seconds
Started Jul 09 04:51:38 PM PDT 24
Finished Jul 09 04:51:49 PM PDT 24
Peak memory 164872 kb
Host smart-1fd971c3-85c6-4ddb-bcd8-1accb65dd416
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=907054355 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.907054355
Directory /workspace/45.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.2719550286
Short name T42
Test name
Test status
Simulation time 1464310000 ps
CPU time 4.38 seconds
Started Jul 09 04:51:28 PM PDT 24
Finished Jul 09 04:51:39 PM PDT 24
Peak memory 164868 kb
Host smart-143a660c-c242-4886-9c1c-e4d7a3c6e11b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2719550286 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.2719550286
Directory /workspace/46.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.634956787
Short name T61
Test name
Test status
Simulation time 1520710000 ps
CPU time 3.45 seconds
Started Jul 09 04:51:21 PM PDT 24
Finished Jul 09 04:51:29 PM PDT 24
Peak memory 164832 kb
Host smart-c0cb570a-df47-4459-aa76-0cceba19fd9c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=634956787 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.634956787
Directory /workspace/47.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.2427530373
Short name T66
Test name
Test status
Simulation time 1349370000 ps
CPU time 4.45 seconds
Started Jul 09 04:51:22 PM PDT 24
Finished Jul 09 04:51:31 PM PDT 24
Peak memory 164840 kb
Host smart-1c41b188-ce43-4026-a873-dd28afa4a004
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2427530373 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.2427530373
Directory /workspace/48.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.1449524598
Short name T1
Test name
Test status
Simulation time 1004930000 ps
CPU time 2.79 seconds
Started Jul 09 04:51:29 PM PDT 24
Finished Jul 09 04:51:35 PM PDT 24
Peak memory 164832 kb
Host smart-b3df17a0-e0c7-463a-b616-19d5f718d592
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1449524598 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.1449524598
Directory /workspace/49.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.4029944167
Short name T65
Test name
Test status
Simulation time 1254870000 ps
CPU time 3.43 seconds
Started Jul 09 04:51:26 PM PDT 24
Finished Jul 09 04:51:34 PM PDT 24
Peak memory 164836 kb
Host smart-28130b09-591c-404b-b4e0-ac7cc8c37f5b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4029944167 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.4029944167
Directory /workspace/5.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.357798969
Short name T54
Test name
Test status
Simulation time 1267870000 ps
CPU time 4.85 seconds
Started Jul 09 04:51:11 PM PDT 24
Finished Jul 09 04:51:23 PM PDT 24
Peak memory 164760 kb
Host smart-2141e3de-1aaa-400e-a728-a0e8948487b1
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=357798969 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.357798969
Directory /workspace/6.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.4232137695
Short name T35
Test name
Test status
Simulation time 1424330000 ps
CPU time 3.57 seconds
Started Jul 09 04:51:31 PM PDT 24
Finished Jul 09 04:51:39 PM PDT 24
Peak memory 164812 kb
Host smart-637d44bb-f792-47a5-9857-bdf7c43201ef
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4232137695 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.4232137695
Directory /workspace/7.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.3855774360
Short name T67
Test name
Test status
Simulation time 1514570000 ps
CPU time 4.86 seconds
Started Jul 09 04:51:30 PM PDT 24
Finished Jul 09 04:51:42 PM PDT 24
Peak memory 164816 kb
Host smart-50dd04a9-232b-4a06-b513-c1b3512d9704
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3855774360 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.3855774360
Directory /workspace/8.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.3076057283
Short name T8
Test name
Test status
Simulation time 1375030000 ps
CPU time 4.1 seconds
Started Jul 09 04:51:20 PM PDT 24
Finished Jul 09 04:51:29 PM PDT 24
Peak memory 165000 kb
Host smart-33be7d73-2402-4c99-8626-dcd2f2de09f3
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3076057283 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.3076057283
Directory /workspace/9.prim_lfsr_gal_smoke/latest
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