Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.31 100.00 96.55 100.00 100.00 95.00


Total tests in report: 200
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
87.31 87.31 100.00 100.00 96.55 96.55 100.00 100.00 100.00 100.00 40.00 40.00 /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.4173055666
96.81 9.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 87.50 47.50 /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.2642537350
98.31 1.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 95.00 7.50 /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.2508236744

Tests that do not contribute to grading

Name
/workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.895807093
/workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.1690930617
/workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.1968543309
/workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.3796742660
/workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.36884317
/workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.2239116634
/workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.484431444
/workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.572553128
/workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.3187103727
/workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.119748894
/workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.353687967
/workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.1456094962
/workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.3334849608
/workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.2067687521
/workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.1976619872
/workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.786071965
/workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.138984042
/workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.1424409079
/workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.687272381
/workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.718707842
/workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.2752560647
/workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.152923606
/workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.2229598647
/workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.1761564291
/workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.1798360347
/workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.3955861436
/workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.3668980399
/workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.3472322241
/workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.2287802519
/workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.3634963592
/workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.1656713779
/workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.1014830039
/workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.3352133939
/workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.2921977769
/workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.479985763
/workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.8565209
/workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.1259263211
/workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.1691830008
/workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.2220980618
/workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.1330809916
/workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.3539037664
/workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.2042075771
/workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.4088235048
/workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.4058299158
/workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.2151708389
/workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.2406185137
/workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.3813545562
/workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.594769525
/workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.1758017666
/workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.4279046660
/workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.1227747115
/workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.3318909587
/workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.1672282415
/workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.3257968573
/workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.4065152653
/workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.3877916426
/workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.3871460390
/workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.3706689393
/workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.2735200584
/workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.803744876
/workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.1660469145
/workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.1574212355
/workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3173276827
/workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.651456635
/workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.1811904055
/workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.545394153
/workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.626889752
/workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.2406079540
/workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.111437669
/workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.1090449335
/workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.375817738
/workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.1934530922
/workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.3832003795
/workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.1738481245
/workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.2650098676
/workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.836543451
/workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.1929281845
/workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.3877302012
/workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.514763768
/workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.134316800
/workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.2747484531
/workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.679080825
/workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.1936400729
/workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.1303190539
/workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.1871910951
/workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.2154829119
/workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.3063744795
/workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.1474572402
/workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.3954332333
/workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.3456540413
/workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.1530880654
/workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.240712921
/workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.3181990146
/workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.3939977791
/workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.1380788541
/workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.1361877544
/workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.2556868252
/workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.3896658037
/workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.2755988702
/workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.3013588935
/workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.2694157428
/workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.2288413531
/workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.2033056899
/workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.2067679697
/workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.308696138
/workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.497086758
/workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.700206323
/workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.2088016876
/workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.3716381993
/workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.865719883
/workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.1582664292
/workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.2802346692
/workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3281646637
/workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.2935785106
/workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.2748627592
/workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.3261704339
/workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.3890082286
/workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.3077417428
/workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.3584040773
/workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.1530514865
/workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.3410378498
/workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.1088824023
/workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.478982619
/workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.774142021
/workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.1085237427
/workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.1750020539
/workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.3019196831
/workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.2798773480
/workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.2805637388
/workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.2179135223
/workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.3481225157
/workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.4288322831
/workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.777211534
/workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.2651523833
/workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.1541234084
/workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.2275181042
/workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.388948545
/workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.431142799
/workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.3712344281
/workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.2409427291
/workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.451972153
/workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.962637074
/workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.4131990120
/workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.2906272039
/workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.1171746551
/workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.1243457897
/workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.754184013
/workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2343207171
/workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.2499808530
/workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.4087002165
/workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.1120315805
/workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.2874178733
/workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.2085952450
/workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.729607922
/workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.2858134251
/workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.81430786
/workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.2314972509
/workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.1407042829
/workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.3988520650
/workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.925248600
/workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.3747546096
/workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.3805365598
/workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.3119209568
/workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.2089034434
/workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.2461473906
/workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.1330888436
/workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.841392392
/workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.642261223
/workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.2099707300
/workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.3955656165
/workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.869932535
/workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.1522475513
/workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.2609162440
/workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.777686208
/workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.2680474888
/workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.2429704610
/workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.1160085676
/workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.3189428111
/workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.133230072
/workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.1443456904
/workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.3148726094
/workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.2711364347
/workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.4209648606
/workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.2296484127
/workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.3666168140
/workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.1542364052
/workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.521082690
/workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.1936738047
/workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.516855814
/workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.1957831363
/workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.3526156854
/workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.1656571360
/workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.2172382521
/workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.308018991
/workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.1272426354
/workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.655934481
/workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.3330443063



Total test records in report: 200
tests.html | tests1.html | tests2.html | tests3.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.2314972509 Jul 10 05:51:52 PM PDT 24 Jul 10 05:52:05 PM PDT 24 1248370000 ps
T2 /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.133230072 Jul 10 05:51:51 PM PDT 24 Jul 10 05:52:02 PM PDT 24 1368450000 ps
T3 /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.729607922 Jul 10 05:51:55 PM PDT 24 Jul 10 05:52:07 PM PDT 24 1466210000 ps
T7 /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.3189428111 Jul 10 05:51:52 PM PDT 24 Jul 10 05:52:07 PM PDT 24 1522090000 ps
T8 /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.4173055666 Jul 10 05:51:47 PM PDT 24 Jul 10 05:51:58 PM PDT 24 1466990000 ps
T9 /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.2680474888 Jul 10 05:51:50 PM PDT 24 Jul 10 05:52:00 PM PDT 24 1381030000 ps
T10 /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.655934481 Jul 10 05:51:49 PM PDT 24 Jul 10 05:52:01 PM PDT 24 1541730000 ps
T11 /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.2296484127 Jul 10 05:51:55 PM PDT 24 Jul 10 05:52:07 PM PDT 24 1549110000 ps
T12 /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.2429704610 Jul 10 05:51:51 PM PDT 24 Jul 10 05:52:03 PM PDT 24 1532250000 ps
T13 /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.516855814 Jul 10 05:51:53 PM PDT 24 Jul 10 05:52:07 PM PDT 24 1600710000 ps
T31 /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.3988520650 Jul 10 05:51:55 PM PDT 24 Jul 10 05:52:07 PM PDT 24 1500430000 ps
T32 /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.2858134251 Jul 10 05:51:53 PM PDT 24 Jul 10 05:52:06 PM PDT 24 1560290000 ps
T33 /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.1522475513 Jul 10 05:51:55 PM PDT 24 Jul 10 05:52:04 PM PDT 24 1086630000 ps
T34 /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.308018991 Jul 10 05:51:44 PM PDT 24 Jul 10 05:51:58 PM PDT 24 1549810000 ps
T35 /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.2874178733 Jul 10 05:51:50 PM PDT 24 Jul 10 05:52:05 PM PDT 24 1517910000 ps
T36 /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.642261223 Jul 10 05:51:50 PM PDT 24 Jul 10 05:52:01 PM PDT 24 1565030000 ps
T37 /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.869932535 Jul 10 05:51:47 PM PDT 24 Jul 10 05:51:59 PM PDT 24 1441310000 ps
T38 /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.2172382521 Jul 10 05:51:48 PM PDT 24 Jul 10 05:52:01 PM PDT 24 1467190000 ps
T39 /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.3747546096 Jul 10 05:51:53 PM PDT 24 Jul 10 05:52:07 PM PDT 24 1458510000 ps
T40 /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.2499808530 Jul 10 05:51:50 PM PDT 24 Jul 10 05:52:02 PM PDT 24 1325010000 ps
T41 /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.925248600 Jul 10 05:51:49 PM PDT 24 Jul 10 05:52:02 PM PDT 24 1463350000 ps
T42 /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.2711364347 Jul 10 05:51:45 PM PDT 24 Jul 10 05:51:58 PM PDT 24 1497890000 ps
T43 /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.521082690 Jul 10 05:51:53 PM PDT 24 Jul 10 05:52:05 PM PDT 24 1366510000 ps
T44 /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.3666168140 Jul 10 05:51:49 PM PDT 24 Jul 10 05:51:59 PM PDT 24 1220710000 ps
T45 /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.1160085676 Jul 10 05:51:49 PM PDT 24 Jul 10 05:52:02 PM PDT 24 1445890000 ps
T46 /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.3330443063 Jul 10 05:51:50 PM PDT 24 Jul 10 05:52:00 PM PDT 24 1454390000 ps
T47 /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.1957831363 Jul 10 05:51:50 PM PDT 24 Jul 10 05:52:00 PM PDT 24 1526430000 ps
T48 /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.3805365598 Jul 10 05:51:51 PM PDT 24 Jul 10 05:52:03 PM PDT 24 1514310000 ps
T49 /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.1272426354 Jul 10 05:51:48 PM PDT 24 Jul 10 05:51:59 PM PDT 24 1488770000 ps
T50 /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.2609162440 Jul 10 05:51:53 PM PDT 24 Jul 10 05:52:07 PM PDT 24 1492770000 ps
T51 /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.3955656165 Jul 10 05:51:51 PM PDT 24 Jul 10 05:52:05 PM PDT 24 1432030000 ps
T52 /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.3148726094 Jul 10 05:51:53 PM PDT 24 Jul 10 05:52:07 PM PDT 24 1570410000 ps
T53 /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.1443456904 Jul 10 05:51:51 PM PDT 24 Jul 10 05:52:03 PM PDT 24 1232190000 ps
T54 /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.1407042829 Jul 10 05:51:52 PM PDT 24 Jul 10 05:52:05 PM PDT 24 1543230000 ps
T55 /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.1330888436 Jul 10 05:51:53 PM PDT 24 Jul 10 05:52:07 PM PDT 24 1413430000 ps
T56 /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.81430786 Jul 10 05:51:54 PM PDT 24 Jul 10 05:52:06 PM PDT 24 1266250000 ps
T57 /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.3119209568 Jul 10 05:51:50 PM PDT 24 Jul 10 05:52:04 PM PDT 24 1547550000 ps
T58 /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.1120315805 Jul 10 05:51:51 PM PDT 24 Jul 10 05:52:06 PM PDT 24 1413350000 ps
T59 /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.2089034434 Jul 10 05:51:55 PM PDT 24 Jul 10 05:52:07 PM PDT 24 1533850000 ps
T60 /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.4209648606 Jul 10 05:51:55 PM PDT 24 Jul 10 05:52:07 PM PDT 24 1342990000 ps
T61 /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.777686208 Jul 10 05:51:53 PM PDT 24 Jul 10 05:52:06 PM PDT 24 1542450000 ps
T62 /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.1936738047 Jul 10 05:51:52 PM PDT 24 Jul 10 05:52:04 PM PDT 24 1220030000 ps
T63 /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.2085952450 Jul 10 05:51:53 PM PDT 24 Jul 10 05:52:06 PM PDT 24 1546010000 ps
T64 /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.2099707300 Jul 10 05:51:53 PM PDT 24 Jul 10 05:52:05 PM PDT 24 1377170000 ps
T65 /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.1542364052 Jul 10 05:51:52 PM PDT 24 Jul 10 05:52:04 PM PDT 24 1570290000 ps
T66 /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.841392392 Jul 10 05:51:53 PM PDT 24 Jul 10 05:52:05 PM PDT 24 1360250000 ps
T67 /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.2461473906 Jul 10 05:51:52 PM PDT 24 Jul 10 05:52:04 PM PDT 24 1582510000 ps
T68 /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.3526156854 Jul 10 05:51:51 PM PDT 24 Jul 10 05:52:04 PM PDT 24 1563770000 ps
T69 /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.4087002165 Jul 10 05:51:51 PM PDT 24 Jul 10 05:52:02 PM PDT 24 1371910000 ps
T70 /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.1656571360 Jul 10 05:51:48 PM PDT 24 Jul 10 05:52:00 PM PDT 24 1437870000 ps
T4 /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.594769525 Jul 10 05:51:40 PM PDT 24 Jul 10 06:22:26 PM PDT 24 337058850000 ps
T5 /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.1761564291 Jul 10 05:51:44 PM PDT 24 Jul 10 06:24:34 PM PDT 24 336536210000 ps
T6 /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.2042075771 Jul 10 05:51:45 PM PDT 24 Jul 10 06:23:21 PM PDT 24 336357790000 ps
T14 /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.2220980618 Jul 10 05:51:45 PM PDT 24 Jul 10 06:29:18 PM PDT 24 336993870000 ps
T15 /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.1798360347 Jul 10 05:51:46 PM PDT 24 Jul 10 06:28:52 PM PDT 24 336642890000 ps
T16 /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.895807093 Jul 10 05:51:33 PM PDT 24 Jul 10 06:23:44 PM PDT 24 336952730000 ps
T17 /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.2287802519 Jul 10 05:51:42 PM PDT 24 Jul 10 06:34:38 PM PDT 24 336627210000 ps
T18 /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.4088235048 Jul 10 05:51:43 PM PDT 24 Jul 10 06:28:26 PM PDT 24 336346670000 ps
T19 /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.1976619872 Jul 10 05:51:45 PM PDT 24 Jul 10 06:22:54 PM PDT 24 336471110000 ps
T20 /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.2642537350 Jul 10 05:51:36 PM PDT 24 Jul 10 06:23:42 PM PDT 24 337172290000 ps
T71 /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.2067687521 Jul 10 05:51:49 PM PDT 24 Jul 10 06:20:46 PM PDT 24 336620110000 ps
T72 /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.3813545562 Jul 10 05:51:36 PM PDT 24 Jul 10 06:19:53 PM PDT 24 336610990000 ps
T73 /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.718707842 Jul 10 05:51:44 PM PDT 24 Jul 10 06:26:28 PM PDT 24 336497610000 ps
T74 /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.1968543309 Jul 10 05:51:41 PM PDT 24 Jul 10 06:23:43 PM PDT 24 337030470000 ps
T75 /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.1758017666 Jul 10 05:51:37 PM PDT 24 Jul 10 06:22:55 PM PDT 24 337049330000 ps
T76 /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.1690930617 Jul 10 05:51:34 PM PDT 24 Jul 10 06:25:30 PM PDT 24 336807350000 ps
T77 /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.119748894 Jul 10 05:51:41 PM PDT 24 Jul 10 06:23:31 PM PDT 24 336902990000 ps
T78 /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.1330809916 Jul 10 05:51:45 PM PDT 24 Jul 10 06:24:53 PM PDT 24 336797670000 ps
T79 /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.2752560647 Jul 10 05:51:43 PM PDT 24 Jul 10 06:23:03 PM PDT 24 336733970000 ps
T80 /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.1014830039 Jul 10 05:51:46 PM PDT 24 Jul 10 06:28:37 PM PDT 24 336547090000 ps
T81 /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.786071965 Jul 10 05:51:43 PM PDT 24 Jul 10 06:24:52 PM PDT 24 337092090000 ps
T82 /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.3955861436 Jul 10 05:51:46 PM PDT 24 Jul 10 06:26:55 PM PDT 24 336927270000 ps
T83 /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.8565209 Jul 10 05:51:45 PM PDT 24 Jul 10 06:22:53 PM PDT 24 336294350000 ps
T84 /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.1691830008 Jul 10 05:51:44 PM PDT 24 Jul 10 06:23:57 PM PDT 24 336634570000 ps
T85 /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.2921977769 Jul 10 05:51:35 PM PDT 24 Jul 10 06:24:23 PM PDT 24 336843670000 ps
T86 /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.484431444 Jul 10 05:51:37 PM PDT 24 Jul 10 06:23:22 PM PDT 24 336702010000 ps
T87 /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.3352133939 Jul 10 05:51:44 PM PDT 24 Jul 10 06:24:21 PM PDT 24 336621290000 ps
T88 /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.3634963592 Jul 10 05:51:47 PM PDT 24 Jul 10 06:24:17 PM PDT 24 336521810000 ps
T89 /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.1656713779 Jul 10 05:51:44 PM PDT 24 Jul 10 06:21:26 PM PDT 24 336946270000 ps
T90 /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.1259263211 Jul 10 05:51:47 PM PDT 24 Jul 10 06:29:40 PM PDT 24 336442690000 ps
T91 /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.36884317 Jul 10 05:51:33 PM PDT 24 Jul 10 06:25:11 PM PDT 24 336915190000 ps
T92 /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.2229598647 Jul 10 05:51:36 PM PDT 24 Jul 10 06:25:50 PM PDT 24 336542870000 ps
T93 /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.479985763 Jul 10 05:51:49 PM PDT 24 Jul 10 06:33:52 PM PDT 24 336414710000 ps
T94 /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.2239116634 Jul 10 05:51:39 PM PDT 24 Jul 10 06:22:40 PM PDT 24 336948830000 ps
T95 /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.3334849608 Jul 10 05:51:49 PM PDT 24 Jul 10 06:19:49 PM PDT 24 336458990000 ps
T96 /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.3472322241 Jul 10 05:51:47 PM PDT 24 Jul 10 06:21:58 PM PDT 24 336810130000 ps
T97 /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.1456094962 Jul 10 05:51:34 PM PDT 24 Jul 10 06:24:46 PM PDT 24 336488010000 ps
T98 /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.4058299158 Jul 10 05:51:44 PM PDT 24 Jul 10 06:28:22 PM PDT 24 336758170000 ps
T99 /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.687272381 Jul 10 05:51:44 PM PDT 24 Jul 10 06:25:55 PM PDT 24 336733530000 ps
T100 /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.572553128 Jul 10 05:51:39 PM PDT 24 Jul 10 06:18:26 PM PDT 24 336927690000 ps
T101 /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.3796742660 Jul 10 05:51:43 PM PDT 24 Jul 10 06:33:36 PM PDT 24 336407630000 ps
T102 /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.2151708389 Jul 10 05:51:35 PM PDT 24 Jul 10 06:25:33 PM PDT 24 336365210000 ps
T103 /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.2406185137 Jul 10 05:51:34 PM PDT 24 Jul 10 06:23:53 PM PDT 24 336753870000 ps
T104 /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.3668980399 Jul 10 05:51:42 PM PDT 24 Jul 10 06:24:00 PM PDT 24 336795270000 ps
T105 /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.3539037664 Jul 10 05:51:46 PM PDT 24 Jul 10 06:22:59 PM PDT 24 336397110000 ps
T106 /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.152923606 Jul 10 05:51:45 PM PDT 24 Jul 10 06:25:26 PM PDT 24 336285090000 ps
T107 /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.1424409079 Jul 10 05:51:45 PM PDT 24 Jul 10 06:24:48 PM PDT 24 337054190000 ps
T108 /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.353687967 Jul 10 05:51:45 PM PDT 24 Jul 10 06:24:51 PM PDT 24 336692890000 ps
T109 /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.3187103727 Jul 10 05:51:42 PM PDT 24 Jul 10 06:29:43 PM PDT 24 337123130000 ps
T110 /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.138984042 Jul 10 05:51:46 PM PDT 24 Jul 10 06:27:55 PM PDT 24 336886970000 ps
T111 /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.962637074 Jul 10 05:51:59 PM PDT 24 Jul 10 05:52:13 PM PDT 24 1500850000 ps
T112 /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.2802346692 Jul 10 05:52:04 PM PDT 24 Jul 10 05:52:16 PM PDT 24 1474450000 ps
T113 /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.2179135223 Jul 10 05:51:59 PM PDT 24 Jul 10 05:52:11 PM PDT 24 1363490000 ps
T114 /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.3077417428 Jul 10 05:52:00 PM PDT 24 Jul 10 05:52:14 PM PDT 24 1405290000 ps
T115 /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.1088824023 Jul 10 05:51:53 PM PDT 24 Jul 10 05:52:05 PM PDT 24 1245510000 ps
T116 /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.865719883 Jul 10 05:51:59 PM PDT 24 Jul 10 05:52:15 PM PDT 24 1548810000 ps
T117 /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.451972153 Jul 10 05:52:09 PM PDT 24 Jul 10 05:52:22 PM PDT 24 1368010000 ps
T118 /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.2748627592 Jul 10 05:52:01 PM PDT 24 Jul 10 05:52:15 PM PDT 24 1540510000 ps
T119 /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.2935785106 Jul 10 05:52:06 PM PDT 24 Jul 10 05:52:19 PM PDT 24 1397850000 ps
T120 /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.2033056899 Jul 10 05:51:58 PM PDT 24 Jul 10 05:52:12 PM PDT 24 1406090000 ps
T121 /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.3261704339 Jul 10 05:52:00 PM PDT 24 Jul 10 05:52:14 PM PDT 24 1580570000 ps
T122 /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.2798773480 Jul 10 05:52:06 PM PDT 24 Jul 10 05:52:20 PM PDT 24 1585690000 ps
T123 /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.2906272039 Jul 10 05:51:50 PM PDT 24 Jul 10 05:52:00 PM PDT 24 1530850000 ps
T124 /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.1750020539 Jul 10 05:51:56 PM PDT 24 Jul 10 05:52:08 PM PDT 24 1246270000 ps
T125 /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.2755988702 Jul 10 05:51:50 PM PDT 24 Jul 10 05:52:01 PM PDT 24 1387010000 ps
T126 /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.431142799 Jul 10 05:51:59 PM PDT 24 Jul 10 05:52:14 PM PDT 24 1470150000 ps
T127 /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.3481225157 Jul 10 05:51:58 PM PDT 24 Jul 10 05:52:11 PM PDT 24 1432930000 ps
T128 /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.497086758 Jul 10 05:52:00 PM PDT 24 Jul 10 05:52:15 PM PDT 24 1430950000 ps
T129 /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.777211534 Jul 10 05:51:58 PM PDT 24 Jul 10 05:52:11 PM PDT 24 1615710000 ps
T130 /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.2651523833 Jul 10 05:52:06 PM PDT 24 Jul 10 05:52:20 PM PDT 24 1455930000 ps
T131 /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.2694157428 Jul 10 05:52:10 PM PDT 24 Jul 10 05:52:26 PM PDT 24 1548990000 ps
T132 /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.1582664292 Jul 10 05:51:58 PM PDT 24 Jul 10 05:52:10 PM PDT 24 1388150000 ps
T133 /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.1085237427 Jul 10 05:52:05 PM PDT 24 Jul 10 05:52:15 PM PDT 24 1253210000 ps
T134 /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2343207171 Jul 10 05:51:57 PM PDT 24 Jul 10 05:52:08 PM PDT 24 1393150000 ps
T135 /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3281646637 Jul 10 05:52:05 PM PDT 24 Jul 10 05:52:19 PM PDT 24 1468790000 ps
T136 /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.3019196831 Jul 10 05:51:58 PM PDT 24 Jul 10 05:52:10 PM PDT 24 1475670000 ps
T137 /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.308696138 Jul 10 05:52:01 PM PDT 24 Jul 10 05:52:13 PM PDT 24 1534410000 ps
T138 /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.754184013 Jul 10 05:52:09 PM PDT 24 Jul 10 05:52:25 PM PDT 24 1493570000 ps
T139 /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.2288413531 Jul 10 05:51:58 PM PDT 24 Jul 10 05:52:11 PM PDT 24 1506450000 ps
T140 /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.1243457897 Jul 10 05:51:52 PM PDT 24 Jul 10 05:52:12 PM PDT 24 1545750000 ps
T141 /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.3890082286 Jul 10 05:52:05 PM PDT 24 Jul 10 05:52:19 PM PDT 24 1409090000 ps
T142 /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.2067679697 Jul 10 05:51:59 PM PDT 24 Jul 10 05:52:13 PM PDT 24 1436550000 ps
T143 /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.3410378498 Jul 10 05:51:59 PM PDT 24 Jul 10 05:52:14 PM PDT 24 1425150000 ps
T144 /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.774142021 Jul 10 05:51:57 PM PDT 24 Jul 10 05:52:10 PM PDT 24 1202230000 ps
T145 /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.2805637388 Jul 10 05:52:09 PM PDT 24 Jul 10 05:52:24 PM PDT 24 1538210000 ps
T146 /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.2275181042 Jul 10 05:52:01 PM PDT 24 Jul 10 05:52:15 PM PDT 24 1490050000 ps
T147 /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.3584040773 Jul 10 05:51:58 PM PDT 24 Jul 10 05:52:12 PM PDT 24 1524850000 ps
T148 /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.1541234084 Jul 10 05:52:01 PM PDT 24 Jul 10 05:52:15 PM PDT 24 1500330000 ps
T149 /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.3013588935 Jul 10 05:51:53 PM PDT 24 Jul 10 05:52:05 PM PDT 24 1511290000 ps
T150 /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.2088016876 Jul 10 05:51:58 PM PDT 24 Jul 10 05:52:10 PM PDT 24 1557410000 ps
T151 /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.1530514865 Jul 10 05:52:00 PM PDT 24 Jul 10 05:52:16 PM PDT 24 1434770000 ps
T152 /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.1171746551 Jul 10 05:51:58 PM PDT 24 Jul 10 05:52:10 PM PDT 24 1461990000 ps
T153 /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.700206323 Jul 10 05:52:06 PM PDT 24 Jul 10 05:52:20 PM PDT 24 1382350000 ps
T154 /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.4131990120 Jul 10 05:51:57 PM PDT 24 Jul 10 05:52:10 PM PDT 24 1563270000 ps
T155 /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.478982619 Jul 10 05:52:02 PM PDT 24 Jul 10 05:52:15 PM PDT 24 1584270000 ps
T156 /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.3716381993 Jul 10 05:51:55 PM PDT 24 Jul 10 05:52:11 PM PDT 24 1537730000 ps
T157 /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.4288322831 Jul 10 05:52:06 PM PDT 24 Jul 10 05:52:19 PM PDT 24 1476670000 ps
T158 /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.388948545 Jul 10 05:52:01 PM PDT 24 Jul 10 05:52:16 PM PDT 24 1451890000 ps
T159 /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.3712344281 Jul 10 05:52:06 PM PDT 24 Jul 10 05:52:17 PM PDT 24 1369990000 ps
T160 /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.2409427291 Jul 10 05:51:59 PM PDT 24 Jul 10 05:52:14 PM PDT 24 1550870000 ps
T21 /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.2508236744 Jul 10 05:52:04 PM PDT 24 Jul 10 06:29:37 PM PDT 24 337000990000 ps
T22 /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.1738481245 Jul 10 05:52:03 PM PDT 24 Jul 10 06:24:08 PM PDT 24 336913690000 ps
T23 /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.651456635 Jul 10 05:52:04 PM PDT 24 Jul 10 06:23:29 PM PDT 24 336405230000 ps
T24 /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.2154829119 Jul 10 05:52:06 PM PDT 24 Jul 10 06:23:41 PM PDT 24 336494750000 ps
T25 /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.679080825 Jul 10 05:52:12 PM PDT 24 Jul 10 06:35:22 PM PDT 24 337055190000 ps
T26 /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.2406079540 Jul 10 05:52:10 PM PDT 24 Jul 10 06:22:56 PM PDT 24 336866690000 ps
T27 /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.2747484531 Jul 10 05:52:12 PM PDT 24 Jul 10 06:35:15 PM PDT 24 336589390000 ps
T28 /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.803744876 Jul 10 05:52:05 PM PDT 24 Jul 10 06:25:36 PM PDT 24 336435170000 ps
T29 /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.1090449335 Jul 10 05:52:07 PM PDT 24 Jul 10 06:33:08 PM PDT 24 336936150000 ps
T30 /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.545394153 Jul 10 05:52:11 PM PDT 24 Jul 10 06:25:22 PM PDT 24 336452890000 ps
T161 /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.2735200584 Jul 10 05:52:03 PM PDT 24 Jul 10 06:24:39 PM PDT 24 336653650000 ps
T162 /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.1380788541 Jul 10 05:52:04 PM PDT 24 Jul 10 06:22:31 PM PDT 24 336406230000 ps
T163 /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.240712921 Jul 10 05:52:06 PM PDT 24 Jul 10 06:22:28 PM PDT 24 337043210000 ps
T164 /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.3063744795 Jul 10 05:52:03 PM PDT 24 Jul 10 06:27:07 PM PDT 24 336635870000 ps
T165 /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.626889752 Jul 10 05:52:12 PM PDT 24 Jul 10 06:25:29 PM PDT 24 336759510000 ps
T166 /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.1811904055 Jul 10 05:52:04 PM PDT 24 Jul 10 06:23:23 PM PDT 24 337145270000 ps
T167 /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.1660469145 Jul 10 05:52:00 PM PDT 24 Jul 10 06:31:00 PM PDT 24 336995090000 ps
T168 /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.3871460390 Jul 10 05:52:10 PM PDT 24 Jul 10 06:33:35 PM PDT 24 336926130000 ps
T169 /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3173276827 Jul 10 05:52:08 PM PDT 24 Jul 10 06:31:07 PM PDT 24 337060290000 ps
T170 /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.1361877544 Jul 10 05:52:05 PM PDT 24 Jul 10 06:21:36 PM PDT 24 336832070000 ps
T171 /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.4065152653 Jul 10 05:52:08 PM PDT 24 Jul 10 06:29:25 PM PDT 24 336377570000 ps
T172 /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.1936400729 Jul 10 05:52:12 PM PDT 24 Jul 10 06:29:47 PM PDT 24 336652330000 ps
T173 /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.1672282415 Jul 10 05:52:10 PM PDT 24 Jul 10 06:33:56 PM PDT 24 336429590000 ps
T174 /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.1227747115 Jul 10 05:52:01 PM PDT 24 Jul 10 06:25:05 PM PDT 24 337094250000 ps
T175 /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.3877916426 Jul 10 05:52:09 PM PDT 24 Jul 10 06:35:12 PM PDT 24 336654290000 ps
T176 /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.514763768 Jul 10 05:52:10 PM PDT 24 Jul 10 06:24:20 PM PDT 24 336853410000 ps
T177 /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.3877302012 Jul 10 05:52:07 PM PDT 24 Jul 10 06:28:04 PM PDT 24 336527830000 ps
T178 /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.3181990146 Jul 10 05:52:08 PM PDT 24 Jul 10 06:33:29 PM PDT 24 336597170000 ps
T179 /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.836543451 Jul 10 05:52:06 PM PDT 24 Jul 10 06:28:09 PM PDT 24 336624170000 ps
T180 /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.3456540413 Jul 10 05:52:04 PM PDT 24 Jul 10 06:24:04 PM PDT 24 336639430000 ps
T181 /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.1530880654 Jul 10 05:52:11 PM PDT 24 Jul 10 06:30:52 PM PDT 24 336936610000 ps
T182 /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.1574212355 Jul 10 05:52:03 PM PDT 24 Jul 10 06:21:14 PM PDT 24 336586750000 ps
T183 /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.3939977791 Jul 10 05:52:03 PM PDT 24 Jul 10 06:22:49 PM PDT 24 336572810000 ps
T184 /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.134316800 Jul 10 05:52:08 PM PDT 24 Jul 10 06:28:47 PM PDT 24 336592350000 ps
T185 /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.1871910951 Jul 10 05:52:10 PM PDT 24 Jul 10 06:34:04 PM PDT 24 336694250000 ps
T186 /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.1929281845 Jul 10 05:52:09 PM PDT 24 Jul 10 06:29:23 PM PDT 24 336454470000 ps
T187 /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.4279046660 Jul 10 05:52:01 PM PDT 24 Jul 10 06:23:18 PM PDT 24 336371450000 ps
T188 /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.1303190539 Jul 10 05:52:07 PM PDT 24 Jul 10 06:28:41 PM PDT 24 337055930000 ps
T189 /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.3257968573 Jul 10 05:52:10 PM PDT 24 Jul 10 06:22:10 PM PDT 24 336537990000 ps
T190 /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.1474572402 Jul 10 05:52:14 PM PDT 24 Jul 10 06:24:38 PM PDT 24 336669890000 ps
T191 /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.3832003795 Jul 10 05:52:03 PM PDT 24 Jul 10 06:23:36 PM PDT 24 336409670000 ps
T192 /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.3318909587 Jul 10 05:52:08 PM PDT 24 Jul 10 06:29:41 PM PDT 24 336385790000 ps
T193 /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.1934530922 Jul 10 05:52:12 PM PDT 24 Jul 10 06:25:19 PM PDT 24 336986290000 ps
T194 /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.3706689393 Jul 10 05:52:12 PM PDT 24 Jul 10 06:24:48 PM PDT 24 336754690000 ps
T195 /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.111437669 Jul 10 05:52:06 PM PDT 24 Jul 10 06:22:20 PM PDT 24 337016410000 ps
T196 /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.3896658037 Jul 10 05:52:08 PM PDT 24 Jul 10 06:24:52 PM PDT 24 336804430000 ps
T197 /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.2556868252 Jul 10 05:52:08 PM PDT 24 Jul 10 06:24:08 PM PDT 24 336907250000 ps
T198 /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.375817738 Jul 10 05:52:07 PM PDT 24 Jul 10 06:24:53 PM PDT 24 336499270000 ps
T199 /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.3954332333 Jul 10 05:52:06 PM PDT 24 Jul 10 06:23:32 PM PDT 24 336787690000 ps
T200 /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.2650098676 Jul 10 05:52:11 PM PDT 24 Jul 10 06:31:35 PM PDT 24 336298850000 ps

Test location /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.4173055666
Short name T8
Test name
Test status
Simulation time 1466990000 ps
CPU time 4.45 seconds
Started Jul 10 05:51:47 PM PDT 24
Finished Jul 10 05:51:58 PM PDT 24
Peak memory 164912 kb
Host smart-8b34eb0e-7861-4ff8-bae0-be04bfe56e39
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4173055666 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.4173055666
Directory /workspace/0.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.2642537350
Short name T20
Test name
Test status
Simulation time 337172290000 ps
CPU time 779.08 seconds
Started Jul 10 05:51:36 PM PDT 24
Finished Jul 10 06:23:42 PM PDT 24
Peak memory 160792 kb
Host smart-8681fa58-9361-4e50-9b53-7a3b9d706a3d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2642537350 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.2642537350
Directory /workspace/0.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.2508236744
Short name T21
Test name
Test status
Simulation time 337000990000 ps
CPU time 884.49 seconds
Started Jul 10 05:52:04 PM PDT 24
Finished Jul 10 06:29:37 PM PDT 24
Peak memory 160828 kb
Host smart-1482c77c-bd7e-4773-8590-1411f78ef23e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2508236744 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.2508236744
Directory /workspace/12.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.895807093
Short name T16
Test name
Test status
Simulation time 336952730000 ps
CPU time 799.5 seconds
Started Jul 10 05:51:33 PM PDT 24
Finished Jul 10 06:23:44 PM PDT 24
Peak memory 160820 kb
Host smart-e5a0c219-8f58-4acb-807f-2a3df91e7144
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=895807093 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.895807093
Directory /workspace/1.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.1690930617
Short name T76
Test name
Test status
Simulation time 336807350000 ps
CPU time 825.98 seconds
Started Jul 10 05:51:34 PM PDT 24
Finished Jul 10 06:25:30 PM PDT 24
Peak memory 160820 kb
Host smart-ad755b12-c2d5-4c20-8318-ebe52b35d0c9
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1690930617 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.1690930617
Directory /workspace/10.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.1968543309
Short name T74
Test name
Test status
Simulation time 337030470000 ps
CPU time 782.91 seconds
Started Jul 10 05:51:41 PM PDT 24
Finished Jul 10 06:23:43 PM PDT 24
Peak memory 160796 kb
Host smart-6c1ed30d-6cdb-4a43-a1c9-89bbc1635e09
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1968543309 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.1968543309
Directory /workspace/11.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.3796742660
Short name T101
Test name
Test status
Simulation time 336407630000 ps
CPU time 982.93 seconds
Started Jul 10 05:51:43 PM PDT 24
Finished Jul 10 06:33:36 PM PDT 24
Peak memory 160808 kb
Host smart-7eb1123c-ddb9-4ec7-bafa-fd3ad356d0a6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3796742660 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.3796742660
Directory /workspace/12.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.36884317
Short name T91
Test name
Test status
Simulation time 336915190000 ps
CPU time 826.27 seconds
Started Jul 10 05:51:33 PM PDT 24
Finished Jul 10 06:25:11 PM PDT 24
Peak memory 160788 kb
Host smart-6b1a13fc-6b8c-4afe-9db1-0ecc15228726
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=36884317 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.36884317
Directory /workspace/13.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.2239116634
Short name T94
Test name
Test status
Simulation time 336948830000 ps
CPU time 754.66 seconds
Started Jul 10 05:51:39 PM PDT 24
Finished Jul 10 06:22:40 PM PDT 24
Peak memory 160764 kb
Host smart-3b2c040e-e199-4115-8b70-44e3a5d9ffdc
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2239116634 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.2239116634
Directory /workspace/14.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.484431444
Short name T86
Test name
Test status
Simulation time 336702010000 ps
CPU time 755.73 seconds
Started Jul 10 05:51:37 PM PDT 24
Finished Jul 10 06:23:22 PM PDT 24
Peak memory 160792 kb
Host smart-2cb2de6b-f74e-4a38-824d-1a8b544a1597
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=484431444 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.484431444
Directory /workspace/15.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.572553128
Short name T100
Test name
Test status
Simulation time 336927690000 ps
CPU time 648.56 seconds
Started Jul 10 05:51:39 PM PDT 24
Finished Jul 10 06:18:26 PM PDT 24
Peak memory 160784 kb
Host smart-05760709-b79f-4343-9ef6-33b88be42073
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=572553128 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.572553128
Directory /workspace/16.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.3187103727
Short name T109
Test name
Test status
Simulation time 337123130000 ps
CPU time 908.79 seconds
Started Jul 10 05:51:42 PM PDT 24
Finished Jul 10 06:29:43 PM PDT 24
Peak memory 160808 kb
Host smart-e43bf109-e307-45ae-8f2c-33340173c805
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3187103727 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.3187103727
Directory /workspace/17.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.119748894
Short name T77
Test name
Test status
Simulation time 336902990000 ps
CPU time 782.37 seconds
Started Jul 10 05:51:41 PM PDT 24
Finished Jul 10 06:23:31 PM PDT 24
Peak memory 160796 kb
Host smart-157dc977-2525-4f41-bc45-3d4e8f8ec8bd
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=119748894 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.119748894
Directory /workspace/18.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.353687967
Short name T108
Test name
Test status
Simulation time 336692890000 ps
CPU time 801.45 seconds
Started Jul 10 05:51:45 PM PDT 24
Finished Jul 10 06:24:51 PM PDT 24
Peak memory 160800 kb
Host smart-8d888606-e20f-4062-8294-4181aae59c76
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=353687967 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.353687967
Directory /workspace/19.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.1456094962
Short name T97
Test name
Test status
Simulation time 336488010000 ps
CPU time 821.42 seconds
Started Jul 10 05:51:34 PM PDT 24
Finished Jul 10 06:24:46 PM PDT 24
Peak memory 160796 kb
Host smart-7db9413f-0279-4d33-8945-4de93bbf3ac9
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1456094962 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.1456094962
Directory /workspace/2.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.3334849608
Short name T95
Test name
Test status
Simulation time 336458990000 ps
CPU time 663.04 seconds
Started Jul 10 05:51:49 PM PDT 24
Finished Jul 10 06:19:49 PM PDT 24
Peak memory 160808 kb
Host smart-65f6bb42-28d5-41d6-9ea0-0892711a038d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3334849608 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.3334849608
Directory /workspace/20.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.2067687521
Short name T71
Test name
Test status
Simulation time 336620110000 ps
CPU time 694.08 seconds
Started Jul 10 05:51:49 PM PDT 24
Finished Jul 10 06:20:46 PM PDT 24
Peak memory 160892 kb
Host smart-0bc0ee60-a6e9-424e-a156-34034f828385
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2067687521 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.2067687521
Directory /workspace/21.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.1976619872
Short name T19
Test name
Test status
Simulation time 336471110000 ps
CPU time 761.52 seconds
Started Jul 10 05:51:45 PM PDT 24
Finished Jul 10 06:22:54 PM PDT 24
Peak memory 160724 kb
Host smart-0d65fbb0-31ae-46ad-a333-e6b68e82931c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1976619872 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.1976619872
Directory /workspace/22.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.786071965
Short name T81
Test name
Test status
Simulation time 337092090000 ps
CPU time 810.24 seconds
Started Jul 10 05:51:43 PM PDT 24
Finished Jul 10 06:24:52 PM PDT 24
Peak memory 160808 kb
Host smart-8c1951aa-0c7c-4dd5-9005-18503df56066
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=786071965 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.786071965
Directory /workspace/23.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.138984042
Short name T110
Test name
Test status
Simulation time 336886970000 ps
CPU time 882.07 seconds
Started Jul 10 05:51:46 PM PDT 24
Finished Jul 10 06:27:55 PM PDT 24
Peak memory 160816 kb
Host smart-591d1868-ecbd-42e9-8025-a4d45cfe1a2d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=138984042 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.138984042
Directory /workspace/24.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.1424409079
Short name T107
Test name
Test status
Simulation time 337054190000 ps
CPU time 795.73 seconds
Started Jul 10 05:51:45 PM PDT 24
Finished Jul 10 06:24:48 PM PDT 24
Peak memory 160800 kb
Host smart-528d2923-4a26-4d99-a2e0-419b25fe4531
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1424409079 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.1424409079
Directory /workspace/25.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.687272381
Short name T99
Test name
Test status
Simulation time 336733530000 ps
CPU time 850.07 seconds
Started Jul 10 05:51:44 PM PDT 24
Finished Jul 10 06:25:55 PM PDT 24
Peak memory 160800 kb
Host smart-7c4b17f0-c735-437f-8a75-20fdae23c744
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=687272381 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.687272381
Directory /workspace/26.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.718707842
Short name T73
Test name
Test status
Simulation time 336497610000 ps
CPU time 873.29 seconds
Started Jul 10 05:51:44 PM PDT 24
Finished Jul 10 06:26:28 PM PDT 24
Peak memory 160812 kb
Host smart-fed394aa-251e-4fb2-8efe-fc1638758bd9
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=718707842 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.718707842
Directory /workspace/27.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.2752560647
Short name T79
Test name
Test status
Simulation time 336733970000 ps
CPU time 760.97 seconds
Started Jul 10 05:51:43 PM PDT 24
Finished Jul 10 06:23:03 PM PDT 24
Peak memory 160724 kb
Host smart-6343d976-a922-4295-bfe3-27d5e70813b1
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2752560647 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.2752560647
Directory /workspace/28.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.152923606
Short name T106
Test name
Test status
Simulation time 336285090000 ps
CPU time 824.46 seconds
Started Jul 10 05:51:45 PM PDT 24
Finished Jul 10 06:25:26 PM PDT 24
Peak memory 160740 kb
Host smart-f7f6543e-756f-4632-ac5d-777471881246
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=152923606 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.152923606
Directory /workspace/29.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.2229598647
Short name T92
Test name
Test status
Simulation time 336542870000 ps
CPU time 833.87 seconds
Started Jul 10 05:51:36 PM PDT 24
Finished Jul 10 06:25:50 PM PDT 24
Peak memory 160796 kb
Host smart-2c22d45c-856c-4738-b6d6-754d88cb6b0e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2229598647 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.2229598647
Directory /workspace/3.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.1761564291
Short name T5
Test name
Test status
Simulation time 336536210000 ps
CPU time 810.1 seconds
Started Jul 10 05:51:44 PM PDT 24
Finished Jul 10 06:24:34 PM PDT 24
Peak memory 160804 kb
Host smart-4a4f61d2-e3da-48d3-a17a-e30467af98ed
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1761564291 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.1761564291
Directory /workspace/30.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.1798360347
Short name T15
Test name
Test status
Simulation time 336642890000 ps
CPU time 891.39 seconds
Started Jul 10 05:51:46 PM PDT 24
Finished Jul 10 06:28:52 PM PDT 24
Peak memory 160796 kb
Host smart-1d1764e8-6388-43b9-bfa3-2f4d1307de7b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1798360347 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.1798360347
Directory /workspace/31.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.3955861436
Short name T82
Test name
Test status
Simulation time 336927270000 ps
CPU time 859.75 seconds
Started Jul 10 05:51:46 PM PDT 24
Finished Jul 10 06:26:55 PM PDT 24
Peak memory 160808 kb
Host smart-1e4ea28d-eada-44dc-8fd3-2b070fb6ad63
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3955861436 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.3955861436
Directory /workspace/32.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.3668980399
Short name T104
Test name
Test status
Simulation time 336795270000 ps
CPU time 794.41 seconds
Started Jul 10 05:51:42 PM PDT 24
Finished Jul 10 06:24:00 PM PDT 24
Peak memory 160916 kb
Host smart-6c2781fe-8bd2-4ff5-894e-8d32ed272ed6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3668980399 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.3668980399
Directory /workspace/33.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.3472322241
Short name T96
Test name
Test status
Simulation time 336810130000 ps
CPU time 740.79 seconds
Started Jul 10 05:51:47 PM PDT 24
Finished Jul 10 06:21:58 PM PDT 24
Peak memory 160748 kb
Host smart-d4473eed-ac0f-4623-8697-5081d2c4b954
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3472322241 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.3472322241
Directory /workspace/34.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.2287802519
Short name T17
Test name
Test status
Simulation time 336627210000 ps
CPU time 1035.2 seconds
Started Jul 10 05:51:42 PM PDT 24
Finished Jul 10 06:34:38 PM PDT 24
Peak memory 160820 kb
Host smart-4652a6af-82a9-4e61-afa9-ab33e2d36a9b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2287802519 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.2287802519
Directory /workspace/35.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.3634963592
Short name T88
Test name
Test status
Simulation time 336521810000 ps
CPU time 796.79 seconds
Started Jul 10 05:51:47 PM PDT 24
Finished Jul 10 06:24:17 PM PDT 24
Peak memory 160824 kb
Host smart-bfe47886-c861-4961-a1aa-2c82806f767f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3634963592 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.3634963592
Directory /workspace/36.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.1656713779
Short name T89
Test name
Test status
Simulation time 336946270000 ps
CPU time 736.24 seconds
Started Jul 10 05:51:44 PM PDT 24
Finished Jul 10 06:21:26 PM PDT 24
Peak memory 160804 kb
Host smart-a47b8936-196d-4f70-a088-49c95e97a935
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1656713779 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.1656713779
Directory /workspace/37.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.1014830039
Short name T80
Test name
Test status
Simulation time 336547090000 ps
CPU time 880.4 seconds
Started Jul 10 05:51:46 PM PDT 24
Finished Jul 10 06:28:37 PM PDT 24
Peak memory 160808 kb
Host smart-9b0f5424-d210-4cd1-b5e8-66008f35fffc
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1014830039 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.1014830039
Directory /workspace/38.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.3352133939
Short name T87
Test name
Test status
Simulation time 336621290000 ps
CPU time 803.64 seconds
Started Jul 10 05:51:44 PM PDT 24
Finished Jul 10 06:24:21 PM PDT 24
Peak memory 160828 kb
Host smart-085331a4-df73-4410-be49-ae6a65ce7621
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3352133939 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.3352133939
Directory /workspace/39.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.2921977769
Short name T85
Test name
Test status
Simulation time 336843670000 ps
CPU time 816.34 seconds
Started Jul 10 05:51:35 PM PDT 24
Finished Jul 10 06:24:23 PM PDT 24
Peak memory 160796 kb
Host smart-94a5b679-d466-4ea5-b42d-63b89265113f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2921977769 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.2921977769
Directory /workspace/4.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.479985763
Short name T93
Test name
Test status
Simulation time 336414710000 ps
CPU time 985.64 seconds
Started Jul 10 05:51:49 PM PDT 24
Finished Jul 10 06:33:52 PM PDT 24
Peak memory 160800 kb
Host smart-99eb9962-203b-4896-91f5-edc30f050d19
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=479985763 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.479985763
Directory /workspace/40.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.8565209
Short name T83
Test name
Test status
Simulation time 336294350000 ps
CPU time 752.77 seconds
Started Jul 10 05:51:45 PM PDT 24
Finished Jul 10 06:22:53 PM PDT 24
Peak memory 160792 kb
Host smart-74344c34-3b09-4e95-8ffc-5212de434de7
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=8565209 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.8565209
Directory /workspace/41.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.1259263211
Short name T90
Test name
Test status
Simulation time 336442690000 ps
CPU time 907.54 seconds
Started Jul 10 05:51:47 PM PDT 24
Finished Jul 10 06:29:40 PM PDT 24
Peak memory 160808 kb
Host smart-6d9aa730-2425-4ce5-83e7-7acc8244a6de
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1259263211 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.1259263211
Directory /workspace/42.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.1691830008
Short name T84
Test name
Test status
Simulation time 336634570000 ps
CPU time 788.93 seconds
Started Jul 10 05:51:44 PM PDT 24
Finished Jul 10 06:23:57 PM PDT 24
Peak memory 160808 kb
Host smart-13178ed3-8e50-4123-8523-e4b7fb626fb0
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1691830008 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.1691830008
Directory /workspace/43.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.2220980618
Short name T14
Test name
Test status
Simulation time 336993870000 ps
CPU time 885.51 seconds
Started Jul 10 05:51:45 PM PDT 24
Finished Jul 10 06:29:18 PM PDT 24
Peak memory 160824 kb
Host smart-21c5ad67-a9cd-48b4-b51d-c10e74e18cb2
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2220980618 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.2220980618
Directory /workspace/44.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.1330809916
Short name T78
Test name
Test status
Simulation time 336797670000 ps
CPU time 803.11 seconds
Started Jul 10 05:51:45 PM PDT 24
Finished Jul 10 06:24:53 PM PDT 24
Peak memory 160808 kb
Host smart-15602b9f-7db0-4490-878d-fd39ba84f258
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1330809916 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.1330809916
Directory /workspace/45.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.3539037664
Short name T105
Test name
Test status
Simulation time 336397110000 ps
CPU time 750.03 seconds
Started Jul 10 05:51:46 PM PDT 24
Finished Jul 10 06:22:59 PM PDT 24
Peak memory 160808 kb
Host smart-72be867d-3152-4a69-9607-85cf4c677f32
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3539037664 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.3539037664
Directory /workspace/46.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.2042075771
Short name T6
Test name
Test status
Simulation time 336357790000 ps
CPU time 773.01 seconds
Started Jul 10 05:51:45 PM PDT 24
Finished Jul 10 06:23:21 PM PDT 24
Peak memory 160832 kb
Host smart-d23b9f67-ba7e-48f1-83d5-977095bd3643
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2042075771 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.2042075771
Directory /workspace/47.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.4088235048
Short name T18
Test name
Test status
Simulation time 336346670000 ps
CPU time 872.95 seconds
Started Jul 10 05:51:43 PM PDT 24
Finished Jul 10 06:28:26 PM PDT 24
Peak memory 160808 kb
Host smart-ca43f62e-b216-4ed3-83df-761377cb5005
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4088235048 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.4088235048
Directory /workspace/48.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.4058299158
Short name T98
Test name
Test status
Simulation time 336758170000 ps
CPU time 870.72 seconds
Started Jul 10 05:51:44 PM PDT 24
Finished Jul 10 06:28:22 PM PDT 24
Peak memory 160824 kb
Host smart-eebda100-f591-488f-98da-945b7a43e255
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4058299158 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.4058299158
Directory /workspace/49.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.2151708389
Short name T102
Test name
Test status
Simulation time 336365210000 ps
CPU time 831.54 seconds
Started Jul 10 05:51:35 PM PDT 24
Finished Jul 10 06:25:33 PM PDT 24
Peak memory 160812 kb
Host smart-9ddc63dd-ac93-47a5-983d-94006594b86b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2151708389 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.2151708389
Directory /workspace/5.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.2406185137
Short name T103
Test name
Test status
Simulation time 336753870000 ps
CPU time 806.82 seconds
Started Jul 10 05:51:34 PM PDT 24
Finished Jul 10 06:23:53 PM PDT 24
Peak memory 160796 kb
Host smart-14eb264d-19ca-43c4-b731-11f313b5f685
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2406185137 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.2406185137
Directory /workspace/6.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.3813545562
Short name T72
Test name
Test status
Simulation time 336610990000 ps
CPU time 688.16 seconds
Started Jul 10 05:51:36 PM PDT 24
Finished Jul 10 06:19:53 PM PDT 24
Peak memory 160880 kb
Host smart-da94a0d0-cf4e-498c-bbf6-fe53f53317ff
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3813545562 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.3813545562
Directory /workspace/7.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.594769525
Short name T4
Test name
Test status
Simulation time 337058850000 ps
CPU time 763.37 seconds
Started Jul 10 05:51:40 PM PDT 24
Finished Jul 10 06:22:26 PM PDT 24
Peak memory 160788 kb
Host smart-39f2d893-b8e1-4176-a378-3244c6ae10c0
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=594769525 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.594769525
Directory /workspace/8.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.1758017666
Short name T75
Test name
Test status
Simulation time 337049330000 ps
CPU time 762.44 seconds
Started Jul 10 05:51:37 PM PDT 24
Finished Jul 10 06:22:55 PM PDT 24
Peak memory 160756 kb
Host smart-1d9e5269-820c-4294-afaa-9f4ffcd358da
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1758017666 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.1758017666
Directory /workspace/9.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.4279046660
Short name T187
Test name
Test status
Simulation time 336371450000 ps
CPU time 752.94 seconds
Started Jul 10 05:52:01 PM PDT 24
Finished Jul 10 06:23:18 PM PDT 24
Peak memory 160804 kb
Host smart-3c05f77d-7c22-4b38-8192-b3b1648f8034
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4279046660 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.4279046660
Directory /workspace/0.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.1227747115
Short name T174
Test name
Test status
Simulation time 337094250000 ps
CPU time 804.97 seconds
Started Jul 10 05:52:01 PM PDT 24
Finished Jul 10 06:25:05 PM PDT 24
Peak memory 160744 kb
Host smart-e72ee613-3fba-4cfd-a24b-b9f83534d6f4
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1227747115 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.1227747115
Directory /workspace/1.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.3318909587
Short name T192
Test name
Test status
Simulation time 336385790000 ps
CPU time 900.15 seconds
Started Jul 10 05:52:08 PM PDT 24
Finished Jul 10 06:29:41 PM PDT 24
Peak memory 160812 kb
Host smart-2b7efb17-1a30-4384-ba57-8c2d0e5cb038
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3318909587 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.3318909587
Directory /workspace/10.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.1672282415
Short name T173
Test name
Test status
Simulation time 336429590000 ps
CPU time 990.06 seconds
Started Jul 10 05:52:10 PM PDT 24
Finished Jul 10 06:33:56 PM PDT 24
Peak memory 160812 kb
Host smart-9a411d89-9b4d-45c0-8880-36c904201b7e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1672282415 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.1672282415
Directory /workspace/11.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.3257968573
Short name T189
Test name
Test status
Simulation time 336537990000 ps
CPU time 729.25 seconds
Started Jul 10 05:52:10 PM PDT 24
Finished Jul 10 06:22:10 PM PDT 24
Peak memory 160864 kb
Host smart-9e66f153-7615-48e4-9b28-8ecdb5295a1a
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3257968573 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.3257968573
Directory /workspace/13.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.4065152653
Short name T171
Test name
Test status
Simulation time 336377570000 ps
CPU time 874.19 seconds
Started Jul 10 05:52:08 PM PDT 24
Finished Jul 10 06:29:25 PM PDT 24
Peak memory 160812 kb
Host smart-49b05513-1a56-4801-80f6-b32cb3613580
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4065152653 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.4065152653
Directory /workspace/14.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.3877916426
Short name T175
Test name
Test status
Simulation time 336654290000 ps
CPU time 1025.4 seconds
Started Jul 10 05:52:09 PM PDT 24
Finished Jul 10 06:35:12 PM PDT 24
Peak memory 160824 kb
Host smart-dca5ebb6-c845-477d-b316-b7dc8b1563f2
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3877916426 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.3877916426
Directory /workspace/15.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.3871460390
Short name T168
Test name
Test status
Simulation time 336926130000 ps
CPU time 992.03 seconds
Started Jul 10 05:52:10 PM PDT 24
Finished Jul 10 06:33:35 PM PDT 24
Peak memory 160820 kb
Host smart-ee7ac584-2948-4c6e-b06d-fca8cbf09f92
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3871460390 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.3871460390
Directory /workspace/16.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.3706689393
Short name T194
Test name
Test status
Simulation time 336754690000 ps
CPU time 804.04 seconds
Started Jul 10 05:52:12 PM PDT 24
Finished Jul 10 06:24:48 PM PDT 24
Peak memory 160808 kb
Host smart-0bcdd4cc-e0f8-4838-bdec-e28b755babb3
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3706689393 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.3706689393
Directory /workspace/17.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.2735200584
Short name T161
Test name
Test status
Simulation time 336653650000 ps
CPU time 788.91 seconds
Started Jul 10 05:52:03 PM PDT 24
Finished Jul 10 06:24:39 PM PDT 24
Peak memory 160812 kb
Host smart-abdec499-536f-4cd5-96bd-50ce52e7a409
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2735200584 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.2735200584
Directory /workspace/18.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.803744876
Short name T28
Test name
Test status
Simulation time 336435170000 ps
CPU time 832.62 seconds
Started Jul 10 05:52:05 PM PDT 24
Finished Jul 10 06:25:36 PM PDT 24
Peak memory 160804 kb
Host smart-7646f61a-a958-426a-857a-20b62f87595d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=803744876 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.803744876
Directory /workspace/19.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.1660469145
Short name T167
Test name
Test status
Simulation time 336995090000 ps
CPU time 950.29 seconds
Started Jul 10 05:52:00 PM PDT 24
Finished Jul 10 06:31:00 PM PDT 24
Peak memory 160804 kb
Host smart-0859abee-9908-43df-b8f0-7fc5439598af
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1660469145 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.1660469145
Directory /workspace/2.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.1574212355
Short name T182
Test name
Test status
Simulation time 336586750000 ps
CPU time 722.88 seconds
Started Jul 10 05:52:03 PM PDT 24
Finished Jul 10 06:21:14 PM PDT 24
Peak memory 160812 kb
Host smart-57d89bf5-b48e-49c2-8eba-04b3b68fb1a5
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1574212355 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.1574212355
Directory /workspace/20.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3173276827
Short name T169
Test name
Test status
Simulation time 337060290000 ps
CPU time 940.65 seconds
Started Jul 10 05:52:08 PM PDT 24
Finished Jul 10 06:31:07 PM PDT 24
Peak memory 160812 kb
Host smart-1b96ebfd-7548-46e8-863c-15d57a7b4620
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3173276827 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.3173276827
Directory /workspace/21.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.651456635
Short name T23
Test name
Test status
Simulation time 336405230000 ps
CPU time 767.2 seconds
Started Jul 10 05:52:04 PM PDT 24
Finished Jul 10 06:23:29 PM PDT 24
Peak memory 160788 kb
Host smart-1c5cde6e-9960-4d7a-8aba-7b05e02c82ea
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=651456635 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.651456635
Directory /workspace/22.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.1811904055
Short name T166
Test name
Test status
Simulation time 337145270000 ps
CPU time 766.54 seconds
Started Jul 10 05:52:04 PM PDT 24
Finished Jul 10 06:23:23 PM PDT 24
Peak memory 160728 kb
Host smart-b6fe0fc5-d41a-4ef9-8da7-325dd91c889c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1811904055 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.1811904055
Directory /workspace/23.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.545394153
Short name T30
Test name
Test status
Simulation time 336452890000 ps
CPU time 822.55 seconds
Started Jul 10 05:52:11 PM PDT 24
Finished Jul 10 06:25:22 PM PDT 24
Peak memory 160800 kb
Host smart-fb4e195c-78d4-45dc-8bbf-4bec170e9d1f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=545394153 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.545394153
Directory /workspace/24.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.626889752
Short name T165
Test name
Test status
Simulation time 336759510000 ps
CPU time 815.35 seconds
Started Jul 10 05:52:12 PM PDT 24
Finished Jul 10 06:25:29 PM PDT 24
Peak memory 160800 kb
Host smart-be677688-571b-43bc-b3b9-1ab9898550dd
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=626889752 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.626889752
Directory /workspace/25.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.2406079540
Short name T26
Test name
Test status
Simulation time 336866690000 ps
CPU time 750.4 seconds
Started Jul 10 05:52:10 PM PDT 24
Finished Jul 10 06:22:56 PM PDT 24
Peak memory 160808 kb
Host smart-4698ff59-3043-4f52-9f3e-f0b008e64403
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2406079540 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.2406079540
Directory /workspace/26.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.111437669
Short name T195
Test name
Test status
Simulation time 337016410000 ps
CPU time 733.65 seconds
Started Jul 10 05:52:06 PM PDT 24
Finished Jul 10 06:22:20 PM PDT 24
Peak memory 160808 kb
Host smart-1dae6ecf-087b-4c46-be89-f0d978ad6bdd
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=111437669 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.111437669
Directory /workspace/27.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.1090449335
Short name T29
Test name
Test status
Simulation time 336936150000 ps
CPU time 986.44 seconds
Started Jul 10 05:52:07 PM PDT 24
Finished Jul 10 06:33:08 PM PDT 24
Peak memory 160820 kb
Host smart-4ce18115-6d57-4fff-9061-1a03ff468f37
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1090449335 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.1090449335
Directory /workspace/28.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.375817738
Short name T198
Test name
Test status
Simulation time 336499270000 ps
CPU time 793.1 seconds
Started Jul 10 05:52:07 PM PDT 24
Finished Jul 10 06:24:53 PM PDT 24
Peak memory 160812 kb
Host smart-49ec4ecc-0df4-44c1-8d64-64e56ab4d451
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=375817738 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.375817738
Directory /workspace/29.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.1934530922
Short name T193
Test name
Test status
Simulation time 336986290000 ps
CPU time 818.37 seconds
Started Jul 10 05:52:12 PM PDT 24
Finished Jul 10 06:25:19 PM PDT 24
Peak memory 160800 kb
Host smart-2dda7fe1-1644-461c-b287-ef7238f1d4ac
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1934530922 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.1934530922
Directory /workspace/3.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.3832003795
Short name T191
Test name
Test status
Simulation time 336409670000 ps
CPU time 768.37 seconds
Started Jul 10 05:52:03 PM PDT 24
Finished Jul 10 06:23:36 PM PDT 24
Peak memory 160812 kb
Host smart-0170f7cf-5b6f-4145-8f52-bddd64523a59
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3832003795 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.3832003795
Directory /workspace/30.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.1738481245
Short name T22
Test name
Test status
Simulation time 336913690000 ps
CPU time 780.33 seconds
Started Jul 10 05:52:03 PM PDT 24
Finished Jul 10 06:24:08 PM PDT 24
Peak memory 160812 kb
Host smart-8e5e78a6-ec5a-4f43-b520-893727dcfa77
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1738481245 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.1738481245
Directory /workspace/31.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.2650098676
Short name T200
Test name
Test status
Simulation time 336298850000 ps
CPU time 938.1 seconds
Started Jul 10 05:52:11 PM PDT 24
Finished Jul 10 06:31:35 PM PDT 24
Peak memory 160820 kb
Host smart-363d727d-67f0-42c4-a7b3-3b195ce44e2c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2650098676 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.2650098676
Directory /workspace/32.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.836543451
Short name T179
Test name
Test status
Simulation time 336624170000 ps
CPU time 866.1 seconds
Started Jul 10 05:52:06 PM PDT 24
Finished Jul 10 06:28:09 PM PDT 24
Peak memory 160744 kb
Host smart-a9c15a5e-e8ca-42f2-91fc-652a3402d404
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=836543451 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.836543451
Directory /workspace/33.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.1929281845
Short name T186
Test name
Test status
Simulation time 336454470000 ps
CPU time 885.85 seconds
Started Jul 10 05:52:09 PM PDT 24
Finished Jul 10 06:29:23 PM PDT 24
Peak memory 160812 kb
Host smart-9f9b4e70-fbee-45d6-9c8d-555fa835c73b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1929281845 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.1929281845
Directory /workspace/34.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.3877302012
Short name T177
Test name
Test status
Simulation time 336527830000 ps
CPU time 867.56 seconds
Started Jul 10 05:52:07 PM PDT 24
Finished Jul 10 06:28:04 PM PDT 24
Peak memory 160752 kb
Host smart-eb668ab6-c7a8-4ac5-8f71-dc4f8206e33c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3877302012 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.3877302012
Directory /workspace/35.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.514763768
Short name T176
Test name
Test status
Simulation time 336853410000 ps
CPU time 782.01 seconds
Started Jul 10 05:52:10 PM PDT 24
Finished Jul 10 06:24:20 PM PDT 24
Peak memory 160804 kb
Host smart-56a2d23f-7993-46b3-89e5-2dc5d11dea5f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=514763768 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.514763768
Directory /workspace/36.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.134316800
Short name T184
Test name
Test status
Simulation time 336592350000 ps
CPU time 871.8 seconds
Started Jul 10 05:52:08 PM PDT 24
Finished Jul 10 06:28:47 PM PDT 24
Peak memory 160804 kb
Host smart-74387acf-6511-4e87-9c2c-017b95ca3e34
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=134316800 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.134316800
Directory /workspace/37.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.2747484531
Short name T27
Test name
Test status
Simulation time 336589390000 ps
CPU time 1029.23 seconds
Started Jul 10 05:52:12 PM PDT 24
Finished Jul 10 06:35:15 PM PDT 24
Peak memory 160824 kb
Host smart-fc242643-eb1b-4457-8558-0a62703d48f6
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2747484531 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.2747484531
Directory /workspace/38.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.679080825
Short name T25
Test name
Test status
Simulation time 337055190000 ps
CPU time 1021.58 seconds
Started Jul 10 05:52:12 PM PDT 24
Finished Jul 10 06:35:22 PM PDT 24
Peak memory 160816 kb
Host smart-286fd945-c850-41ed-ab34-9dbea7818321
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=679080825 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.679080825
Directory /workspace/39.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.1936400729
Short name T172
Test name
Test status
Simulation time 336652330000 ps
CPU time 905.48 seconds
Started Jul 10 05:52:12 PM PDT 24
Finished Jul 10 06:29:47 PM PDT 24
Peak memory 160804 kb
Host smart-ada71ac0-e134-44ae-91e3-7b6b6fb4120d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1936400729 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.1936400729
Directory /workspace/4.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.1303190539
Short name T188
Test name
Test status
Simulation time 337055930000 ps
CPU time 891.84 seconds
Started Jul 10 05:52:07 PM PDT 24
Finished Jul 10 06:28:41 PM PDT 24
Peak memory 160828 kb
Host smart-e58f4a52-d4c2-42d0-874f-d7db173559ba
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1303190539 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.1303190539
Directory /workspace/40.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.1871910951
Short name T185
Test name
Test status
Simulation time 336694250000 ps
CPU time 977.85 seconds
Started Jul 10 05:52:10 PM PDT 24
Finished Jul 10 06:34:04 PM PDT 24
Peak memory 160812 kb
Host smart-91b2e0ad-8622-49e9-a309-3ad02054de21
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1871910951 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.1871910951
Directory /workspace/41.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.2154829119
Short name T24
Test name
Test status
Simulation time 336494750000 ps
CPU time 772.19 seconds
Started Jul 10 05:52:06 PM PDT 24
Finished Jul 10 06:23:41 PM PDT 24
Peak memory 160228 kb
Host smart-4493f1f8-57cb-44b1-92ef-91fc383f905f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2154829119 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.2154829119
Directory /workspace/42.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.3063744795
Short name T164
Test name
Test status
Simulation time 336635870000 ps
CPU time 855.05 seconds
Started Jul 10 05:52:03 PM PDT 24
Finished Jul 10 06:27:07 PM PDT 24
Peak memory 160812 kb
Host smart-69c53b8c-d9be-40c6-9fff-d3a04c90cff7
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3063744795 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.3063744795
Directory /workspace/43.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.1474572402
Short name T190
Test name
Test status
Simulation time 336669890000 ps
CPU time 797.69 seconds
Started Jul 10 05:52:14 PM PDT 24
Finished Jul 10 06:24:38 PM PDT 24
Peak memory 160824 kb
Host smart-cbbd8f22-e2ee-4e5e-ac11-db20d0a78b32
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1474572402 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.1474572402
Directory /workspace/44.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.3954332333
Short name T199
Test name
Test status
Simulation time 336787690000 ps
CPU time 765.5 seconds
Started Jul 10 05:52:06 PM PDT 24
Finished Jul 10 06:23:32 PM PDT 24
Peak memory 160084 kb
Host smart-a5bbfac9-a911-40d7-a2d1-f88856f3089b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3954332333 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.3954332333
Directory /workspace/45.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.3456540413
Short name T180
Test name
Test status
Simulation time 336639430000 ps
CPU time 780.28 seconds
Started Jul 10 05:52:04 PM PDT 24
Finished Jul 10 06:24:04 PM PDT 24
Peak memory 160828 kb
Host smart-e6d76295-2638-43c8-acf3-905875a5f6b2
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3456540413 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.3456540413
Directory /workspace/46.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.1530880654
Short name T181
Test name
Test status
Simulation time 336936610000 ps
CPU time 933.72 seconds
Started Jul 10 05:52:11 PM PDT 24
Finished Jul 10 06:30:52 PM PDT 24
Peak memory 160812 kb
Host smart-309082ac-c760-4f58-9541-2271acc0bacb
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1530880654 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.1530880654
Directory /workspace/47.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.240712921
Short name T163
Test name
Test status
Simulation time 337043210000 ps
CPU time 734.49 seconds
Started Jul 10 05:52:06 PM PDT 24
Finished Jul 10 06:22:28 PM PDT 24
Peak memory 160808 kb
Host smart-369f6dc7-9612-42d4-ab8c-9627cded967e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=240712921 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.240712921
Directory /workspace/48.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.3181990146
Short name T178
Test name
Test status
Simulation time 336597170000 ps
CPU time 989.22 seconds
Started Jul 10 05:52:08 PM PDT 24
Finished Jul 10 06:33:29 PM PDT 24
Peak memory 160820 kb
Host smart-1934a047-e42c-4ed7-9a89-addb94f20619
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3181990146 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.3181990146
Directory /workspace/49.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.3939977791
Short name T183
Test name
Test status
Simulation time 336572810000 ps
CPU time 749.71 seconds
Started Jul 10 05:52:03 PM PDT 24
Finished Jul 10 06:22:49 PM PDT 24
Peak memory 160832 kb
Host smart-07588375-6bd8-4804-a519-db858426214d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3939977791 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.3939977791
Directory /workspace/5.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.1380788541
Short name T162
Test name
Test status
Simulation time 336406230000 ps
CPU time 736.38 seconds
Started Jul 10 05:52:04 PM PDT 24
Finished Jul 10 06:22:31 PM PDT 24
Peak memory 160820 kb
Host smart-4c1a632d-4ac9-4b7e-8fac-714187a03a1b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1380788541 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.1380788541
Directory /workspace/6.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.1361877544
Short name T170
Test name
Test status
Simulation time 336832070000 ps
CPU time 703.22 seconds
Started Jul 10 05:52:05 PM PDT 24
Finished Jul 10 06:21:36 PM PDT 24
Peak memory 160800 kb
Host smart-f932fdab-c203-4ca4-bb86-44e4b6933caa
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1361877544 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.1361877544
Directory /workspace/7.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.2556868252
Short name T197
Test name
Test status
Simulation time 336907250000 ps
CPU time 781.76 seconds
Started Jul 10 05:52:08 PM PDT 24
Finished Jul 10 06:24:08 PM PDT 24
Peak memory 160788 kb
Host smart-da8513b0-c510-4be0-9298-1edfd2c621c0
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2556868252 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.2556868252
Directory /workspace/8.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.3896658037
Short name T196
Test name
Test status
Simulation time 336804430000 ps
CPU time 799.92 seconds
Started Jul 10 05:52:08 PM PDT 24
Finished Jul 10 06:24:52 PM PDT 24
Peak memory 160820 kb
Host smart-edef8663-ae5d-498a-adbd-c9781a2419af
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3896658037 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.3896658037
Directory /workspace/9.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.2755988702
Short name T125
Test name
Test status
Simulation time 1387010000 ps
CPU time 3.99 seconds
Started Jul 10 05:51:50 PM PDT 24
Finished Jul 10 05:52:01 PM PDT 24
Peak memory 164964 kb
Host smart-45aa78ed-f01b-4e6c-afdf-badfd7f7c677
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2755988702 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.2755988702
Directory /workspace/0.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.3013588935
Short name T149
Test name
Test status
Simulation time 1511290000 ps
CPU time 4.15 seconds
Started Jul 10 05:51:53 PM PDT 24
Finished Jul 10 05:52:05 PM PDT 24
Peak memory 164912 kb
Host smart-763e0296-d540-4ab0-9fe2-723f8f4e0d6d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3013588935 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.3013588935
Directory /workspace/1.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.2694157428
Short name T131
Test name
Test status
Simulation time 1548990000 ps
CPU time 4.86 seconds
Started Jul 10 05:52:10 PM PDT 24
Finished Jul 10 05:52:26 PM PDT 24
Peak memory 164964 kb
Host smart-84d07e90-8c0a-4abe-a40d-197978b77bc0
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2694157428 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.2694157428
Directory /workspace/10.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.2288413531
Short name T139
Test name
Test status
Simulation time 1506450000 ps
CPU time 4.16 seconds
Started Jul 10 05:51:58 PM PDT 24
Finished Jul 10 05:52:11 PM PDT 24
Peak memory 164884 kb
Host smart-03dfb926-4bb4-4cad-a896-53f5a5e5ba97
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2288413531 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.2288413531
Directory /workspace/11.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.2033056899
Short name T120
Test name
Test status
Simulation time 1406090000 ps
CPU time 5.19 seconds
Started Jul 10 05:51:58 PM PDT 24
Finished Jul 10 05:52:12 PM PDT 24
Peak memory 164964 kb
Host smart-f46c154b-18c4-4596-85fd-130baf690ce1
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2033056899 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.2033056899
Directory /workspace/12.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.2067679697
Short name T142
Test name
Test status
Simulation time 1436550000 ps
CPU time 4.86 seconds
Started Jul 10 05:51:59 PM PDT 24
Finished Jul 10 05:52:13 PM PDT 24
Peak memory 164948 kb
Host smart-5dd62a52-5834-44e4-b07d-009ae6febb9c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2067679697 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.2067679697
Directory /workspace/13.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.308696138
Short name T137
Test name
Test status
Simulation time 1534410000 ps
CPU time 4.1 seconds
Started Jul 10 05:52:01 PM PDT 24
Finished Jul 10 05:52:13 PM PDT 24
Peak memory 164960 kb
Host smart-befa66cf-630c-4582-a036-9941b79a206e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=308696138 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.308696138
Directory /workspace/14.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.497086758
Short name T128
Test name
Test status
Simulation time 1430950000 ps
CPU time 5.43 seconds
Started Jul 10 05:52:00 PM PDT 24
Finished Jul 10 05:52:15 PM PDT 24
Peak memory 164960 kb
Host smart-ba6e8779-b06b-4f78-81d4-0aa13b712fa4
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=497086758 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.497086758
Directory /workspace/15.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.700206323
Short name T153
Test name
Test status
Simulation time 1382350000 ps
CPU time 4.82 seconds
Started Jul 10 05:52:06 PM PDT 24
Finished Jul 10 05:52:20 PM PDT 24
Peak memory 164960 kb
Host smart-23ef55b2-195b-487a-a80c-fa2bec0b41dd
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=700206323 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.700206323
Directory /workspace/16.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.2088016876
Short name T150
Test name
Test status
Simulation time 1557410000 ps
CPU time 4.28 seconds
Started Jul 10 05:51:58 PM PDT 24
Finished Jul 10 05:52:10 PM PDT 24
Peak memory 164912 kb
Host smart-90496683-976c-4257-96df-a3fa175355b2
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2088016876 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.2088016876
Directory /workspace/17.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.3716381993
Short name T156
Test name
Test status
Simulation time 1537730000 ps
CPU time 6.64 seconds
Started Jul 10 05:51:55 PM PDT 24
Finished Jul 10 05:52:11 PM PDT 24
Peak memory 164964 kb
Host smart-9282e59c-8cca-4f8d-b09f-901e9b6b8e30
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3716381993 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.3716381993
Directory /workspace/18.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.865719883
Short name T116
Test name
Test status
Simulation time 1548810000 ps
CPU time 5.74 seconds
Started Jul 10 05:51:59 PM PDT 24
Finished Jul 10 05:52:15 PM PDT 24
Peak memory 164964 kb
Host smart-1bc0d870-e287-4a1c-bbd9-74af4bd6c633
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=865719883 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.865719883
Directory /workspace/19.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.1582664292
Short name T132
Test name
Test status
Simulation time 1388150000 ps
CPU time 4.33 seconds
Started Jul 10 05:51:58 PM PDT 24
Finished Jul 10 05:52:10 PM PDT 24
Peak memory 164940 kb
Host smart-7e2db5c0-0a0a-40fd-82e2-2c5bdb418b83
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1582664292 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.1582664292
Directory /workspace/2.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.2802346692
Short name T112
Test name
Test status
Simulation time 1474450000 ps
CPU time 4.53 seconds
Started Jul 10 05:52:04 PM PDT 24
Finished Jul 10 05:52:16 PM PDT 24
Peak memory 164964 kb
Host smart-2452d00a-6dd6-4a52-8521-cf0ddb2a0181
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2802346692 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.2802346692
Directory /workspace/20.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3281646637
Short name T135
Test name
Test status
Simulation time 1468790000 ps
CPU time 5.02 seconds
Started Jul 10 05:52:05 PM PDT 24
Finished Jul 10 05:52:19 PM PDT 24
Peak memory 164968 kb
Host smart-40b51649-2de0-4921-8db1-5b73ad91209f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3281646637 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.3281646637
Directory /workspace/21.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.2935785106
Short name T119
Test name
Test status
Simulation time 1397850000 ps
CPU time 5.1 seconds
Started Jul 10 05:52:06 PM PDT 24
Finished Jul 10 05:52:19 PM PDT 24
Peak memory 164956 kb
Host smart-9f8672cf-0966-4acb-9393-4d742d8ef094
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2935785106 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.2935785106
Directory /workspace/22.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.2748627592
Short name T118
Test name
Test status
Simulation time 1540510000 ps
CPU time 4.55 seconds
Started Jul 10 05:52:01 PM PDT 24
Finished Jul 10 05:52:15 PM PDT 24
Peak memory 164912 kb
Host smart-a31a297e-fdee-4a39-ae3a-df4626942200
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2748627592 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.2748627592
Directory /workspace/23.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.3261704339
Short name T121
Test name
Test status
Simulation time 1580570000 ps
CPU time 5.27 seconds
Started Jul 10 05:52:00 PM PDT 24
Finished Jul 10 05:52:14 PM PDT 24
Peak memory 164888 kb
Host smart-7de29411-01f6-4c51-85cf-644890378cdb
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3261704339 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.3261704339
Directory /workspace/24.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.3890082286
Short name T141
Test name
Test status
Simulation time 1409090000 ps
CPU time 4.65 seconds
Started Jul 10 05:52:05 PM PDT 24
Finished Jul 10 05:52:19 PM PDT 24
Peak memory 164964 kb
Host smart-20384daa-56b5-4379-9e12-c184a2446091
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3890082286 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.3890082286
Directory /workspace/25.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.3077417428
Short name T114
Test name
Test status
Simulation time 1405290000 ps
CPU time 4.92 seconds
Started Jul 10 05:52:00 PM PDT 24
Finished Jul 10 05:52:14 PM PDT 24
Peak memory 164964 kb
Host smart-a3093d0f-2827-4e37-aede-8ac852693ab4
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3077417428 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.3077417428
Directory /workspace/26.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.3584040773
Short name T147
Test name
Test status
Simulation time 1524850000 ps
CPU time 5.11 seconds
Started Jul 10 05:51:58 PM PDT 24
Finished Jul 10 05:52:12 PM PDT 24
Peak memory 164932 kb
Host smart-746b2594-449e-40b1-9e70-7c9142caa506
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3584040773 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.3584040773
Directory /workspace/27.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.1530514865
Short name T151
Test name
Test status
Simulation time 1434770000 ps
CPU time 5.61 seconds
Started Jul 10 05:52:00 PM PDT 24
Finished Jul 10 05:52:16 PM PDT 24
Peak memory 164964 kb
Host smart-ae92aa76-9bcf-4725-8c19-de04d8c59256
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1530514865 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.1530514865
Directory /workspace/28.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.3410378498
Short name T143
Test name
Test status
Simulation time 1425150000 ps
CPU time 5.07 seconds
Started Jul 10 05:51:59 PM PDT 24
Finished Jul 10 05:52:14 PM PDT 24
Peak memory 164964 kb
Host smart-745f6ae7-7d7e-48e8-9962-2d66d1dfd4cf
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3410378498 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.3410378498
Directory /workspace/29.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.1088824023
Short name T115
Test name
Test status
Simulation time 1245510000 ps
CPU time 4.23 seconds
Started Jul 10 05:51:53 PM PDT 24
Finished Jul 10 05:52:05 PM PDT 24
Peak memory 164968 kb
Host smart-ac6ac6bb-5eb3-4e7b-aa63-236e46dfb7e0
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1088824023 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.1088824023
Directory /workspace/3.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.478982619
Short name T155
Test name
Test status
Simulation time 1584270000 ps
CPU time 4.89 seconds
Started Jul 10 05:52:02 PM PDT 24
Finished Jul 10 05:52:15 PM PDT 24
Peak memory 164960 kb
Host smart-f5371b72-f105-4a24-8af5-4b4ce58abd5d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=478982619 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.478982619
Directory /workspace/30.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.774142021
Short name T144
Test name
Test status
Simulation time 1202230000 ps
CPU time 4.65 seconds
Started Jul 10 05:51:57 PM PDT 24
Finished Jul 10 05:52:10 PM PDT 24
Peak memory 164960 kb
Host smart-3f56c0e8-509a-479f-b5e0-abbda2c676c9
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=774142021 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.774142021
Directory /workspace/31.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.1085237427
Short name T133
Test name
Test status
Simulation time 1253210000 ps
CPU time 3.81 seconds
Started Jul 10 05:52:05 PM PDT 24
Finished Jul 10 05:52:15 PM PDT 24
Peak memory 164964 kb
Host smart-f21d7e27-aeef-4c41-a725-930bc400d0a6
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1085237427 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.1085237427
Directory /workspace/32.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.1750020539
Short name T124
Test name
Test status
Simulation time 1246270000 ps
CPU time 4.25 seconds
Started Jul 10 05:51:56 PM PDT 24
Finished Jul 10 05:52:08 PM PDT 24
Peak memory 164912 kb
Host smart-b3ecea88-3d6d-4a16-9588-7373f6a7a1a8
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1750020539 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.1750020539
Directory /workspace/33.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.3019196831
Short name T136
Test name
Test status
Simulation time 1475670000 ps
CPU time 4.03 seconds
Started Jul 10 05:51:58 PM PDT 24
Finished Jul 10 05:52:10 PM PDT 24
Peak memory 164968 kb
Host smart-020d07f8-77d7-42a7-9eb3-857990be8c34
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3019196831 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.3019196831
Directory /workspace/34.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.2798773480
Short name T122
Test name
Test status
Simulation time 1585690000 ps
CPU time 5.17 seconds
Started Jul 10 05:52:06 PM PDT 24
Finished Jul 10 05:52:20 PM PDT 24
Peak memory 164920 kb
Host smart-178790fb-235f-4c8c-b52f-2b545427b8ce
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2798773480 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.2798773480
Directory /workspace/35.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.2805637388
Short name T145
Test name
Test status
Simulation time 1538210000 ps
CPU time 4.73 seconds
Started Jul 10 05:52:09 PM PDT 24
Finished Jul 10 05:52:24 PM PDT 24
Peak memory 164964 kb
Host smart-493b0ae0-6045-4da7-ad5a-b7359d79aad6
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2805637388 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.2805637388
Directory /workspace/36.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.2179135223
Short name T113
Test name
Test status
Simulation time 1363490000 ps
CPU time 4.45 seconds
Started Jul 10 05:51:59 PM PDT 24
Finished Jul 10 05:52:11 PM PDT 24
Peak memory 164960 kb
Host smart-1d9c0dea-ca1d-47d3-abcf-0f90b4710f08
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2179135223 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.2179135223
Directory /workspace/37.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.3481225157
Short name T127
Test name
Test status
Simulation time 1432930000 ps
CPU time 4.33 seconds
Started Jul 10 05:51:58 PM PDT 24
Finished Jul 10 05:52:11 PM PDT 24
Peak memory 164968 kb
Host smart-7d540e9e-52e3-4767-99a8-47059213518d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3481225157 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.3481225157
Directory /workspace/38.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.4288322831
Short name T157
Test name
Test status
Simulation time 1476670000 ps
CPU time 4.72 seconds
Started Jul 10 05:52:06 PM PDT 24
Finished Jul 10 05:52:19 PM PDT 24
Peak memory 164920 kb
Host smart-4c23fd16-f85f-4a88-8b24-e15f4734709d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4288322831 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.4288322831
Directory /workspace/39.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.777211534
Short name T129
Test name
Test status
Simulation time 1615710000 ps
CPU time 4.96 seconds
Started Jul 10 05:51:58 PM PDT 24
Finished Jul 10 05:52:11 PM PDT 24
Peak memory 164864 kb
Host smart-a8c022ee-474f-4004-bc80-2d3daf0fa422
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=777211534 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.777211534
Directory /workspace/4.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.2651523833
Short name T130
Test name
Test status
Simulation time 1455930000 ps
CPU time 5.19 seconds
Started Jul 10 05:52:06 PM PDT 24
Finished Jul 10 05:52:20 PM PDT 24
Peak memory 164884 kb
Host smart-ae9554cc-494e-4524-aee2-7663d0f3659a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2651523833 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.2651523833
Directory /workspace/40.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.1541234084
Short name T148
Test name
Test status
Simulation time 1500330000 ps
CPU time 5.23 seconds
Started Jul 10 05:52:01 PM PDT 24
Finished Jul 10 05:52:15 PM PDT 24
Peak memory 164964 kb
Host smart-eabcc89c-7c6c-414d-aeda-9bb1e3d8bb5d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1541234084 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.1541234084
Directory /workspace/41.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.2275181042
Short name T146
Test name
Test status
Simulation time 1490050000 ps
CPU time 5.1 seconds
Started Jul 10 05:52:01 PM PDT 24
Finished Jul 10 05:52:15 PM PDT 24
Peak memory 164908 kb
Host smart-86691688-3ca8-459c-ac52-0963134e9377
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2275181042 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.2275181042
Directory /workspace/42.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.388948545
Short name T158
Test name
Test status
Simulation time 1451890000 ps
CPU time 5.46 seconds
Started Jul 10 05:52:01 PM PDT 24
Finished Jul 10 05:52:16 PM PDT 24
Peak memory 164960 kb
Host smart-9a699c6d-d530-4a17-bdc8-57f1c87fc1e2
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=388948545 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.388948545
Directory /workspace/43.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.431142799
Short name T126
Test name
Test status
Simulation time 1470150000 ps
CPU time 5.39 seconds
Started Jul 10 05:51:59 PM PDT 24
Finished Jul 10 05:52:14 PM PDT 24
Peak memory 164964 kb
Host smart-b8acee5b-f939-4768-a5a0-bfac157581e3
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=431142799 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.431142799
Directory /workspace/44.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.3712344281
Short name T159
Test name
Test status
Simulation time 1369990000 ps
CPU time 3.61 seconds
Started Jul 10 05:52:06 PM PDT 24
Finished Jul 10 05:52:17 PM PDT 24
Peak memory 164956 kb
Host smart-3e087fa7-1c93-4c1a-95b6-a46eebf52efd
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3712344281 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.3712344281
Directory /workspace/45.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.2409427291
Short name T160
Test name
Test status
Simulation time 1550870000 ps
CPU time 5.27 seconds
Started Jul 10 05:51:59 PM PDT 24
Finished Jul 10 05:52:14 PM PDT 24
Peak memory 164888 kb
Host smart-0f368b1d-2977-44d0-876b-6c4821a24c4e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2409427291 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.2409427291
Directory /workspace/46.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.451972153
Short name T117
Test name
Test status
Simulation time 1368010000 ps
CPU time 3.76 seconds
Started Jul 10 05:52:09 PM PDT 24
Finished Jul 10 05:52:22 PM PDT 24
Peak memory 164960 kb
Host smart-670c9274-5536-4747-9470-c8b3141330ae
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=451972153 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.451972153
Directory /workspace/47.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.962637074
Short name T111
Test name
Test status
Simulation time 1500850000 ps
CPU time 5.56 seconds
Started Jul 10 05:51:59 PM PDT 24
Finished Jul 10 05:52:13 PM PDT 24
Peak memory 164960 kb
Host smart-6532b21d-e31b-4b08-825f-b451acbd8bb6
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=962637074 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.962637074
Directory /workspace/48.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.4131990120
Short name T154
Test name
Test status
Simulation time 1563270000 ps
CPU time 4.96 seconds
Started Jul 10 05:51:57 PM PDT 24
Finished Jul 10 05:52:10 PM PDT 24
Peak memory 164964 kb
Host smart-46a2741f-5d26-447e-9f1b-5d4ebe6450de
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4131990120 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.4131990120
Directory /workspace/49.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.2906272039
Short name T123
Test name
Test status
Simulation time 1530850000 ps
CPU time 3.48 seconds
Started Jul 10 05:51:50 PM PDT 24
Finished Jul 10 05:52:00 PM PDT 24
Peak memory 164912 kb
Host smart-719922ee-e49d-4575-ac0e-d047ba1a9af6
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2906272039 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.2906272039
Directory /workspace/5.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.1171746551
Short name T152
Test name
Test status
Simulation time 1461990000 ps
CPU time 4.41 seconds
Started Jul 10 05:51:58 PM PDT 24
Finished Jul 10 05:52:10 PM PDT 24
Peak memory 164940 kb
Host smart-7b1df2e7-30d3-42f7-89b8-122874562866
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1171746551 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.1171746551
Directory /workspace/6.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.1243457897
Short name T140
Test name
Test status
Simulation time 1545750000 ps
CPU time 5.92 seconds
Started Jul 10 05:51:52 PM PDT 24
Finished Jul 10 05:52:12 PM PDT 24
Peak memory 164964 kb
Host smart-203c7ba8-5aea-4b0d-8846-458999ab4999
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1243457897 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.1243457897
Directory /workspace/7.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.754184013
Short name T138
Test name
Test status
Simulation time 1493570000 ps
CPU time 5.08 seconds
Started Jul 10 05:52:09 PM PDT 24
Finished Jul 10 05:52:25 PM PDT 24
Peak memory 164884 kb
Host smart-a70ad01d-c9d0-4081-a7f1-3240c2247845
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=754184013 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.754184013
Directory /workspace/8.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2343207171
Short name T134
Test name
Test status
Simulation time 1393150000 ps
CPU time 3.55 seconds
Started Jul 10 05:51:57 PM PDT 24
Finished Jul 10 05:52:08 PM PDT 24
Peak memory 164956 kb
Host smart-66e7ede5-b3be-4d6d-b4a6-0499f86d1c89
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2343207171 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.2343207171
Directory /workspace/9.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.2499808530
Short name T40
Test name
Test status
Simulation time 1325010000 ps
CPU time 4.44 seconds
Started Jul 10 05:51:50 PM PDT 24
Finished Jul 10 05:52:02 PM PDT 24
Peak memory 164968 kb
Host smart-059258fe-9596-4358-90d2-96fee11e128f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2499808530 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.2499808530
Directory /workspace/1.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.4087002165
Short name T69
Test name
Test status
Simulation time 1371910000 ps
CPU time 3.96 seconds
Started Jul 10 05:51:51 PM PDT 24
Finished Jul 10 05:52:02 PM PDT 24
Peak memory 164956 kb
Host smart-080d95ef-c8a7-497e-b34f-a79c64c65ce8
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4087002165 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.4087002165
Directory /workspace/10.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.1120315805
Short name T58
Test name
Test status
Simulation time 1413350000 ps
CPU time 5.91 seconds
Started Jul 10 05:51:51 PM PDT 24
Finished Jul 10 05:52:06 PM PDT 24
Peak memory 164956 kb
Host smart-0bd89b36-ba69-43a6-87d6-13775eb31b1a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1120315805 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.1120315805
Directory /workspace/11.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.2874178733
Short name T35
Test name
Test status
Simulation time 1517910000 ps
CPU time 6.17 seconds
Started Jul 10 05:51:50 PM PDT 24
Finished Jul 10 05:52:05 PM PDT 24
Peak memory 164964 kb
Host smart-9fdbc837-f665-4656-a109-2140ff161004
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2874178733 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.2874178733
Directory /workspace/12.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.2085952450
Short name T63
Test name
Test status
Simulation time 1546010000 ps
CPU time 4.74 seconds
Started Jul 10 05:51:53 PM PDT 24
Finished Jul 10 05:52:06 PM PDT 24
Peak memory 164884 kb
Host smart-443edd0a-8523-47ca-8f9c-0f886a09bd20
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2085952450 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.2085952450
Directory /workspace/13.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.729607922
Short name T3
Test name
Test status
Simulation time 1466210000 ps
CPU time 4.65 seconds
Started Jul 10 05:51:55 PM PDT 24
Finished Jul 10 05:52:07 PM PDT 24
Peak memory 164832 kb
Host smart-7a99d22a-25d5-4ce7-846e-e2e7d414b66e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=729607922 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.729607922
Directory /workspace/14.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.2858134251
Short name T32
Test name
Test status
Simulation time 1560290000 ps
CPU time 4.78 seconds
Started Jul 10 05:51:53 PM PDT 24
Finished Jul 10 05:52:06 PM PDT 24
Peak memory 164976 kb
Host smart-7fb61f54-1a53-4a2e-8e03-55991d13910f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2858134251 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.2858134251
Directory /workspace/15.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.81430786
Short name T56
Test name
Test status
Simulation time 1266250000 ps
CPU time 4.33 seconds
Started Jul 10 05:51:54 PM PDT 24
Finished Jul 10 05:52:06 PM PDT 24
Peak memory 164884 kb
Host smart-67e4eb6f-e4d5-433c-9d68-89d6739329df
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=81430786 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.81430786
Directory /workspace/16.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.2314972509
Short name T1
Test name
Test status
Simulation time 1248370000 ps
CPU time 5.15 seconds
Started Jul 10 05:51:52 PM PDT 24
Finished Jul 10 05:52:05 PM PDT 24
Peak memory 164956 kb
Host smart-d2c97d41-efe8-4968-a826-56ec075130d6
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2314972509 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.2314972509
Directory /workspace/17.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.1407042829
Short name T54
Test name
Test status
Simulation time 1543230000 ps
CPU time 4.77 seconds
Started Jul 10 05:51:52 PM PDT 24
Finished Jul 10 05:52:05 PM PDT 24
Peak memory 164912 kb
Host smart-cf6ea186-9e63-41bf-a627-26c41cebd7b6
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1407042829 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.1407042829
Directory /workspace/18.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.3988520650
Short name T31
Test name
Test status
Simulation time 1500430000 ps
CPU time 4.56 seconds
Started Jul 10 05:51:55 PM PDT 24
Finished Jul 10 05:52:07 PM PDT 24
Peak memory 164844 kb
Host smart-ca5d3014-fdb9-4e9e-b197-c07b07174a23
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3988520650 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.3988520650
Directory /workspace/19.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.925248600
Short name T41
Test name
Test status
Simulation time 1463350000 ps
CPU time 5.69 seconds
Started Jul 10 05:51:49 PM PDT 24
Finished Jul 10 05:52:02 PM PDT 24
Peak memory 164892 kb
Host smart-cc27f711-9c9d-4653-b767-0c47c06ab44d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=925248600 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.925248600
Directory /workspace/2.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.3747546096
Short name T39
Test name
Test status
Simulation time 1458510000 ps
CPU time 5.16 seconds
Started Jul 10 05:51:53 PM PDT 24
Finished Jul 10 05:52:07 PM PDT 24
Peak memory 164960 kb
Host smart-b2307259-e3e4-4444-81ad-9676674bd601
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3747546096 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.3747546096
Directory /workspace/20.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.3805365598
Short name T48
Test name
Test status
Simulation time 1514310000 ps
CPU time 4.36 seconds
Started Jul 10 05:51:51 PM PDT 24
Finished Jul 10 05:52:03 PM PDT 24
Peak memory 164964 kb
Host smart-3f05138d-8e98-4372-b250-668e170b9f0b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3805365598 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.3805365598
Directory /workspace/21.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.3119209568
Short name T57
Test name
Test status
Simulation time 1547550000 ps
CPU time 5.46 seconds
Started Jul 10 05:51:50 PM PDT 24
Finished Jul 10 05:52:04 PM PDT 24
Peak memory 164964 kb
Host smart-a2e85bc0-0727-461b-ada2-f389fec60e1e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3119209568 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.3119209568
Directory /workspace/22.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.2089034434
Short name T59
Test name
Test status
Simulation time 1533850000 ps
CPU time 4.42 seconds
Started Jul 10 05:51:55 PM PDT 24
Finished Jul 10 05:52:07 PM PDT 24
Peak memory 164936 kb
Host smart-29f47591-047c-4014-aafb-faa100575747
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2089034434 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.2089034434
Directory /workspace/23.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.2461473906
Short name T67
Test name
Test status
Simulation time 1582510000 ps
CPU time 4.7 seconds
Started Jul 10 05:51:52 PM PDT 24
Finished Jul 10 05:52:04 PM PDT 24
Peak memory 164964 kb
Host smart-7639cccf-882b-4bc5-963e-2d6ccd7695dd
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2461473906 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.2461473906
Directory /workspace/24.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.1330888436
Short name T55
Test name
Test status
Simulation time 1413430000 ps
CPU time 5.52 seconds
Started Jul 10 05:51:53 PM PDT 24
Finished Jul 10 05:52:07 PM PDT 24
Peak memory 164964 kb
Host smart-ca16a6a7-db5d-4bd0-9998-a37f25ed3925
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1330888436 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.1330888436
Directory /workspace/25.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.841392392
Short name T66
Test name
Test status
Simulation time 1360250000 ps
CPU time 4.41 seconds
Started Jul 10 05:51:53 PM PDT 24
Finished Jul 10 05:52:05 PM PDT 24
Peak memory 164928 kb
Host smart-5edfdf28-a379-4bd8-96b6-cc9cffa6ef5c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=841392392 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.841392392
Directory /workspace/26.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.642261223
Short name T36
Test name
Test status
Simulation time 1565030000 ps
CPU time 4.2 seconds
Started Jul 10 05:51:50 PM PDT 24
Finished Jul 10 05:52:01 PM PDT 24
Peak memory 164964 kb
Host smart-87672814-2f38-4a85-93c7-ff5e97617d77
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=642261223 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.642261223
Directory /workspace/27.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.2099707300
Short name T64
Test name
Test status
Simulation time 1377170000 ps
CPU time 4.45 seconds
Started Jul 10 05:51:53 PM PDT 24
Finished Jul 10 05:52:05 PM PDT 24
Peak memory 164908 kb
Host smart-b127f97f-200b-405a-ba99-42507e87661d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2099707300 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.2099707300
Directory /workspace/28.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.3955656165
Short name T51
Test name
Test status
Simulation time 1432030000 ps
CPU time 5.51 seconds
Started Jul 10 05:51:51 PM PDT 24
Finished Jul 10 05:52:05 PM PDT 24
Peak memory 164956 kb
Host smart-5e64d4fb-95af-4715-a733-8c39566d99a3
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3955656165 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.3955656165
Directory /workspace/29.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.869932535
Short name T37
Test name
Test status
Simulation time 1441310000 ps
CPU time 5.08 seconds
Started Jul 10 05:51:47 PM PDT 24
Finished Jul 10 05:51:59 PM PDT 24
Peak memory 164836 kb
Host smart-b8db9117-5466-4d3b-8a4f-cc3770ae2c09
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=869932535 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.869932535
Directory /workspace/3.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.1522475513
Short name T33
Test name
Test status
Simulation time 1086630000 ps
CPU time 3.36 seconds
Started Jul 10 05:51:55 PM PDT 24
Finished Jul 10 05:52:04 PM PDT 24
Peak memory 164932 kb
Host smart-87aaf255-43d4-4e66-aed1-26ca65877d8b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1522475513 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.1522475513
Directory /workspace/30.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.2609162440
Short name T50
Test name
Test status
Simulation time 1492770000 ps
CPU time 5.6 seconds
Started Jul 10 05:51:53 PM PDT 24
Finished Jul 10 05:52:07 PM PDT 24
Peak memory 164912 kb
Host smart-009a72b2-8d1d-45b6-9c0f-ae3b210e168f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2609162440 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.2609162440
Directory /workspace/31.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.777686208
Short name T61
Test name
Test status
Simulation time 1542450000 ps
CPU time 4.86 seconds
Started Jul 10 05:51:53 PM PDT 24
Finished Jul 10 05:52:06 PM PDT 24
Peak memory 164956 kb
Host smart-c0181089-8ff9-4b21-83d0-59cf87f5d44b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=777686208 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.777686208
Directory /workspace/32.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.2680474888
Short name T9
Test name
Test status
Simulation time 1381030000 ps
CPU time 3.57 seconds
Started Jul 10 05:51:50 PM PDT 24
Finished Jul 10 05:52:00 PM PDT 24
Peak memory 164964 kb
Host smart-77281cad-e3c2-4244-a537-e90e5e384251
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2680474888 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.2680474888
Directory /workspace/33.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.2429704610
Short name T12
Test name
Test status
Simulation time 1532250000 ps
CPU time 4.64 seconds
Started Jul 10 05:51:51 PM PDT 24
Finished Jul 10 05:52:03 PM PDT 24
Peak memory 164964 kb
Host smart-327bff23-05d7-44f7-a2ba-eefccc5c4d51
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2429704610 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.2429704610
Directory /workspace/34.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.1160085676
Short name T45
Test name
Test status
Simulation time 1445890000 ps
CPU time 5.18 seconds
Started Jul 10 05:51:49 PM PDT 24
Finished Jul 10 05:52:02 PM PDT 24
Peak memory 164932 kb
Host smart-2628a689-be76-4cfe-b540-3fd78df361d7
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1160085676 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.1160085676
Directory /workspace/35.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.3189428111
Short name T7
Test name
Test status
Simulation time 1522090000 ps
CPU time 5.73 seconds
Started Jul 10 05:51:52 PM PDT 24
Finished Jul 10 05:52:07 PM PDT 24
Peak memory 164908 kb
Host smart-629cf1a9-dd1f-4adf-a09e-0e3f2a2c885d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3189428111 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.3189428111
Directory /workspace/36.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.133230072
Short name T2
Test name
Test status
Simulation time 1368450000 ps
CPU time 4.32 seconds
Started Jul 10 05:51:51 PM PDT 24
Finished Jul 10 05:52:02 PM PDT 24
Peak memory 164960 kb
Host smart-dd6cda11-6eb2-4d62-8063-fdbb6e33862e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=133230072 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.133230072
Directory /workspace/37.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.1443456904
Short name T53
Test name
Test status
Simulation time 1232190000 ps
CPU time 5.15 seconds
Started Jul 10 05:51:51 PM PDT 24
Finished Jul 10 05:52:03 PM PDT 24
Peak memory 164964 kb
Host smart-16ba57aa-fb37-47e7-85a4-bf8a41cbdfb5
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1443456904 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.1443456904
Directory /workspace/38.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.3148726094
Short name T52
Test name
Test status
Simulation time 1570410000 ps
CPU time 5.46 seconds
Started Jul 10 05:51:53 PM PDT 24
Finished Jul 10 05:52:07 PM PDT 24
Peak memory 164960 kb
Host smart-c91f3264-d226-4187-a507-be787b818d16
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3148726094 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.3148726094
Directory /workspace/39.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.2711364347
Short name T42
Test name
Test status
Simulation time 1497890000 ps
CPU time 5.14 seconds
Started Jul 10 05:51:45 PM PDT 24
Finished Jul 10 05:51:58 PM PDT 24
Peak memory 164948 kb
Host smart-fca138ab-e651-4e0c-b3e6-991d93359bee
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2711364347 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.2711364347
Directory /workspace/4.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.4209648606
Short name T60
Test name
Test status
Simulation time 1342990000 ps
CPU time 4.25 seconds
Started Jul 10 05:51:55 PM PDT 24
Finished Jul 10 05:52:07 PM PDT 24
Peak memory 164932 kb
Host smart-0821f000-6011-46e6-9435-f2d07a136e5f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4209648606 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.4209648606
Directory /workspace/40.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.2296484127
Short name T11
Test name
Test status
Simulation time 1549110000 ps
CPU time 4.79 seconds
Started Jul 10 05:51:55 PM PDT 24
Finished Jul 10 05:52:07 PM PDT 24
Peak memory 164920 kb
Host smart-0fd7f057-854c-4a4b-946d-8c65c40825a1
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2296484127 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.2296484127
Directory /workspace/41.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.3666168140
Short name T44
Test name
Test status
Simulation time 1220710000 ps
CPU time 4.02 seconds
Started Jul 10 05:51:49 PM PDT 24
Finished Jul 10 05:51:59 PM PDT 24
Peak memory 164932 kb
Host smart-1fc84db9-542f-4250-b435-d39d5f00f49e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3666168140 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.3666168140
Directory /workspace/42.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.1542364052
Short name T65
Test name
Test status
Simulation time 1570290000 ps
CPU time 4.78 seconds
Started Jul 10 05:51:52 PM PDT 24
Finished Jul 10 05:52:04 PM PDT 24
Peak memory 164956 kb
Host smart-a9a2e561-2640-4759-93ca-a7533fb7af07
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1542364052 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.1542364052
Directory /workspace/43.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.521082690
Short name T43
Test name
Test status
Simulation time 1366510000 ps
CPU time 4.37 seconds
Started Jul 10 05:51:53 PM PDT 24
Finished Jul 10 05:52:05 PM PDT 24
Peak memory 164956 kb
Host smart-80d1a152-c528-460d-baf2-f3ddc987fc28
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=521082690 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.521082690
Directory /workspace/44.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.1936738047
Short name T62
Test name
Test status
Simulation time 1220030000 ps
CPU time 4.54 seconds
Started Jul 10 05:51:52 PM PDT 24
Finished Jul 10 05:52:04 PM PDT 24
Peak memory 164960 kb
Host smart-1a69de97-5514-492c-963a-923515326d62
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1936738047 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.1936738047
Directory /workspace/45.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.516855814
Short name T13
Test name
Test status
Simulation time 1600710000 ps
CPU time 5.19 seconds
Started Jul 10 05:51:53 PM PDT 24
Finished Jul 10 05:52:07 PM PDT 24
Peak memory 164928 kb
Host smart-26a1c9b2-990c-40bb-9c12-6c3d9217a637
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=516855814 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.516855814
Directory /workspace/46.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.1957831363
Short name T47
Test name
Test status
Simulation time 1526430000 ps
CPU time 4.08 seconds
Started Jul 10 05:51:50 PM PDT 24
Finished Jul 10 05:52:00 PM PDT 24
Peak memory 164920 kb
Host smart-ff6e51f4-7348-4d7b-8d70-c735f5421611
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1957831363 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.1957831363
Directory /workspace/47.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.3526156854
Short name T68
Test name
Test status
Simulation time 1563770000 ps
CPU time 5.52 seconds
Started Jul 10 05:51:51 PM PDT 24
Finished Jul 10 05:52:04 PM PDT 24
Peak memory 164968 kb
Host smart-91be8e06-0033-4f85-b915-b0689009589f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3526156854 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.3526156854
Directory /workspace/48.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.1656571360
Short name T70
Test name
Test status
Simulation time 1437870000 ps
CPU time 4.76 seconds
Started Jul 10 05:51:48 PM PDT 24
Finished Jul 10 05:52:00 PM PDT 24
Peak memory 164976 kb
Host smart-623673e3-8d1f-47a5-866b-153de51946d1
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1656571360 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.1656571360
Directory /workspace/49.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.2172382521
Short name T38
Test name
Test status
Simulation time 1467190000 ps
CPU time 5.54 seconds
Started Jul 10 05:51:48 PM PDT 24
Finished Jul 10 05:52:01 PM PDT 24
Peak memory 164968 kb
Host smart-42e84c0d-782b-43f4-b123-e576a2eb47d7
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2172382521 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.2172382521
Directory /workspace/5.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.308018991
Short name T34
Test name
Test status
Simulation time 1549810000 ps
CPU time 5.92 seconds
Started Jul 10 05:51:44 PM PDT 24
Finished Jul 10 05:51:58 PM PDT 24
Peak memory 164812 kb
Host smart-6a5e99cb-d7d0-4aa6-bcf0-4c44a3cf7ee8
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=308018991 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.308018991
Directory /workspace/6.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.1272426354
Short name T49
Test name
Test status
Simulation time 1488770000 ps
CPU time 4.48 seconds
Started Jul 10 05:51:48 PM PDT 24
Finished Jul 10 05:51:59 PM PDT 24
Peak memory 164944 kb
Host smart-a95b67e6-721d-410c-9c1b-d2c88fe09608
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1272426354 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.1272426354
Directory /workspace/7.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.655934481
Short name T10
Test name
Test status
Simulation time 1541730000 ps
CPU time 4.61 seconds
Started Jul 10 05:51:49 PM PDT 24
Finished Jul 10 05:52:01 PM PDT 24
Peak memory 164944 kb
Host smart-dc9eb2b3-e3e1-43fb-92a2-ba16f8938430
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=655934481 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.655934481
Directory /workspace/8.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.3330443063
Short name T46
Test name
Test status
Simulation time 1454390000 ps
CPU time 3.95 seconds
Started Jul 10 05:51:50 PM PDT 24
Finished Jul 10 05:52:00 PM PDT 24
Peak memory 164968 kb
Host smart-09223ef2-2318-4367-bf0b-3c31653e7b0e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3330443063 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.3330443063
Directory /workspace/9.prim_lfsr_gal_smoke/latest
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