Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.31 100.00 96.55 100.00 100.00 95.00


Total tests in report: 200
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
87.31 87.31 100.00 100.00 96.55 96.55 100.00 100.00 100.00 100.00 40.00 40.00 /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.2279227834
96.81 9.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 87.50 47.50 /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.3373181898
98.31 1.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 95.00 7.50 /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.1668917868

Tests that do not contribute to grading

Name
/workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.2023732500
/workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.4241674681
/workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.1808484394
/workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.169759353
/workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.372695380
/workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.3992709121
/workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.1934764755
/workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.384513046
/workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.4166064011
/workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.271353643
/workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.3337873959
/workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.3412806799
/workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.322156898
/workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.4229259217
/workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.3879810292
/workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.694967240
/workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.1961462702
/workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.1131079150
/workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.143996337
/workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.2958439922
/workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.1308353979
/workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.2710689969
/workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.4053741824
/workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3623275701
/workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.1445949173
/workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.3703712250
/workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.1545469170
/workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.3557237944
/workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.1073265144
/workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.652364378
/workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.2248904226
/workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.878070349
/workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.4077869802
/workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.3052500869
/workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.3762635122
/workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.3538570812
/workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.2777509475
/workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.3802383881
/workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.1868516996
/workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.4047455866
/workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.3421766240
/workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.1913618148
/workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.3394904000
/workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.986271642
/workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.456486299
/workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.2218269428
/workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.2683811333
/workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1185679645
/workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.3246444224
/workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.4153855829
/workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.1370754938
/workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.608515794
/workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.1262719952
/workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.1504898687
/workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.4278509987
/workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.3254827764
/workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.520121542
/workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.3213502483
/workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.1439348902
/workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.4164007938
/workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.348250406
/workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.1317370653
/workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3821048416
/workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.2889429575
/workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.109961557
/workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.603932089
/workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.1381199632
/workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.1342383394
/workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.865867671
/workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.693760674
/workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.3582486314
/workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.2701809426
/workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.639875512
/workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.1201164446
/workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.3319475770
/workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.3196673253
/workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.3236938397
/workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.3935582142
/workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.2582604131
/workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.1192032847
/workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.4151707841
/workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.2944692754
/workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.1290253679
/workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.4107595530
/workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.2114986551
/workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.173578672
/workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.452251909
/workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.1144384212
/workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.1442621938
/workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.4233652792
/workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.2792357553
/workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1571226253
/workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.3355463113
/workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.2175620090
/workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.2549884501
/workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.2031081399
/workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.2897356326
/workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.1098485390
/workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.663373821
/workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.2988404960
/workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.769484297
/workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.2820267438
/workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.431883172
/workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.1503970304
/workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.3579458095
/workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.1518633039
/workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.503525673
/workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.426824755
/workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.2694506734
/workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.1649631184
/workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.2037991172
/workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.1324898787
/workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.4015837448
/workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.2437055988
/workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.3104934825
/workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.421342068
/workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.1793574385
/workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2801523582
/workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.1980744983
/workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.4094375393
/workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.853274745
/workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.2181896602
/workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.3376826175
/workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.2619300756
/workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.2848648361
/workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.448550729
/workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.3229646624
/workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.1012322055
/workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.2728948004
/workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.3376280469
/workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.3711191211
/workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.1997426812
/workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.2215008349
/workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.3539894357
/workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.2249596592
/workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.2849364987
/workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.513229087
/workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.3060309259
/workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.3526184038
/workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.3534248102
/workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.641139139
/workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.853184152
/workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.1549005157
/workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.856082788
/workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.2757915907
/workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.2084266705
/workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.3684349553
/workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.3106841888
/workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.992500051
/workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.3148515633
/workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.2778670832
/workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.2549976643
/workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.218324894
/workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.3047539613
/workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.1917430137
/workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.1076781444
/workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.858204937
/workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.1500339511
/workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.3799690261
/workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.3323203790
/workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.3337372885
/workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.370610806
/workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.3843372042
/workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.3719626936
/workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.3699502963
/workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.3540195416
/workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.601362838
/workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.2304029210
/workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.4198688397
/workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.1529859499
/workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.2546965742
/workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.364837476
/workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.2704911854
/workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.2227352313
/workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.93034945
/workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.3078630458
/workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.1423159946
/workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.2435125689
/workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.4269969759
/workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.2674240955
/workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.1070913086
/workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.1321723325
/workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.3113504829
/workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.3967547908
/workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.3924221932
/workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.1486797044
/workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.124435074
/workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.2627862299
/workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.2446654803
/workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.539664421
/workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.855981162
/workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.2141448325
/workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.2028097697
/workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.2148873396
/workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.3538382002
/workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.2965530881
/workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.2832694553



Total test records in report: 200
tests.html | tests1.html | tests2.html | tests3.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.855981162 Jul 11 04:55:14 PM PDT 24 Jul 11 04:55:26 PM PDT 24 1423410000 ps
T2 /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.2227352313 Jul 11 04:55:13 PM PDT 24 Jul 11 04:55:24 PM PDT 24 1417850000 ps
T3 /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.3924221932 Jul 11 04:55:15 PM PDT 24 Jul 11 04:55:26 PM PDT 24 1571950000 ps
T7 /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.2279227834 Jul 11 04:55:12 PM PDT 24 Jul 11 04:55:23 PM PDT 24 1452870000 ps
T8 /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.1070913086 Jul 11 04:55:14 PM PDT 24 Jul 11 04:55:25 PM PDT 24 1297510000 ps
T9 /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.2148873396 Jul 11 04:55:07 PM PDT 24 Jul 11 04:55:17 PM PDT 24 1253810000 ps
T10 /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.4198688397 Jul 11 04:55:10 PM PDT 24 Jul 11 04:55:26 PM PDT 24 1570730000 ps
T11 /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.1321723325 Jul 11 04:55:08 PM PDT 24 Jul 11 04:55:19 PM PDT 24 1572330000 ps
T12 /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.3699502963 Jul 11 04:55:14 PM PDT 24 Jul 11 04:55:25 PM PDT 24 1361090000 ps
T13 /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.2627862299 Jul 11 04:55:20 PM PDT 24 Jul 11 04:55:32 PM PDT 24 1483930000 ps
T31 /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.539664421 Jul 11 04:55:14 PM PDT 24 Jul 11 04:55:28 PM PDT 24 1518370000 ps
T32 /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.2704911854 Jul 11 04:55:09 PM PDT 24 Jul 11 04:55:22 PM PDT 24 1555930000 ps
T33 /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.93034945 Jul 11 04:55:15 PM PDT 24 Jul 11 04:55:28 PM PDT 24 1376510000 ps
T34 /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.3047539613 Jul 11 04:55:13 PM PDT 24 Jul 11 04:55:25 PM PDT 24 1552150000 ps
T35 /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.124435074 Jul 11 04:55:17 PM PDT 24 Jul 11 04:55:29 PM PDT 24 1559570000 ps
T36 /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.3538382002 Jul 11 04:55:12 PM PDT 24 Jul 11 04:55:25 PM PDT 24 1471310000 ps
T37 /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.3323203790 Jul 11 04:55:12 PM PDT 24 Jul 11 04:55:24 PM PDT 24 1482830000 ps
T38 /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.992500051 Jul 11 04:55:05 PM PDT 24 Jul 11 04:55:18 PM PDT 24 1571810000 ps
T39 /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.858204937 Jul 11 04:55:17 PM PDT 24 Jul 11 04:55:31 PM PDT 24 1386690000 ps
T40 /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.2832694553 Jul 11 04:55:13 PM PDT 24 Jul 11 04:55:25 PM PDT 24 1392750000 ps
T41 /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.1529859499 Jul 11 04:55:14 PM PDT 24 Jul 11 04:55:26 PM PDT 24 1424010000 ps
T42 /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.3799690261 Jul 11 04:55:09 PM PDT 24 Jul 11 04:55:23 PM PDT 24 1385830000 ps
T43 /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.3337372885 Jul 11 04:55:08 PM PDT 24 Jul 11 04:55:18 PM PDT 24 1411390000 ps
T44 /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.3113504829 Jul 11 04:55:14 PM PDT 24 Jul 11 04:55:26 PM PDT 24 1577410000 ps
T45 /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.4269969759 Jul 11 04:55:15 PM PDT 24 Jul 11 04:55:27 PM PDT 24 1302970000 ps
T46 /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.2965530881 Jul 11 04:55:07 PM PDT 24 Jul 11 04:55:22 PM PDT 24 1565490000 ps
T47 /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.1423159946 Jul 11 04:55:13 PM PDT 24 Jul 11 04:55:23 PM PDT 24 1296870000 ps
T48 /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.2141448325 Jul 11 04:55:18 PM PDT 24 Jul 11 04:55:32 PM PDT 24 1562130000 ps
T49 /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.2446654803 Jul 11 04:55:19 PM PDT 24 Jul 11 04:55:31 PM PDT 24 1436710000 ps
T50 /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.1076781444 Jul 11 04:55:13 PM PDT 24 Jul 11 04:55:29 PM PDT 24 1509430000 ps
T51 /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.370610806 Jul 11 04:55:15 PM PDT 24 Jul 11 04:55:28 PM PDT 24 1567470000 ps
T52 /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.3078630458 Jul 11 04:55:13 PM PDT 24 Jul 11 04:55:26 PM PDT 24 1377130000 ps
T53 /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.2028097697 Jul 11 04:55:11 PM PDT 24 Jul 11 04:55:23 PM PDT 24 1524330000 ps
T54 /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.2778670832 Jul 11 04:55:18 PM PDT 24 Jul 11 04:55:33 PM PDT 24 1567210000 ps
T55 /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.1917430137 Jul 11 04:55:16 PM PDT 24 Jul 11 04:55:28 PM PDT 24 1446550000 ps
T56 /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.1500339511 Jul 11 04:55:11 PM PDT 24 Jul 11 04:55:26 PM PDT 24 1554710000 ps
T57 /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.3843372042 Jul 11 04:55:12 PM PDT 24 Jul 11 04:55:22 PM PDT 24 1151110000 ps
T58 /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.2549976643 Jul 11 04:55:11 PM PDT 24 Jul 11 04:55:21 PM PDT 24 1467710000 ps
T59 /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.3967547908 Jul 11 04:55:16 PM PDT 24 Jul 11 04:55:29 PM PDT 24 1543310000 ps
T60 /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.3719626936 Jul 11 04:55:12 PM PDT 24 Jul 11 04:55:25 PM PDT 24 1316410000 ps
T61 /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.2304029210 Jul 11 04:55:08 PM PDT 24 Jul 11 04:55:20 PM PDT 24 1370370000 ps
T62 /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.3540195416 Jul 11 04:55:13 PM PDT 24 Jul 11 04:55:26 PM PDT 24 1322710000 ps
T63 /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.364837476 Jul 11 04:55:09 PM PDT 24 Jul 11 04:55:20 PM PDT 24 1221910000 ps
T64 /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.601362838 Jul 11 04:55:21 PM PDT 24 Jul 11 04:55:31 PM PDT 24 1300530000 ps
T65 /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.1486797044 Jul 11 04:55:14 PM PDT 24 Jul 11 04:55:26 PM PDT 24 1538750000 ps
T66 /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.2674240955 Jul 11 04:55:13 PM PDT 24 Jul 11 04:55:27 PM PDT 24 1510050000 ps
T67 /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.2546965742 Jul 11 04:55:09 PM PDT 24 Jul 11 04:55:21 PM PDT 24 1270490000 ps
T68 /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.218324894 Jul 11 04:55:10 PM PDT 24 Jul 11 04:55:24 PM PDT 24 1514190000 ps
T69 /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.3148515633 Jul 11 04:55:08 PM PDT 24 Jul 11 04:55:21 PM PDT 24 1401570000 ps
T70 /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.2435125689 Jul 11 04:55:13 PM PDT 24 Jul 11 04:55:28 PM PDT 24 1529770000 ps
T4 /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.3992709121 Jul 11 04:55:10 PM PDT 24 Jul 11 05:26:56 PM PDT 24 336486790000 ps
T5 /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.652364378 Jul 11 04:55:11 PM PDT 24 Jul 11 05:26:25 PM PDT 24 336708750000 ps
T6 /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.2248904226 Jul 11 04:55:03 PM PDT 24 Jul 11 05:32:55 PM PDT 24 336812950000 ps
T14 /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.986271642 Jul 11 04:55:07 PM PDT 24 Jul 11 05:25:47 PM PDT 24 336338830000 ps
T15 /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.3373181898 Jul 11 04:55:01 PM PDT 24 Jul 11 05:27:52 PM PDT 24 336575010000 ps
T16 /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.2710689969 Jul 11 04:55:07 PM PDT 24 Jul 11 05:32:51 PM PDT 24 337093070000 ps
T17 /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.1868516996 Jul 11 04:55:11 PM PDT 24 Jul 11 05:26:25 PM PDT 24 336735990000 ps
T18 /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.3802383881 Jul 11 04:55:06 PM PDT 24 Jul 11 05:28:30 PM PDT 24 336548910000 ps
T19 /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.1131079150 Jul 11 04:55:03 PM PDT 24 Jul 11 05:23:47 PM PDT 24 336526610000 ps
T20 /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.3762635122 Jul 11 04:55:06 PM PDT 24 Jul 11 05:21:34 PM PDT 24 336599890000 ps
T71 /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.3394904000 Jul 11 04:55:05 PM PDT 24 Jul 11 05:29:17 PM PDT 24 336631430000 ps
T72 /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.1934764755 Jul 11 04:55:05 PM PDT 24 Jul 11 05:21:22 PM PDT 24 336569970000 ps
T73 /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.3246444224 Jul 11 04:55:08 PM PDT 24 Jul 11 05:32:40 PM PDT 24 336374690000 ps
T74 /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.322156898 Jul 11 04:55:08 PM PDT 24 Jul 11 05:29:20 PM PDT 24 336775250000 ps
T75 /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.2958439922 Jul 11 04:55:01 PM PDT 24 Jul 11 05:27:49 PM PDT 24 336919030000 ps
T76 /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.4229259217 Jul 11 04:55:01 PM PDT 24 Jul 11 05:29:28 PM PDT 24 336590510000 ps
T77 /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.271353643 Jul 11 04:55:03 PM PDT 24 Jul 11 05:25:49 PM PDT 24 336745870000 ps
T78 /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.3052500869 Jul 11 04:54:56 PM PDT 24 Jul 11 05:20:49 PM PDT 24 336466870000 ps
T79 /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.694967240 Jul 11 04:55:01 PM PDT 24 Jul 11 05:28:00 PM PDT 24 336737790000 ps
T80 /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.4053741824 Jul 11 04:54:55 PM PDT 24 Jul 11 05:22:24 PM PDT 24 337065170000 ps
T81 /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.1308353979 Jul 11 04:55:05 PM PDT 24 Jul 11 05:28:18 PM PDT 24 336829430000 ps
T82 /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.1073265144 Jul 11 04:55:34 PM PDT 24 Jul 11 05:32:42 PM PDT 24 337140630000 ps
T83 /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.456486299 Jul 11 04:54:59 PM PDT 24 Jul 11 05:23:02 PM PDT 24 336861490000 ps
T84 /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.1961462702 Jul 11 04:55:08 PM PDT 24 Jul 11 05:32:49 PM PDT 24 336489930000 ps
T85 /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.3538570812 Jul 11 04:55:06 PM PDT 24 Jul 11 05:27:20 PM PDT 24 336448630000 ps
T86 /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.878070349 Jul 11 04:55:07 PM PDT 24 Jul 11 05:25:54 PM PDT 24 336367450000 ps
T87 /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.2777509475 Jul 11 04:55:07 PM PDT 24 Jul 11 05:23:03 PM PDT 24 336531210000 ps
T88 /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.3879810292 Jul 11 04:55:01 PM PDT 24 Jul 11 05:22:39 PM PDT 24 336786570000 ps
T89 /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.2218269428 Jul 11 04:54:58 PM PDT 24 Jul 11 05:28:57 PM PDT 24 336785490000 ps
T90 /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.2683811333 Jul 11 04:55:11 PM PDT 24 Jul 11 05:27:19 PM PDT 24 336723070000 ps
T91 /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.4166064011 Jul 11 04:55:03 PM PDT 24 Jul 11 05:21:45 PM PDT 24 336484230000 ps
T92 /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.3337873959 Jul 11 04:55:05 PM PDT 24 Jul 11 05:28:45 PM PDT 24 336640770000 ps
T93 /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.3557237944 Jul 11 04:55:10 PM PDT 24 Jul 11 05:29:17 PM PDT 24 336370890000 ps
T94 /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.4077869802 Jul 11 04:55:12 PM PDT 24 Jul 11 05:19:58 PM PDT 24 336593450000 ps
T95 /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.143996337 Jul 11 04:55:10 PM PDT 24 Jul 11 05:29:22 PM PDT 24 336566330000 ps
T96 /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.2023732500 Jul 11 04:54:55 PM PDT 24 Jul 11 05:31:56 PM PDT 24 336903390000 ps
T97 /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1185679645 Jul 11 04:54:59 PM PDT 24 Jul 11 05:23:12 PM PDT 24 336980510000 ps
T98 /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.372695380 Jul 11 04:55:02 PM PDT 24 Jul 11 05:29:08 PM PDT 24 336595870000 ps
T99 /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.3421766240 Jul 11 04:55:05 PM PDT 24 Jul 11 05:27:08 PM PDT 24 336572690000 ps
T100 /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.1445949173 Jul 11 04:54:59 PM PDT 24 Jul 11 05:33:33 PM PDT 24 336557130000 ps
T101 /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.4241674681 Jul 11 04:54:56 PM PDT 24 Jul 11 05:28:51 PM PDT 24 336457250000 ps
T102 /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.169759353 Jul 11 04:55:03 PM PDT 24 Jul 11 05:23:44 PM PDT 24 336639710000 ps
T103 /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.3412806799 Jul 11 04:54:59 PM PDT 24 Jul 11 05:27:10 PM PDT 24 336514650000 ps
T104 /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.3703712250 Jul 11 04:55:01 PM PDT 24 Jul 11 05:24:47 PM PDT 24 336444330000 ps
T105 /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.1808484394 Jul 11 04:55:00 PM PDT 24 Jul 11 05:19:14 PM PDT 24 336959870000 ps
T106 /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.384513046 Jul 11 04:55:08 PM PDT 24 Jul 11 05:32:43 PM PDT 24 336344550000 ps
T107 /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3623275701 Jul 11 04:55:01 PM PDT 24 Jul 11 05:24:31 PM PDT 24 336696730000 ps
T108 /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.1913618148 Jul 11 04:55:12 PM PDT 24 Jul 11 05:26:20 PM PDT 24 336571290000 ps
T109 /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.1545469170 Jul 11 04:55:05 PM PDT 24 Jul 11 05:35:50 PM PDT 24 336434430000 ps
T110 /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.4047455866 Jul 11 04:55:12 PM PDT 24 Jul 11 05:26:31 PM PDT 24 336595070000 ps
T111 /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.2249596592 Jul 11 04:47:40 PM PDT 24 Jul 11 04:47:56 PM PDT 24 1495770000 ps
T112 /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.2215008349 Jul 11 04:47:42 PM PDT 24 Jul 11 04:47:59 PM PDT 24 1506770000 ps
T113 /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.663373821 Jul 11 04:47:42 PM PDT 24 Jul 11 04:47:57 PM PDT 24 1111170000 ps
T114 /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.1980744983 Jul 11 04:48:58 PM PDT 24 Jul 11 04:49:17 PM PDT 24 1550730000 ps
T115 /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.2437055988 Jul 11 04:47:39 PM PDT 24 Jul 11 04:47:54 PM PDT 24 1373530000 ps
T116 /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.2694506734 Jul 11 04:47:38 PM PDT 24 Jul 11 04:47:54 PM PDT 24 1469650000 ps
T117 /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.769484297 Jul 11 04:47:40 PM PDT 24 Jul 11 04:47:59 PM PDT 24 1519950000 ps
T118 /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.2757915907 Jul 11 04:47:38 PM PDT 24 Jul 11 04:47:53 PM PDT 24 1339710000 ps
T119 /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.2849364987 Jul 11 04:47:39 PM PDT 24 Jul 11 04:47:54 PM PDT 24 1281090000 ps
T120 /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.3711191211 Jul 11 04:47:44 PM PDT 24 Jul 11 04:48:03 PM PDT 24 1595590000 ps
T121 /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.4094375393 Jul 11 04:47:41 PM PDT 24 Jul 11 04:47:56 PM PDT 24 1431190000 ps
T122 /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.3579458095 Jul 11 04:47:40 PM PDT 24 Jul 11 04:47:59 PM PDT 24 1451410000 ps
T123 /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.856082788 Jul 11 04:47:40 PM PDT 24 Jul 11 04:47:58 PM PDT 24 1318810000 ps
T124 /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.2084266705 Jul 11 04:47:40 PM PDT 24 Jul 11 04:47:57 PM PDT 24 1548130000 ps
T125 /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.3106841888 Jul 11 04:47:43 PM PDT 24 Jul 11 04:48:00 PM PDT 24 1344050000 ps
T126 /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.1012322055 Jul 11 04:47:39 PM PDT 24 Jul 11 04:47:56 PM PDT 24 1422690000 ps
T127 /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.3060309259 Jul 11 04:47:41 PM PDT 24 Jul 11 04:48:00 PM PDT 24 1518430000 ps
T128 /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.3526184038 Jul 11 04:47:39 PM PDT 24 Jul 11 04:47:55 PM PDT 24 1468970000 ps
T129 /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.4015837448 Jul 11 04:47:33 PM PDT 24 Jul 11 04:47:48 PM PDT 24 1537010000 ps
T130 /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.853184152 Jul 11 04:47:40 PM PDT 24 Jul 11 04:47:58 PM PDT 24 1587510000 ps
T131 /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.1549005157 Jul 11 04:47:39 PM PDT 24 Jul 11 04:47:57 PM PDT 24 1470850000 ps
T132 /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.2619300756 Jul 11 04:47:40 PM PDT 24 Jul 11 04:47:59 PM PDT 24 1558350000 ps
T133 /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.421342068 Jul 11 04:47:42 PM PDT 24 Jul 11 04:48:00 PM PDT 24 1437010000 ps
T134 /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.3539894357 Jul 11 04:47:37 PM PDT 24 Jul 11 04:47:52 PM PDT 24 1503790000 ps
T135 /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.3104934825 Jul 11 04:47:46 PM PDT 24 Jul 11 04:48:05 PM PDT 24 1462170000 ps
T136 /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.3229646624 Jul 11 04:47:37 PM PDT 24 Jul 11 04:47:52 PM PDT 24 1545730000 ps
T137 /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.503525673 Jul 11 04:47:39 PM PDT 24 Jul 11 04:47:55 PM PDT 24 1300950000 ps
T138 /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.2181896602 Jul 11 04:47:42 PM PDT 24 Jul 11 04:48:00 PM PDT 24 1645390000 ps
T139 /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.3376280469 Jul 11 04:47:44 PM PDT 24 Jul 11 04:48:03 PM PDT 24 1503710000 ps
T140 /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.1997426812 Jul 11 04:47:42 PM PDT 24 Jul 11 04:48:01 PM PDT 24 1518810000 ps
T141 /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.1649631184 Jul 11 04:47:32 PM PDT 24 Jul 11 04:47:47 PM PDT 24 1460250000 ps
T142 /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.853274745 Jul 11 04:47:39 PM PDT 24 Jul 11 04:47:55 PM PDT 24 1317810000 ps
T143 /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.1324898787 Jul 11 04:47:42 PM PDT 24 Jul 11 04:47:59 PM PDT 24 1466670000 ps
T144 /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.448550729 Jul 11 04:47:38 PM PDT 24 Jul 11 04:47:55 PM PDT 24 1475590000 ps
T145 /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2801523582 Jul 11 04:47:39 PM PDT 24 Jul 11 04:47:55 PM PDT 24 1285350000 ps
T146 /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.3684349553 Jul 11 04:47:38 PM PDT 24 Jul 11 04:47:54 PM PDT 24 1482670000 ps
T147 /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.3534248102 Jul 11 04:47:42 PM PDT 24 Jul 11 04:47:58 PM PDT 24 1412270000 ps
T148 /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.2820267438 Jul 11 04:47:32 PM PDT 24 Jul 11 04:47:46 PM PDT 24 1472730000 ps
T149 /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.3376826175 Jul 11 04:47:37 PM PDT 24 Jul 11 04:47:53 PM PDT 24 1590910000 ps
T150 /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.1518633039 Jul 11 04:47:33 PM PDT 24 Jul 11 04:47:49 PM PDT 24 1474430000 ps
T151 /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.641139139 Jul 11 04:47:46 PM PDT 24 Jul 11 04:48:05 PM PDT 24 1566030000 ps
T152 /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.2848648361 Jul 11 04:47:40 PM PDT 24 Jul 11 04:47:57 PM PDT 24 1193370000 ps
T153 /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.2037991172 Jul 11 04:47:39 PM PDT 24 Jul 11 04:47:56 PM PDT 24 1508270000 ps
T154 /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.426824755 Jul 11 04:47:38 PM PDT 24 Jul 11 04:47:54 PM PDT 24 1319570000 ps
T155 /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.1503970304 Jul 11 04:47:39 PM PDT 24 Jul 11 04:47:55 PM PDT 24 1553130000 ps
T156 /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.513229087 Jul 11 04:47:40 PM PDT 24 Jul 11 04:47:59 PM PDT 24 1584170000 ps
T157 /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.1793574385 Jul 11 04:47:41 PM PDT 24 Jul 11 04:47:58 PM PDT 24 1482630000 ps
T158 /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.431883172 Jul 11 04:47:40 PM PDT 24 Jul 11 04:47:58 PM PDT 24 1481850000 ps
T159 /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.2728948004 Jul 11 04:47:40 PM PDT 24 Jul 11 04:47:58 PM PDT 24 1491350000 ps
T160 /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.2988404960 Jul 11 04:47:38 PM PDT 24 Jul 11 04:47:55 PM PDT 24 1561990000 ps
T21 /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.1098485390 Jul 11 04:48:58 PM PDT 24 Jul 11 05:27:49 PM PDT 24 336662530000 ps
T22 /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.1668917868 Jul 11 04:48:55 PM PDT 24 Jul 11 05:26:26 PM PDT 24 336761230000 ps
T23 /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.2114986551 Jul 11 04:47:45 PM PDT 24 Jul 11 05:27:51 PM PDT 24 336896710000 ps
T24 /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.452251909 Jul 11 04:47:44 PM PDT 24 Jul 11 05:24:38 PM PDT 24 336475350000 ps
T25 /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.1381199632 Jul 11 04:47:41 PM PDT 24 Jul 11 05:17:12 PM PDT 24 337004430000 ps
T26 /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.4153855829 Jul 11 04:47:43 PM PDT 24 Jul 11 05:21:53 PM PDT 24 336799410000 ps
T27 /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.3319475770 Jul 11 04:47:41 PM PDT 24 Jul 11 05:12:56 PM PDT 24 337165130000 ps
T28 /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.2792357553 Jul 11 04:47:43 PM PDT 24 Jul 11 05:21:59 PM PDT 24 336832170000 ps
T29 /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.2582604131 Jul 11 04:47:45 PM PDT 24 Jul 11 05:24:19 PM PDT 24 336872270000 ps
T30 /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.173578672 Jul 11 04:47:47 PM PDT 24 Jul 11 05:24:16 PM PDT 24 336542390000 ps
T161 /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.4151707841 Jul 11 04:47:42 PM PDT 24 Jul 11 05:13:00 PM PDT 24 336534590000 ps
T162 /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.2944692754 Jul 11 04:47:45 PM PDT 24 Jul 11 05:28:01 PM PDT 24 336421630000 ps
T163 /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.4107595530 Jul 11 04:47:42 PM PDT 24 Jul 11 05:16:13 PM PDT 24 336840090000 ps
T164 /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.1439348902 Jul 11 04:47:43 PM PDT 24 Jul 11 05:22:41 PM PDT 24 336866270000 ps
T165 /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.1144384212 Jul 11 04:47:40 PM PDT 24 Jul 11 05:10:53 PM PDT 24 336781690000 ps
T166 /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.639875512 Jul 11 04:47:44 PM PDT 24 Jul 11 05:19:20 PM PDT 24 336522290000 ps
T167 /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.693760674 Jul 11 04:47:43 PM PDT 24 Jul 11 05:22:06 PM PDT 24 336972370000 ps
T168 /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.3254827764 Jul 11 04:47:43 PM PDT 24 Jul 11 05:22:56 PM PDT 24 336671770000 ps
T169 /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.3935582142 Jul 11 04:47:48 PM PDT 24 Jul 11 05:16:59 PM PDT 24 336679730000 ps
T170 /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.348250406 Jul 11 04:47:41 PM PDT 24 Jul 11 05:18:50 PM PDT 24 336735390000 ps
T171 /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.1370754938 Jul 11 04:47:44 PM PDT 24 Jul 11 05:17:46 PM PDT 24 336892370000 ps
T172 /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.2889429575 Jul 11 04:47:42 PM PDT 24 Jul 11 05:16:26 PM PDT 24 336823350000 ps
T173 /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.3196673253 Jul 11 04:47:44 PM PDT 24 Jul 11 05:17:12 PM PDT 24 337054990000 ps
T174 /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.603932089 Jul 11 04:47:43 PM PDT 24 Jul 11 05:14:17 PM PDT 24 336446870000 ps
T175 /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.1262719952 Jul 11 04:47:40 PM PDT 24 Jul 11 05:28:45 PM PDT 24 336887470000 ps
T176 /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.2897356326 Jul 11 04:47:42 PM PDT 24 Jul 11 05:13:29 PM PDT 24 336463650000 ps
T177 /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.3236938397 Jul 11 04:47:47 PM PDT 24 Jul 11 05:13:25 PM PDT 24 336622870000 ps
T178 /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.2031081399 Jul 11 04:48:44 PM PDT 24 Jul 11 05:26:40 PM PDT 24 336524790000 ps
T179 /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.109961557 Jul 11 04:47:43 PM PDT 24 Jul 11 05:29:36 PM PDT 24 336611870000 ps
T180 /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.608515794 Jul 11 04:48:56 PM PDT 24 Jul 11 05:27:52 PM PDT 24 336958450000 ps
T181 /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.865867671 Jul 11 04:47:42 PM PDT 24 Jul 11 05:18:40 PM PDT 24 336734950000 ps
T182 /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.4164007938 Jul 11 04:47:41 PM PDT 24 Jul 11 05:22:17 PM PDT 24 337017350000 ps
T183 /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.1504898687 Jul 11 04:47:39 PM PDT 24 Jul 11 05:17:49 PM PDT 24 336612270000 ps
T184 /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.1290253679 Jul 11 04:47:42 PM PDT 24 Jul 11 05:11:15 PM PDT 24 336411950000 ps
T185 /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.4278509987 Jul 11 04:47:46 PM PDT 24 Jul 11 05:19:01 PM PDT 24 337029390000 ps
T186 /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.1342383394 Jul 11 04:47:41 PM PDT 24 Jul 11 05:18:48 PM PDT 24 336878510000 ps
T187 /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3821048416 Jul 11 04:47:48 PM PDT 24 Jul 11 05:15:59 PM PDT 24 337015250000 ps
T188 /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.1442621938 Jul 11 04:47:44 PM PDT 24 Jul 11 05:24:18 PM PDT 24 336856430000 ps
T189 /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1571226253 Jul 11 04:47:45 PM PDT 24 Jul 11 05:14:41 PM PDT 24 336323650000 ps
T190 /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.3355463113 Jul 11 04:47:47 PM PDT 24 Jul 11 05:17:59 PM PDT 24 336760590000 ps
T191 /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.1192032847 Jul 11 04:47:42 PM PDT 24 Jul 11 05:18:24 PM PDT 24 336583230000 ps
T192 /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.2701809426 Jul 11 04:47:40 PM PDT 24 Jul 11 05:13:16 PM PDT 24 336352730000 ps
T193 /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.1201164446 Jul 11 04:47:44 PM PDT 24 Jul 11 05:24:39 PM PDT 24 336361650000 ps
T194 /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.1317370653 Jul 11 04:47:46 PM PDT 24 Jul 11 05:18:08 PM PDT 24 337033850000 ps
T195 /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.2175620090 Jul 11 04:47:40 PM PDT 24 Jul 11 05:18:58 PM PDT 24 336892470000 ps
T196 /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.3582486314 Jul 11 04:47:50 PM PDT 24 Jul 11 05:18:34 PM PDT 24 336569170000 ps
T197 /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.3213502483 Jul 11 04:47:40 PM PDT 24 Jul 11 05:18:19 PM PDT 24 336719610000 ps
T198 /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.4233652792 Jul 11 04:47:45 PM PDT 24 Jul 11 05:24:21 PM PDT 24 336881710000 ps
T199 /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.520121542 Jul 11 04:47:41 PM PDT 24 Jul 11 05:29:58 PM PDT 24 336674110000 ps
T200 /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.2549884501 Jul 11 04:47:46 PM PDT 24 Jul 11 05:19:03 PM PDT 24 336531490000 ps

Test location /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.2279227834
Short name T7
Test name
Test status
Simulation time 1452870000 ps
CPU time 3.82 seconds
Started Jul 11 04:55:12 PM PDT 24
Finished Jul 11 04:55:23 PM PDT 24
Peak memory 164932 kb
Host smart-507e5db6-656f-4313-9dad-31e4471f056f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2279227834 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.2279227834
Directory /workspace/15.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.3373181898
Short name T15
Test name
Test status
Simulation time 336575010000 ps
CPU time 802.81 seconds
Started Jul 11 04:55:01 PM PDT 24
Finished Jul 11 05:27:52 PM PDT 24
Peak memory 160720 kb
Host smart-001b185c-8690-48e5-9cd8-d18d6268aeda
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3373181898 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.3373181898
Directory /workspace/11.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.1668917868
Short name T22
Test name
Test status
Simulation time 336761230000 ps
CPU time 888.71 seconds
Started Jul 11 04:48:55 PM PDT 24
Finished Jul 11 05:26:26 PM PDT 24
Peak memory 160588 kb
Host smart-4e0a8fb7-41f8-44eb-83e1-29ad1fe83f5c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1668917868 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.1668917868
Directory /workspace/0.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.2023732500
Short name T96
Test name
Test status
Simulation time 336903390000 ps
CPU time 893.5 seconds
Started Jul 11 04:54:55 PM PDT 24
Finished Jul 11 05:31:56 PM PDT 24
Peak memory 160800 kb
Host smart-5d44eed8-2de8-43de-8b23-07f311f77bdb
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2023732500 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.2023732500
Directory /workspace/0.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.4241674681
Short name T101
Test name
Test status
Simulation time 336457250000 ps
CPU time 832.73 seconds
Started Jul 11 04:54:56 PM PDT 24
Finished Jul 11 05:28:51 PM PDT 24
Peak memory 160792 kb
Host smart-7fdb6183-5156-42f4-8aa1-70cd1f518eb5
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4241674681 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.4241674681
Directory /workspace/1.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.1808484394
Short name T105
Test name
Test status
Simulation time 336959870000 ps
CPU time 574.45 seconds
Started Jul 11 04:55:00 PM PDT 24
Finished Jul 11 05:19:14 PM PDT 24
Peak memory 160800 kb
Host smart-4854395e-c4d5-4bfc-a1d5-2717947b7d29
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1808484394 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.1808484394
Directory /workspace/10.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.169759353
Short name T102
Test name
Test status
Simulation time 336639710000 ps
CPU time 697.34 seconds
Started Jul 11 04:55:03 PM PDT 24
Finished Jul 11 05:23:44 PM PDT 24
Peak memory 160700 kb
Host smart-9d19dd08-7c69-4947-a228-d4891640128b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=169759353 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.169759353
Directory /workspace/12.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.372695380
Short name T98
Test name
Test status
Simulation time 336595870000 ps
CPU time 837.44 seconds
Started Jul 11 04:55:02 PM PDT 24
Finished Jul 11 05:29:08 PM PDT 24
Peak memory 160796 kb
Host smart-8a05d4f2-2cc5-4212-8310-2c7bef9c2351
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=372695380 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.372695380
Directory /workspace/13.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.3992709121
Short name T4
Test name
Test status
Simulation time 336486790000 ps
CPU time 770.14 seconds
Started Jul 11 04:55:10 PM PDT 24
Finished Jul 11 05:26:56 PM PDT 24
Peak memory 160808 kb
Host smart-4b0bf586-58f8-4f6e-bb2b-8fc1bbe37512
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3992709121 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.3992709121
Directory /workspace/14.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.1934764755
Short name T72
Test name
Test status
Simulation time 336569970000 ps
CPU time 634.72 seconds
Started Jul 11 04:55:05 PM PDT 24
Finished Jul 11 05:21:22 PM PDT 24
Peak memory 160764 kb
Host smart-f7bc61b1-8135-4341-9114-fb8024543243
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1934764755 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.1934764755
Directory /workspace/15.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.384513046
Short name T106
Test name
Test status
Simulation time 336344550000 ps
CPU time 909.94 seconds
Started Jul 11 04:55:08 PM PDT 24
Finished Jul 11 05:32:43 PM PDT 24
Peak memory 160720 kb
Host smart-5213346c-1697-4bbc-b307-fdec6e0b1006
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=384513046 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.384513046
Directory /workspace/16.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.4166064011
Short name T91
Test name
Test status
Simulation time 336484230000 ps
CPU time 642.7 seconds
Started Jul 11 04:55:03 PM PDT 24
Finished Jul 11 05:21:45 PM PDT 24
Peak memory 160716 kb
Host smart-614caf36-9cb0-410c-bf29-27f43460f93d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4166064011 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.4166064011
Directory /workspace/17.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.271353643
Short name T77
Test name
Test status
Simulation time 336745870000 ps
CPU time 749.45 seconds
Started Jul 11 04:55:03 PM PDT 24
Finished Jul 11 05:25:49 PM PDT 24
Peak memory 160716 kb
Host smart-f8b14c17-9f6f-46a2-81e5-4e3e7f10755b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=271353643 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.271353643
Directory /workspace/18.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.3337873959
Short name T92
Test name
Test status
Simulation time 336640770000 ps
CPU time 820.81 seconds
Started Jul 11 04:55:05 PM PDT 24
Finished Jul 11 05:28:45 PM PDT 24
Peak memory 160804 kb
Host smart-422a5a95-09ab-4b02-ae0c-e29e3b3a80b2
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3337873959 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.3337873959
Directory /workspace/19.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.3412806799
Short name T103
Test name
Test status
Simulation time 336514650000 ps
CPU time 786.72 seconds
Started Jul 11 04:54:59 PM PDT 24
Finished Jul 11 05:27:10 PM PDT 24
Peak memory 160768 kb
Host smart-f64d0869-9be6-4451-9f8d-3c7742d4673f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3412806799 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.3412806799
Directory /workspace/2.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.322156898
Short name T74
Test name
Test status
Simulation time 336775250000 ps
CPU time 807.6 seconds
Started Jul 11 04:55:08 PM PDT 24
Finished Jul 11 05:29:20 PM PDT 24
Peak memory 160788 kb
Host smart-9818c4b3-1615-4ae8-a960-8ece0533088f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=322156898 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.322156898
Directory /workspace/20.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.4229259217
Short name T76
Test name
Test status
Simulation time 336590510000 ps
CPU time 841.02 seconds
Started Jul 11 04:55:01 PM PDT 24
Finished Jul 11 05:29:28 PM PDT 24
Peak memory 160700 kb
Host smart-fc2f3e84-7cf7-4ba4-a602-fb3043821d61
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4229259217 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.4229259217
Directory /workspace/21.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.3879810292
Short name T88
Test name
Test status
Simulation time 336786570000 ps
CPU time 663.33 seconds
Started Jul 11 04:55:01 PM PDT 24
Finished Jul 11 05:22:39 PM PDT 24
Peak memory 160788 kb
Host smart-55c0e673-2c87-49ae-8245-d4d004b5a133
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3879810292 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.3879810292
Directory /workspace/22.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.694967240
Short name T79
Test name
Test status
Simulation time 336737790000 ps
CPU time 810.78 seconds
Started Jul 11 04:55:01 PM PDT 24
Finished Jul 11 05:28:00 PM PDT 24
Peak memory 160708 kb
Host smart-a871777f-043a-4975-b1a0-8e67f2a17eff
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=694967240 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.694967240
Directory /workspace/23.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.1961462702
Short name T84
Test name
Test status
Simulation time 336489930000 ps
CPU time 911.41 seconds
Started Jul 11 04:55:08 PM PDT 24
Finished Jul 11 05:32:49 PM PDT 24
Peak memory 160496 kb
Host smart-b9b7c588-9493-42a1-97c7-919d89259368
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1961462702 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.1961462702
Directory /workspace/24.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.1131079150
Short name T19
Test name
Test status
Simulation time 336526610000 ps
CPU time 698.11 seconds
Started Jul 11 04:55:03 PM PDT 24
Finished Jul 11 05:23:47 PM PDT 24
Peak memory 160708 kb
Host smart-042a2d8d-590e-4ac3-88c9-90c32909c227
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1131079150 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.1131079150
Directory /workspace/25.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.143996337
Short name T95
Test name
Test status
Simulation time 336566330000 ps
CPU time 810.25 seconds
Started Jul 11 04:55:10 PM PDT 24
Finished Jul 11 05:29:22 PM PDT 24
Peak memory 160788 kb
Host smart-f94d4c33-380a-48f3-b91d-6529fcf3dd35
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=143996337 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.143996337
Directory /workspace/26.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.2958439922
Short name T75
Test name
Test status
Simulation time 336919030000 ps
CPU time 798.22 seconds
Started Jul 11 04:55:01 PM PDT 24
Finished Jul 11 05:27:49 PM PDT 24
Peak memory 160720 kb
Host smart-1797cf3b-48d1-4ca3-bdcb-79e1b244c50b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2958439922 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.2958439922
Directory /workspace/27.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.1308353979
Short name T81
Test name
Test status
Simulation time 336829430000 ps
CPU time 806.31 seconds
Started Jul 11 04:55:05 PM PDT 24
Finished Jul 11 05:28:18 PM PDT 24
Peak memory 160804 kb
Host smart-a70777de-8ec5-4208-8eb1-af8ab196d275
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1308353979 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.1308353979
Directory /workspace/28.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.2710689969
Short name T16
Test name
Test status
Simulation time 337093070000 ps
CPU time 912.67 seconds
Started Jul 11 04:55:07 PM PDT 24
Finished Jul 11 05:32:51 PM PDT 24
Peak memory 160728 kb
Host smart-d349f27c-4040-4fd2-827c-26c44705a805
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2710689969 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.2710689969
Directory /workspace/29.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.4053741824
Short name T80
Test name
Test status
Simulation time 337065170000 ps
CPU time 660.37 seconds
Started Jul 11 04:54:55 PM PDT 24
Finished Jul 11 05:22:24 PM PDT 24
Peak memory 160696 kb
Host smart-24571e17-94c1-4b31-a1dc-c902086765bc
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4053741824 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.4053741824
Directory /workspace/3.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3623275701
Short name T107
Test name
Test status
Simulation time 336696730000 ps
CPU time 722.49 seconds
Started Jul 11 04:55:01 PM PDT 24
Finished Jul 11 05:24:31 PM PDT 24
Peak memory 160712 kb
Host smart-fe845109-fb2f-4f44-bef6-6a81fad90715
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3623275701 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.3623275701
Directory /workspace/30.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.1445949173
Short name T100
Test name
Test status
Simulation time 336557130000 ps
CPU time 932 seconds
Started Jul 11 04:54:59 PM PDT 24
Finished Jul 11 05:33:33 PM PDT 24
Peak memory 160704 kb
Host smart-8dea6973-c786-471e-bb46-627712aedb61
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1445949173 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.1445949173
Directory /workspace/31.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.3703712250
Short name T104
Test name
Test status
Simulation time 336444330000 ps
CPU time 731.22 seconds
Started Jul 11 04:55:01 PM PDT 24
Finished Jul 11 05:24:47 PM PDT 24
Peak memory 160732 kb
Host smart-8754c2e3-73f4-426d-973d-63ee9ee3f4b9
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3703712250 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.3703712250
Directory /workspace/32.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.1545469170
Short name T109
Test name
Test status
Simulation time 336434430000 ps
CPU time 988.12 seconds
Started Jul 11 04:55:05 PM PDT 24
Finished Jul 11 05:35:50 PM PDT 24
Peak memory 160808 kb
Host smart-95dacff8-a2a6-4239-9c64-57ce6704e600
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1545469170 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.1545469170
Directory /workspace/33.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.3557237944
Short name T93
Test name
Test status
Simulation time 336370890000 ps
CPU time 814.18 seconds
Started Jul 11 04:55:10 PM PDT 24
Finished Jul 11 05:29:17 PM PDT 24
Peak memory 160796 kb
Host smart-32b82057-2a9b-4062-b1d9-bc926830e45c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3557237944 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.3557237944
Directory /workspace/34.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.1073265144
Short name T82
Test name
Test status
Simulation time 337140630000 ps
CPU time 891.49 seconds
Started Jul 11 04:55:34 PM PDT 24
Finished Jul 11 05:32:42 PM PDT 24
Peak memory 160808 kb
Host smart-50022a0e-375d-405d-8f4e-485b5c9a43bd
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1073265144 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.1073265144
Directory /workspace/35.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.652364378
Short name T5
Test name
Test status
Simulation time 336708750000 ps
CPU time 753.58 seconds
Started Jul 11 04:55:11 PM PDT 24
Finished Jul 11 05:26:25 PM PDT 24
Peak memory 160736 kb
Host smart-b0fcdb15-1ae2-4418-a815-e4743cba7dd1
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=652364378 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.652364378
Directory /workspace/36.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.2248904226
Short name T6
Test name
Test status
Simulation time 336812950000 ps
CPU time 916.95 seconds
Started Jul 11 04:55:03 PM PDT 24
Finished Jul 11 05:32:55 PM PDT 24
Peak memory 160664 kb
Host smart-6147450d-e36e-436e-b509-20b63ef19ed2
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2248904226 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.2248904226
Directory /workspace/37.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.878070349
Short name T86
Test name
Test status
Simulation time 336367450000 ps
CPU time 745.48 seconds
Started Jul 11 04:55:07 PM PDT 24
Finished Jul 11 05:25:54 PM PDT 24
Peak memory 160716 kb
Host smart-1cce685a-3b38-4a2e-94f5-7e5bf06b0ec2
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=878070349 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.878070349
Directory /workspace/38.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.4077869802
Short name T94
Test name
Test status
Simulation time 336593450000 ps
CPU time 594.73 seconds
Started Jul 11 04:55:12 PM PDT 24
Finished Jul 11 05:19:58 PM PDT 24
Peak memory 160784 kb
Host smart-119a6338-d36b-4971-bfa4-9f406d0e4633
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4077869802 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.4077869802
Directory /workspace/39.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.3052500869
Short name T78
Test name
Test status
Simulation time 336466870000 ps
CPU time 608.37 seconds
Started Jul 11 04:54:56 PM PDT 24
Finished Jul 11 05:20:49 PM PDT 24
Peak memory 160692 kb
Host smart-2d3a69ae-f216-43d3-8a6e-069c92fd6ec0
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3052500869 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.3052500869
Directory /workspace/4.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.3762635122
Short name T20
Test name
Test status
Simulation time 336599890000 ps
CPU time 639.39 seconds
Started Jul 11 04:55:06 PM PDT 24
Finished Jul 11 05:21:34 PM PDT 24
Peak memory 160720 kb
Host smart-09971d84-05c8-4488-a7a3-535ff2477c11
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3762635122 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.3762635122
Directory /workspace/40.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.3538570812
Short name T85
Test name
Test status
Simulation time 336448630000 ps
CPU time 787.15 seconds
Started Jul 11 04:55:06 PM PDT 24
Finished Jul 11 05:27:20 PM PDT 24
Peak memory 160776 kb
Host smart-0b9fda95-c43a-4c94-ba32-85b6089f0bc4
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3538570812 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.3538570812
Directory /workspace/41.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.2777509475
Short name T87
Test name
Test status
Simulation time 336531210000 ps
CPU time 676.44 seconds
Started Jul 11 04:55:07 PM PDT 24
Finished Jul 11 05:23:03 PM PDT 24
Peak memory 160792 kb
Host smart-3b553fe9-a191-4178-b1e8-0270af52b6ce
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2777509475 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.2777509475
Directory /workspace/42.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.3802383881
Short name T18
Test name
Test status
Simulation time 336548910000 ps
CPU time 809.57 seconds
Started Jul 11 04:55:06 PM PDT 24
Finished Jul 11 05:28:30 PM PDT 24
Peak memory 160804 kb
Host smart-f24661fd-e28b-448a-8358-f5f5d0f91c4b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3802383881 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.3802383881
Directory /workspace/43.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.1868516996
Short name T17
Test name
Test status
Simulation time 336735990000 ps
CPU time 750.43 seconds
Started Jul 11 04:55:11 PM PDT 24
Finished Jul 11 05:26:25 PM PDT 24
Peak memory 160744 kb
Host smart-f49c2872-1bd4-4cc8-9780-98ea1e64ced1
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1868516996 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.1868516996
Directory /workspace/44.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.4047455866
Short name T110
Test name
Test status
Simulation time 336595070000 ps
CPU time 755.27 seconds
Started Jul 11 04:55:12 PM PDT 24
Finished Jul 11 05:26:31 PM PDT 24
Peak memory 160744 kb
Host smart-4c363646-dd30-40b8-95e9-3cba3da57c75
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4047455866 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.4047455866
Directory /workspace/45.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.3421766240
Short name T99
Test name
Test status
Simulation time 336572690000 ps
CPU time 785.68 seconds
Started Jul 11 04:55:05 PM PDT 24
Finished Jul 11 05:27:08 PM PDT 24
Peak memory 160796 kb
Host smart-88331d20-ff05-4122-8c12-90d07d112a14
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3421766240 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.3421766240
Directory /workspace/46.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.1913618148
Short name T108
Test name
Test status
Simulation time 336571290000 ps
CPU time 761.56 seconds
Started Jul 11 04:55:12 PM PDT 24
Finished Jul 11 05:26:20 PM PDT 24
Peak memory 160800 kb
Host smart-4db58bb3-0a17-449e-ade2-27512396674b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1913618148 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.1913618148
Directory /workspace/47.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.3394904000
Short name T71
Test name
Test status
Simulation time 336631430000 ps
CPU time 834.53 seconds
Started Jul 11 04:55:05 PM PDT 24
Finished Jul 11 05:29:17 PM PDT 24
Peak memory 160804 kb
Host smart-795fd266-3b53-4789-8987-78842dab421c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3394904000 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.3394904000
Directory /workspace/48.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.986271642
Short name T14
Test name
Test status
Simulation time 336338830000 ps
CPU time 742.87 seconds
Started Jul 11 04:55:07 PM PDT 24
Finished Jul 11 05:25:47 PM PDT 24
Peak memory 160716 kb
Host smart-6d81c1af-70a0-4a70-a753-e5aabe90dcfb
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=986271642 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.986271642
Directory /workspace/49.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.456486299
Short name T83
Test name
Test status
Simulation time 336861490000 ps
CPU time 683.98 seconds
Started Jul 11 04:54:59 PM PDT 24
Finished Jul 11 05:23:02 PM PDT 24
Peak memory 160780 kb
Host smart-d74930ca-cca6-4a60-977a-00b4dacb6764
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=456486299 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.456486299
Directory /workspace/5.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.2218269428
Short name T89
Test name
Test status
Simulation time 336785490000 ps
CPU time 832.25 seconds
Started Jul 11 04:54:58 PM PDT 24
Finished Jul 11 05:28:57 PM PDT 24
Peak memory 160792 kb
Host smart-f5c44b36-fe58-4e81-85ee-128554ac5b00
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2218269428 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.2218269428
Directory /workspace/6.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.2683811333
Short name T90
Test name
Test status
Simulation time 336723070000 ps
CPU time 782.68 seconds
Started Jul 11 04:55:11 PM PDT 24
Finished Jul 11 05:27:19 PM PDT 24
Peak memory 160800 kb
Host smart-370e70dd-590e-406f-82e6-51fce3c3ab9c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2683811333 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.2683811333
Directory /workspace/7.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1185679645
Short name T97
Test name
Test status
Simulation time 336980510000 ps
CPU time 680.51 seconds
Started Jul 11 04:54:59 PM PDT 24
Finished Jul 11 05:23:12 PM PDT 24
Peak memory 160716 kb
Host smart-3a13f04a-5bd0-476d-ac36-8cda05bec234
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1185679645 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.1185679645
Directory /workspace/8.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.3246444224
Short name T73
Test name
Test status
Simulation time 336374690000 ps
CPU time 908.26 seconds
Started Jul 11 04:55:08 PM PDT 24
Finished Jul 11 05:32:40 PM PDT 24
Peak memory 160504 kb
Host smart-befad6ef-fce7-43f9-bae1-aa6b901a0fb6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3246444224 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.3246444224
Directory /workspace/9.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.4153855829
Short name T26
Test name
Test status
Simulation time 336799410000 ps
CPU time 823.38 seconds
Started Jul 11 04:47:43 PM PDT 24
Finished Jul 11 05:21:53 PM PDT 24
Peak memory 160700 kb
Host smart-0d24a151-e745-45c9-974b-bcb6c0740495
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4153855829 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.4153855829
Directory /workspace/1.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.1370754938
Short name T171
Test name
Test status
Simulation time 336892370000 ps
CPU time 731.23 seconds
Started Jul 11 04:47:44 PM PDT 24
Finished Jul 11 05:17:46 PM PDT 24
Peak memory 160724 kb
Host smart-c5ae0dbb-4c67-4b09-989c-1417071379a4
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1370754938 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.1370754938
Directory /workspace/10.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.608515794
Short name T180
Test name
Test status
Simulation time 336958450000 ps
CPU time 924.67 seconds
Started Jul 11 04:48:56 PM PDT 24
Finished Jul 11 05:27:52 PM PDT 24
Peak memory 160592 kb
Host smart-e4cc593f-b528-4aea-96a2-f220fe3a88ef
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=608515794 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.608515794
Directory /workspace/11.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.1262719952
Short name T175
Test name
Test status
Simulation time 336887470000 ps
CPU time 1003.14 seconds
Started Jul 11 04:47:40 PM PDT 24
Finished Jul 11 05:28:45 PM PDT 24
Peak memory 160808 kb
Host smart-11d81ef3-26d0-4d79-b811-b1514f3e21f7
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1262719952 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.1262719952
Directory /workspace/12.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.1504898687
Short name T183
Test name
Test status
Simulation time 336612270000 ps
CPU time 726.82 seconds
Started Jul 11 04:47:39 PM PDT 24
Finished Jul 11 05:17:49 PM PDT 24
Peak memory 160796 kb
Host smart-7ca39873-b119-48c6-b86f-060ec6fafdea
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1504898687 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.1504898687
Directory /workspace/13.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.4278509987
Short name T185
Test name
Test status
Simulation time 337029390000 ps
CPU time 763.97 seconds
Started Jul 11 04:47:46 PM PDT 24
Finished Jul 11 05:19:01 PM PDT 24
Peak memory 160708 kb
Host smart-f102b011-7a3d-4447-b418-39a12dd5fcba
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4278509987 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.4278509987
Directory /workspace/14.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.3254827764
Short name T168
Test name
Test status
Simulation time 336671770000 ps
CPU time 852.95 seconds
Started Jul 11 04:47:43 PM PDT 24
Finished Jul 11 05:22:56 PM PDT 24
Peak memory 160340 kb
Host smart-889d1f5f-28ab-4735-89e1-c5871b78fb81
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3254827764 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.3254827764
Directory /workspace/15.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.520121542
Short name T199
Test name
Test status
Simulation time 336674110000 ps
CPU time 1028.9 seconds
Started Jul 11 04:47:41 PM PDT 24
Finished Jul 11 05:29:58 PM PDT 24
Peak memory 160800 kb
Host smart-26db2784-2e19-4ca6-baab-4e7d7400ce46
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=520121542 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.520121542
Directory /workspace/16.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.3213502483
Short name T197
Test name
Test status
Simulation time 336719610000 ps
CPU time 735.45 seconds
Started Jul 11 04:47:40 PM PDT 24
Finished Jul 11 05:18:19 PM PDT 24
Peak memory 160796 kb
Host smart-eb58652d-dfa1-48ca-aef0-56df3fb2da89
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3213502483 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.3213502483
Directory /workspace/17.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.1439348902
Short name T164
Test name
Test status
Simulation time 336866270000 ps
CPU time 848.66 seconds
Started Jul 11 04:47:43 PM PDT 24
Finished Jul 11 05:22:41 PM PDT 24
Peak memory 160708 kb
Host smart-4c7f7de0-5a77-4c60-b03f-384a6adf0ae8
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1439348902 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.1439348902
Directory /workspace/18.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.4164007938
Short name T182
Test name
Test status
Simulation time 337017350000 ps
CPU time 850.15 seconds
Started Jul 11 04:47:41 PM PDT 24
Finished Jul 11 05:22:17 PM PDT 24
Peak memory 160724 kb
Host smart-f984d560-4b43-4076-8814-7a0487624798
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4164007938 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.4164007938
Directory /workspace/19.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.348250406
Short name T170
Test name
Test status
Simulation time 336735390000 ps
CPU time 754.73 seconds
Started Jul 11 04:47:41 PM PDT 24
Finished Jul 11 05:18:50 PM PDT 24
Peak memory 160760 kb
Host smart-f0bf290f-abd4-40c1-a99e-64b1f3258692
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=348250406 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.348250406
Directory /workspace/2.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.1317370653
Short name T194
Test name
Test status
Simulation time 337033850000 ps
CPU time 725.87 seconds
Started Jul 11 04:47:46 PM PDT 24
Finished Jul 11 05:18:08 PM PDT 24
Peak memory 160724 kb
Host smart-89fb5638-23b0-4ce4-bf61-865f24c494f8
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1317370653 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.1317370653
Directory /workspace/20.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3821048416
Short name T187
Test name
Test status
Simulation time 337015250000 ps
CPU time 680.03 seconds
Started Jul 11 04:47:48 PM PDT 24
Finished Jul 11 05:15:59 PM PDT 24
Peak memory 160712 kb
Host smart-afc07bd6-9944-47e2-b28f-428e1e1faae4
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3821048416 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.3821048416
Directory /workspace/21.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.2889429575
Short name T172
Test name
Test status
Simulation time 336823350000 ps
CPU time 693.51 seconds
Started Jul 11 04:47:42 PM PDT 24
Finished Jul 11 05:16:26 PM PDT 24
Peak memory 160908 kb
Host smart-8ef7c924-ca68-42c4-9f71-533f4a2d3441
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2889429575 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.2889429575
Directory /workspace/22.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.109961557
Short name T179
Test name
Test status
Simulation time 336611870000 ps
CPU time 1014.67 seconds
Started Jul 11 04:47:43 PM PDT 24
Finished Jul 11 05:29:36 PM PDT 24
Peak memory 160800 kb
Host smart-73ecd913-4ad7-4598-a4a3-63f5380313e6
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=109961557 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.109961557
Directory /workspace/23.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.603932089
Short name T174
Test name
Test status
Simulation time 336446870000 ps
CPU time 634.74 seconds
Started Jul 11 04:47:43 PM PDT 24
Finished Jul 11 05:14:17 PM PDT 24
Peak memory 160720 kb
Host smart-578a5261-b6d3-4c4d-b545-c945d1410cf7
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=603932089 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.603932089
Directory /workspace/24.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.1381199632
Short name T25
Test name
Test status
Simulation time 337004430000 ps
CPU time 721.58 seconds
Started Jul 11 04:47:41 PM PDT 24
Finished Jul 11 05:17:12 PM PDT 24
Peak memory 160796 kb
Host smart-bdcdeb69-e0ef-4e22-ab3e-ba009e0c2502
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1381199632 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.1381199632
Directory /workspace/25.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.1342383394
Short name T186
Test name
Test status
Simulation time 336878510000 ps
CPU time 753.6 seconds
Started Jul 11 04:47:41 PM PDT 24
Finished Jul 11 05:18:48 PM PDT 24
Peak memory 160768 kb
Host smart-d9c64f0d-9523-4864-970a-803e0386f8f9
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1342383394 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.1342383394
Directory /workspace/26.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.865867671
Short name T181
Test name
Test status
Simulation time 336734950000 ps
CPU time 758.3 seconds
Started Jul 11 04:47:42 PM PDT 24
Finished Jul 11 05:18:40 PM PDT 24
Peak memory 160792 kb
Host smart-66943f92-3eb5-41c2-b787-3ac35cbbcab6
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=865867671 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.865867671
Directory /workspace/27.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.693760674
Short name T167
Test name
Test status
Simulation time 336972370000 ps
CPU time 829.44 seconds
Started Jul 11 04:47:43 PM PDT 24
Finished Jul 11 05:22:06 PM PDT 24
Peak memory 160364 kb
Host smart-4400e427-d995-47a1-8b99-96f0bf572dc4
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=693760674 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.693760674
Directory /workspace/28.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.3582486314
Short name T196
Test name
Test status
Simulation time 336569170000 ps
CPU time 738.92 seconds
Started Jul 11 04:47:50 PM PDT 24
Finished Jul 11 05:18:34 PM PDT 24
Peak memory 160800 kb
Host smart-9e26bc82-9e47-4feb-af8e-96864eb0b24c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3582486314 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.3582486314
Directory /workspace/29.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.2701809426
Short name T192
Test name
Test status
Simulation time 336352730000 ps
CPU time 618.14 seconds
Started Jul 11 04:47:40 PM PDT 24
Finished Jul 11 05:13:16 PM PDT 24
Peak memory 160692 kb
Host smart-9104e8de-3dfa-4405-8f13-5b7a76675dab
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2701809426 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.2701809426
Directory /workspace/3.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.639875512
Short name T166
Test name
Test status
Simulation time 336522290000 ps
CPU time 768.72 seconds
Started Jul 11 04:47:44 PM PDT 24
Finished Jul 11 05:19:20 PM PDT 24
Peak memory 160708 kb
Host smart-c23f08cc-1ea5-43e9-a325-5edb17efa387
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=639875512 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.639875512
Directory /workspace/30.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.1201164446
Short name T193
Test name
Test status
Simulation time 336361650000 ps
CPU time 902.93 seconds
Started Jul 11 04:47:44 PM PDT 24
Finished Jul 11 05:24:39 PM PDT 24
Peak memory 160652 kb
Host smart-00fd723d-ae38-4110-84ff-6d87e09e2cc0
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1201164446 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.1201164446
Directory /workspace/31.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.3319475770
Short name T27
Test name
Test status
Simulation time 337165130000 ps
CPU time 592.36 seconds
Started Jul 11 04:47:41 PM PDT 24
Finished Jul 11 05:12:56 PM PDT 24
Peak memory 160804 kb
Host smart-c8fdadf8-12ff-4f5f-a82e-6099d4fefa97
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3319475770 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.3319475770
Directory /workspace/32.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.3196673253
Short name T173
Test name
Test status
Simulation time 337054990000 ps
CPU time 704.04 seconds
Started Jul 11 04:47:44 PM PDT 24
Finished Jul 11 05:17:12 PM PDT 24
Peak memory 160800 kb
Host smart-b965ea84-2b9a-4674-a26f-6705c33bf13d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3196673253 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.3196673253
Directory /workspace/33.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.3236938397
Short name T177
Test name
Test status
Simulation time 336622870000 ps
CPU time 606.33 seconds
Started Jul 11 04:47:47 PM PDT 24
Finished Jul 11 05:13:25 PM PDT 24
Peak memory 160724 kb
Host smart-ab6196d7-3b43-4d9c-a3d9-fa3fae586949
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3236938397 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.3236938397
Directory /workspace/34.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.3935582142
Short name T169
Test name
Test status
Simulation time 336679730000 ps
CPU time 710.19 seconds
Started Jul 11 04:47:48 PM PDT 24
Finished Jul 11 05:16:59 PM PDT 24
Peak memory 160800 kb
Host smart-66b22450-a7ac-4ba4-8536-340eae08506b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3935582142 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.3935582142
Directory /workspace/35.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.2582604131
Short name T29
Test name
Test status
Simulation time 336872270000 ps
CPU time 889.17 seconds
Started Jul 11 04:47:45 PM PDT 24
Finished Jul 11 05:24:19 PM PDT 24
Peak memory 160728 kb
Host smart-773c329a-4570-41fc-b682-ddc2d9c272ef
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2582604131 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.2582604131
Directory /workspace/36.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.1192032847
Short name T191
Test name
Test status
Simulation time 336583230000 ps
CPU time 735.66 seconds
Started Jul 11 04:47:42 PM PDT 24
Finished Jul 11 05:18:24 PM PDT 24
Peak memory 160796 kb
Host smart-3719a468-d139-40c3-97c7-95435318af75
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1192032847 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.1192032847
Directory /workspace/37.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.4151707841
Short name T161
Test name
Test status
Simulation time 336534590000 ps
CPU time 602.14 seconds
Started Jul 11 04:47:42 PM PDT 24
Finished Jul 11 05:13:00 PM PDT 24
Peak memory 160800 kb
Host smart-516e8e6c-a5b2-42f0-9ad0-80a5bebce643
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4151707841 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.4151707841
Directory /workspace/38.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.2944692754
Short name T162
Test name
Test status
Simulation time 336421630000 ps
CPU time 967.76 seconds
Started Jul 11 04:47:45 PM PDT 24
Finished Jul 11 05:28:01 PM PDT 24
Peak memory 160704 kb
Host smart-826a8042-41bb-4948-991e-3a8bccde7def
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2944692754 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.2944692754
Directory /workspace/39.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.1290253679
Short name T184
Test name
Test status
Simulation time 336411950000 ps
CPU time 552 seconds
Started Jul 11 04:47:42 PM PDT 24
Finished Jul 11 05:11:15 PM PDT 24
Peak memory 160792 kb
Host smart-bb287ae7-23d2-4ed9-9e2f-5320e4c2b21e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1290253679 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.1290253679
Directory /workspace/4.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.4107595530
Short name T163
Test name
Test status
Simulation time 336840090000 ps
CPU time 690.78 seconds
Started Jul 11 04:47:42 PM PDT 24
Finished Jul 11 05:16:13 PM PDT 24
Peak memory 160908 kb
Host smart-94ccea1f-40f8-4b73-9a13-ddbfa429e818
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4107595530 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.4107595530
Directory /workspace/40.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.2114986551
Short name T23
Test name
Test status
Simulation time 336896710000 ps
CPU time 971.26 seconds
Started Jul 11 04:47:45 PM PDT 24
Finished Jul 11 05:27:51 PM PDT 24
Peak memory 160704 kb
Host smart-0b055a71-44e2-47ee-a3dc-79bac42d37e0
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2114986551 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.2114986551
Directory /workspace/41.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.173578672
Short name T30
Test name
Test status
Simulation time 336542390000 ps
CPU time 884.02 seconds
Started Jul 11 04:47:47 PM PDT 24
Finished Jul 11 05:24:16 PM PDT 24
Peak memory 160720 kb
Host smart-407c005d-b82f-4c19-a0a0-194707a6d5c2
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=173578672 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.173578672
Directory /workspace/42.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.452251909
Short name T24
Test name
Test status
Simulation time 336475350000 ps
CPU time 902.29 seconds
Started Jul 11 04:47:44 PM PDT 24
Finished Jul 11 05:24:38 PM PDT 24
Peak memory 160644 kb
Host smart-1dd47482-0afb-4ab6-9f3c-a4915159da59
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=452251909 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.452251909
Directory /workspace/43.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.1144384212
Short name T165
Test name
Test status
Simulation time 336781690000 ps
CPU time 531.73 seconds
Started Jul 11 04:47:40 PM PDT 24
Finished Jul 11 05:10:53 PM PDT 24
Peak memory 160804 kb
Host smart-665ca23f-f121-4d6a-a71b-8e56c23a783b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1144384212 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.1144384212
Directory /workspace/44.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.1442621938
Short name T188
Test name
Test status
Simulation time 336856430000 ps
CPU time 883.05 seconds
Started Jul 11 04:47:44 PM PDT 24
Finished Jul 11 05:24:18 PM PDT 24
Peak memory 160808 kb
Host smart-88d647de-a189-43e2-ab5d-7d0464e60161
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1442621938 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.1442621938
Directory /workspace/45.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.4233652792
Short name T198
Test name
Test status
Simulation time 336881710000 ps
CPU time 874.33 seconds
Started Jul 11 04:47:45 PM PDT 24
Finished Jul 11 05:24:21 PM PDT 24
Peak memory 160808 kb
Host smart-75badbbc-b39a-4341-851e-bf20191cccb0
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4233652792 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.4233652792
Directory /workspace/46.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.2792357553
Short name T28
Test name
Test status
Simulation time 336832170000 ps
CPU time 836.5 seconds
Started Jul 11 04:47:43 PM PDT 24
Finished Jul 11 05:21:59 PM PDT 24
Peak memory 160724 kb
Host smart-8ff292c1-e266-428a-af61-f2e36cac781d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2792357553 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.2792357553
Directory /workspace/47.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1571226253
Short name T189
Test name
Test status
Simulation time 336323650000 ps
CPU time 635.32 seconds
Started Jul 11 04:47:45 PM PDT 24
Finished Jul 11 05:14:41 PM PDT 24
Peak memory 160728 kb
Host smart-3ad1557b-92b4-4e6b-a542-ed7c8043bb18
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1571226253 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.1571226253
Directory /workspace/48.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.3355463113
Short name T190
Test name
Test status
Simulation time 336760590000 ps
CPU time 726.19 seconds
Started Jul 11 04:47:47 PM PDT 24
Finished Jul 11 05:17:59 PM PDT 24
Peak memory 160720 kb
Host smart-103a5871-10fa-4e3e-8c13-1968a8c4c5af
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3355463113 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.3355463113
Directory /workspace/49.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.2175620090
Short name T195
Test name
Test status
Simulation time 336892470000 ps
CPU time 761.33 seconds
Started Jul 11 04:47:40 PM PDT 24
Finished Jul 11 05:18:58 PM PDT 24
Peak memory 160760 kb
Host smart-aff8c889-6cf4-474e-94bd-4f7426b96b3a
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2175620090 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.2175620090
Directory /workspace/5.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.2549884501
Short name T200
Test name
Test status
Simulation time 336531490000 ps
CPU time 766.61 seconds
Started Jul 11 04:47:46 PM PDT 24
Finished Jul 11 05:19:03 PM PDT 24
Peak memory 160636 kb
Host smart-9091a19d-dc3f-4144-a2e6-b8aa8f747307
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2549884501 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.2549884501
Directory /workspace/6.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.2031081399
Short name T178
Test name
Test status
Simulation time 336524790000 ps
CPU time 899.32 seconds
Started Jul 11 04:48:44 PM PDT 24
Finished Jul 11 05:26:40 PM PDT 24
Peak memory 160416 kb
Host smart-3a407f1b-e35b-4fc7-9c43-b9b2da4b2ee8
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2031081399 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.2031081399
Directory /workspace/7.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.2897356326
Short name T176
Test name
Test status
Simulation time 336463650000 ps
CPU time 622.69 seconds
Started Jul 11 04:47:42 PM PDT 24
Finished Jul 11 05:13:29 PM PDT 24
Peak memory 160692 kb
Host smart-ed9097b3-4982-4090-b75b-ce9792a67d51
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2897356326 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.2897356326
Directory /workspace/8.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.1098485390
Short name T21
Test name
Test status
Simulation time 336662530000 ps
CPU time 924.33 seconds
Started Jul 11 04:48:58 PM PDT 24
Finished Jul 11 05:27:49 PM PDT 24
Peak memory 160588 kb
Host smart-82e86a49-6e09-4c8e-872a-05542053faa0
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1098485390 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.1098485390
Directory /workspace/9.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.663373821
Short name T113
Test name
Test status
Simulation time 1111170000 ps
CPU time 3.29 seconds
Started Jul 11 04:47:42 PM PDT 24
Finished Jul 11 04:47:57 PM PDT 24
Peak memory 164800 kb
Host smart-1604a41d-1f4a-49f3-bf1d-4b97551bd08e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=663373821 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.663373821
Directory /workspace/0.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.2988404960
Short name T160
Test name
Test status
Simulation time 1561990000 ps
CPU time 4.92 seconds
Started Jul 11 04:47:38 PM PDT 24
Finished Jul 11 04:47:55 PM PDT 24
Peak memory 164900 kb
Host smart-a2dd7ca0-d4c3-49d4-a505-3068a2012807
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2988404960 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.2988404960
Directory /workspace/1.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.769484297
Short name T117
Test name
Test status
Simulation time 1519950000 ps
CPU time 5.49 seconds
Started Jul 11 04:47:40 PM PDT 24
Finished Jul 11 04:47:59 PM PDT 24
Peak memory 164872 kb
Host smart-1eed0e38-23b0-4def-9d9a-c68565357358
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=769484297 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.769484297
Directory /workspace/10.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.2820267438
Short name T148
Test name
Test status
Simulation time 1472730000 ps
CPU time 4.1 seconds
Started Jul 11 04:47:32 PM PDT 24
Finished Jul 11 04:47:46 PM PDT 24
Peak memory 164808 kb
Host smart-b3ce56b9-eeec-43a0-bfba-313361a900ee
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2820267438 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.2820267438
Directory /workspace/11.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.431883172
Short name T158
Test name
Test status
Simulation time 1481850000 ps
CPU time 4.4 seconds
Started Jul 11 04:47:40 PM PDT 24
Finished Jul 11 04:47:58 PM PDT 24
Peak memory 164844 kb
Host smart-44064471-0c30-4c9f-a05c-d3d5ecca5b60
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=431883172 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.431883172
Directory /workspace/12.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.1503970304
Short name T155
Test name
Test status
Simulation time 1553130000 ps
CPU time 4.31 seconds
Started Jul 11 04:47:39 PM PDT 24
Finished Jul 11 04:47:55 PM PDT 24
Peak memory 164884 kb
Host smart-1661265b-c704-4d38-a868-fc9079f7a0fd
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1503970304 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.1503970304
Directory /workspace/13.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.3579458095
Short name T122
Test name
Test status
Simulation time 1451410000 ps
CPU time 5.25 seconds
Started Jul 11 04:47:40 PM PDT 24
Finished Jul 11 04:47:59 PM PDT 24
Peak memory 164640 kb
Host smart-a61f7e47-24e7-4e02-8e2f-3859583a6048
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3579458095 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.3579458095
Directory /workspace/14.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.1518633039
Short name T150
Test name
Test status
Simulation time 1474430000 ps
CPU time 4.86 seconds
Started Jul 11 04:47:33 PM PDT 24
Finished Jul 11 04:47:49 PM PDT 24
Peak memory 164932 kb
Host smart-e2e63912-7009-47e0-8daa-908999065ed0
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1518633039 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.1518633039
Directory /workspace/15.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.503525673
Short name T137
Test name
Test status
Simulation time 1300950000 ps
CPU time 3.56 seconds
Started Jul 11 04:47:39 PM PDT 24
Finished Jul 11 04:47:55 PM PDT 24
Peak memory 164844 kb
Host smart-20babdcd-8848-48ec-a2b1-20992ea73880
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=503525673 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.503525673
Directory /workspace/16.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.426824755
Short name T154
Test name
Test status
Simulation time 1319570000 ps
CPU time 4.44 seconds
Started Jul 11 04:47:38 PM PDT 24
Finished Jul 11 04:47:54 PM PDT 24
Peak memory 164896 kb
Host smart-f6f0d654-4224-4740-8574-a70b2744d76a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=426824755 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.426824755
Directory /workspace/17.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.2694506734
Short name T116
Test name
Test status
Simulation time 1469650000 ps
CPU time 4.2 seconds
Started Jul 11 04:47:38 PM PDT 24
Finished Jul 11 04:47:54 PM PDT 24
Peak memory 164900 kb
Host smart-80dcbc83-4b6c-422b-be33-dead9a651636
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2694506734 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.2694506734
Directory /workspace/18.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.1649631184
Short name T141
Test name
Test status
Simulation time 1460250000 ps
CPU time 4.25 seconds
Started Jul 11 04:47:32 PM PDT 24
Finished Jul 11 04:47:47 PM PDT 24
Peak memory 164928 kb
Host smart-448fd081-5141-48d0-98c2-048e3f963dd1
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1649631184 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.1649631184
Directory /workspace/19.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.2037991172
Short name T153
Test name
Test status
Simulation time 1508270000 ps
CPU time 4.36 seconds
Started Jul 11 04:47:39 PM PDT 24
Finished Jul 11 04:47:56 PM PDT 24
Peak memory 164884 kb
Host smart-d397a5a4-1e5c-4fa2-a324-2090925514f7
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2037991172 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.2037991172
Directory /workspace/2.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.1324898787
Short name T143
Test name
Test status
Simulation time 1466670000 ps
CPU time 4.02 seconds
Started Jul 11 04:47:42 PM PDT 24
Finished Jul 11 04:47:59 PM PDT 24
Peak memory 164876 kb
Host smart-03d70716-f167-45ec-add2-b89233e03fe3
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1324898787 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.1324898787
Directory /workspace/20.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.4015837448
Short name T129
Test name
Test status
Simulation time 1537010000 ps
CPU time 3.94 seconds
Started Jul 11 04:47:33 PM PDT 24
Finished Jul 11 04:47:48 PM PDT 24
Peak memory 164824 kb
Host smart-bd06ae24-333e-48eb-9432-b7bc35a240ca
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4015837448 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.4015837448
Directory /workspace/21.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.2437055988
Short name T115
Test name
Test status
Simulation time 1373530000 ps
CPU time 3.72 seconds
Started Jul 11 04:47:39 PM PDT 24
Finished Jul 11 04:47:54 PM PDT 24
Peak memory 164868 kb
Host smart-efdc68c3-f6f5-4cf8-b655-a4e23d949846
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2437055988 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.2437055988
Directory /workspace/22.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.3104934825
Short name T135
Test name
Test status
Simulation time 1462170000 ps
CPU time 4.98 seconds
Started Jul 11 04:47:46 PM PDT 24
Finished Jul 11 04:48:05 PM PDT 24
Peak memory 164780 kb
Host smart-d070cddb-eec6-479a-8d02-4e2fea834a92
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3104934825 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.3104934825
Directory /workspace/23.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.421342068
Short name T133
Test name
Test status
Simulation time 1437010000 ps
CPU time 4.7 seconds
Started Jul 11 04:47:42 PM PDT 24
Finished Jul 11 04:48:00 PM PDT 24
Peak memory 164844 kb
Host smart-75cafc29-e1c3-4b6b-b228-50d55763075a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=421342068 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.421342068
Directory /workspace/24.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.1793574385
Short name T157
Test name
Test status
Simulation time 1482630000 ps
CPU time 4.1 seconds
Started Jul 11 04:47:41 PM PDT 24
Finished Jul 11 04:47:58 PM PDT 24
Peak memory 164824 kb
Host smart-6fc72fc5-136f-42c9-a36e-c0081304aa84
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1793574385 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.1793574385
Directory /workspace/25.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2801523582
Short name T145
Test name
Test status
Simulation time 1285350000 ps
CPU time 3.9 seconds
Started Jul 11 04:47:39 PM PDT 24
Finished Jul 11 04:47:55 PM PDT 24
Peak memory 164768 kb
Host smart-deb26eec-d404-4e08-8b6f-707d99113cbb
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2801523582 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.2801523582
Directory /workspace/26.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.1980744983
Short name T114
Test name
Test status
Simulation time 1550730000 ps
CPU time 5.6 seconds
Started Jul 11 04:48:58 PM PDT 24
Finished Jul 11 04:49:17 PM PDT 24
Peak memory 164636 kb
Host smart-25f2878d-1f38-4951-aa00-8b104096b293
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1980744983 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.1980744983
Directory /workspace/27.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.4094375393
Short name T121
Test name
Test status
Simulation time 1431190000 ps
CPU time 3.08 seconds
Started Jul 11 04:47:41 PM PDT 24
Finished Jul 11 04:47:56 PM PDT 24
Peak memory 164904 kb
Host smart-1d10b3cf-3a1c-4cb8-9aa0-2f712d12ea70
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4094375393 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.4094375393
Directory /workspace/28.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.853274745
Short name T142
Test name
Test status
Simulation time 1317810000 ps
CPU time 3.86 seconds
Started Jul 11 04:47:39 PM PDT 24
Finished Jul 11 04:47:55 PM PDT 24
Peak memory 164852 kb
Host smart-a2e8cd43-ab20-493c-856c-50af2f93c7c7
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=853274745 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.853274745
Directory /workspace/29.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.2181896602
Short name T138
Test name
Test status
Simulation time 1645390000 ps
CPU time 4.66 seconds
Started Jul 11 04:47:42 PM PDT 24
Finished Jul 11 04:48:00 PM PDT 24
Peak memory 164876 kb
Host smart-1ba0e8b6-cb48-40e3-b162-c03c8a0500a4
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2181896602 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.2181896602
Directory /workspace/3.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.3376826175
Short name T149
Test name
Test status
Simulation time 1590910000 ps
CPU time 4.25 seconds
Started Jul 11 04:47:37 PM PDT 24
Finished Jul 11 04:47:53 PM PDT 24
Peak memory 164896 kb
Host smart-84588d8b-f0f7-49fb-b7dd-5d2bd2c44b6b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3376826175 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.3376826175
Directory /workspace/30.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.2619300756
Short name T132
Test name
Test status
Simulation time 1558350000 ps
CPU time 5.62 seconds
Started Jul 11 04:47:40 PM PDT 24
Finished Jul 11 04:47:59 PM PDT 24
Peak memory 164876 kb
Host smart-864d78fa-d4aa-432b-b990-9b3ce23c7bc4
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2619300756 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.2619300756
Directory /workspace/31.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.2848648361
Short name T152
Test name
Test status
Simulation time 1193370000 ps
CPU time 4.04 seconds
Started Jul 11 04:47:40 PM PDT 24
Finished Jul 11 04:47:57 PM PDT 24
Peak memory 164876 kb
Host smart-a73c91c0-bfeb-45a3-99bb-68bf5a3c7741
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2848648361 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.2848648361
Directory /workspace/32.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.448550729
Short name T144
Test name
Test status
Simulation time 1475590000 ps
CPU time 4.55 seconds
Started Jul 11 04:47:38 PM PDT 24
Finished Jul 11 04:47:55 PM PDT 24
Peak memory 164896 kb
Host smart-38ec7b58-68b3-43f3-a649-c53aa45948bd
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=448550729 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.448550729
Directory /workspace/33.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.3229646624
Short name T136
Test name
Test status
Simulation time 1545730000 ps
CPU time 3.67 seconds
Started Jul 11 04:47:37 PM PDT 24
Finished Jul 11 04:47:52 PM PDT 24
Peak memory 164824 kb
Host smart-4020a6a7-9774-402a-ac67-e56f28cb2ffb
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3229646624 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.3229646624
Directory /workspace/34.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.1012322055
Short name T126
Test name
Test status
Simulation time 1422690000 ps
CPU time 5.08 seconds
Started Jul 11 04:47:39 PM PDT 24
Finished Jul 11 04:47:56 PM PDT 24
Peak memory 164844 kb
Host smart-126b22f5-c606-48c2-b022-acfefab75b81
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1012322055 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.1012322055
Directory /workspace/35.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.2728948004
Short name T159
Test name
Test status
Simulation time 1491350000 ps
CPU time 5.3 seconds
Started Jul 11 04:47:40 PM PDT 24
Finished Jul 11 04:47:58 PM PDT 24
Peak memory 164928 kb
Host smart-d333366a-a18c-4e29-8837-310c8fba4c34
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2728948004 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.2728948004
Directory /workspace/36.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.3376280469
Short name T139
Test name
Test status
Simulation time 1503710000 ps
CPU time 4.9 seconds
Started Jul 11 04:47:44 PM PDT 24
Finished Jul 11 04:48:03 PM PDT 24
Peak memory 164872 kb
Host smart-c9a2370a-2c79-4907-9ea0-5866f171158d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3376280469 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.3376280469
Directory /workspace/37.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.3711191211
Short name T120
Test name
Test status
Simulation time 1595590000 ps
CPU time 5.13 seconds
Started Jul 11 04:47:44 PM PDT 24
Finished Jul 11 04:48:03 PM PDT 24
Peak memory 164872 kb
Host smart-5025ca5d-5e97-4c24-b73c-2f620b0594e1
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3711191211 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.3711191211
Directory /workspace/38.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.1997426812
Short name T140
Test name
Test status
Simulation time 1518810000 ps
CPU time 4.73 seconds
Started Jul 11 04:47:42 PM PDT 24
Finished Jul 11 04:48:01 PM PDT 24
Peak memory 164848 kb
Host smart-103a4693-d41b-4d1e-b55e-252aface63ed
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1997426812 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.1997426812
Directory /workspace/39.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.2215008349
Short name T112
Test name
Test status
Simulation time 1506770000 ps
CPU time 4.44 seconds
Started Jul 11 04:47:42 PM PDT 24
Finished Jul 11 04:47:59 PM PDT 24
Peak memory 164872 kb
Host smart-01d68da6-e3ab-4700-b311-d335b9adbe1d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2215008349 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.2215008349
Directory /workspace/4.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.3539894357
Short name T134
Test name
Test status
Simulation time 1503790000 ps
CPU time 4.1 seconds
Started Jul 11 04:47:37 PM PDT 24
Finished Jul 11 04:47:52 PM PDT 24
Peak memory 164860 kb
Host smart-fb7167ed-2e27-42ca-bfe0-ea28402a31cd
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3539894357 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.3539894357
Directory /workspace/40.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.2249596592
Short name T111
Test name
Test status
Simulation time 1495770000 ps
CPU time 3.67 seconds
Started Jul 11 04:47:40 PM PDT 24
Finished Jul 11 04:47:56 PM PDT 24
Peak memory 164824 kb
Host smart-adc40145-6b50-491b-adb6-74d0091896a7
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2249596592 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.2249596592
Directory /workspace/41.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.2849364987
Short name T119
Test name
Test status
Simulation time 1281090000 ps
CPU time 3.77 seconds
Started Jul 11 04:47:39 PM PDT 24
Finished Jul 11 04:47:54 PM PDT 24
Peak memory 164900 kb
Host smart-b1dcb474-9854-49c5-b6ec-9a9f0a4ca3f8
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2849364987 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.2849364987
Directory /workspace/42.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.513229087
Short name T156
Test name
Test status
Simulation time 1584170000 ps
CPU time 4.55 seconds
Started Jul 11 04:47:40 PM PDT 24
Finished Jul 11 04:47:59 PM PDT 24
Peak memory 164872 kb
Host smart-098d2afb-a30e-445d-9e5a-6d6b55ef337b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=513229087 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.513229087
Directory /workspace/43.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.3060309259
Short name T127
Test name
Test status
Simulation time 1518430000 ps
CPU time 5.24 seconds
Started Jul 11 04:47:41 PM PDT 24
Finished Jul 11 04:48:00 PM PDT 24
Peak memory 164928 kb
Host smart-40f7032c-6686-43f1-9aac-904ed3a3ba73
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3060309259 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.3060309259
Directory /workspace/44.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.3526184038
Short name T128
Test name
Test status
Simulation time 1468970000 ps
CPU time 4.17 seconds
Started Jul 11 04:47:39 PM PDT 24
Finished Jul 11 04:47:55 PM PDT 24
Peak memory 164844 kb
Host smart-681e666c-87e1-479f-b8d2-ff7c18be5537
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3526184038 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.3526184038
Directory /workspace/45.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.3534248102
Short name T147
Test name
Test status
Simulation time 1412270000 ps
CPU time 4.05 seconds
Started Jul 11 04:47:42 PM PDT 24
Finished Jul 11 04:47:58 PM PDT 24
Peak memory 164904 kb
Host smart-a53d419b-fb8f-4261-974a-4f135535ccfe
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3534248102 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.3534248102
Directory /workspace/46.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.641139139
Short name T151
Test name
Test status
Simulation time 1566030000 ps
CPU time 5.28 seconds
Started Jul 11 04:47:46 PM PDT 24
Finished Jul 11 04:48:05 PM PDT 24
Peak memory 164844 kb
Host smart-09b44cb8-e463-427f-8e54-b164a9718e52
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=641139139 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.641139139
Directory /workspace/47.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.853184152
Short name T130
Test name
Test status
Simulation time 1587510000 ps
CPU time 5.1 seconds
Started Jul 11 04:47:40 PM PDT 24
Finished Jul 11 04:47:58 PM PDT 24
Peak memory 164840 kb
Host smart-c413fbd9-02e1-49de-b0fc-4e567141e110
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=853184152 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.853184152
Directory /workspace/48.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.1549005157
Short name T131
Test name
Test status
Simulation time 1470850000 ps
CPU time 4.85 seconds
Started Jul 11 04:47:39 PM PDT 24
Finished Jul 11 04:47:57 PM PDT 24
Peak memory 164844 kb
Host smart-68124e26-8787-496f-aeec-7b362867d486
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1549005157 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.1549005157
Directory /workspace/49.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.856082788
Short name T123
Test name
Test status
Simulation time 1318810000 ps
CPU time 4.94 seconds
Started Jul 11 04:47:40 PM PDT 24
Finished Jul 11 04:47:58 PM PDT 24
Peak memory 164484 kb
Host smart-13cabb26-ff68-4150-92d4-308731d15d60
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=856082788 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.856082788
Directory /workspace/5.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.2757915907
Short name T118
Test name
Test status
Simulation time 1339710000 ps
CPU time 3.72 seconds
Started Jul 11 04:47:38 PM PDT 24
Finished Jul 11 04:47:53 PM PDT 24
Peak memory 164900 kb
Host smart-80afe27d-3685-4f2a-9cf5-d0e54ef0fe19
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2757915907 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.2757915907
Directory /workspace/6.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.2084266705
Short name T124
Test name
Test status
Simulation time 1548130000 ps
CPU time 4.38 seconds
Started Jul 11 04:47:40 PM PDT 24
Finished Jul 11 04:47:57 PM PDT 24
Peak memory 164872 kb
Host smart-8f14710c-3382-4247-8444-ef363603da8a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2084266705 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.2084266705
Directory /workspace/7.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.3684349553
Short name T146
Test name
Test status
Simulation time 1482670000 ps
CPU time 4.05 seconds
Started Jul 11 04:47:38 PM PDT 24
Finished Jul 11 04:47:54 PM PDT 24
Peak memory 164884 kb
Host smart-952c6fb4-a875-47d1-b2c5-efdabcc1b3ec
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3684349553 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.3684349553
Directory /workspace/8.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.3106841888
Short name T125
Test name
Test status
Simulation time 1344050000 ps
CPU time 3.9 seconds
Started Jul 11 04:47:43 PM PDT 24
Finished Jul 11 04:48:00 PM PDT 24
Peak memory 164876 kb
Host smart-91bec6bb-f258-473b-a7b2-627ab7d8649d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3106841888 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.3106841888
Directory /workspace/9.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.992500051
Short name T38
Test name
Test status
Simulation time 1571810000 ps
CPU time 3.92 seconds
Started Jul 11 04:55:05 PM PDT 24
Finished Jul 11 04:55:18 PM PDT 24
Peak memory 164772 kb
Host smart-a641ef2f-85ca-439b-bfcf-22e0e7ebfe9e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=992500051 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.992500051
Directory /workspace/0.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.3148515633
Short name T69
Test name
Test status
Simulation time 1401570000 ps
CPU time 4.5 seconds
Started Jul 11 04:55:08 PM PDT 24
Finished Jul 11 04:55:21 PM PDT 24
Peak memory 164832 kb
Host smart-69b718b3-13bd-45b6-b027-d769ab95fac0
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3148515633 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.3148515633
Directory /workspace/1.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.2778670832
Short name T54
Test name
Test status
Simulation time 1567210000 ps
CPU time 5.14 seconds
Started Jul 11 04:55:18 PM PDT 24
Finished Jul 11 04:55:33 PM PDT 24
Peak memory 164888 kb
Host smart-b5784d88-c508-4684-aa74-0cc88642fcf1
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2778670832 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.2778670832
Directory /workspace/10.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.2549976643
Short name T58
Test name
Test status
Simulation time 1467710000 ps
CPU time 3.31 seconds
Started Jul 11 04:55:11 PM PDT 24
Finished Jul 11 04:55:21 PM PDT 24
Peak memory 164868 kb
Host smart-85b86dfc-a6c3-4e56-90e1-9f5ff550bfa8
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2549976643 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.2549976643
Directory /workspace/11.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.218324894
Short name T68
Test name
Test status
Simulation time 1514190000 ps
CPU time 5.24 seconds
Started Jul 11 04:55:10 PM PDT 24
Finished Jul 11 04:55:24 PM PDT 24
Peak memory 164828 kb
Host smart-baa558f9-6f67-4358-b3e8-36c1b23cfd07
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=218324894 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.218324894
Directory /workspace/12.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.3047539613
Short name T34
Test name
Test status
Simulation time 1552150000 ps
CPU time 4.34 seconds
Started Jul 11 04:55:13 PM PDT 24
Finished Jul 11 04:55:25 PM PDT 24
Peak memory 164912 kb
Host smart-a13bf6c8-62eb-4d98-bcbc-705bdfd0d0e9
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3047539613 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.3047539613
Directory /workspace/13.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.1917430137
Short name T55
Test name
Test status
Simulation time 1446550000 ps
CPU time 3.79 seconds
Started Jul 11 04:55:16 PM PDT 24
Finished Jul 11 04:55:28 PM PDT 24
Peak memory 164876 kb
Host smart-5723be09-0383-4c59-b56e-4ac4a7ca3e71
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1917430137 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.1917430137
Directory /workspace/14.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.1076781444
Short name T50
Test name
Test status
Simulation time 1509430000 ps
CPU time 5.99 seconds
Started Jul 11 04:55:13 PM PDT 24
Finished Jul 11 04:55:29 PM PDT 24
Peak memory 164692 kb
Host smart-6ae0285b-18d1-4143-a16f-3038546653e5
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1076781444 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.1076781444
Directory /workspace/16.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.858204937
Short name T39
Test name
Test status
Simulation time 1386690000 ps
CPU time 4.75 seconds
Started Jul 11 04:55:17 PM PDT 24
Finished Jul 11 04:55:31 PM PDT 24
Peak memory 164892 kb
Host smart-87889c6d-2719-4c06-82d5-c106f275326c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=858204937 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.858204937
Directory /workspace/17.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.1500339511
Short name T56
Test name
Test status
Simulation time 1554710000 ps
CPU time 5.45 seconds
Started Jul 11 04:55:11 PM PDT 24
Finished Jul 11 04:55:26 PM PDT 24
Peak memory 164848 kb
Host smart-ec45503a-b643-4b46-a164-51a81058f7a7
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1500339511 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.1500339511
Directory /workspace/18.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.3799690261
Short name T42
Test name
Test status
Simulation time 1385830000 ps
CPU time 4.63 seconds
Started Jul 11 04:55:09 PM PDT 24
Finished Jul 11 04:55:23 PM PDT 24
Peak memory 164904 kb
Host smart-b255059e-6b85-4181-acf1-7ace786bcefe
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3799690261 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.3799690261
Directory /workspace/19.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.3323203790
Short name T37
Test name
Test status
Simulation time 1482830000 ps
CPU time 4.21 seconds
Started Jul 11 04:55:12 PM PDT 24
Finished Jul 11 04:55:24 PM PDT 24
Peak memory 164892 kb
Host smart-979c3d0f-ba71-4fa9-a482-300087e1ba08
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3323203790 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.3323203790
Directory /workspace/2.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.3337372885
Short name T43
Test name
Test status
Simulation time 1411390000 ps
CPU time 2.96 seconds
Started Jul 11 04:55:08 PM PDT 24
Finished Jul 11 04:55:18 PM PDT 24
Peak memory 164872 kb
Host smart-511077c4-8209-4fd8-ad62-2311548ec8b0
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3337372885 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.3337372885
Directory /workspace/20.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.370610806
Short name T51
Test name
Test status
Simulation time 1567470000 ps
CPU time 4.41 seconds
Started Jul 11 04:55:15 PM PDT 24
Finished Jul 11 04:55:28 PM PDT 24
Peak memory 164884 kb
Host smart-f3ea0ecb-59d8-4603-b9bc-eeeb31d3b992
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=370610806 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.370610806
Directory /workspace/21.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.3843372042
Short name T57
Test name
Test status
Simulation time 1151110000 ps
CPU time 3.6 seconds
Started Jul 11 04:55:12 PM PDT 24
Finished Jul 11 04:55:22 PM PDT 24
Peak memory 164868 kb
Host smart-5fb518f9-73b3-49fd-b7dc-c51802d78917
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3843372042 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.3843372042
Directory /workspace/22.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.3719626936
Short name T60
Test name
Test status
Simulation time 1316410000 ps
CPU time 4.9 seconds
Started Jul 11 04:55:12 PM PDT 24
Finished Jul 11 04:55:25 PM PDT 24
Peak memory 164836 kb
Host smart-6e3dedd1-ff56-4cc5-abe1-2076cfb0bd52
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3719626936 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.3719626936
Directory /workspace/23.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.3699502963
Short name T12
Test name
Test status
Simulation time 1361090000 ps
CPU time 3.89 seconds
Started Jul 11 04:55:14 PM PDT 24
Finished Jul 11 04:55:25 PM PDT 24
Peak memory 164656 kb
Host smart-7601f719-cc01-4639-8649-2657d1287d1a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3699502963 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.3699502963
Directory /workspace/24.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.3540195416
Short name T62
Test name
Test status
Simulation time 1322710000 ps
CPU time 4.54 seconds
Started Jul 11 04:55:13 PM PDT 24
Finished Jul 11 04:55:26 PM PDT 24
Peak memory 165032 kb
Host smart-55ba63cd-b6b8-480f-baf4-5a84afb88e75
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3540195416 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.3540195416
Directory /workspace/25.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.601362838
Short name T64
Test name
Test status
Simulation time 1300530000 ps
CPU time 2.88 seconds
Started Jul 11 04:55:21 PM PDT 24
Finished Jul 11 04:55:31 PM PDT 24
Peak memory 164904 kb
Host smart-bdac3ce3-e4f4-465e-a853-efd44ba87f8e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=601362838 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.601362838
Directory /workspace/26.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.2304029210
Short name T61
Test name
Test status
Simulation time 1370370000 ps
CPU time 3.68 seconds
Started Jul 11 04:55:08 PM PDT 24
Finished Jul 11 04:55:20 PM PDT 24
Peak memory 165000 kb
Host smart-6341164b-8b0b-46ae-a050-74cc61c227fb
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2304029210 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.2304029210
Directory /workspace/27.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.4198688397
Short name T10
Test name
Test status
Simulation time 1570730000 ps
CPU time 5.76 seconds
Started Jul 11 04:55:10 PM PDT 24
Finished Jul 11 04:55:26 PM PDT 24
Peak memory 164812 kb
Host smart-59edc107-071f-4dd5-898c-d897403d9b1c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4198688397 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.4198688397
Directory /workspace/28.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.1529859499
Short name T41
Test name
Test status
Simulation time 1424010000 ps
CPU time 4.46 seconds
Started Jul 11 04:55:14 PM PDT 24
Finished Jul 11 04:55:26 PM PDT 24
Peak memory 164700 kb
Host smart-144abecc-ac35-4d00-bd7f-ebe271235ef5
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1529859499 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.1529859499
Directory /workspace/29.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.2546965742
Short name T67
Test name
Test status
Simulation time 1270490000 ps
CPU time 4.1 seconds
Started Jul 11 04:55:09 PM PDT 24
Finished Jul 11 04:55:21 PM PDT 24
Peak memory 164836 kb
Host smart-99fabcb1-fba4-4d20-8f85-9dbedc75325d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2546965742 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.2546965742
Directory /workspace/3.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.364837476
Short name T63
Test name
Test status
Simulation time 1221910000 ps
CPU time 3.78 seconds
Started Jul 11 04:55:09 PM PDT 24
Finished Jul 11 04:55:20 PM PDT 24
Peak memory 164872 kb
Host smart-6eebbd8a-9deb-4650-a912-a6e5e46df172
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=364837476 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.364837476
Directory /workspace/30.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.2704911854
Short name T32
Test name
Test status
Simulation time 1555930000 ps
CPU time 4.79 seconds
Started Jul 11 04:55:09 PM PDT 24
Finished Jul 11 04:55:22 PM PDT 24
Peak memory 164840 kb
Host smart-a9065c0b-3aa0-45b8-adbf-8786d7396e2d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2704911854 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.2704911854
Directory /workspace/31.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.2227352313
Short name T2
Test name
Test status
Simulation time 1417850000 ps
CPU time 3.96 seconds
Started Jul 11 04:55:13 PM PDT 24
Finished Jul 11 04:55:24 PM PDT 24
Peak memory 164864 kb
Host smart-7a515df9-8cdc-4f07-8596-6e2767ce3628
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2227352313 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.2227352313
Directory /workspace/32.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.93034945
Short name T33
Test name
Test status
Simulation time 1376510000 ps
CPU time 4.75 seconds
Started Jul 11 04:55:15 PM PDT 24
Finished Jul 11 04:55:28 PM PDT 24
Peak memory 164820 kb
Host smart-bd34055f-151c-438d-afd9-454964e68f46
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=93034945 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.93034945
Directory /workspace/33.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.3078630458
Short name T52
Test name
Test status
Simulation time 1377130000 ps
CPU time 4.78 seconds
Started Jul 11 04:55:13 PM PDT 24
Finished Jul 11 04:55:26 PM PDT 24
Peak memory 165032 kb
Host smart-06aef525-904c-4fbb-9f2d-dee78eb2e9df
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3078630458 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.3078630458
Directory /workspace/34.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.1423159946
Short name T47
Test name
Test status
Simulation time 1296870000 ps
CPU time 3.74 seconds
Started Jul 11 04:55:13 PM PDT 24
Finished Jul 11 04:55:23 PM PDT 24
Peak memory 164864 kb
Host smart-4c713875-a30e-46a4-ab8b-645552ed62d9
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1423159946 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.1423159946
Directory /workspace/35.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.2435125689
Short name T70
Test name
Test status
Simulation time 1529770000 ps
CPU time 5.69 seconds
Started Jul 11 04:55:13 PM PDT 24
Finished Jul 11 04:55:28 PM PDT 24
Peak memory 164700 kb
Host smart-5839fa33-adcd-416b-bb63-2e5b9cd7434d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2435125689 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.2435125689
Directory /workspace/36.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.4269969759
Short name T45
Test name
Test status
Simulation time 1302970000 ps
CPU time 3.97 seconds
Started Jul 11 04:55:15 PM PDT 24
Finished Jul 11 04:55:27 PM PDT 24
Peak memory 164888 kb
Host smart-862d7f83-ecec-4ef6-a6af-0583d35251de
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4269969759 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.4269969759
Directory /workspace/37.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.2674240955
Short name T66
Test name
Test status
Simulation time 1510050000 ps
CPU time 4.97 seconds
Started Jul 11 04:55:13 PM PDT 24
Finished Jul 11 04:55:27 PM PDT 24
Peak memory 164880 kb
Host smart-e0807996-07df-42ad-b0d1-378c07380dfb
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2674240955 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.2674240955
Directory /workspace/38.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.1070913086
Short name T8
Test name
Test status
Simulation time 1297510000 ps
CPU time 3.77 seconds
Started Jul 11 04:55:14 PM PDT 24
Finished Jul 11 04:55:25 PM PDT 24
Peak memory 164888 kb
Host smart-1e6fa02a-b55e-4ec8-a074-77b5d6e1890a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1070913086 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.1070913086
Directory /workspace/39.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.1321723325
Short name T11
Test name
Test status
Simulation time 1572330000 ps
CPU time 3.49 seconds
Started Jul 11 04:55:08 PM PDT 24
Finished Jul 11 04:55:19 PM PDT 24
Peak memory 164868 kb
Host smart-0070c3f3-a9c2-4616-b0d6-598e0b12b63c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1321723325 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.1321723325
Directory /workspace/4.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.3113504829
Short name T44
Test name
Test status
Simulation time 1577410000 ps
CPU time 4.56 seconds
Started Jul 11 04:55:14 PM PDT 24
Finished Jul 11 04:55:26 PM PDT 24
Peak memory 164888 kb
Host smart-e7ed55ca-58a3-4e8d-886c-47e351702b62
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3113504829 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.3113504829
Directory /workspace/40.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.3967547908
Short name T59
Test name
Test status
Simulation time 1543310000 ps
CPU time 4.35 seconds
Started Jul 11 04:55:16 PM PDT 24
Finished Jul 11 04:55:29 PM PDT 24
Peak memory 164908 kb
Host smart-5a46fdd2-a8d0-4c25-9b84-aa7fa6427e11
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3967547908 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.3967547908
Directory /workspace/41.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.3924221932
Short name T3
Test name
Test status
Simulation time 1571950000 ps
CPU time 4 seconds
Started Jul 11 04:55:15 PM PDT 24
Finished Jul 11 04:55:26 PM PDT 24
Peak memory 164848 kb
Host smart-be70bc13-353e-4454-a823-d34124e6140c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3924221932 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.3924221932
Directory /workspace/42.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.1486797044
Short name T65
Test name
Test status
Simulation time 1538750000 ps
CPU time 4.42 seconds
Started Jul 11 04:55:14 PM PDT 24
Finished Jul 11 04:55:26 PM PDT 24
Peak memory 164876 kb
Host smart-602db4f9-ba11-42ad-a1ae-f1b4b39f49b4
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1486797044 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.1486797044
Directory /workspace/43.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.124435074
Short name T35
Test name
Test status
Simulation time 1559570000 ps
CPU time 4.55 seconds
Started Jul 11 04:55:17 PM PDT 24
Finished Jul 11 04:55:29 PM PDT 24
Peak memory 164832 kb
Host smart-9b7b0551-c61a-4550-aa8f-aa3131ec6643
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=124435074 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.124435074
Directory /workspace/44.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.2627862299
Short name T13
Test name
Test status
Simulation time 1483930000 ps
CPU time 3.6 seconds
Started Jul 11 04:55:20 PM PDT 24
Finished Jul 11 04:55:32 PM PDT 24
Peak memory 164876 kb
Host smart-7a8a4108-b0e7-4785-bb0d-368cf03d081e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2627862299 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.2627862299
Directory /workspace/45.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.2446654803
Short name T49
Test name
Test status
Simulation time 1436710000 ps
CPU time 3.51 seconds
Started Jul 11 04:55:19 PM PDT 24
Finished Jul 11 04:55:31 PM PDT 24
Peak memory 164912 kb
Host smart-37ebef9f-a57f-4382-b0bb-0b3f3c316d2a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2446654803 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.2446654803
Directory /workspace/46.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.539664421
Short name T31
Test name
Test status
Simulation time 1518370000 ps
CPU time 4.75 seconds
Started Jul 11 04:55:14 PM PDT 24
Finished Jul 11 04:55:28 PM PDT 24
Peak memory 164876 kb
Host smart-51dada97-37f2-4ec7-b5e8-fe22b48716a8
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=539664421 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.539664421
Directory /workspace/47.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.855981162
Short name T1
Test name
Test status
Simulation time 1423410000 ps
CPU time 4.03 seconds
Started Jul 11 04:55:14 PM PDT 24
Finished Jul 11 04:55:26 PM PDT 24
Peak memory 164888 kb
Host smart-8d962d32-e32d-4943-a54e-8cea2e516983
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=855981162 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.855981162
Directory /workspace/48.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.2141448325
Short name T48
Test name
Test status
Simulation time 1562130000 ps
CPU time 5.1 seconds
Started Jul 11 04:55:18 PM PDT 24
Finished Jul 11 04:55:32 PM PDT 24
Peak memory 164888 kb
Host smart-29afe988-3e87-4a4d-ac6b-dd495a3f0f64
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2141448325 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.2141448325
Directory /workspace/49.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.2028097697
Short name T53
Test name
Test status
Simulation time 1524330000 ps
CPU time 4.4 seconds
Started Jul 11 04:55:11 PM PDT 24
Finished Jul 11 04:55:23 PM PDT 24
Peak memory 164892 kb
Host smart-b658ba99-012c-4b20-84b5-e1e474d0e064
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2028097697 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.2028097697
Directory /workspace/5.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.2148873396
Short name T9
Test name
Test status
Simulation time 1253810000 ps
CPU time 3 seconds
Started Jul 11 04:55:07 PM PDT 24
Finished Jul 11 04:55:17 PM PDT 24
Peak memory 164900 kb
Host smart-29184803-e6fe-4e5b-85a9-d253793dbe3a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2148873396 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.2148873396
Directory /workspace/6.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.3538382002
Short name T36
Test name
Test status
Simulation time 1471310000 ps
CPU time 4.47 seconds
Started Jul 11 04:55:12 PM PDT 24
Finished Jul 11 04:55:25 PM PDT 24
Peak memory 164892 kb
Host smart-479b4ef8-9d38-476d-a815-c4cc6db25813
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3538382002 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.3538382002
Directory /workspace/7.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.2965530881
Short name T46
Test name
Test status
Simulation time 1565490000 ps
CPU time 5.08 seconds
Started Jul 11 04:55:07 PM PDT 24
Finished Jul 11 04:55:22 PM PDT 24
Peak memory 164904 kb
Host smart-6aa87f7e-652c-4813-be80-59da75b4c8db
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2965530881 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.2965530881
Directory /workspace/8.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.2832694553
Short name T40
Test name
Test status
Simulation time 1392750000 ps
CPU time 4.23 seconds
Started Jul 11 04:55:13 PM PDT 24
Finished Jul 11 04:55:25 PM PDT 24
Peak memory 164880 kb
Host smart-ffba51de-cada-4d3d-9fe4-dcef9af13f48
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2832694553 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.2832694553
Directory /workspace/9.prim_lfsr_gal_smoke/latest
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