Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.31 100.00 96.55 100.00 100.00 95.00


Total tests in report: 200
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
87.31 87.31 100.00 100.00 96.55 96.55 100.00 100.00 100.00 100.00 40.00 40.00 /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.2185361966
96.81 9.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 87.50 47.50 /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.4141635595
98.31 1.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 95.00 7.50 /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.2885030850

Tests that do not contribute to grading

Name
/workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.1328736139
/workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.1475366623
/workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.4064965779
/workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.1661892240
/workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.618429519
/workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.4088627673
/workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.2602552562
/workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.490464498
/workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.2957009300
/workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.34785333
/workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.365671444
/workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.3724719230
/workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.2013069409
/workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.2245584028
/workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.3795521815
/workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.3620541897
/workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.3423134475
/workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.1691723199
/workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.553915461
/workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.2952319975
/workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.3173040454
/workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.3070381477
/workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.3328607958
/workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3683456610
/workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.2673767729
/workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.380641174
/workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.1529881917
/workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.3847080689
/workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.1041115430
/workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.1442006659
/workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.1705327936
/workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.3206154084
/workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.3408312637
/workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.3303874141
/workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.2229545072
/workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.2753111412
/workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.3140040513
/workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.1186188438
/workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.2809445546
/workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.1261664131
/workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.16622304
/workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.1325470607
/workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.815633866
/workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.293158423
/workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.625529282
/workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.3580456782
/workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.3647615764
/workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.3842667186
/workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.690689118
/workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.2078392250
/workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.1421113577
/workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.4275845616
/workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.1423284530
/workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.3468723445
/workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.495706399
/workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.140852887
/workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.3625039177
/workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.4082069786
/workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.4080709846
/workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.2698543942
/workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.3133867036
/workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.496878231
/workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.1515503614
/workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.3011949005
/workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.2455998569
/workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.3632775849
/workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.3261066670
/workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.427167803
/workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.2959290546
/workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.4225172261
/workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.3084601312
/workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.3248458592
/workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.1665858075
/workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.2581589331
/workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.138960416
/workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.3336105288
/workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.3629695177
/workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.604542078
/workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.382765011
/workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.2146368920
/workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.875521283
/workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.3545678739
/workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.3419046169
/workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.2813383643
/workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.2115365789
/workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.2537888321
/workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.3174730922
/workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.177714981
/workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.1384926643
/workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.2622868640
/workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.2124470792
/workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1987430776
/workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.1902543375
/workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.982791167
/workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.111180546
/workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.2358678729
/workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.892473805
/workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.3916058489
/workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.4070557559
/workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.2824984641
/workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.2379304937
/workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.3860462528
/workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.3702940406
/workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.3069215018
/workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.2069846655
/workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.3511558143
/workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.3939794751
/workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.1898539665
/workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.462167487
/workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.836285651
/workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.1388940214
/workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.127350954
/workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.97407983
/workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.1470245902
/workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.3278792418
/workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.2575411015
/workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.2034021613
/workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.1694642922
/workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.2578610778
/workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.161310610
/workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.3640532802
/workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.3080390594
/workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.1192782001
/workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.112710970
/workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.1464910573
/workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.2925407495
/workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.1287476437
/workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.945850127
/workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.231902587
/workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.380126831
/workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.4138628493
/workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.2837758065
/workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.679637078
/workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.588396537
/workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.3297061231
/workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.3836996798
/workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.920072768
/workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.2620936447
/workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.3899279132
/workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.561915500
/workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.3796576741
/workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.2009159341
/workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.4193516757
/workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.3587952909
/workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.2414473084
/workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.597704984
/workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.3217742461
/workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2794252868
/workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.4167471474
/workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.104718392
/workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.2144013377
/workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.1772680919
/workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.1522937041
/workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.846181860
/workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.1398060333
/workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.8049256
/workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.3761487833
/workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.85863042
/workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.3100449902
/workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.499493043
/workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.2513593203
/workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.840951609
/workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.1343657080
/workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.2939229310
/workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.393088066
/workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.3240993322
/workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.4174162098
/workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.3780084049
/workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.3107304875
/workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.1877261425
/workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.3280186472
/workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.311483877
/workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.822890859
/workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.3260566758
/workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.679784365
/workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.1419594631
/workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.4214421887
/workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.1112387013
/workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.500689930
/workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.1873593655
/workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.660993387
/workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.119369639
/workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.555255079
/workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.745566519
/workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.3744302760
/workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.187552055
/workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.79952689
/workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.903530920
/workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.856026959
/workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.1135393800
/workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.291883169
/workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.4068639313
/workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.1762073867
/workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.4160908684
/workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.955067634
/workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.54497155
/workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.978862033



Total test records in report: 200
tests.html | tests1.html | tests2.html | tests3.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.679784365 Jul 17 04:18:51 PM PDT 24 Jul 17 04:19:04 PM PDT 24 1518490000 ps
T2 /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.54497155 Jul 17 04:18:08 PM PDT 24 Jul 17 04:18:18 PM PDT 24 1413330000 ps
T3 /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.2144013377 Jul 17 04:22:34 PM PDT 24 Jul 17 04:22:45 PM PDT 24 1545290000 ps
T4 /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.187552055 Jul 17 04:23:21 PM PDT 24 Jul 17 04:23:32 PM PDT 24 1559350000 ps
T8 /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.2185361966 Jul 17 04:18:14 PM PDT 24 Jul 17 04:18:24 PM PDT 24 1483110000 ps
T9 /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.1522937041 Jul 17 04:18:09 PM PDT 24 Jul 17 04:18:19 PM PDT 24 1381090000 ps
T10 /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.4068639313 Jul 17 04:22:34 PM PDT 24 Jul 17 04:22:44 PM PDT 24 1457630000 ps
T11 /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.955067634 Jul 17 04:17:24 PM PDT 24 Jul 17 04:17:34 PM PDT 24 1527430000 ps
T12 /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.119369639 Jul 17 04:18:43 PM PDT 24 Jul 17 04:18:52 PM PDT 24 1381150000 ps
T13 /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.8049256 Jul 17 04:18:06 PM PDT 24 Jul 17 04:18:17 PM PDT 24 1354090000 ps
T31 /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.4160908684 Jul 17 04:18:43 PM PDT 24 Jul 17 04:18:52 PM PDT 24 1323010000 ps
T32 /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.3780084049 Jul 17 04:19:02 PM PDT 24 Jul 17 04:19:11 PM PDT 24 1147710000 ps
T33 /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.4214421887 Jul 17 04:24:34 PM PDT 24 Jul 17 04:24:44 PM PDT 24 1455710000 ps
T34 /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.2939229310 Jul 17 04:19:12 PM PDT 24 Jul 17 04:19:22 PM PDT 24 1571370000 ps
T35 /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.978862033 Jul 17 04:21:38 PM PDT 24 Jul 17 04:21:50 PM PDT 24 1381510000 ps
T36 /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.291883169 Jul 17 04:23:28 PM PDT 24 Jul 17 04:23:38 PM PDT 24 1571310000 ps
T37 /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.1762073867 Jul 17 04:17:06 PM PDT 24 Jul 17 04:17:15 PM PDT 24 1323370000 ps
T38 /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.822890859 Jul 17 04:21:15 PM PDT 24 Jul 17 04:21:23 PM PDT 24 1345150000 ps
T39 /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.846181860 Jul 17 04:18:06 PM PDT 24 Jul 17 04:18:17 PM PDT 24 1389430000 ps
T40 /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.393088066 Jul 17 04:24:32 PM PDT 24 Jul 17 04:24:43 PM PDT 24 1498910000 ps
T41 /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.856026959 Jul 17 04:22:42 PM PDT 24 Jul 17 04:22:51 PM PDT 24 1329910000 ps
T42 /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.1419594631 Jul 17 04:23:12 PM PDT 24 Jul 17 04:23:24 PM PDT 24 1592690000 ps
T43 /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.3107304875 Jul 17 04:17:46 PM PDT 24 Jul 17 04:17:56 PM PDT 24 1381590000 ps
T44 /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.85863042 Jul 17 04:17:48 PM PDT 24 Jul 17 04:17:55 PM PDT 24 1268110000 ps
T45 /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.500689930 Jul 17 04:21:51 PM PDT 24 Jul 17 04:22:02 PM PDT 24 1532530000 ps
T46 /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.1772680919 Jul 17 04:18:06 PM PDT 24 Jul 17 04:18:18 PM PDT 24 1571230000 ps
T47 /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.1873593655 Jul 17 04:24:33 PM PDT 24 Jul 17 04:24:42 PM PDT 24 1157170000 ps
T48 /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.4174162098 Jul 17 04:23:18 PM PDT 24 Jul 17 04:23:27 PM PDT 24 1488270000 ps
T49 /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.555255079 Jul 17 04:22:34 PM PDT 24 Jul 17 04:22:44 PM PDT 24 1409930000 ps
T50 /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.3260566758 Jul 17 04:18:50 PM PDT 24 Jul 17 04:18:58 PM PDT 24 1417450000 ps
T51 /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.1112387013 Jul 17 04:20:10 PM PDT 24 Jul 17 04:20:21 PM PDT 24 1554610000 ps
T52 /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.3761487833 Jul 17 04:18:14 PM PDT 24 Jul 17 04:18:24 PM PDT 24 1539030000 ps
T53 /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.3280186472 Jul 17 04:18:28 PM PDT 24 Jul 17 04:18:38 PM PDT 24 1557890000 ps
T54 /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.3100449902 Jul 17 04:22:19 PM PDT 24 Jul 17 04:22:32 PM PDT 24 1333930000 ps
T55 /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.1877261425 Jul 17 04:18:52 PM PDT 24 Jul 17 04:19:04 PM PDT 24 1465790000 ps
T56 /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.903530920 Jul 17 04:20:36 PM PDT 24 Jul 17 04:20:49 PM PDT 24 1596530000 ps
T57 /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.4167471474 Jul 17 04:18:46 PM PDT 24 Jul 17 04:18:59 PM PDT 24 1419130000 ps
T58 /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.840951609 Jul 17 04:17:33 PM PDT 24 Jul 17 04:17:45 PM PDT 24 1561230000 ps
T59 /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.1343657080 Jul 17 04:21:52 PM PDT 24 Jul 17 04:22:03 PM PDT 24 1504570000 ps
T60 /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.3240993322 Jul 17 04:18:33 PM PDT 24 Jul 17 04:18:43 PM PDT 24 1523370000 ps
T61 /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.660993387 Jul 17 04:24:34 PM PDT 24 Jul 17 04:24:45 PM PDT 24 1554750000 ps
T62 /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.311483877 Jul 17 04:23:34 PM PDT 24 Jul 17 04:23:43 PM PDT 24 1541190000 ps
T63 /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.745566519 Jul 17 04:21:25 PM PDT 24 Jul 17 04:21:36 PM PDT 24 1505330000 ps
T64 /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.79952689 Jul 17 04:22:28 PM PDT 24 Jul 17 04:22:37 PM PDT 24 1451230000 ps
T65 /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.2513593203 Jul 17 04:18:00 PM PDT 24 Jul 17 04:18:12 PM PDT 24 1586590000 ps
T66 /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.499493043 Jul 17 04:19:47 PM PDT 24 Jul 17 04:19:58 PM PDT 24 1622510000 ps
T67 /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.3744302760 Jul 17 04:24:18 PM PDT 24 Jul 17 04:24:27 PM PDT 24 1440470000 ps
T68 /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.1398060333 Jul 17 04:18:45 PM PDT 24 Jul 17 04:18:55 PM PDT 24 1578910000 ps
T69 /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.104718392 Jul 17 04:22:47 PM PDT 24 Jul 17 04:22:56 PM PDT 24 1480170000 ps
T70 /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.1135393800 Jul 17 04:22:51 PM PDT 24 Jul 17 04:23:01 PM PDT 24 1354210000 ps
T5 /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.4088627673 Jul 17 04:24:16 PM PDT 24 Jul 17 04:57:23 PM PDT 24 337071510000 ps
T6 /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.34785333 Jul 17 04:24:18 PM PDT 24 Jul 17 04:58:05 PM PDT 24 336405270000 ps
T7 /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.3408312637 Jul 17 04:22:15 PM PDT 24 Jul 17 04:52:36 PM PDT 24 336445950000 ps
T14 /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.380641174 Jul 17 04:24:35 PM PDT 24 Jul 17 04:52:59 PM PDT 24 336909850000 ps
T15 /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.2753111412 Jul 17 04:24:51 PM PDT 24 Jul 17 04:52:27 PM PDT 24 336412810000 ps
T16 /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.3328607958 Jul 17 04:21:52 PM PDT 24 Jul 17 04:53:04 PM PDT 24 337012150000 ps
T17 /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.4141635595 Jul 17 04:21:52 PM PDT 24 Jul 17 04:53:05 PM PDT 24 336716130000 ps
T18 /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.3206154084 Jul 17 04:22:13 PM PDT 24 Jul 17 04:52:16 PM PDT 24 336756890000 ps
T19 /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.3724719230 Jul 17 04:22:01 PM PDT 24 Jul 17 04:53:15 PM PDT 24 336501430000 ps
T20 /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.3842667186 Jul 17 04:24:15 PM PDT 24 Jul 17 04:57:04 PM PDT 24 336412030000 ps
T71 /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.3580456782 Jul 17 04:21:52 PM PDT 24 Jul 17 04:52:47 PM PDT 24 336821590000 ps
T72 /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.3070381477 Jul 17 04:20:13 PM PDT 24 Jul 17 04:47:27 PM PDT 24 336828930000 ps
T73 /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.293158423 Jul 17 04:24:39 PM PDT 24 Jul 17 05:11:07 PM PDT 24 337107750000 ps
T74 /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.1186188438 Jul 17 04:24:39 PM PDT 24 Jul 17 05:10:42 PM PDT 24 336419510000 ps
T75 /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.3647615764 Jul 17 04:20:07 PM PDT 24 Jul 17 04:54:43 PM PDT 24 336350970000 ps
T76 /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.3423134475 Jul 17 04:23:14 PM PDT 24 Jul 17 04:52:15 PM PDT 24 337057350000 ps
T77 /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.1529881917 Jul 17 04:22:02 PM PDT 24 Jul 17 04:52:59 PM PDT 24 336651970000 ps
T78 /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.2245584028 Jul 17 04:21:36 PM PDT 24 Jul 17 04:58:16 PM PDT 24 336985190000 ps
T79 /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.690689118 Jul 17 04:22:27 PM PDT 24 Jul 17 04:51:55 PM PDT 24 336395110000 ps
T80 /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.2673767729 Jul 17 04:22:12 PM PDT 24 Jul 17 04:46:46 PM PDT 24 336796010000 ps
T81 /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.2809445546 Jul 17 04:24:35 PM PDT 24 Jul 17 04:51:17 PM PDT 24 336697270000 ps
T82 /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.1661892240 Jul 17 04:22:27 PM PDT 24 Jul 17 04:52:01 PM PDT 24 336682810000 ps
T83 /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.3795521815 Jul 17 04:20:13 PM PDT 24 Jul 17 04:47:31 PM PDT 24 336328250000 ps
T84 /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.365671444 Jul 17 04:23:18 PM PDT 24 Jul 17 04:53:59 PM PDT 24 337007250000 ps
T85 /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.2957009300 Jul 17 04:23:18 PM PDT 24 Jul 17 04:50:46 PM PDT 24 336915670000 ps
T86 /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.618429519 Jul 17 04:24:15 PM PDT 24 Jul 17 04:56:53 PM PDT 24 336614450000 ps
T87 /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.1261664131 Jul 17 04:25:07 PM PDT 24 Jul 17 04:55:22 PM PDT 24 336354390000 ps
T88 /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.625529282 Jul 17 04:23:21 PM PDT 24 Jul 17 04:58:00 PM PDT 24 337085970000 ps
T89 /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.3140040513 Jul 17 04:24:27 PM PDT 24 Jul 17 04:47:41 PM PDT 24 336366190000 ps
T90 /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.1328736139 Jul 17 04:20:50 PM PDT 24 Jul 17 04:52:07 PM PDT 24 336711650000 ps
T91 /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.3847080689 Jul 17 04:22:56 PM PDT 24 Jul 17 04:56:16 PM PDT 24 336520670000 ps
T92 /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3683456610 Jul 17 04:24:35 PM PDT 24 Jul 17 04:52:49 PM PDT 24 336409450000 ps
T93 /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.4064965779 Jul 17 04:24:54 PM PDT 24 Jul 17 04:55:36 PM PDT 24 336472370000 ps
T94 /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.2013069409 Jul 17 04:19:10 PM PDT 24 Jul 17 04:49:57 PM PDT 24 336674450000 ps
T95 /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.2952319975 Jul 17 04:22:02 PM PDT 24 Jul 17 04:46:27 PM PDT 24 336362730000 ps
T96 /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.3620541897 Jul 17 04:22:59 PM PDT 24 Jul 17 04:52:02 PM PDT 24 336657370000 ps
T97 /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.1475366623 Jul 17 04:24:30 PM PDT 24 Jul 17 04:58:24 PM PDT 24 336427370000 ps
T98 /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.553915461 Jul 17 04:23:04 PM PDT 24 Jul 17 04:52:24 PM PDT 24 336431570000 ps
T99 /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.1325470607 Jul 17 04:24:39 PM PDT 24 Jul 17 05:11:13 PM PDT 24 336928730000 ps
T100 /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.490464498 Jul 17 04:23:31 PM PDT 24 Jul 17 04:55:26 PM PDT 24 336366410000 ps
T101 /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.2602552562 Jul 17 04:24:30 PM PDT 24 Jul 17 04:58:38 PM PDT 24 336386150000 ps
T102 /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.3173040454 Jul 17 04:24:05 PM PDT 24 Jul 17 04:52:40 PM PDT 24 336451010000 ps
T103 /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.815633866 Jul 17 04:25:08 PM PDT 24 Jul 17 04:56:41 PM PDT 24 336494350000 ps
T104 /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.1041115430 Jul 17 04:21:36 PM PDT 24 Jul 17 04:58:16 PM PDT 24 336688530000 ps
T105 /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.1705327936 Jul 17 04:24:32 PM PDT 24 Jul 17 04:48:19 PM PDT 24 336330350000 ps
T106 /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.2229545072 Jul 17 04:24:39 PM PDT 24 Jul 17 05:10:57 PM PDT 24 337049650000 ps
T107 /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.1442006659 Jul 17 04:19:35 PM PDT 24 Jul 17 04:55:32 PM PDT 24 336509410000 ps
T108 /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.1691723199 Jul 17 04:19:12 PM PDT 24 Jul 17 04:52:44 PM PDT 24 336469770000 ps
T109 /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.16622304 Jul 17 04:24:26 PM PDT 24 Jul 17 04:50:45 PM PDT 24 336886690000 ps
T110 /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.3303874141 Jul 17 04:20:14 PM PDT 24 Jul 17 04:54:29 PM PDT 24 336964710000 ps
T111 /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.2034021613 Jul 17 04:17:35 PM PDT 24 Jul 17 04:17:44 PM PDT 24 1545350000 ps
T112 /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.597704984 Jul 17 04:23:00 PM PDT 24 Jul 17 04:23:07 PM PDT 24 1283150000 ps
T113 /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.3939794751 Jul 17 04:23:17 PM PDT 24 Jul 17 04:23:24 PM PDT 24 1231270000 ps
T114 /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.1388940214 Jul 17 04:19:39 PM PDT 24 Jul 17 04:19:48 PM PDT 24 1394490000 ps
T115 /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.3860462528 Jul 17 04:17:55 PM PDT 24 Jul 17 04:18:03 PM PDT 24 1190530000 ps
T116 /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.4070557559 Jul 17 04:17:53 PM PDT 24 Jul 17 04:18:03 PM PDT 24 1587850000 ps
T117 /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.1694642922 Jul 17 04:24:53 PM PDT 24 Jul 17 04:25:02 PM PDT 24 1502790000 ps
T118 /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.2925407495 Jul 17 04:23:35 PM PDT 24 Jul 17 04:23:45 PM PDT 24 1585950000 ps
T119 /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.2578610778 Jul 17 04:23:35 PM PDT 24 Jul 17 04:23:44 PM PDT 24 1461070000 ps
T120 /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.1898539665 Jul 17 04:18:06 PM PDT 24 Jul 17 04:18:17 PM PDT 24 1484630000 ps
T121 /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.3796576741 Jul 17 04:24:49 PM PDT 24 Jul 17 04:24:58 PM PDT 24 1293690000 ps
T122 /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.4193516757 Jul 17 04:22:34 PM PDT 24 Jul 17 04:22:44 PM PDT 24 1440410000 ps
T123 /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.3702940406 Jul 17 04:23:34 PM PDT 24 Jul 17 04:23:44 PM PDT 24 1535650000 ps
T124 /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.3587952909 Jul 17 04:18:07 PM PDT 24 Jul 17 04:18:18 PM PDT 24 1558890000 ps
T125 /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.3297061231 Jul 17 04:24:15 PM PDT 24 Jul 17 04:24:25 PM PDT 24 1493130000 ps
T126 /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.2069846655 Jul 17 04:18:07 PM PDT 24 Jul 17 04:18:17 PM PDT 24 1334770000 ps
T127 /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.3069215018 Jul 17 04:20:14 PM PDT 24 Jul 17 04:20:26 PM PDT 24 1446750000 ps
T128 /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.3080390594 Jul 17 04:18:09 PM PDT 24 Jul 17 04:18:20 PM PDT 24 1561650000 ps
T129 /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.588396537 Jul 17 04:20:50 PM PDT 24 Jul 17 04:20:59 PM PDT 24 1510090000 ps
T130 /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.679637078 Jul 17 04:18:08 PM PDT 24 Jul 17 04:18:16 PM PDT 24 1178330000 ps
T131 /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.3640532802 Jul 17 04:18:13 PM PDT 24 Jul 17 04:18:24 PM PDT 24 1658830000 ps
T132 /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.2837758065 Jul 17 04:21:20 PM PDT 24 Jul 17 04:21:29 PM PDT 24 1312150000 ps
T133 /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.462167487 Jul 17 04:19:12 PM PDT 24 Jul 17 04:19:21 PM PDT 24 1445510000 ps
T134 /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.2009159341 Jul 17 04:17:57 PM PDT 24 Jul 17 04:18:06 PM PDT 24 1446310000 ps
T135 /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.3278792418 Jul 17 04:22:40 PM PDT 24 Jul 17 04:22:50 PM PDT 24 1437990000 ps
T136 /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.3836996798 Jul 17 04:22:21 PM PDT 24 Jul 17 04:22:35 PM PDT 24 1641250000 ps
T137 /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.97407983 Jul 17 04:18:01 PM PDT 24 Jul 17 04:18:11 PM PDT 24 1312230000 ps
T138 /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.161310610 Jul 17 04:17:38 PM PDT 24 Jul 17 04:17:50 PM PDT 24 1448870000 ps
T139 /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.561915500 Jul 17 04:18:42 PM PDT 24 Jul 17 04:18:52 PM PDT 24 1398190000 ps
T140 /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.231902587 Jul 17 04:21:51 PM PDT 24 Jul 17 04:22:00 PM PDT 24 1271670000 ps
T141 /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.1470245902 Jul 17 04:18:00 PM PDT 24 Jul 17 04:18:11 PM PDT 24 1382430000 ps
T142 /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.3899279132 Jul 17 04:22:42 PM PDT 24 Jul 17 04:22:52 PM PDT 24 1544290000 ps
T143 /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.920072768 Jul 17 04:17:50 PM PDT 24 Jul 17 04:17:59 PM PDT 24 1520110000 ps
T144 /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.112710970 Jul 17 04:23:41 PM PDT 24 Jul 17 04:23:50 PM PDT 24 1512990000 ps
T145 /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.4138628493 Jul 17 04:21:06 PM PDT 24 Jul 17 04:21:16 PM PDT 24 1562450000 ps
T146 /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.2824984641 Jul 17 04:21:23 PM PDT 24 Jul 17 04:21:33 PM PDT 24 1381710000 ps
T147 /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.127350954 Jul 17 04:18:04 PM PDT 24 Jul 17 04:18:14 PM PDT 24 1517750000 ps
T148 /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.380126831 Jul 17 04:18:14 PM PDT 24 Jul 17 04:18:24 PM PDT 24 1477350000 ps
T149 /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.1464910573 Jul 17 04:24:22 PM PDT 24 Jul 17 04:24:30 PM PDT 24 1427330000 ps
T150 /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2794252868 Jul 17 04:20:43 PM PDT 24 Jul 17 04:20:54 PM PDT 24 1476050000 ps
T151 /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.2414473084 Jul 17 04:18:08 PM PDT 24 Jul 17 04:18:19 PM PDT 24 1592930000 ps
T152 /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.1192782001 Jul 17 04:23:12 PM PDT 24 Jul 17 04:23:24 PM PDT 24 1564150000 ps
T153 /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.2575411015 Jul 17 04:17:31 PM PDT 24 Jul 17 04:17:43 PM PDT 24 1576710000 ps
T154 /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.3217742461 Jul 17 04:17:59 PM PDT 24 Jul 17 04:18:10 PM PDT 24 1653430000 ps
T155 /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.945850127 Jul 17 04:21:00 PM PDT 24 Jul 17 04:21:08 PM PDT 24 1301010000 ps
T156 /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.836285651 Jul 17 04:22:42 PM PDT 24 Jul 17 04:22:53 PM PDT 24 1529130000 ps
T157 /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.2620936447 Jul 17 04:21:14 PM PDT 24 Jul 17 04:21:25 PM PDT 24 1455250000 ps
T158 /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.3511558143 Jul 17 04:17:57 PM PDT 24 Jul 17 04:18:05 PM PDT 24 1321910000 ps
T159 /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.2379304937 Jul 17 04:18:00 PM PDT 24 Jul 17 04:18:10 PM PDT 24 1331770000 ps
T160 /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.1287476437 Jul 17 04:18:46 PM PDT 24 Jul 17 04:19:00 PM PDT 24 1558850000 ps
T21 /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.2078392250 Jul 17 05:34:09 PM PDT 24 Jul 17 06:05:59 PM PDT 24 336462070000 ps
T22 /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.111180546 Jul 17 05:31:25 PM PDT 24 Jul 17 06:09:00 PM PDT 24 336361790000 ps
T23 /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.2885030850 Jul 17 05:34:10 PM PDT 24 Jul 17 06:05:48 PM PDT 24 336391830000 ps
T24 /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.2455998569 Jul 17 05:31:27 PM PDT 24 Jul 17 06:04:45 PM PDT 24 336933050000 ps
T25 /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.4082069786 Jul 17 05:31:30 PM PDT 24 Jul 17 06:05:02 PM PDT 24 337151970000 ps
T26 /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.1515503614 Jul 17 05:31:25 PM PDT 24 Jul 17 06:08:47 PM PDT 24 336951330000 ps
T27 /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.1384926643 Jul 17 05:31:28 PM PDT 24 Jul 17 06:02:43 PM PDT 24 336373070000 ps
T28 /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.495706399 Jul 17 05:31:25 PM PDT 24 Jul 17 06:08:52 PM PDT 24 336409090000 ps
T29 /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.1665858075 Jul 17 05:31:30 PM PDT 24 Jul 17 05:56:53 PM PDT 24 336875710000 ps
T30 /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.3336105288 Jul 17 05:31:29 PM PDT 24 Jul 17 05:58:54 PM PDT 24 336538270000 ps
T161 /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.3261066670 Jul 17 05:31:28 PM PDT 24 Jul 17 05:58:46 PM PDT 24 336666750000 ps
T162 /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.4225172261 Jul 17 05:31:35 PM PDT 24 Jul 17 06:10:01 PM PDT 24 336807070000 ps
T163 /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.2537888321 Jul 17 05:31:35 PM PDT 24 Jul 17 06:09:33 PM PDT 24 336581210000 ps
T164 /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.382765011 Jul 17 05:31:28 PM PDT 24 Jul 17 06:04:49 PM PDT 24 336799570000 ps
T165 /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.138960416 Jul 17 05:33:40 PM PDT 24 Jul 17 06:02:08 PM PDT 24 336564230000 ps
T166 /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.604542078 Jul 17 05:31:30 PM PDT 24 Jul 17 06:01:58 PM PDT 24 336705410000 ps
T167 /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.3133867036 Jul 17 05:31:25 PM PDT 24 Jul 17 06:08:37 PM PDT 24 336924450000 ps
T168 /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.3011949005 Jul 17 05:31:25 PM PDT 24 Jul 17 05:59:59 PM PDT 24 336632990000 ps
T169 /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.3916058489 Jul 17 05:31:21 PM PDT 24 Jul 17 06:07:56 PM PDT 24 336893930000 ps
T170 /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.2813383643 Jul 17 05:31:30 PM PDT 24 Jul 17 06:01:51 PM PDT 24 336817730000 ps
T171 /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.3468723445 Jul 17 05:31:19 PM PDT 24 Jul 17 05:59:07 PM PDT 24 337101110000 ps
T172 /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.1421113577 Jul 17 05:31:24 PM PDT 24 Jul 17 06:09:56 PM PDT 24 336650430000 ps
T173 /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.3084601312 Jul 17 05:31:31 PM PDT 24 Jul 17 06:08:59 PM PDT 24 336702090000 ps
T174 /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.2146368920 Jul 17 05:31:31 PM PDT 24 Jul 17 06:04:32 PM PDT 24 336754590000 ps
T175 /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.875521283 Jul 17 05:31:31 PM PDT 24 Jul 17 06:08:25 PM PDT 24 337041170000 ps
T176 /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.2358678729 Jul 17 05:31:24 PM PDT 24 Jul 17 06:09:44 PM PDT 24 336832630000 ps
T177 /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1987430776 Jul 17 05:31:34 PM PDT 24 Jul 17 06:09:29 PM PDT 24 336558650000 ps
T178 /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.4275845616 Jul 17 05:31:23 PM PDT 24 Jul 17 06:08:02 PM PDT 24 336840510000 ps
T179 /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.2124470792 Jul 17 05:33:38 PM PDT 24 Jul 17 06:02:36 PM PDT 24 337034950000 ps
T180 /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.2698543942 Jul 17 05:31:23 PM PDT 24 Jul 17 06:09:57 PM PDT 24 336608490000 ps
T181 /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.3625039177 Jul 17 05:31:24 PM PDT 24 Jul 17 06:05:20 PM PDT 24 336943670000 ps
T182 /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.3174730922 Jul 17 05:31:36 PM PDT 24 Jul 17 06:01:04 PM PDT 24 336765070000 ps
T183 /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.3629695177 Jul 17 05:31:36 PM PDT 24 Jul 17 06:00:14 PM PDT 24 336633470000 ps
T184 /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.2622868640 Jul 17 05:31:28 PM PDT 24 Jul 17 06:00:56 PM PDT 24 336718210000 ps
T185 /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.1902543375 Jul 17 05:34:12 PM PDT 24 Jul 17 05:59:25 PM PDT 24 336873290000 ps
T186 /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.140852887 Jul 17 05:31:24 PM PDT 24 Jul 17 06:05:26 PM PDT 24 336716590000 ps
T187 /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.892473805 Jul 17 05:31:21 PM PDT 24 Jul 17 06:07:41 PM PDT 24 336565250000 ps
T188 /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.2115365789 Jul 17 05:31:33 PM PDT 24 Jul 17 06:04:53 PM PDT 24 336804250000 ps
T189 /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.3248458592 Jul 17 05:31:22 PM PDT 24 Jul 17 06:07:38 PM PDT 24 336531070000 ps
T190 /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.2959290546 Jul 17 05:31:28 PM PDT 24 Jul 17 05:59:06 PM PDT 24 336484450000 ps
T191 /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.427167803 Jul 17 05:31:28 PM PDT 24 Jul 17 05:59:26 PM PDT 24 337065330000 ps
T192 /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.3545678739 Jul 17 05:31:31 PM PDT 24 Jul 17 05:59:49 PM PDT 24 336816550000 ps
T193 /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.3632775849 Jul 17 05:31:29 PM PDT 24 Jul 17 06:04:39 PM PDT 24 336499290000 ps
T194 /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.496878231 Jul 17 05:31:29 PM PDT 24 Jul 17 06:05:09 PM PDT 24 336787110000 ps
T195 /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.177714981 Jul 17 05:31:31 PM PDT 24 Jul 17 06:00:18 PM PDT 24 336830050000 ps
T196 /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.2581589331 Jul 17 05:34:03 PM PDT 24 Jul 17 06:02:22 PM PDT 24 336609530000 ps
T197 /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.1423284530 Jul 17 05:31:18 PM PDT 24 Jul 17 05:59:52 PM PDT 24 336435150000 ps
T198 /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.4080709846 Jul 17 05:31:24 PM PDT 24 Jul 17 06:09:47 PM PDT 24 336730850000 ps
T199 /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.3419046169 Jul 17 05:31:23 PM PDT 24 Jul 17 06:09:41 PM PDT 24 336654310000 ps
T200 /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.982791167 Jul 17 05:31:21 PM PDT 24 Jul 17 06:00:08 PM PDT 24 336486550000 ps

Test location /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.2185361966
Short name T8
Test name
Test status
Simulation time 1483110000 ps
CPU time 3.86 seconds
Started Jul 17 04:18:14 PM PDT 24
Finished Jul 17 04:18:24 PM PDT 24
Peak memory 165016 kb
Host smart-395c13cc-78d4-4786-b014-21cbefc2f50e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2185361966 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.2185361966
Directory /workspace/0.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.4141635595
Short name T17
Test name
Test status
Simulation time 336716130000 ps
CPU time 736.76 seconds
Started Jul 17 04:21:52 PM PDT 24
Finished Jul 17 04:53:05 PM PDT 24
Peak memory 158736 kb
Host smart-1c6c9926-c25b-4da1-a23a-66630d5160bf
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4141635595 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.4141635595
Directory /workspace/0.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.2885030850
Short name T23
Test name
Test status
Simulation time 336391830000 ps
CPU time 765.24 seconds
Started Jul 17 05:34:10 PM PDT 24
Finished Jul 17 06:05:48 PM PDT 24
Peak memory 160816 kb
Host smart-f2831a92-12a3-4f0d-a2db-b0fde6b42c6d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2885030850 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.2885030850
Directory /workspace/0.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.1328736139
Short name T90
Test name
Test status
Simulation time 336711650000 ps
CPU time 764.61 seconds
Started Jul 17 04:20:50 PM PDT 24
Finished Jul 17 04:52:07 PM PDT 24
Peak memory 160844 kb
Host smart-d829ede2-8304-4825-ac97-97158fe50f6b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1328736139 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.1328736139
Directory /workspace/1.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.1475366623
Short name T97
Test name
Test status
Simulation time 336427370000 ps
CPU time 811.3 seconds
Started Jul 17 04:24:30 PM PDT 24
Finished Jul 17 04:58:24 PM PDT 24
Peak memory 160540 kb
Host smart-48b958e5-be1e-4239-849c-548e13e67a11
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1475366623 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.1475366623
Directory /workspace/10.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.4064965779
Short name T93
Test name
Test status
Simulation time 336472370000 ps
CPU time 748.07 seconds
Started Jul 17 04:24:54 PM PDT 24
Finished Jul 17 04:55:36 PM PDT 24
Peak memory 159768 kb
Host smart-e12bac57-8dca-473c-ab1e-df2c004e6164
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4064965779 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.4064965779
Directory /workspace/11.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.1661892240
Short name T82
Test name
Test status
Simulation time 336682810000 ps
CPU time 696.53 seconds
Started Jul 17 04:22:27 PM PDT 24
Finished Jul 17 04:52:01 PM PDT 24
Peak memory 159244 kb
Host smart-d6061114-5d63-4462-91a2-f64443d9cab7
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1661892240 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.1661892240
Directory /workspace/12.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.618429519
Short name T86
Test name
Test status
Simulation time 336614450000 ps
CPU time 756.67 seconds
Started Jul 17 04:24:15 PM PDT 24
Finished Jul 17 04:56:53 PM PDT 24
Peak memory 158748 kb
Host smart-fd2ac2fe-3436-4ede-aa36-70119564ff8a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=618429519 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.618429519
Directory /workspace/13.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.4088627673
Short name T5
Test name
Test status
Simulation time 337071510000 ps
CPU time 774.14 seconds
Started Jul 17 04:24:16 PM PDT 24
Finished Jul 17 04:57:23 PM PDT 24
Peak memory 160152 kb
Host smart-1bb03208-b143-4e2d-bfeb-21066a5f3ae0
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4088627673 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.4088627673
Directory /workspace/14.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.2602552562
Short name T101
Test name
Test status
Simulation time 336386150000 ps
CPU time 821.12 seconds
Started Jul 17 04:24:30 PM PDT 24
Finished Jul 17 04:58:38 PM PDT 24
Peak memory 160460 kb
Host smart-3e877421-78ab-421e-be2b-f7396a573ec0
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2602552562 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.2602552562
Directory /workspace/15.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.490464498
Short name T100
Test name
Test status
Simulation time 336366410000 ps
CPU time 793.35 seconds
Started Jul 17 04:23:31 PM PDT 24
Finished Jul 17 04:55:26 PM PDT 24
Peak memory 160472 kb
Host smart-1c9325a9-ce7e-49cf-9e4f-f38ef0f3f8d8
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=490464498 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.490464498
Directory /workspace/16.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.2957009300
Short name T85
Test name
Test status
Simulation time 336915670000 ps
CPU time 663.67 seconds
Started Jul 17 04:23:18 PM PDT 24
Finished Jul 17 04:50:46 PM PDT 24
Peak memory 160572 kb
Host smart-78ff4e6e-c328-4966-aa8d-05e8e511c3e6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2957009300 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.2957009300
Directory /workspace/17.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.34785333
Short name T6
Test name
Test status
Simulation time 336405270000 ps
CPU time 837.05 seconds
Started Jul 17 04:24:18 PM PDT 24
Finished Jul 17 04:58:05 PM PDT 24
Peak memory 160248 kb
Host smart-393ebf4b-2857-489a-ad6e-501f13930ce6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=34785333 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.34785333
Directory /workspace/18.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.365671444
Short name T84
Test name
Test status
Simulation time 337007250000 ps
CPU time 753.46 seconds
Started Jul 17 04:23:18 PM PDT 24
Finished Jul 17 04:53:59 PM PDT 24
Peak memory 160724 kb
Host smart-9875de56-2930-4eae-b728-b3a161fff728
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=365671444 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.365671444
Directory /workspace/19.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.3724719230
Short name T19
Test name
Test status
Simulation time 336501430000 ps
CPU time 753.36 seconds
Started Jul 17 04:22:01 PM PDT 24
Finished Jul 17 04:53:15 PM PDT 24
Peak memory 160240 kb
Host smart-e39182ed-ccf2-4967-b3e4-8635b48752fa
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3724719230 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.3724719230
Directory /workspace/2.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.2013069409
Short name T94
Test name
Test status
Simulation time 336674450000 ps
CPU time 758.02 seconds
Started Jul 17 04:19:10 PM PDT 24
Finished Jul 17 04:49:57 PM PDT 24
Peak memory 160848 kb
Host smart-cb2b81e7-605a-418e-8b8b-30305822d1ab
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2013069409 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.2013069409
Directory /workspace/20.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.2245584028
Short name T78
Test name
Test status
Simulation time 336985190000 ps
CPU time 889.53 seconds
Started Jul 17 04:21:36 PM PDT 24
Finished Jul 17 04:58:16 PM PDT 24
Peak memory 160696 kb
Host smart-e325b025-8b56-40f5-8a2e-ea8ebf8dcd4f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2245584028 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.2245584028
Directory /workspace/21.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.3795521815
Short name T83
Test name
Test status
Simulation time 336328250000 ps
CPU time 660.39 seconds
Started Jul 17 04:20:13 PM PDT 24
Finished Jul 17 04:47:31 PM PDT 24
Peak memory 159348 kb
Host smart-d44a2a80-158c-4def-8ba6-1ac1d92c73ac
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3795521815 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.3795521815
Directory /workspace/22.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.3620541897
Short name T96
Test name
Test status
Simulation time 336657370000 ps
CPU time 703.39 seconds
Started Jul 17 04:22:59 PM PDT 24
Finished Jul 17 04:52:02 PM PDT 24
Peak memory 160552 kb
Host smart-1b70333b-8918-4577-9b03-4fd0ae2aaff7
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3620541897 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.3620541897
Directory /workspace/23.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.3423134475
Short name T76
Test name
Test status
Simulation time 337057350000 ps
CPU time 694.64 seconds
Started Jul 17 04:23:14 PM PDT 24
Finished Jul 17 04:52:15 PM PDT 24
Peak memory 160840 kb
Host smart-95bb5e20-6d46-4828-8912-f3d349594c4b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3423134475 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.3423134475
Directory /workspace/24.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.1691723199
Short name T108
Test name
Test status
Simulation time 336469770000 ps
CPU time 820.14 seconds
Started Jul 17 04:19:12 PM PDT 24
Finished Jul 17 04:52:44 PM PDT 24
Peak memory 160864 kb
Host smart-84901a4e-aced-46ce-b9f5-2c45f8ac690a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1691723199 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.1691723199
Directory /workspace/25.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.553915461
Short name T98
Test name
Test status
Simulation time 336431570000 ps
CPU time 707.56 seconds
Started Jul 17 04:23:04 PM PDT 24
Finished Jul 17 04:52:24 PM PDT 24
Peak memory 160832 kb
Host smart-08a0e5ca-4726-4ad0-a69a-9f6a13862489
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=553915461 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.553915461
Directory /workspace/26.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.2952319975
Short name T95
Test name
Test status
Simulation time 336362730000 ps
CPU time 592.6 seconds
Started Jul 17 04:22:02 PM PDT 24
Finished Jul 17 04:46:27 PM PDT 24
Peak memory 159604 kb
Host smart-6d864641-92ac-4cc9-8727-3e52eca11c7c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2952319975 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.2952319975
Directory /workspace/27.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.3173040454
Short name T102
Test name
Test status
Simulation time 336451010000 ps
CPU time 692.35 seconds
Started Jul 17 04:24:05 PM PDT 24
Finished Jul 17 04:52:40 PM PDT 24
Peak memory 159768 kb
Host smart-75d805a0-3696-403c-accb-e83a24753ec3
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3173040454 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.3173040454
Directory /workspace/28.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.3070381477
Short name T72
Test name
Test status
Simulation time 336828930000 ps
CPU time 656.81 seconds
Started Jul 17 04:20:13 PM PDT 24
Finished Jul 17 04:47:27 PM PDT 24
Peak memory 159292 kb
Host smart-e151eca7-ffca-4ae4-b512-af7bf37ab8ef
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3070381477 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.3070381477
Directory /workspace/29.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.3328607958
Short name T16
Test name
Test status
Simulation time 337012150000 ps
CPU time 737.37 seconds
Started Jul 17 04:21:52 PM PDT 24
Finished Jul 17 04:53:04 PM PDT 24
Peak memory 158584 kb
Host smart-a1d763f3-d6ca-4d72-9598-5d4a49eea1f1
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3328607958 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.3328607958
Directory /workspace/3.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3683456610
Short name T92
Test name
Test status
Simulation time 336409450000 ps
CPU time 683.98 seconds
Started Jul 17 04:24:35 PM PDT 24
Finished Jul 17 04:52:49 PM PDT 24
Peak memory 159084 kb
Host smart-d4cb0836-1a83-4523-95d6-b37b404f95dc
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3683456610 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.3683456610
Directory /workspace/30.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.2673767729
Short name T80
Test name
Test status
Simulation time 336796010000 ps
CPU time 590.55 seconds
Started Jul 17 04:22:12 PM PDT 24
Finished Jul 17 04:46:46 PM PDT 24
Peak memory 160512 kb
Host smart-75ebaf82-143b-4bb3-b6b7-0f6e59e122d1
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2673767729 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.2673767729
Directory /workspace/31.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.380641174
Short name T14
Test name
Test status
Simulation time 336909850000 ps
CPU time 685.92 seconds
Started Jul 17 04:24:35 PM PDT 24
Finished Jul 17 04:52:59 PM PDT 24
Peak memory 159780 kb
Host smart-f3b9df2e-9f52-4ad4-971f-bc0f3062fdb5
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=380641174 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.380641174
Directory /workspace/32.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.1529881917
Short name T77
Test name
Test status
Simulation time 336651970000 ps
CPU time 744.03 seconds
Started Jul 17 04:22:02 PM PDT 24
Finished Jul 17 04:52:59 PM PDT 24
Peak memory 159768 kb
Host smart-bd6846a7-570a-4077-bb7c-44dcce0f3e0c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1529881917 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.1529881917
Directory /workspace/33.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.3847080689
Short name T91
Test name
Test status
Simulation time 336520670000 ps
CPU time 824.65 seconds
Started Jul 17 04:22:56 PM PDT 24
Finished Jul 17 04:56:16 PM PDT 24
Peak memory 160568 kb
Host smart-bcef01e4-b11c-4b86-9e17-8e1f00a5adb4
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3847080689 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.3847080689
Directory /workspace/34.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.1041115430
Short name T104
Test name
Test status
Simulation time 336688530000 ps
CPU time 886.26 seconds
Started Jul 17 04:21:36 PM PDT 24
Finished Jul 17 04:58:16 PM PDT 24
Peak memory 160696 kb
Host smart-6c4b2ac7-4914-41f6-8e9b-044a044be580
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1041115430 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.1041115430
Directory /workspace/35.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.1442006659
Short name T107
Test name
Test status
Simulation time 336509410000 ps
CPU time 861.21 seconds
Started Jul 17 04:19:35 PM PDT 24
Finished Jul 17 04:55:32 PM PDT 24
Peak memory 160604 kb
Host smart-3ac761b9-daed-41c7-a134-219b36c33aab
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1442006659 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.1442006659
Directory /workspace/36.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.1705327936
Short name T105
Test name
Test status
Simulation time 336330350000 ps
CPU time 574.79 seconds
Started Jul 17 04:24:32 PM PDT 24
Finished Jul 17 04:48:19 PM PDT 24
Peak memory 159496 kb
Host smart-1252e75a-b6b1-476c-889a-5c79694c36d8
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1705327936 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.1705327936
Directory /workspace/37.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.3206154084
Short name T18
Test name
Test status
Simulation time 336756890000 ps
CPU time 702.11 seconds
Started Jul 17 04:22:13 PM PDT 24
Finished Jul 17 04:52:16 PM PDT 24
Peak memory 160264 kb
Host smart-d1c8aef9-0905-4b71-9a79-5557e0e3773e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3206154084 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.3206154084
Directory /workspace/38.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.3408312637
Short name T7
Test name
Test status
Simulation time 336445950000 ps
CPU time 711.33 seconds
Started Jul 17 04:22:15 PM PDT 24
Finished Jul 17 04:52:36 PM PDT 24
Peak memory 160264 kb
Host smart-84fff124-6825-4008-bf5f-7b3774bf7ff4
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3408312637 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.3408312637
Directory /workspace/39.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.3303874141
Short name T110
Test name
Test status
Simulation time 336964710000 ps
CPU time 842.22 seconds
Started Jul 17 04:20:14 PM PDT 24
Finished Jul 17 04:54:29 PM PDT 24
Peak memory 160308 kb
Host smart-0374094c-8bc7-46df-a09f-16879bf1b8b4
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3303874141 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.3303874141
Directory /workspace/4.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.2229545072
Short name T106
Test name
Test status
Simulation time 337049650000 ps
CPU time 1083.05 seconds
Started Jul 17 04:24:39 PM PDT 24
Finished Jul 17 05:10:57 PM PDT 24
Peak memory 158000 kb
Host smart-66f54f63-0070-439b-b432-8c9e08351548
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2229545072 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.2229545072
Directory /workspace/40.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.2753111412
Short name T15
Test name
Test status
Simulation time 336412810000 ps
CPU time 668.58 seconds
Started Jul 17 04:24:51 PM PDT 24
Finished Jul 17 04:52:27 PM PDT 24
Peak memory 159712 kb
Host smart-60ae14dd-bc67-49bf-8125-f8580bd458ed
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2753111412 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.2753111412
Directory /workspace/41.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.3140040513
Short name T89
Test name
Test status
Simulation time 336366190000 ps
CPU time 554.12 seconds
Started Jul 17 04:24:27 PM PDT 24
Finished Jul 17 04:47:41 PM PDT 24
Peak memory 159728 kb
Host smart-9d9c367a-a09e-4c6a-a555-e180e29dd6f3
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3140040513 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.3140040513
Directory /workspace/42.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.1186188438
Short name T74
Test name
Test status
Simulation time 336419510000 ps
CPU time 1067.95 seconds
Started Jul 17 04:24:39 PM PDT 24
Finished Jul 17 05:10:42 PM PDT 24
Peak memory 159552 kb
Host smart-e4b4a3b8-264a-4350-ab9d-e455dfde1bb4
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1186188438 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.1186188438
Directory /workspace/43.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.2809445546
Short name T81
Test name
Test status
Simulation time 336697270000 ps
CPU time 645.61 seconds
Started Jul 17 04:24:35 PM PDT 24
Finished Jul 17 04:51:17 PM PDT 24
Peak memory 160244 kb
Host smart-504661d3-614b-4e5d-b0b5-ecb858222634
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2809445546 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.2809445546
Directory /workspace/44.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.1261664131
Short name T87
Test name
Test status
Simulation time 336354390000 ps
CPU time 742.76 seconds
Started Jul 17 04:25:07 PM PDT 24
Finished Jul 17 04:55:22 PM PDT 24
Peak memory 160244 kb
Host smart-6778ab57-8db3-4ccc-896f-5df581d4348b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1261664131 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.1261664131
Directory /workspace/45.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.16622304
Short name T109
Test name
Test status
Simulation time 336886690000 ps
CPU time 642.55 seconds
Started Jul 17 04:24:26 PM PDT 24
Finished Jul 17 04:50:45 PM PDT 24
Peak memory 159748 kb
Host smart-034b199c-637c-4c4d-9513-ce696f21a9c9
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=16622304 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.16622304
Directory /workspace/46.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.1325470607
Short name T99
Test name
Test status
Simulation time 336928730000 ps
CPU time 1085.3 seconds
Started Jul 17 04:24:39 PM PDT 24
Finished Jul 17 05:11:13 PM PDT 24
Peak memory 158560 kb
Host smart-70fabba3-5034-4d6a-91f4-b9dae770026e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1325470607 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.1325470607
Directory /workspace/47.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.815633866
Short name T103
Test name
Test status
Simulation time 336494350000 ps
CPU time 781.12 seconds
Started Jul 17 04:25:08 PM PDT 24
Finished Jul 17 04:56:41 PM PDT 24
Peak memory 160244 kb
Host smart-8879825c-4a7a-4811-8d45-94a7f6bc1a70
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=815633866 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.815633866
Directory /workspace/48.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.293158423
Short name T73
Test name
Test status
Simulation time 337107750000 ps
CPU time 1084.28 seconds
Started Jul 17 04:24:39 PM PDT 24
Finished Jul 17 05:11:07 PM PDT 24
Peak memory 158128 kb
Host smart-f0dd530e-56b3-4139-ab2c-80e8a7765a8d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=293158423 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.293158423
Directory /workspace/49.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.625529282
Short name T88
Test name
Test status
Simulation time 337085970000 ps
CPU time 847.85 seconds
Started Jul 17 04:23:21 PM PDT 24
Finished Jul 17 04:58:00 PM PDT 24
Peak memory 160848 kb
Host smart-d8267c65-b69d-4511-8910-5e76711880d5
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=625529282 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.625529282
Directory /workspace/5.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.3580456782
Short name T71
Test name
Test status
Simulation time 336821590000 ps
CPU time 732.32 seconds
Started Jul 17 04:21:52 PM PDT 24
Finished Jul 17 04:52:47 PM PDT 24
Peak memory 158728 kb
Host smart-27af51fb-a645-4bb3-834c-6968c3b5f42f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3580456782 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.3580456782
Directory /workspace/6.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.3647615764
Short name T75
Test name
Test status
Simulation time 336350970000 ps
CPU time 842.24 seconds
Started Jul 17 04:20:07 PM PDT 24
Finished Jul 17 04:54:43 PM PDT 24
Peak memory 160864 kb
Host smart-a9b09a73-5d61-4230-9b31-78ffbeacbe9b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3647615764 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.3647615764
Directory /workspace/7.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.3842667186
Short name T20
Test name
Test status
Simulation time 336412030000 ps
CPU time 767.67 seconds
Started Jul 17 04:24:15 PM PDT 24
Finished Jul 17 04:57:04 PM PDT 24
Peak memory 158752 kb
Host smart-e0d7ed7e-3339-42bc-a84a-40dc69d29fd3
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3842667186 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.3842667186
Directory /workspace/8.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.690689118
Short name T79
Test name
Test status
Simulation time 336395110000 ps
CPU time 701.76 seconds
Started Jul 17 04:22:27 PM PDT 24
Finished Jul 17 04:51:55 PM PDT 24
Peak memory 159188 kb
Host smart-dd1e11ae-a438-4ace-b121-e1bee255838b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=690689118 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.690689118
Directory /workspace/9.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.2078392250
Short name T21
Test name
Test status
Simulation time 336462070000 ps
CPU time 767.73 seconds
Started Jul 17 05:34:09 PM PDT 24
Finished Jul 17 06:05:59 PM PDT 24
Peak memory 160816 kb
Host smart-c824e585-b7d4-4225-a003-f4fe9a9158ed
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2078392250 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.2078392250
Directory /workspace/1.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.1421113577
Short name T172
Test name
Test status
Simulation time 336650430000 ps
CPU time 941.09 seconds
Started Jul 17 05:31:24 PM PDT 24
Finished Jul 17 06:09:56 PM PDT 24
Peak memory 160840 kb
Host smart-6030bfc7-5861-4c8b-910c-2180440687d0
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1421113577 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.1421113577
Directory /workspace/10.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.4275845616
Short name T178
Test name
Test status
Simulation time 336840510000 ps
CPU time 873.08 seconds
Started Jul 17 05:31:23 PM PDT 24
Finished Jul 17 06:08:02 PM PDT 24
Peak memory 160812 kb
Host smart-e668375c-3bdb-43b6-85c2-92514dc45891
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4275845616 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.4275845616
Directory /workspace/11.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.1423284530
Short name T197
Test name
Test status
Simulation time 336435150000 ps
CPU time 693.14 seconds
Started Jul 17 05:31:18 PM PDT 24
Finished Jul 17 05:59:52 PM PDT 24
Peak memory 160764 kb
Host smart-4752012c-b3fc-4899-84db-92e01adce0b5
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1423284530 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.1423284530
Directory /workspace/12.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.3468723445
Short name T171
Test name
Test status
Simulation time 337101110000 ps
CPU time 680.72 seconds
Started Jul 17 05:31:19 PM PDT 24
Finished Jul 17 05:59:07 PM PDT 24
Peak memory 160820 kb
Host smart-d028da55-87a8-434f-8b01-7f7f9aae0aea
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3468723445 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.3468723445
Directory /workspace/13.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.495706399
Short name T28
Test name
Test status
Simulation time 336409090000 ps
CPU time 911.91 seconds
Started Jul 17 05:31:25 PM PDT 24
Finished Jul 17 06:08:52 PM PDT 24
Peak memory 160864 kb
Host smart-edb2902f-3026-4fbf-a16b-8efcfdef82a3
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=495706399 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.495706399
Directory /workspace/14.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.140852887
Short name T186
Test name
Test status
Simulation time 336716590000 ps
CPU time 809.82 seconds
Started Jul 17 05:31:24 PM PDT 24
Finished Jul 17 06:05:26 PM PDT 24
Peak memory 160852 kb
Host smart-a443180e-5998-4e12-8a3d-69a8d63d9755
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=140852887 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.140852887
Directory /workspace/15.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.3625039177
Short name T181
Test name
Test status
Simulation time 336943670000 ps
CPU time 812.68 seconds
Started Jul 17 05:31:24 PM PDT 24
Finished Jul 17 06:05:20 PM PDT 24
Peak memory 160856 kb
Host smart-df92b613-2052-4a6f-ae28-9349bf12771a
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3625039177 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.3625039177
Directory /workspace/16.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.4082069786
Short name T25
Test name
Test status
Simulation time 337151970000 ps
CPU time 819.45 seconds
Started Jul 17 05:31:30 PM PDT 24
Finished Jul 17 06:05:02 PM PDT 24
Peak memory 160856 kb
Host smart-21b480a5-af93-4db3-9a6b-a776384467fa
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4082069786 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.4082069786
Directory /workspace/17.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.4080709846
Short name T198
Test name
Test status
Simulation time 336730850000 ps
CPU time 897.05 seconds
Started Jul 17 05:31:24 PM PDT 24
Finished Jul 17 06:09:47 PM PDT 24
Peak memory 160840 kb
Host smart-fe83f25c-bfd4-4cea-8499-96483877c1a7
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4080709846 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.4080709846
Directory /workspace/18.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.2698543942
Short name T180
Test name
Test status
Simulation time 336608490000 ps
CPU time 907.75 seconds
Started Jul 17 05:31:23 PM PDT 24
Finished Jul 17 06:09:57 PM PDT 24
Peak memory 160840 kb
Host smart-a5d692f2-3429-4990-934e-5a43a403c1ac
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2698543942 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.2698543942
Directory /workspace/19.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.3133867036
Short name T167
Test name
Test status
Simulation time 336924450000 ps
CPU time 875.18 seconds
Started Jul 17 05:31:25 PM PDT 24
Finished Jul 17 06:08:37 PM PDT 24
Peak memory 160864 kb
Host smart-7ffa2ac5-3240-4e78-b1d8-4fac429a43d1
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3133867036 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.3133867036
Directory /workspace/2.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.496878231
Short name T194
Test name
Test status
Simulation time 336787110000 ps
CPU time 806.58 seconds
Started Jul 17 05:31:29 PM PDT 24
Finished Jul 17 06:05:09 PM PDT 24
Peak memory 160852 kb
Host smart-e4f78332-2550-4101-abf6-573d6e2b4990
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=496878231 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.496878231
Directory /workspace/20.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.1515503614
Short name T26
Test name
Test status
Simulation time 336951330000 ps
CPU time 884.6 seconds
Started Jul 17 05:31:25 PM PDT 24
Finished Jul 17 06:08:47 PM PDT 24
Peak memory 160872 kb
Host smart-75a6d92c-b9eb-48eb-8b8d-4cf6adfd3cde
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1515503614 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.1515503614
Directory /workspace/21.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.3011949005
Short name T168
Test name
Test status
Simulation time 336632990000 ps
CPU time 689.4 seconds
Started Jul 17 05:31:25 PM PDT 24
Finished Jul 17 05:59:59 PM PDT 24
Peak memory 160804 kb
Host smart-5b43cf7e-bd48-4557-9852-762db14f53d1
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3011949005 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.3011949005
Directory /workspace/22.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.2455998569
Short name T24
Test name
Test status
Simulation time 336933050000 ps
CPU time 815.02 seconds
Started Jul 17 05:31:27 PM PDT 24
Finished Jul 17 06:04:45 PM PDT 24
Peak memory 160856 kb
Host smart-b3830323-94ee-423e-b0f5-2d4f92b20b50
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2455998569 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.2455998569
Directory /workspace/23.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.3632775849
Short name T193
Test name
Test status
Simulation time 336499290000 ps
CPU time 806.77 seconds
Started Jul 17 05:31:29 PM PDT 24
Finished Jul 17 06:04:39 PM PDT 24
Peak memory 160792 kb
Host smart-ffbc5504-12e0-4208-8b6f-1a6a5562f9bf
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3632775849 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.3632775849
Directory /workspace/24.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.3261066670
Short name T161
Test name
Test status
Simulation time 336666750000 ps
CPU time 662.07 seconds
Started Jul 17 05:31:28 PM PDT 24
Finished Jul 17 05:58:46 PM PDT 24
Peak memory 160768 kb
Host smart-46840130-e076-4ee5-9129-5b20435d339e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3261066670 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.3261066670
Directory /workspace/25.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.427167803
Short name T191
Test name
Test status
Simulation time 337065330000 ps
CPU time 677.83 seconds
Started Jul 17 05:31:28 PM PDT 24
Finished Jul 17 05:59:26 PM PDT 24
Peak memory 160748 kb
Host smart-2ea16c2f-6794-4a64-97f9-86f39983a376
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=427167803 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.427167803
Directory /workspace/26.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.2959290546
Short name T190
Test name
Test status
Simulation time 336484450000 ps
CPU time 682.47 seconds
Started Jul 17 05:31:28 PM PDT 24
Finished Jul 17 05:59:06 PM PDT 24
Peak memory 160776 kb
Host smart-215c773d-92c7-4abc-8190-de71e8ea7506
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2959290546 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.2959290546
Directory /workspace/27.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.4225172261
Short name T162
Test name
Test status
Simulation time 336807070000 ps
CPU time 924.07 seconds
Started Jul 17 05:31:35 PM PDT 24
Finished Jul 17 06:10:01 PM PDT 24
Peak memory 160840 kb
Host smart-7c9d466f-929b-4386-baef-15b141a36186
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4225172261 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.4225172261
Directory /workspace/28.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.3084601312
Short name T173
Test name
Test status
Simulation time 336702090000 ps
CPU time 898.19 seconds
Started Jul 17 05:31:31 PM PDT 24
Finished Jul 17 06:08:59 PM PDT 24
Peak memory 160872 kb
Host smart-89c777ac-7a37-46ce-b7d4-7bd6ccb68413
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3084601312 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.3084601312
Directory /workspace/29.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.3248458592
Short name T189
Test name
Test status
Simulation time 336531070000 ps
CPU time 852.58 seconds
Started Jul 17 05:31:22 PM PDT 24
Finished Jul 17 06:07:38 PM PDT 24
Peak memory 160804 kb
Host smart-4e2a4a27-fe00-4469-9fd7-7be347271b21
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3248458592 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.3248458592
Directory /workspace/3.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.1665858075
Short name T29
Test name
Test status
Simulation time 336875710000 ps
CPU time 594.33 seconds
Started Jul 17 05:31:30 PM PDT 24
Finished Jul 17 05:56:53 PM PDT 24
Peak memory 160804 kb
Host smart-478bb966-f123-43cf-9b11-fbac90b733da
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1665858075 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.1665858075
Directory /workspace/30.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.2581589331
Short name T196
Test name
Test status
Simulation time 336609530000 ps
CPU time 684.83 seconds
Started Jul 17 05:34:03 PM PDT 24
Finished Jul 17 06:02:22 PM PDT 24
Peak memory 160824 kb
Host smart-bbfd4477-49e5-4b16-b125-b033cec7caad
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2581589331 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.2581589331
Directory /workspace/31.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.138960416
Short name T165
Test name
Test status
Simulation time 336564230000 ps
CPU time 693.9 seconds
Started Jul 17 05:33:40 PM PDT 24
Finished Jul 17 06:02:08 PM PDT 24
Peak memory 160832 kb
Host smart-b3378100-a8e8-4144-83cd-fee6c0864719
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=138960416 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.138960416
Directory /workspace/32.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.3336105288
Short name T30
Test name
Test status
Simulation time 336538270000 ps
CPU time 664.76 seconds
Started Jul 17 05:31:29 PM PDT 24
Finished Jul 17 05:58:54 PM PDT 24
Peak memory 160788 kb
Host smart-a30bbf37-2042-4210-bcbd-4d061bec3c11
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3336105288 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.3336105288
Directory /workspace/33.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.3629695177
Short name T183
Test name
Test status
Simulation time 336633470000 ps
CPU time 688.15 seconds
Started Jul 17 05:31:36 PM PDT 24
Finished Jul 17 06:00:14 PM PDT 24
Peak memory 160800 kb
Host smart-e34e6600-b6e8-4541-9159-1cf1b097f523
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3629695177 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.3629695177
Directory /workspace/34.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.604542078
Short name T166
Test name
Test status
Simulation time 336705410000 ps
CPU time 738.14 seconds
Started Jul 17 05:31:30 PM PDT 24
Finished Jul 17 06:01:58 PM PDT 24
Peak memory 160812 kb
Host smart-7f672e09-c6ed-4d01-b5b2-432e4d032dc3
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=604542078 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.604542078
Directory /workspace/35.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.382765011
Short name T164
Test name
Test status
Simulation time 336799570000 ps
CPU time 822.37 seconds
Started Jul 17 05:31:28 PM PDT 24
Finished Jul 17 06:04:49 PM PDT 24
Peak memory 160756 kb
Host smart-ef0722e5-7bd3-4e02-9d52-2fcc6e1858dc
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=382765011 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.382765011
Directory /workspace/36.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.2146368920
Short name T174
Test name
Test status
Simulation time 336754590000 ps
CPU time 798.43 seconds
Started Jul 17 05:31:31 PM PDT 24
Finished Jul 17 06:04:32 PM PDT 24
Peak memory 160784 kb
Host smart-fb22a524-6f7e-4ee8-b969-6ec6d85d3f3f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2146368920 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.2146368920
Directory /workspace/37.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.875521283
Short name T175
Test name
Test status
Simulation time 337041170000 ps
CPU time 875.76 seconds
Started Jul 17 05:31:31 PM PDT 24
Finished Jul 17 06:08:25 PM PDT 24
Peak memory 160804 kb
Host smart-1babe07b-5c6c-4d13-a947-fdf25fe2c77f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=875521283 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.875521283
Directory /workspace/38.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.3545678739
Short name T192
Test name
Test status
Simulation time 336816550000 ps
CPU time 681.49 seconds
Started Jul 17 05:31:31 PM PDT 24
Finished Jul 17 05:59:49 PM PDT 24
Peak memory 160816 kb
Host smart-22b49af0-ae31-4b42-ae23-1355b6e903b3
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3545678739 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.3545678739
Directory /workspace/39.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.3419046169
Short name T199
Test name
Test status
Simulation time 336654310000 ps
CPU time 923.19 seconds
Started Jul 17 05:31:23 PM PDT 24
Finished Jul 17 06:09:41 PM PDT 24
Peak memory 160832 kb
Host smart-30e0ef6b-781e-4dc6-9efb-739bf0a3f1f5
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3419046169 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.3419046169
Directory /workspace/4.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.2813383643
Short name T170
Test name
Test status
Simulation time 336817730000 ps
CPU time 741.68 seconds
Started Jul 17 05:31:30 PM PDT 24
Finished Jul 17 06:01:51 PM PDT 24
Peak memory 160788 kb
Host smart-6b6a4122-8f4f-4f90-8cb0-37c073fe0388
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2813383643 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.2813383643
Directory /workspace/40.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.2115365789
Short name T188
Test name
Test status
Simulation time 336804250000 ps
CPU time 816.3 seconds
Started Jul 17 05:31:33 PM PDT 24
Finished Jul 17 06:04:53 PM PDT 24
Peak memory 160856 kb
Host smart-21e9cea4-83c0-458d-bd89-af95886bc872
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2115365789 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.2115365789
Directory /workspace/41.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.2537888321
Short name T163
Test name
Test status
Simulation time 336581210000 ps
CPU time 885.42 seconds
Started Jul 17 05:31:35 PM PDT 24
Finished Jul 17 06:09:33 PM PDT 24
Peak memory 160840 kb
Host smart-8fd7f718-e5be-4618-800e-e1fb972207a0
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2537888321 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.2537888321
Directory /workspace/42.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.3174730922
Short name T182
Test name
Test status
Simulation time 336765070000 ps
CPU time 709.06 seconds
Started Jul 17 05:31:36 PM PDT 24
Finished Jul 17 06:01:04 PM PDT 24
Peak memory 160800 kb
Host smart-9ca9148e-7657-4b72-87d9-6928d403a932
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3174730922 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.3174730922
Directory /workspace/43.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.177714981
Short name T195
Test name
Test status
Simulation time 336830050000 ps
CPU time 699.07 seconds
Started Jul 17 05:31:31 PM PDT 24
Finished Jul 17 06:00:18 PM PDT 24
Peak memory 160800 kb
Host smart-4bf5461b-ee38-4853-be3b-732dcdb273f3
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=177714981 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.177714981
Directory /workspace/44.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.1384926643
Short name T27
Test name
Test status
Simulation time 336373070000 ps
CPU time 750.47 seconds
Started Jul 17 05:31:28 PM PDT 24
Finished Jul 17 06:02:43 PM PDT 24
Peak memory 160788 kb
Host smart-d6ac7805-5ca6-448d-a8be-b4e772fa1c0c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1384926643 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.1384926643
Directory /workspace/45.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.2622868640
Short name T184
Test name
Test status
Simulation time 336718210000 ps
CPU time 712.16 seconds
Started Jul 17 05:31:28 PM PDT 24
Finished Jul 17 06:00:56 PM PDT 24
Peak memory 160832 kb
Host smart-6af4d559-7253-44b9-892d-798822db2078
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2622868640 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.2622868640
Directory /workspace/46.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.2124470792
Short name T179
Test name
Test status
Simulation time 337034950000 ps
CPU time 697.4 seconds
Started Jul 17 05:33:38 PM PDT 24
Finished Jul 17 06:02:36 PM PDT 24
Peak memory 160840 kb
Host smart-d03d53d6-d48c-44e8-b661-2772925a5b6b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2124470792 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.2124470792
Directory /workspace/47.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1987430776
Short name T177
Test name
Test status
Simulation time 336558650000 ps
CPU time 886.03 seconds
Started Jul 17 05:31:34 PM PDT 24
Finished Jul 17 06:09:29 PM PDT 24
Peak memory 160840 kb
Host smart-366b2aae-d42d-4425-8613-b4ce250e5623
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1987430776 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.1987430776
Directory /workspace/48.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.1902543375
Short name T185
Test name
Test status
Simulation time 336873290000 ps
CPU time 601.72 seconds
Started Jul 17 05:34:12 PM PDT 24
Finished Jul 17 05:59:25 PM PDT 24
Peak memory 160796 kb
Host smart-7d300700-6b4d-4046-a658-32f406282b49
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1902543375 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.1902543375
Directory /workspace/49.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.982791167
Short name T200
Test name
Test status
Simulation time 336486550000 ps
CPU time 702.71 seconds
Started Jul 17 05:31:21 PM PDT 24
Finished Jul 17 06:00:08 PM PDT 24
Peak memory 160728 kb
Host smart-83a22aac-675a-4d9e-9296-3d9f11cb3567
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=982791167 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.982791167
Directory /workspace/5.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.111180546
Short name T22
Test name
Test status
Simulation time 336361790000 ps
CPU time 906.16 seconds
Started Jul 17 05:31:25 PM PDT 24
Finished Jul 17 06:09:00 PM PDT 24
Peak memory 160844 kb
Host smart-8a27e0b0-3fe9-45f7-b0fa-876378f91166
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=111180546 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.111180546
Directory /workspace/6.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.2358678729
Short name T176
Test name
Test status
Simulation time 336832630000 ps
CPU time 912.37 seconds
Started Jul 17 05:31:24 PM PDT 24
Finished Jul 17 06:09:44 PM PDT 24
Peak memory 160832 kb
Host smart-d0478c43-4eaf-4f0e-831f-525cfe3c27b9
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2358678729 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.2358678729
Directory /workspace/7.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.892473805
Short name T187
Test name
Test status
Simulation time 336565250000 ps
CPU time 851.64 seconds
Started Jul 17 05:31:21 PM PDT 24
Finished Jul 17 06:07:41 PM PDT 24
Peak memory 160800 kb
Host smart-e9647cd4-05c7-4a90-b2e6-4d71e287bdb0
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=892473805 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.892473805
Directory /workspace/8.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.3916058489
Short name T169
Test name
Test status
Simulation time 336893930000 ps
CPU time 870.71 seconds
Started Jul 17 05:31:21 PM PDT 24
Finished Jul 17 06:07:56 PM PDT 24
Peak memory 160784 kb
Host smart-8f37659a-637b-4219-a31c-7e8f006c6510
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3916058489 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.3916058489
Directory /workspace/9.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.4070557559
Short name T116
Test name
Test status
Simulation time 1587850000 ps
CPU time 4.04 seconds
Started Jul 17 04:17:53 PM PDT 24
Finished Jul 17 04:18:03 PM PDT 24
Peak memory 164660 kb
Host smart-2492ef03-9634-4e47-aed6-8bf5ee1a55d7
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4070557559 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.4070557559
Directory /workspace/0.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.2824984641
Short name T146
Test name
Test status
Simulation time 1381710000 ps
CPU time 4.38 seconds
Started Jul 17 04:21:23 PM PDT 24
Finished Jul 17 04:21:33 PM PDT 24
Peak memory 164656 kb
Host smart-3bbdec28-48f6-40a2-87d0-d94322c1b39f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2824984641 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.2824984641
Directory /workspace/1.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.2379304937
Short name T159
Test name
Test status
Simulation time 1331770000 ps
CPU time 3.97 seconds
Started Jul 17 04:18:00 PM PDT 24
Finished Jul 17 04:18:10 PM PDT 24
Peak memory 164564 kb
Host smart-d65b45c3-b767-4407-b777-274f5e9d00cf
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2379304937 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.2379304937
Directory /workspace/10.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.3860462528
Short name T115
Test name
Test status
Simulation time 1190530000 ps
CPU time 3.43 seconds
Started Jul 17 04:17:55 PM PDT 24
Finished Jul 17 04:18:03 PM PDT 24
Peak memory 164652 kb
Host smart-94d8a898-2fa4-4a7e-a34e-243bf5958f4d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3860462528 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.3860462528
Directory /workspace/11.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.3702940406
Short name T123
Test name
Test status
Simulation time 1535650000 ps
CPU time 4.32 seconds
Started Jul 17 04:23:34 PM PDT 24
Finished Jul 17 04:23:44 PM PDT 24
Peak memory 164836 kb
Host smart-33fc02aa-70e4-4830-82ee-b1ee953e5fee
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3702940406 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.3702940406
Directory /workspace/12.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.3069215018
Short name T127
Test name
Test status
Simulation time 1446750000 ps
CPU time 5.05 seconds
Started Jul 17 04:20:14 PM PDT 24
Finished Jul 17 04:20:26 PM PDT 24
Peak memory 164636 kb
Host smart-6d3fa46b-ef1a-4e12-85b6-5c313cf190de
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3069215018 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.3069215018
Directory /workspace/13.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.2069846655
Short name T126
Test name
Test status
Simulation time 1334770000 ps
CPU time 4.32 seconds
Started Jul 17 04:18:07 PM PDT 24
Finished Jul 17 04:18:17 PM PDT 24
Peak memory 164584 kb
Host smart-766970bb-5acd-44f3-9fbf-903433b467d2
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2069846655 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.2069846655
Directory /workspace/14.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.3511558143
Short name T158
Test name
Test status
Simulation time 1321910000 ps
CPU time 3.44 seconds
Started Jul 17 04:17:57 PM PDT 24
Finished Jul 17 04:18:05 PM PDT 24
Peak memory 164620 kb
Host smart-af68f864-c8c9-43a5-a3b5-6832e090673c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3511558143 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.3511558143
Directory /workspace/15.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.3939794751
Short name T113
Test name
Test status
Simulation time 1231270000 ps
CPU time 3.04 seconds
Started Jul 17 04:23:17 PM PDT 24
Finished Jul 17 04:23:24 PM PDT 24
Peak memory 164396 kb
Host smart-968ef644-b608-4066-a0b6-57b11171c7cd
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3939794751 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.3939794751
Directory /workspace/16.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.1898539665
Short name T120
Test name
Test status
Simulation time 1484630000 ps
CPU time 4.24 seconds
Started Jul 17 04:18:06 PM PDT 24
Finished Jul 17 04:18:17 PM PDT 24
Peak memory 164984 kb
Host smart-9f2c4c7e-4617-4e8e-b0b8-e0eeacec65ed
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1898539665 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.1898539665
Directory /workspace/17.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.462167487
Short name T133
Test name
Test status
Simulation time 1445510000 ps
CPU time 3.84 seconds
Started Jul 17 04:19:12 PM PDT 24
Finished Jul 17 04:19:21 PM PDT 24
Peak memory 165012 kb
Host smart-2f63f6ce-0e60-46ea-b032-1edae18306d9
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=462167487 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.462167487
Directory /workspace/18.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.836285651
Short name T156
Test name
Test status
Simulation time 1529130000 ps
CPU time 4.79 seconds
Started Jul 17 04:22:42 PM PDT 24
Finished Jul 17 04:22:53 PM PDT 24
Peak memory 164544 kb
Host smart-70d48f98-22ab-4e8f-a852-70c393703915
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=836285651 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.836285651
Directory /workspace/19.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.1388940214
Short name T114
Test name
Test status
Simulation time 1394490000 ps
CPU time 3.54 seconds
Started Jul 17 04:19:39 PM PDT 24
Finished Jul 17 04:19:48 PM PDT 24
Peak memory 164652 kb
Host smart-758f2ec7-bf80-4132-aaf7-ff2c170814d2
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1388940214 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.1388940214
Directory /workspace/2.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.127350954
Short name T147
Test name
Test status
Simulation time 1517750000 ps
CPU time 4.24 seconds
Started Jul 17 04:18:04 PM PDT 24
Finished Jul 17 04:18:14 PM PDT 24
Peak memory 164980 kb
Host smart-ed15de48-64c4-4769-9b30-dd192729a43c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=127350954 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.127350954
Directory /workspace/20.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.97407983
Short name T137
Test name
Test status
Simulation time 1312230000 ps
CPU time 4.33 seconds
Started Jul 17 04:18:01 PM PDT 24
Finished Jul 17 04:18:11 PM PDT 24
Peak memory 164580 kb
Host smart-5883b66d-96ec-4a51-80f2-5783359f9f4b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=97407983 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.97407983
Directory /workspace/21.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.1470245902
Short name T141
Test name
Test status
Simulation time 1382430000 ps
CPU time 4.35 seconds
Started Jul 17 04:18:00 PM PDT 24
Finished Jul 17 04:18:11 PM PDT 24
Peak memory 164604 kb
Host smart-06d7fdde-9e7b-4468-b21d-e238181ea782
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1470245902 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.1470245902
Directory /workspace/22.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.3278792418
Short name T135
Test name
Test status
Simulation time 1437990000 ps
CPU time 4.31 seconds
Started Jul 17 04:22:40 PM PDT 24
Finished Jul 17 04:22:50 PM PDT 24
Peak memory 164800 kb
Host smart-277cc249-ac26-4d12-97dc-c33ba880d944
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3278792418 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.3278792418
Directory /workspace/23.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.2575411015
Short name T153
Test name
Test status
Simulation time 1576710000 ps
CPU time 5.09 seconds
Started Jul 17 04:17:31 PM PDT 24
Finished Jul 17 04:17:43 PM PDT 24
Peak memory 164624 kb
Host smart-65d1671b-2405-42fb-adfc-8c61b25174d4
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2575411015 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.2575411015
Directory /workspace/24.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.2034021613
Short name T111
Test name
Test status
Simulation time 1545350000 ps
CPU time 3.69 seconds
Started Jul 17 04:17:35 PM PDT 24
Finished Jul 17 04:17:44 PM PDT 24
Peak memory 164660 kb
Host smart-c0da554e-4302-442b-887e-71652eaea189
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2034021613 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.2034021613
Directory /workspace/25.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.1694642922
Short name T117
Test name
Test status
Simulation time 1502790000 ps
CPU time 3.36 seconds
Started Jul 17 04:24:53 PM PDT 24
Finished Jul 17 04:25:02 PM PDT 24
Peak memory 164396 kb
Host smart-1705b118-bcb4-4ab6-9e94-fa06567aad3f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1694642922 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.1694642922
Directory /workspace/26.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.2578610778
Short name T119
Test name
Test status
Simulation time 1461070000 ps
CPU time 3.59 seconds
Started Jul 17 04:23:35 PM PDT 24
Finished Jul 17 04:23:44 PM PDT 24
Peak memory 164396 kb
Host smart-01353f44-dede-4a40-8328-a19b95be0986
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2578610778 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.2578610778
Directory /workspace/27.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.161310610
Short name T138
Test name
Test status
Simulation time 1448870000 ps
CPU time 4.45 seconds
Started Jul 17 04:17:38 PM PDT 24
Finished Jul 17 04:17:50 PM PDT 24
Peak memory 164604 kb
Host smart-8251a224-981f-4d5c-ac4b-1d220f6bcc59
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=161310610 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.161310610
Directory /workspace/28.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.3640532802
Short name T131
Test name
Test status
Simulation time 1658830000 ps
CPU time 4.56 seconds
Started Jul 17 04:18:13 PM PDT 24
Finished Jul 17 04:18:24 PM PDT 24
Peak memory 164652 kb
Host smart-0b6a1d1f-6c81-4928-913a-32644733a831
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3640532802 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.3640532802
Directory /workspace/29.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.3080390594
Short name T128
Test name
Test status
Simulation time 1561650000 ps
CPU time 4.25 seconds
Started Jul 17 04:18:09 PM PDT 24
Finished Jul 17 04:18:20 PM PDT 24
Peak memory 164996 kb
Host smart-14b801f8-9ee8-4231-9283-e59e240d7b3c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3080390594 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.3080390594
Directory /workspace/3.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.1192782001
Short name T152
Test name
Test status
Simulation time 1564150000 ps
CPU time 5.09 seconds
Started Jul 17 04:23:12 PM PDT 24
Finished Jul 17 04:23:24 PM PDT 24
Peak memory 162948 kb
Host smart-eb7d1ac6-e38e-433b-86ac-fb48c59a8efe
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1192782001 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.1192782001
Directory /workspace/30.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.112710970
Short name T144
Test name
Test status
Simulation time 1512990000 ps
CPU time 3.83 seconds
Started Jul 17 04:23:41 PM PDT 24
Finished Jul 17 04:23:50 PM PDT 24
Peak memory 164492 kb
Host smart-d51b541f-3f9d-4fd4-9cd1-c1672307740e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=112710970 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.112710970
Directory /workspace/31.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.1464910573
Short name T149
Test name
Test status
Simulation time 1427330000 ps
CPU time 3.08 seconds
Started Jul 17 04:24:22 PM PDT 24
Finished Jul 17 04:24:30 PM PDT 24
Peak memory 164396 kb
Host smart-b627b7b7-38e3-4b93-8369-183a32c468b5
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1464910573 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.1464910573
Directory /workspace/32.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.2925407495
Short name T118
Test name
Test status
Simulation time 1585950000 ps
CPU time 4.05 seconds
Started Jul 17 04:23:35 PM PDT 24
Finished Jul 17 04:23:45 PM PDT 24
Peak memory 164424 kb
Host smart-871fdb0b-a182-40d9-9fee-320603586479
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2925407495 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.2925407495
Directory /workspace/33.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.1287476437
Short name T160
Test name
Test status
Simulation time 1558850000 ps
CPU time 5.78 seconds
Started Jul 17 04:18:46 PM PDT 24
Finished Jul 17 04:19:00 PM PDT 24
Peak memory 164652 kb
Host smart-bc63ae67-741c-4b43-9888-15c20002499e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1287476437 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.1287476437
Directory /workspace/34.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.945850127
Short name T155
Test name
Test status
Simulation time 1301010000 ps
CPU time 3.66 seconds
Started Jul 17 04:21:00 PM PDT 24
Finished Jul 17 04:21:08 PM PDT 24
Peak memory 164392 kb
Host smart-2cf66642-0c4c-4ca4-86e9-e66a120afc73
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=945850127 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.945850127
Directory /workspace/35.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.231902587
Short name T140
Test name
Test status
Simulation time 1271670000 ps
CPU time 4.11 seconds
Started Jul 17 04:21:51 PM PDT 24
Finished Jul 17 04:22:00 PM PDT 24
Peak memory 164660 kb
Host smart-2a30a649-1068-4ba6-a28f-73c09083da23
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=231902587 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.231902587
Directory /workspace/36.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.380126831
Short name T148
Test name
Test status
Simulation time 1477350000 ps
CPU time 3.79 seconds
Started Jul 17 04:18:14 PM PDT 24
Finished Jul 17 04:18:24 PM PDT 24
Peak memory 165012 kb
Host smart-a6ea15cd-b4be-4861-aa0e-7a5cf0a3808b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=380126831 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.380126831
Directory /workspace/37.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.4138628493
Short name T145
Test name
Test status
Simulation time 1562450000 ps
CPU time 4 seconds
Started Jul 17 04:21:06 PM PDT 24
Finished Jul 17 04:21:16 PM PDT 24
Peak memory 166544 kb
Host smart-d9e034f2-a5c2-4e4e-9716-c3a3d1e46d1d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4138628493 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.4138628493
Directory /workspace/38.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.2837758065
Short name T132
Test name
Test status
Simulation time 1312150000 ps
CPU time 3.7 seconds
Started Jul 17 04:21:20 PM PDT 24
Finished Jul 17 04:21:29 PM PDT 24
Peak memory 164996 kb
Host smart-391e343d-94e3-44d9-8479-edac0500c1fb
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2837758065 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.2837758065
Directory /workspace/39.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.679637078
Short name T130
Test name
Test status
Simulation time 1178330000 ps
CPU time 3.54 seconds
Started Jul 17 04:18:08 PM PDT 24
Finished Jul 17 04:18:16 PM PDT 24
Peak memory 164996 kb
Host smart-31379f9f-2aff-4aa4-b54b-b5883eee58f8
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=679637078 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.679637078
Directory /workspace/4.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.588396537
Short name T129
Test name
Test status
Simulation time 1510090000 ps
CPU time 3.53 seconds
Started Jul 17 04:20:50 PM PDT 24
Finished Jul 17 04:20:59 PM PDT 24
Peak memory 164980 kb
Host smart-a9340339-f89d-4d12-a3c6-5b4ee7c7da13
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=588396537 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.588396537
Directory /workspace/40.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.3297061231
Short name T125
Test name
Test status
Simulation time 1493130000 ps
CPU time 4.02 seconds
Started Jul 17 04:24:15 PM PDT 24
Finished Jul 17 04:24:25 PM PDT 24
Peak memory 163484 kb
Host smart-6b773471-d944-4f12-8e7f-38e859f6cd50
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3297061231 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.3297061231
Directory /workspace/41.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.3836996798
Short name T136
Test name
Test status
Simulation time 1641250000 ps
CPU time 5.95 seconds
Started Jul 17 04:22:21 PM PDT 24
Finished Jul 17 04:22:35 PM PDT 24
Peak memory 164824 kb
Host smart-139bca98-c3c6-47e7-9239-14e57bbf0da6
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3836996798 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.3836996798
Directory /workspace/42.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.920072768
Short name T143
Test name
Test status
Simulation time 1520110000 ps
CPU time 3.92 seconds
Started Jul 17 04:17:50 PM PDT 24
Finished Jul 17 04:17:59 PM PDT 24
Peak memory 164604 kb
Host smart-276a8eff-d7fa-49da-b0ca-41ba18aa8b93
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=920072768 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.920072768
Directory /workspace/43.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.2620936447
Short name T157
Test name
Test status
Simulation time 1455250000 ps
CPU time 4.74 seconds
Started Jul 17 04:21:14 PM PDT 24
Finished Jul 17 04:21:25 PM PDT 24
Peak memory 164836 kb
Host smart-9bf070bc-14ca-44bd-bba8-4c1d594a4458
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2620936447 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.2620936447
Directory /workspace/44.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.3899279132
Short name T142
Test name
Test status
Simulation time 1544290000 ps
CPU time 4.03 seconds
Started Jul 17 04:22:42 PM PDT 24
Finished Jul 17 04:22:52 PM PDT 24
Peak memory 164308 kb
Host smart-e0f23eea-64b0-4360-965c-36edbd39b43d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3899279132 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.3899279132
Directory /workspace/45.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.561915500
Short name T139
Test name
Test status
Simulation time 1398190000 ps
CPU time 4.37 seconds
Started Jul 17 04:18:42 PM PDT 24
Finished Jul 17 04:18:52 PM PDT 24
Peak memory 164604 kb
Host smart-6f0c61c1-6476-481b-b6e1-2d72d1e23883
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=561915500 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.561915500
Directory /workspace/46.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.3796576741
Short name T121
Test name
Test status
Simulation time 1293690000 ps
CPU time 3.6 seconds
Started Jul 17 04:24:49 PM PDT 24
Finished Jul 17 04:24:58 PM PDT 24
Peak memory 164320 kb
Host smart-feff7a38-4dbe-4561-859d-57e36a54a3d0
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3796576741 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.3796576741
Directory /workspace/47.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.2009159341
Short name T134
Test name
Test status
Simulation time 1446310000 ps
CPU time 3.27 seconds
Started Jul 17 04:17:57 PM PDT 24
Finished Jul 17 04:18:06 PM PDT 24
Peak memory 164660 kb
Host smart-90d81d06-582d-4f75-bc25-e137c6166c65
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2009159341 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.2009159341
Directory /workspace/48.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.4193516757
Short name T122
Test name
Test status
Simulation time 1440410000 ps
CPU time 4.16 seconds
Started Jul 17 04:22:34 PM PDT 24
Finished Jul 17 04:22:44 PM PDT 24
Peak memory 162492 kb
Host smart-8c3c16f7-aa9e-4758-8db2-7d10e8eb0ae2
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4193516757 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.4193516757
Directory /workspace/49.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.3587952909
Short name T124
Test name
Test status
Simulation time 1558890000 ps
CPU time 4.32 seconds
Started Jul 17 04:18:07 PM PDT 24
Finished Jul 17 04:18:18 PM PDT 24
Peak memory 164996 kb
Host smart-85e914d1-b9fe-4be5-8b25-f3338f86c1a0
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3587952909 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.3587952909
Directory /workspace/5.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.2414473084
Short name T151
Test name
Test status
Simulation time 1592930000 ps
CPU time 4.29 seconds
Started Jul 17 04:18:08 PM PDT 24
Finished Jul 17 04:18:19 PM PDT 24
Peak memory 164996 kb
Host smart-92a346f5-9156-4986-b6d2-7f1675b14603
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2414473084 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.2414473084
Directory /workspace/6.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.597704984
Short name T112
Test name
Test status
Simulation time 1283150000 ps
CPU time 3.08 seconds
Started Jul 17 04:23:00 PM PDT 24
Finished Jul 17 04:23:07 PM PDT 24
Peak memory 164464 kb
Host smart-c1823a82-c60a-4569-8398-59f658ae2964
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=597704984 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.597704984
Directory /workspace/7.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.3217742461
Short name T154
Test name
Test status
Simulation time 1653430000 ps
CPU time 4.43 seconds
Started Jul 17 04:17:59 PM PDT 24
Finished Jul 17 04:18:10 PM PDT 24
Peak memory 164660 kb
Host smart-7ab9698a-5393-4d2c-8e62-f801e759b25a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3217742461 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.3217742461
Directory /workspace/8.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2794252868
Short name T150
Test name
Test status
Simulation time 1476050000 ps
CPU time 4.68 seconds
Started Jul 17 04:20:43 PM PDT 24
Finished Jul 17 04:20:54 PM PDT 24
Peak memory 164836 kb
Host smart-8d0ae37c-f42f-4c92-926b-c158064604a7
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2794252868 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.2794252868
Directory /workspace/9.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.4167471474
Short name T57
Test name
Test status
Simulation time 1419130000 ps
CPU time 5.43 seconds
Started Jul 17 04:18:46 PM PDT 24
Finished Jul 17 04:18:59 PM PDT 24
Peak memory 164652 kb
Host smart-f7f75b92-449e-4771-bce9-b5227fa45435
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4167471474 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.4167471474
Directory /workspace/1.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.104718392
Short name T69
Test name
Test status
Simulation time 1480170000 ps
CPU time 3.9 seconds
Started Jul 17 04:22:47 PM PDT 24
Finished Jul 17 04:22:56 PM PDT 24
Peak memory 164392 kb
Host smart-cf23de6c-7fbe-4b2b-8775-0056f17d9a79
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=104718392 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.104718392
Directory /workspace/10.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.2144013377
Short name T3
Test name
Test status
Simulation time 1545290000 ps
CPU time 4.28 seconds
Started Jul 17 04:22:34 PM PDT 24
Finished Jul 17 04:22:45 PM PDT 24
Peak memory 162224 kb
Host smart-66c7f835-520b-4deb-968a-7246402fcbfb
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2144013377 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.2144013377
Directory /workspace/11.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.1772680919
Short name T46
Test name
Test status
Simulation time 1571230000 ps
CPU time 4.58 seconds
Started Jul 17 04:18:06 PM PDT 24
Finished Jul 17 04:18:18 PM PDT 24
Peak memory 164984 kb
Host smart-f8bfcd9e-ec90-4fd3-9d36-060540b689ab
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1772680919 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.1772680919
Directory /workspace/12.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.1522937041
Short name T9
Test name
Test status
Simulation time 1381090000 ps
CPU time 4.23 seconds
Started Jul 17 04:18:09 PM PDT 24
Finished Jul 17 04:18:19 PM PDT 24
Peak memory 164996 kb
Host smart-a83cba46-93cd-463a-a071-3c18a96e04eb
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1522937041 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.1522937041
Directory /workspace/13.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.846181860
Short name T39
Test name
Test status
Simulation time 1389430000 ps
CPU time 4.18 seconds
Started Jul 17 04:18:06 PM PDT 24
Finished Jul 17 04:18:17 PM PDT 24
Peak memory 164980 kb
Host smart-1a59bfd6-10c8-4010-9508-5c28544bb8fa
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=846181860 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.846181860
Directory /workspace/14.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.1398060333
Short name T68
Test name
Test status
Simulation time 1578910000 ps
CPU time 4.55 seconds
Started Jul 17 04:18:45 PM PDT 24
Finished Jul 17 04:18:55 PM PDT 24
Peak memory 164660 kb
Host smart-75c132ab-03c3-43cc-b837-a283da0ce49d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1398060333 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.1398060333
Directory /workspace/15.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.8049256
Short name T13
Test name
Test status
Simulation time 1354090000 ps
CPU time 4.24 seconds
Started Jul 17 04:18:06 PM PDT 24
Finished Jul 17 04:18:17 PM PDT 24
Peak memory 165032 kb
Host smart-c84f469d-7aef-4035-9ade-5dde10edfa73
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=8049256 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.8049256
Directory /workspace/16.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.3761487833
Short name T52
Test name
Test status
Simulation time 1539030000 ps
CPU time 3.97 seconds
Started Jul 17 04:18:14 PM PDT 24
Finished Jul 17 04:18:24 PM PDT 24
Peak memory 166596 kb
Host smart-f31b4458-f46e-4e57-805f-4d63e4825986
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3761487833 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.3761487833
Directory /workspace/17.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.85863042
Short name T44
Test name
Test status
Simulation time 1268110000 ps
CPU time 2.81 seconds
Started Jul 17 04:17:48 PM PDT 24
Finished Jul 17 04:17:55 PM PDT 24
Peak memory 164576 kb
Host smart-55ecec8a-3b22-4e0d-949d-1a6ff9eee839
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=85863042 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.85863042
Directory /workspace/18.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.3100449902
Short name T54
Test name
Test status
Simulation time 1333930000 ps
CPU time 5.27 seconds
Started Jul 17 04:22:19 PM PDT 24
Finished Jul 17 04:22:32 PM PDT 24
Peak memory 164824 kb
Host smart-5aaf332b-ea4c-46f0-90d9-a1469f0facff
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3100449902 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.3100449902
Directory /workspace/19.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.499493043
Short name T66
Test name
Test status
Simulation time 1622510000 ps
CPU time 4.41 seconds
Started Jul 17 04:19:47 PM PDT 24
Finished Jul 17 04:19:58 PM PDT 24
Peak memory 164592 kb
Host smart-6175c471-2731-4a60-a581-2d3f902442a6
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=499493043 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.499493043
Directory /workspace/2.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.2513593203
Short name T65
Test name
Test status
Simulation time 1586590000 ps
CPU time 4.69 seconds
Started Jul 17 04:18:00 PM PDT 24
Finished Jul 17 04:18:12 PM PDT 24
Peak memory 164596 kb
Host smart-b7dfdc4f-7439-4497-8134-2fd88cdd42dd
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2513593203 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.2513593203
Directory /workspace/20.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.840951609
Short name T58
Test name
Test status
Simulation time 1561230000 ps
CPU time 4.72 seconds
Started Jul 17 04:17:33 PM PDT 24
Finished Jul 17 04:17:45 PM PDT 24
Peak memory 164648 kb
Host smart-8b1328d4-8a3e-4dd6-b055-19a0898ed644
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=840951609 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.840951609
Directory /workspace/21.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.1343657080
Short name T59
Test name
Test status
Simulation time 1504570000 ps
CPU time 4.16 seconds
Started Jul 17 04:21:52 PM PDT 24
Finished Jul 17 04:22:03 PM PDT 24
Peak memory 163468 kb
Host smart-f929daf4-45f1-4400-89a5-a6e6a4fc7982
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1343657080 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.1343657080
Directory /workspace/22.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.2939229310
Short name T34
Test name
Test status
Simulation time 1571370000 ps
CPU time 4.01 seconds
Started Jul 17 04:19:12 PM PDT 24
Finished Jul 17 04:19:22 PM PDT 24
Peak memory 166596 kb
Host smart-0d697e8e-1d84-4729-b50c-2b3509a0e13d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2939229310 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.2939229310
Directory /workspace/23.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.393088066
Short name T40
Test name
Test status
Simulation time 1498910000 ps
CPU time 4 seconds
Started Jul 17 04:24:32 PM PDT 24
Finished Jul 17 04:24:43 PM PDT 24
Peak memory 163992 kb
Host smart-13a137e6-b8e4-408f-a331-276ea924c1a4
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=393088066 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.393088066
Directory /workspace/24.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.3240993322
Short name T60
Test name
Test status
Simulation time 1523370000 ps
CPU time 4.18 seconds
Started Jul 17 04:18:33 PM PDT 24
Finished Jul 17 04:18:43 PM PDT 24
Peak memory 164660 kb
Host smart-e14d056a-16f3-489c-bd74-840f8e31d14f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3240993322 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.3240993322
Directory /workspace/25.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.4174162098
Short name T48
Test name
Test status
Simulation time 1488270000 ps
CPU time 3.84 seconds
Started Jul 17 04:23:18 PM PDT 24
Finished Jul 17 04:23:27 PM PDT 24
Peak memory 164984 kb
Host smart-f03cdb95-ae03-418e-a484-7e231a0c183c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4174162098 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.4174162098
Directory /workspace/26.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.3780084049
Short name T32
Test name
Test status
Simulation time 1147710000 ps
CPU time 3.79 seconds
Started Jul 17 04:19:02 PM PDT 24
Finished Jul 17 04:19:11 PM PDT 24
Peak memory 164652 kb
Host smart-07404572-e680-4a2a-b481-f03ce0eb1b58
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3780084049 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.3780084049
Directory /workspace/27.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.3107304875
Short name T43
Test name
Test status
Simulation time 1381590000 ps
CPU time 4.28 seconds
Started Jul 17 04:17:46 PM PDT 24
Finished Jul 17 04:17:56 PM PDT 24
Peak memory 164660 kb
Host smart-41aff776-b823-4f4b-a869-b2f4cf95286f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3107304875 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.3107304875
Directory /workspace/28.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.1877261425
Short name T55
Test name
Test status
Simulation time 1465790000 ps
CPU time 5.1 seconds
Started Jul 17 04:18:52 PM PDT 24
Finished Jul 17 04:19:04 PM PDT 24
Peak memory 164660 kb
Host smart-d790a9d0-9f97-4ab8-8312-76717f6c1652
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1877261425 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.1877261425
Directory /workspace/29.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.3280186472
Short name T53
Test name
Test status
Simulation time 1557890000 ps
CPU time 3.9 seconds
Started Jul 17 04:18:28 PM PDT 24
Finished Jul 17 04:18:38 PM PDT 24
Peak memory 164652 kb
Host smart-39926840-d16f-4872-9a1b-219148344e14
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3280186472 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.3280186472
Directory /workspace/3.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.311483877
Short name T62
Test name
Test status
Simulation time 1541190000 ps
CPU time 3.68 seconds
Started Jul 17 04:23:34 PM PDT 24
Finished Jul 17 04:23:43 PM PDT 24
Peak memory 164648 kb
Host smart-c70e0114-5a3a-4a3d-a115-2119d67f578f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=311483877 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.311483877
Directory /workspace/30.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.822890859
Short name T38
Test name
Test status
Simulation time 1345150000 ps
CPU time 3.44 seconds
Started Jul 17 04:21:15 PM PDT 24
Finished Jul 17 04:21:23 PM PDT 24
Peak memory 164536 kb
Host smart-07c0ac8e-df4d-4a0c-8004-589d8cae9cb9
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=822890859 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.822890859
Directory /workspace/31.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.3260566758
Short name T50
Test name
Test status
Simulation time 1417450000 ps
CPU time 3.65 seconds
Started Jul 17 04:18:50 PM PDT 24
Finished Jul 17 04:18:58 PM PDT 24
Peak memory 164660 kb
Host smart-27ac47eb-70a9-4242-9e04-12176343f4d3
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3260566758 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.3260566758
Directory /workspace/32.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.679784365
Short name T1
Test name
Test status
Simulation time 1518490000 ps
CPU time 5.4 seconds
Started Jul 17 04:18:51 PM PDT 24
Finished Jul 17 04:19:04 PM PDT 24
Peak memory 164604 kb
Host smart-01881c7d-3e34-426a-a408-9c73a7d45e43
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=679784365 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.679784365
Directory /workspace/33.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.1419594631
Short name T42
Test name
Test status
Simulation time 1592690000 ps
CPU time 4.68 seconds
Started Jul 17 04:23:12 PM PDT 24
Finished Jul 17 04:23:24 PM PDT 24
Peak memory 163704 kb
Host smart-d8ec0e77-2627-45b5-ad70-187232c7266d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1419594631 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.1419594631
Directory /workspace/34.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.4214421887
Short name T33
Test name
Test status
Simulation time 1455710000 ps
CPU time 3.72 seconds
Started Jul 17 04:24:34 PM PDT 24
Finished Jul 17 04:24:44 PM PDT 24
Peak memory 164540 kb
Host smart-a7f226b5-cbb8-4661-8080-05ad97b969c6
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4214421887 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.4214421887
Directory /workspace/35.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.1112387013
Short name T51
Test name
Test status
Simulation time 1554610000 ps
CPU time 4.97 seconds
Started Jul 17 04:20:10 PM PDT 24
Finished Jul 17 04:20:21 PM PDT 24
Peak memory 166596 kb
Host smart-61d00fb5-4bbd-4caa-8b6f-849607dfcc8a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1112387013 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.1112387013
Directory /workspace/36.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.500689930
Short name T45
Test name
Test status
Simulation time 1532530000 ps
CPU time 5.02 seconds
Started Jul 17 04:21:51 PM PDT 24
Finished Jul 17 04:22:02 PM PDT 24
Peak memory 164660 kb
Host smart-e7c1a40b-2bba-4831-aa24-d189e34ff939
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=500689930 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.500689930
Directory /workspace/37.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.1873593655
Short name T47
Test name
Test status
Simulation time 1157170000 ps
CPU time 3.24 seconds
Started Jul 17 04:24:33 PM PDT 24
Finished Jul 17 04:24:42 PM PDT 24
Peak memory 164540 kb
Host smart-1a271419-4e41-4b86-a1e8-cb4388a7836a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1873593655 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.1873593655
Directory /workspace/38.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.660993387
Short name T61
Test name
Test status
Simulation time 1554750000 ps
CPU time 3.87 seconds
Started Jul 17 04:24:34 PM PDT 24
Finished Jul 17 04:24:45 PM PDT 24
Peak memory 164536 kb
Host smart-a6980738-56f5-4d2a-9820-6c3739049aac
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=660993387 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.660993387
Directory /workspace/39.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.119369639
Short name T12
Test name
Test status
Simulation time 1381150000 ps
CPU time 4.33 seconds
Started Jul 17 04:18:43 PM PDT 24
Finished Jul 17 04:18:52 PM PDT 24
Peak memory 164500 kb
Host smart-6cff94c8-789e-43dd-9343-34abf0035ae0
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=119369639 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.119369639
Directory /workspace/4.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.555255079
Short name T49
Test name
Test status
Simulation time 1409930000 ps
CPU time 3.9 seconds
Started Jul 17 04:22:34 PM PDT 24
Finished Jul 17 04:22:44 PM PDT 24
Peak memory 162696 kb
Host smart-ac0355f1-7520-4be3-978e-29bdffb3bfd3
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=555255079 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.555255079
Directory /workspace/40.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.745566519
Short name T63
Test name
Test status
Simulation time 1505330000 ps
CPU time 4.67 seconds
Started Jul 17 04:21:25 PM PDT 24
Finished Jul 17 04:21:36 PM PDT 24
Peak memory 164604 kb
Host smart-f839603d-b158-464a-aa8d-c7b313f86ca4
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=745566519 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.745566519
Directory /workspace/41.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.3744302760
Short name T67
Test name
Test status
Simulation time 1440470000 ps
CPU time 3.71 seconds
Started Jul 17 04:24:18 PM PDT 24
Finished Jul 17 04:24:27 PM PDT 24
Peak memory 164396 kb
Host smart-8811d4e7-bee2-4e2d-b21e-8622411e6700
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3744302760 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.3744302760
Directory /workspace/42.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.187552055
Short name T4
Test name
Test status
Simulation time 1559350000 ps
CPU time 4.47 seconds
Started Jul 17 04:23:21 PM PDT 24
Finished Jul 17 04:23:32 PM PDT 24
Peak memory 165012 kb
Host smart-2a71f392-b605-4b91-9c0e-1a4888d3a1a8
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=187552055 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.187552055
Directory /workspace/43.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.79952689
Short name T64
Test name
Test status
Simulation time 1451230000 ps
CPU time 3.95 seconds
Started Jul 17 04:22:28 PM PDT 24
Finished Jul 17 04:22:37 PM PDT 24
Peak memory 164536 kb
Host smart-fbfe1a71-977f-4cb5-bb9a-8e8ec3028e02
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=79952689 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.79952689
Directory /workspace/44.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.903530920
Short name T56
Test name
Test status
Simulation time 1596530000 ps
CPU time 5.46 seconds
Started Jul 17 04:20:36 PM PDT 24
Finished Jul 17 04:20:49 PM PDT 24
Peak memory 164604 kb
Host smart-9eba1e04-7bcc-407c-be4d-d7ea5732716e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=903530920 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.903530920
Directory /workspace/45.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.856026959
Short name T41
Test name
Test status
Simulation time 1329910000 ps
CPU time 3.55 seconds
Started Jul 17 04:22:42 PM PDT 24
Finished Jul 17 04:22:51 PM PDT 24
Peak memory 164304 kb
Host smart-ca300721-5300-4d46-ac00-879e25d77f3c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=856026959 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.856026959
Directory /workspace/46.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.1135393800
Short name T70
Test name
Test status
Simulation time 1354210000 ps
CPU time 4.43 seconds
Started Jul 17 04:22:51 PM PDT 24
Finished Jul 17 04:23:01 PM PDT 24
Peak memory 164424 kb
Host smart-a7f83315-2e66-4926-be06-9cd94e24c8ce
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1135393800 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.1135393800
Directory /workspace/47.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.291883169
Short name T36
Test name
Test status
Simulation time 1571310000 ps
CPU time 4.33 seconds
Started Jul 17 04:23:28 PM PDT 24
Finished Jul 17 04:23:38 PM PDT 24
Peak memory 164340 kb
Host smart-f97b63f8-2746-4a69-bde9-eaff28921331
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=291883169 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.291883169
Directory /workspace/48.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.4068639313
Short name T10
Test name
Test status
Simulation time 1457630000 ps
CPU time 4.1 seconds
Started Jul 17 04:22:34 PM PDT 24
Finished Jul 17 04:22:44 PM PDT 24
Peak memory 162076 kb
Host smart-7af82748-933f-4217-9b71-12f21648a6f4
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4068639313 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.4068639313
Directory /workspace/49.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.1762073867
Short name T37
Test name
Test status
Simulation time 1323370000 ps
CPU time 2.84 seconds
Started Jul 17 04:17:06 PM PDT 24
Finished Jul 17 04:17:15 PM PDT 24
Peak memory 164632 kb
Host smart-1bd46f6a-dbf2-4013-99c3-09255a13b27a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1762073867 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.1762073867
Directory /workspace/5.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.4160908684
Short name T31
Test name
Test status
Simulation time 1323010000 ps
CPU time 3.93 seconds
Started Jul 17 04:18:43 PM PDT 24
Finished Jul 17 04:18:52 PM PDT 24
Peak memory 164544 kb
Host smart-c6a90c2f-d50c-40c5-aa20-4474c690c342
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4160908684 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.4160908684
Directory /workspace/6.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.955067634
Short name T11
Test name
Test status
Simulation time 1527430000 ps
CPU time 4.04 seconds
Started Jul 17 04:17:24 PM PDT 24
Finished Jul 17 04:17:34 PM PDT 24
Peak memory 164564 kb
Host smart-8382af60-04a9-4df9-a2e1-27f2955721fd
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=955067634 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.955067634
Directory /workspace/7.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.54497155
Short name T2
Test name
Test status
Simulation time 1413330000 ps
CPU time 3.82 seconds
Started Jul 17 04:18:08 PM PDT 24
Finished Jul 17 04:18:18 PM PDT 24
Peak memory 164988 kb
Host smart-b46d4e17-88fe-4d4a-8d4b-23b34a806075
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=54497155 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.54497155
Directory /workspace/8.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.978862033
Short name T35
Test name
Test status
Simulation time 1381510000 ps
CPU time 5.09 seconds
Started Jul 17 04:21:38 PM PDT 24
Finished Jul 17 04:21:50 PM PDT 24
Peak memory 164576 kb
Host smart-7d41e39e-c928-4b43-a18f-b988f94b8b6b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=978862033 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.978862033
Directory /workspace/9.prim_lfsr_gal_smoke/latest
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