Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.31 100.00 96.55 100.00 100.00 95.00


Total tests in report: 200
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
87.31 87.31 100.00 100.00 96.55 96.55 100.00 100.00 100.00 100.00 40.00 40.00 /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.1544060837
96.81 9.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 87.50 47.50 /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.1981042014
98.31 1.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 95.00 7.50 /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.3510793541

Tests that do not contribute to grading

Name
/workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.1095731431
/workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.2225466716
/workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.4249722346
/workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.168099713
/workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.730313527
/workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.314392223
/workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.3140788537
/workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.1504939686
/workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.780347494
/workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.853959607
/workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.1814730390
/workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.2902023820
/workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.837809131
/workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.1469219010
/workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.1474527198
/workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.3948966510
/workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.637485423
/workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.27793523
/workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1466173754
/workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.3602196787
/workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.858714295
/workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.764727841
/workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.502245561
/workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.2384794128
/workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.545329398
/workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.3208402431
/workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.426829899
/workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.2139265150
/workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.1768131956
/workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.3331578187
/workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.2080145860
/workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.1230417176
/workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.1643753994
/workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.2911383049
/workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.1724135108
/workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.316101947
/workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.2661079505
/workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.18018433
/workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.1986029728
/workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.2485393639
/workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.3798845574
/workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.881076899
/workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.654945040
/workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.3944264367
/workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.819922015
/workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.1349242074
/workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.479715075
/workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.6996384
/workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.3692704536
/workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.1229189955
/workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.1229848164
/workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.2926659087
/workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.307530741
/workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.1782530553
/workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.1175356970
/workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.2029360178
/workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.1761693371
/workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.1016464909
/workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.2868416674
/workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.2887824089
/workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.3917913658
/workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.1612356122
/workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.316059161
/workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.106228698
/workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.3915404068
/workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.1264946033
/workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.2155602184
/workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.280885597
/workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.1827737731
/workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.2534297789
/workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.853801015
/workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.1153622195
/workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.749259267
/workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.164264904
/workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.2932997595
/workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.1840932751
/workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.1832162205
/workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.3963220272
/workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.3375694510
/workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.3404225937
/workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.2038438948
/workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.903416946
/workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.531669591
/workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.781401705
/workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.2509308254
/workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.2412133993
/workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.694496321
/workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.3280208661
/workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.4261152711
/workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.2128755038
/workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.190181937
/workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.250481170
/workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.3634499798
/workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.2358307812
/workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.3494803622
/workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.4187175458
/workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.3871620361
/workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.462092093
/workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.2677308789
/workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.505229981
/workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.611416181
/workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.417268122
/workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.3625091524
/workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.3816829556
/workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.3088462716
/workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.1105165243
/workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.2680122332
/workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.2265600631
/workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.3402075259
/workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.2225848640
/workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.3562687622
/workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.1590574383
/workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3592770209
/workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.4088715939
/workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.1847164190
/workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.2197665532
/workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.2616920895
/workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.902266453
/workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.4195679656
/workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.2624314070
/workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.1840868505
/workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.2508437251
/workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.2048649915
/workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.1401383263
/workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.4241115264
/workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.246385459
/workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.2180284982
/workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.420308509
/workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.770297888
/workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1889884409
/workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.1594906710
/workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.2310421645
/workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3876849857
/workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.3561301897
/workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.2722118821
/workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.2576964161
/workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.3445158136
/workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.4221224768
/workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.686457697
/workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.1204068861
/workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.2669151032
/workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.1240899933
/workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.2613087625
/workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.4146782455
/workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.2688352641
/workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.1775337470
/workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.2469375246
/workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2242048709
/workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.2089827675
/workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.4202376328
/workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.2437584468
/workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.383114398
/workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.2665368888
/workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.3586356484
/workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.60057567
/workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.115488460
/workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.3637929325
/workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.2662968298
/workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.3440863135
/workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.1977017057
/workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.113928758
/workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.1213002180
/workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.2748948216
/workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.3953042216
/workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.1143996047
/workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.433803084
/workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.2663966223
/workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.616522457
/workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.3588144444
/workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.3101467841
/workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.842931927
/workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.3106778879
/workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.421651142
/workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.3537715817
/workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.391574850
/workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.322765039
/workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.2813927924
/workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.2249246780
/workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.1691430228
/workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.3640701961
/workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.343258410
/workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.2458784571
/workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.1772727756
/workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.2228176691
/workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.442965238
/workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.2425859052
/workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.879592068
/workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.2514118257
/workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.1728116076
/workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.2758226757
/workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.3264940681
/workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.1816648358
/workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.422738578
/workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.3525884853
/workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.3119200598
/workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.3686143176
/workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.1219073692



Total test records in report: 200
tests.html | tests1.html | tests2.html | tests3.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.2662968298 Jul 18 04:45:39 PM PDT 24 Jul 18 04:45:57 PM PDT 24 1498130000 ps
T2 /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.2249246780 Jul 18 04:46:30 PM PDT 24 Jul 18 04:46:42 PM PDT 24 1476230000 ps
T3 /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.1544060837 Jul 18 04:45:42 PM PDT 24 Jul 18 04:45:59 PM PDT 24 1364670000 ps
T7 /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.1143996047 Jul 18 04:45:58 PM PDT 24 Jul 18 04:46:09 PM PDT 24 1294870000 ps
T8 /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.1816648358 Jul 18 04:46:19 PM PDT 24 Jul 18 04:46:29 PM PDT 24 1558490000 ps
T9 /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.3101467841 Jul 18 04:45:54 PM PDT 24 Jul 18 04:46:05 PM PDT 24 1465690000 ps
T10 /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.433803084 Jul 18 04:45:54 PM PDT 24 Jul 18 04:46:08 PM PDT 24 1505810000 ps
T11 /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.2458784571 Jul 18 04:45:36 PM PDT 24 Jul 18 04:45:52 PM PDT 24 1623230000 ps
T12 /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.2813927924 Jul 18 04:46:17 PM PDT 24 Jul 18 04:46:24 PM PDT 24 1474970000 ps
T13 /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.113928758 Jul 18 04:45:41 PM PDT 24 Jul 18 04:45:57 PM PDT 24 1464530000 ps
T31 /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.2748948216 Jul 18 04:45:55 PM PDT 24 Jul 18 04:46:04 PM PDT 24 1472090000 ps
T32 /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.322765039 Jul 18 04:46:27 PM PDT 24 Jul 18 04:46:38 PM PDT 24 1383210000 ps
T33 /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.3440863135 Jul 18 04:45:43 PM PDT 24 Jul 18 04:45:58 PM PDT 24 1527510000 ps
T34 /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.1213002180 Jul 18 04:45:53 PM PDT 24 Jul 18 04:46:03 PM PDT 24 1369830000 ps
T35 /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.2089827675 Jul 18 04:45:38 PM PDT 24 Jul 18 04:45:52 PM PDT 24 1465950000 ps
T36 /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.2228176691 Jul 18 04:46:21 PM PDT 24 Jul 18 04:46:34 PM PDT 24 1448870000 ps
T37 /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.3637929325 Jul 18 04:45:43 PM PDT 24 Jul 18 04:45:58 PM PDT 24 1438510000 ps
T38 /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.1977017057 Jul 18 04:45:38 PM PDT 24 Jul 18 04:45:54 PM PDT 24 1538810000 ps
T39 /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.115488460 Jul 18 04:45:38 PM PDT 24 Jul 18 04:45:53 PM PDT 24 1482230000 ps
T40 /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.1219073692 Jul 18 04:45:38 PM PDT 24 Jul 18 04:45:50 PM PDT 24 1461070000 ps
T41 /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.879592068 Jul 18 04:46:17 PM PDT 24 Jul 18 04:46:23 PM PDT 24 1003550000 ps
T42 /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.4202376328 Jul 18 04:45:40 PM PDT 24 Jul 18 04:45:54 PM PDT 24 1145050000 ps
T43 /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.1728116076 Jul 18 04:46:16 PM PDT 24 Jul 18 04:46:25 PM PDT 24 1549670000 ps
T44 /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.3588144444 Jul 18 04:45:55 PM PDT 24 Jul 18 04:46:05 PM PDT 24 1366270000 ps
T45 /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.1772727756 Jul 18 04:46:22 PM PDT 24 Jul 18 04:46:32 PM PDT 24 1503090000 ps
T46 /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.3264940681 Jul 18 04:46:20 PM PDT 24 Jul 18 04:46:29 PM PDT 24 1416550000 ps
T47 /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.3537715817 Jul 18 04:46:19 PM PDT 24 Jul 18 04:46:28 PM PDT 24 1533250000 ps
T48 /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.3640701961 Jul 18 04:46:20 PM PDT 24 Jul 18 04:46:29 PM PDT 24 1475630000 ps
T49 /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.3953042216 Jul 18 04:45:53 PM PDT 24 Jul 18 04:46:03 PM PDT 24 1451910000 ps
T50 /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.2758226757 Jul 18 04:46:26 PM PDT 24 Jul 18 04:46:39 PM PDT 24 1492070000 ps
T51 /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.391574850 Jul 18 04:46:20 PM PDT 24 Jul 18 04:46:29 PM PDT 24 1406530000 ps
T52 /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.3686143176 Jul 18 04:45:40 PM PDT 24 Jul 18 04:45:55 PM PDT 24 1542870000 ps
T53 /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.3106778879 Jul 18 04:45:56 PM PDT 24 Jul 18 04:46:07 PM PDT 24 1360290000 ps
T54 /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.421651142 Jul 18 04:45:55 PM PDT 24 Jul 18 04:46:05 PM PDT 24 1311350000 ps
T55 /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.616522457 Jul 18 04:45:53 PM PDT 24 Jul 18 04:46:01 PM PDT 24 1468710000 ps
T56 /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.3586356484 Jul 18 04:45:41 PM PDT 24 Jul 18 04:45:55 PM PDT 24 1149090000 ps
T57 /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.2514118257 Jul 18 04:46:19 PM PDT 24 Jul 18 04:46:30 PM PDT 24 1503570000 ps
T58 /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.442965238 Jul 18 04:46:22 PM PDT 24 Jul 18 04:46:30 PM PDT 24 1343510000 ps
T59 /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.422738578 Jul 18 04:45:40 PM PDT 24 Jul 18 04:45:57 PM PDT 24 1351690000 ps
T60 /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.383114398 Jul 18 04:45:41 PM PDT 24 Jul 18 04:45:56 PM PDT 24 1429930000 ps
T61 /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.343258410 Jul 18 04:46:26 PM PDT 24 Jul 18 04:46:39 PM PDT 24 1490190000 ps
T62 /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.1691430228 Jul 18 04:46:16 PM PDT 24 Jul 18 04:46:25 PM PDT 24 1541890000 ps
T63 /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.2663966223 Jul 18 04:45:56 PM PDT 24 Jul 18 04:46:08 PM PDT 24 1452230000 ps
T64 /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.842931927 Jul 18 04:45:35 PM PDT 24 Jul 18 04:45:52 PM PDT 24 1509410000 ps
T65 /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.60057567 Jul 18 04:45:37 PM PDT 24 Jul 18 04:45:54 PM PDT 24 1485990000 ps
T66 /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.2437584468 Jul 18 04:45:37 PM PDT 24 Jul 18 04:45:55 PM PDT 24 1477450000 ps
T67 /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.2665368888 Jul 18 04:45:42 PM PDT 24 Jul 18 04:45:56 PM PDT 24 1563470000 ps
T68 /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.3525884853 Jul 18 04:45:37 PM PDT 24 Jul 18 04:45:52 PM PDT 24 1513250000 ps
T69 /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.3119200598 Jul 18 04:45:39 PM PDT 24 Jul 18 04:45:59 PM PDT 24 1504130000 ps
T70 /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.2425859052 Jul 18 04:46:23 PM PDT 24 Jul 18 04:46:33 PM PDT 24 1574090000 ps
T4 /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.1981042014 Jul 18 04:45:38 PM PDT 24 Jul 18 05:16:10 PM PDT 24 336903250000 ps
T5 /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.2080145860 Jul 18 04:45:37 PM PDT 24 Jul 18 05:23:28 PM PDT 24 336374650000 ps
T6 /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.853959607 Jul 18 04:45:39 PM PDT 24 Jul 18 05:17:06 PM PDT 24 336802690000 ps
T14 /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.881076899 Jul 18 04:45:38 PM PDT 24 Jul 18 05:29:12 PM PDT 24 336573770000 ps
T15 /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.1230417176 Jul 18 04:45:39 PM PDT 24 Jul 18 05:20:16 PM PDT 24 336668990000 ps
T16 /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1466173754 Jul 18 04:45:36 PM PDT 24 Jul 18 05:24:33 PM PDT 24 336548290000 ps
T17 /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.819922015 Jul 18 04:45:39 PM PDT 24 Jul 18 05:14:50 PM PDT 24 336524770000 ps
T18 /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.654945040 Jul 18 04:45:38 PM PDT 24 Jul 18 05:20:45 PM PDT 24 336571510000 ps
T19 /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.6996384 Jul 18 04:45:42 PM PDT 24 Jul 18 05:25:25 PM PDT 24 336408170000 ps
T20 /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.1469219010 Jul 18 04:45:38 PM PDT 24 Jul 18 05:19:40 PM PDT 24 336474610000 ps
T71 /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.502245561 Jul 18 04:45:37 PM PDT 24 Jul 18 05:26:56 PM PDT 24 337087670000 ps
T72 /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.858714295 Jul 18 04:45:39 PM PDT 24 Jul 18 05:21:31 PM PDT 24 336780350000 ps
T73 /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.4249722346 Jul 18 04:45:39 PM PDT 24 Jul 18 05:29:57 PM PDT 24 336966050000 ps
T74 /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.2661079505 Jul 18 04:45:38 PM PDT 24 Jul 18 05:21:50 PM PDT 24 336448630000 ps
T75 /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.3692704536 Jul 18 04:45:40 PM PDT 24 Jul 18 05:20:43 PM PDT 24 336245610000 ps
T76 /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.3798845574 Jul 18 04:45:34 PM PDT 24 Jul 18 05:20:46 PM PDT 24 336345470000 ps
T77 /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.780347494 Jul 18 04:45:39 PM PDT 24 Jul 18 05:29:40 PM PDT 24 336747610000 ps
T78 /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.2225466716 Jul 18 04:45:37 PM PDT 24 Jul 18 05:18:45 PM PDT 24 336977950000 ps
T79 /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.764727841 Jul 18 04:45:43 PM PDT 24 Jul 18 05:22:58 PM PDT 24 337002170000 ps
T80 /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.2139265150 Jul 18 04:45:37 PM PDT 24 Jul 18 05:17:26 PM PDT 24 336883370000 ps
T81 /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.545329398 Jul 18 04:45:39 PM PDT 24 Jul 18 05:21:44 PM PDT 24 336510890000 ps
T82 /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.168099713 Jul 18 04:45:42 PM PDT 24 Jul 18 05:25:43 PM PDT 24 337058350000 ps
T83 /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.1643753994 Jul 18 04:45:42 PM PDT 24 Jul 18 05:30:14 PM PDT 24 336356830000 ps
T84 /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.1095731431 Jul 18 04:45:40 PM PDT 24 Jul 18 05:26:05 PM PDT 24 336512290000 ps
T85 /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.1504939686 Jul 18 04:45:42 PM PDT 24 Jul 18 05:22:38 PM PDT 24 336679050000 ps
T86 /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.479715075 Jul 18 04:45:40 PM PDT 24 Jul 18 05:23:01 PM PDT 24 336343890000 ps
T87 /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.2902023820 Jul 18 04:45:39 PM PDT 24 Jul 18 05:19:56 PM PDT 24 336814590000 ps
T88 /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.3948966510 Jul 18 04:45:39 PM PDT 24 Jul 18 05:17:44 PM PDT 24 336370450000 ps
T89 /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.1768131956 Jul 18 04:45:40 PM PDT 24 Jul 18 05:19:10 PM PDT 24 337065410000 ps
T90 /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.637485423 Jul 18 04:45:40 PM PDT 24 Jul 18 05:26:16 PM PDT 24 336950050000 ps
T91 /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.1986029728 Jul 18 04:45:38 PM PDT 24 Jul 18 05:29:34 PM PDT 24 336723670000 ps
T92 /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.3944264367 Jul 18 04:45:38 PM PDT 24 Jul 18 05:20:00 PM PDT 24 337049430000 ps
T93 /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.1814730390 Jul 18 04:45:40 PM PDT 24 Jul 18 05:26:07 PM PDT 24 336470110000 ps
T94 /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.1474527198 Jul 18 04:45:37 PM PDT 24 Jul 18 05:23:23 PM PDT 24 336708030000 ps
T95 /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.18018433 Jul 18 04:45:39 PM PDT 24 Jul 18 05:29:50 PM PDT 24 337160590000 ps
T96 /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.316101947 Jul 18 04:45:35 PM PDT 24 Jul 18 05:18:05 PM PDT 24 336814270000 ps
T97 /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.2384794128 Jul 18 04:45:35 PM PDT 24 Jul 18 05:21:05 PM PDT 24 336562810000 ps
T98 /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.2485393639 Jul 18 04:45:42 PM PDT 24 Jul 18 05:25:13 PM PDT 24 336611210000 ps
T99 /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.27793523 Jul 18 04:45:39 PM PDT 24 Jul 18 05:12:58 PM PDT 24 336816330000 ps
T100 /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.3140788537 Jul 18 04:45:43 PM PDT 24 Jul 18 05:22:19 PM PDT 24 336940470000 ps
T101 /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.837809131 Jul 18 04:45:41 PM PDT 24 Jul 18 05:16:47 PM PDT 24 336616990000 ps
T102 /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.1724135108 Jul 18 04:45:34 PM PDT 24 Jul 18 05:19:51 PM PDT 24 337010910000 ps
T103 /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.730313527 Jul 18 04:45:39 PM PDT 24 Jul 18 05:21:47 PM PDT 24 336686950000 ps
T104 /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.3602196787 Jul 18 04:45:36 PM PDT 24 Jul 18 05:24:18 PM PDT 24 336642610000 ps
T105 /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.314392223 Jul 18 04:45:35 PM PDT 24 Jul 18 05:27:08 PM PDT 24 336390090000 ps
T106 /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.426829899 Jul 18 04:45:38 PM PDT 24 Jul 18 05:20:40 PM PDT 24 336546050000 ps
T107 /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.3331578187 Jul 18 04:45:39 PM PDT 24 Jul 18 05:20:52 PM PDT 24 337167350000 ps
T108 /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.1349242074 Jul 18 04:45:39 PM PDT 24 Jul 18 05:21:11 PM PDT 24 336944570000 ps
T109 /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.3208402431 Jul 18 04:45:39 PM PDT 24 Jul 18 05:30:19 PM PDT 24 336926910000 ps
T110 /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.2911383049 Jul 18 04:45:37 PM PDT 24 Jul 18 05:23:00 PM PDT 24 336524150000 ps
T111 /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.2048649915 Jul 18 05:53:54 PM PDT 24 Jul 18 05:54:02 PM PDT 24 1409950000 ps
T112 /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.4221224768 Jul 18 05:36:07 PM PDT 24 Jul 18 05:36:19 PM PDT 24 1141390000 ps
T113 /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.2688352641 Jul 18 05:36:07 PM PDT 24 Jul 18 05:36:21 PM PDT 24 1575070000 ps
T114 /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.3088462716 Jul 18 05:36:08 PM PDT 24 Jul 18 05:36:20 PM PDT 24 1117310000 ps
T115 /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.2508437251 Jul 18 05:36:02 PM PDT 24 Jul 18 05:36:13 PM PDT 24 1507390000 ps
T116 /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.1594906710 Jul 18 05:36:05 PM PDT 24 Jul 18 05:36:18 PM PDT 24 1600230000 ps
T117 /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3876849857 Jul 18 05:36:06 PM PDT 24 Jul 18 05:36:21 PM PDT 24 1412990000 ps
T118 /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.4088715939 Jul 18 05:36:05 PM PDT 24 Jul 18 05:36:18 PM PDT 24 1550070000 ps
T119 /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2242048709 Jul 18 05:36:05 PM PDT 24 Jul 18 05:36:17 PM PDT 24 1481390000 ps
T120 /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.3816829556 Jul 18 05:36:08 PM PDT 24 Jul 18 05:36:21 PM PDT 24 1301650000 ps
T121 /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.2197665532 Jul 18 05:36:05 PM PDT 24 Jul 18 05:36:19 PM PDT 24 1454530000 ps
T122 /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.4146782455 Jul 18 05:36:05 PM PDT 24 Jul 18 05:36:17 PM PDT 24 1515510000 ps
T123 /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.2616920895 Jul 18 05:36:08 PM PDT 24 Jul 18 05:36:25 PM PDT 24 1459970000 ps
T124 /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.2624314070 Jul 18 05:36:03 PM PDT 24 Jul 18 05:36:15 PM PDT 24 1538130000 ps
T125 /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3592770209 Jul 18 05:36:06 PM PDT 24 Jul 18 05:36:18 PM PDT 24 1544990000 ps
T126 /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.246385459 Jul 18 05:36:04 PM PDT 24 Jul 18 05:36:17 PM PDT 24 1575750000 ps
T127 /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.3562687622 Jul 18 05:36:04 PM PDT 24 Jul 18 05:36:16 PM PDT 24 1476010000 ps
T128 /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.4195679656 Jul 18 05:36:07 PM PDT 24 Jul 18 05:36:21 PM PDT 24 1526770000 ps
T129 /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.2576964161 Jul 18 05:36:03 PM PDT 24 Jul 18 05:36:17 PM PDT 24 1543450000 ps
T130 /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.1775337470 Jul 18 05:36:03 PM PDT 24 Jul 18 05:36:17 PM PDT 24 1332050000 ps
T131 /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.2669151032 Jul 18 05:36:08 PM PDT 24 Jul 18 05:36:22 PM PDT 24 1301510000 ps
T132 /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.2180284982 Jul 18 05:36:08 PM PDT 24 Jul 18 05:36:21 PM PDT 24 1473630000 ps
T133 /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.3402075259 Jul 18 05:36:12 PM PDT 24 Jul 18 05:36:28 PM PDT 24 1353830000 ps
T134 /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.770297888 Jul 18 05:36:08 PM PDT 24 Jul 18 05:36:22 PM PDT 24 1206990000 ps
T135 /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.611416181 Jul 18 05:36:06 PM PDT 24 Jul 18 05:36:19 PM PDT 24 1501690000 ps
T136 /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.2680122332 Jul 18 05:36:08 PM PDT 24 Jul 18 05:36:23 PM PDT 24 1472150000 ps
T137 /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.2722118821 Jul 18 05:36:06 PM PDT 24 Jul 18 05:36:22 PM PDT 24 1442510000 ps
T138 /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.2613087625 Jul 18 05:36:02 PM PDT 24 Jul 18 05:36:14 PM PDT 24 1612430000 ps
T139 /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.2677308789 Jul 18 05:36:05 PM PDT 24 Jul 18 05:36:18 PM PDT 24 1537370000 ps
T140 /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.2310421645 Jul 18 05:36:07 PM PDT 24 Jul 18 05:36:21 PM PDT 24 1559190000 ps
T141 /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.2265600631 Jul 18 05:36:05 PM PDT 24 Jul 18 05:36:16 PM PDT 24 1394730000 ps
T142 /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.1847164190 Jul 18 05:36:12 PM PDT 24 Jul 18 05:36:28 PM PDT 24 1448890000 ps
T143 /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.1204068861 Jul 18 05:36:06 PM PDT 24 Jul 18 05:36:21 PM PDT 24 1537510000 ps
T144 /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.1840868505 Jul 18 05:36:11 PM PDT 24 Jul 18 05:36:26 PM PDT 24 1400570000 ps
T145 /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.686457697 Jul 18 05:36:11 PM PDT 24 Jul 18 05:36:26 PM PDT 24 1377190000 ps
T146 /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.3561301897 Jul 18 05:36:06 PM PDT 24 Jul 18 05:36:20 PM PDT 24 1548790000 ps
T147 /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.1105165243 Jul 18 05:36:07 PM PDT 24 Jul 18 05:36:21 PM PDT 24 1183090000 ps
T148 /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.2225848640 Jul 18 05:36:13 PM PDT 24 Jul 18 05:36:29 PM PDT 24 1425450000 ps
T149 /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.1401383263 Jul 18 05:36:08 PM PDT 24 Jul 18 05:36:21 PM PDT 24 1501410000 ps
T150 /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.1240899933 Jul 18 05:36:20 PM PDT 24 Jul 18 05:36:35 PM PDT 24 1490610000 ps
T151 /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.1590574383 Jul 18 05:36:16 PM PDT 24 Jul 18 05:36:34 PM PDT 24 1495250000 ps
T152 /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.3625091524 Jul 18 05:36:07 PM PDT 24 Jul 18 05:36:20 PM PDT 24 1491230000 ps
T153 /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.417268122 Jul 18 05:36:09 PM PDT 24 Jul 18 05:36:24 PM PDT 24 1396670000 ps
T154 /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.2469375246 Jul 18 05:36:09 PM PDT 24 Jul 18 05:36:23 PM PDT 24 1274130000 ps
T155 /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1889884409 Jul 18 05:36:09 PM PDT 24 Jul 18 05:36:34 PM PDT 24 1464610000 ps
T156 /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.505229981 Jul 18 05:36:07 PM PDT 24 Jul 18 05:36:19 PM PDT 24 1345230000 ps
T157 /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.902266453 Jul 18 05:36:07 PM PDT 24 Jul 18 05:36:23 PM PDT 24 1383870000 ps
T158 /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.3445158136 Jul 18 05:36:05 PM PDT 24 Jul 18 05:36:15 PM PDT 24 1550350000 ps
T159 /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.4241115264 Jul 18 05:36:05 PM PDT 24 Jul 18 05:36:17 PM PDT 24 1416990000 ps
T160 /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.420308509 Jul 18 05:36:05 PM PDT 24 Jul 18 05:36:17 PM PDT 24 1496690000 ps
T21 /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.3375694510 Jul 18 04:46:38 PM PDT 24 Jul 18 05:22:48 PM PDT 24 337182110000 ps
T22 /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.1832162205 Jul 18 04:46:36 PM PDT 24 Jul 18 05:20:28 PM PDT 24 337166030000 ps
T23 /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.316059161 Jul 18 04:46:38 PM PDT 24 Jul 18 05:21:57 PM PDT 24 336344050000 ps
T24 /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.1761693371 Jul 18 04:46:37 PM PDT 24 Jul 18 05:18:18 PM PDT 24 337033810000 ps
T25 /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.106228698 Jul 18 04:46:37 PM PDT 24 Jul 18 05:27:58 PM PDT 24 336359470000 ps
T26 /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.250481170 Jul 18 04:46:37 PM PDT 24 Jul 18 05:21:16 PM PDT 24 337013590000 ps
T27 /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.462092093 Jul 18 04:46:35 PM PDT 24 Jul 18 05:20:53 PM PDT 24 336577350000 ps
T28 /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.3510793541 Jul 18 04:46:35 PM PDT 24 Jul 18 05:26:40 PM PDT 24 336930570000 ps
T29 /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.1827737731 Jul 18 04:46:41 PM PDT 24 Jul 18 05:23:02 PM PDT 24 336398510000 ps
T30 /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.2868416674 Jul 18 04:46:36 PM PDT 24 Jul 18 05:22:38 PM PDT 24 336586530000 ps
T161 /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.4187175458 Jul 18 04:46:38 PM PDT 24 Jul 18 05:22:45 PM PDT 24 336792130000 ps
T162 /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.2128755038 Jul 18 04:46:35 PM PDT 24 Jul 18 05:21:26 PM PDT 24 336519850000 ps
T163 /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.2887824089 Jul 18 04:46:37 PM PDT 24 Jul 18 05:20:35 PM PDT 24 336870930000 ps
T164 /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.190181937 Jul 18 04:56:22 PM PDT 24 Jul 18 05:32:18 PM PDT 24 337089070000 ps
T165 /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.1153622195 Jul 18 04:46:31 PM PDT 24 Jul 18 05:16:19 PM PDT 24 336977250000 ps
T166 /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.280885597 Jul 18 04:46:36 PM PDT 24 Jul 18 05:30:34 PM PDT 24 336914330000 ps
T167 /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.853801015 Jul 18 04:46:40 PM PDT 24 Jul 18 05:27:08 PM PDT 24 336793110000 ps
T168 /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.749259267 Jul 18 04:46:40 PM PDT 24 Jul 18 05:25:22 PM PDT 24 336692530000 ps
T169 /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.2534297789 Jul 18 04:46:38 PM PDT 24 Jul 18 05:20:23 PM PDT 24 336428310000 ps
T170 /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.2038438948 Jul 18 04:46:40 PM PDT 24 Jul 18 05:22:30 PM PDT 24 336339910000 ps
T171 /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.3871620361 Jul 18 04:46:38 PM PDT 24 Jul 18 05:21:58 PM PDT 24 337140970000 ps
T172 /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.2509308254 Jul 18 04:46:41 PM PDT 24 Jul 18 05:23:23 PM PDT 24 336351230000 ps
T173 /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.1229189955 Jul 18 04:46:25 PM PDT 24 Jul 18 05:19:23 PM PDT 24 336719610000 ps
T174 /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.3963220272 Jul 18 04:46:40 PM PDT 24 Jul 18 05:27:15 PM PDT 24 337067270000 ps
T175 /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.1016464909 Jul 18 04:46:38 PM PDT 24 Jul 18 05:20:11 PM PDT 24 337003950000 ps
T176 /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.1782530553 Jul 18 04:46:38 PM PDT 24 Jul 18 05:18:05 PM PDT 24 336977570000 ps
T177 /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.3494803622 Jul 18 04:46:36 PM PDT 24 Jul 18 05:18:37 PM PDT 24 336528350000 ps
T178 /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.307530741 Jul 18 04:46:37 PM PDT 24 Jul 18 05:23:20 PM PDT 24 336856470000 ps
T179 /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.2412133993 Jul 18 04:46:38 PM PDT 24 Jul 18 05:22:34 PM PDT 24 336494310000 ps
T180 /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.4261152711 Jul 18 04:46:38 PM PDT 24 Jul 18 05:30:51 PM PDT 24 336363870000 ps
T181 /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.3915404068 Jul 18 04:46:39 PM PDT 24 Jul 18 05:21:59 PM PDT 24 336693670000 ps
T182 /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.3634499798 Jul 18 04:46:38 PM PDT 24 Jul 18 05:29:32 PM PDT 24 336860790000 ps
T183 /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.2029360178 Jul 18 04:46:38 PM PDT 24 Jul 18 05:25:36 PM PDT 24 336923490000 ps
T184 /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.531669591 Jul 18 04:46:36 PM PDT 24 Jul 18 05:20:06 PM PDT 24 336889250000 ps
T185 /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.1840932751 Jul 18 04:46:38 PM PDT 24 Jul 18 05:23:50 PM PDT 24 336953210000 ps
T186 /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.3404225937 Jul 18 04:46:41 PM PDT 24 Jul 18 05:26:07 PM PDT 24 336829110000 ps
T187 /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.694496321 Jul 18 04:46:37 PM PDT 24 Jul 18 05:30:23 PM PDT 24 336992730000 ps
T188 /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.781401705 Jul 18 04:46:37 PM PDT 24 Jul 18 05:25:37 PM PDT 24 336613410000 ps
T189 /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.3280208661 Jul 18 04:46:38 PM PDT 24 Jul 18 05:29:25 PM PDT 24 337079850000 ps
T190 /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.2926659087 Jul 18 04:46:38 PM PDT 24 Jul 18 05:22:01 PM PDT 24 336672470000 ps
T191 /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.2358307812 Jul 18 04:46:38 PM PDT 24 Jul 18 05:21:16 PM PDT 24 337011830000 ps
T192 /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.2932997595 Jul 18 04:46:37 PM PDT 24 Jul 18 05:24:23 PM PDT 24 336380490000 ps
T193 /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.1229848164 Jul 18 04:46:20 PM PDT 24 Jul 18 05:29:10 PM PDT 24 337131770000 ps
T194 /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.164264904 Jul 18 04:46:36 PM PDT 24 Jul 18 05:24:41 PM PDT 24 336628650000 ps
T195 /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.1612356122 Jul 18 04:46:37 PM PDT 24 Jul 18 05:21:12 PM PDT 24 336470150000 ps
T196 /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.3917913658 Jul 18 04:46:19 PM PDT 24 Jul 18 05:29:10 PM PDT 24 336554910000 ps
T197 /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.903416946 Jul 18 04:46:37 PM PDT 24 Jul 18 05:18:50 PM PDT 24 336353130000 ps
T198 /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.1264946033 Jul 18 04:46:34 PM PDT 24 Jul 18 05:24:22 PM PDT 24 336585670000 ps
T199 /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.2155602184 Jul 18 04:46:37 PM PDT 24 Jul 18 05:28:14 PM PDT 24 336640330000 ps
T200 /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.1175356970 Jul 18 04:46:40 PM PDT 24 Jul 18 05:22:27 PM PDT 24 336334110000 ps

Test location /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.1544060837
Short name T3
Test name
Test status
Simulation time 1364670000 ps
CPU time 5.35 seconds
Started Jul 18 04:45:42 PM PDT 24
Finished Jul 18 04:45:59 PM PDT 24
Peak memory 164784 kb
Host smart-7e8f226a-108d-4d10-844a-63a9c08c918c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1544060837 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.1544060837
Directory /workspace/10.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.1981042014
Short name T4
Test name
Test status
Simulation time 336903250000 ps
CPU time 748.4 seconds
Started Jul 18 04:45:38 PM PDT 24
Finished Jul 18 05:16:10 PM PDT 24
Peak memory 160708 kb
Host smart-30bf4289-d758-4b69-b5dc-3ff92c48dee3
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1981042014 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.1981042014
Directory /workspace/14.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.3510793541
Short name T28
Test name
Test status
Simulation time 336930570000 ps
CPU time 952.72 seconds
Started Jul 18 04:46:35 PM PDT 24
Finished Jul 18 05:26:40 PM PDT 24
Peak memory 160712 kb
Host smart-d8280a63-a2eb-4444-a729-90fbefbfdd9f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3510793541 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.3510793541
Directory /workspace/10.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.1095731431
Short name T84
Test name
Test status
Simulation time 336512290000 ps
CPU time 965.19 seconds
Started Jul 18 04:45:40 PM PDT 24
Finished Jul 18 05:26:05 PM PDT 24
Peak memory 160692 kb
Host smart-0210e169-100d-439e-916b-a7a5f8f5dc2d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1095731431 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.1095731431
Directory /workspace/0.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.2225466716
Short name T78
Test name
Test status
Simulation time 336977950000 ps
CPU time 808.04 seconds
Started Jul 18 04:45:37 PM PDT 24
Finished Jul 18 05:18:45 PM PDT 24
Peak memory 160704 kb
Host smart-fd74e2e2-4c99-42c1-b59a-62ce011ba284
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2225466716 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.2225466716
Directory /workspace/1.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.4249722346
Short name T73
Test name
Test status
Simulation time 336966050000 ps
CPU time 1062.52 seconds
Started Jul 18 04:45:39 PM PDT 24
Finished Jul 18 05:29:57 PM PDT 24
Peak memory 160736 kb
Host smart-652c4e0b-4523-4c35-9b74-c95f30824f08
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4249722346 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.4249722346
Directory /workspace/10.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.168099713
Short name T82
Test name
Test status
Simulation time 337058350000 ps
CPU time 969.53 seconds
Started Jul 18 04:45:42 PM PDT 24
Finished Jul 18 05:25:43 PM PDT 24
Peak memory 160616 kb
Host smart-4fb1fe1e-3229-4fc3-b9b0-dd39b57534f8
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=168099713 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.168099713
Directory /workspace/11.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.730313527
Short name T103
Test name
Test status
Simulation time 336686950000 ps
CPU time 862.92 seconds
Started Jul 18 04:45:39 PM PDT 24
Finished Jul 18 05:21:47 PM PDT 24
Peak memory 160692 kb
Host smart-f698f9d9-85c6-42e9-81de-14e44a0b3032
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=730313527 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.730313527
Directory /workspace/12.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.314392223
Short name T105
Test name
Test status
Simulation time 336390090000 ps
CPU time 959.93 seconds
Started Jul 18 04:45:35 PM PDT 24
Finished Jul 18 05:27:08 PM PDT 24
Peak memory 160704 kb
Host smart-fa01491c-c765-48fa-9eb5-73800c93c1e3
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=314392223 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.314392223
Directory /workspace/13.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.3140788537
Short name T100
Test name
Test status
Simulation time 336940470000 ps
CPU time 890.15 seconds
Started Jul 18 04:45:43 PM PDT 24
Finished Jul 18 05:22:19 PM PDT 24
Peak memory 160708 kb
Host smart-cf0613ed-369e-4fab-a5e6-25ef9eafdff3
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3140788537 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.3140788537
Directory /workspace/15.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.1504939686
Short name T85
Test name
Test status
Simulation time 336679050000 ps
CPU time 908.28 seconds
Started Jul 18 04:45:42 PM PDT 24
Finished Jul 18 05:22:38 PM PDT 24
Peak memory 160708 kb
Host smart-fbc27590-f2b2-4b38-b54b-bac759392d02
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1504939686 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.1504939686
Directory /workspace/16.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.780347494
Short name T77
Test name
Test status
Simulation time 336747610000 ps
CPU time 1042.03 seconds
Started Jul 18 04:45:39 PM PDT 24
Finished Jul 18 05:29:40 PM PDT 24
Peak memory 160864 kb
Host smart-abb70dcd-d0dd-402b-a8e1-8f8916bbcac7
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=780347494 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.780347494
Directory /workspace/17.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.853959607
Short name T6
Test name
Test status
Simulation time 336802690000 ps
CPU time 761.16 seconds
Started Jul 18 04:45:39 PM PDT 24
Finished Jul 18 05:17:06 PM PDT 24
Peak memory 160692 kb
Host smart-e8ddfebc-9c9d-419d-9f3d-249605138291
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=853959607 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.853959607
Directory /workspace/18.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.1814730390
Short name T93
Test name
Test status
Simulation time 336470110000 ps
CPU time 960.16 seconds
Started Jul 18 04:45:40 PM PDT 24
Finished Jul 18 05:26:07 PM PDT 24
Peak memory 160696 kb
Host smart-767d2d7d-fc04-4204-9bb2-2f9541b8ddcf
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1814730390 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.1814730390
Directory /workspace/19.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.2902023820
Short name T87
Test name
Test status
Simulation time 336814590000 ps
CPU time 826.44 seconds
Started Jul 18 04:45:39 PM PDT 24
Finished Jul 18 05:19:56 PM PDT 24
Peak memory 160600 kb
Host smart-a72511fd-0761-4b3f-840e-ac539a3f1bbb
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2902023820 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.2902023820
Directory /workspace/2.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.837809131
Short name T101
Test name
Test status
Simulation time 336616990000 ps
CPU time 762.8 seconds
Started Jul 18 04:45:41 PM PDT 24
Finished Jul 18 05:16:47 PM PDT 24
Peak memory 160748 kb
Host smart-f6065196-60b0-4b26-8ce4-c4514546c0d5
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=837809131 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.837809131
Directory /workspace/20.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.1469219010
Short name T20
Test name
Test status
Simulation time 336474610000 ps
CPU time 837.35 seconds
Started Jul 18 04:45:38 PM PDT 24
Finished Jul 18 05:19:40 PM PDT 24
Peak memory 160708 kb
Host smart-fccf3d33-38e0-4cd0-b6df-51352aed78e3
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1469219010 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.1469219010
Directory /workspace/21.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.1474527198
Short name T94
Test name
Test status
Simulation time 336708030000 ps
CPU time 914.51 seconds
Started Jul 18 04:45:37 PM PDT 24
Finished Jul 18 05:23:23 PM PDT 24
Peak memory 160672 kb
Host smart-a30dbb41-29d3-48af-981a-fd0f43a612d4
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1474527198 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.1474527198
Directory /workspace/22.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.3948966510
Short name T88
Test name
Test status
Simulation time 336370450000 ps
CPU time 795.36 seconds
Started Jul 18 04:45:39 PM PDT 24
Finished Jul 18 05:17:44 PM PDT 24
Peak memory 160748 kb
Host smart-953723c9-3f86-42b3-ac45-92cbbc923dcd
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3948966510 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.3948966510
Directory /workspace/23.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.637485423
Short name T90
Test name
Test status
Simulation time 336950050000 ps
CPU time 982.03 seconds
Started Jul 18 04:45:40 PM PDT 24
Finished Jul 18 05:26:16 PM PDT 24
Peak memory 160700 kb
Host smart-0e36c711-8dfa-4da4-b09b-efeefa4842eb
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=637485423 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.637485423
Directory /workspace/24.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.27793523
Short name T99
Test name
Test status
Simulation time 336816330000 ps
CPU time 649.69 seconds
Started Jul 18 04:45:39 PM PDT 24
Finished Jul 18 05:12:58 PM PDT 24
Peak memory 160708 kb
Host smart-1bfce1cb-03aa-4e20-86be-7c3dc13a73fe
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=27793523 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.27793523
Directory /workspace/25.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1466173754
Short name T16
Test name
Test status
Simulation time 336548290000 ps
CPU time 934.97 seconds
Started Jul 18 04:45:36 PM PDT 24
Finished Jul 18 05:24:33 PM PDT 24
Peak memory 160724 kb
Host smart-41b6fe8a-ae39-424d-af0f-75bc1acf048f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1466173754 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.1466173754
Directory /workspace/26.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.3602196787
Short name T104
Test name
Test status
Simulation time 336642610000 ps
CPU time 934.74 seconds
Started Jul 18 04:45:36 PM PDT 24
Finished Jul 18 05:24:18 PM PDT 24
Peak memory 160724 kb
Host smart-ac10e10d-5c3d-4509-8094-34a2730c2a04
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3602196787 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.3602196787
Directory /workspace/27.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.858714295
Short name T72
Test name
Test status
Simulation time 336780350000 ps
CPU time 862.16 seconds
Started Jul 18 04:45:39 PM PDT 24
Finished Jul 18 05:21:31 PM PDT 24
Peak memory 160720 kb
Host smart-93a0d27d-dd11-42ac-83d0-ca453af5bfd5
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=858714295 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.858714295
Directory /workspace/28.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.764727841
Short name T79
Test name
Test status
Simulation time 337002170000 ps
CPU time 914.95 seconds
Started Jul 18 04:45:43 PM PDT 24
Finished Jul 18 05:22:58 PM PDT 24
Peak memory 160708 kb
Host smart-82866911-f6dc-4e51-b252-f6ebc9498512
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=764727841 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.764727841
Directory /workspace/29.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.502245561
Short name T71
Test name
Test status
Simulation time 337087670000 ps
CPU time 937.93 seconds
Started Jul 18 04:45:37 PM PDT 24
Finished Jul 18 05:26:56 PM PDT 24
Peak memory 160700 kb
Host smart-1e4e0c91-86e8-4db8-ba52-647d2b793591
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=502245561 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.502245561
Directory /workspace/3.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.2384794128
Short name T97
Test name
Test status
Simulation time 336562810000 ps
CPU time 880.74 seconds
Started Jul 18 04:45:35 PM PDT 24
Finished Jul 18 05:21:05 PM PDT 24
Peak memory 160740 kb
Host smart-63389fe8-9434-4819-a81f-8ddf0e53b0a4
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2384794128 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.2384794128
Directory /workspace/30.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.545329398
Short name T81
Test name
Test status
Simulation time 336510890000 ps
CPU time 860.88 seconds
Started Jul 18 04:45:39 PM PDT 24
Finished Jul 18 05:21:44 PM PDT 24
Peak memory 160720 kb
Host smart-cf9c3742-0140-4558-942f-3cf274047493
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=545329398 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.545329398
Directory /workspace/31.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.3208402431
Short name T109
Test name
Test status
Simulation time 336926910000 ps
CPU time 1061.88 seconds
Started Jul 18 04:45:39 PM PDT 24
Finished Jul 18 05:30:19 PM PDT 24
Peak memory 160736 kb
Host smart-14d2377b-3fcf-47e9-b530-b91567987a0f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3208402431 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.3208402431
Directory /workspace/32.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.426829899
Short name T106
Test name
Test status
Simulation time 336546050000 ps
CPU time 831.48 seconds
Started Jul 18 04:45:38 PM PDT 24
Finished Jul 18 05:20:40 PM PDT 24
Peak memory 159908 kb
Host smart-a9c6b879-bb57-4ff4-ad6c-d6c7170d87ed
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=426829899 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.426829899
Directory /workspace/33.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.2139265150
Short name T80
Test name
Test status
Simulation time 336883370000 ps
CPU time 784.67 seconds
Started Jul 18 04:45:37 PM PDT 24
Finished Jul 18 05:17:26 PM PDT 24
Peak memory 160748 kb
Host smart-46db23cf-5abb-4b6b-aaf0-4ce79dbed08a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2139265150 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.2139265150
Directory /workspace/34.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.1768131956
Short name T89
Test name
Test status
Simulation time 337065410000 ps
CPU time 829.37 seconds
Started Jul 18 04:45:40 PM PDT 24
Finished Jul 18 05:19:10 PM PDT 24
Peak memory 160728 kb
Host smart-3a3a6695-d4ed-4992-926e-c4fb15999cfe
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1768131956 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.1768131956
Directory /workspace/35.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.3331578187
Short name T107
Test name
Test status
Simulation time 337167350000 ps
CPU time 838.44 seconds
Started Jul 18 04:45:39 PM PDT 24
Finished Jul 18 05:20:52 PM PDT 24
Peak memory 160740 kb
Host smart-8e043241-b4fc-49e7-8764-69d1e385a6f5
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3331578187 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.3331578187
Directory /workspace/36.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.2080145860
Short name T5
Test name
Test status
Simulation time 336374650000 ps
CPU time 913.71 seconds
Started Jul 18 04:45:37 PM PDT 24
Finished Jul 18 05:23:28 PM PDT 24
Peak memory 160672 kb
Host smart-4d71d204-766c-46ab-89cc-dac9a4ef8ed4
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2080145860 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.2080145860
Directory /workspace/37.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.1230417176
Short name T15
Test name
Test status
Simulation time 336668990000 ps
CPU time 843.26 seconds
Started Jul 18 04:45:39 PM PDT 24
Finished Jul 18 05:20:16 PM PDT 24
Peak memory 160604 kb
Host smart-3497b3a8-4713-474e-9471-6a6c6764686f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1230417176 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.1230417176
Directory /workspace/38.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.1643753994
Short name T83
Test name
Test status
Simulation time 336356830000 ps
CPU time 1059.21 seconds
Started Jul 18 04:45:42 PM PDT 24
Finished Jul 18 05:30:14 PM PDT 24
Peak memory 160736 kb
Host smart-fdcd8f55-b52b-43cc-bb95-7aa050cc8bea
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1643753994 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.1643753994
Directory /workspace/39.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.2911383049
Short name T110
Test name
Test status
Simulation time 336524150000 ps
CPU time 891.07 seconds
Started Jul 18 04:45:37 PM PDT 24
Finished Jul 18 05:23:00 PM PDT 24
Peak memory 160636 kb
Host smart-a1d2850a-fdf8-4b8f-80e5-458c325e4972
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2911383049 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.2911383049
Directory /workspace/4.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.1724135108
Short name T102
Test name
Test status
Simulation time 337010910000 ps
CPU time 837.39 seconds
Started Jul 18 04:45:34 PM PDT 24
Finished Jul 18 05:19:51 PM PDT 24
Peak memory 160728 kb
Host smart-c1d303bb-bcda-4f09-ac0f-1b781ee98304
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1724135108 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.1724135108
Directory /workspace/40.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.316101947
Short name T96
Test name
Test status
Simulation time 336814270000 ps
CPU time 803.44 seconds
Started Jul 18 04:45:35 PM PDT 24
Finished Jul 18 05:18:05 PM PDT 24
Peak memory 160696 kb
Host smart-c4bae1ad-5113-4db2-a33d-ce92d8c8f6b9
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=316101947 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.316101947
Directory /workspace/41.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.2661079505
Short name T74
Test name
Test status
Simulation time 336448630000 ps
CPU time 876.54 seconds
Started Jul 18 04:45:38 PM PDT 24
Finished Jul 18 05:21:50 PM PDT 24
Peak memory 160728 kb
Host smart-c3307e25-48eb-495f-ab17-51fec8c54644
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2661079505 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.2661079505
Directory /workspace/42.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.18018433
Short name T95
Test name
Test status
Simulation time 337160590000 ps
CPU time 1049.11 seconds
Started Jul 18 04:45:39 PM PDT 24
Finished Jul 18 05:29:50 PM PDT 24
Peak memory 160864 kb
Host smart-3c348350-e459-4932-bb5e-14fb46889a32
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=18018433 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.18018433
Directory /workspace/43.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.1986029728
Short name T91
Test name
Test status
Simulation time 336723670000 ps
CPU time 1057.62 seconds
Started Jul 18 04:45:38 PM PDT 24
Finished Jul 18 05:29:34 PM PDT 24
Peak memory 160872 kb
Host smart-aa5e68db-7580-446a-8a02-fff71f3359a8
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1986029728 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.1986029728
Directory /workspace/44.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.2485393639
Short name T98
Test name
Test status
Simulation time 336611210000 ps
CPU time 953.35 seconds
Started Jul 18 04:45:42 PM PDT 24
Finished Jul 18 05:25:13 PM PDT 24
Peak memory 160716 kb
Host smart-4559027c-886a-4580-b283-ad2772632d6f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2485393639 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.2485393639
Directory /workspace/45.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.3798845574
Short name T76
Test name
Test status
Simulation time 336345470000 ps
CPU time 849.17 seconds
Started Jul 18 04:45:34 PM PDT 24
Finished Jul 18 05:20:46 PM PDT 24
Peak memory 160700 kb
Host smart-e8d893fa-704b-4b74-adcb-74fd65e6ecb2
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3798845574 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.3798845574
Directory /workspace/46.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.881076899
Short name T14
Test name
Test status
Simulation time 336573770000 ps
CPU time 1037.2 seconds
Started Jul 18 04:45:38 PM PDT 24
Finished Jul 18 05:29:12 PM PDT 24
Peak memory 160740 kb
Host smart-51e89ad8-ec58-4f75-a3d5-0a0ddbd5ae65
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=881076899 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.881076899
Directory /workspace/47.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.654945040
Short name T18
Test name
Test status
Simulation time 336571510000 ps
CPU time 835.06 seconds
Started Jul 18 04:45:38 PM PDT 24
Finished Jul 18 05:20:45 PM PDT 24
Peak memory 160172 kb
Host smart-52ff17e0-de7c-4931-945e-099c67f66c8e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=654945040 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.654945040
Directory /workspace/48.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.3944264367
Short name T92
Test name
Test status
Simulation time 337049430000 ps
CPU time 809.52 seconds
Started Jul 18 04:45:38 PM PDT 24
Finished Jul 18 05:20:00 PM PDT 24
Peak memory 160748 kb
Host smart-03304fc9-8f29-44b2-9a8f-9415cbd404b3
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3944264367 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.3944264367
Directory /workspace/49.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.819922015
Short name T17
Test name
Test status
Simulation time 336524770000 ps
CPU time 710.26 seconds
Started Jul 18 04:45:39 PM PDT 24
Finished Jul 18 05:14:50 PM PDT 24
Peak memory 160708 kb
Host smart-80e37bbe-9180-4491-bd32-3e301ed72689
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=819922015 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.819922015
Directory /workspace/5.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.1349242074
Short name T108
Test name
Test status
Simulation time 336944570000 ps
CPU time 851.78 seconds
Started Jul 18 04:45:39 PM PDT 24
Finished Jul 18 05:21:11 PM PDT 24
Peak memory 160720 kb
Host smart-e400510d-54e6-4f3b-9f85-6c1100a7dd75
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1349242074 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.1349242074
Directory /workspace/6.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.479715075
Short name T86
Test name
Test status
Simulation time 336343890000 ps
CPU time 916.36 seconds
Started Jul 18 04:45:40 PM PDT 24
Finished Jul 18 05:23:01 PM PDT 24
Peak memory 160700 kb
Host smart-e98257a9-4ed6-4180-a9ad-364cd8524252
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=479715075 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.479715075
Directory /workspace/7.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.6996384
Short name T19
Test name
Test status
Simulation time 336408170000 ps
CPU time 949.4 seconds
Started Jul 18 04:45:42 PM PDT 24
Finished Jul 18 05:25:25 PM PDT 24
Peak memory 160772 kb
Host smart-5bab895c-5298-4fad-bf73-dd73fe01d900
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=6996384 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.6996384
Directory /workspace/8.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.3692704536
Short name T75
Test name
Test status
Simulation time 336245610000 ps
CPU time 848.57 seconds
Started Jul 18 04:45:40 PM PDT 24
Finished Jul 18 05:20:43 PM PDT 24
Peak memory 160716 kb
Host smart-f4e62532-d9f1-4a50-a576-9a3ca684a065
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3692704536 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.3692704536
Directory /workspace/9.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.1229189955
Short name T173
Test name
Test status
Simulation time 336719610000 ps
CPU time 810.42 seconds
Started Jul 18 04:46:25 PM PDT 24
Finished Jul 18 05:19:23 PM PDT 24
Peak memory 160708 kb
Host smart-70e4b98c-2530-45e8-8361-daf4be160885
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1229189955 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.1229189955
Directory /workspace/0.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.1229848164
Short name T193
Test name
Test status
Simulation time 337131770000 ps
CPU time 1021.75 seconds
Started Jul 18 04:46:20 PM PDT 24
Finished Jul 18 05:29:10 PM PDT 24
Peak memory 160744 kb
Host smart-bded5ae0-9532-4d7c-82bb-71940797c480
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1229848164 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.1229848164
Directory /workspace/1.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.2926659087
Short name T190
Test name
Test status
Simulation time 336672470000 ps
CPU time 856.51 seconds
Started Jul 18 04:46:38 PM PDT 24
Finished Jul 18 05:22:01 PM PDT 24
Peak memory 160344 kb
Host smart-75119df7-971e-4188-a485-7643e391aec5
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2926659087 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.2926659087
Directory /workspace/11.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.307530741
Short name T178
Test name
Test status
Simulation time 336856470000 ps
CPU time 895.87 seconds
Started Jul 18 04:46:37 PM PDT 24
Finished Jul 18 05:23:20 PM PDT 24
Peak memory 160732 kb
Host smart-fb60e53f-6be9-49b3-95c6-7f02ef527929
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=307530741 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.307530741
Directory /workspace/12.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.1782530553
Short name T176
Test name
Test status
Simulation time 336977570000 ps
CPU time 770.85 seconds
Started Jul 18 04:46:38 PM PDT 24
Finished Jul 18 05:18:05 PM PDT 24
Peak memory 160648 kb
Host smart-3105925f-879d-438f-a619-2221458ee44a
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1782530553 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.1782530553
Directory /workspace/13.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.1175356970
Short name T200
Test name
Test status
Simulation time 336334110000 ps
CPU time 859.63 seconds
Started Jul 18 04:46:40 PM PDT 24
Finished Jul 18 05:22:27 PM PDT 24
Peak memory 160732 kb
Host smart-d0db236f-8060-4d21-8061-57cf2b139a0a
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1175356970 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.1175356970
Directory /workspace/14.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.2029360178
Short name T183
Test name
Test status
Simulation time 336923490000 ps
CPU time 935.08 seconds
Started Jul 18 04:46:38 PM PDT 24
Finished Jul 18 05:25:36 PM PDT 24
Peak memory 160728 kb
Host smart-f3db9c9f-0e7a-458f-98a1-45af5eab0020
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2029360178 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.2029360178
Directory /workspace/15.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.1761693371
Short name T24
Test name
Test status
Simulation time 337033810000 ps
CPU time 776.07 seconds
Started Jul 18 04:46:37 PM PDT 24
Finished Jul 18 05:18:18 PM PDT 24
Peak memory 160648 kb
Host smart-f64e6fc6-e20f-4a25-afb1-579715fca8b5
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1761693371 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.1761693371
Directory /workspace/16.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.1016464909
Short name T175
Test name
Test status
Simulation time 337003950000 ps
CPU time 805.43 seconds
Started Jul 18 04:46:38 PM PDT 24
Finished Jul 18 05:20:11 PM PDT 24
Peak memory 160712 kb
Host smart-105daf35-3e3c-4095-913b-a28f10d9e4e3
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1016464909 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.1016464909
Directory /workspace/17.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.2868416674
Short name T30
Test name
Test status
Simulation time 336586530000 ps
CPU time 864.37 seconds
Started Jul 18 04:46:36 PM PDT 24
Finished Jul 18 05:22:38 PM PDT 24
Peak memory 160752 kb
Host smart-36491da4-817c-493a-aade-5bb685cc9ef3
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2868416674 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.2868416674
Directory /workspace/18.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.2887824089
Short name T163
Test name
Test status
Simulation time 336870930000 ps
CPU time 820.97 seconds
Started Jul 18 04:46:37 PM PDT 24
Finished Jul 18 05:20:35 PM PDT 24
Peak memory 160712 kb
Host smart-d41f4290-c634-4878-b6bc-14bb1f5d327e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2887824089 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.2887824089
Directory /workspace/19.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.3917913658
Short name T196
Test name
Test status
Simulation time 336554910000 ps
CPU time 1012.8 seconds
Started Jul 18 04:46:19 PM PDT 24
Finished Jul 18 05:29:10 PM PDT 24
Peak memory 160744 kb
Host smart-1ee9540f-778f-4ada-bf22-d4a9e5ff020b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3917913658 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.3917913658
Directory /workspace/2.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.1612356122
Short name T195
Test name
Test status
Simulation time 336470150000 ps
CPU time 850.4 seconds
Started Jul 18 04:46:37 PM PDT 24
Finished Jul 18 05:21:12 PM PDT 24
Peak memory 160804 kb
Host smart-3c1e4e44-2ce1-4bd7-a098-9cb59f8b8b0f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1612356122 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.1612356122
Directory /workspace/20.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.316059161
Short name T23
Test name
Test status
Simulation time 336344050000 ps
CPU time 852.72 seconds
Started Jul 18 04:46:38 PM PDT 24
Finished Jul 18 05:21:57 PM PDT 24
Peak memory 160672 kb
Host smart-69c0447b-ce70-4661-abe3-9a7272338694
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=316059161 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.316059161
Directory /workspace/21.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.106228698
Short name T25
Test name
Test status
Simulation time 336359470000 ps
CPU time 957.49 seconds
Started Jul 18 04:46:37 PM PDT 24
Finished Jul 18 05:27:58 PM PDT 24
Peak memory 160708 kb
Host smart-eb94aa65-67ba-4e30-b511-ae417eed4acb
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=106228698 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.106228698
Directory /workspace/22.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.3915404068
Short name T181
Test name
Test status
Simulation time 336693670000 ps
CPU time 855.82 seconds
Started Jul 18 04:46:39 PM PDT 24
Finished Jul 18 05:21:59 PM PDT 24
Peak memory 160316 kb
Host smart-7cf2891c-2238-41e9-9cef-3adf57f39844
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3915404068 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.3915404068
Directory /workspace/23.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.1264946033
Short name T198
Test name
Test status
Simulation time 336585670000 ps
CPU time 912.3 seconds
Started Jul 18 04:46:34 PM PDT 24
Finished Jul 18 05:24:22 PM PDT 24
Peak memory 160684 kb
Host smart-4c44fbf9-07e3-4014-b2c6-03a8ece76076
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1264946033 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.1264946033
Directory /workspace/24.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.2155602184
Short name T199
Test name
Test status
Simulation time 336640330000 ps
CPU time 963.66 seconds
Started Jul 18 04:46:37 PM PDT 24
Finished Jul 18 05:28:14 PM PDT 24
Peak memory 160708 kb
Host smart-91b7d75b-8e32-4a17-a420-26d60c9b2c60
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2155602184 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.2155602184
Directory /workspace/25.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.280885597
Short name T166
Test name
Test status
Simulation time 336914330000 ps
CPU time 1053.4 seconds
Started Jul 18 04:46:36 PM PDT 24
Finished Jul 18 05:30:34 PM PDT 24
Peak memory 160868 kb
Host smart-57f9acc9-04e7-49ec-a896-62b37bd73a88
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=280885597 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.280885597
Directory /workspace/26.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.1827737731
Short name T29
Test name
Test status
Simulation time 336398510000 ps
CPU time 886.87 seconds
Started Jul 18 04:46:41 PM PDT 24
Finished Jul 18 05:23:02 PM PDT 24
Peak memory 160732 kb
Host smart-9a2b6b82-ef05-4a6c-83e0-12fe1aa263f5
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1827737731 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.1827737731
Directory /workspace/27.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.2534297789
Short name T169
Test name
Test status
Simulation time 336428310000 ps
CPU time 821.89 seconds
Started Jul 18 04:46:38 PM PDT 24
Finished Jul 18 05:20:23 PM PDT 24
Peak memory 160708 kb
Host smart-32e29a82-d64e-4ba9-953d-9ed3773c1d47
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2534297789 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.2534297789
Directory /workspace/28.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.853801015
Short name T167
Test name
Test status
Simulation time 336793110000 ps
CPU time 991.44 seconds
Started Jul 18 04:46:40 PM PDT 24
Finished Jul 18 05:27:08 PM PDT 24
Peak memory 160572 kb
Host smart-8df50867-afab-482c-bf38-0bdc3fb5f5b3
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=853801015 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.853801015
Directory /workspace/29.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.1153622195
Short name T165
Test name
Test status
Simulation time 336977250000 ps
CPU time 732.66 seconds
Started Jul 18 04:46:31 PM PDT 24
Finished Jul 18 05:16:19 PM PDT 24
Peak memory 160704 kb
Host smart-5739600d-8594-438d-abf9-62fad6faae18
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1153622195 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.1153622195
Directory /workspace/3.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.749259267
Short name T168
Test name
Test status
Simulation time 336692530000 ps
CPU time 921.35 seconds
Started Jul 18 04:46:40 PM PDT 24
Finished Jul 18 05:25:22 PM PDT 24
Peak memory 160784 kb
Host smart-bffd6cfa-c5dc-4d47-8eac-fb4ba30f23a0
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=749259267 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.749259267
Directory /workspace/30.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.164264904
Short name T194
Test name
Test status
Simulation time 336628650000 ps
CPU time 907.2 seconds
Started Jul 18 04:46:36 PM PDT 24
Finished Jul 18 05:24:41 PM PDT 24
Peak memory 160640 kb
Host smart-49421ef0-c508-4f78-b0f7-da6164c79067
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=164264904 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.164264904
Directory /workspace/31.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.2932997595
Short name T192
Test name
Test status
Simulation time 336380490000 ps
CPU time 904.28 seconds
Started Jul 18 04:46:37 PM PDT 24
Finished Jul 18 05:24:23 PM PDT 24
Peak memory 160640 kb
Host smart-65340a73-b303-418c-aac1-f6766296b454
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2932997595 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.2932997595
Directory /workspace/32.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.1840932751
Short name T185
Test name
Test status
Simulation time 336953210000 ps
CPU time 907.65 seconds
Started Jul 18 04:46:38 PM PDT 24
Finished Jul 18 05:23:50 PM PDT 24
Peak memory 160708 kb
Host smart-8cadaba0-280f-4f15-9f61-2db13e1fa1ed
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1840932751 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.1840932751
Directory /workspace/33.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.1832162205
Short name T22
Test name
Test status
Simulation time 337166030000 ps
CPU time 836.32 seconds
Started Jul 18 04:46:36 PM PDT 24
Finished Jul 18 05:20:28 PM PDT 24
Peak memory 160732 kb
Host smart-3c8c86fa-db01-43f4-bde4-e5315173a500
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1832162205 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.1832162205
Directory /workspace/34.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.3963220272
Short name T174
Test name
Test status
Simulation time 337067270000 ps
CPU time 997.79 seconds
Started Jul 18 04:46:40 PM PDT 24
Finished Jul 18 05:27:15 PM PDT 24
Peak memory 160584 kb
Host smart-2edf923f-afe2-42ed-94d3-edfa1defd918
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3963220272 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.3963220272
Directory /workspace/35.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.3375694510
Short name T21
Test name
Test status
Simulation time 337182110000 ps
CPU time 883.52 seconds
Started Jul 18 04:46:38 PM PDT 24
Finished Jul 18 05:22:48 PM PDT 24
Peak memory 160732 kb
Host smart-dae6f2e1-01b2-42d3-bdb0-b672b6e23be1
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3375694510 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.3375694510
Directory /workspace/36.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.3404225937
Short name T186
Test name
Test status
Simulation time 336829110000 ps
CPU time 940.53 seconds
Started Jul 18 04:46:41 PM PDT 24
Finished Jul 18 05:26:07 PM PDT 24
Peak memory 160792 kb
Host smart-ba30804a-d7c3-4a00-a9ab-289238a6f536
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3404225937 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.3404225937
Directory /workspace/37.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.2038438948
Short name T170
Test name
Test status
Simulation time 336339910000 ps
CPU time 860.85 seconds
Started Jul 18 04:46:40 PM PDT 24
Finished Jul 18 05:22:30 PM PDT 24
Peak memory 160732 kb
Host smart-7be87b7b-032b-4f42-aa3f-41fa76b6ced0
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2038438948 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.2038438948
Directory /workspace/38.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.903416946
Short name T197
Test name
Test status
Simulation time 336353130000 ps
CPU time 781.26 seconds
Started Jul 18 04:46:37 PM PDT 24
Finished Jul 18 05:18:50 PM PDT 24
Peak memory 160708 kb
Host smart-d6360c1f-3264-4f08-9037-e2b038583dcd
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=903416946 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.903416946
Directory /workspace/39.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.531669591
Short name T184
Test name
Test status
Simulation time 336889250000 ps
CPU time 821.47 seconds
Started Jul 18 04:46:36 PM PDT 24
Finished Jul 18 05:20:06 PM PDT 24
Peak memory 160724 kb
Host smart-508698a3-9ec7-4400-a7f5-52a25c09c96f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=531669591 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.531669591
Directory /workspace/4.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.781401705
Short name T188
Test name
Test status
Simulation time 336613410000 ps
CPU time 932.86 seconds
Started Jul 18 04:46:37 PM PDT 24
Finished Jul 18 05:25:37 PM PDT 24
Peak memory 160720 kb
Host smart-9062646a-b405-40c1-8831-98df9fccbbd2
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=781401705 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.781401705
Directory /workspace/40.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.2509308254
Short name T172
Test name
Test status
Simulation time 336351230000 ps
CPU time 896.9 seconds
Started Jul 18 04:46:41 PM PDT 24
Finished Jul 18 05:23:23 PM PDT 24
Peak memory 160732 kb
Host smart-2da8c823-2536-448f-b5d1-4d03b2d6a016
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2509308254 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.2509308254
Directory /workspace/41.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.2412133993
Short name T179
Test name
Test status
Simulation time 336494310000 ps
CPU time 852.66 seconds
Started Jul 18 04:46:38 PM PDT 24
Finished Jul 18 05:22:34 PM PDT 24
Peak memory 160704 kb
Host smart-a02c7e8d-919f-4d53-a49d-75a9e58af7ac
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2412133993 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.2412133993
Directory /workspace/42.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.694496321
Short name T187
Test name
Test status
Simulation time 336992730000 ps
CPU time 1047.05 seconds
Started Jul 18 04:46:37 PM PDT 24
Finished Jul 18 05:30:23 PM PDT 24
Peak memory 160868 kb
Host smart-6dadee5d-1348-492d-8374-14d108020573
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=694496321 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.694496321
Directory /workspace/43.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.3280208661
Short name T189
Test name
Test status
Simulation time 337079850000 ps
CPU time 1015.01 seconds
Started Jul 18 04:46:38 PM PDT 24
Finished Jul 18 05:29:25 PM PDT 24
Peak memory 160752 kb
Host smart-61ca2fac-4cb9-43b2-bd69-d73ab4ac5b54
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3280208661 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.3280208661
Directory /workspace/44.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.4261152711
Short name T180
Test name
Test status
Simulation time 336363870000 ps
CPU time 1050.94 seconds
Started Jul 18 04:46:38 PM PDT 24
Finished Jul 18 05:30:51 PM PDT 24
Peak memory 160740 kb
Host smart-afcc0255-b26a-44ab-8d5a-f8d9fb765fab
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4261152711 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.4261152711
Directory /workspace/45.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.2128755038
Short name T162
Test name
Test status
Simulation time 336519850000 ps
CPU time 856.98 seconds
Started Jul 18 04:46:35 PM PDT 24
Finished Jul 18 05:21:26 PM PDT 24
Peak memory 160732 kb
Host smart-835456a3-d2f9-4aac-9b55-544037ae4a7b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2128755038 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.2128755038
Directory /workspace/46.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.190181937
Short name T164
Test name
Test status
Simulation time 337089070000 ps
CPU time 876.41 seconds
Started Jul 18 04:56:22 PM PDT 24
Finished Jul 18 05:32:18 PM PDT 24
Peak memory 160732 kb
Host smart-e2f933e7-fc27-48af-8046-e0256117cf63
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=190181937 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.190181937
Directory /workspace/47.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.250481170
Short name T26
Test name
Test status
Simulation time 337013590000 ps
CPU time 854.59 seconds
Started Jul 18 04:46:37 PM PDT 24
Finished Jul 18 05:21:16 PM PDT 24
Peak memory 160804 kb
Host smart-0c6f0a2f-9396-406e-9ffb-53756043ccae
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=250481170 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.250481170
Directory /workspace/48.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.3634499798
Short name T182
Test name
Test status
Simulation time 336860790000 ps
CPU time 1018.2 seconds
Started Jul 18 04:46:38 PM PDT 24
Finished Jul 18 05:29:32 PM PDT 24
Peak memory 160752 kb
Host smart-cc7bb465-657c-4821-ac26-c06bc62bf4e1
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3634499798 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.3634499798
Directory /workspace/49.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.2358307812
Short name T191
Test name
Test status
Simulation time 337011830000 ps
CPU time 842.77 seconds
Started Jul 18 04:46:38 PM PDT 24
Finished Jul 18 05:21:16 PM PDT 24
Peak memory 160700 kb
Host smart-8ad05b1f-684a-43b0-9b64-d01960bc0c90
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2358307812 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.2358307812
Directory /workspace/5.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.3494803622
Short name T177
Test name
Test status
Simulation time 336528350000 ps
CPU time 779.61 seconds
Started Jul 18 04:46:36 PM PDT 24
Finished Jul 18 05:18:37 PM PDT 24
Peak memory 160708 kb
Host smart-ae643f5a-845b-43ad-881a-7fcd142e4805
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3494803622 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.3494803622
Directory /workspace/6.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.4187175458
Short name T161
Test name
Test status
Simulation time 336792130000 ps
CPU time 864.77 seconds
Started Jul 18 04:46:38 PM PDT 24
Finished Jul 18 05:22:45 PM PDT 24
Peak memory 160696 kb
Host smart-5850f2b7-f860-427e-8e5e-e72bae26dae7
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4187175458 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.4187175458
Directory /workspace/7.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.3871620361
Short name T171
Test name
Test status
Simulation time 337140970000 ps
CPU time 854.58 seconds
Started Jul 18 04:46:38 PM PDT 24
Finished Jul 18 05:21:58 PM PDT 24
Peak memory 160696 kb
Host smart-0c6ae57f-32a0-41a4-aead-579a572e4f02
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3871620361 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.3871620361
Directory /workspace/8.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.462092093
Short name T27
Test name
Test status
Simulation time 336577350000 ps
CPU time 835.08 seconds
Started Jul 18 04:46:35 PM PDT 24
Finished Jul 18 05:20:53 PM PDT 24
Peak memory 160728 kb
Host smart-3a5edbc9-ded7-459a-9882-4d574b5eff0c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=462092093 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.462092093
Directory /workspace/9.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.2677308789
Short name T139
Test name
Test status
Simulation time 1537370000 ps
CPU time 4.93 seconds
Started Jul 18 05:36:05 PM PDT 24
Finished Jul 18 05:36:18 PM PDT 24
Peak memory 164968 kb
Host smart-2e9e82a6-dfb7-40c7-98fa-bd68146f4b30
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2677308789 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.2677308789
Directory /workspace/0.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.505229981
Short name T156
Test name
Test status
Simulation time 1345230000 ps
CPU time 3.19 seconds
Started Jul 18 05:36:07 PM PDT 24
Finished Jul 18 05:36:19 PM PDT 24
Peak memory 164900 kb
Host smart-cd1fa568-d67b-4184-8a81-ac323aeaf995
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=505229981 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.505229981
Directory /workspace/1.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.611416181
Short name T135
Test name
Test status
Simulation time 1501690000 ps
CPU time 4.31 seconds
Started Jul 18 05:36:06 PM PDT 24
Finished Jul 18 05:36:19 PM PDT 24
Peak memory 164872 kb
Host smart-6d0631c7-3cec-466e-abb1-45a065117644
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=611416181 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.611416181
Directory /workspace/10.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.417268122
Short name T153
Test name
Test status
Simulation time 1396670000 ps
CPU time 4.4 seconds
Started Jul 18 05:36:09 PM PDT 24
Finished Jul 18 05:36:24 PM PDT 24
Peak memory 164908 kb
Host smart-064f9c1d-3a8d-475e-abd0-7893301b18cd
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=417268122 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.417268122
Directory /workspace/11.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.3625091524
Short name T152
Test name
Test status
Simulation time 1491230000 ps
CPU time 3.78 seconds
Started Jul 18 05:36:07 PM PDT 24
Finished Jul 18 05:36:20 PM PDT 24
Peak memory 164712 kb
Host smart-39cd51e1-8441-4514-9dce-c46568dd3527
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3625091524 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.3625091524
Directory /workspace/12.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.3816829556
Short name T120
Test name
Test status
Simulation time 1301650000 ps
CPU time 3.97 seconds
Started Jul 18 05:36:08 PM PDT 24
Finished Jul 18 05:36:21 PM PDT 24
Peak memory 164928 kb
Host smart-ac77f6e6-6c22-49a4-b6d7-8b1c8cd192eb
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3816829556 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.3816829556
Directory /workspace/13.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.3088462716
Short name T114
Test name
Test status
Simulation time 1117310000 ps
CPU time 2.32 seconds
Started Jul 18 05:36:08 PM PDT 24
Finished Jul 18 05:36:20 PM PDT 24
Peak memory 164980 kb
Host smart-58a6e255-6748-4774-9c69-9b064d9fcf38
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3088462716 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.3088462716
Directory /workspace/14.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.1105165243
Short name T147
Test name
Test status
Simulation time 1183090000 ps
CPU time 4.01 seconds
Started Jul 18 05:36:07 PM PDT 24
Finished Jul 18 05:36:21 PM PDT 24
Peak memory 164928 kb
Host smart-dab5bb0d-c1e6-4afd-afed-60e6ebe6987c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1105165243 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.1105165243
Directory /workspace/15.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.2680122332
Short name T136
Test name
Test status
Simulation time 1472150000 ps
CPU time 3.94 seconds
Started Jul 18 05:36:08 PM PDT 24
Finished Jul 18 05:36:23 PM PDT 24
Peak memory 164960 kb
Host smart-83c6c856-ed58-4316-82b4-5d2c55a70096
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2680122332 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.2680122332
Directory /workspace/16.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.2265600631
Short name T141
Test name
Test status
Simulation time 1394730000 ps
CPU time 4.56 seconds
Started Jul 18 05:36:05 PM PDT 24
Finished Jul 18 05:36:16 PM PDT 24
Peak memory 164944 kb
Host smart-0da7a3c6-8bf6-49ec-9519-81f582548476
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2265600631 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.2265600631
Directory /workspace/17.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.3402075259
Short name T133
Test name
Test status
Simulation time 1353830000 ps
CPU time 3.65 seconds
Started Jul 18 05:36:12 PM PDT 24
Finished Jul 18 05:36:28 PM PDT 24
Peak memory 164952 kb
Host smart-256bd354-f67f-4882-951d-b75c9e1c1ac5
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3402075259 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.3402075259
Directory /workspace/18.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.2225848640
Short name T148
Test name
Test status
Simulation time 1425450000 ps
CPU time 3.44 seconds
Started Jul 18 05:36:13 PM PDT 24
Finished Jul 18 05:36:29 PM PDT 24
Peak memory 164912 kb
Host smart-2034df23-75d8-4a5e-b1c0-8c2422ac752d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2225848640 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.2225848640
Directory /workspace/19.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.3562687622
Short name T127
Test name
Test status
Simulation time 1476010000 ps
CPU time 4.66 seconds
Started Jul 18 05:36:04 PM PDT 24
Finished Jul 18 05:36:16 PM PDT 24
Peak memory 164984 kb
Host smart-ffe4c0d1-1f95-4959-8f0b-0e901296a396
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3562687622 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.3562687622
Directory /workspace/2.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.1590574383
Short name T151
Test name
Test status
Simulation time 1495250000 ps
CPU time 4.31 seconds
Started Jul 18 05:36:16 PM PDT 24
Finished Jul 18 05:36:34 PM PDT 24
Peak memory 164932 kb
Host smart-a9396064-2f3a-44e3-a3ff-3b279d48705d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1590574383 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.1590574383
Directory /workspace/20.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3592770209
Short name T125
Test name
Test status
Simulation time 1544990000 ps
CPU time 4.41 seconds
Started Jul 18 05:36:06 PM PDT 24
Finished Jul 18 05:36:18 PM PDT 24
Peak memory 164928 kb
Host smart-c3289e35-ba52-4eac-a681-e2ed9f4cc525
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3592770209 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.3592770209
Directory /workspace/21.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.4088715939
Short name T118
Test name
Test status
Simulation time 1550070000 ps
CPU time 4.2 seconds
Started Jul 18 05:36:05 PM PDT 24
Finished Jul 18 05:36:18 PM PDT 24
Peak memory 164928 kb
Host smart-95764514-a13d-479d-80dd-a18d0e07afba
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4088715939 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.4088715939
Directory /workspace/22.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.1847164190
Short name T142
Test name
Test status
Simulation time 1448890000 ps
CPU time 3.81 seconds
Started Jul 18 05:36:12 PM PDT 24
Finished Jul 18 05:36:28 PM PDT 24
Peak memory 164952 kb
Host smart-f86f2cf2-153a-4496-a500-bbd4089b00cf
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1847164190 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.1847164190
Directory /workspace/23.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.2197665532
Short name T121
Test name
Test status
Simulation time 1454530000 ps
CPU time 4.92 seconds
Started Jul 18 05:36:05 PM PDT 24
Finished Jul 18 05:36:19 PM PDT 24
Peak memory 164932 kb
Host smart-2b070008-c3e6-4153-af01-1d1a241fa8b1
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2197665532 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.2197665532
Directory /workspace/24.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.2616920895
Short name T123
Test name
Test status
Simulation time 1459970000 ps
CPU time 4.77 seconds
Started Jul 18 05:36:08 PM PDT 24
Finished Jul 18 05:36:25 PM PDT 24
Peak memory 164912 kb
Host smart-f27a37d0-b808-462f-9fb6-b47ad7b927de
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2616920895 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.2616920895
Directory /workspace/25.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.902266453
Short name T157
Test name
Test status
Simulation time 1383870000 ps
CPU time 5.43 seconds
Started Jul 18 05:36:07 PM PDT 24
Finished Jul 18 05:36:23 PM PDT 24
Peak memory 164888 kb
Host smart-3d605bed-d2df-4b34-bd6f-2d84293c4ee6
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=902266453 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.902266453
Directory /workspace/26.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.4195679656
Short name T128
Test name
Test status
Simulation time 1526770000 ps
CPU time 4.43 seconds
Started Jul 18 05:36:07 PM PDT 24
Finished Jul 18 05:36:21 PM PDT 24
Peak memory 164904 kb
Host smart-899e47aa-7db1-439b-8863-b6004bd26d0b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4195679656 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.4195679656
Directory /workspace/27.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.2624314070
Short name T124
Test name
Test status
Simulation time 1538130000 ps
CPU time 4.51 seconds
Started Jul 18 05:36:03 PM PDT 24
Finished Jul 18 05:36:15 PM PDT 24
Peak memory 164928 kb
Host smart-30a5a40a-7ac9-447a-9886-51f7df13d94f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2624314070 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.2624314070
Directory /workspace/28.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.1840868505
Short name T144
Test name
Test status
Simulation time 1400570000 ps
CPU time 3.16 seconds
Started Jul 18 05:36:11 PM PDT 24
Finished Jul 18 05:36:26 PM PDT 24
Peak memory 164932 kb
Host smart-94332ff3-4f30-41a1-ad4d-af20fc7bf7bb
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1840868505 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.1840868505
Directory /workspace/29.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.2508437251
Short name T115
Test name
Test status
Simulation time 1507390000 ps
CPU time 3.94 seconds
Started Jul 18 05:36:02 PM PDT 24
Finished Jul 18 05:36:13 PM PDT 24
Peak memory 164968 kb
Host smart-c903b4c9-4a2a-423d-bf09-47407a9f5128
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2508437251 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.2508437251
Directory /workspace/3.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.2048649915
Short name T111
Test name
Test status
Simulation time 1409950000 ps
CPU time 3.14 seconds
Started Jul 18 05:53:54 PM PDT 24
Finished Jul 18 05:54:02 PM PDT 24
Peak memory 164904 kb
Host smart-a4f0c2a5-80d3-4d77-a56b-7e31f0507b5b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2048649915 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.2048649915
Directory /workspace/30.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.1401383263
Short name T149
Test name
Test status
Simulation time 1501410000 ps
CPU time 3.5 seconds
Started Jul 18 05:36:08 PM PDT 24
Finished Jul 18 05:36:21 PM PDT 24
Peak memory 164976 kb
Host smart-152dc6df-7aa1-48cf-bb1e-e06f0bbe832f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1401383263 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.1401383263
Directory /workspace/31.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.4241115264
Short name T159
Test name
Test status
Simulation time 1416990000 ps
CPU time 4.21 seconds
Started Jul 18 05:36:05 PM PDT 24
Finished Jul 18 05:36:17 PM PDT 24
Peak memory 164928 kb
Host smart-ac091905-2482-4126-83b3-dab6b1a4283a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4241115264 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.4241115264
Directory /workspace/32.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.246385459
Short name T126
Test name
Test status
Simulation time 1575750000 ps
CPU time 5.13 seconds
Started Jul 18 05:36:04 PM PDT 24
Finished Jul 18 05:36:17 PM PDT 24
Peak memory 164860 kb
Host smart-2935dd39-e483-4e48-a328-959032634a6d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=246385459 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.246385459
Directory /workspace/33.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.2180284982
Short name T132
Test name
Test status
Simulation time 1473630000 ps
CPU time 3.76 seconds
Started Jul 18 05:36:08 PM PDT 24
Finished Jul 18 05:36:21 PM PDT 24
Peak memory 164904 kb
Host smart-91bff599-b054-469a-b644-b07b713a67fd
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2180284982 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.2180284982
Directory /workspace/34.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.420308509
Short name T160
Test name
Test status
Simulation time 1496690000 ps
CPU time 4.78 seconds
Started Jul 18 05:36:05 PM PDT 24
Finished Jul 18 05:36:17 PM PDT 24
Peak memory 164888 kb
Host smart-0b60a77e-a3ce-4cad-aa87-be4852de0a5b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=420308509 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.420308509
Directory /workspace/35.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.770297888
Short name T134
Test name
Test status
Simulation time 1206990000 ps
CPU time 3.41 seconds
Started Jul 18 05:36:08 PM PDT 24
Finished Jul 18 05:36:22 PM PDT 24
Peak memory 164880 kb
Host smart-026fcf2a-5f8a-4fe0-982e-cb790de790f9
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=770297888 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.770297888
Directory /workspace/36.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1889884409
Short name T155
Test name
Test status
Simulation time 1464610000 ps
CPU time 4.94 seconds
Started Jul 18 05:36:09 PM PDT 24
Finished Jul 18 05:36:34 PM PDT 24
Peak memory 164968 kb
Host smart-200911d9-3a0f-4d9c-b32a-83dad199670f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1889884409 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.1889884409
Directory /workspace/37.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.1594906710
Short name T116
Test name
Test status
Simulation time 1600230000 ps
CPU time 4.48 seconds
Started Jul 18 05:36:05 PM PDT 24
Finished Jul 18 05:36:18 PM PDT 24
Peak memory 164928 kb
Host smart-8201aa08-bda2-4d82-9531-a0ab3148fe9e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1594906710 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.1594906710
Directory /workspace/38.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.2310421645
Short name T140
Test name
Test status
Simulation time 1559190000 ps
CPU time 4.63 seconds
Started Jul 18 05:36:07 PM PDT 24
Finished Jul 18 05:36:21 PM PDT 24
Peak memory 164908 kb
Host smart-3716a6bc-1c91-49c0-bfa5-1ccd89211503
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2310421645 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.2310421645
Directory /workspace/39.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3876849857
Short name T117
Test name
Test status
Simulation time 1412990000 ps
CPU time 4.36 seconds
Started Jul 18 05:36:06 PM PDT 24
Finished Jul 18 05:36:21 PM PDT 24
Peak memory 164960 kb
Host smart-89c8b167-b2ee-4a13-a925-938e3678deeb
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3876849857 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.3876849857
Directory /workspace/4.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.3561301897
Short name T146
Test name
Test status
Simulation time 1548790000 ps
CPU time 4.44 seconds
Started Jul 18 05:36:06 PM PDT 24
Finished Jul 18 05:36:20 PM PDT 24
Peak memory 164968 kb
Host smart-ff35ba2f-9f19-447a-a58e-57f58f0894a5
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3561301897 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.3561301897
Directory /workspace/40.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.2722118821
Short name T137
Test name
Test status
Simulation time 1442510000 ps
CPU time 4.85 seconds
Started Jul 18 05:36:06 PM PDT 24
Finished Jul 18 05:36:22 PM PDT 24
Peak memory 164932 kb
Host smart-a92e3876-03ba-4a09-a712-5862d42d65d7
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2722118821 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.2722118821
Directory /workspace/41.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.2576964161
Short name T129
Test name
Test status
Simulation time 1543450000 ps
CPU time 5.28 seconds
Started Jul 18 05:36:03 PM PDT 24
Finished Jul 18 05:36:17 PM PDT 24
Peak memory 164968 kb
Host smart-a8ed93f9-0131-4b6d-83aa-0643fc6908c0
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2576964161 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.2576964161
Directory /workspace/42.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.3445158136
Short name T158
Test name
Test status
Simulation time 1550350000 ps
CPU time 3.83 seconds
Started Jul 18 05:36:05 PM PDT 24
Finished Jul 18 05:36:15 PM PDT 24
Peak memory 164928 kb
Host smart-5a7c4a77-8d6e-4eb4-b0de-fcc854f611c4
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3445158136 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.3445158136
Directory /workspace/43.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.4221224768
Short name T112
Test name
Test status
Simulation time 1141390000 ps
CPU time 3.27 seconds
Started Jul 18 05:36:07 PM PDT 24
Finished Jul 18 05:36:19 PM PDT 24
Peak memory 164692 kb
Host smart-268a7c8b-650a-42f4-a783-5d6d69599c89
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4221224768 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.4221224768
Directory /workspace/44.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.686457697
Short name T145
Test name
Test status
Simulation time 1377190000 ps
CPU time 3.08 seconds
Started Jul 18 05:36:11 PM PDT 24
Finished Jul 18 05:36:26 PM PDT 24
Peak memory 164876 kb
Host smart-852b57dd-ecb2-41a1-a0ea-20a25669a837
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=686457697 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.686457697
Directory /workspace/45.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.1204068861
Short name T143
Test name
Test status
Simulation time 1537510000 ps
CPU time 5.45 seconds
Started Jul 18 05:36:06 PM PDT 24
Finished Jul 18 05:36:21 PM PDT 24
Peak memory 164984 kb
Host smart-a6672248-4bae-4755-8d3a-f77005b3ea16
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1204068861 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.1204068861
Directory /workspace/46.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.2669151032
Short name T131
Test name
Test status
Simulation time 1301510000 ps
CPU time 3.19 seconds
Started Jul 18 05:36:08 PM PDT 24
Finished Jul 18 05:36:22 PM PDT 24
Peak memory 164920 kb
Host smart-d934df89-7194-49b1-bf39-23dc6aea6d60
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2669151032 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.2669151032
Directory /workspace/47.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.1240899933
Short name T150
Test name
Test status
Simulation time 1490610000 ps
CPU time 3.78 seconds
Started Jul 18 05:36:20 PM PDT 24
Finished Jul 18 05:36:35 PM PDT 24
Peak memory 164976 kb
Host smart-c785679c-8818-4d6b-9b9d-635d3018c153
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1240899933 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.1240899933
Directory /workspace/48.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.2613087625
Short name T138
Test name
Test status
Simulation time 1612430000 ps
CPU time 4.19 seconds
Started Jul 18 05:36:02 PM PDT 24
Finished Jul 18 05:36:14 PM PDT 24
Peak memory 164884 kb
Host smart-b89c40b5-f58a-4779-8c5a-27f0533d9868
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2613087625 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.2613087625
Directory /workspace/49.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.4146782455
Short name T122
Test name
Test status
Simulation time 1515510000 ps
CPU time 4.72 seconds
Started Jul 18 05:36:05 PM PDT 24
Finished Jul 18 05:36:17 PM PDT 24
Peak memory 164920 kb
Host smart-998dfaf5-cea8-41f2-8741-a3a2f16f03e5
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4146782455 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.4146782455
Directory /workspace/5.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.2688352641
Short name T113
Test name
Test status
Simulation time 1575070000 ps
CPU time 4.62 seconds
Started Jul 18 05:36:07 PM PDT 24
Finished Jul 18 05:36:21 PM PDT 24
Peak memory 164912 kb
Host smart-2c8d699f-4644-48f5-a8b9-361ea8e3ecf9
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2688352641 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.2688352641
Directory /workspace/6.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.1775337470
Short name T130
Test name
Test status
Simulation time 1332050000 ps
CPU time 5.57 seconds
Started Jul 18 05:36:03 PM PDT 24
Finished Jul 18 05:36:17 PM PDT 24
Peak memory 164916 kb
Host smart-cda8178e-28b3-41d4-ade1-ec2d120b0edc
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1775337470 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.1775337470
Directory /workspace/7.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.2469375246
Short name T154
Test name
Test status
Simulation time 1274130000 ps
CPU time 2.89 seconds
Started Jul 18 05:36:09 PM PDT 24
Finished Jul 18 05:36:23 PM PDT 24
Peak memory 164928 kb
Host smart-9aa8f5c3-7d3e-4b03-9ca5-3eb5febc57f3
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2469375246 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.2469375246
Directory /workspace/8.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2242048709
Short name T119
Test name
Test status
Simulation time 1481390000 ps
CPU time 4.19 seconds
Started Jul 18 05:36:05 PM PDT 24
Finished Jul 18 05:36:17 PM PDT 24
Peak memory 164928 kb
Host smart-0adc29d9-1286-4d7e-af82-4db3ca322803
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2242048709 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.2242048709
Directory /workspace/9.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.2089827675
Short name T35
Test name
Test status
Simulation time 1465950000 ps
CPU time 3.82 seconds
Started Jul 18 04:45:38 PM PDT 24
Finished Jul 18 04:45:52 PM PDT 24
Peak memory 164844 kb
Host smart-b6ffef9c-58bf-4a4a-99ea-711055b073ab
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2089827675 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.2089827675
Directory /workspace/0.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.4202376328
Short name T42
Test name
Test status
Simulation time 1145050000 ps
CPU time 3.39 seconds
Started Jul 18 04:45:40 PM PDT 24
Finished Jul 18 04:45:54 PM PDT 24
Peak memory 164872 kb
Host smart-c4bde58e-1285-4c51-8610-4705ea7c5544
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4202376328 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.4202376328
Directory /workspace/1.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.2437584468
Short name T66
Test name
Test status
Simulation time 1477450000 ps
CPU time 5.96 seconds
Started Jul 18 04:45:37 PM PDT 24
Finished Jul 18 04:45:55 PM PDT 24
Peak memory 164876 kb
Host smart-fe278cb3-ba41-40ca-bb8d-50333bb0601c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2437584468 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.2437584468
Directory /workspace/11.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.383114398
Short name T60
Test name
Test status
Simulation time 1429930000 ps
CPU time 3.99 seconds
Started Jul 18 04:45:41 PM PDT 24
Finished Jul 18 04:45:56 PM PDT 24
Peak memory 164848 kb
Host smart-c4ff961d-c20f-4ff6-bf6c-0118eb095354
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=383114398 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.383114398
Directory /workspace/12.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.2665368888
Short name T67
Test name
Test status
Simulation time 1563470000 ps
CPU time 3.84 seconds
Started Jul 18 04:45:42 PM PDT 24
Finished Jul 18 04:45:56 PM PDT 24
Peak memory 164928 kb
Host smart-b37d6a73-b5da-474e-8f32-7ee353c83be5
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2665368888 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.2665368888
Directory /workspace/13.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.3586356484
Short name T56
Test name
Test status
Simulation time 1149090000 ps
CPU time 3.55 seconds
Started Jul 18 04:45:41 PM PDT 24
Finished Jul 18 04:45:55 PM PDT 24
Peak memory 164820 kb
Host smart-2b1cca0f-7c07-480e-b320-1c7ec99dfa51
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3586356484 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.3586356484
Directory /workspace/14.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.60057567
Short name T65
Test name
Test status
Simulation time 1485990000 ps
CPU time 5.96 seconds
Started Jul 18 04:45:37 PM PDT 24
Finished Jul 18 04:45:54 PM PDT 24
Peak memory 164816 kb
Host smart-48d23341-9d17-4523-ba8e-4ad26f8c929e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=60057567 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.60057567
Directory /workspace/15.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.115488460
Short name T39
Test name
Test status
Simulation time 1482230000 ps
CPU time 3.92 seconds
Started Jul 18 04:45:38 PM PDT 24
Finished Jul 18 04:45:53 PM PDT 24
Peak memory 164848 kb
Host smart-cb351b6e-6c38-417f-a949-f5784035553a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=115488460 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.115488460
Directory /workspace/16.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.3637929325
Short name T37
Test name
Test status
Simulation time 1438510000 ps
CPU time 4.44 seconds
Started Jul 18 04:45:43 PM PDT 24
Finished Jul 18 04:45:58 PM PDT 24
Peak memory 164864 kb
Host smart-5cc301c8-89e4-45ac-9efa-1a71da9458c4
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3637929325 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.3637929325
Directory /workspace/17.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.2662968298
Short name T1
Test name
Test status
Simulation time 1498130000 ps
CPU time 4.74 seconds
Started Jul 18 04:45:39 PM PDT 24
Finished Jul 18 04:45:57 PM PDT 24
Peak memory 164848 kb
Host smart-a3841b56-9a3f-42b9-a25f-24a86304a539
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2662968298 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.2662968298
Directory /workspace/18.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.3440863135
Short name T33
Test name
Test status
Simulation time 1527510000 ps
CPU time 4.74 seconds
Started Jul 18 04:45:43 PM PDT 24
Finished Jul 18 04:45:58 PM PDT 24
Peak memory 164820 kb
Host smart-0df2edc8-41a6-443b-89f8-1076e8fe5e91
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3440863135 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.3440863135
Directory /workspace/19.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.1977017057
Short name T38
Test name
Test status
Simulation time 1538810000 ps
CPU time 4.5 seconds
Started Jul 18 04:45:38 PM PDT 24
Finished Jul 18 04:45:54 PM PDT 24
Peak memory 164868 kb
Host smart-001a9aaa-5950-44a0-8f7e-35728b3ab713
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1977017057 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.1977017057
Directory /workspace/2.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.113928758
Short name T13
Test name
Test status
Simulation time 1464530000 ps
CPU time 4.35 seconds
Started Jul 18 04:45:41 PM PDT 24
Finished Jul 18 04:45:57 PM PDT 24
Peak memory 164868 kb
Host smart-69a81365-e8ff-4290-a858-2271b61c16f3
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=113928758 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.113928758
Directory /workspace/20.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.1213002180
Short name T34
Test name
Test status
Simulation time 1369830000 ps
CPU time 4.35 seconds
Started Jul 18 04:45:53 PM PDT 24
Finished Jul 18 04:46:03 PM PDT 24
Peak memory 164876 kb
Host smart-3ff4f34e-7b5b-4969-99c7-1bf77c97f022
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1213002180 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.1213002180
Directory /workspace/21.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.2748948216
Short name T31
Test name
Test status
Simulation time 1472090000 ps
CPU time 3.57 seconds
Started Jul 18 04:45:55 PM PDT 24
Finished Jul 18 04:46:04 PM PDT 24
Peak memory 164868 kb
Host smart-abb53bec-1916-42ac-87ef-194571e41d15
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2748948216 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.2748948216
Directory /workspace/22.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.3953042216
Short name T49
Test name
Test status
Simulation time 1451910000 ps
CPU time 4.4 seconds
Started Jul 18 04:45:53 PM PDT 24
Finished Jul 18 04:46:03 PM PDT 24
Peak memory 164868 kb
Host smart-c5279451-fac6-4591-a8ea-8298c52b3bb2
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3953042216 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.3953042216
Directory /workspace/23.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.1143996047
Short name T7
Test name
Test status
Simulation time 1294870000 ps
CPU time 4.24 seconds
Started Jul 18 04:45:58 PM PDT 24
Finished Jul 18 04:46:09 PM PDT 24
Peak memory 164876 kb
Host smart-b542d886-ade7-4bee-9292-1227416ac5f3
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1143996047 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.1143996047
Directory /workspace/24.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.433803084
Short name T10
Test name
Test status
Simulation time 1505810000 ps
CPU time 5.56 seconds
Started Jul 18 04:45:54 PM PDT 24
Finished Jul 18 04:46:08 PM PDT 24
Peak memory 164780 kb
Host smart-db5e50f5-d955-45e2-8ff3-9e9848517e85
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=433803084 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.433803084
Directory /workspace/25.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.2663966223
Short name T63
Test name
Test status
Simulation time 1452230000 ps
CPU time 4.63 seconds
Started Jul 18 04:45:56 PM PDT 24
Finished Jul 18 04:46:08 PM PDT 24
Peak memory 164872 kb
Host smart-e5a1912d-dde7-42fb-9d3d-79bb586d7c4b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2663966223 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.2663966223
Directory /workspace/26.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.616522457
Short name T55
Test name
Test status
Simulation time 1468710000 ps
CPU time 3.14 seconds
Started Jul 18 04:45:53 PM PDT 24
Finished Jul 18 04:46:01 PM PDT 24
Peak memory 164872 kb
Host smart-a073b55e-d1af-457d-811a-c1cc7c7d49a3
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=616522457 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.616522457
Directory /workspace/27.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.3588144444
Short name T44
Test name
Test status
Simulation time 1366270000 ps
CPU time 3.65 seconds
Started Jul 18 04:45:55 PM PDT 24
Finished Jul 18 04:46:05 PM PDT 24
Peak memory 164796 kb
Host smart-266b9369-726c-47ef-9595-5aff35472e59
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3588144444 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.3588144444
Directory /workspace/28.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.3101467841
Short name T9
Test name
Test status
Simulation time 1465690000 ps
CPU time 4.37 seconds
Started Jul 18 04:45:54 PM PDT 24
Finished Jul 18 04:46:05 PM PDT 24
Peak memory 164916 kb
Host smart-fc1f0a9e-16a8-4746-bc13-18bb982d8833
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3101467841 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.3101467841
Directory /workspace/29.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.842931927
Short name T64
Test name
Test status
Simulation time 1509410000 ps
CPU time 5.7 seconds
Started Jul 18 04:45:35 PM PDT 24
Finished Jul 18 04:45:52 PM PDT 24
Peak memory 164744 kb
Host smart-2a730c1e-9e9c-4e52-b6e7-84839fdd205e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=842931927 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.842931927
Directory /workspace/3.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.3106778879
Short name T53
Test name
Test status
Simulation time 1360290000 ps
CPU time 4.3 seconds
Started Jul 18 04:45:56 PM PDT 24
Finished Jul 18 04:46:07 PM PDT 24
Peak memory 164868 kb
Host smart-eb585951-b744-4924-b928-67beafbbd961
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3106778879 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.3106778879
Directory /workspace/30.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.421651142
Short name T54
Test name
Test status
Simulation time 1311350000 ps
CPU time 3.67 seconds
Started Jul 18 04:45:55 PM PDT 24
Finished Jul 18 04:46:05 PM PDT 24
Peak memory 164816 kb
Host smart-10f15c37-9a17-40dd-a02f-baa97b2ad7d5
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=421651142 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.421651142
Directory /workspace/31.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.3537715817
Short name T47
Test name
Test status
Simulation time 1533250000 ps
CPU time 3.69 seconds
Started Jul 18 04:46:19 PM PDT 24
Finished Jul 18 04:46:28 PM PDT 24
Peak memory 164872 kb
Host smart-45afb784-929d-4572-a1d5-4e6e8d9b6b27
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3537715817 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.3537715817
Directory /workspace/32.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.391574850
Short name T51
Test name
Test status
Simulation time 1406530000 ps
CPU time 3.52 seconds
Started Jul 18 04:46:20 PM PDT 24
Finished Jul 18 04:46:29 PM PDT 24
Peak memory 164764 kb
Host smart-b10af6fb-16e2-459d-9697-36ba6c87d4be
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=391574850 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.391574850
Directory /workspace/33.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.322765039
Short name T32
Test name
Test status
Simulation time 1383210000 ps
CPU time 4.62 seconds
Started Jul 18 04:46:27 PM PDT 24
Finished Jul 18 04:46:38 PM PDT 24
Peak memory 164816 kb
Host smart-2af41293-48a2-40eb-a333-aabd0de90386
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=322765039 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.322765039
Directory /workspace/34.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.2813927924
Short name T12
Test name
Test status
Simulation time 1474970000 ps
CPU time 2.84 seconds
Started Jul 18 04:46:17 PM PDT 24
Finished Jul 18 04:46:24 PM PDT 24
Peak memory 164872 kb
Host smart-932613ea-f4fd-43df-82d2-88ef0d4ecabb
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2813927924 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.2813927924
Directory /workspace/35.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.2249246780
Short name T2
Test name
Test status
Simulation time 1476230000 ps
CPU time 4.74 seconds
Started Jul 18 04:46:30 PM PDT 24
Finished Jul 18 04:46:42 PM PDT 24
Peak memory 164872 kb
Host smart-3e00598a-a606-4ae9-8f96-f8c9590cb4a8
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2249246780 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.2249246780
Directory /workspace/36.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.1691430228
Short name T62
Test name
Test status
Simulation time 1541890000 ps
CPU time 3.08 seconds
Started Jul 18 04:46:16 PM PDT 24
Finished Jul 18 04:46:25 PM PDT 24
Peak memory 164872 kb
Host smart-37152344-362a-4f8e-ac2b-2fd660bdfa1a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1691430228 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.1691430228
Directory /workspace/37.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.3640701961
Short name T48
Test name
Test status
Simulation time 1475630000 ps
CPU time 3.89 seconds
Started Jul 18 04:46:20 PM PDT 24
Finished Jul 18 04:46:29 PM PDT 24
Peak memory 164876 kb
Host smart-2f403d6f-b40d-46c4-adb3-5be40638790e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3640701961 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.3640701961
Directory /workspace/38.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.343258410
Short name T61
Test name
Test status
Simulation time 1490190000 ps
CPU time 4.88 seconds
Started Jul 18 04:46:26 PM PDT 24
Finished Jul 18 04:46:39 PM PDT 24
Peak memory 164816 kb
Host smart-a3d94393-8cdf-4f6b-9622-310848c305b1
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=343258410 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.343258410
Directory /workspace/39.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.2458784571
Short name T11
Test name
Test status
Simulation time 1623230000 ps
CPU time 5.03 seconds
Started Jul 18 04:45:36 PM PDT 24
Finished Jul 18 04:45:52 PM PDT 24
Peak memory 164876 kb
Host smart-055f4a06-837b-4b26-9f92-ace751681b92
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2458784571 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.2458784571
Directory /workspace/4.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.1772727756
Short name T45
Test name
Test status
Simulation time 1503090000 ps
CPU time 4.62 seconds
Started Jul 18 04:46:22 PM PDT 24
Finished Jul 18 04:46:32 PM PDT 24
Peak memory 164872 kb
Host smart-c072b76b-e8fe-480e-a74f-212af5789a3c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1772727756 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.1772727756
Directory /workspace/40.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.2228176691
Short name T36
Test name
Test status
Simulation time 1448870000 ps
CPU time 5.3 seconds
Started Jul 18 04:46:21 PM PDT 24
Finished Jul 18 04:46:34 PM PDT 24
Peak memory 164860 kb
Host smart-ce3eed65-8c64-4216-be41-7720588f6e72
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2228176691 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.2228176691
Directory /workspace/41.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.442965238
Short name T58
Test name
Test status
Simulation time 1343510000 ps
CPU time 3.84 seconds
Started Jul 18 04:46:22 PM PDT 24
Finished Jul 18 04:46:30 PM PDT 24
Peak memory 164816 kb
Host smart-39ae1ebc-d43f-45fe-822f-0d5344633ea6
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=442965238 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.442965238
Directory /workspace/42.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.2425859052
Short name T70
Test name
Test status
Simulation time 1574090000 ps
CPU time 4.06 seconds
Started Jul 18 04:46:23 PM PDT 24
Finished Jul 18 04:46:33 PM PDT 24
Peak memory 164876 kb
Host smart-8b3463a5-1cc0-4ca2-a6a2-893bddb13276
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2425859052 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.2425859052
Directory /workspace/43.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.879592068
Short name T41
Test name
Test status
Simulation time 1003550000 ps
CPU time 2.38 seconds
Started Jul 18 04:46:17 PM PDT 24
Finished Jul 18 04:46:23 PM PDT 24
Peak memory 164864 kb
Host smart-0e5a5797-e870-4de7-b829-3d5edcfbeb50
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=879592068 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.879592068
Directory /workspace/44.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.2514118257
Short name T57
Test name
Test status
Simulation time 1503570000 ps
CPU time 4.54 seconds
Started Jul 18 04:46:19 PM PDT 24
Finished Jul 18 04:46:30 PM PDT 24
Peak memory 164864 kb
Host smart-f7151fd4-9b24-4294-bb93-384a9f4257bb
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2514118257 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.2514118257
Directory /workspace/45.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.1728116076
Short name T43
Test name
Test status
Simulation time 1549670000 ps
CPU time 3.3 seconds
Started Jul 18 04:46:16 PM PDT 24
Finished Jul 18 04:46:25 PM PDT 24
Peak memory 164868 kb
Host smart-fc12a614-23e5-4924-8faa-a5e645d2839d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1728116076 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.1728116076
Directory /workspace/46.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.2758226757
Short name T50
Test name
Test status
Simulation time 1492070000 ps
CPU time 4.9 seconds
Started Jul 18 04:46:26 PM PDT 24
Finished Jul 18 04:46:39 PM PDT 24
Peak memory 164872 kb
Host smart-70ed117d-46b1-41c3-8ab4-d2dd26a74b5c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2758226757 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.2758226757
Directory /workspace/47.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.3264940681
Short name T46
Test name
Test status
Simulation time 1416550000 ps
CPU time 3.92 seconds
Started Jul 18 04:46:20 PM PDT 24
Finished Jul 18 04:46:29 PM PDT 24
Peak memory 164868 kb
Host smart-cd09e372-d752-4704-8ac4-8eacdba0faf8
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3264940681 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.3264940681
Directory /workspace/48.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.1816648358
Short name T8
Test name
Test status
Simulation time 1558490000 ps
CPU time 4.26 seconds
Started Jul 18 04:46:19 PM PDT 24
Finished Jul 18 04:46:29 PM PDT 24
Peak memory 164868 kb
Host smart-1eafd7af-5cd4-4f84-9cec-82da168f9c71
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1816648358 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.1816648358
Directory /workspace/49.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.422738578
Short name T59
Test name
Test status
Simulation time 1351690000 ps
CPU time 4.44 seconds
Started Jul 18 04:45:40 PM PDT 24
Finished Jul 18 04:45:57 PM PDT 24
Peak memory 164768 kb
Host smart-8e482a75-3998-46b9-9593-9d8b05fb1aa3
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=422738578 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.422738578
Directory /workspace/5.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.3525884853
Short name T68
Test name
Test status
Simulation time 1513250000 ps
CPU time 4.61 seconds
Started Jul 18 04:45:37 PM PDT 24
Finished Jul 18 04:45:52 PM PDT 24
Peak memory 164876 kb
Host smart-3a55825f-ac4d-408c-ac34-2d31a58bc9b0
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3525884853 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.3525884853
Directory /workspace/6.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.3119200598
Short name T69
Test name
Test status
Simulation time 1504130000 ps
CPU time 6.45 seconds
Started Jul 18 04:45:39 PM PDT 24
Finished Jul 18 04:45:59 PM PDT 24
Peak memory 164868 kb
Host smart-5c22204d-e2e8-4f0c-b6b7-b50f46974344
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3119200598 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.3119200598
Directory /workspace/7.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.3686143176
Short name T52
Test name
Test status
Simulation time 1542870000 ps
CPU time 3.58 seconds
Started Jul 18 04:45:40 PM PDT 24
Finished Jul 18 04:45:55 PM PDT 24
Peak memory 164864 kb
Host smart-f3f5aeaa-db43-4a44-9a50-2ca01266e88a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3686143176 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.3686143176
Directory /workspace/8.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.1219073692
Short name T40
Test name
Test status
Simulation time 1461070000 ps
CPU time 3.28 seconds
Started Jul 18 04:45:38 PM PDT 24
Finished Jul 18 04:45:50 PM PDT 24
Peak memory 164872 kb
Host smart-7cb3037b-8346-4e2b-9ea1-f197eea77d6b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1219073692 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.1219073692
Directory /workspace/9.prim_lfsr_gal_smoke/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%