Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.31 100.00 96.55 100.00 100.00 95.00


Total tests in report: 200
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
87.31 87.31 100.00 100.00 96.55 96.55 100.00 100.00 100.00 100.00 40.00 40.00 /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.718774369
96.81 9.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 87.50 47.50 /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.2508586477
98.31 1.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 95.00 7.50 /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.1737350564

Tests that do not contribute to grading

Name
/workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.3326903778
/workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.4155606835
/workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.416455111
/workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.2931578627
/workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.2512921319
/workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.354125814
/workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.1690828843
/workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.3041084894
/workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.3793065917
/workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.945979685
/workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2134786088
/workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.4102468693
/workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.79973527
/workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.42416840
/workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.2710147917
/workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.3590842692
/workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.2313860105
/workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.1269968380
/workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1222353028
/workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.2274059109
/workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.2912033512
/workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.906796593
/workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.1179521788
/workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3963822714
/workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.2103621152
/workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.3464826127
/workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.3574857207
/workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.1914579505
/workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.3949525300
/workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.1405377740
/workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.1019539235
/workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.445972512
/workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.3567282735
/workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.3328007697
/workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.1636682365
/workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.1070575235
/workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.523860620
/workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.2605858538
/workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.1729741882
/workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.3312377678
/workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.1623076339
/workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.1022792900
/workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.1586879775
/workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.2158190571
/workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.1396277182
/workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.2362036393
/workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.776779469
/workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.2652403767
/workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.2347916142
/workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.2609359373
/workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.2388358559
/workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.479217945
/workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.1766285205
/workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.2587221066
/workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.2109553475
/workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.3217187592
/workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.3729141381
/workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.974685203
/workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.3029150727
/workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.1472200408
/workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.2253119388
/workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.1542125325
/workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.431251918
/workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.4137191336
/workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.2142886333
/workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.290029437
/workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.552055417
/workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.223927756
/workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.3433846970
/workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.999164943
/workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.1253648979
/workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.2221034373
/workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.1171960659
/workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.439000800
/workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.3445395963
/workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.1252701586
/workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.3620689019
/workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.193206908
/workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.2233474985
/workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.881944043
/workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.2222937660
/workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.1643621038
/workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.874294041
/workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.959581134
/workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.3531092691
/workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.1291892515
/workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.1773389306
/workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.4216908446
/workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.1117835791
/workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.3617299060
/workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.1949398259
/workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.577732827
/workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.3227683191
/workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.3772932316
/workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.58290608
/workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.2079529731
/workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.2285107759
/workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.1931142499
/workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.3443172961
/workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.3017899971
/workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.1636680550
/workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.10233401
/workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.2919969901
/workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.4122411392
/workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.1371698199
/workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.3985142145
/workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.108865708
/workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.2411310350
/workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.635504869
/workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.45426351
/workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.1264582098
/workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.2758547698
/workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.2521856482
/workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.288057847
/workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.4176740242
/workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.1789879059
/workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.2865461500
/workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.3735971831
/workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.433899300
/workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.1431911963
/workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.3424449367
/workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.1749096653
/workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.3389450104
/workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.851824210
/workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.1503474039
/workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.3368907078
/workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.3589103300
/workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.538822211
/workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.1946946931
/workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1003970128
/workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.3708035694
/workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.3160668965
/workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.2165252840
/workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.1332673607
/workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.4268211358
/workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.3632172493
/workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1172899726
/workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.2463689571
/workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.1163041889
/workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.3364862399
/workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.3550239107
/workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.1053243948
/workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.1063225872
/workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.1502093144
/workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.2195579945
/workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.2634198739
/workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.2460852652
/workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.955549681
/workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.1449427621
/workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.4035321234
/workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.1216713839
/workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.1689071202
/workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.917452999
/workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.2660756210
/workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.2132500149
/workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.2337502375
/workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.494579346
/workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.3317754940
/workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.1998096387
/workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.329916
/workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.1159762666
/workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.3980812355
/workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.333093872
/workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.1269841809
/workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.2333983698
/workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.294607274
/workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.2273237458
/workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.1152680157
/workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.2421473090
/workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.1920141648
/workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.3719484651
/workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.3118154745
/workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.1250009740
/workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.2542349597
/workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.3977262536
/workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.854974320
/workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.2009527152
/workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.2521955832
/workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.2227256578
/workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.601218271
/workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.1269999989
/workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.3088800814
/workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.3445255612
/workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.3367640089
/workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.2719096225
/workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.935240654
/workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.2532260166
/workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.1862016722
/workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.3699438132
/workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.2719375895
/workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.3105099577
/workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.1085034868
/workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.2771026451
/workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.3470176929
/workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.1796888981
/workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.495291498
/workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.439365556



Total test records in report: 200
tests.html | tests1.html | tests2.html | tests3.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.854974320 Jul 19 04:22:30 PM PDT 24 Jul 19 04:22:39 PM PDT 24 1390530000 ps
T2 /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.1998096387 Jul 19 04:22:07 PM PDT 24 Jul 19 04:22:18 PM PDT 24 1559790000 ps
T3 /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.718774369 Jul 19 04:22:28 PM PDT 24 Jul 19 04:22:39 PM PDT 24 1423510000 ps
T7 /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.1862016722 Jul 19 04:19:56 PM PDT 24 Jul 19 04:20:05 PM PDT 24 1383070000 ps
T8 /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.1152680157 Jul 19 04:19:19 PM PDT 24 Jul 19 04:19:30 PM PDT 24 1510650000 ps
T9 /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.294607274 Jul 19 04:20:11 PM PDT 24 Jul 19 04:20:19 PM PDT 24 1371170000 ps
T10 /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.3105099577 Jul 19 04:22:07 PM PDT 24 Jul 19 04:22:18 PM PDT 24 1424350000 ps
T11 /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.2333983698 Jul 19 04:23:03 PM PDT 24 Jul 19 04:23:15 PM PDT 24 1042630000 ps
T12 /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.2227256578 Jul 19 04:19:56 PM PDT 24 Jul 19 04:20:06 PM PDT 24 1509710000 ps
T13 /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.2542349597 Jul 19 04:21:33 PM PDT 24 Jul 19 04:21:44 PM PDT 24 1454950000 ps
T31 /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.2132500149 Jul 19 04:22:21 PM PDT 24 Jul 19 04:22:34 PM PDT 24 1472450000 ps
T32 /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.935240654 Jul 19 04:19:56 PM PDT 24 Jul 19 04:20:06 PM PDT 24 1518170000 ps
T33 /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.2532260166 Jul 19 04:22:44 PM PDT 24 Jul 19 04:22:53 PM PDT 24 1549630000 ps
T34 /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.3118154745 Jul 19 04:18:40 PM PDT 24 Jul 19 04:18:51 PM PDT 24 1347830000 ps
T35 /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.3980812355 Jul 19 04:19:15 PM PDT 24 Jul 19 04:19:24 PM PDT 24 1508010000 ps
T36 /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.1689071202 Jul 19 04:19:15 PM PDT 24 Jul 19 04:19:24 PM PDT 24 1340170000 ps
T37 /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.2421473090 Jul 19 04:20:03 PM PDT 24 Jul 19 04:20:14 PM PDT 24 1411550000 ps
T38 /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.333093872 Jul 19 04:22:20 PM PDT 24 Jul 19 04:22:32 PM PDT 24 1318470000 ps
T39 /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.1159762666 Jul 19 04:21:35 PM PDT 24 Jul 19 04:21:47 PM PDT 24 1507330000 ps
T40 /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.3470176929 Jul 19 04:23:08 PM PDT 24 Jul 19 04:23:31 PM PDT 24 1549570000 ps
T41 /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.439365556 Jul 19 04:22:53 PM PDT 24 Jul 19 04:23:02 PM PDT 24 1536290000 ps
T42 /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.3699438132 Jul 19 04:20:22 PM PDT 24 Jul 19 04:20:33 PM PDT 24 1544950000 ps
T43 /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.3088800814 Jul 19 04:21:24 PM PDT 24 Jul 19 04:21:34 PM PDT 24 1547710000 ps
T44 /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.2771026451 Jul 19 04:23:08 PM PDT 24 Jul 19 04:23:30 PM PDT 24 1332350000 ps
T45 /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.2337502375 Jul 19 04:22:53 PM PDT 24 Jul 19 04:23:05 PM PDT 24 1365530000 ps
T46 /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.3317754940 Jul 19 04:22:56 PM PDT 24 Jul 19 04:23:08 PM PDT 24 1607870000 ps
T47 /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.2521955832 Jul 19 04:18:38 PM PDT 24 Jul 19 04:18:50 PM PDT 24 1464230000 ps
T48 /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.3977262536 Jul 19 04:17:34 PM PDT 24 Jul 19 04:17:47 PM PDT 24 1605090000 ps
T49 /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.2009527152 Jul 19 04:22:53 PM PDT 24 Jul 19 04:23:05 PM PDT 24 1448670000 ps
T50 /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.3719484651 Jul 19 04:23:08 PM PDT 24 Jul 19 04:23:31 PM PDT 24 1486730000 ps
T51 /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.1796888981 Jul 19 04:22:55 PM PDT 24 Jul 19 04:23:07 PM PDT 24 1469550000 ps
T52 /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.3445255612 Jul 19 04:19:18 PM PDT 24 Jul 19 04:19:28 PM PDT 24 1381050000 ps
T53 /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.2719096225 Jul 19 04:22:53 PM PDT 24 Jul 19 04:23:06 PM PDT 24 1483630000 ps
T54 /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.917452999 Jul 19 04:22:22 PM PDT 24 Jul 19 04:22:35 PM PDT 24 1505990000 ps
T55 /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.329916 Jul 19 04:21:00 PM PDT 24 Jul 19 04:21:11 PM PDT 24 1586010000 ps
T56 /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.1085034868 Jul 19 04:19:18 PM PDT 24 Jul 19 04:19:27 PM PDT 24 1151650000 ps
T57 /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.1920141648 Jul 19 04:22:08 PM PDT 24 Jul 19 04:22:19 PM PDT 24 1445670000 ps
T58 /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.2719375895 Jul 19 04:20:27 PM PDT 24 Jul 19 04:20:36 PM PDT 24 1267530000 ps
T59 /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.2660756210 Jul 19 04:22:53 PM PDT 24 Jul 19 04:23:04 PM PDT 24 1255630000 ps
T60 /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.601218271 Jul 19 04:22:07 PM PDT 24 Jul 19 04:22:18 PM PDT 24 1383090000 ps
T61 /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.1216713839 Jul 19 04:22:54 PM PDT 24 Jul 19 04:23:03 PM PDT 24 1528190000 ps
T62 /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.1449427621 Jul 19 04:20:59 PM PDT 24 Jul 19 04:21:10 PM PDT 24 1512610000 ps
T63 /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.4035321234 Jul 19 04:21:22 PM PDT 24 Jul 19 04:21:31 PM PDT 24 1469950000 ps
T64 /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.3367640089 Jul 19 04:20:22 PM PDT 24 Jul 19 04:20:31 PM PDT 24 1296490000 ps
T65 /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.494579346 Jul 19 04:22:54 PM PDT 24 Jul 19 04:23:06 PM PDT 24 1547570000 ps
T66 /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.495291498 Jul 19 04:22:55 PM PDT 24 Jul 19 04:23:07 PM PDT 24 1554110000 ps
T67 /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.1269841809 Jul 19 04:22:07 PM PDT 24 Jul 19 04:22:19 PM PDT 24 1475850000 ps
T68 /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.2273237458 Jul 19 04:19:27 PM PDT 24 Jul 19 04:19:37 PM PDT 24 1213350000 ps
T69 /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.1269999989 Jul 19 04:19:19 PM PDT 24 Jul 19 04:19:29 PM PDT 24 1294310000 ps
T70 /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.1250009740 Jul 19 04:22:53 PM PDT 24 Jul 19 04:23:05 PM PDT 24 1451850000 ps
T4 /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.1623076339 Jul 19 04:17:34 PM PDT 24 Jul 19 04:56:14 PM PDT 24 337037670000 ps
T5 /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.1636682365 Jul 19 04:19:55 PM PDT 24 Jul 19 04:45:19 PM PDT 24 336704190000 ps
T6 /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.523860620 Jul 19 04:22:16 PM PDT 24 Jul 19 04:59:36 PM PDT 24 336662030000 ps
T14 /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.2103621152 Jul 19 04:22:16 PM PDT 24 Jul 19 04:59:30 PM PDT 24 336950270000 ps
T15 /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.2158190571 Jul 19 04:22:21 PM PDT 24 Jul 19 04:52:36 PM PDT 24 336336250000 ps
T16 /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.3949525300 Jul 19 04:22:53 PM PDT 24 Jul 19 04:54:07 PM PDT 24 337059010000 ps
T17 /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.2508586477 Jul 19 04:17:34 PM PDT 24 Jul 19 04:50:11 PM PDT 24 337046310000 ps
T18 /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.2605858538 Jul 19 04:21:39 PM PDT 24 Jul 19 04:49:48 PM PDT 24 336813010000 ps
T19 /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.2710147917 Jul 19 04:17:18 PM PDT 24 Jul 19 04:56:08 PM PDT 24 336536030000 ps
T20 /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3963822714 Jul 19 04:19:18 PM PDT 24 Jul 19 04:51:26 PM PDT 24 336393450000 ps
T71 /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.2931578627 Jul 19 04:21:16 PM PDT 24 Jul 19 04:52:52 PM PDT 24 336434990000 ps
T72 /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.416455111 Jul 19 04:17:21 PM PDT 24 Jul 19 04:50:49 PM PDT 24 336697830000 ps
T73 /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.945979685 Jul 19 04:23:07 PM PDT 24 Jul 19 04:52:29 PM PDT 24 336904510000 ps
T74 /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.3041084894 Jul 19 04:23:04 PM PDT 24 Jul 19 04:51:27 PM PDT 24 336647750000 ps
T75 /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.2912033512 Jul 19 04:23:08 PM PDT 24 Jul 19 04:56:14 PM PDT 24 336402930000 ps
T76 /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.1586879775 Jul 19 04:22:07 PM PDT 24 Jul 19 04:51:17 PM PDT 24 336638430000 ps
T77 /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.445972512 Jul 19 04:22:07 PM PDT 24 Jul 19 04:50:52 PM PDT 24 336906390000 ps
T78 /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.3574857207 Jul 19 04:23:04 PM PDT 24 Jul 19 04:54:30 PM PDT 24 336307770000 ps
T79 /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1222353028 Jul 19 04:21:00 PM PDT 24 Jul 19 04:53:08 PM PDT 24 336679890000 ps
T80 /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.3567282735 Jul 19 04:17:32 PM PDT 24 Jul 19 04:54:02 PM PDT 24 336897770000 ps
T81 /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.2347916142 Jul 19 04:20:46 PM PDT 24 Jul 19 04:50:16 PM PDT 24 336910350000 ps
T82 /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.4102468693 Jul 19 04:22:54 PM PDT 24 Jul 19 04:52:59 PM PDT 24 336495030000 ps
T83 /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.3793065917 Jul 19 04:21:39 PM PDT 24 Jul 19 04:50:52 PM PDT 24 336440410000 ps
T84 /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.42416840 Jul 19 04:23:48 PM PDT 24 Jul 19 04:48:51 PM PDT 24 336555470000 ps
T85 /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.1914579505 Jul 19 04:17:48 PM PDT 24 Jul 19 04:55:49 PM PDT 24 336476170000 ps
T86 /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.3590842692 Jul 19 04:22:57 PM PDT 24 Jul 19 04:52:31 PM PDT 24 336362530000 ps
T87 /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.2362036393 Jul 19 04:22:31 PM PDT 24 Jul 19 04:54:31 PM PDT 24 336915770000 ps
T88 /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.1729741882 Jul 19 04:22:53 PM PDT 24 Jul 19 04:53:48 PM PDT 24 336592830000 ps
T89 /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2134786088 Jul 19 04:23:06 PM PDT 24 Jul 19 04:52:38 PM PDT 24 336558810000 ps
T90 /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.906796593 Jul 19 04:23:11 PM PDT 24 Jul 19 04:55:23 PM PDT 24 336744470000 ps
T91 /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.1690828843 Jul 19 04:17:11 PM PDT 24 Jul 19 04:54:05 PM PDT 24 336752190000 ps
T92 /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.3328007697 Jul 19 04:22:41 PM PDT 24 Jul 19 04:55:20 PM PDT 24 337059450000 ps
T93 /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.1405377740 Jul 19 04:21:14 PM PDT 24 Jul 19 04:54:35 PM PDT 24 336476690000 ps
T94 /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.2313860105 Jul 19 04:23:46 PM PDT 24 Jul 19 04:58:03 PM PDT 24 336885770000 ps
T95 /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.3312377678 Jul 19 04:18:23 PM PDT 24 Jul 19 04:51:33 PM PDT 24 336942470000 ps
T96 /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.1179521788 Jul 19 04:22:38 PM PDT 24 Jul 19 04:46:19 PM PDT 24 336949210000 ps
T97 /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.776779469 Jul 19 04:21:46 PM PDT 24 Jul 19 04:54:22 PM PDT 24 336891050000 ps
T98 /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.79973527 Jul 19 04:23:03 PM PDT 24 Jul 19 04:51:09 PM PDT 24 336825830000 ps
T99 /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.1022792900 Jul 19 04:17:52 PM PDT 24 Jul 19 04:56:26 PM PDT 24 336646050000 ps
T100 /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.2512921319 Jul 19 04:22:57 PM PDT 24 Jul 19 04:50:37 PM PDT 24 336733490000 ps
T101 /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.3464826127 Jul 19 04:19:15 PM PDT 24 Jul 19 04:48:53 PM PDT 24 336448110000 ps
T102 /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.1396277182 Jul 19 04:22:31 PM PDT 24 Jul 19 04:54:42 PM PDT 24 336781290000 ps
T103 /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.1019539235 Jul 19 04:21:56 PM PDT 24 Jul 19 05:00:29 PM PDT 24 336954910000 ps
T104 /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.3326903778 Jul 19 04:22:41 PM PDT 24 Jul 19 04:55:43 PM PDT 24 336396470000 ps
T105 /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.354125814 Jul 19 04:23:03 PM PDT 24 Jul 19 04:51:11 PM PDT 24 336667270000 ps
T106 /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.2274059109 Jul 19 04:23:11 PM PDT 24 Jul 19 04:55:29 PM PDT 24 336919070000 ps
T107 /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.1269968380 Jul 19 04:21:00 PM PDT 24 Jul 19 04:53:14 PM PDT 24 336777250000 ps
T108 /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.4155606835 Jul 19 04:23:08 PM PDT 24 Jul 19 04:55:38 PM PDT 24 336787290000 ps
T109 /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.1070575235 Jul 19 04:22:17 PM PDT 24 Jul 19 04:59:26 PM PDT 24 336334770000 ps
T110 /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.2652403767 Jul 19 04:22:31 PM PDT 24 Jul 19 04:53:30 PM PDT 24 336647890000 ps
T111 /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.108865708 Jul 19 04:32:08 PM PDT 24 Jul 19 04:32:16 PM PDT 24 1441110000 ps
T112 /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.2460852652 Jul 19 04:32:07 PM PDT 24 Jul 19 04:32:16 PM PDT 24 1462030000 ps
T113 /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.3364862399 Jul 19 04:32:32 PM PDT 24 Jul 19 04:32:46 PM PDT 24 1370430000 ps
T114 /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.1371698199 Jul 19 04:32:18 PM PDT 24 Jul 19 04:32:30 PM PDT 24 1560910000 ps
T115 /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.1789879059 Jul 19 04:32:14 PM PDT 24 Jul 19 04:32:23 PM PDT 24 1631270000 ps
T116 /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.1502093144 Jul 19 04:32:21 PM PDT 24 Jul 19 04:32:34 PM PDT 24 1585030000 ps
T117 /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.955549681 Jul 19 04:32:17 PM PDT 24 Jul 19 04:32:30 PM PDT 24 1535210000 ps
T118 /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.1063225872 Jul 19 04:32:20 PM PDT 24 Jul 19 04:32:32 PM PDT 24 1446030000 ps
T119 /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.2165252840 Jul 19 04:32:09 PM PDT 24 Jul 19 04:32:21 PM PDT 24 1525750000 ps
T120 /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.433899300 Jul 19 04:32:06 PM PDT 24 Jul 19 04:32:18 PM PDT 24 1514070000 ps
T121 /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.4122411392 Jul 19 04:32:22 PM PDT 24 Jul 19 04:32:36 PM PDT 24 1396510000 ps
T122 /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1172899726 Jul 19 04:32:26 PM PDT 24 Jul 19 04:32:35 PM PDT 24 1491750000 ps
T123 /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.1636680550 Jul 19 04:32:18 PM PDT 24 Jul 19 04:32:25 PM PDT 24 1381690000 ps
T124 /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.4176740242 Jul 19 04:32:10 PM PDT 24 Jul 19 04:32:17 PM PDT 24 1089590000 ps
T125 /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.1431911963 Jul 19 04:32:18 PM PDT 24 Jul 19 04:32:27 PM PDT 24 1412270000 ps
T126 /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.2521856482 Jul 19 04:32:13 PM PDT 24 Jul 19 04:32:23 PM PDT 24 1432470000 ps
T127 /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.3443172961 Jul 19 04:32:16 PM PDT 24 Jul 19 04:32:25 PM PDT 24 1520810000 ps
T128 /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.538822211 Jul 19 04:32:13 PM PDT 24 Jul 19 04:32:22 PM PDT 24 1586550000 ps
T129 /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.1163041889 Jul 19 04:32:38 PM PDT 24 Jul 19 04:32:53 PM PDT 24 1308670000 ps
T130 /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.2195579945 Jul 19 04:32:22 PM PDT 24 Jul 19 04:32:34 PM PDT 24 1494330000 ps
T131 /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.2758547698 Jul 19 04:32:20 PM PDT 24 Jul 19 04:32:32 PM PDT 24 1322110000 ps
T132 /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.288057847 Jul 19 04:32:22 PM PDT 24 Jul 19 04:32:36 PM PDT 24 1470410000 ps
T133 /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1003970128 Jul 19 04:32:21 PM PDT 24 Jul 19 04:32:37 PM PDT 24 1536230000 ps
T134 /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.3735971831 Jul 19 04:32:12 PM PDT 24 Jul 19 04:32:20 PM PDT 24 1257590000 ps
T135 /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.3160668965 Jul 19 04:32:22 PM PDT 24 Jul 19 04:32:36 PM PDT 24 1569810000 ps
T136 /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.10233401 Jul 19 04:32:21 PM PDT 24 Jul 19 04:32:35 PM PDT 24 1545010000 ps
T137 /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.2919969901 Jul 19 04:32:08 PM PDT 24 Jul 19 04:32:19 PM PDT 24 1541110000 ps
T138 /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.851824210 Jul 19 04:32:12 PM PDT 24 Jul 19 04:32:19 PM PDT 24 1192650000 ps
T139 /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.635504869 Jul 19 04:32:12 PM PDT 24 Jul 19 04:32:20 PM PDT 24 1400490000 ps
T140 /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.2865461500 Jul 19 04:32:21 PM PDT 24 Jul 19 04:32:36 PM PDT 24 1529850000 ps
T141 /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.2411310350 Jul 19 04:32:20 PM PDT 24 Jul 19 04:32:32 PM PDT 24 1564390000 ps
T142 /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.1503474039 Jul 19 04:32:07 PM PDT 24 Jul 19 04:32:15 PM PDT 24 1339510000 ps
T143 /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.3708035694 Jul 19 04:32:11 PM PDT 24 Jul 19 04:32:22 PM PDT 24 1474890000 ps
T144 /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.3550239107 Jul 19 04:32:18 PM PDT 24 Jul 19 04:32:30 PM PDT 24 1474630000 ps
T145 /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.3017899971 Jul 19 04:32:22 PM PDT 24 Jul 19 04:32:33 PM PDT 24 1369250000 ps
T146 /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.1264582098 Jul 19 04:32:20 PM PDT 24 Jul 19 04:32:33 PM PDT 24 1219750000 ps
T147 /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.1946946931 Jul 19 04:32:20 PM PDT 24 Jul 19 04:32:32 PM PDT 24 1468190000 ps
T148 /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.3985142145 Jul 19 04:32:20 PM PDT 24 Jul 19 04:32:30 PM PDT 24 1300170000 ps
T149 /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.3368907078 Jul 19 04:32:12 PM PDT 24 Jul 19 04:32:21 PM PDT 24 1055430000 ps
T150 /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.2463689571 Jul 19 04:32:30 PM PDT 24 Jul 19 04:32:42 PM PDT 24 1379970000 ps
T151 /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.1332673607 Jul 19 04:32:11 PM PDT 24 Jul 19 04:32:20 PM PDT 24 1531670000 ps
T152 /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.3632172493 Jul 19 04:32:19 PM PDT 24 Jul 19 04:32:30 PM PDT 24 1391050000 ps
T153 /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.3424449367 Jul 19 04:32:21 PM PDT 24 Jul 19 04:32:34 PM PDT 24 1474950000 ps
T154 /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.3589103300 Jul 19 04:32:20 PM PDT 24 Jul 19 04:32:32 PM PDT 24 1469530000 ps
T155 /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.3389450104 Jul 19 04:32:05 PM PDT 24 Jul 19 04:32:14 PM PDT 24 1323210000 ps
T156 /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.4268211358 Jul 19 04:32:18 PM PDT 24 Jul 19 04:32:27 PM PDT 24 1302450000 ps
T157 /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.1749096653 Jul 19 04:32:13 PM PDT 24 Jul 19 04:32:22 PM PDT 24 1581530000 ps
T158 /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.1053243948 Jul 19 04:32:23 PM PDT 24 Jul 19 04:32:36 PM PDT 24 1522090000 ps
T159 /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.45426351 Jul 19 04:32:11 PM PDT 24 Jul 19 04:32:21 PM PDT 24 1392510000 ps
T160 /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.2634198739 Jul 19 04:32:13 PM PDT 24 Jul 19 04:32:21 PM PDT 24 1383430000 ps
T21 /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.3531092691 Jul 19 04:32:16 PM PDT 24 Jul 19 05:01:02 PM PDT 24 337137830000 ps
T22 /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.193206908 Jul 19 04:32:28 PM PDT 24 Jul 19 05:03:54 PM PDT 24 336409930000 ps
T23 /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.1773389306 Jul 19 04:32:19 PM PDT 24 Jul 19 05:08:41 PM PDT 24 336730950000 ps
T24 /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.3620689019 Jul 19 04:32:30 PM PDT 24 Jul 19 05:03:15 PM PDT 24 336706710000 ps
T25 /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.1291892515 Jul 19 04:32:18 PM PDT 24 Jul 19 05:04:29 PM PDT 24 336523950000 ps
T26 /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.1252701586 Jul 19 04:32:29 PM PDT 24 Jul 19 05:03:01 PM PDT 24 336668750000 ps
T27 /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.2253119388 Jul 19 04:32:20 PM PDT 24 Jul 19 05:05:24 PM PDT 24 336713230000 ps
T28 /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.1737350564 Jul 19 04:32:20 PM PDT 24 Jul 19 05:02:58 PM PDT 24 336585230000 ps
T29 /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.3217187592 Jul 19 04:32:34 PM PDT 24 Jul 19 05:06:44 PM PDT 24 336422850000 ps
T30 /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.552055417 Jul 19 04:32:29 PM PDT 24 Jul 19 05:05:45 PM PDT 24 336497970000 ps
T161 /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.479217945 Jul 19 04:32:22 PM PDT 24 Jul 19 05:06:33 PM PDT 24 336520130000 ps
T162 /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.1949398259 Jul 19 04:32:25 PM PDT 24 Jul 19 05:03:41 PM PDT 24 336683010000 ps
T163 /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.874294041 Jul 19 04:32:20 PM PDT 24 Jul 19 05:00:37 PM PDT 24 336803830000 ps
T164 /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.4216908446 Jul 19 04:32:30 PM PDT 24 Jul 19 05:06:13 PM PDT 24 336927610000 ps
T165 /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.2388358559 Jul 19 04:32:24 PM PDT 24 Jul 19 05:02:30 PM PDT 24 337174890000 ps
T166 /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.3227683191 Jul 19 04:32:34 PM PDT 24 Jul 19 05:04:32 PM PDT 24 336745090000 ps
T167 /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.2285107759 Jul 19 04:32:19 PM PDT 24 Jul 19 05:05:06 PM PDT 24 336335010000 ps
T168 /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.1542125325 Jul 19 04:32:26 PM PDT 24 Jul 19 05:10:48 PM PDT 24 336924250000 ps
T169 /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.2233474985 Jul 19 04:32:29 PM PDT 24 Jul 19 05:03:09 PM PDT 24 336482130000 ps
T170 /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.1766285205 Jul 19 04:32:25 PM PDT 24 Jul 19 05:08:06 PM PDT 24 336952490000 ps
T171 /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.974685203 Jul 19 04:32:25 PM PDT 24 Jul 19 05:00:40 PM PDT 24 336367450000 ps
T172 /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.2609359373 Jul 19 04:32:19 PM PDT 24 Jul 19 05:01:26 PM PDT 24 336829750000 ps
T173 /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.577732827 Jul 19 04:32:22 PM PDT 24 Jul 19 04:59:51 PM PDT 24 336975890000 ps
T174 /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.2142886333 Jul 19 04:32:18 PM PDT 24 Jul 19 05:03:04 PM PDT 24 336879690000 ps
T175 /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.3729141381 Jul 19 04:32:28 PM PDT 24 Jul 19 05:06:17 PM PDT 24 337081170000 ps
T176 /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.3433846970 Jul 19 04:32:28 PM PDT 24 Jul 19 05:04:54 PM PDT 24 336932830000 ps
T177 /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.1472200408 Jul 19 04:32:27 PM PDT 24 Jul 19 05:12:11 PM PDT 24 336888470000 ps
T178 /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.431251918 Jul 19 04:32:34 PM PDT 24 Jul 19 05:03:17 PM PDT 24 336370550000 ps
T179 /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.2221034373 Jul 19 04:32:22 PM PDT 24 Jul 19 05:06:39 PM PDT 24 336486530000 ps
T180 /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.2587221066 Jul 19 04:32:23 PM PDT 24 Jul 19 05:10:49 PM PDT 24 336921870000 ps
T181 /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.3445395963 Jul 19 04:32:23 PM PDT 24 Jul 19 04:59:41 PM PDT 24 336817190000 ps
T182 /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.3772932316 Jul 19 04:32:28 PM PDT 24 Jul 19 05:03:13 PM PDT 24 336921310000 ps
T183 /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.223927756 Jul 19 04:32:18 PM PDT 24 Jul 19 05:03:04 PM PDT 24 336617750000 ps
T184 /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.3617299060 Jul 19 04:32:20 PM PDT 24 Jul 19 05:02:45 PM PDT 24 336853770000 ps
T185 /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.58290608 Jul 19 04:32:18 PM PDT 24 Jul 19 04:59:09 PM PDT 24 336545070000 ps
T186 /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.1253648979 Jul 19 04:32:20 PM PDT 24 Jul 19 05:02:54 PM PDT 24 336476990000 ps
T187 /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.2109553475 Jul 19 04:32:18 PM PDT 24 Jul 19 05:05:41 PM PDT 24 336514710000 ps
T188 /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.4137191336 Jul 19 04:32:21 PM PDT 24 Jul 19 05:05:07 PM PDT 24 336445270000 ps
T189 /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.1643621038 Jul 19 04:32:26 PM PDT 24 Jul 19 05:01:03 PM PDT 24 336926150000 ps
T190 /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.290029437 Jul 19 04:32:33 PM PDT 24 Jul 19 05:06:16 PM PDT 24 336413870000 ps
T191 /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.1171960659 Jul 19 04:32:20 PM PDT 24 Jul 19 05:02:20 PM PDT 24 336576990000 ps
T192 /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.3029150727 Jul 19 04:32:30 PM PDT 24 Jul 19 05:05:43 PM PDT 24 337134870000 ps
T193 /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.999164943 Jul 19 04:32:19 PM PDT 24 Jul 19 04:59:03 PM PDT 24 336645530000 ps
T194 /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.2079529731 Jul 19 04:32:29 PM PDT 24 Jul 19 05:01:05 PM PDT 24 337000530000 ps
T195 /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.1931142499 Jul 19 04:32:23 PM PDT 24 Jul 19 05:12:15 PM PDT 24 336721610000 ps
T196 /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.439000800 Jul 19 04:32:42 PM PDT 24 Jul 19 05:04:30 PM PDT 24 336916270000 ps
T197 /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.1117835791 Jul 19 04:32:45 PM PDT 24 Jul 19 05:04:51 PM PDT 24 337077710000 ps
T198 /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.959581134 Jul 19 04:32:26 PM PDT 24 Jul 19 05:02:21 PM PDT 24 336759930000 ps
T199 /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.881944043 Jul 19 04:32:26 PM PDT 24 Jul 19 05:01:56 PM PDT 24 336362730000 ps
T200 /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.2222937660 Jul 19 04:32:27 PM PDT 24 Jul 19 05:12:05 PM PDT 24 336615110000 ps

Test location /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.718774369
Short name T3
Test name
Test status
Simulation time 1423510000 ps
CPU time 4.62 seconds
Started Jul 19 04:22:28 PM PDT 24
Finished Jul 19 04:22:39 PM PDT 24
Peak memory 165044 kb
Host smart-13566f16-8db9-49f0-a3a4-7afa4f7aa07a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=718774369 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.718774369
Directory /workspace/18.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.2508586477
Short name T17
Test name
Test status
Simulation time 337046310000 ps
CPU time 796.91 seconds
Started Jul 19 04:17:34 PM PDT 24
Finished Jul 19 04:50:11 PM PDT 24
Peak memory 160884 kb
Host smart-69a6c39c-635b-4808-b35c-c474297e3e78
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2508586477 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.2508586477
Directory /workspace/11.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.1737350564
Short name T28
Test name
Test status
Simulation time 336585230000 ps
CPU time 751.86 seconds
Started Jul 19 04:32:20 PM PDT 24
Finished Jul 19 05:02:58 PM PDT 24
Peak memory 160712 kb
Host smart-88ebcd0f-28c4-4f27-a3c1-5dd618722d4c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1737350564 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.1737350564
Directory /workspace/13.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.3326903778
Short name T104
Test name
Test status
Simulation time 336396470000 ps
CPU time 809.23 seconds
Started Jul 19 04:22:41 PM PDT 24
Finished Jul 19 04:55:43 PM PDT 24
Peak memory 160244 kb
Host smart-7d575b6f-1a81-4a69-85d7-e142c1974c37
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3326903778 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.3326903778
Directory /workspace/0.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.4155606835
Short name T108
Test name
Test status
Simulation time 336787290000 ps
CPU time 769.12 seconds
Started Jul 19 04:23:08 PM PDT 24
Finished Jul 19 04:55:38 PM PDT 24
Peak memory 160532 kb
Host smart-16353ed9-b262-44c1-86ba-fe686795cfc7
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4155606835 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.4155606835
Directory /workspace/1.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.416455111
Short name T72
Test name
Test status
Simulation time 336697830000 ps
CPU time 822.05 seconds
Started Jul 19 04:17:21 PM PDT 24
Finished Jul 19 04:50:49 PM PDT 24
Peak memory 160876 kb
Host smart-b8427e09-523c-4a03-bf63-92e89f885186
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=416455111 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.416455111
Directory /workspace/10.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.2931578627
Short name T71
Test name
Test status
Simulation time 336434990000 ps
CPU time 768.11 seconds
Started Jul 19 04:21:16 PM PDT 24
Finished Jul 19 04:52:52 PM PDT 24
Peak memory 160884 kb
Host smart-bfc7d570-a3aa-4e50-aa38-5da9997b0527
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2931578627 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.2931578627
Directory /workspace/12.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.2512921319
Short name T100
Test name
Test status
Simulation time 336733490000 ps
CPU time 676.18 seconds
Started Jul 19 04:22:57 PM PDT 24
Finished Jul 19 04:50:37 PM PDT 24
Peak memory 159732 kb
Host smart-871425df-8027-4254-ab61-acd44ee93e58
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2512921319 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.2512921319
Directory /workspace/13.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.354125814
Short name T105
Test name
Test status
Simulation time 336667270000 ps
CPU time 686.19 seconds
Started Jul 19 04:23:03 PM PDT 24
Finished Jul 19 04:51:11 PM PDT 24
Peak memory 160624 kb
Host smart-a4717c76-6188-4b5b-aff1-e8c580f5ee87
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=354125814 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.354125814
Directory /workspace/14.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.1690828843
Short name T91
Test name
Test status
Simulation time 336752190000 ps
CPU time 890.62 seconds
Started Jul 19 04:17:11 PM PDT 24
Finished Jul 19 04:54:05 PM PDT 24
Peak memory 160860 kb
Host smart-ad91e495-5c7a-4f81-b4c7-099392ef1a12
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1690828843 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.1690828843
Directory /workspace/15.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.3041084894
Short name T74
Test name
Test status
Simulation time 336647750000 ps
CPU time 689.82 seconds
Started Jul 19 04:23:04 PM PDT 24
Finished Jul 19 04:51:27 PM PDT 24
Peak memory 160632 kb
Host smart-18233b8e-bc0b-4584-b685-8dfa3d22942b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3041084894 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.3041084894
Directory /workspace/16.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.3793065917
Short name T83
Test name
Test status
Simulation time 336440410000 ps
CPU time 698.15 seconds
Started Jul 19 04:21:39 PM PDT 24
Finished Jul 19 04:50:52 PM PDT 24
Peak memory 160840 kb
Host smart-4e214580-bba0-4fe9-ae45-4b97d1f1f084
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3793065917 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.3793065917
Directory /workspace/17.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.945979685
Short name T73
Test name
Test status
Simulation time 336904510000 ps
CPU time 715.04 seconds
Started Jul 19 04:23:07 PM PDT 24
Finished Jul 19 04:52:29 PM PDT 24
Peak memory 160432 kb
Host smart-5c84c0b5-aadd-426f-be03-dd9d3f12c534
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=945979685 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.945979685
Directory /workspace/18.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2134786088
Short name T89
Test name
Test status
Simulation time 336558810000 ps
CPU time 713.3 seconds
Started Jul 19 04:23:06 PM PDT 24
Finished Jul 19 04:52:38 PM PDT 24
Peak memory 160236 kb
Host smart-83ea09ee-9c09-4207-85d6-817d6d650efc
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2134786088 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.2134786088
Directory /workspace/19.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.4102468693
Short name T82
Test name
Test status
Simulation time 336495030000 ps
CPU time 717.69 seconds
Started Jul 19 04:22:54 PM PDT 24
Finished Jul 19 04:52:59 PM PDT 24
Peak memory 160324 kb
Host smart-61e0d0e6-623a-45f5-89a3-d98c535d824a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4102468693 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.4102468693
Directory /workspace/2.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.79973527
Short name T98
Test name
Test status
Simulation time 336825830000 ps
CPU time 689.19 seconds
Started Jul 19 04:23:03 PM PDT 24
Finished Jul 19 04:51:09 PM PDT 24
Peak memory 160564 kb
Host smart-578266be-7a94-474c-8a5b-ad523cac6e07
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=79973527 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.79973527
Directory /workspace/20.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.42416840
Short name T84
Test name
Test status
Simulation time 336555470000 ps
CPU time 588 seconds
Started Jul 19 04:23:48 PM PDT 24
Finished Jul 19 04:48:51 PM PDT 24
Peak memory 160344 kb
Host smart-c264a21b-57fb-4521-88f3-e89a4405efa1
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=42416840 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.42416840
Directory /workspace/21.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.2710147917
Short name T19
Test name
Test status
Simulation time 336536030000 ps
CPU time 942.74 seconds
Started Jul 19 04:17:18 PM PDT 24
Finished Jul 19 04:56:08 PM PDT 24
Peak memory 160896 kb
Host smart-4c56016c-f7af-4387-8beb-7761203a0ecc
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2710147917 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.2710147917
Directory /workspace/22.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.3590842692
Short name T86
Test name
Test status
Simulation time 336362530000 ps
CPU time 724.21 seconds
Started Jul 19 04:22:57 PM PDT 24
Finished Jul 19 04:52:31 PM PDT 24
Peak memory 160396 kb
Host smart-e9c75835-d849-4a6c-8e6a-466930b57c48
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3590842692 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.3590842692
Directory /workspace/23.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.2313860105
Short name T94
Test name
Test status
Simulation time 336885770000 ps
CPU time 811.44 seconds
Started Jul 19 04:23:46 PM PDT 24
Finished Jul 19 04:58:03 PM PDT 24
Peak memory 160364 kb
Host smart-27f87aa6-779f-47ae-b012-4f6d3913d7f0
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2313860105 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.2313860105
Directory /workspace/24.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.1269968380
Short name T107
Test name
Test status
Simulation time 336777250000 ps
CPU time 786.44 seconds
Started Jul 19 04:21:00 PM PDT 24
Finished Jul 19 04:53:14 PM PDT 24
Peak memory 160524 kb
Host smart-922dc13a-e728-447d-9967-555d0f7ce771
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1269968380 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.1269968380
Directory /workspace/25.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1222353028
Short name T79
Test name
Test status
Simulation time 336679890000 ps
CPU time 775.81 seconds
Started Jul 19 04:21:00 PM PDT 24
Finished Jul 19 04:53:08 PM PDT 24
Peak memory 160596 kb
Host smart-9de122f1-a995-4400-8f0f-082b5e553245
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1222353028 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.1222353028
Directory /workspace/26.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.2274059109
Short name T106
Test name
Test status
Simulation time 336919070000 ps
CPU time 775.69 seconds
Started Jul 19 04:23:11 PM PDT 24
Finished Jul 19 04:55:29 PM PDT 24
Peak memory 160660 kb
Host smart-96ceecc9-f3d0-4d1e-b382-67a0e65e41e6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2274059109 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.2274059109
Directory /workspace/27.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.2912033512
Short name T75
Test name
Test status
Simulation time 336402930000 ps
CPU time 786.92 seconds
Started Jul 19 04:23:08 PM PDT 24
Finished Jul 19 04:56:14 PM PDT 24
Peak memory 160560 kb
Host smart-23a9e3cf-ddf8-46c4-9960-1ca61b0e2da9
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2912033512 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.2912033512
Directory /workspace/28.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.906796593
Short name T90
Test name
Test status
Simulation time 336744470000 ps
CPU time 775.84 seconds
Started Jul 19 04:23:11 PM PDT 24
Finished Jul 19 04:55:23 PM PDT 24
Peak memory 160660 kb
Host smart-317a2159-642e-4f0b-a6d5-12352a1b4664
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=906796593 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.906796593
Directory /workspace/29.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.1179521788
Short name T96
Test name
Test status
Simulation time 336949210000 ps
CPU time 572.76 seconds
Started Jul 19 04:22:38 PM PDT 24
Finished Jul 19 04:46:19 PM PDT 24
Peak memory 159384 kb
Host smart-7ee34059-080a-4541-9784-1853920d4a51
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1179521788 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.1179521788
Directory /workspace/3.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3963822714
Short name T20
Test name
Test status
Simulation time 336393450000 ps
CPU time 778.73 seconds
Started Jul 19 04:19:18 PM PDT 24
Finished Jul 19 04:51:26 PM PDT 24
Peak memory 160148 kb
Host smart-7afcbb1e-d9b8-4d56-8f03-18cdba5e87c3
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3963822714 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.3963822714
Directory /workspace/30.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.2103621152
Short name T14
Test name
Test status
Simulation time 336950270000 ps
CPU time 884.37 seconds
Started Jul 19 04:22:16 PM PDT 24
Finished Jul 19 04:59:30 PM PDT 24
Peak memory 160596 kb
Host smart-fda7b0e6-0d8a-412c-b290-f7a0c5c8d82e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2103621152 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.2103621152
Directory /workspace/31.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.3464826127
Short name T101
Test name
Test status
Simulation time 336448110000 ps
CPU time 713.14 seconds
Started Jul 19 04:19:15 PM PDT 24
Finished Jul 19 04:48:53 PM PDT 24
Peak memory 160840 kb
Host smart-6c6315f2-984b-40ed-8a31-799eac47ab97
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3464826127 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.3464826127
Directory /workspace/32.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.3574857207
Short name T78
Test name
Test status
Simulation time 336307770000 ps
CPU time 766.33 seconds
Started Jul 19 04:23:04 PM PDT 24
Finished Jul 19 04:54:30 PM PDT 24
Peak memory 160292 kb
Host smart-2714da00-46a8-4fb2-932a-d91de6531831
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3574857207 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.3574857207
Directory /workspace/33.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.1914579505
Short name T85
Test name
Test status
Simulation time 336476170000 ps
CPU time 918.33 seconds
Started Jul 19 04:17:48 PM PDT 24
Finished Jul 19 04:55:49 PM PDT 24
Peak memory 160896 kb
Host smart-0bc11731-9f52-49f8-8cda-abf3779d1a0c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1914579505 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.1914579505
Directory /workspace/34.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.3949525300
Short name T16
Test name
Test status
Simulation time 337059010000 ps
CPU time 760.77 seconds
Started Jul 19 04:22:53 PM PDT 24
Finished Jul 19 04:54:07 PM PDT 24
Peak memory 158848 kb
Host smart-fa893d89-191c-4148-8980-f7ae1c8cca7e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3949525300 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.3949525300
Directory /workspace/35.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.1405377740
Short name T93
Test name
Test status
Simulation time 336476690000 ps
CPU time 804.41 seconds
Started Jul 19 04:21:14 PM PDT 24
Finished Jul 19 04:54:35 PM PDT 24
Peak memory 160652 kb
Host smart-a65ed4c7-e36b-4670-a057-e3b2a5a6fcb2
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1405377740 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.1405377740
Directory /workspace/36.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.1019539235
Short name T103
Test name
Test status
Simulation time 336954910000 ps
CPU time 944.16 seconds
Started Jul 19 04:21:56 PM PDT 24
Finished Jul 19 05:00:29 PM PDT 24
Peak memory 160596 kb
Host smart-021fb9aa-b8fc-4d6c-a670-7dac6c3847c6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1019539235 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.1019539235
Directory /workspace/37.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.445972512
Short name T77
Test name
Test status
Simulation time 336906390000 ps
CPU time 694.61 seconds
Started Jul 19 04:22:07 PM PDT 24
Finished Jul 19 04:50:52 PM PDT 24
Peak memory 159012 kb
Host smart-087c3f23-1c96-4ffb-a5e9-01c5c9db62f9
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=445972512 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.445972512
Directory /workspace/38.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.3567282735
Short name T80
Test name
Test status
Simulation time 336897770000 ps
CPU time 882.71 seconds
Started Jul 19 04:17:32 PM PDT 24
Finished Jul 19 04:54:02 PM PDT 24
Peak memory 160860 kb
Host smart-0af86a8a-272f-4f28-bcf2-f4d11ce5ef5e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3567282735 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.3567282735
Directory /workspace/39.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.3328007697
Short name T92
Test name
Test status
Simulation time 337059450000 ps
CPU time 797.67 seconds
Started Jul 19 04:22:41 PM PDT 24
Finished Jul 19 04:55:20 PM PDT 24
Peak memory 160244 kb
Host smart-44cc2ad7-d333-4a94-bfaf-5d307b22127b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3328007697 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.3328007697
Directory /workspace/4.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.1636682365
Short name T5
Test name
Test status
Simulation time 336704190000 ps
CPU time 619.32 seconds
Started Jul 19 04:19:55 PM PDT 24
Finished Jul 19 04:45:19 PM PDT 24
Peak memory 160152 kb
Host smart-63246550-aa98-49f5-afcc-b113b9b0fc7f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1636682365 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.1636682365
Directory /workspace/40.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.1070575235
Short name T109
Test name
Test status
Simulation time 336334770000 ps
CPU time 893.78 seconds
Started Jul 19 04:22:17 PM PDT 24
Finished Jul 19 04:59:26 PM PDT 24
Peak memory 160564 kb
Host smart-dd57ab03-49bf-4e3d-97c2-1824afec7492
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1070575235 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.1070575235
Directory /workspace/41.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.523860620
Short name T6
Test name
Test status
Simulation time 336662030000 ps
CPU time 891.29 seconds
Started Jul 19 04:22:16 PM PDT 24
Finished Jul 19 04:59:36 PM PDT 24
Peak memory 160596 kb
Host smart-ba76f69b-e6e3-4370-8701-77329cdcb6fd
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=523860620 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.523860620
Directory /workspace/42.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.2605858538
Short name T18
Test name
Test status
Simulation time 336813010000 ps
CPU time 684.25 seconds
Started Jul 19 04:21:39 PM PDT 24
Finished Jul 19 04:49:48 PM PDT 24
Peak memory 160628 kb
Host smart-da903dc3-4af7-4b70-89b4-768714148486
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2605858538 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.2605858538
Directory /workspace/43.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.1729741882
Short name T88
Test name
Test status
Simulation time 336592830000 ps
CPU time 756.91 seconds
Started Jul 19 04:22:53 PM PDT 24
Finished Jul 19 04:53:48 PM PDT 24
Peak memory 158844 kb
Host smart-bf85eea5-64b3-4c05-bcf3-27a52f8335db
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1729741882 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.1729741882
Directory /workspace/44.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.3312377678
Short name T95
Test name
Test status
Simulation time 336942470000 ps
CPU time 811.56 seconds
Started Jul 19 04:18:23 PM PDT 24
Finished Jul 19 04:51:33 PM PDT 24
Peak memory 160884 kb
Host smart-454b9ffa-bddb-4dec-9a9f-6db794fa74fc
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3312377678 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.3312377678
Directory /workspace/45.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.1623076339
Short name T4
Test name
Test status
Simulation time 337037670000 ps
CPU time 935.02 seconds
Started Jul 19 04:17:34 PM PDT 24
Finished Jul 19 04:56:14 PM PDT 24
Peak memory 160896 kb
Host smart-81313453-8225-4f5d-b8ef-400e161b1d4c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1623076339 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.1623076339
Directory /workspace/46.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.1022792900
Short name T99
Test name
Test status
Simulation time 336646050000 ps
CPU time 934.93 seconds
Started Jul 19 04:17:52 PM PDT 24
Finished Jul 19 04:56:26 PM PDT 24
Peak memory 160896 kb
Host smart-86bbd16d-e144-4c7b-9255-6eef5ddc90b1
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1022792900 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.1022792900
Directory /workspace/47.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.1586879775
Short name T76
Test name
Test status
Simulation time 336638430000 ps
CPU time 701.32 seconds
Started Jul 19 04:22:07 PM PDT 24
Finished Jul 19 04:51:17 PM PDT 24
Peak memory 158760 kb
Host smart-f5fc6e20-147a-495b-972e-ca96e6935808
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1586879775 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.1586879775
Directory /workspace/48.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.2158190571
Short name T15
Test name
Test status
Simulation time 336336250000 ps
CPU time 726.73 seconds
Started Jul 19 04:22:21 PM PDT 24
Finished Jul 19 04:52:36 PM PDT 24
Peak memory 160548 kb
Host smart-0a65dfaf-f1c4-48c6-841e-057c27401a9a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2158190571 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.2158190571
Directory /workspace/49.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.1396277182
Short name T102
Test name
Test status
Simulation time 336781290000 ps
CPU time 782.69 seconds
Started Jul 19 04:22:31 PM PDT 24
Finished Jul 19 04:54:42 PM PDT 24
Peak memory 158932 kb
Host smart-6cd75625-551c-4170-8da4-a60bc8acac85
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1396277182 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.1396277182
Directory /workspace/5.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.2362036393
Short name T87
Test name
Test status
Simulation time 336915770000 ps
CPU time 776.42 seconds
Started Jul 19 04:22:31 PM PDT 24
Finished Jul 19 04:54:31 PM PDT 24
Peak memory 158848 kb
Host smart-dfbcb387-8385-4f89-934b-bc258f5e5459
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2362036393 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.2362036393
Directory /workspace/6.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.776779469
Short name T97
Test name
Test status
Simulation time 336891050000 ps
CPU time 779.64 seconds
Started Jul 19 04:21:46 PM PDT 24
Finished Jul 19 04:54:22 PM PDT 24
Peak memory 160640 kb
Host smart-cc41ec15-fe15-4818-bc45-bc78246d7d49
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=776779469 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.776779469
Directory /workspace/7.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.2652403767
Short name T110
Test name
Test status
Simulation time 336647890000 ps
CPU time 749.04 seconds
Started Jul 19 04:22:31 PM PDT 24
Finished Jul 19 04:53:30 PM PDT 24
Peak memory 159024 kb
Host smart-7d15252a-2f07-4e7b-a030-cfcc5ee69e0f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2652403767 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.2652403767
Directory /workspace/8.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.2347916142
Short name T81
Test name
Test status
Simulation time 336910350000 ps
CPU time 711.35 seconds
Started Jul 19 04:20:46 PM PDT 24
Finished Jul 19 04:50:16 PM PDT 24
Peak memory 160832 kb
Host smart-7c663e0c-00c2-4eb4-9188-2fa18e1cdfe0
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2347916142 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.2347916142
Directory /workspace/9.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.2609359373
Short name T172
Test name
Test status
Simulation time 336829750000 ps
CPU time 711.95 seconds
Started Jul 19 04:32:19 PM PDT 24
Finished Jul 19 05:01:26 PM PDT 24
Peak memory 160716 kb
Host smart-7aeef4a9-7655-49d9-8c9b-e5c3a223040a
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2609359373 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.2609359373
Directory /workspace/0.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.2388358559
Short name T165
Test name
Test status
Simulation time 337174890000 ps
CPU time 743.82 seconds
Started Jul 19 04:32:24 PM PDT 24
Finished Jul 19 05:02:30 PM PDT 24
Peak memory 160724 kb
Host smart-8f6ebb61-9da6-45df-9a0b-39dc5b6705f7
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2388358559 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.2388358559
Directory /workspace/1.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.479217945
Short name T161
Test name
Test status
Simulation time 336520130000 ps
CPU time 830.28 seconds
Started Jul 19 04:32:22 PM PDT 24
Finished Jul 19 05:06:33 PM PDT 24
Peak memory 160728 kb
Host smart-1cebcf51-a24a-45c9-8ca7-e1ef2ee58041
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=479217945 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.479217945
Directory /workspace/10.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.1766285205
Short name T170
Test name
Test status
Simulation time 336952490000 ps
CPU time 853.42 seconds
Started Jul 19 04:32:25 PM PDT 24
Finished Jul 19 05:08:06 PM PDT 24
Peak memory 160700 kb
Host smart-c8335d95-f124-4421-a66e-7c9760459642
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1766285205 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.1766285205
Directory /workspace/11.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.2587221066
Short name T180
Test name
Test status
Simulation time 336921870000 ps
CPU time 937.49 seconds
Started Jul 19 04:32:23 PM PDT 24
Finished Jul 19 05:10:49 PM PDT 24
Peak memory 160864 kb
Host smart-0dbfe9df-9bbe-4885-ba8e-c03b99100a54
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2587221066 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.2587221066
Directory /workspace/12.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.2109553475
Short name T187
Test name
Test status
Simulation time 336514710000 ps
CPU time 818.3 seconds
Started Jul 19 04:32:18 PM PDT 24
Finished Jul 19 05:05:41 PM PDT 24
Peak memory 160728 kb
Host smart-62050f83-89f0-4df8-bb70-6ce432f39131
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2109553475 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.2109553475
Directory /workspace/14.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.3217187592
Short name T29
Test name
Test status
Simulation time 336422850000 ps
CPU time 818.71 seconds
Started Jul 19 04:32:34 PM PDT 24
Finished Jul 19 05:06:44 PM PDT 24
Peak memory 160784 kb
Host smart-efaba1bc-7c3e-4478-bb23-be90d21fee4c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3217187592 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.3217187592
Directory /workspace/15.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.3729141381
Short name T175
Test name
Test status
Simulation time 337081170000 ps
CPU time 820.34 seconds
Started Jul 19 04:32:28 PM PDT 24
Finished Jul 19 05:06:17 PM PDT 24
Peak memory 160736 kb
Host smart-16442dea-d80d-4150-988e-96f569b66fa7
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3729141381 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.3729141381
Directory /workspace/16.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.974685203
Short name T171
Test name
Test status
Simulation time 336367450000 ps
CPU time 691.6 seconds
Started Jul 19 04:32:25 PM PDT 24
Finished Jul 19 05:00:40 PM PDT 24
Peak memory 160716 kb
Host smart-187b2088-cb5d-4f32-a404-70468d3ee00c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=974685203 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.974685203
Directory /workspace/17.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.3029150727
Short name T192
Test name
Test status
Simulation time 337134870000 ps
CPU time 794.88 seconds
Started Jul 19 04:32:30 PM PDT 24
Finished Jul 19 05:05:43 PM PDT 24
Peak memory 160776 kb
Host smart-282cd6ca-2f23-402e-92b7-4860205d9dad
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3029150727 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.3029150727
Directory /workspace/18.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.1472200408
Short name T177
Test name
Test status
Simulation time 336888470000 ps
CPU time 972.16 seconds
Started Jul 19 04:32:27 PM PDT 24
Finished Jul 19 05:12:11 PM PDT 24
Peak memory 160712 kb
Host smart-6160c3c8-1f38-4b7d-97be-2de553171015
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1472200408 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.1472200408
Directory /workspace/19.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.2253119388
Short name T27
Test name
Test status
Simulation time 336713230000 ps
CPU time 815.25 seconds
Started Jul 19 04:32:20 PM PDT 24
Finished Jul 19 05:05:24 PM PDT 24
Peak memory 160716 kb
Host smart-92ce3adb-6dd7-4a25-b534-adf072d8bfcd
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2253119388 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.2253119388
Directory /workspace/2.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.1542125325
Short name T168
Test name
Test status
Simulation time 336924250000 ps
CPU time 934.01 seconds
Started Jul 19 04:32:26 PM PDT 24
Finished Jul 19 05:10:48 PM PDT 24
Peak memory 160832 kb
Host smart-d6dd583a-d3f1-4563-9475-7867cac839c5
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1542125325 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.1542125325
Directory /workspace/20.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.431251918
Short name T178
Test name
Test status
Simulation time 336370550000 ps
CPU time 743.78 seconds
Started Jul 19 04:32:34 PM PDT 24
Finished Jul 19 05:03:17 PM PDT 24
Peak memory 160716 kb
Host smart-d681efe5-9214-4ff5-a0a6-9b0e1c1feeeb
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=431251918 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.431251918
Directory /workspace/21.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.4137191336
Short name T188
Test name
Test status
Simulation time 336445270000 ps
CPU time 795.5 seconds
Started Jul 19 04:32:21 PM PDT 24
Finished Jul 19 05:05:07 PM PDT 24
Peak memory 160728 kb
Host smart-679e222d-128f-4ff0-afbd-628bfbf07a96
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4137191336 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.4137191336
Directory /workspace/22.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.2142886333
Short name T174
Test name
Test status
Simulation time 336879690000 ps
CPU time 748.52 seconds
Started Jul 19 04:32:18 PM PDT 24
Finished Jul 19 05:03:04 PM PDT 24
Peak memory 160692 kb
Host smart-cec2749d-9ec7-49cd-8394-c22a4ffa09ae
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2142886333 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.2142886333
Directory /workspace/23.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.290029437
Short name T190
Test name
Test status
Simulation time 336413870000 ps
CPU time 815.75 seconds
Started Jul 19 04:32:33 PM PDT 24
Finished Jul 19 05:06:16 PM PDT 24
Peak memory 160728 kb
Host smart-218d0268-4786-419f-82c0-d3eaee79d235
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=290029437 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.290029437
Directory /workspace/24.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.552055417
Short name T30
Test name
Test status
Simulation time 336497970000 ps
CPU time 804.5 seconds
Started Jul 19 04:32:29 PM PDT 24
Finished Jul 19 05:05:45 PM PDT 24
Peak memory 160728 kb
Host smart-2bb66a0b-37cf-4785-8391-cf2d875810aa
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=552055417 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.552055417
Directory /workspace/25.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.223927756
Short name T183
Test name
Test status
Simulation time 336617750000 ps
CPU time 743.11 seconds
Started Jul 19 04:32:18 PM PDT 24
Finished Jul 19 05:03:04 PM PDT 24
Peak memory 160700 kb
Host smart-83aad500-024e-483d-984e-95ecbecc3f12
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=223927756 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.223927756
Directory /workspace/26.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.3433846970
Short name T176
Test name
Test status
Simulation time 336932830000 ps
CPU time 794.65 seconds
Started Jul 19 04:32:28 PM PDT 24
Finished Jul 19 05:04:54 PM PDT 24
Peak memory 160716 kb
Host smart-3ddb5172-4111-45fd-8c81-81b141473e8e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3433846970 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.3433846970
Directory /workspace/27.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.999164943
Short name T193
Test name
Test status
Simulation time 336645530000 ps
CPU time 644.52 seconds
Started Jul 19 04:32:19 PM PDT 24
Finished Jul 19 04:59:03 PM PDT 24
Peak memory 160716 kb
Host smart-eb89e690-7831-4e08-8754-7df01a7bc4a9
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=999164943 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.999164943
Directory /workspace/28.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.1253648979
Short name T186
Test name
Test status
Simulation time 336476990000 ps
CPU time 750.12 seconds
Started Jul 19 04:32:20 PM PDT 24
Finished Jul 19 05:02:54 PM PDT 24
Peak memory 160652 kb
Host smart-39a38813-84c7-41a5-9c15-b35fd33548bb
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1253648979 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.1253648979
Directory /workspace/29.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.2221034373
Short name T179
Test name
Test status
Simulation time 336486530000 ps
CPU time 837.92 seconds
Started Jul 19 04:32:22 PM PDT 24
Finished Jul 19 05:06:39 PM PDT 24
Peak memory 160728 kb
Host smart-f51db8e4-eeb4-4a06-ae2b-a7e176749fb8
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2221034373 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.2221034373
Directory /workspace/3.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.1171960659
Short name T191
Test name
Test status
Simulation time 336576990000 ps
CPU time 733.36 seconds
Started Jul 19 04:32:20 PM PDT 24
Finished Jul 19 05:02:20 PM PDT 24
Peak memory 160596 kb
Host smart-0872aa40-98ee-4c6b-8747-c013fb45fd2e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1171960659 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.1171960659
Directory /workspace/30.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.439000800
Short name T196
Test name
Test status
Simulation time 336916270000 ps
CPU time 777.72 seconds
Started Jul 19 04:32:42 PM PDT 24
Finished Jul 19 05:04:30 PM PDT 24
Peak memory 160724 kb
Host smart-7b2aeb3c-0650-45a3-978f-ee8067d851aa
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=439000800 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.439000800
Directory /workspace/31.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.3445395963
Short name T181
Test name
Test status
Simulation time 336817190000 ps
CPU time 660.86 seconds
Started Jul 19 04:32:23 PM PDT 24
Finished Jul 19 04:59:41 PM PDT 24
Peak memory 160748 kb
Host smart-0d4d8427-49cc-4795-9ce2-98067014d330
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3445395963 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.3445395963
Directory /workspace/32.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.1252701586
Short name T26
Test name
Test status
Simulation time 336668750000 ps
CPU time 743.6 seconds
Started Jul 19 04:32:29 PM PDT 24
Finished Jul 19 05:03:01 PM PDT 24
Peak memory 160680 kb
Host smart-ea51c5be-c71d-47f5-ab57-0a44a06d5e22
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1252701586 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.1252701586
Directory /workspace/33.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.3620689019
Short name T24
Test name
Test status
Simulation time 336706710000 ps
CPU time 746.83 seconds
Started Jul 19 04:32:30 PM PDT 24
Finished Jul 19 05:03:15 PM PDT 24
Peak memory 160696 kb
Host smart-df762843-83d1-4903-ac2d-23ad9ac45c7d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3620689019 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.3620689019
Directory /workspace/34.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.193206908
Short name T22
Test name
Test status
Simulation time 336409930000 ps
CPU time 768.9 seconds
Started Jul 19 04:32:28 PM PDT 24
Finished Jul 19 05:03:54 PM PDT 24
Peak memory 160776 kb
Host smart-cfd46dcf-d91d-4f50-a6ac-92f12ea0ff03
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=193206908 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.193206908
Directory /workspace/35.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.2233474985
Short name T169
Test name
Test status
Simulation time 336482130000 ps
CPU time 744.11 seconds
Started Jul 19 04:32:29 PM PDT 24
Finished Jul 19 05:03:09 PM PDT 24
Peak memory 160680 kb
Host smart-a638b72e-e3ae-49c5-8e5b-e26fbe12960b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2233474985 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.2233474985
Directory /workspace/36.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.881944043
Short name T199
Test name
Test status
Simulation time 336362730000 ps
CPU time 723.08 seconds
Started Jul 19 04:32:26 PM PDT 24
Finished Jul 19 05:01:56 PM PDT 24
Peak memory 160720 kb
Host smart-1fbf95dd-4f28-4a7e-8a29-70ea0d767cfa
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=881944043 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.881944043
Directory /workspace/37.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.2222937660
Short name T200
Test name
Test status
Simulation time 336615110000 ps
CPU time 966.28 seconds
Started Jul 19 04:32:27 PM PDT 24
Finished Jul 19 05:12:05 PM PDT 24
Peak memory 160712 kb
Host smart-9553815f-78a3-4b35-899a-60fd4e3027e5
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2222937660 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.2222937660
Directory /workspace/38.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.1643621038
Short name T189
Test name
Test status
Simulation time 336926150000 ps
CPU time 696.31 seconds
Started Jul 19 04:32:26 PM PDT 24
Finished Jul 19 05:01:03 PM PDT 24
Peak memory 160728 kb
Host smart-20a1fe62-a402-449d-b48b-38371226fe0d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1643621038 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.1643621038
Directory /workspace/39.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.874294041
Short name T163
Test name
Test status
Simulation time 336803830000 ps
CPU time 692.61 seconds
Started Jul 19 04:32:20 PM PDT 24
Finished Jul 19 05:00:37 PM PDT 24
Peak memory 160712 kb
Host smart-958b666d-9aff-4211-8b31-7ddcc483a18a
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=874294041 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.874294041
Directory /workspace/4.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.959581134
Short name T198
Test name
Test status
Simulation time 336759930000 ps
CPU time 737.49 seconds
Started Jul 19 04:32:26 PM PDT 24
Finished Jul 19 05:02:21 PM PDT 24
Peak memory 160728 kb
Host smart-bb328d2c-49f4-46eb-86fd-ef80ef9fb9e5
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=959581134 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.959581134
Directory /workspace/40.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.3531092691
Short name T21
Test name
Test status
Simulation time 337137830000 ps
CPU time 703.55 seconds
Started Jul 19 04:32:16 PM PDT 24
Finished Jul 19 05:01:02 PM PDT 24
Peak memory 160716 kb
Host smart-b25c6a82-6bf8-4662-8994-3f99239e5196
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3531092691 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.3531092691
Directory /workspace/41.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.1291892515
Short name T25
Test name
Test status
Simulation time 336523950000 ps
CPU time 782.21 seconds
Started Jul 19 04:32:18 PM PDT 24
Finished Jul 19 05:04:29 PM PDT 24
Peak memory 160712 kb
Host smart-39e9504a-79e8-40ff-afbd-f7707802f2e2
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1291892515 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.1291892515
Directory /workspace/42.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.1773389306
Short name T23
Test name
Test status
Simulation time 336730950000 ps
CPU time 878.87 seconds
Started Jul 19 04:32:19 PM PDT 24
Finished Jul 19 05:08:41 PM PDT 24
Peak memory 160700 kb
Host smart-16471278-7c5e-4ffc-92b2-8758b37ea125
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1773389306 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.1773389306
Directory /workspace/43.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.4216908446
Short name T164
Test name
Test status
Simulation time 336927610000 ps
CPU time 804.23 seconds
Started Jul 19 04:32:30 PM PDT 24
Finished Jul 19 05:06:13 PM PDT 24
Peak memory 160776 kb
Host smart-abec97b1-8847-434e-992b-0979b95a2146
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4216908446 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.4216908446
Directory /workspace/44.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.1117835791
Short name T197
Test name
Test status
Simulation time 337077710000 ps
CPU time 784.51 seconds
Started Jul 19 04:32:45 PM PDT 24
Finished Jul 19 05:04:51 PM PDT 24
Peak memory 160732 kb
Host smart-1eaeaed1-83b2-441f-b2bd-72da7e29fb9b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1117835791 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.1117835791
Directory /workspace/45.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.3617299060
Short name T184
Test name
Test status
Simulation time 336853770000 ps
CPU time 746.28 seconds
Started Jul 19 04:32:20 PM PDT 24
Finished Jul 19 05:02:45 PM PDT 24
Peak memory 160712 kb
Host smart-77d21a3b-c284-4bbc-9a46-3411019f4fcd
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3617299060 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.3617299060
Directory /workspace/46.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.1949398259
Short name T162
Test name
Test status
Simulation time 336683010000 ps
CPU time 766.96 seconds
Started Jul 19 04:32:25 PM PDT 24
Finished Jul 19 05:03:41 PM PDT 24
Peak memory 160732 kb
Host smart-55273cdb-f8e2-488e-8822-8ee3e724ab14
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1949398259 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.1949398259
Directory /workspace/47.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.577732827
Short name T173
Test name
Test status
Simulation time 336975890000 ps
CPU time 673.05 seconds
Started Jul 19 04:32:22 PM PDT 24
Finished Jul 19 04:59:51 PM PDT 24
Peak memory 160652 kb
Host smart-489a0f77-cf96-4020-9a0c-ad633b2add6d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=577732827 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.577732827
Directory /workspace/48.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.3227683191
Short name T166
Test name
Test status
Simulation time 336745090000 ps
CPU time 770.04 seconds
Started Jul 19 04:32:34 PM PDT 24
Finished Jul 19 05:04:32 PM PDT 24
Peak memory 160724 kb
Host smart-f863cbb8-2105-4264-a803-60a6665d1d50
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3227683191 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.3227683191
Directory /workspace/49.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.3772932316
Short name T182
Test name
Test status
Simulation time 336921310000 ps
CPU time 733.07 seconds
Started Jul 19 04:32:28 PM PDT 24
Finished Jul 19 05:03:13 PM PDT 24
Peak memory 160768 kb
Host smart-2c943e77-01cd-4a6b-bc2f-228fe2adeb2a
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3772932316 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.3772932316
Directory /workspace/5.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.58290608
Short name T185
Test name
Test status
Simulation time 336545070000 ps
CPU time 649.43 seconds
Started Jul 19 04:32:18 PM PDT 24
Finished Jul 19 04:59:09 PM PDT 24
Peak memory 160764 kb
Host smart-796be8f0-7eea-4ac8-a96c-73737a83a135
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=58290608 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.58290608
Directory /workspace/6.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.2079529731
Short name T194
Test name
Test status
Simulation time 337000530000 ps
CPU time 702.19 seconds
Started Jul 19 04:32:29 PM PDT 24
Finished Jul 19 05:01:05 PM PDT 24
Peak memory 160728 kb
Host smart-a20e1be5-9d0c-4aa7-8a6c-1d1c6e96f67f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2079529731 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.2079529731
Directory /workspace/7.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.2285107759
Short name T167
Test name
Test status
Simulation time 336335010000 ps
CPU time 802.51 seconds
Started Jul 19 04:32:19 PM PDT 24
Finished Jul 19 05:05:06 PM PDT 24
Peak memory 160728 kb
Host smart-f5ab77e6-d7cb-4dc9-b155-f2303a7e476e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2285107759 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.2285107759
Directory /workspace/8.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.1931142499
Short name T195
Test name
Test status
Simulation time 336721610000 ps
CPU time 974.78 seconds
Started Jul 19 04:32:23 PM PDT 24
Finished Jul 19 05:12:15 PM PDT 24
Peak memory 160712 kb
Host smart-7831f471-552c-4be9-a830-328ec10bd235
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1931142499 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.1931142499
Directory /workspace/9.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.3443172961
Short name T127
Test name
Test status
Simulation time 1520810000 ps
CPU time 3.61 seconds
Started Jul 19 04:32:16 PM PDT 24
Finished Jul 19 04:32:25 PM PDT 24
Peak memory 164872 kb
Host smart-138a08ac-ccfd-428c-be4c-40fe5e5fbfd7
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3443172961 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.3443172961
Directory /workspace/0.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.3017899971
Short name T145
Test name
Test status
Simulation time 1369250000 ps
CPU time 3 seconds
Started Jul 19 04:32:22 PM PDT 24
Finished Jul 19 04:32:33 PM PDT 24
Peak memory 164876 kb
Host smart-025d1889-7292-4758-b1b6-3336dee1f063
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3017899971 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.3017899971
Directory /workspace/1.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.1636680550
Short name T123
Test name
Test status
Simulation time 1381690000 ps
CPU time 2.91 seconds
Started Jul 19 04:32:18 PM PDT 24
Finished Jul 19 04:32:25 PM PDT 24
Peak memory 164808 kb
Host smart-afd3ad6d-d758-4b81-9e5e-6e585ced74eb
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1636680550 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.1636680550
Directory /workspace/10.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.10233401
Short name T136
Test name
Test status
Simulation time 1545010000 ps
CPU time 4.49 seconds
Started Jul 19 04:32:21 PM PDT 24
Finished Jul 19 04:32:35 PM PDT 24
Peak memory 164800 kb
Host smart-bfae6dba-e19a-46fd-8903-0c7a3890f2d2
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=10233401 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.10233401
Directory /workspace/11.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.2919969901
Short name T137
Test name
Test status
Simulation time 1541110000 ps
CPU time 4.51 seconds
Started Jul 19 04:32:08 PM PDT 24
Finished Jul 19 04:32:19 PM PDT 24
Peak memory 164824 kb
Host smart-06b64a87-ab43-491e-bd30-20645a038653
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2919969901 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.2919969901
Directory /workspace/12.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.4122411392
Short name T121
Test name
Test status
Simulation time 1396510000 ps
CPU time 4.39 seconds
Started Jul 19 04:32:22 PM PDT 24
Finished Jul 19 04:32:36 PM PDT 24
Peak memory 164880 kb
Host smart-a389b418-8f64-422f-abb1-0b1441c0d4a5
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4122411392 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.4122411392
Directory /workspace/13.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.1371698199
Short name T114
Test name
Test status
Simulation time 1560910000 ps
CPU time 3.73 seconds
Started Jul 19 04:32:18 PM PDT 24
Finished Jul 19 04:32:30 PM PDT 24
Peak memory 164872 kb
Host smart-a4fcab2a-74d2-4a6f-8dea-4bf8449c462b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1371698199 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.1371698199
Directory /workspace/14.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.3985142145
Short name T148
Test name
Test status
Simulation time 1300170000 ps
CPU time 2.67 seconds
Started Jul 19 04:32:20 PM PDT 24
Finished Jul 19 04:32:30 PM PDT 24
Peak memory 164876 kb
Host smart-60bc952b-8f03-4ffb-95ac-e5ec02135927
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3985142145 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.3985142145
Directory /workspace/15.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.108865708
Short name T111
Test name
Test status
Simulation time 1441110000 ps
CPU time 3.08 seconds
Started Jul 19 04:32:08 PM PDT 24
Finished Jul 19 04:32:16 PM PDT 24
Peak memory 164800 kb
Host smart-5e0498ad-f412-4eb1-b893-a8f8a0d3e4cd
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=108865708 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.108865708
Directory /workspace/16.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.2411310350
Short name T141
Test name
Test status
Simulation time 1564390000 ps
CPU time 3.19 seconds
Started Jul 19 04:32:20 PM PDT 24
Finished Jul 19 04:32:32 PM PDT 24
Peak memory 164808 kb
Host smart-bc125d67-0ac6-4178-bbbb-4d0961a9bd27
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2411310350 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.2411310350
Directory /workspace/17.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.635504869
Short name T139
Test name
Test status
Simulation time 1400490000 ps
CPU time 3.47 seconds
Started Jul 19 04:32:12 PM PDT 24
Finished Jul 19 04:32:20 PM PDT 24
Peak memory 164824 kb
Host smart-f17dcf64-3ece-46d5-96fd-1f8a5e7b8aa9
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=635504869 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.635504869
Directory /workspace/18.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.45426351
Short name T159
Test name
Test status
Simulation time 1392510000 ps
CPU time 3.84 seconds
Started Jul 19 04:32:11 PM PDT 24
Finished Jul 19 04:32:21 PM PDT 24
Peak memory 164820 kb
Host smart-5850bde7-f417-4616-9b10-0dcb94081cd0
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=45426351 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.45426351
Directory /workspace/19.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.1264582098
Short name T146
Test name
Test status
Simulation time 1219750000 ps
CPU time 3.74 seconds
Started Jul 19 04:32:20 PM PDT 24
Finished Jul 19 04:32:33 PM PDT 24
Peak memory 164876 kb
Host smart-419c9341-065d-448c-9fd5-6d95c98524a5
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1264582098 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.1264582098
Directory /workspace/2.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.2758547698
Short name T131
Test name
Test status
Simulation time 1322110000 ps
CPU time 3.54 seconds
Started Jul 19 04:32:20 PM PDT 24
Finished Jul 19 04:32:32 PM PDT 24
Peak memory 164868 kb
Host smart-3dcce420-dcfe-46d9-bb04-9568da066580
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2758547698 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.2758547698
Directory /workspace/20.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.2521856482
Short name T126
Test name
Test status
Simulation time 1432470000 ps
CPU time 4.1 seconds
Started Jul 19 04:32:13 PM PDT 24
Finished Jul 19 04:32:23 PM PDT 24
Peak memory 164880 kb
Host smart-ca409b5f-c9f5-4445-ab9b-38985e12b28c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2521856482 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.2521856482
Directory /workspace/21.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.288057847
Short name T132
Test name
Test status
Simulation time 1470410000 ps
CPU time 4.58 seconds
Started Jul 19 04:32:22 PM PDT 24
Finished Jul 19 04:32:36 PM PDT 24
Peak memory 164876 kb
Host smart-79e7601a-5a96-426a-8e28-3e724bce3a2e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=288057847 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.288057847
Directory /workspace/22.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.4176740242
Short name T124
Test name
Test status
Simulation time 1089590000 ps
CPU time 3 seconds
Started Jul 19 04:32:10 PM PDT 24
Finished Jul 19 04:32:17 PM PDT 24
Peak memory 164876 kb
Host smart-981bcd1b-936b-4cdb-a34f-82b503a38851
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4176740242 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.4176740242
Directory /workspace/23.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.1789879059
Short name T115
Test name
Test status
Simulation time 1631270000 ps
CPU time 3.64 seconds
Started Jul 19 04:32:14 PM PDT 24
Finished Jul 19 04:32:23 PM PDT 24
Peak memory 164808 kb
Host smart-89d26465-b6c1-4a49-be26-d18d075970d6
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1789879059 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.1789879059
Directory /workspace/24.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.2865461500
Short name T140
Test name
Test status
Simulation time 1529850000 ps
CPU time 4.44 seconds
Started Jul 19 04:32:21 PM PDT 24
Finished Jul 19 04:32:36 PM PDT 24
Peak memory 164876 kb
Host smart-82a60d89-9d36-413b-8cde-3841b14287e2
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2865461500 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.2865461500
Directory /workspace/25.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.3735971831
Short name T134
Test name
Test status
Simulation time 1257590000 ps
CPU time 3.21 seconds
Started Jul 19 04:32:12 PM PDT 24
Finished Jul 19 04:32:20 PM PDT 24
Peak memory 164620 kb
Host smart-430b27bf-9b4d-49a5-8eab-0c8434216914
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3735971831 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.3735971831
Directory /workspace/26.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.433899300
Short name T120
Test name
Test status
Simulation time 1514070000 ps
CPU time 4.98 seconds
Started Jul 19 04:32:06 PM PDT 24
Finished Jul 19 04:32:18 PM PDT 24
Peak memory 164764 kb
Host smart-e3637e49-0422-4a17-add2-7df881599edd
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=433899300 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.433899300
Directory /workspace/27.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.1431911963
Short name T125
Test name
Test status
Simulation time 1412270000 ps
CPU time 3.46 seconds
Started Jul 19 04:32:18 PM PDT 24
Finished Jul 19 04:32:27 PM PDT 24
Peak memory 164872 kb
Host smart-687324ab-ac0c-4efd-a40a-454a8031d67c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1431911963 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.1431911963
Directory /workspace/28.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.3424449367
Short name T153
Test name
Test status
Simulation time 1474950000 ps
CPU time 3.53 seconds
Started Jul 19 04:32:21 PM PDT 24
Finished Jul 19 04:32:34 PM PDT 24
Peak memory 164900 kb
Host smart-a0d9a1c8-0396-471f-b028-5a7420b72649
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3424449367 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.3424449367
Directory /workspace/29.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.1749096653
Short name T157
Test name
Test status
Simulation time 1581530000 ps
CPU time 3.95 seconds
Started Jul 19 04:32:13 PM PDT 24
Finished Jul 19 04:32:22 PM PDT 24
Peak memory 164884 kb
Host smart-0b4bf0d1-a178-410e-925a-8d50ac76d304
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1749096653 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.1749096653
Directory /workspace/3.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.3389450104
Short name T155
Test name
Test status
Simulation time 1323210000 ps
CPU time 4.11 seconds
Started Jul 19 04:32:05 PM PDT 24
Finished Jul 19 04:32:14 PM PDT 24
Peak memory 164868 kb
Host smart-0236bc98-c043-480d-bd8e-30afb43e8308
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3389450104 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.3389450104
Directory /workspace/30.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.851824210
Short name T138
Test name
Test status
Simulation time 1192650000 ps
CPU time 2.98 seconds
Started Jul 19 04:32:12 PM PDT 24
Finished Jul 19 04:32:19 PM PDT 24
Peak memory 164568 kb
Host smart-7c3bc247-9de3-49f6-9aed-32f0b4aea4be
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=851824210 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.851824210
Directory /workspace/31.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.1503474039
Short name T142
Test name
Test status
Simulation time 1339510000 ps
CPU time 3.74 seconds
Started Jul 19 04:32:07 PM PDT 24
Finished Jul 19 04:32:15 PM PDT 24
Peak memory 164876 kb
Host smart-2671094a-544f-4f84-a9d2-01f75a7dbab5
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1503474039 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.1503474039
Directory /workspace/32.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.3368907078
Short name T149
Test name
Test status
Simulation time 1055430000 ps
CPU time 3.59 seconds
Started Jul 19 04:32:12 PM PDT 24
Finished Jul 19 04:32:21 PM PDT 24
Peak memory 164880 kb
Host smart-d562bd5b-cd26-4c31-b3e9-06d345d05021
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3368907078 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.3368907078
Directory /workspace/33.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.3589103300
Short name T154
Test name
Test status
Simulation time 1469530000 ps
CPU time 3.14 seconds
Started Jul 19 04:32:20 PM PDT 24
Finished Jul 19 04:32:32 PM PDT 24
Peak memory 164872 kb
Host smart-6a25718e-d735-46cd-beea-ac440fa6a9ff
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3589103300 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.3589103300
Directory /workspace/34.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.538822211
Short name T128
Test name
Test status
Simulation time 1586550000 ps
CPU time 3.7 seconds
Started Jul 19 04:32:13 PM PDT 24
Finished Jul 19 04:32:22 PM PDT 24
Peak memory 164828 kb
Host smart-506e4b11-aa7c-4df5-8a3c-85ab735d5e8d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=538822211 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.538822211
Directory /workspace/35.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.1946946931
Short name T147
Test name
Test status
Simulation time 1468190000 ps
CPU time 3.87 seconds
Started Jul 19 04:32:20 PM PDT 24
Finished Jul 19 04:32:32 PM PDT 24
Peak memory 164872 kb
Host smart-534c8333-86ae-4aef-8c15-ac74504035c8
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1946946931 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.1946946931
Directory /workspace/36.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1003970128
Short name T133
Test name
Test status
Simulation time 1536230000 ps
CPU time 5.24 seconds
Started Jul 19 04:32:21 PM PDT 24
Finished Jul 19 04:32:37 PM PDT 24
Peak memory 165028 kb
Host smart-c24a12de-87d0-44eb-b78c-48f5923a69d0
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1003970128 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.1003970128
Directory /workspace/37.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.3708035694
Short name T143
Test name
Test status
Simulation time 1474890000 ps
CPU time 4.55 seconds
Started Jul 19 04:32:11 PM PDT 24
Finished Jul 19 04:32:22 PM PDT 24
Peak memory 164744 kb
Host smart-7b4b5b5a-db6e-49c3-b811-800e2213c263
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3708035694 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.3708035694
Directory /workspace/38.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.3160668965
Short name T135
Test name
Test status
Simulation time 1569810000 ps
CPU time 4.68 seconds
Started Jul 19 04:32:22 PM PDT 24
Finished Jul 19 04:32:36 PM PDT 24
Peak memory 164880 kb
Host smart-f0e3ac19-88c7-4ac3-8123-4db72d8b5639
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3160668965 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.3160668965
Directory /workspace/39.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.2165252840
Short name T119
Test name
Test status
Simulation time 1525750000 ps
CPU time 4.86 seconds
Started Jul 19 04:32:09 PM PDT 24
Finished Jul 19 04:32:21 PM PDT 24
Peak memory 164744 kb
Host smart-9dd67b93-b870-49d6-9b64-d373818648f8
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2165252840 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.2165252840
Directory /workspace/4.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.1332673607
Short name T151
Test name
Test status
Simulation time 1531670000 ps
CPU time 3.61 seconds
Started Jul 19 04:32:11 PM PDT 24
Finished Jul 19 04:32:20 PM PDT 24
Peak memory 164880 kb
Host smart-eea8326a-d71a-445d-a085-b1d95d9efda2
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1332673607 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.1332673607
Directory /workspace/40.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.4268211358
Short name T156
Test name
Test status
Simulation time 1302450000 ps
CPU time 3.46 seconds
Started Jul 19 04:32:18 PM PDT 24
Finished Jul 19 04:32:27 PM PDT 24
Peak memory 164872 kb
Host smart-042de68e-9605-4c32-af65-965ef8f4d53c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4268211358 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.4268211358
Directory /workspace/41.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.3632172493
Short name T152
Test name
Test status
Simulation time 1391050000 ps
CPU time 3.41 seconds
Started Jul 19 04:32:19 PM PDT 24
Finished Jul 19 04:32:30 PM PDT 24
Peak memory 164900 kb
Host smart-8e623749-edc6-49ba-9bf5-10a47e20b12d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3632172493 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.3632172493
Directory /workspace/42.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1172899726
Short name T122
Test name
Test status
Simulation time 1491750000 ps
CPU time 2.93 seconds
Started Jul 19 04:32:26 PM PDT 24
Finished Jul 19 04:32:35 PM PDT 24
Peak memory 164928 kb
Host smart-3b5bf61f-f6d6-4cd3-95e3-e9e6ccbb4415
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1172899726 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.1172899726
Directory /workspace/43.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.2463689571
Short name T150
Test name
Test status
Simulation time 1379970000 ps
CPU time 3.21 seconds
Started Jul 19 04:32:30 PM PDT 24
Finished Jul 19 04:32:42 PM PDT 24
Peak memory 164876 kb
Host smart-60fe4d3c-df44-4255-8f72-2b1b1530b35c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2463689571 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.2463689571
Directory /workspace/44.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.1163041889
Short name T129
Test name
Test status
Simulation time 1308670000 ps
CPU time 3.25 seconds
Started Jul 19 04:32:38 PM PDT 24
Finished Jul 19 04:32:53 PM PDT 24
Peak memory 164844 kb
Host smart-381b32bf-dcae-4d86-94de-b2b12534cb1f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1163041889 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.1163041889
Directory /workspace/45.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.3364862399
Short name T113
Test name
Test status
Simulation time 1370430000 ps
CPU time 3.01 seconds
Started Jul 19 04:32:32 PM PDT 24
Finished Jul 19 04:32:46 PM PDT 24
Peak memory 164856 kb
Host smart-fa892707-2273-4483-a514-22e112009ba8
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3364862399 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.3364862399
Directory /workspace/46.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.3550239107
Short name T144
Test name
Test status
Simulation time 1474630000 ps
CPU time 4.77 seconds
Started Jul 19 04:32:18 PM PDT 24
Finished Jul 19 04:32:30 PM PDT 24
Peak memory 164804 kb
Host smart-8d63d790-165d-4f98-b532-3bcc2f71b37c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3550239107 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.3550239107
Directory /workspace/47.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.1053243948
Short name T158
Test name
Test status
Simulation time 1522090000 ps
CPU time 4.32 seconds
Started Jul 19 04:32:23 PM PDT 24
Finished Jul 19 04:32:36 PM PDT 24
Peak memory 164876 kb
Host smart-90c4b736-b8af-4173-b4d7-7c5abec7ecbd
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1053243948 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.1053243948
Directory /workspace/48.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.1063225872
Short name T118
Test name
Test status
Simulation time 1446030000 ps
CPU time 3.18 seconds
Started Jul 19 04:32:20 PM PDT 24
Finished Jul 19 04:32:32 PM PDT 24
Peak memory 164884 kb
Host smart-60a45523-71bd-4e8b-a6fd-4448dd96f711
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1063225872 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.1063225872
Directory /workspace/49.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.1502093144
Short name T116
Test name
Test status
Simulation time 1585030000 ps
CPU time 3.93 seconds
Started Jul 19 04:32:21 PM PDT 24
Finished Jul 19 04:32:34 PM PDT 24
Peak memory 164872 kb
Host smart-84c8de77-dd7c-4d82-9b7c-214c5b2f523a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1502093144 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.1502093144
Directory /workspace/5.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.2195579945
Short name T130
Test name
Test status
Simulation time 1494330000 ps
CPU time 3.41 seconds
Started Jul 19 04:32:22 PM PDT 24
Finished Jul 19 04:32:34 PM PDT 24
Peak memory 164876 kb
Host smart-eed6fd4f-3aeb-4142-b48b-740e09a33d21
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2195579945 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.2195579945
Directory /workspace/6.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.2634198739
Short name T160
Test name
Test status
Simulation time 1383430000 ps
CPU time 3.43 seconds
Started Jul 19 04:32:13 PM PDT 24
Finished Jul 19 04:32:21 PM PDT 24
Peak memory 164884 kb
Host smart-bc4968e0-fbce-4549-b17e-805e25511682
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2634198739 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.2634198739
Directory /workspace/7.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.2460852652
Short name T112
Test name
Test status
Simulation time 1462030000 ps
CPU time 3.48 seconds
Started Jul 19 04:32:07 PM PDT 24
Finished Jul 19 04:32:16 PM PDT 24
Peak memory 164876 kb
Host smart-915d094e-54aa-4778-afae-ceb6bf33b2d8
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2460852652 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.2460852652
Directory /workspace/8.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.955549681
Short name T117
Test name
Test status
Simulation time 1535210000 ps
CPU time 5.36 seconds
Started Jul 19 04:32:17 PM PDT 24
Finished Jul 19 04:32:30 PM PDT 24
Peak memory 165024 kb
Host smart-17ced39d-4b43-4cbb-aa46-63b2e5f401af
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=955549681 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.955549681
Directory /workspace/9.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.1449427621
Short name T62
Test name
Test status
Simulation time 1512610000 ps
CPU time 5.01 seconds
Started Jul 19 04:20:59 PM PDT 24
Finished Jul 19 04:21:10 PM PDT 24
Peak memory 164716 kb
Host smart-b44ab542-5699-412a-bc6f-437ed08fb455
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1449427621 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.1449427621
Directory /workspace/0.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.4035321234
Short name T63
Test name
Test status
Simulation time 1469950000 ps
CPU time 3.43 seconds
Started Jul 19 04:21:22 PM PDT 24
Finished Jul 19 04:21:31 PM PDT 24
Peak memory 164308 kb
Host smart-9318880e-75dc-446f-bc53-9fecb3f92052
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4035321234 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.4035321234
Directory /workspace/1.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.1216713839
Short name T61
Test name
Test status
Simulation time 1528190000 ps
CPU time 3.21 seconds
Started Jul 19 04:22:54 PM PDT 24
Finished Jul 19 04:23:03 PM PDT 24
Peak memory 164456 kb
Host smart-dd37f85a-66cf-4269-9342-c63884f0d938
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1216713839 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.1216713839
Directory /workspace/10.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.1689071202
Short name T36
Test name
Test status
Simulation time 1340170000 ps
CPU time 3.62 seconds
Started Jul 19 04:19:15 PM PDT 24
Finished Jul 19 04:19:24 PM PDT 24
Peak memory 164236 kb
Host smart-e9d50e40-0557-4d30-b2ed-e6c9d83d2abf
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1689071202 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.1689071202
Directory /workspace/11.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.917452999
Short name T54
Test name
Test status
Simulation time 1505990000 ps
CPU time 4.98 seconds
Started Jul 19 04:22:22 PM PDT 24
Finished Jul 19 04:22:35 PM PDT 24
Peak memory 164624 kb
Host smart-0ae51ae0-675b-4fd9-937c-28d8e097d08f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=917452999 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.917452999
Directory /workspace/12.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.2660756210
Short name T59
Test name
Test status
Simulation time 1255630000 ps
CPU time 4.22 seconds
Started Jul 19 04:22:53 PM PDT 24
Finished Jul 19 04:23:04 PM PDT 24
Peak memory 163132 kb
Host smart-a254dc53-eef5-41c7-8a85-1269a2d46935
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2660756210 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.2660756210
Directory /workspace/13.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.2132500149
Short name T31
Test name
Test status
Simulation time 1472450000 ps
CPU time 4.78 seconds
Started Jul 19 04:22:21 PM PDT 24
Finished Jul 19 04:22:34 PM PDT 24
Peak memory 164628 kb
Host smart-55f68879-5f54-4a8a-9c51-98470ae4d8a4
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2132500149 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.2132500149
Directory /workspace/14.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.2337502375
Short name T45
Test name
Test status
Simulation time 1365530000 ps
CPU time 4.39 seconds
Started Jul 19 04:22:53 PM PDT 24
Finished Jul 19 04:23:05 PM PDT 24
Peak memory 162868 kb
Host smart-8041971a-f804-4fd8-9576-718e6c78ea79
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2337502375 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.2337502375
Directory /workspace/15.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.494579346
Short name T65
Test name
Test status
Simulation time 1547570000 ps
CPU time 4.51 seconds
Started Jul 19 04:22:54 PM PDT 24
Finished Jul 19 04:23:06 PM PDT 24
Peak memory 164212 kb
Host smart-457dc4d9-c9bf-419d-8c6f-85910b4db655
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=494579346 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.494579346
Directory /workspace/16.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.3317754940
Short name T46
Test name
Test status
Simulation time 1607870000 ps
CPU time 3.93 seconds
Started Jul 19 04:22:56 PM PDT 24
Finished Jul 19 04:23:08 PM PDT 24
Peak memory 163516 kb
Host smart-11bb72c7-77ed-4b2c-8e45-8d973fc6cf7b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3317754940 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.3317754940
Directory /workspace/17.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.1998096387
Short name T2
Test name
Test status
Simulation time 1559790000 ps
CPU time 4.31 seconds
Started Jul 19 04:22:07 PM PDT 24
Finished Jul 19 04:22:18 PM PDT 24
Peak memory 164804 kb
Host smart-f8a10f4f-d2cf-4df9-abd1-22ad34a3ba81
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1998096387 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.1998096387
Directory /workspace/19.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.329916
Short name T55
Test name
Test status
Simulation time 1586010000 ps
CPU time 5.03 seconds
Started Jul 19 04:21:00 PM PDT 24
Finished Jul 19 04:21:11 PM PDT 24
Peak memory 164564 kb
Host smart-0186904a-c51f-40f4-85bf-36e70e44b37d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=329916 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.329916
Directory /workspace/2.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.1159762666
Short name T39
Test name
Test status
Simulation time 1507330000 ps
CPU time 5.14 seconds
Started Jul 19 04:21:35 PM PDT 24
Finished Jul 19 04:21:47 PM PDT 24
Peak memory 166596 kb
Host smart-d43299d9-3eea-40dd-a4c4-c4b984b228be
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1159762666 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.1159762666
Directory /workspace/20.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.3980812355
Short name T35
Test name
Test status
Simulation time 1508010000 ps
CPU time 3.66 seconds
Started Jul 19 04:19:15 PM PDT 24
Finished Jul 19 04:19:24 PM PDT 24
Peak memory 163548 kb
Host smart-aff67b47-cb59-45ca-9272-37e043fc9b20
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3980812355 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.3980812355
Directory /workspace/21.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.333093872
Short name T38
Test name
Test status
Simulation time 1318470000 ps
CPU time 4.12 seconds
Started Jul 19 04:22:20 PM PDT 24
Finished Jul 19 04:22:32 PM PDT 24
Peak memory 164624 kb
Host smart-a4bbe1e2-5784-4728-a597-f6408c98efc4
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=333093872 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.333093872
Directory /workspace/22.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.1269841809
Short name T67
Test name
Test status
Simulation time 1475850000 ps
CPU time 4.43 seconds
Started Jul 19 04:22:07 PM PDT 24
Finished Jul 19 04:22:19 PM PDT 24
Peak memory 161996 kb
Host smart-6f360938-f802-418c-b29e-6a7a271d674b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1269841809 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.1269841809
Directory /workspace/23.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.2333983698
Short name T11
Test name
Test status
Simulation time 1042630000 ps
CPU time 3.16 seconds
Started Jul 19 04:23:03 PM PDT 24
Finished Jul 19 04:23:15 PM PDT 24
Peak memory 164328 kb
Host smart-a8dfe738-0584-40c6-86ab-3e93c7b6b160
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2333983698 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.2333983698
Directory /workspace/24.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.294607274
Short name T9
Test name
Test status
Simulation time 1371170000 ps
CPU time 3.28 seconds
Started Jul 19 04:20:11 PM PDT 24
Finished Jul 19 04:20:19 PM PDT 24
Peak memory 164480 kb
Host smart-e6243d4e-8678-4e90-9a04-148b42739815
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=294607274 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.294607274
Directory /workspace/25.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.2273237458
Short name T68
Test name
Test status
Simulation time 1213350000 ps
CPU time 4.06 seconds
Started Jul 19 04:19:27 PM PDT 24
Finished Jul 19 04:19:37 PM PDT 24
Peak memory 166596 kb
Host smart-8b81c4d8-4619-4b15-b33e-b4b5857cc209
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2273237458 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.2273237458
Directory /workspace/26.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.1152680157
Short name T8
Test name
Test status
Simulation time 1510650000 ps
CPU time 4.02 seconds
Started Jul 19 04:19:19 PM PDT 24
Finished Jul 19 04:19:30 PM PDT 24
Peak memory 164340 kb
Host smart-cbea5f3f-8302-4f62-ac39-c107794f6afe
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1152680157 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.1152680157
Directory /workspace/27.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.2421473090
Short name T37
Test name
Test status
Simulation time 1411550000 ps
CPU time 4.6 seconds
Started Jul 19 04:20:03 PM PDT 24
Finished Jul 19 04:20:14 PM PDT 24
Peak memory 164472 kb
Host smart-555265af-429b-445c-be9f-a3d18d86baa5
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2421473090 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.2421473090
Directory /workspace/28.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.1920141648
Short name T57
Test name
Test status
Simulation time 1445670000 ps
CPU time 4.61 seconds
Started Jul 19 04:22:08 PM PDT 24
Finished Jul 19 04:22:19 PM PDT 24
Peak memory 164076 kb
Host smart-7e2fb981-45de-4157-b301-77a8d290d99f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1920141648 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.1920141648
Directory /workspace/29.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.3719484651
Short name T50
Test name
Test status
Simulation time 1486730000 ps
CPU time 4.57 seconds
Started Jul 19 04:23:08 PM PDT 24
Finished Jul 19 04:23:31 PM PDT 24
Peak memory 164532 kb
Host smart-60441c44-725e-49c1-82d7-ddb4edb120f1
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3719484651 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.3719484651
Directory /workspace/3.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.3118154745
Short name T34
Test name
Test status
Simulation time 1347830000 ps
CPU time 4.59 seconds
Started Jul 19 04:18:40 PM PDT 24
Finished Jul 19 04:18:51 PM PDT 24
Peak memory 164972 kb
Host smart-cfffc60a-e3c1-4f25-abe5-eb973066dba4
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3118154745 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.3118154745
Directory /workspace/30.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.1250009740
Short name T70
Test name
Test status
Simulation time 1451850000 ps
CPU time 4.46 seconds
Started Jul 19 04:22:53 PM PDT 24
Finished Jul 19 04:23:05 PM PDT 24
Peak memory 163952 kb
Host smart-6cefd6a0-c26c-4cae-9207-ebcb1399a024
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1250009740 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.1250009740
Directory /workspace/31.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.2542349597
Short name T13
Test name
Test status
Simulation time 1454950000 ps
CPU time 4.86 seconds
Started Jul 19 04:21:33 PM PDT 24
Finished Jul 19 04:21:44 PM PDT 24
Peak memory 166596 kb
Host smart-51667dd2-0ad9-462b-b8e7-b4a362e618bb
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2542349597 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.2542349597
Directory /workspace/32.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.3977262536
Short name T48
Test name
Test status
Simulation time 1605090000 ps
CPU time 5.64 seconds
Started Jul 19 04:17:34 PM PDT 24
Finished Jul 19 04:17:47 PM PDT 24
Peak memory 164972 kb
Host smart-7a791670-8ab8-4bab-b819-d01232b51c2a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3977262536 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.3977262536
Directory /workspace/33.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.854974320
Short name T1
Test name
Test status
Simulation time 1390530000 ps
CPU time 4.05 seconds
Started Jul 19 04:22:30 PM PDT 24
Finished Jul 19 04:22:39 PM PDT 24
Peak memory 164732 kb
Host smart-829d4fa4-11ee-46cf-81bf-7c5ccb32e0cd
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=854974320 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.854974320
Directory /workspace/34.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.2009527152
Short name T49
Test name
Test status
Simulation time 1448670000 ps
CPU time 4.49 seconds
Started Jul 19 04:22:53 PM PDT 24
Finished Jul 19 04:23:05 PM PDT 24
Peak memory 163040 kb
Host smart-be30bea8-04a4-4d4d-9595-08cf48743792
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2009527152 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.2009527152
Directory /workspace/35.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.2521955832
Short name T47
Test name
Test status
Simulation time 1464230000 ps
CPU time 5.12 seconds
Started Jul 19 04:18:38 PM PDT 24
Finished Jul 19 04:18:50 PM PDT 24
Peak memory 164996 kb
Host smart-629ebbc6-78ff-4ed2-8251-0e0ddee62484
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2521955832 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.2521955832
Directory /workspace/36.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.2227256578
Short name T12
Test name
Test status
Simulation time 1509710000 ps
CPU time 4.22 seconds
Started Jul 19 04:19:56 PM PDT 24
Finished Jul 19 04:20:06 PM PDT 24
Peak memory 164384 kb
Host smart-69a24fc8-9ef2-40a1-8280-f2d3d80f2995
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2227256578 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.2227256578
Directory /workspace/37.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.601218271
Short name T60
Test name
Test status
Simulation time 1383090000 ps
CPU time 4.21 seconds
Started Jul 19 04:22:07 PM PDT 24
Finished Jul 19 04:22:18 PM PDT 24
Peak memory 162200 kb
Host smart-3d1802cc-ed72-45ad-b841-df6f0f58ae94
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=601218271 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.601218271
Directory /workspace/38.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.1269999989
Short name T69
Test name
Test status
Simulation time 1294310000 ps
CPU time 3.87 seconds
Started Jul 19 04:19:19 PM PDT 24
Finished Jul 19 04:19:29 PM PDT 24
Peak memory 164196 kb
Host smart-721ac08b-1429-4f4e-b7af-e7fed3b91f11
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1269999989 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.1269999989
Directory /workspace/39.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.3088800814
Short name T43
Test name
Test status
Simulation time 1547710000 ps
CPU time 3.55 seconds
Started Jul 19 04:21:24 PM PDT 24
Finished Jul 19 04:21:34 PM PDT 24
Peak memory 163564 kb
Host smart-2cabba13-117b-4300-b97c-38edb253bd15
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3088800814 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.3088800814
Directory /workspace/4.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.3445255612
Short name T52
Test name
Test status
Simulation time 1381050000 ps
CPU time 4.04 seconds
Started Jul 19 04:19:18 PM PDT 24
Finished Jul 19 04:19:28 PM PDT 24
Peak memory 163336 kb
Host smart-47a8914c-e07f-43d9-862a-77d21749b3ee
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3445255612 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.3445255612
Directory /workspace/40.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.3367640089
Short name T64
Test name
Test status
Simulation time 1296490000 ps
CPU time 3.84 seconds
Started Jul 19 04:20:22 PM PDT 24
Finished Jul 19 04:20:31 PM PDT 24
Peak memory 166596 kb
Host smart-05613a06-763f-481c-879e-3dbf5f6d5584
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3367640089 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.3367640089
Directory /workspace/41.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.2719096225
Short name T53
Test name
Test status
Simulation time 1483630000 ps
CPU time 4.84 seconds
Started Jul 19 04:22:53 PM PDT 24
Finished Jul 19 04:23:06 PM PDT 24
Peak memory 162312 kb
Host smart-da98096c-7a77-437d-821f-521b783381e5
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2719096225 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.2719096225
Directory /workspace/42.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.935240654
Short name T32
Test name
Test status
Simulation time 1518170000 ps
CPU time 4.29 seconds
Started Jul 19 04:19:56 PM PDT 24
Finished Jul 19 04:20:06 PM PDT 24
Peak memory 164408 kb
Host smart-57c11daf-dbf7-4eaf-be79-48051a2587d3
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=935240654 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.935240654
Directory /workspace/43.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.2532260166
Short name T33
Test name
Test status
Simulation time 1549630000 ps
CPU time 3.42 seconds
Started Jul 19 04:22:44 PM PDT 24
Finished Jul 19 04:22:53 PM PDT 24
Peak memory 164196 kb
Host smart-5654e47f-9266-4337-9324-c43b37b9599c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2532260166 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.2532260166
Directory /workspace/44.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.1862016722
Short name T7
Test name
Test status
Simulation time 1383070000 ps
CPU time 4.17 seconds
Started Jul 19 04:19:56 PM PDT 24
Finished Jul 19 04:20:05 PM PDT 24
Peak memory 164380 kb
Host smart-25cf05ad-3da7-4335-9e61-979d0c5e3400
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1862016722 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.1862016722
Directory /workspace/45.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.3699438132
Short name T42
Test name
Test status
Simulation time 1544950000 ps
CPU time 4.86 seconds
Started Jul 19 04:20:22 PM PDT 24
Finished Jul 19 04:20:33 PM PDT 24
Peak memory 166596 kb
Host smart-94504cfd-6084-42a2-8e0b-bd3ee990ea34
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3699438132 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.3699438132
Directory /workspace/46.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.2719375895
Short name T58
Test name
Test status
Simulation time 1267530000 ps
CPU time 3.97 seconds
Started Jul 19 04:20:27 PM PDT 24
Finished Jul 19 04:20:36 PM PDT 24
Peak memory 164752 kb
Host smart-5bfd3f10-c921-4784-a90e-a5b39aed15fa
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2719375895 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.2719375895
Directory /workspace/47.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.3105099577
Short name T10
Test name
Test status
Simulation time 1424350000 ps
CPU time 4.34 seconds
Started Jul 19 04:22:07 PM PDT 24
Finished Jul 19 04:22:18 PM PDT 24
Peak memory 162184 kb
Host smart-633c06ff-51c8-4754-b2f2-a9e5e165d22c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3105099577 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.3105099577
Directory /workspace/48.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.1085034868
Short name T56
Test name
Test status
Simulation time 1151650000 ps
CPU time 3.56 seconds
Started Jul 19 04:19:18 PM PDT 24
Finished Jul 19 04:19:27 PM PDT 24
Peak memory 163996 kb
Host smart-12e597c0-e5c2-426c-886f-8010c4e0e0db
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1085034868 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.1085034868
Directory /workspace/49.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.2771026451
Short name T44
Test name
Test status
Simulation time 1332350000 ps
CPU time 4.13 seconds
Started Jul 19 04:23:08 PM PDT 24
Finished Jul 19 04:23:30 PM PDT 24
Peak memory 164532 kb
Host smart-89ed383a-e17f-4f6d-b925-821331f8d75d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2771026451 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.2771026451
Directory /workspace/5.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.3470176929
Short name T40
Test name
Test status
Simulation time 1549570000 ps
CPU time 4.71 seconds
Started Jul 19 04:23:08 PM PDT 24
Finished Jul 19 04:23:31 PM PDT 24
Peak memory 164504 kb
Host smart-08767d68-97d6-41be-9643-bbfce2cddbf1
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3470176929 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.3470176929
Directory /workspace/6.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.1796888981
Short name T51
Test name
Test status
Simulation time 1469550000 ps
CPU time 4.45 seconds
Started Jul 19 04:22:55 PM PDT 24
Finished Jul 19 04:23:07 PM PDT 24
Peak memory 164040 kb
Host smart-32f2c283-e4f1-4068-8903-0cfd197bf183
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1796888981 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.1796888981
Directory /workspace/7.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.495291498
Short name T66
Test name
Test status
Simulation time 1554110000 ps
CPU time 4.53 seconds
Started Jul 19 04:22:55 PM PDT 24
Finished Jul 19 04:23:07 PM PDT 24
Peak memory 163984 kb
Host smart-04215e50-c600-4270-a626-35e0d2b8c417
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=495291498 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.495291498
Directory /workspace/8.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.439365556
Short name T41
Test name
Test status
Simulation time 1536290000 ps
CPU time 3.13 seconds
Started Jul 19 04:22:53 PM PDT 24
Finished Jul 19 04:23:02 PM PDT 24
Peak memory 163780 kb
Host smart-c281649e-552d-443a-89dc-eb8400ff7f5a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=439365556 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.439365556
Directory /workspace/9.prim_lfsr_gal_smoke/latest
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