Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.31 100.00 96.55 100.00 100.00 95.00


Total tests in report: 200
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
87.31 87.31 100.00 100.00 96.55 96.55 100.00 100.00 100.00 100.00 40.00 40.00 /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.2938329105
96.81 9.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 87.50 47.50 /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2355019256
98.31 1.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 95.00 7.50 /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.440171166

Tests that do not contribute to grading

Name
/workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.4056777266
/workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.1915575416
/workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.3228756620
/workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.3693799262
/workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.2324444864
/workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.1273299906
/workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.447985461
/workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.2805586115
/workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.2474761527
/workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.1847066486
/workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.1810944380
/workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.3785325054
/workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.2375920886
/workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.2831989441
/workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.3152949225
/workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.2759475502
/workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.2036085171
/workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.99883206
/workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.2823610284
/workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.1878875008
/workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.1539677108
/workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.3546414745
/workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.939451071
/workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.1377424307
/workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.2574021461
/workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.672743478
/workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.1135947229
/workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.4018162906
/workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.1021827610
/workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.1382536911
/workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.485482311
/workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.335952774
/workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.1127054652
/workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.1933955768
/workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.1981040584
/workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.2820814662
/workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.3771870578
/workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.1537487312
/workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.3874028878
/workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.4023674314
/workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.2654699290
/workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.4166707461
/workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.14525659
/workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.1424770749
/workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.1472585591
/workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.28574280
/workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.2111808062
/workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1238181174
/workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.1295152366
/workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.2980119152
/workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.3692314817
/workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.3261533952
/workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.1777994880
/workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.3620787990
/workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.1692420225
/workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.4145153416
/workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.3300695862
/workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.3212449564
/workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.290000959
/workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.2501786606
/workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.489743898
/workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.3282108511
/workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3273022622
/workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.996108628
/workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.491170656
/workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.1263034628
/workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.1924288520
/workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.881758060
/workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.3367773337
/workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.2978817094
/workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.996001149
/workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.1872886046
/workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.2582727314
/workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.1276406216
/workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.3496173423
/workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.3347200122
/workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.301244542
/workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.1823448992
/workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.761477146
/workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.4278241451
/workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3335780087
/workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.2177980433
/workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.4094009841
/workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.2296239961
/workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.226930895
/workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.1739447019
/workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.2908249279
/workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.3130339611
/workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.2653607154
/workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.810175130
/workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.1308125733
/workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.2655892914
/workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.4025225748
/workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.292651449
/workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.1173796076
/workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.556669663
/workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.2008402771
/workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.1731113028
/workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.589392131
/workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.3781773506
/workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.1764037985
/workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.1566641814
/workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.3580527330
/workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.729069785
/workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.263071482
/workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.617550338
/workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.1849168989
/workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.1969596370
/workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.2229537865
/workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.249772079
/workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.754555946
/workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.3178341286
/workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.1218682070
/workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.3876971198
/workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.3751371982
/workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.3365679591
/workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.4126234938
/workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.1687971085
/workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.406735013
/workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.1692776004
/workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.935822382
/workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.864256810
/workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.36905768
/workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.871426582
/workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.2774641587
/workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.35780950
/workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.3429887452
/workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.2058597692
/workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.2119087239
/workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.4209889355
/workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.3857807982
/workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.1942989707
/workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3335155732
/workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.1071285294
/workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.3161321845
/workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.3723895005
/workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.3227125427
/workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.2365526417
/workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.3980760425
/workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.156133252
/workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.842730683
/workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.2062550372
/workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.3295527859
/workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.3792272928
/workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.2051880762
/workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.1028926980
/workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1222159492
/workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2033231498
/workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.1146298271
/workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.3769067441
/workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.574244975
/workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.2908265861
/workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.741572234
/workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.368752433
/workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.388108286
/workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.4270213884
/workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.3839700836
/workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.965045966
/workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.457759626
/workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.3408147021
/workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.4176052416
/workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.1073113042
/workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.3017146098
/workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.2434835036
/workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.827508303
/workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.1263912106
/workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.3328422908
/workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.2802727031
/workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.2310746610
/workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.1155137895
/workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.488670356
/workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.318419134
/workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.1248266855
/workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.1413211986
/workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.1138947861
/workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.3942155719
/workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.3365233832
/workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.3474272006
/workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.3635457037
/workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.4277934321
/workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.2412894227
/workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.735362944
/workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.2783052829
/workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.375575749
/workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.3190085174
/workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.3604779457
/workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.3386613428
/workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.3496578507
/workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.2723501448
/workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.3633008633
/workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.2067322164
/workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.2517084475
/workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.2767920758
/workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.1941841558
/workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.3028508166
/workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.3328837047
/workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.3046433661



Total test records in report: 200
tests.html | tests1.html | tests2.html | tests3.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.1138947861 Jul 21 05:01:50 PM PDT 24 Jul 21 05:01:59 PM PDT 24 1499510000 ps
T2 /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.3474272006 Jul 21 05:01:49 PM PDT 24 Jul 21 05:01:59 PM PDT 24 1605230000 ps
T3 /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.3496578507 Jul 21 05:01:55 PM PDT 24 Jul 21 05:02:07 PM PDT 24 1406770000 ps
T7 /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.1155137895 Jul 21 05:01:49 PM PDT 24 Jul 21 05:02:00 PM PDT 24 1432270000 ps
T8 /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.318419134 Jul 21 05:01:48 PM PDT 24 Jul 21 05:01:59 PM PDT 24 1451090000 ps
T9 /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.3328422908 Jul 21 05:01:43 PM PDT 24 Jul 21 05:01:51 PM PDT 24 1435490000 ps
T10 /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.1413211986 Jul 21 05:01:49 PM PDT 24 Jul 21 05:02:00 PM PDT 24 1452650000 ps
T11 /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.2938329105 Jul 21 05:01:44 PM PDT 24 Jul 21 05:01:54 PM PDT 24 1466330000 ps
T12 /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.2434835036 Jul 21 05:01:42 PM PDT 24 Jul 21 05:01:56 PM PDT 24 1611190000 ps
T13 /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.3604779457 Jul 21 05:01:59 PM PDT 24 Jul 21 05:02:08 PM PDT 24 1227850000 ps
T31 /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.3408147021 Jul 21 05:01:38 PM PDT 24 Jul 21 05:01:49 PM PDT 24 1490710000 ps
T32 /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.2908265861 Jul 21 05:01:37 PM PDT 24 Jul 21 05:01:49 PM PDT 24 1465690000 ps
T33 /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.2310746610 Jul 21 05:01:49 PM PDT 24 Jul 21 05:02:00 PM PDT 24 1413150000 ps
T34 /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.3386613428 Jul 21 05:01:55 PM PDT 24 Jul 21 05:02:06 PM PDT 24 1600730000 ps
T35 /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.3190085174 Jul 21 05:01:54 PM PDT 24 Jul 21 05:02:05 PM PDT 24 1511390000 ps
T36 /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.3635457037 Jul 21 05:01:49 PM PDT 24 Jul 21 05:02:01 PM PDT 24 1565770000 ps
T37 /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.4277934321 Jul 21 05:01:50 PM PDT 24 Jul 21 05:02:02 PM PDT 24 1418230000 ps
T38 /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.2412894227 Jul 21 05:01:53 PM PDT 24 Jul 21 05:02:00 PM PDT 24 1420730000 ps
T39 /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.735362944 Jul 21 05:01:37 PM PDT 24 Jul 21 05:01:45 PM PDT 24 1356370000 ps
T40 /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.1941841558 Jul 21 05:01:37 PM PDT 24 Jul 21 05:01:49 PM PDT 24 1565350000 ps
T41 /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.965045966 Jul 21 05:01:43 PM PDT 24 Jul 21 05:01:54 PM PDT 24 1551870000 ps
T42 /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.1073113042 Jul 21 05:01:42 PM PDT 24 Jul 21 05:01:54 PM PDT 24 1421710000 ps
T43 /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.3365233832 Jul 21 05:01:49 PM PDT 24 Jul 21 05:01:59 PM PDT 24 1474370000 ps
T44 /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.4270213884 Jul 21 05:01:41 PM PDT 24 Jul 21 05:01:49 PM PDT 24 1511350000 ps
T45 /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.3769067441 Jul 21 05:01:38 PM PDT 24 Jul 21 05:01:50 PM PDT 24 1475730000 ps
T46 /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.3028508166 Jul 21 05:01:37 PM PDT 24 Jul 21 05:01:46 PM PDT 24 1371990000 ps
T47 /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.3839700836 Jul 21 05:01:42 PM PDT 24 Jul 21 05:01:51 PM PDT 24 1514890000 ps
T48 /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.2723501448 Jul 21 05:01:56 PM PDT 24 Jul 21 05:02:10 PM PDT 24 1481510000 ps
T49 /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.1248266855 Jul 21 05:01:49 PM PDT 24 Jul 21 05:02:00 PM PDT 24 1328310000 ps
T50 /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.2067322164 Jul 21 05:01:56 PM PDT 24 Jul 21 05:02:07 PM PDT 24 1501430000 ps
T51 /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.375575749 Jul 21 05:01:55 PM PDT 24 Jul 21 05:02:08 PM PDT 24 1478090000 ps
T52 /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.1263912106 Jul 21 05:01:42 PM PDT 24 Jul 21 05:01:55 PM PDT 24 1520710000 ps
T53 /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.3017146098 Jul 21 05:01:43 PM PDT 24 Jul 21 05:01:55 PM PDT 24 1494290000 ps
T54 /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.2517084475 Jul 21 05:01:54 PM PDT 24 Jul 21 05:02:04 PM PDT 24 1433970000 ps
T55 /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.2767920758 Jul 21 05:01:39 PM PDT 24 Jul 21 05:01:50 PM PDT 24 1256990000 ps
T56 /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.2802727031 Jul 21 05:01:49 PM PDT 24 Jul 21 05:02:02 PM PDT 24 1576330000 ps
T57 /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.368752433 Jul 21 05:01:41 PM PDT 24 Jul 21 05:01:49 PM PDT 24 1290930000 ps
T58 /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.3328837047 Jul 21 05:01:37 PM PDT 24 Jul 21 05:01:50 PM PDT 24 1444310000 ps
T59 /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.457759626 Jul 21 05:01:42 PM PDT 24 Jul 21 05:01:55 PM PDT 24 1421490000 ps
T60 /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.4176052416 Jul 21 05:01:44 PM PDT 24 Jul 21 05:01:53 PM PDT 24 1244510000 ps
T61 /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.388108286 Jul 21 05:01:42 PM PDT 24 Jul 21 05:01:50 PM PDT 24 1545490000 ps
T62 /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.1146298271 Jul 21 05:01:29 PM PDT 24 Jul 21 05:01:36 PM PDT 24 1333990000 ps
T63 /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.574244975 Jul 21 05:01:39 PM PDT 24 Jul 21 05:01:52 PM PDT 24 1525290000 ps
T64 /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.741572234 Jul 21 05:01:38 PM PDT 24 Jul 21 05:01:53 PM PDT 24 1563910000 ps
T65 /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.3942155719 Jul 21 05:01:50 PM PDT 24 Jul 21 05:01:57 PM PDT 24 1383530000 ps
T66 /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.3633008633 Jul 21 05:01:56 PM PDT 24 Jul 21 05:02:07 PM PDT 24 1458190000 ps
T67 /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.827508303 Jul 21 05:01:42 PM PDT 24 Jul 21 05:01:54 PM PDT 24 1430110000 ps
T68 /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.2783052829 Jul 21 05:01:55 PM PDT 24 Jul 21 05:02:08 PM PDT 24 1456370000 ps
T69 /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.3046433661 Jul 21 05:01:39 PM PDT 24 Jul 21 05:01:49 PM PDT 24 1524210000 ps
T70 /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.488670356 Jul 21 05:01:38 PM PDT 24 Jul 21 05:01:49 PM PDT 24 1459430000 ps
T4 /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.14525659 Jul 21 04:22:40 PM PDT 24 Jul 21 04:52:49 PM PDT 24 337068030000 ps
T5 /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2355019256 Jul 21 04:22:13 PM PDT 24 Jul 21 04:52:59 PM PDT 24 336316550000 ps
T6 /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.2823610284 Jul 21 04:23:04 PM PDT 24 Jul 21 05:03:08 PM PDT 24 336942710000 ps
T14 /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.99883206 Jul 21 04:23:17 PM PDT 24 Jul 21 04:52:26 PM PDT 24 336526290000 ps
T15 /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.4166707461 Jul 21 04:22:52 PM PDT 24 Jul 21 04:52:23 PM PDT 24 336636010000 ps
T16 /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.2036085171 Jul 21 04:23:31 PM PDT 24 Jul 21 04:46:39 PM PDT 24 336911830000 ps
T17 /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.1878875008 Jul 21 04:23:32 PM PDT 24 Jul 21 04:55:19 PM PDT 24 336920250000 ps
T18 /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.1295152366 Jul 21 04:18:54 PM PDT 24 Jul 21 04:57:24 PM PDT 24 336476690000 ps
T19 /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.2375920886 Jul 21 04:20:02 PM PDT 24 Jul 21 04:50:00 PM PDT 24 336851750000 ps
T20 /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.2820814662 Jul 21 04:22:40 PM PDT 24 Jul 21 04:53:01 PM PDT 24 336741110000 ps
T71 /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.1537487312 Jul 21 04:20:57 PM PDT 24 Jul 21 04:53:33 PM PDT 24 336394790000 ps
T72 /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.1847066486 Jul 21 04:23:11 PM PDT 24 Jul 21 04:52:41 PM PDT 24 336766010000 ps
T73 /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.4018162906 Jul 21 04:23:07 PM PDT 24 Jul 21 04:52:06 PM PDT 24 336800930000 ps
T74 /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.2474761527 Jul 21 04:23:40 PM PDT 24 Jul 21 04:55:28 PM PDT 24 336984850000 ps
T75 /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.1539677108 Jul 21 04:23:04 PM PDT 24 Jul 21 05:01:33 PM PDT 24 336893550000 ps
T76 /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.485482311 Jul 21 04:23:28 PM PDT 24 Jul 21 04:55:00 PM PDT 24 337106070000 ps
T77 /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.1127054652 Jul 21 04:22:42 PM PDT 24 Jul 21 04:52:21 PM PDT 24 336661310000 ps
T78 /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.3546414745 Jul 21 04:22:57 PM PDT 24 Jul 21 04:48:41 PM PDT 24 336947410000 ps
T79 /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.3228756620 Jul 21 04:23:00 PM PDT 24 Jul 21 04:52:22 PM PDT 24 336894670000 ps
T80 /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.2111808062 Jul 21 04:23:11 PM PDT 24 Jul 21 04:53:25 PM PDT 24 337043730000 ps
T81 /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.28574280 Jul 21 04:23:03 PM PDT 24 Jul 21 04:53:18 PM PDT 24 337041710000 ps
T82 /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.2831989441 Jul 21 04:20:11 PM PDT 24 Jul 21 04:55:32 PM PDT 24 337151990000 ps
T83 /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.3771870578 Jul 21 04:20:28 PM PDT 24 Jul 21 04:55:08 PM PDT 24 336524970000 ps
T84 /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.1810944380 Jul 21 04:23:03 PM PDT 24 Jul 21 04:53:00 PM PDT 24 336422010000 ps
T85 /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.1981040584 Jul 21 04:22:41 PM PDT 24 Jul 21 04:52:31 PM PDT 24 336545330000 ps
T86 /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.1915575416 Jul 21 04:23:07 PM PDT 24 Jul 21 04:49:19 PM PDT 24 336661530000 ps
T87 /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.3152949225 Jul 21 04:23:03 PM PDT 24 Jul 21 04:53:06 PM PDT 24 336675310000 ps
T88 /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.1273299906 Jul 21 04:22:45 PM PDT 24 Jul 21 04:59:14 PM PDT 24 337077110000 ps
T89 /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.1021827610 Jul 21 04:20:45 PM PDT 24 Jul 21 04:52:05 PM PDT 24 336528050000 ps
T90 /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.1377424307 Jul 21 04:24:00 PM PDT 24 Jul 21 04:53:01 PM PDT 24 336878870000 ps
T91 /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.2759475502 Jul 21 04:23:16 PM PDT 24 Jul 21 05:04:01 PM PDT 24 336649590000 ps
T92 /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.447985461 Jul 21 04:19:56 PM PDT 24 Jul 21 04:55:22 PM PDT 24 336801990000 ps
T93 /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.4023674314 Jul 21 04:22:54 PM PDT 24 Jul 21 04:53:57 PM PDT 24 336720110000 ps
T94 /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.1382536911 Jul 21 04:23:21 PM PDT 24 Jul 21 04:52:31 PM PDT 24 336599410000 ps
T95 /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.1933955768 Jul 21 04:19:56 PM PDT 24 Jul 21 04:47:03 PM PDT 24 336322110000 ps
T96 /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.3693799262 Jul 21 04:23:40 PM PDT 24 Jul 21 04:55:20 PM PDT 24 336895390000 ps
T97 /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.2805586115 Jul 21 04:19:57 PM PDT 24 Jul 21 04:59:56 PM PDT 24 336701830000 ps
T98 /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.335952774 Jul 21 04:21:18 PM PDT 24 Jul 21 04:51:54 PM PDT 24 336479070000 ps
T99 /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.672743478 Jul 21 04:23:58 PM PDT 24 Jul 21 04:52:47 PM PDT 24 336798090000 ps
T100 /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.1424770749 Jul 21 04:19:55 PM PDT 24 Jul 21 04:55:17 PM PDT 24 336296750000 ps
T101 /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1238181174 Jul 21 04:23:11 PM PDT 24 Jul 21 04:53:38 PM PDT 24 336495010000 ps
T102 /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.939451071 Jul 21 04:20:15 PM PDT 24 Jul 21 04:51:55 PM PDT 24 336520110000 ps
T103 /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.4056777266 Jul 21 04:22:53 PM PDT 24 Jul 21 04:49:10 PM PDT 24 336564250000 ps
T104 /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.3874028878 Jul 21 04:20:14 PM PDT 24 Jul 21 04:58:43 PM PDT 24 336728250000 ps
T105 /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.2654699290 Jul 21 04:23:06 PM PDT 24 Jul 21 04:54:26 PM PDT 24 336466590000 ps
T106 /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.2324444864 Jul 21 04:22:53 PM PDT 24 Jul 21 04:57:50 PM PDT 24 336326630000 ps
T107 /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.1472585591 Jul 21 04:22:45 PM PDT 24 Jul 21 04:51:11 PM PDT 24 336784710000 ps
T108 /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.1135947229 Jul 21 04:23:05 PM PDT 24 Jul 21 04:52:15 PM PDT 24 336312450000 ps
T109 /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.3785325054 Jul 21 04:22:52 PM PDT 24 Jul 21 04:52:44 PM PDT 24 336879210000 ps
T110 /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.2574021461 Jul 21 04:23:49 PM PDT 24 Jul 21 04:53:07 PM PDT 24 336542530000 ps
T111 /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.871426582 Jul 21 04:22:52 PM PDT 24 Jul 21 04:23:02 PM PDT 24 1492430000 ps
T112 /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.3178341286 Jul 21 04:19:39 PM PDT 24 Jul 21 04:19:48 PM PDT 24 1545510000 ps
T113 /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.842730683 Jul 21 04:18:55 PM PDT 24 Jul 21 04:19:04 PM PDT 24 1436890000 ps
T114 /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.3295527859 Jul 21 04:22:52 PM PDT 24 Jul 21 04:23:02 PM PDT 24 1479150000 ps
T115 /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.589392131 Jul 21 04:19:54 PM PDT 24 Jul 21 04:20:04 PM PDT 24 1407490000 ps
T116 /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.3365679591 Jul 21 04:18:55 PM PDT 24 Jul 21 04:19:02 PM PDT 24 1090770000 ps
T117 /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.4126234938 Jul 21 04:23:11 PM PDT 24 Jul 21 04:23:21 PM PDT 24 1506570000 ps
T118 /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.864256810 Jul 21 04:22:53 PM PDT 24 Jul 21 04:23:01 PM PDT 24 1060970000 ps
T119 /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.1764037985 Jul 21 04:19:33 PM PDT 24 Jul 21 04:19:45 PM PDT 24 1467170000 ps
T120 /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.3161321845 Jul 21 04:20:24 PM PDT 24 Jul 21 04:20:34 PM PDT 24 1550830000 ps
T121 /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.36905768 Jul 21 04:22:43 PM PDT 24 Jul 21 04:22:50 PM PDT 24 1525910000 ps
T122 /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.263071482 Jul 21 04:18:58 PM PDT 24 Jul 21 04:19:05 PM PDT 24 1072790000 ps
T123 /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.1028926980 Jul 21 04:22:53 PM PDT 24 Jul 21 04:23:03 PM PDT 24 1326090000 ps
T124 /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.406735013 Jul 21 04:23:11 PM PDT 24 Jul 21 04:23:21 PM PDT 24 1475910000 ps
T125 /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.3580527330 Jul 21 04:20:58 PM PDT 24 Jul 21 04:21:08 PM PDT 24 1609350000 ps
T126 /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.3723895005 Jul 21 04:23:06 PM PDT 24 Jul 21 04:23:17 PM PDT 24 1484210000 ps
T127 /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.3227125427 Jul 21 04:22:40 PM PDT 24 Jul 21 04:22:48 PM PDT 24 1465410000 ps
T128 /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.3781773506 Jul 21 04:23:07 PM PDT 24 Jul 21 04:23:17 PM PDT 24 1537870000 ps
T129 /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.1071285294 Jul 21 04:20:24 PM PDT 24 Jul 21 04:20:37 PM PDT 24 1520290000 ps
T130 /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.754555946 Jul 21 04:23:07 PM PDT 24 Jul 21 04:23:14 PM PDT 24 994290000 ps
T131 /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.249772079 Jul 21 04:21:10 PM PDT 24 Jul 21 04:21:19 PM PDT 24 1412790000 ps
T132 /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.1849168989 Jul 21 04:23:11 PM PDT 24 Jul 21 04:23:19 PM PDT 24 1279710000 ps
T133 /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.2119087239 Jul 21 04:23:59 PM PDT 24 Jul 21 04:24:08 PM PDT 24 1384430000 ps
T134 /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.1942989707 Jul 21 04:22:41 PM PDT 24 Jul 21 04:22:50 PM PDT 24 1437610000 ps
T135 /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.3792272928 Jul 21 04:22:54 PM PDT 24 Jul 21 04:23:03 PM PDT 24 1427850000 ps
T136 /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.3751371982 Jul 21 04:21:52 PM PDT 24 Jul 21 04:22:02 PM PDT 24 1478790000 ps
T137 /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.1692776004 Jul 21 04:22:14 PM PDT 24 Jul 21 04:22:24 PM PDT 24 1536470000 ps
T138 /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.3429887452 Jul 21 04:23:28 PM PDT 24 Jul 21 04:23:39 PM PDT 24 1512730000 ps
T139 /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.729069785 Jul 21 04:22:46 PM PDT 24 Jul 21 04:22:56 PM PDT 24 1316450000 ps
T140 /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.35780950 Jul 21 04:22:52 PM PDT 24 Jul 21 04:23:01 PM PDT 24 1251950000 ps
T141 /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.3876971198 Jul 21 04:20:33 PM PDT 24 Jul 21 04:20:43 PM PDT 24 1518110000 ps
T142 /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.1566641814 Jul 21 04:23:02 PM PDT 24 Jul 21 04:23:12 PM PDT 24 1456630000 ps
T143 /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.3980760425 Jul 21 04:19:34 PM PDT 24 Jul 21 04:19:44 PM PDT 24 1543090000 ps
T144 /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.935822382 Jul 21 04:18:59 PM PDT 24 Jul 21 04:19:11 PM PDT 24 1543310000 ps
T145 /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.3857807982 Jul 21 04:23:06 PM PDT 24 Jul 21 04:23:15 PM PDT 24 1433610000 ps
T146 /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3335155732 Jul 21 04:19:14 PM PDT 24 Jul 21 04:19:24 PM PDT 24 1546570000 ps
T147 /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.156133252 Jul 21 04:22:52 PM PDT 24 Jul 21 04:23:04 PM PDT 24 1508250000 ps
T148 /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.1218682070 Jul 21 04:19:04 PM PDT 24 Jul 21 04:19:15 PM PDT 24 1376190000 ps
T149 /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.1969596370 Jul 21 04:18:54 PM PDT 24 Jul 21 04:19:03 PM PDT 24 1497430000 ps
T150 /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.2365526417 Jul 21 04:23:05 PM PDT 24 Jul 21 04:23:15 PM PDT 24 1314050000 ps
T151 /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.2058597692 Jul 21 04:23:40 PM PDT 24 Jul 21 04:23:50 PM PDT 24 1458290000 ps
T152 /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2033231498 Jul 21 04:22:46 PM PDT 24 Jul 21 04:22:54 PM PDT 24 1217130000 ps
T153 /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.2062550372 Jul 21 04:19:55 PM PDT 24 Jul 21 04:20:06 PM PDT 24 1462490000 ps
T154 /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1222159492 Jul 21 04:22:45 PM PDT 24 Jul 21 04:22:54 PM PDT 24 1386350000 ps
T155 /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.2051880762 Jul 21 04:22:53 PM PDT 24 Jul 21 04:23:03 PM PDT 24 1459770000 ps
T156 /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.617550338 Jul 21 04:19:56 PM PDT 24 Jul 21 04:20:07 PM PDT 24 1491870000 ps
T157 /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.2229537865 Jul 21 04:23:19 PM PDT 24 Jul 21 04:23:27 PM PDT 24 1262130000 ps
T158 /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.2774641587 Jul 21 04:20:25 PM PDT 24 Jul 21 04:20:33 PM PDT 24 1462350000 ps
T159 /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.1687971085 Jul 21 04:23:02 PM PDT 24 Jul 21 04:23:11 PM PDT 24 1483390000 ps
T160 /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.4209889355 Jul 21 04:23:06 PM PDT 24 Jul 21 04:23:14 PM PDT 24 1363210000 ps
T21 /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.996001149 Jul 21 04:18:55 PM PDT 24 Jul 21 04:44:35 PM PDT 24 336331970000 ps
T22 /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.1692420225 Jul 21 04:19:55 PM PDT 24 Jul 21 04:50:27 PM PDT 24 337107190000 ps
T23 /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.2177980433 Jul 21 04:20:21 PM PDT 24 Jul 21 04:54:10 PM PDT 24 336366150000 ps
T24 /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.3367773337 Jul 21 04:23:04 PM PDT 24 Jul 21 05:03:07 PM PDT 24 336675810000 ps
T25 /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.556669663 Jul 21 04:19:03 PM PDT 24 Jul 21 04:50:57 PM PDT 24 337114090000 ps
T26 /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.1173796076 Jul 21 04:22:45 PM PDT 24 Jul 21 04:51:31 PM PDT 24 336587750000 ps
T27 /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.292651449 Jul 21 04:22:41 PM PDT 24 Jul 21 04:51:24 PM PDT 24 336320670000 ps
T28 /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.440171166 Jul 21 04:20:58 PM PDT 24 Jul 21 04:58:45 PM PDT 24 336666470000 ps
T29 /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.3300695862 Jul 21 04:22:45 PM PDT 24 Jul 21 04:59:07 PM PDT 24 336506490000 ps
T30 /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.2653607154 Jul 21 04:23:51 PM PDT 24 Jul 21 04:50:32 PM PDT 24 336922650000 ps
T161 /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.1823448992 Jul 21 04:23:28 PM PDT 24 Jul 21 04:54:42 PM PDT 24 336536090000 ps
T162 /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.2908249279 Jul 21 04:23:49 PM PDT 24 Jul 21 04:51:26 PM PDT 24 336684570000 ps
T163 /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.1263034628 Jul 21 04:23:03 PM PDT 24 Jul 21 04:52:25 PM PDT 24 336793310000 ps
T164 /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.1777994880 Jul 21 04:22:45 PM PDT 24 Jul 21 04:57:56 PM PDT 24 336993590000 ps
T165 /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.2582727314 Jul 21 04:20:42 PM PDT 24 Jul 21 04:55:28 PM PDT 24 337029310000 ps
T166 /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.290000959 Jul 21 04:23:40 PM PDT 24 Jul 21 04:55:21 PM PDT 24 336869070000 ps
T167 /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.1308125733 Jul 21 04:23:50 PM PDT 24 Jul 21 04:54:26 PM PDT 24 336915270000 ps
T168 /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.491170656 Jul 21 04:18:59 PM PDT 24 Jul 21 04:52:36 PM PDT 24 336531930000 ps
T169 /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.3130339611 Jul 21 04:23:47 PM PDT 24 Jul 21 04:54:28 PM PDT 24 336574510000 ps
T170 /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.4025225748 Jul 21 04:23:46 PM PDT 24 Jul 21 04:50:29 PM PDT 24 336532370000 ps
T171 /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.4145153416 Jul 21 04:22:45 PM PDT 24 Jul 21 04:58:01 PM PDT 24 336925470000 ps
T172 /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.1872886046 Jul 21 04:20:15 PM PDT 24 Jul 21 04:52:29 PM PDT 24 336655090000 ps
T173 /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.2008402771 Jul 21 04:22:52 PM PDT 24 Jul 21 04:51:54 PM PDT 24 336975570000 ps
T174 /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.996108628 Jul 21 04:23:19 PM PDT 24 Jul 21 04:49:10 PM PDT 24 336330890000 ps
T175 /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.3692314817 Jul 21 04:22:46 PM PDT 24 Jul 21 04:49:18 PM PDT 24 337036970000 ps
T176 /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.3347200122 Jul 21 04:20:20 PM PDT 24 Jul 21 04:54:27 PM PDT 24 336521410000 ps
T177 /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.489743898 Jul 21 04:18:49 PM PDT 24 Jul 21 04:48:26 PM PDT 24 336701530000 ps
T178 /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.2655892914 Jul 21 04:24:00 PM PDT 24 Jul 21 04:55:21 PM PDT 24 337118750000 ps
T179 /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.2980119152 Jul 21 04:18:59 PM PDT 24 Jul 21 04:51:34 PM PDT 24 336667250000 ps
T180 /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.4094009841 Jul 21 04:22:41 PM PDT 24 Jul 21 04:50:01 PM PDT 24 336635030000 ps
T181 /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.3620787990 Jul 21 04:22:46 PM PDT 24 Jul 21 04:58:10 PM PDT 24 336900090000 ps
T182 /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.3496173423 Jul 21 04:23:11 PM PDT 24 Jul 21 04:50:58 PM PDT 24 336779190000 ps
T183 /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.881758060 Jul 21 04:23:16 PM PDT 24 Jul 21 05:04:07 PM PDT 24 336703530000 ps
T184 /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3273022622 Jul 21 04:20:19 PM PDT 24 Jul 21 04:51:42 PM PDT 24 336667770000 ps
T185 /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.2501786606 Jul 21 04:19:17 PM PDT 24 Jul 21 04:58:39 PM PDT 24 336663870000 ps
T186 /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.810175130 Jul 21 04:24:01 PM PDT 24 Jul 21 04:55:20 PM PDT 24 336964690000 ps
T187 /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.761477146 Jul 21 04:23:04 PM PDT 24 Jul 21 04:53:21 PM PDT 24 336424070000 ps
T188 /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.1924288520 Jul 21 04:19:48 PM PDT 24 Jul 21 04:48:49 PM PDT 24 336602410000 ps
T189 /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.3282108511 Jul 21 04:20:28 PM PDT 24 Jul 21 04:55:07 PM PDT 24 336478450000 ps
T190 /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.1731113028 Jul 21 04:21:30 PM PDT 24 Jul 21 04:51:16 PM PDT 24 337032530000 ps
T191 /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.2296239961 Jul 21 04:23:14 PM PDT 24 Jul 21 04:51:32 PM PDT 24 336976710000 ps
T192 /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3335780087 Jul 21 04:24:02 PM PDT 24 Jul 21 04:54:05 PM PDT 24 336966510000 ps
T193 /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.301244542 Jul 21 04:23:11 PM PDT 24 Jul 21 04:50:39 PM PDT 24 337061130000 ps
T194 /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.2978817094 Jul 21 04:19:51 PM PDT 24 Jul 21 04:49:16 PM PDT 24 336488710000 ps
T195 /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.1276406216 Jul 21 04:24:01 PM PDT 24 Jul 21 04:52:37 PM PDT 24 336469410000 ps
T196 /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.4278241451 Jul 21 04:23:49 PM PDT 24 Jul 21 04:52:31 PM PDT 24 336634730000 ps
T197 /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.226930895 Jul 21 04:22:54 PM PDT 24 Jul 21 04:54:14 PM PDT 24 337130670000 ps
T198 /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.3261533952 Jul 21 04:23:24 PM PDT 24 Jul 21 04:52:40 PM PDT 24 336394470000 ps
T199 /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.1739447019 Jul 21 04:18:55 PM PDT 24 Jul 21 04:50:51 PM PDT 24 336798070000 ps
T200 /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.3212449564 Jul 21 04:22:45 PM PDT 24 Jul 21 04:56:32 PM PDT 24 336643390000 ps

Test location /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.2938329105
Short name T11
Test name
Test status
Simulation time 1466330000 ps
CPU time 4.25 seconds
Started Jul 21 05:01:44 PM PDT 24
Finished Jul 21 05:01:54 PM PDT 24
Peak memory 164852 kb
Host smart-c6f0649a-d4af-4ee6-ae94-bb083e63533c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2938329105 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.2938329105
Directory /workspace/19.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2355019256
Short name T5
Test name
Test status
Simulation time 336316550000 ps
CPU time 746.06 seconds
Started Jul 21 04:22:13 PM PDT 24
Finished Jul 21 04:52:59 PM PDT 24
Peak memory 160744 kb
Host smart-80bad4e8-747e-4331-821c-5a1398ea26a4
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2355019256 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.2355019256
Directory /workspace/19.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.440171166
Short name T28
Test name
Test status
Simulation time 336666470000 ps
CPU time 902.53 seconds
Started Jul 21 04:20:58 PM PDT 24
Finished Jul 21 04:58:45 PM PDT 24
Peak memory 160704 kb
Host smart-0268af76-0b6e-42cb-8b08-ccf46f071a93
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=440171166 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.440171166
Directory /workspace/0.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.4056777266
Short name T103
Test name
Test status
Simulation time 336564250000 ps
CPU time 640.78 seconds
Started Jul 21 04:22:53 PM PDT 24
Finished Jul 21 04:49:10 PM PDT 24
Peak memory 159568 kb
Host smart-c96aad10-b4d7-4398-8051-42570b58a31e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4056777266 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.4056777266
Directory /workspace/0.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.1915575416
Short name T86
Test name
Test status
Simulation time 336661530000 ps
CPU time 636.22 seconds
Started Jul 21 04:23:07 PM PDT 24
Finished Jul 21 04:49:19 PM PDT 24
Peak memory 160568 kb
Host smart-c00db863-6a21-4843-a373-386655acc32b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1915575416 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.1915575416
Directory /workspace/1.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.3228756620
Short name T79
Test name
Test status
Simulation time 336894670000 ps
CPU time 714.43 seconds
Started Jul 21 04:23:00 PM PDT 24
Finished Jul 21 04:52:22 PM PDT 24
Peak memory 160416 kb
Host smart-f95516bf-9e51-4785-99b8-a2c24237a398
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3228756620 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.3228756620
Directory /workspace/10.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.3693799262
Short name T96
Test name
Test status
Simulation time 336895390000 ps
CPU time 772.34 seconds
Started Jul 21 04:23:40 PM PDT 24
Finished Jul 21 04:55:20 PM PDT 24
Peak memory 160448 kb
Host smart-c78f4057-fa9c-4df1-9fd9-b9eaa4f345c8
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3693799262 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.3693799262
Directory /workspace/11.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.2324444864
Short name T106
Test name
Test status
Simulation time 336326630000 ps
CPU time 846.47 seconds
Started Jul 21 04:22:53 PM PDT 24
Finished Jul 21 04:57:50 PM PDT 24
Peak memory 160424 kb
Host smart-e6862c07-fcfd-43f7-a7f2-5b0ff255a6c9
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2324444864 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.2324444864
Directory /workspace/12.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.1273299906
Short name T88
Test name
Test status
Simulation time 337077110000 ps
CPU time 899.24 seconds
Started Jul 21 04:22:45 PM PDT 24
Finished Jul 21 04:59:14 PM PDT 24
Peak memory 157928 kb
Host smart-494b956d-93f4-40ab-a858-5fff836c253d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1273299906 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.1273299906
Directory /workspace/13.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.447985461
Short name T92
Test name
Test status
Simulation time 336801990000 ps
CPU time 860.84 seconds
Started Jul 21 04:19:56 PM PDT 24
Finished Jul 21 04:55:22 PM PDT 24
Peak memory 160868 kb
Host smart-6f4c5673-336b-4fb0-886a-6ee4511ee414
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=447985461 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.447985461
Directory /workspace/14.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.2805586115
Short name T97
Test name
Test status
Simulation time 336701830000 ps
CPU time 972.88 seconds
Started Jul 21 04:19:57 PM PDT 24
Finished Jul 21 04:59:56 PM PDT 24
Peak memory 160700 kb
Host smart-df1d87c2-c8c0-4cae-b55f-67ae757b7ea2
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2805586115 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.2805586115
Directory /workspace/15.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.2474761527
Short name T74
Test name
Test status
Simulation time 336984850000 ps
CPU time 771.75 seconds
Started Jul 21 04:23:40 PM PDT 24
Finished Jul 21 04:55:28 PM PDT 24
Peak memory 160448 kb
Host smart-35700892-b6c2-466d-b85d-8bafcc065b25
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2474761527 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.2474761527
Directory /workspace/16.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.1847066486
Short name T72
Test name
Test status
Simulation time 336766010000 ps
CPU time 716.73 seconds
Started Jul 21 04:23:11 PM PDT 24
Finished Jul 21 04:52:41 PM PDT 24
Peak memory 160464 kb
Host smart-3fba26df-df38-40d8-9e84-0a8a45f3fe4e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1847066486 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.1847066486
Directory /workspace/17.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.1810944380
Short name T84
Test name
Test status
Simulation time 336422010000 ps
CPU time 733.84 seconds
Started Jul 21 04:23:03 PM PDT 24
Finished Jul 21 04:53:00 PM PDT 24
Peak memory 160344 kb
Host smart-bff3cccf-6003-446b-bb67-b7140dfe5454
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1810944380 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.1810944380
Directory /workspace/18.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.3785325054
Short name T109
Test name
Test status
Simulation time 336879210000 ps
CPU time 727.13 seconds
Started Jul 21 04:22:52 PM PDT 24
Finished Jul 21 04:52:44 PM PDT 24
Peak memory 160432 kb
Host smart-5c029879-dfb5-433e-84b1-eb5f5c116528
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3785325054 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.3785325054
Directory /workspace/2.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.2375920886
Short name T19
Test name
Test status
Simulation time 336851750000 ps
CPU time 731.79 seconds
Started Jul 21 04:20:02 PM PDT 24
Finished Jul 21 04:50:00 PM PDT 24
Peak memory 160776 kb
Host smart-7eda013b-99fe-4365-8e6e-bbba63694145
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2375920886 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.2375920886
Directory /workspace/20.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.2831989441
Short name T82
Test name
Test status
Simulation time 337151990000 ps
CPU time 859.5 seconds
Started Jul 21 04:20:11 PM PDT 24
Finished Jul 21 04:55:32 PM PDT 24
Peak memory 160676 kb
Host smart-c6cc350b-a966-46c8-b9d3-7ee2b9a10bae
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2831989441 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.2831989441
Directory /workspace/21.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.3152949225
Short name T87
Test name
Test status
Simulation time 336675310000 ps
CPU time 733.29 seconds
Started Jul 21 04:23:03 PM PDT 24
Finished Jul 21 04:53:06 PM PDT 24
Peak memory 160344 kb
Host smart-0b8e1f3a-c1c0-41c4-bf49-98fb701155e7
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3152949225 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.3152949225
Directory /workspace/22.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.2759475502
Short name T91
Test name
Test status
Simulation time 336649590000 ps
CPU time 977.28 seconds
Started Jul 21 04:23:16 PM PDT 24
Finished Jul 21 05:04:01 PM PDT 24
Peak memory 160356 kb
Host smart-d3fe2ef3-0e8f-45d9-b629-b0f00630eff7
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2759475502 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.2759475502
Directory /workspace/23.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.2036085171
Short name T16
Test name
Test status
Simulation time 336911830000 ps
CPU time 550.11 seconds
Started Jul 21 04:23:31 PM PDT 24
Finished Jul 21 04:46:39 PM PDT 24
Peak memory 159276 kb
Host smart-b47e6b28-3b41-44da-94fe-e4a1c686b5f8
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2036085171 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.2036085171
Directory /workspace/24.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.99883206
Short name T14
Test name
Test status
Simulation time 336526290000 ps
CPU time 708.37 seconds
Started Jul 21 04:23:17 PM PDT 24
Finished Jul 21 04:52:26 PM PDT 24
Peak memory 159480 kb
Host smart-a0b19f65-06c1-46df-853d-c1f392716a8c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=99883206 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.99883206
Directory /workspace/25.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.2823610284
Short name T6
Test name
Test status
Simulation time 336942710000 ps
CPU time 952.13 seconds
Started Jul 21 04:23:04 PM PDT 24
Finished Jul 21 05:03:08 PM PDT 24
Peak memory 158704 kb
Host smart-b5399af5-c0e6-46cc-9efd-900d5cb23892
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2823610284 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.2823610284
Directory /workspace/26.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.1878875008
Short name T17
Test name
Test status
Simulation time 336920250000 ps
CPU time 777.71 seconds
Started Jul 21 04:23:32 PM PDT 24
Finished Jul 21 04:55:19 PM PDT 24
Peak memory 160436 kb
Host smart-2ff0ac1f-131b-419f-98db-e37dcd1aedf6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1878875008 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.1878875008
Directory /workspace/27.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.1539677108
Short name T75
Test name
Test status
Simulation time 336893550000 ps
CPU time 888.19 seconds
Started Jul 21 04:23:04 PM PDT 24
Finished Jul 21 05:01:33 PM PDT 24
Peak memory 160244 kb
Host smart-baf095ec-74e6-4288-a5a9-a41a96c5ad64
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1539677108 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.1539677108
Directory /workspace/28.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.3546414745
Short name T78
Test name
Test status
Simulation time 336947410000 ps
CPU time 624.28 seconds
Started Jul 21 04:22:57 PM PDT 24
Finished Jul 21 04:48:41 PM PDT 24
Peak memory 160620 kb
Host smart-fa2a0f9c-dd61-4f21-bcc4-6d0c42d8e73c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3546414745 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.3546414745
Directory /workspace/29.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.939451071
Short name T102
Test name
Test status
Simulation time 336520110000 ps
CPU time 767.09 seconds
Started Jul 21 04:20:15 PM PDT 24
Finished Jul 21 04:51:55 PM PDT 24
Peak memory 160616 kb
Host smart-f8d80271-ab4e-4386-a37d-a257435696ab
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=939451071 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.939451071
Directory /workspace/3.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.1377424307
Short name T90
Test name
Test status
Simulation time 336878870000 ps
CPU time 696.38 seconds
Started Jul 21 04:24:00 PM PDT 24
Finished Jul 21 04:53:01 PM PDT 24
Peak memory 160620 kb
Host smart-90072197-1800-4951-a9d3-16c9da929cf6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1377424307 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.1377424307
Directory /workspace/30.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.2574021461
Short name T110
Test name
Test status
Simulation time 336542530000 ps
CPU time 708.39 seconds
Started Jul 21 04:23:49 PM PDT 24
Finished Jul 21 04:53:07 PM PDT 24
Peak memory 159504 kb
Host smart-db6d21ad-3697-41f0-b4a5-99981efe0db7
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2574021461 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.2574021461
Directory /workspace/31.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.672743478
Short name T99
Test name
Test status
Simulation time 336798090000 ps
CPU time 689.52 seconds
Started Jul 21 04:23:58 PM PDT 24
Finished Jul 21 04:52:47 PM PDT 24
Peak memory 160224 kb
Host smart-e9c069d8-0f3c-4518-b225-5c5ccd77c6d3
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=672743478 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.672743478
Directory /workspace/32.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.1135947229
Short name T108
Test name
Test status
Simulation time 336312450000 ps
CPU time 709.55 seconds
Started Jul 21 04:23:05 PM PDT 24
Finished Jul 21 04:52:15 PM PDT 24
Peak memory 160464 kb
Host smart-64a12b36-eb5d-4327-a938-8677d19017a4
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1135947229 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.1135947229
Directory /workspace/33.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.4018162906
Short name T73
Test name
Test status
Simulation time 336800930000 ps
CPU time 705.47 seconds
Started Jul 21 04:23:07 PM PDT 24
Finished Jul 21 04:52:06 PM PDT 24
Peak memory 160628 kb
Host smart-b0604b90-93e9-4690-b968-1ed07c71a95a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4018162906 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.4018162906
Directory /workspace/34.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.1021827610
Short name T89
Test name
Test status
Simulation time 336528050000 ps
CPU time 770.99 seconds
Started Jul 21 04:20:45 PM PDT 24
Finished Jul 21 04:52:05 PM PDT 24
Peak memory 160672 kb
Host smart-c2f1f361-033d-4fb0-b3d8-32a590fc31b5
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1021827610 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.1021827610
Directory /workspace/35.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.1382536911
Short name T94
Test name
Test status
Simulation time 336599410000 ps
CPU time 704.82 seconds
Started Jul 21 04:23:21 PM PDT 24
Finished Jul 21 04:52:31 PM PDT 24
Peak memory 160528 kb
Host smart-fa491f79-1b51-4248-8de0-9c76599dab43
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1382536911 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.1382536911
Directory /workspace/36.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.485482311
Short name T76
Test name
Test status
Simulation time 337106070000 ps
CPU time 770.42 seconds
Started Jul 21 04:23:28 PM PDT 24
Finished Jul 21 04:55:00 PM PDT 24
Peak memory 160600 kb
Host smart-6543620d-af52-4ba7-845c-305c7d12c2c6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=485482311 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.485482311
Directory /workspace/37.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.335952774
Short name T98
Test name
Test status
Simulation time 336479070000 ps
CPU time 751.73 seconds
Started Jul 21 04:21:18 PM PDT 24
Finished Jul 21 04:51:54 PM PDT 24
Peak memory 160672 kb
Host smart-3616425e-8f6a-49ac-bd7a-6f29f48a80cb
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=335952774 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.335952774
Directory /workspace/38.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.1127054652
Short name T77
Test name
Test status
Simulation time 336661310000 ps
CPU time 714.65 seconds
Started Jul 21 04:22:42 PM PDT 24
Finished Jul 21 04:52:21 PM PDT 24
Peak memory 160448 kb
Host smart-c19fb876-ac58-4155-8032-9523a418bfdf
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1127054652 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.1127054652
Directory /workspace/39.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.1933955768
Short name T95
Test name
Test status
Simulation time 336322110000 ps
CPU time 654.96 seconds
Started Jul 21 04:19:56 PM PDT 24
Finished Jul 21 04:47:03 PM PDT 24
Peak memory 160672 kb
Host smart-e138528b-4ae2-41c9-8a66-b45cdfaef2f3
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1933955768 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.1933955768
Directory /workspace/4.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.1981040584
Short name T85
Test name
Test status
Simulation time 336545330000 ps
CPU time 716.97 seconds
Started Jul 21 04:22:41 PM PDT 24
Finished Jul 21 04:52:31 PM PDT 24
Peak memory 160068 kb
Host smart-d64ecd89-19e2-4717-9ec5-27d00eca14d9
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1981040584 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.1981040584
Directory /workspace/40.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.2820814662
Short name T20
Test name
Test status
Simulation time 336741110000 ps
CPU time 734.89 seconds
Started Jul 21 04:22:40 PM PDT 24
Finished Jul 21 04:53:01 PM PDT 24
Peak memory 159532 kb
Host smart-908ab681-7704-4e9b-a86c-1243fb319453
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2820814662 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.2820814662
Directory /workspace/41.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.3771870578
Short name T83
Test name
Test status
Simulation time 336524970000 ps
CPU time 841.53 seconds
Started Jul 21 04:20:28 PM PDT 24
Finished Jul 21 04:55:08 PM PDT 24
Peak memory 160876 kb
Host smart-0c834cfc-d81f-4390-86ca-218a4d7ca768
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3771870578 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.3771870578
Directory /workspace/42.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.1537487312
Short name T71
Test name
Test status
Simulation time 336394790000 ps
CPU time 794.92 seconds
Started Jul 21 04:20:57 PM PDT 24
Finished Jul 21 04:53:33 PM PDT 24
Peak memory 160652 kb
Host smart-61525a58-8339-451c-947a-a316203d1522
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1537487312 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.1537487312
Directory /workspace/43.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.3874028878
Short name T104
Test name
Test status
Simulation time 336728250000 ps
CPU time 914.26 seconds
Started Jul 21 04:20:14 PM PDT 24
Finished Jul 21 04:58:43 PM PDT 24
Peak memory 160704 kb
Host smart-e86a2ebb-eb69-4423-abd2-93769e421ae8
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3874028878 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.3874028878
Directory /workspace/44.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.4023674314
Short name T93
Test name
Test status
Simulation time 336720110000 ps
CPU time 748.65 seconds
Started Jul 21 04:22:54 PM PDT 24
Finished Jul 21 04:53:57 PM PDT 24
Peak memory 160592 kb
Host smart-3d483f60-e56c-4808-a09b-415e60c90655
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4023674314 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.4023674314
Directory /workspace/45.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.2654699290
Short name T105
Test name
Test status
Simulation time 336466590000 ps
CPU time 767.23 seconds
Started Jul 21 04:23:06 PM PDT 24
Finished Jul 21 04:54:26 PM PDT 24
Peak memory 160500 kb
Host smart-a8609ac7-baf3-4575-887a-ac875df8f936
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2654699290 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.2654699290
Directory /workspace/46.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.4166707461
Short name T15
Test name
Test status
Simulation time 336636010000 ps
CPU time 725.15 seconds
Started Jul 21 04:22:52 PM PDT 24
Finished Jul 21 04:52:23 PM PDT 24
Peak memory 159504 kb
Host smart-6df6e62a-3ef8-4ce1-b7b3-cb027f14f505
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4166707461 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.4166707461
Directory /workspace/47.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.14525659
Short name T4
Test name
Test status
Simulation time 337068030000 ps
CPU time 732.29 seconds
Started Jul 21 04:22:40 PM PDT 24
Finished Jul 21 04:52:49 PM PDT 24
Peak memory 159604 kb
Host smart-f0b14bd8-7d12-46a6-a564-ea54b9509033
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=14525659 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.14525659
Directory /workspace/48.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.1424770749
Short name T100
Test name
Test status
Simulation time 336296750000 ps
CPU time 871.67 seconds
Started Jul 21 04:19:55 PM PDT 24
Finished Jul 21 04:55:17 PM PDT 24
Peak memory 160676 kb
Host smart-3c419f2f-30cd-49e1-b7c2-f7721c186b19
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1424770749 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.1424770749
Directory /workspace/49.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.1472585591
Short name T107
Test name
Test status
Simulation time 336784710000 ps
CPU time 683.37 seconds
Started Jul 21 04:22:45 PM PDT 24
Finished Jul 21 04:51:11 PM PDT 24
Peak memory 158744 kb
Host smart-f4c78dd3-acec-4a90-8dca-5e67f56127b2
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1472585591 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.1472585591
Directory /workspace/5.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.28574280
Short name T81
Test name
Test status
Simulation time 337041710000 ps
CPU time 745.21 seconds
Started Jul 21 04:23:03 PM PDT 24
Finished Jul 21 04:53:18 PM PDT 24
Peak memory 159752 kb
Host smart-a5f0076c-62ea-4710-b74a-2224f03d5b1d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=28574280 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.28574280
Directory /workspace/6.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.2111808062
Short name T80
Test name
Test status
Simulation time 337043730000 ps
CPU time 735.56 seconds
Started Jul 21 04:23:11 PM PDT 24
Finished Jul 21 04:53:25 PM PDT 24
Peak memory 160164 kb
Host smart-515b1b1c-44b9-4568-abca-f43538597778
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2111808062 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.2111808062
Directory /workspace/7.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1238181174
Short name T101
Test name
Test status
Simulation time 336495010000 ps
CPU time 741.62 seconds
Started Jul 21 04:23:11 PM PDT 24
Finished Jul 21 04:53:38 PM PDT 24
Peak memory 160140 kb
Host smart-4b021910-2b7c-4f1f-84e1-8908143f4905
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1238181174 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.1238181174
Directory /workspace/8.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.1295152366
Short name T18
Test name
Test status
Simulation time 336476690000 ps
CPU time 929.04 seconds
Started Jul 21 04:18:54 PM PDT 24
Finished Jul 21 04:57:24 PM PDT 24
Peak memory 160524 kb
Host smart-2dbe3958-452e-4adc-b969-68027501ec43
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1295152366 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.1295152366
Directory /workspace/9.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.2980119152
Short name T179
Test name
Test status
Simulation time 336667250000 ps
CPU time 791.88 seconds
Started Jul 21 04:18:59 PM PDT 24
Finished Jul 21 04:51:34 PM PDT 24
Peak memory 160472 kb
Host smart-90d73292-9a00-4424-b567-7f80d0ebc408
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2980119152 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.2980119152
Directory /workspace/1.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.3692314817
Short name T175
Test name
Test status
Simulation time 337036970000 ps
CPU time 641.87 seconds
Started Jul 21 04:22:46 PM PDT 24
Finished Jul 21 04:49:18 PM PDT 24
Peak memory 160320 kb
Host smart-549f9c8e-38dd-49af-b7f5-d81ce5a8bc3d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3692314817 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.3692314817
Directory /workspace/10.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.3261533952
Short name T198
Test name
Test status
Simulation time 336394470000 ps
CPU time 707.97 seconds
Started Jul 21 04:23:24 PM PDT 24
Finished Jul 21 04:52:40 PM PDT 24
Peak memory 159640 kb
Host smart-2fa791e2-ac0d-47a0-8ca8-78d94ffebf4d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3261533952 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.3261533952
Directory /workspace/11.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.1777994880
Short name T164
Test name
Test status
Simulation time 336993590000 ps
CPU time 856.16 seconds
Started Jul 21 04:22:45 PM PDT 24
Finished Jul 21 04:57:56 PM PDT 24
Peak memory 158112 kb
Host smart-51e12678-f73f-48ae-9f91-a01a95ce49aa
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1777994880 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.1777994880
Directory /workspace/12.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.3620787990
Short name T181
Test name
Test status
Simulation time 336900090000 ps
CPU time 858.5 seconds
Started Jul 21 04:22:46 PM PDT 24
Finished Jul 21 04:58:10 PM PDT 24
Peak memory 160292 kb
Host smart-c6816554-de03-4b32-9a74-46c8d251c8ad
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3620787990 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.3620787990
Directory /workspace/13.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.1692420225
Short name T22
Test name
Test status
Simulation time 337107190000 ps
CPU time 743.53 seconds
Started Jul 21 04:19:55 PM PDT 24
Finished Jul 21 04:50:27 PM PDT 24
Peak memory 160716 kb
Host smart-e2becbc7-576d-4bc4-b791-2a06aab652c3
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1692420225 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.1692420225
Directory /workspace/14.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.4145153416
Short name T171
Test name
Test status
Simulation time 336925470000 ps
CPU time 861.42 seconds
Started Jul 21 04:22:45 PM PDT 24
Finished Jul 21 04:58:01 PM PDT 24
Peak memory 158168 kb
Host smart-600ec488-78ea-46b8-aeec-e840bc410274
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4145153416 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.4145153416
Directory /workspace/15.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.3300695862
Short name T29
Test name
Test status
Simulation time 336506490000 ps
CPU time 888.54 seconds
Started Jul 21 04:22:45 PM PDT 24
Finished Jul 21 04:59:07 PM PDT 24
Peak memory 158212 kb
Host smart-79772f5a-a996-431e-be8c-128f1e51d156
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3300695862 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.3300695862
Directory /workspace/16.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.3212449564
Short name T200
Test name
Test status
Simulation time 336643390000 ps
CPU time 820.57 seconds
Started Jul 21 04:22:45 PM PDT 24
Finished Jul 21 04:56:32 PM PDT 24
Peak memory 158192 kb
Host smart-e993bab2-0b0d-4d53-a544-5ba9da97558c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3212449564 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.3212449564
Directory /workspace/17.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.290000959
Short name T166
Test name
Test status
Simulation time 336869070000 ps
CPU time 769.08 seconds
Started Jul 21 04:23:40 PM PDT 24
Finished Jul 21 04:55:21 PM PDT 24
Peak memory 160444 kb
Host smart-7dca9d0d-0b3b-443f-af7d-c63186e9af75
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=290000959 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.290000959
Directory /workspace/18.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.2501786606
Short name T185
Test name
Test status
Simulation time 336663870000 ps
CPU time 942.91 seconds
Started Jul 21 04:19:17 PM PDT 24
Finished Jul 21 04:58:39 PM PDT 24
Peak memory 160624 kb
Host smart-65643265-2a11-4d47-85c1-d439c3a2215f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2501786606 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.2501786606
Directory /workspace/19.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.489743898
Short name T177
Test name
Test status
Simulation time 336701530000 ps
CPU time 725.76 seconds
Started Jul 21 04:18:49 PM PDT 24
Finished Jul 21 04:48:26 PM PDT 24
Peak memory 160260 kb
Host smart-6ba37638-aeec-4045-ba61-e515cf587801
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=489743898 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.489743898
Directory /workspace/2.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.3282108511
Short name T189
Test name
Test status
Simulation time 336478450000 ps
CPU time 839.94 seconds
Started Jul 21 04:20:28 PM PDT 24
Finished Jul 21 04:55:07 PM PDT 24
Peak memory 160880 kb
Host smart-f1842099-43b0-455f-aa78-7e182c1fe015
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3282108511 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.3282108511
Directory /workspace/20.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3273022622
Short name T184
Test name
Test status
Simulation time 336667770000 ps
CPU time 762.07 seconds
Started Jul 21 04:20:19 PM PDT 24
Finished Jul 21 04:51:42 PM PDT 24
Peak memory 160776 kb
Host smart-d0d767f8-6b77-4bb0-b3ea-9aebb9cb73b3
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3273022622 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.3273022622
Directory /workspace/21.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.996108628
Short name T174
Test name
Test status
Simulation time 336330890000 ps
CPU time 624.24 seconds
Started Jul 21 04:23:19 PM PDT 24
Finished Jul 21 04:49:10 PM PDT 24
Peak memory 160424 kb
Host smart-3bc801fc-f927-4836-964a-60ad97c7b840
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=996108628 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.996108628
Directory /workspace/22.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.491170656
Short name T168
Test name
Test status
Simulation time 336531930000 ps
CPU time 817.06 seconds
Started Jul 21 04:18:59 PM PDT 24
Finished Jul 21 04:52:36 PM PDT 24
Peak memory 160480 kb
Host smart-98f8f406-df7b-4e4b-8bf4-a79ce68cf5f0
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=491170656 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.491170656
Directory /workspace/23.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.1263034628
Short name T163
Test name
Test status
Simulation time 336793310000 ps
CPU time 715.92 seconds
Started Jul 21 04:23:03 PM PDT 24
Finished Jul 21 04:52:25 PM PDT 24
Peak memory 160348 kb
Host smart-601b3cf1-c1b5-4c0a-871b-358a90d9cb9a
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1263034628 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.1263034628
Directory /workspace/24.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.1924288520
Short name T188
Test name
Test status
Simulation time 336602410000 ps
CPU time 716.46 seconds
Started Jul 21 04:19:48 PM PDT 24
Finished Jul 21 04:48:49 PM PDT 24
Peak memory 160764 kb
Host smart-75389e03-47d5-4316-b5f8-bbd6c722eebb
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1924288520 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.1924288520
Directory /workspace/25.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.881758060
Short name T183
Test name
Test status
Simulation time 336703530000 ps
CPU time 988.83 seconds
Started Jul 21 04:23:16 PM PDT 24
Finished Jul 21 05:04:07 PM PDT 24
Peak memory 160352 kb
Host smart-4427c977-e7f8-4d02-8f66-364c4a9196eb
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=881758060 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.881758060
Directory /workspace/26.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.3367773337
Short name T24
Test name
Test status
Simulation time 336675810000 ps
CPU time 949.61 seconds
Started Jul 21 04:23:04 PM PDT 24
Finished Jul 21 05:03:07 PM PDT 24
Peak memory 158676 kb
Host smart-70f5fff9-a21d-4aa2-bb84-7726251cad63
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3367773337 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.3367773337
Directory /workspace/27.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.2978817094
Short name T194
Test name
Test status
Simulation time 336488710000 ps
CPU time 727.05 seconds
Started Jul 21 04:19:51 PM PDT 24
Finished Jul 21 04:49:16 PM PDT 24
Peak memory 160648 kb
Host smart-661c4973-19b7-474e-bb9e-977a22ccb1bc
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2978817094 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.2978817094
Directory /workspace/28.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.996001149
Short name T21
Test name
Test status
Simulation time 336331970000 ps
CPU time 632.07 seconds
Started Jul 21 04:18:55 PM PDT 24
Finished Jul 21 04:44:35 PM PDT 24
Peak memory 160480 kb
Host smart-70e91a3e-1a49-4251-a2c9-c42323f16dd1
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=996001149 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.996001149
Directory /workspace/29.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.1872886046
Short name T172
Test name
Test status
Simulation time 336655090000 ps
CPU time 788.69 seconds
Started Jul 21 04:20:15 PM PDT 24
Finished Jul 21 04:52:29 PM PDT 24
Peak memory 160408 kb
Host smart-cac52390-5ddd-4e62-bf69-f4c0d21bbcbd
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1872886046 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.1872886046
Directory /workspace/3.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.2582727314
Short name T165
Test name
Test status
Simulation time 337029310000 ps
CPU time 843.85 seconds
Started Jul 21 04:20:42 PM PDT 24
Finished Jul 21 04:55:28 PM PDT 24
Peak memory 160684 kb
Host smart-e7b1dca2-e8dc-48ef-a323-358f33a5f3d9
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2582727314 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.2582727314
Directory /workspace/30.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.1276406216
Short name T195
Test name
Test status
Simulation time 336469410000 ps
CPU time 686.85 seconds
Started Jul 21 04:24:01 PM PDT 24
Finished Jul 21 04:52:37 PM PDT 24
Peak memory 160624 kb
Host smart-af276df5-7e09-480a-8f2b-15690568dea5
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1276406216 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.1276406216
Directory /workspace/31.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.3496173423
Short name T182
Test name
Test status
Simulation time 336779190000 ps
CPU time 676.88 seconds
Started Jul 21 04:23:11 PM PDT 24
Finished Jul 21 04:50:58 PM PDT 24
Peak memory 160528 kb
Host smart-9393d4a0-d65d-4612-b13f-cce538ae5358
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3496173423 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.3496173423
Directory /workspace/32.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.3347200122
Short name T176
Test name
Test status
Simulation time 336521410000 ps
CPU time 834.74 seconds
Started Jul 21 04:20:20 PM PDT 24
Finished Jul 21 04:54:27 PM PDT 24
Peak memory 160708 kb
Host smart-c459649a-694a-4003-86a1-8faa15681522
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3347200122 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.3347200122
Directory /workspace/33.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.301244542
Short name T193
Test name
Test status
Simulation time 337061130000 ps
CPU time 665.31 seconds
Started Jul 21 04:23:11 PM PDT 24
Finished Jul 21 04:50:39 PM PDT 24
Peak memory 160524 kb
Host smart-450c24bd-70b2-4dab-ad65-32399607da20
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=301244542 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.301244542
Directory /workspace/34.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.1823448992
Short name T161
Test name
Test status
Simulation time 336536090000 ps
CPU time 760.55 seconds
Started Jul 21 04:23:28 PM PDT 24
Finished Jul 21 04:54:42 PM PDT 24
Peak memory 160628 kb
Host smart-898fd34b-a005-416e-827b-6b7e0d7bc911
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1823448992 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.1823448992
Directory /workspace/35.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.761477146
Short name T187
Test name
Test status
Simulation time 336424070000 ps
CPU time 741.67 seconds
Started Jul 21 04:23:04 PM PDT 24
Finished Jul 21 04:53:21 PM PDT 24
Peak memory 160464 kb
Host smart-63dd5cbc-f1bb-439b-961d-f4306dd88e60
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=761477146 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.761477146
Directory /workspace/36.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.4278241451
Short name T196
Test name
Test status
Simulation time 336634730000 ps
CPU time 688.04 seconds
Started Jul 21 04:23:49 PM PDT 24
Finished Jul 21 04:52:31 PM PDT 24
Peak memory 159496 kb
Host smart-7d0a55ea-95c9-4b62-ae66-74b94ee8ca18
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4278241451 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.4278241451
Directory /workspace/37.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3335780087
Short name T192
Test name
Test status
Simulation time 336966510000 ps
CPU time 732.65 seconds
Started Jul 21 04:24:02 PM PDT 24
Finished Jul 21 04:54:05 PM PDT 24
Peak memory 160644 kb
Host smart-11e25b1e-fdc1-40db-b90a-3896e3500535
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3335780087 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.3335780087
Directory /workspace/38.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.2177980433
Short name T23
Test name
Test status
Simulation time 336366150000 ps
CPU time 827.63 seconds
Started Jul 21 04:20:21 PM PDT 24
Finished Jul 21 04:54:10 PM PDT 24
Peak memory 160708 kb
Host smart-a1fa8597-d0e8-4435-8986-c75559410c69
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2177980433 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.2177980433
Directory /workspace/39.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.4094009841
Short name T180
Test name
Test status
Simulation time 336635030000 ps
CPU time 663.43 seconds
Started Jul 21 04:22:41 PM PDT 24
Finished Jul 21 04:50:01 PM PDT 24
Peak memory 159972 kb
Host smart-e7f6fb46-4ffc-4e9d-9831-81b2e33dbdfd
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4094009841 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.4094009841
Directory /workspace/4.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.2296239961
Short name T191
Test name
Test status
Simulation time 336976710000 ps
CPU time 688.97 seconds
Started Jul 21 04:23:14 PM PDT 24
Finished Jul 21 04:51:32 PM PDT 24
Peak memory 160680 kb
Host smart-ba8c8358-f6ab-4503-b0b3-089c795469ac
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2296239961 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.2296239961
Directory /workspace/40.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.226930895
Short name T197
Test name
Test status
Simulation time 337130670000 ps
CPU time 760.43 seconds
Started Jul 21 04:22:54 PM PDT 24
Finished Jul 21 04:54:14 PM PDT 24
Peak memory 160456 kb
Host smart-70613028-6809-4a5d-8de3-be43d10ab461
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=226930895 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.226930895
Directory /workspace/41.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.1739447019
Short name T199
Test name
Test status
Simulation time 336798070000 ps
CPU time 781.66 seconds
Started Jul 21 04:18:55 PM PDT 24
Finished Jul 21 04:50:51 PM PDT 24
Peak memory 160680 kb
Host smart-721c7962-30e0-445e-97a5-9a31491236b5
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1739447019 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.1739447019
Directory /workspace/42.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.2908249279
Short name T162
Test name
Test status
Simulation time 336684570000 ps
CPU time 664.35 seconds
Started Jul 21 04:23:49 PM PDT 24
Finished Jul 21 04:51:26 PM PDT 24
Peak memory 160636 kb
Host smart-af262c79-6a0f-49cd-aafa-ef8b16c10341
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2908249279 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.2908249279
Directory /workspace/43.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.3130339611
Short name T169
Test name
Test status
Simulation time 336574510000 ps
CPU time 752.66 seconds
Started Jul 21 04:23:47 PM PDT 24
Finished Jul 21 04:54:28 PM PDT 24
Peak memory 160604 kb
Host smart-5f8dca60-bf12-4591-8603-62db19dbe3be
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3130339611 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.3130339611
Directory /workspace/44.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.2653607154
Short name T30
Test name
Test status
Simulation time 336922650000 ps
CPU time 642.96 seconds
Started Jul 21 04:23:51 PM PDT 24
Finished Jul 21 04:50:32 PM PDT 24
Peak memory 160584 kb
Host smart-9f73fbaf-254f-4d02-aa66-3493eff079f2
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2653607154 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.2653607154
Directory /workspace/45.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.810175130
Short name T186
Test name
Test status
Simulation time 336964690000 ps
CPU time 761.72 seconds
Started Jul 21 04:24:01 PM PDT 24
Finished Jul 21 04:55:20 PM PDT 24
Peak memory 160636 kb
Host smart-1692454f-7865-4230-a51c-2e26786ddcac
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=810175130 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.810175130
Directory /workspace/46.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.1308125733
Short name T167
Test name
Test status
Simulation time 336915270000 ps
CPU time 740.8 seconds
Started Jul 21 04:23:50 PM PDT 24
Finished Jul 21 04:54:26 PM PDT 24
Peak memory 160652 kb
Host smart-d854fc53-9e73-4ee9-a99c-7991be9a6c0e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1308125733 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.1308125733
Directory /workspace/47.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.2655892914
Short name T178
Test name
Test status
Simulation time 337118750000 ps
CPU time 764.8 seconds
Started Jul 21 04:24:00 PM PDT 24
Finished Jul 21 04:55:21 PM PDT 24
Peak memory 160644 kb
Host smart-513fac13-b68b-43bd-8378-38ad3611ad40
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2655892914 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.2655892914
Directory /workspace/48.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.4025225748
Short name T170
Test name
Test status
Simulation time 336532370000 ps
CPU time 647.82 seconds
Started Jul 21 04:23:46 PM PDT 24
Finished Jul 21 04:50:29 PM PDT 24
Peak memory 160576 kb
Host smart-4d266b33-4b7e-468d-bee7-bc396457ca7b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4025225748 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.4025225748
Directory /workspace/49.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.292651449
Short name T27
Test name
Test status
Simulation time 336320670000 ps
CPU time 702.43 seconds
Started Jul 21 04:22:41 PM PDT 24
Finished Jul 21 04:51:24 PM PDT 24
Peak memory 159628 kb
Host smart-ff2ba58a-a18a-4dc3-9975-9abd8a7a67c7
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=292651449 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.292651449
Directory /workspace/5.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.1173796076
Short name T26
Test name
Test status
Simulation time 336587750000 ps
CPU time 698.53 seconds
Started Jul 21 04:22:45 PM PDT 24
Finished Jul 21 04:51:31 PM PDT 24
Peak memory 158848 kb
Host smart-35a2f649-3f1c-4ee8-adbb-72bc958ed292
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1173796076 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.1173796076
Directory /workspace/6.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.556669663
Short name T25
Test name
Test status
Simulation time 337114090000 ps
CPU time 775.05 seconds
Started Jul 21 04:19:03 PM PDT 24
Finished Jul 21 04:50:57 PM PDT 24
Peak memory 160660 kb
Host smart-a89c2a6f-a09a-4625-aa95-a6ae0b285168
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=556669663 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.556669663
Directory /workspace/7.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.2008402771
Short name T173
Test name
Test status
Simulation time 336975570000 ps
CPU time 707.74 seconds
Started Jul 21 04:22:52 PM PDT 24
Finished Jul 21 04:51:54 PM PDT 24
Peak memory 159488 kb
Host smart-3dd25614-180c-45d6-a5ac-9b37d8ea3d01
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2008402771 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.2008402771
Directory /workspace/8.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.1731113028
Short name T190
Test name
Test status
Simulation time 337032530000 ps
CPU time 726.55 seconds
Started Jul 21 04:21:30 PM PDT 24
Finished Jul 21 04:51:16 PM PDT 24
Peak memory 160744 kb
Host smart-91ebbf0e-5f21-4392-a39c-1aabfed36968
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1731113028 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.1731113028
Directory /workspace/9.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.589392131
Short name T115
Test name
Test status
Simulation time 1407490000 ps
CPU time 4.42 seconds
Started Jul 21 04:19:54 PM PDT 24
Finished Jul 21 04:20:04 PM PDT 24
Peak memory 164524 kb
Host smart-283a981c-52b9-4285-bef3-450d465745c1
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=589392131 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.589392131
Directory /workspace/0.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.3781773506
Short name T128
Test name
Test status
Simulation time 1537870000 ps
CPU time 4.13 seconds
Started Jul 21 04:23:07 PM PDT 24
Finished Jul 21 04:23:17 PM PDT 24
Peak memory 164660 kb
Host smart-eb21debf-b17c-4179-8c91-1618c5a075ad
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3781773506 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.3781773506
Directory /workspace/1.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.1764037985
Short name T119
Test name
Test status
Simulation time 1467170000 ps
CPU time 4.96 seconds
Started Jul 21 04:19:33 PM PDT 24
Finished Jul 21 04:19:45 PM PDT 24
Peak memory 164660 kb
Host smart-3f44d55d-80fd-42a6-922f-0721e9fea03e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1764037985 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.1764037985
Directory /workspace/10.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.1566641814
Short name T142
Test name
Test status
Simulation time 1456630000 ps
CPU time 4.35 seconds
Started Jul 21 04:23:02 PM PDT 24
Finished Jul 21 04:23:12 PM PDT 24
Peak memory 164536 kb
Host smart-a2371591-c818-4782-b2ec-268c8d83e164
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1566641814 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.1566641814
Directory /workspace/11.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.3580527330
Short name T125
Test name
Test status
Simulation time 1609350000 ps
CPU time 4.55 seconds
Started Jul 21 04:20:58 PM PDT 24
Finished Jul 21 04:21:08 PM PDT 24
Peak memory 164760 kb
Host smart-cfba460e-ef8b-45fe-9d53-e876ca2829d9
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3580527330 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.3580527330
Directory /workspace/12.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.729069785
Short name T139
Test name
Test status
Simulation time 1316450000 ps
CPU time 4.17 seconds
Started Jul 21 04:22:46 PM PDT 24
Finished Jul 21 04:22:56 PM PDT 24
Peak memory 164424 kb
Host smart-6b192841-dad4-483a-b58e-0e43f6a4b54c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=729069785 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.729069785
Directory /workspace/13.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.263071482
Short name T122
Test name
Test status
Simulation time 1072790000 ps
CPU time 3.21 seconds
Started Jul 21 04:18:58 PM PDT 24
Finished Jul 21 04:19:05 PM PDT 24
Peak memory 164360 kb
Host smart-78888b2e-48e1-4071-b53d-4d542bba7918
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=263071482 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.263071482
Directory /workspace/14.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.617550338
Short name T156
Test name
Test status
Simulation time 1491870000 ps
CPU time 5.04 seconds
Started Jul 21 04:19:56 PM PDT 24
Finished Jul 21 04:20:07 PM PDT 24
Peak memory 164964 kb
Host smart-fd8e850e-d4d2-482a-9bb0-bca4296d148d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=617550338 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.617550338
Directory /workspace/15.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.1849168989
Short name T132
Test name
Test status
Simulation time 1279710000 ps
CPU time 3.31 seconds
Started Jul 21 04:23:11 PM PDT 24
Finished Jul 21 04:23:19 PM PDT 24
Peak memory 163404 kb
Host smart-2ab0bd3f-5c50-4005-b900-00ce010a9a3e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1849168989 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.1849168989
Directory /workspace/16.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.1969596370
Short name T149
Test name
Test status
Simulation time 1497430000 ps
CPU time 4.14 seconds
Started Jul 21 04:18:54 PM PDT 24
Finished Jul 21 04:19:03 PM PDT 24
Peak memory 164808 kb
Host smart-c705b44b-441e-4b11-97a5-54e548e6ba6d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1969596370 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.1969596370
Directory /workspace/17.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.2229537865
Short name T157
Test name
Test status
Simulation time 1262130000 ps
CPU time 3.32 seconds
Started Jul 21 04:23:19 PM PDT 24
Finished Jul 21 04:23:27 PM PDT 24
Peak memory 164548 kb
Host smart-1a317ac3-f83a-472a-83e4-2117778c7155
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2229537865 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.2229537865
Directory /workspace/18.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.249772079
Short name T131
Test name
Test status
Simulation time 1412790000 ps
CPU time 4.05 seconds
Started Jul 21 04:21:10 PM PDT 24
Finished Jul 21 04:21:19 PM PDT 24
Peak memory 164844 kb
Host smart-6b2bd2ef-eebe-4e8d-97be-4086c751cb70
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=249772079 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.249772079
Directory /workspace/19.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.754555946
Short name T130
Test name
Test status
Simulation time 994290000 ps
CPU time 2.57 seconds
Started Jul 21 04:23:07 PM PDT 24
Finished Jul 21 04:23:14 PM PDT 24
Peak memory 164712 kb
Host smart-f2a44687-45ee-4f33-afa2-8419f383ae1f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=754555946 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.754555946
Directory /workspace/2.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.3178341286
Short name T112
Test name
Test status
Simulation time 1545510000 ps
CPU time 3.98 seconds
Started Jul 21 04:19:39 PM PDT 24
Finished Jul 21 04:19:48 PM PDT 24
Peak memory 164804 kb
Host smart-d8933712-ef05-4fee-adc9-533e0ed975c9
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3178341286 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.3178341286
Directory /workspace/20.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.1218682070
Short name T148
Test name
Test status
Simulation time 1376190000 ps
CPU time 5.12 seconds
Started Jul 21 04:19:04 PM PDT 24
Finished Jul 21 04:19:15 PM PDT 24
Peak memory 164660 kb
Host smart-bd111aea-8a1b-4b43-8ba9-39e97be6783b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1218682070 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.1218682070
Directory /workspace/21.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.3876971198
Short name T141
Test name
Test status
Simulation time 1518110000 ps
CPU time 4.58 seconds
Started Jul 21 04:20:33 PM PDT 24
Finished Jul 21 04:20:43 PM PDT 24
Peak memory 164796 kb
Host smart-5f4fedf7-e5f9-4d02-a289-b3cc3f2c7f4c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3876971198 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.3876971198
Directory /workspace/22.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.3751371982
Short name T136
Test name
Test status
Simulation time 1478790000 ps
CPU time 4.42 seconds
Started Jul 21 04:21:52 PM PDT 24
Finished Jul 21 04:22:02 PM PDT 24
Peak memory 164928 kb
Host smart-a5e5e23e-1ced-4f4b-a09e-1b4184df1bf9
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3751371982 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.3751371982
Directory /workspace/23.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.3365679591
Short name T116
Test name
Test status
Simulation time 1090770000 ps
CPU time 3.26 seconds
Started Jul 21 04:18:55 PM PDT 24
Finished Jul 21 04:19:02 PM PDT 24
Peak memory 164628 kb
Host smart-f3f049a5-2cc5-4e20-bde0-be59caa6b649
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3365679591 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.3365679591
Directory /workspace/24.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.4126234938
Short name T117
Test name
Test status
Simulation time 1506570000 ps
CPU time 4.34 seconds
Started Jul 21 04:23:11 PM PDT 24
Finished Jul 21 04:23:21 PM PDT 24
Peak memory 164576 kb
Host smart-71383cd1-7a2d-453c-98ab-0eefaf3fa392
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4126234938 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.4126234938
Directory /workspace/25.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.1687971085
Short name T159
Test name
Test status
Simulation time 1483390000 ps
CPU time 3.94 seconds
Started Jul 21 04:23:02 PM PDT 24
Finished Jul 21 04:23:11 PM PDT 24
Peak memory 163572 kb
Host smart-28dfce6e-cbe1-4b43-89aa-33634f7dd48f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1687971085 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.1687971085
Directory /workspace/26.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.406735013
Short name T124
Test name
Test status
Simulation time 1475910000 ps
CPU time 4.24 seconds
Started Jul 21 04:23:11 PM PDT 24
Finished Jul 21 04:23:21 PM PDT 24
Peak memory 164572 kb
Host smart-8be174fb-d23a-4f1b-ac31-f0558797730e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=406735013 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.406735013
Directory /workspace/27.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.1692776004
Short name T137
Test name
Test status
Simulation time 1536470000 ps
CPU time 3.98 seconds
Started Jul 21 04:22:14 PM PDT 24
Finished Jul 21 04:22:24 PM PDT 24
Peak memory 164852 kb
Host smart-e0007850-6adc-4619-a1d1-60b2d6a6a4ca
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1692776004 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.1692776004
Directory /workspace/28.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.935822382
Short name T144
Test name
Test status
Simulation time 1543310000 ps
CPU time 5.31 seconds
Started Jul 21 04:18:59 PM PDT 24
Finished Jul 21 04:19:11 PM PDT 24
Peak memory 164964 kb
Host smart-dcbceaf0-92c8-435c-8bb8-d5324ca809f1
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=935822382 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.935822382
Directory /workspace/29.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.864256810
Short name T118
Test name
Test status
Simulation time 1060970000 ps
CPU time 3.11 seconds
Started Jul 21 04:22:53 PM PDT 24
Finished Jul 21 04:23:01 PM PDT 24
Peak memory 164492 kb
Host smart-b3055f70-38ea-40f6-aef6-0dde43689dcf
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=864256810 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.864256810
Directory /workspace/3.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.36905768
Short name T121
Test name
Test status
Simulation time 1525910000 ps
CPU time 3.06 seconds
Started Jul 21 04:22:43 PM PDT 24
Finished Jul 21 04:22:50 PM PDT 24
Peak memory 164336 kb
Host smart-f54376cd-5079-4cfe-ae9e-2e48c066b15e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=36905768 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.36905768
Directory /workspace/30.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.871426582
Short name T111
Test name
Test status
Simulation time 1492430000 ps
CPU time 3.7 seconds
Started Jul 21 04:22:52 PM PDT 24
Finished Jul 21 04:23:02 PM PDT 24
Peak memory 163264 kb
Host smart-628824b3-b1db-41d7-a62b-40efb0993dc4
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=871426582 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.871426582
Directory /workspace/31.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.2774641587
Short name T158
Test name
Test status
Simulation time 1462350000 ps
CPU time 3.42 seconds
Started Jul 21 04:20:25 PM PDT 24
Finished Jul 21 04:20:33 PM PDT 24
Peak memory 164812 kb
Host smart-3ee61519-2015-4f3b-97ad-705796a2829a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2774641587 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.2774641587
Directory /workspace/32.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.35780950
Short name T140
Test name
Test status
Simulation time 1251950000 ps
CPU time 3.15 seconds
Started Jul 21 04:22:52 PM PDT 24
Finished Jul 21 04:23:01 PM PDT 24
Peak memory 163892 kb
Host smart-cccd95d8-d4f0-4713-9d53-6727a7d7d272
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=35780950 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.35780950
Directory /workspace/33.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.3429887452
Short name T138
Test name
Test status
Simulation time 1512730000 ps
CPU time 4.3 seconds
Started Jul 21 04:23:28 PM PDT 24
Finished Jul 21 04:23:39 PM PDT 24
Peak memory 164812 kb
Host smart-2c5d4d25-51e1-477d-8ff1-e5ef0e3169b1
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3429887452 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.3429887452
Directory /workspace/34.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.2058597692
Short name T151
Test name
Test status
Simulation time 1458290000 ps
CPU time 4.15 seconds
Started Jul 21 04:23:40 PM PDT 24
Finished Jul 21 04:23:50 PM PDT 24
Peak memory 164568 kb
Host smart-fd058c5d-d718-4f00-8f61-4b3b76fbc050
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2058597692 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.2058597692
Directory /workspace/35.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.2119087239
Short name T133
Test name
Test status
Simulation time 1384430000 ps
CPU time 3.77 seconds
Started Jul 21 04:23:59 PM PDT 24
Finished Jul 21 04:24:08 PM PDT 24
Peak memory 164568 kb
Host smart-32502ccd-6ce6-4573-b4a7-ede697a6b644
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2119087239 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.2119087239
Directory /workspace/36.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.4209889355
Short name T160
Test name
Test status
Simulation time 1363210000 ps
CPU time 3.32 seconds
Started Jul 21 04:23:06 PM PDT 24
Finished Jul 21 04:23:14 PM PDT 24
Peak memory 163380 kb
Host smart-32bc5b42-1272-48d0-8050-3d86a37a2d02
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4209889355 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.4209889355
Directory /workspace/37.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.3857807982
Short name T145
Test name
Test status
Simulation time 1433610000 ps
CPU time 3.53 seconds
Started Jul 21 04:23:06 PM PDT 24
Finished Jul 21 04:23:15 PM PDT 24
Peak memory 163292 kb
Host smart-cbd74df2-4722-4bff-84ff-e9a54c9db34d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3857807982 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.3857807982
Directory /workspace/38.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.1942989707
Short name T134
Test name
Test status
Simulation time 1437610000 ps
CPU time 3.68 seconds
Started Jul 21 04:22:41 PM PDT 24
Finished Jul 21 04:22:50 PM PDT 24
Peak memory 164024 kb
Host smart-3cb6dc27-aa62-4442-8df0-7ae62a36f1a2
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1942989707 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.1942989707
Directory /workspace/39.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3335155732
Short name T146
Test name
Test status
Simulation time 1546570000 ps
CPU time 4.79 seconds
Started Jul 21 04:19:14 PM PDT 24
Finished Jul 21 04:19:24 PM PDT 24
Peak memory 164948 kb
Host smart-02234d9d-5e4c-4abc-8003-230eb32e04e2
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3335155732 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.3335155732
Directory /workspace/4.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.1071285294
Short name T129
Test name
Test status
Simulation time 1520290000 ps
CPU time 5.64 seconds
Started Jul 21 04:20:24 PM PDT 24
Finished Jul 21 04:20:37 PM PDT 24
Peak memory 164788 kb
Host smart-4cce001a-5777-4ed7-8e9e-0c25373269ed
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1071285294 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.1071285294
Directory /workspace/40.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.3161321845
Short name T120
Test name
Test status
Simulation time 1550830000 ps
CPU time 4.59 seconds
Started Jul 21 04:20:24 PM PDT 24
Finished Jul 21 04:20:34 PM PDT 24
Peak memory 164812 kb
Host smart-efb3cd59-b3a6-4938-a385-beef6acf1cd5
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3161321845 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.3161321845
Directory /workspace/41.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.3723895005
Short name T126
Test name
Test status
Simulation time 1484210000 ps
CPU time 5.03 seconds
Started Jul 21 04:23:06 PM PDT 24
Finished Jul 21 04:23:17 PM PDT 24
Peak memory 164584 kb
Host smart-5a0b21ce-02d0-4f2d-adde-a1823082d0ac
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3723895005 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.3723895005
Directory /workspace/42.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.3227125427
Short name T127
Test name
Test status
Simulation time 1465410000 ps
CPU time 3.67 seconds
Started Jul 21 04:22:40 PM PDT 24
Finished Jul 21 04:22:48 PM PDT 24
Peak memory 164104 kb
Host smart-58e7d0e5-53fe-4b6f-9f67-91f9c0747947
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3227125427 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.3227125427
Directory /workspace/43.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.2365526417
Short name T150
Test name
Test status
Simulation time 1314050000 ps
CPU time 4.3 seconds
Started Jul 21 04:23:05 PM PDT 24
Finished Jul 21 04:23:15 PM PDT 24
Peak memory 164472 kb
Host smart-a9353503-2091-4ddf-80f0-4897bd24d936
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2365526417 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.2365526417
Directory /workspace/44.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.3980760425
Short name T143
Test name
Test status
Simulation time 1543090000 ps
CPU time 4.52 seconds
Started Jul 21 04:19:34 PM PDT 24
Finished Jul 21 04:19:44 PM PDT 24
Peak memory 164888 kb
Host smart-22f478fe-1b73-43c4-84b5-2e8aaadd4ffb
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3980760425 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.3980760425
Directory /workspace/45.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.156133252
Short name T147
Test name
Test status
Simulation time 1508250000 ps
CPU time 4.2 seconds
Started Jul 21 04:22:52 PM PDT 24
Finished Jul 21 04:23:04 PM PDT 24
Peak memory 164376 kb
Host smart-aaadef5d-4987-4120-a842-3a870346a7d4
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=156133252 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.156133252
Directory /workspace/46.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.842730683
Short name T113
Test name
Test status
Simulation time 1436890000 ps
CPU time 3.85 seconds
Started Jul 21 04:18:55 PM PDT 24
Finished Jul 21 04:19:04 PM PDT 24
Peak memory 164824 kb
Host smart-0648711e-a7c7-4c99-be94-1f3014ed7ced
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=842730683 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.842730683
Directory /workspace/47.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.2062550372
Short name T153
Test name
Test status
Simulation time 1462490000 ps
CPU time 5.18 seconds
Started Jul 21 04:19:55 PM PDT 24
Finished Jul 21 04:20:06 PM PDT 24
Peak memory 164788 kb
Host smart-f2ffe590-66f4-4054-beee-b7662909f42a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2062550372 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.2062550372
Directory /workspace/48.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.3295527859
Short name T114
Test name
Test status
Simulation time 1479150000 ps
CPU time 4.13 seconds
Started Jul 21 04:22:52 PM PDT 24
Finished Jul 21 04:23:02 PM PDT 24
Peak memory 163284 kb
Host smart-94594464-b632-4807-9724-b8d044327b25
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3295527859 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.3295527859
Directory /workspace/49.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.3792272928
Short name T135
Test name
Test status
Simulation time 1427850000 ps
CPU time 3.62 seconds
Started Jul 21 04:22:54 PM PDT 24
Finished Jul 21 04:23:03 PM PDT 24
Peak memory 164440 kb
Host smart-e5034f38-0495-4d08-8712-558cb9f865f2
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3792272928 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.3792272928
Directory /workspace/5.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.2051880762
Short name T155
Test name
Test status
Simulation time 1459770000 ps
CPU time 3.91 seconds
Started Jul 21 04:22:53 PM PDT 24
Finished Jul 21 04:23:03 PM PDT 24
Peak memory 164548 kb
Host smart-27e57944-bb58-42d4-8161-1032e80c322c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2051880762 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.2051880762
Directory /workspace/6.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.1028926980
Short name T123
Test name
Test status
Simulation time 1326090000 ps
CPU time 3.37 seconds
Started Jul 21 04:22:53 PM PDT 24
Finished Jul 21 04:23:03 PM PDT 24
Peak memory 163556 kb
Host smart-90c4bf73-e441-4516-8614-653b97e2ca07
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1028926980 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.1028926980
Directory /workspace/7.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1222159492
Short name T154
Test name
Test status
Simulation time 1386350000 ps
CPU time 3.14 seconds
Started Jul 21 04:22:45 PM PDT 24
Finished Jul 21 04:22:54 PM PDT 24
Peak memory 162592 kb
Host smart-791682d5-d81e-4cf8-9128-5068d3c67bfd
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1222159492 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.1222159492
Directory /workspace/8.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2033231498
Short name T152
Test name
Test status
Simulation time 1217130000 ps
CPU time 2.95 seconds
Started Jul 21 04:22:46 PM PDT 24
Finished Jul 21 04:22:54 PM PDT 24
Peak memory 164432 kb
Host smart-192835cd-e3dd-47de-84f0-41259384ec78
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2033231498 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.2033231498
Directory /workspace/9.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.1146298271
Short name T62
Test name
Test status
Simulation time 1333990000 ps
CPU time 3.3 seconds
Started Jul 21 05:01:29 PM PDT 24
Finished Jul 21 05:01:36 PM PDT 24
Peak memory 164848 kb
Host smart-1ad94828-02d2-47bc-862a-eb82ec0ad4c7
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1146298271 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.1146298271
Directory /workspace/0.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.3769067441
Short name T45
Test name
Test status
Simulation time 1475730000 ps
CPU time 5.28 seconds
Started Jul 21 05:01:38 PM PDT 24
Finished Jul 21 05:01:50 PM PDT 24
Peak memory 164864 kb
Host smart-600459f4-4d57-4170-ba78-ebd842fdbbc7
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3769067441 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.3769067441
Directory /workspace/1.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.574244975
Short name T63
Test name
Test status
Simulation time 1525290000 ps
CPU time 5.36 seconds
Started Jul 21 05:01:39 PM PDT 24
Finished Jul 21 05:01:52 PM PDT 24
Peak memory 164836 kb
Host smart-1056559e-f2b6-48db-ae93-d52baadd8a02
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=574244975 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.574244975
Directory /workspace/10.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.2908265861
Short name T32
Test name
Test status
Simulation time 1465690000 ps
CPU time 5.09 seconds
Started Jul 21 05:01:37 PM PDT 24
Finished Jul 21 05:01:49 PM PDT 24
Peak memory 164852 kb
Host smart-3ecd5f52-f3e7-40ad-9117-d85c2ce22ed0
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2908265861 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.2908265861
Directory /workspace/11.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.741572234
Short name T64
Test name
Test status
Simulation time 1563910000 ps
CPU time 6.9 seconds
Started Jul 21 05:01:38 PM PDT 24
Finished Jul 21 05:01:53 PM PDT 24
Peak memory 164856 kb
Host smart-993e07f6-cc46-46b9-9b9c-70e74c18d5b9
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=741572234 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.741572234
Directory /workspace/12.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.368752433
Short name T57
Test name
Test status
Simulation time 1290930000 ps
CPU time 4.01 seconds
Started Jul 21 05:01:41 PM PDT 24
Finished Jul 21 05:01:49 PM PDT 24
Peak memory 164900 kb
Host smart-f840066f-f611-4ff0-8985-973b43d7c677
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=368752433 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.368752433
Directory /workspace/13.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.388108286
Short name T61
Test name
Test status
Simulation time 1545490000 ps
CPU time 3.48 seconds
Started Jul 21 05:01:42 PM PDT 24
Finished Jul 21 05:01:50 PM PDT 24
Peak memory 164836 kb
Host smart-434a3d60-dc02-40ed-a5f2-939dd6f1f211
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=388108286 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.388108286
Directory /workspace/14.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.4270213884
Short name T44
Test name
Test status
Simulation time 1511350000 ps
CPU time 3.42 seconds
Started Jul 21 05:01:41 PM PDT 24
Finished Jul 21 05:01:49 PM PDT 24
Peak memory 164904 kb
Host smart-5bedc083-57c9-4e0f-8c39-d545ba0f091f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4270213884 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.4270213884
Directory /workspace/15.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.3839700836
Short name T47
Test name
Test status
Simulation time 1514890000 ps
CPU time 3.58 seconds
Started Jul 21 05:01:42 PM PDT 24
Finished Jul 21 05:01:51 PM PDT 24
Peak memory 164872 kb
Host smart-df0004f6-fc75-42a7-84d1-ca05ab4325b4
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3839700836 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.3839700836
Directory /workspace/16.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.965045966
Short name T41
Test name
Test status
Simulation time 1551870000 ps
CPU time 4.82 seconds
Started Jul 21 05:01:43 PM PDT 24
Finished Jul 21 05:01:54 PM PDT 24
Peak memory 164784 kb
Host smart-f1825f04-1149-45f1-9d8b-af309d18136a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=965045966 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.965045966
Directory /workspace/17.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.457759626
Short name T59
Test name
Test status
Simulation time 1421490000 ps
CPU time 5.83 seconds
Started Jul 21 05:01:42 PM PDT 24
Finished Jul 21 05:01:55 PM PDT 24
Peak memory 164816 kb
Host smart-1a9ff9ee-119d-456d-9479-411ff6670bd2
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=457759626 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.457759626
Directory /workspace/18.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.3408147021
Short name T31
Test name
Test status
Simulation time 1490710000 ps
CPU time 4.7 seconds
Started Jul 21 05:01:38 PM PDT 24
Finished Jul 21 05:01:49 PM PDT 24
Peak memory 164836 kb
Host smart-5dbb61d5-30f8-49c5-bd7f-d48d00dbf1ae
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3408147021 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.3408147021
Directory /workspace/2.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.4176052416
Short name T60
Test name
Test status
Simulation time 1244510000 ps
CPU time 3.83 seconds
Started Jul 21 05:01:44 PM PDT 24
Finished Jul 21 05:01:53 PM PDT 24
Peak memory 164852 kb
Host smart-941407bb-f1b0-4ace-a4a0-edb35f6684f7
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4176052416 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.4176052416
Directory /workspace/20.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.1073113042
Short name T42
Test name
Test status
Simulation time 1421710000 ps
CPU time 5.04 seconds
Started Jul 21 05:01:42 PM PDT 24
Finished Jul 21 05:01:54 PM PDT 24
Peak memory 164920 kb
Host smart-8b513d8c-33da-4662-98f3-73a6e0e5e90f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1073113042 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.1073113042
Directory /workspace/21.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.3017146098
Short name T53
Test name
Test status
Simulation time 1494290000 ps
CPU time 5.1 seconds
Started Jul 21 05:01:43 PM PDT 24
Finished Jul 21 05:01:55 PM PDT 24
Peak memory 164836 kb
Host smart-9f6fe022-5b12-41c3-b1e4-8ad5abeded84
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3017146098 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.3017146098
Directory /workspace/22.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.2434835036
Short name T12
Test name
Test status
Simulation time 1611190000 ps
CPU time 6.08 seconds
Started Jul 21 05:01:42 PM PDT 24
Finished Jul 21 05:01:56 PM PDT 24
Peak memory 164776 kb
Host smart-457ae7ec-ee43-454b-9ab3-4d4c99a76cd1
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2434835036 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.2434835036
Directory /workspace/23.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.827508303
Short name T67
Test name
Test status
Simulation time 1430110000 ps
CPU time 5.45 seconds
Started Jul 21 05:01:42 PM PDT 24
Finished Jul 21 05:01:54 PM PDT 24
Peak memory 164860 kb
Host smart-fd166135-e38f-4fc7-a668-adb850531fb3
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=827508303 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.827508303
Directory /workspace/24.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.1263912106
Short name T52
Test name
Test status
Simulation time 1520710000 ps
CPU time 6.05 seconds
Started Jul 21 05:01:42 PM PDT 24
Finished Jul 21 05:01:55 PM PDT 24
Peak memory 164848 kb
Host smart-a58d9c13-d579-4e97-ab3c-dc1682fd3494
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1263912106 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.1263912106
Directory /workspace/25.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.3328422908
Short name T9
Test name
Test status
Simulation time 1435490000 ps
CPU time 3.4 seconds
Started Jul 21 05:01:43 PM PDT 24
Finished Jul 21 05:01:51 PM PDT 24
Peak memory 164844 kb
Host smart-5465c9a4-508f-4ab7-b81b-a3af70a30a04
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3328422908 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.3328422908
Directory /workspace/26.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.2802727031
Short name T56
Test name
Test status
Simulation time 1576330000 ps
CPU time 6.01 seconds
Started Jul 21 05:01:49 PM PDT 24
Finished Jul 21 05:02:02 PM PDT 24
Peak memory 164856 kb
Host smart-1579cffb-90f5-4dfc-9251-a77d138e357a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2802727031 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.2802727031
Directory /workspace/27.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.2310746610
Short name T33
Test name
Test status
Simulation time 1413150000 ps
CPU time 4.82 seconds
Started Jul 21 05:01:49 PM PDT 24
Finished Jul 21 05:02:00 PM PDT 24
Peak memory 164932 kb
Host smart-d1e181e7-e9f1-45cf-ac5d-7be2d9bac44c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2310746610 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.2310746610
Directory /workspace/28.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.1155137895
Short name T7
Test name
Test status
Simulation time 1432270000 ps
CPU time 4.76 seconds
Started Jul 21 05:01:49 PM PDT 24
Finished Jul 21 05:02:00 PM PDT 24
Peak memory 164884 kb
Host smart-5645a2e1-10fd-4a08-8f44-63e625a711d8
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1155137895 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.1155137895
Directory /workspace/29.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.488670356
Short name T70
Test name
Test status
Simulation time 1459430000 ps
CPU time 5 seconds
Started Jul 21 05:01:38 PM PDT 24
Finished Jul 21 05:01:49 PM PDT 24
Peak memory 164772 kb
Host smart-91a4c092-284d-4fe2-acb1-48c4c1105abc
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=488670356 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.488670356
Directory /workspace/3.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.318419134
Short name T8
Test name
Test status
Simulation time 1451090000 ps
CPU time 4.76 seconds
Started Jul 21 05:01:48 PM PDT 24
Finished Jul 21 05:01:59 PM PDT 24
Peak memory 164840 kb
Host smart-e3bc312b-c491-486b-8541-efa7eba09a85
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=318419134 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.318419134
Directory /workspace/30.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.1248266855
Short name T49
Test name
Test status
Simulation time 1328310000 ps
CPU time 5.01 seconds
Started Jul 21 05:01:49 PM PDT 24
Finished Jul 21 05:02:00 PM PDT 24
Peak memory 164796 kb
Host smart-64021554-b1f2-4593-86c8-88c5e2a2d96a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1248266855 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.1248266855
Directory /workspace/31.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.1413211986
Short name T10
Test name
Test status
Simulation time 1452650000 ps
CPU time 4.39 seconds
Started Jul 21 05:01:49 PM PDT 24
Finished Jul 21 05:02:00 PM PDT 24
Peak memory 164920 kb
Host smart-5bd3517a-e74e-40f2-b167-80e01827c572
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1413211986 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.1413211986
Directory /workspace/32.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.1138947861
Short name T1
Test name
Test status
Simulation time 1499510000 ps
CPU time 3.95 seconds
Started Jul 21 05:01:50 PM PDT 24
Finished Jul 21 05:01:59 PM PDT 24
Peak memory 164820 kb
Host smart-3b245dac-4fc6-4f5c-88e1-3c2e259c5201
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1138947861 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.1138947861
Directory /workspace/33.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.3942155719
Short name T65
Test name
Test status
Simulation time 1383530000 ps
CPU time 3.1 seconds
Started Jul 21 05:01:50 PM PDT 24
Finished Jul 21 05:01:57 PM PDT 24
Peak memory 164920 kb
Host smart-a6d49b07-ed31-4fe0-b458-368ca7fa76cf
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3942155719 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.3942155719
Directory /workspace/34.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.3365233832
Short name T43
Test name
Test status
Simulation time 1474370000 ps
CPU time 4.42 seconds
Started Jul 21 05:01:49 PM PDT 24
Finished Jul 21 05:01:59 PM PDT 24
Peak memory 164872 kb
Host smart-6862dc03-7cbe-4645-b723-631cec0375c4
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3365233832 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.3365233832
Directory /workspace/35.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.3474272006
Short name T2
Test name
Test status
Simulation time 1605230000 ps
CPU time 4.2 seconds
Started Jul 21 05:01:49 PM PDT 24
Finished Jul 21 05:01:59 PM PDT 24
Peak memory 164844 kb
Host smart-5f80ac4b-b880-40b4-9b8a-7a0a26bd33d8
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3474272006 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.3474272006
Directory /workspace/36.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.3635457037
Short name T36
Test name
Test status
Simulation time 1565770000 ps
CPU time 5.31 seconds
Started Jul 21 05:01:49 PM PDT 24
Finished Jul 21 05:02:01 PM PDT 24
Peak memory 164816 kb
Host smart-5da7d045-9f4e-4912-9f65-3386a0af72f0
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3635457037 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.3635457037
Directory /workspace/37.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.4277934321
Short name T37
Test name
Test status
Simulation time 1418230000 ps
CPU time 5.61 seconds
Started Jul 21 05:01:50 PM PDT 24
Finished Jul 21 05:02:02 PM PDT 24
Peak memory 164828 kb
Host smart-fd86e8f9-2103-483b-96e0-95a7c881c7bb
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4277934321 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.4277934321
Directory /workspace/38.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.2412894227
Short name T38
Test name
Test status
Simulation time 1420730000 ps
CPU time 3.19 seconds
Started Jul 21 05:01:53 PM PDT 24
Finished Jul 21 05:02:00 PM PDT 24
Peak memory 164820 kb
Host smart-a3700b38-4920-438b-83f0-c0e710a1ebf5
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2412894227 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.2412894227
Directory /workspace/39.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.735362944
Short name T39
Test name
Test status
Simulation time 1356370000 ps
CPU time 3.29 seconds
Started Jul 21 05:01:37 PM PDT 24
Finished Jul 21 05:01:45 PM PDT 24
Peak memory 164848 kb
Host smart-32cfa9fc-b328-4846-92c2-9be379d4b613
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=735362944 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.735362944
Directory /workspace/4.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.2783052829
Short name T68
Test name
Test status
Simulation time 1456370000 ps
CPU time 6.14 seconds
Started Jul 21 05:01:55 PM PDT 24
Finished Jul 21 05:02:08 PM PDT 24
Peak memory 164836 kb
Host smart-6eb18db6-c42c-45e6-8a9d-2e60a0bde0a6
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2783052829 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.2783052829
Directory /workspace/40.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.375575749
Short name T51
Test name
Test status
Simulation time 1478090000 ps
CPU time 5.45 seconds
Started Jul 21 05:01:55 PM PDT 24
Finished Jul 21 05:02:08 PM PDT 24
Peak memory 164820 kb
Host smart-3a93f20d-64af-4a45-a717-9c3be3217d04
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=375575749 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.375575749
Directory /workspace/41.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.3190085174
Short name T35
Test name
Test status
Simulation time 1511390000 ps
CPU time 4.58 seconds
Started Jul 21 05:01:54 PM PDT 24
Finished Jul 21 05:02:05 PM PDT 24
Peak memory 164932 kb
Host smart-9c308a98-7c41-40c2-82f0-d687e296a49f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3190085174 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.3190085174
Directory /workspace/42.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.3604779457
Short name T13
Test name
Test status
Simulation time 1227850000 ps
CPU time 3.87 seconds
Started Jul 21 05:01:59 PM PDT 24
Finished Jul 21 05:02:08 PM PDT 24
Peak memory 164848 kb
Host smart-6e333dfa-805f-4f88-adfc-500ee58a6894
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3604779457 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.3604779457
Directory /workspace/43.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.3386613428
Short name T34
Test name
Test status
Simulation time 1600730000 ps
CPU time 4.85 seconds
Started Jul 21 05:01:55 PM PDT 24
Finished Jul 21 05:02:06 PM PDT 24
Peak memory 164864 kb
Host smart-d3d85463-541f-4125-a595-706faf2ebd0b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3386613428 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.3386613428
Directory /workspace/44.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.3496578507
Short name T3
Test name
Test status
Simulation time 1406770000 ps
CPU time 5.17 seconds
Started Jul 21 05:01:55 PM PDT 24
Finished Jul 21 05:02:07 PM PDT 24
Peak memory 164876 kb
Host smart-30f71549-7cd1-4b89-915a-3eb826984805
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3496578507 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.3496578507
Directory /workspace/45.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.2723501448
Short name T48
Test name
Test status
Simulation time 1481510000 ps
CPU time 6.45 seconds
Started Jul 21 05:01:56 PM PDT 24
Finished Jul 21 05:02:10 PM PDT 24
Peak memory 164968 kb
Host smart-49943b8f-6873-4a07-bb92-2cb442cd54dd
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2723501448 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.2723501448
Directory /workspace/46.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.3633008633
Short name T66
Test name
Test status
Simulation time 1458190000 ps
CPU time 4.77 seconds
Started Jul 21 05:01:56 PM PDT 24
Finished Jul 21 05:02:07 PM PDT 24
Peak memory 164880 kb
Host smart-e8c06847-ce40-45f0-8eed-fa72a2e431ce
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3633008633 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.3633008633
Directory /workspace/47.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.2067322164
Short name T50
Test name
Test status
Simulation time 1501430000 ps
CPU time 4.76 seconds
Started Jul 21 05:01:56 PM PDT 24
Finished Jul 21 05:02:07 PM PDT 24
Peak memory 164856 kb
Host smart-38f2e1c4-0c5d-49df-80a5-bcb262283bac
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2067322164 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.2067322164
Directory /workspace/48.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.2517084475
Short name T54
Test name
Test status
Simulation time 1433970000 ps
CPU time 4.32 seconds
Started Jul 21 05:01:54 PM PDT 24
Finished Jul 21 05:02:04 PM PDT 24
Peak memory 164864 kb
Host smart-17b039af-90cd-40ed-8218-02f7e0fbf81c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2517084475 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.2517084475
Directory /workspace/49.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.2767920758
Short name T55
Test name
Test status
Simulation time 1256990000 ps
CPU time 4.5 seconds
Started Jul 21 05:01:39 PM PDT 24
Finished Jul 21 05:01:50 PM PDT 24
Peak memory 164892 kb
Host smart-fab8b2dd-f10e-4503-97ca-09ef6939cff0
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2767920758 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.2767920758
Directory /workspace/5.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.1941841558
Short name T40
Test name
Test status
Simulation time 1565350000 ps
CPU time 5.3 seconds
Started Jul 21 05:01:37 PM PDT 24
Finished Jul 21 05:01:49 PM PDT 24
Peak memory 164828 kb
Host smart-ab528a8b-ff38-456a-bac8-24d7fc67a683
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1941841558 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.1941841558
Directory /workspace/6.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.3028508166
Short name T46
Test name
Test status
Simulation time 1371990000 ps
CPU time 3.8 seconds
Started Jul 21 05:01:37 PM PDT 24
Finished Jul 21 05:01:46 PM PDT 24
Peak memory 164840 kb
Host smart-153f7fcb-0caf-4fae-b83d-0b6d7969e261
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3028508166 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.3028508166
Directory /workspace/7.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.3328837047
Short name T58
Test name
Test status
Simulation time 1444310000 ps
CPU time 5.96 seconds
Started Jul 21 05:01:37 PM PDT 24
Finished Jul 21 05:01:50 PM PDT 24
Peak memory 164884 kb
Host smart-f9f6deb0-6755-464b-92f5-b1e4887ca34f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3328837047 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.3328837047
Directory /workspace/8.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.3046433661
Short name T69
Test name
Test status
Simulation time 1524210000 ps
CPU time 4.55 seconds
Started Jul 21 05:01:39 PM PDT 24
Finished Jul 21 05:01:49 PM PDT 24
Peak memory 164892 kb
Host smart-e0231bbb-c785-4945-913b-98b476df4774
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3046433661 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.3046433661
Directory /workspace/9.prim_lfsr_gal_smoke/latest
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