Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.31 100.00 96.55 100.00 100.00 95.00


Total tests in report: 200
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
87.31 87.31 100.00 100.00 96.55 96.55 100.00 100.00 100.00 100.00 40.00 40.00 /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.1525528488
96.81 9.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 87.50 47.50 /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.3471581650
98.31 1.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 95.00 7.50 /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.2816519825

Tests that do not contribute to grading

Name
/workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.4879280
/workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.1720355867
/workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.3267611151
/workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.1810000388
/workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.2840589829
/workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.2372868012
/workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.550731585
/workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.1092422548
/workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.406095412
/workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.799170898
/workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.25063680
/workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.1565490708
/workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.921094860
/workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.3494083438
/workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.2839064781
/workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.1243497270
/workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.2685044260
/workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.4039543391
/workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.386596636
/workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.1031595984
/workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.4205465133
/workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.198236472
/workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.1787671160
/workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.635343494
/workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.1762375034
/workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.1582238661
/workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.1871079204
/workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.82384685
/workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.924822254
/workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.433942048
/workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.3341046115
/workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.3852120894
/workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.516138565
/workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.1621081700
/workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.3649049587
/workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.3431694508
/workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.1945146040
/workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.3021820105
/workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.1448437288
/workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.1346199686
/workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.383936397
/workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.867395543
/workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.1641714609
/workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.3493685783
/workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.4047940322
/workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.1793253794
/workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.3800959042
/workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.2613235509
/workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.1106059619
/workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.1381319673
/workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.1907205473
/workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.1612788267
/workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.110579131
/workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.977863834
/workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.2835226614
/workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.1442461590
/workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.511966296
/workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.1350685585
/workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.1458441336
/workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.3956922108
/workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.3023308306
/workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.249967532
/workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.2771234783
/workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.3945786609
/workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.3134829618
/workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.3560536079
/workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.630767379
/workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.435461922
/workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.737286257
/workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.2529058343
/workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.1743538175
/workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.718908225
/workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.3345988412
/workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.3622687585
/workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.2993975164
/workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.272935676
/workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.3823329673
/workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.3764903508
/workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.4288011010
/workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.2893763370
/workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.4114613701
/workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.695499224
/workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.1737524945
/workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.671314216
/workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.2664094398
/workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.3212533248
/workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.3126891107
/workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.1561039853
/workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.4040281038
/workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.302996549
/workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.2559892885
/workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.3267603863
/workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.2794667400
/workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.1303199165
/workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.118097089
/workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.631165212
/workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.1971646599
/workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.1704337694
/workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.3352909747
/workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.996719600
/workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.3689135890
/workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.3041369743
/workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.3854698811
/workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.1461972963
/workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.1957919782
/workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.3082256225
/workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.2803343307
/workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.3176076528
/workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.609408891
/workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.3527616268
/workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.3687689744
/workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.790365404
/workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3464059283
/workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.19881716
/workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.312415097
/workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.3907080348
/workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.984298656
/workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2283282327
/workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.3163941510
/workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.1797271034
/workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.3491605420
/workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.2226305146
/workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.170734887
/workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.1089274941
/workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.3696485916
/workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.2614477120
/workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.526752181
/workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.2194950333
/workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.1675465063
/workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.4262642339
/workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.2185459109
/workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.1119585955
/workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.2124629861
/workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.3775492882
/workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.1117301247
/workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.2217017770
/workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1710278243
/workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.806812498
/workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.1639331396
/workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.3536598313
/workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.3709761837
/workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.1364168168
/workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.3000266183
/workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.2674644806
/workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.2686357580
/workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.3981385225
/workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1011727970
/workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.3391448663
/workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.837001472
/workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.347289786
/workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.3808310
/workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.2341052974
/workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.1518244233
/workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.787878121
/workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.2349063245
/workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.2200882902
/workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.2349391882
/workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.1960255040
/workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.2851127053
/workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.149083519
/workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.1345563198
/workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.680411137
/workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.3501428850
/workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.2840430322
/workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.2730540460
/workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.3273879714
/workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.3025381766
/workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.2061368495
/workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.39470856
/workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.3339402853
/workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.2043125051
/workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.855660640
/workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.2082249683
/workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.1166232885
/workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.800726849
/workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.3467237847
/workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.1281326448
/workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.1963116772
/workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.4279410313
/workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.214279601
/workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.362026119
/workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.1257800350
/workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.3622042931
/workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.3362276842
/workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.1012074747
/workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.1136907513
/workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.90767057
/workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.3163428672
/workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.1431204510
/workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.3682834117
/workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.1740820416
/workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.2269902645
/workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.2832233753
/workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.3175529378
/workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.2891451277
/workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.2996907932
/workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.1749643793



Total test records in report: 200
tests.html | tests1.html | tests2.html | tests3.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.362026119 Jul 22 04:57:02 PM PDT 24 Jul 22 04:57:09 PM PDT 24 1514290000 ps
T2 /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.4279410313 Jul 22 04:57:00 PM PDT 24 Jul 22 04:57:12 PM PDT 24 1523990000 ps
T3 /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.1525528488 Jul 22 04:56:53 PM PDT 24 Jul 22 04:57:05 PM PDT 24 1471230000 ps
T7 /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.2349391882 Jul 22 04:56:59 PM PDT 24 Jul 22 04:57:08 PM PDT 24 1391950000 ps
T8 /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.3467237847 Jul 22 04:56:56 PM PDT 24 Jul 22 04:57:07 PM PDT 24 1544050000 ps
T9 /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.3175529378 Jul 22 04:56:59 PM PDT 24 Jul 22 04:57:08 PM PDT 24 1489550000 ps
T10 /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.3362276842 Jul 22 04:57:02 PM PDT 24 Jul 22 04:57:12 PM PDT 24 1377830000 ps
T11 /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.2200882902 Jul 22 04:56:59 PM PDT 24 Jul 22 04:57:08 PM PDT 24 1428970000 ps
T12 /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.1345563198 Jul 22 04:56:52 PM PDT 24 Jul 22 04:57:00 PM PDT 24 1429250000 ps
T13 /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.800726849 Jul 22 04:56:52 PM PDT 24 Jul 22 04:57:03 PM PDT 24 1578170000 ps
T31 /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.3682834117 Jul 22 04:57:10 PM PDT 24 Jul 22 04:57:19 PM PDT 24 1545050000 ps
T32 /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.214279601 Jul 22 04:57:05 PM PDT 24 Jul 22 04:57:15 PM PDT 24 1563290000 ps
T33 /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.3273879714 Jul 22 04:56:59 PM PDT 24 Jul 22 04:57:08 PM PDT 24 1520470000 ps
T34 /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.2851127053 Jul 22 04:56:57 PM PDT 24 Jul 22 04:57:08 PM PDT 24 1436010000 ps
T35 /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.1166232885 Jul 22 04:56:54 PM PDT 24 Jul 22 04:57:06 PM PDT 24 1560090000 ps
T36 /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.1431204510 Jul 22 04:57:01 PM PDT 24 Jul 22 04:57:11 PM PDT 24 1397530000 ps
T37 /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.2269902645 Jul 22 04:57:03 PM PDT 24 Jul 22 04:57:11 PM PDT 24 1350390000 ps
T38 /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.2341052974 Jul 22 04:56:59 PM PDT 24 Jul 22 04:57:09 PM PDT 24 1625850000 ps
T39 /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.1136907513 Jul 22 04:57:02 PM PDT 24 Jul 22 04:57:11 PM PDT 24 1429050000 ps
T40 /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.2043125051 Jul 22 04:56:55 PM PDT 24 Jul 22 04:57:04 PM PDT 24 1497770000 ps
T41 /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.3025381766 Jul 22 04:56:52 PM PDT 24 Jul 22 04:57:02 PM PDT 24 1521250000 ps
T42 /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.1518244233 Jul 22 04:56:53 PM PDT 24 Jul 22 04:57:02 PM PDT 24 1429990000 ps
T43 /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.2832233753 Jul 22 04:56:51 PM PDT 24 Jul 22 04:56:59 PM PDT 24 1086590000 ps
T44 /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.2730540460 Jul 22 04:56:56 PM PDT 24 Jul 22 04:57:07 PM PDT 24 1450790000 ps
T45 /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.2349063245 Jul 22 04:56:54 PM PDT 24 Jul 22 04:57:04 PM PDT 24 1298210000 ps
T46 /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.787878121 Jul 22 04:56:54 PM PDT 24 Jul 22 04:57:06 PM PDT 24 1540850000 ps
T47 /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.39470856 Jul 22 04:56:51 PM PDT 24 Jul 22 04:57:01 PM PDT 24 1451330000 ps
T48 /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.1281326448 Jul 22 04:57:02 PM PDT 24 Jul 22 04:57:10 PM PDT 24 1184750000 ps
T49 /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.3501428850 Jul 22 04:56:53 PM PDT 24 Jul 22 04:57:07 PM PDT 24 1559970000 ps
T50 /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.2891451277 Jul 22 04:56:54 PM PDT 24 Jul 22 04:57:06 PM PDT 24 1520850000 ps
T51 /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.347289786 Jul 22 04:56:56 PM PDT 24 Jul 22 04:57:08 PM PDT 24 1506170000 ps
T52 /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.1740820416 Jul 22 04:57:11 PM PDT 24 Jul 22 04:57:18 PM PDT 24 1395830000 ps
T53 /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.1749643793 Jul 22 04:56:55 PM PDT 24 Jul 22 04:57:06 PM PDT 24 1374630000 ps
T54 /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.1257800350 Jul 22 04:56:51 PM PDT 24 Jul 22 04:57:02 PM PDT 24 1241810000 ps
T55 /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.90767057 Jul 22 04:57:02 PM PDT 24 Jul 22 04:57:13 PM PDT 24 1581750000 ps
T56 /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.1012074747 Jul 22 04:57:03 PM PDT 24 Jul 22 04:57:14 PM PDT 24 1467750000 ps
T57 /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.3622042931 Jul 22 04:57:03 PM PDT 24 Jul 22 04:57:13 PM PDT 24 1623610000 ps
T58 /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.3163428672 Jul 22 04:57:01 PM PDT 24 Jul 22 04:57:10 PM PDT 24 1471950000 ps
T59 /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.855660640 Jul 22 04:56:59 PM PDT 24 Jul 22 04:57:08 PM PDT 24 1352390000 ps
T60 /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.1960255040 Jul 22 04:56:52 PM PDT 24 Jul 22 04:57:01 PM PDT 24 1394450000 ps
T61 /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.837001472 Jul 22 04:59:35 PM PDT 24 Jul 22 04:59:43 PM PDT 24 1519770000 ps
T62 /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.2996907932 Jul 22 04:56:52 PM PDT 24 Jul 22 04:57:03 PM PDT 24 1477050000 ps
T63 /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.2082249683 Jul 22 04:56:53 PM PDT 24 Jul 22 04:57:02 PM PDT 24 1395230000 ps
T64 /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.3339402853 Jul 22 04:56:54 PM PDT 24 Jul 22 04:57:04 PM PDT 24 1294370000 ps
T65 /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.3808310 Jul 22 04:56:54 PM PDT 24 Jul 22 04:57:03 PM PDT 24 1355750000 ps
T66 /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.2840430322 Jul 22 04:56:55 PM PDT 24 Jul 22 04:57:06 PM PDT 24 1379070000 ps
T67 /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.680411137 Jul 22 04:56:54 PM PDT 24 Jul 22 04:57:02 PM PDT 24 1317730000 ps
T68 /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.2061368495 Jul 22 04:56:52 PM PDT 24 Jul 22 04:57:04 PM PDT 24 1547430000 ps
T69 /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.1963116772 Jul 22 04:57:05 PM PDT 24 Jul 22 04:57:13 PM PDT 24 1481630000 ps
T70 /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.149083519 Jul 22 04:56:53 PM PDT 24 Jul 22 04:57:07 PM PDT 24 1529570000 ps
T4 /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.516138565 Jul 22 04:21:28 PM PDT 24 Jul 22 04:54:31 PM PDT 24 336819210000 ps
T5 /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.2685044260 Jul 22 04:24:40 PM PDT 24 Jul 22 05:03:17 PM PDT 24 336964970000 ps
T6 /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.25063680 Jul 22 04:26:44 PM PDT 24 Jul 22 05:01:42 PM PDT 24 336845390000 ps
T14 /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.433942048 Jul 22 04:23:02 PM PDT 24 Jul 22 04:54:28 PM PDT 24 337008970000 ps
T15 /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.4205465133 Jul 22 04:25:26 PM PDT 24 Jul 22 04:54:23 PM PDT 24 336770490000 ps
T16 /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.383936397 Jul 22 04:25:44 PM PDT 24 Jul 22 04:55:01 PM PDT 24 336781770000 ps
T17 /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.3341046115 Jul 22 04:22:11 PM PDT 24 Jul 22 04:53:24 PM PDT 24 336939830000 ps
T18 /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.1762375034 Jul 22 04:25:10 PM PDT 24 Jul 22 04:54:39 PM PDT 24 336991790000 ps
T19 /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.3471581650 Jul 22 04:20:33 PM PDT 24 Jul 22 04:46:46 PM PDT 24 336632090000 ps
T20 /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.1787671160 Jul 22 04:20:47 PM PDT 24 Jul 22 04:48:44 PM PDT 24 336449570000 ps
T71 /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.1582238661 Jul 22 04:21:52 PM PDT 24 Jul 22 04:59:45 PM PDT 24 337018430000 ps
T72 /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.198236472 Jul 22 04:25:26 PM PDT 24 Jul 22 04:53:10 PM PDT 24 336466730000 ps
T73 /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.4039543391 Jul 22 04:26:04 PM PDT 24 Jul 22 04:52:29 PM PDT 24 336515890000 ps
T74 /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.3431694508 Jul 22 04:21:58 PM PDT 24 Jul 22 04:51:43 PM PDT 24 336379730000 ps
T75 /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.406095412 Jul 22 04:26:44 PM PDT 24 Jul 22 05:01:18 PM PDT 24 336775690000 ps
T76 /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.1720355867 Jul 22 04:24:17 PM PDT 24 Jul 22 04:55:56 PM PDT 24 336388010000 ps
T77 /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.1565490708 Jul 22 04:20:37 PM PDT 24 Jul 22 05:02:50 PM PDT 24 336723590000 ps
T78 /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.4047940322 Jul 22 04:20:48 PM PDT 24 Jul 22 04:48:16 PM PDT 24 336471950000 ps
T79 /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.3494083438 Jul 22 04:26:26 PM PDT 24 Jul 22 04:55:26 PM PDT 24 337044650000 ps
T80 /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.2840589829 Jul 22 04:26:55 PM PDT 24 Jul 22 04:58:33 PM PDT 24 336725770000 ps
T81 /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.799170898 Jul 22 04:26:27 PM PDT 24 Jul 22 04:55:16 PM PDT 24 336636330000 ps
T82 /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.82384685 Jul 22 04:21:29 PM PDT 24 Jul 22 04:51:32 PM PDT 24 337007110000 ps
T83 /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.921094860 Jul 22 04:26:04 PM PDT 24 Jul 22 04:52:36 PM PDT 24 336774230000 ps
T84 /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.4879280 Jul 22 04:20:37 PM PDT 24 Jul 22 05:02:47 PM PDT 24 336889290000 ps
T85 /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.924822254 Jul 22 04:21:20 PM PDT 24 Jul 22 05:03:24 PM PDT 24 336747970000 ps
T86 /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.1945146040 Jul 22 04:25:29 PM PDT 24 Jul 22 04:54:19 PM PDT 24 336654030000 ps
T87 /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.1106059619 Jul 22 04:20:39 PM PDT 24 Jul 22 04:57:53 PM PDT 24 336567030000 ps
T88 /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.3649049587 Jul 22 04:21:58 PM PDT 24 Jul 22 04:51:31 PM PDT 24 336470430000 ps
T89 /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.867395543 Jul 22 04:26:41 PM PDT 24 Jul 22 04:59:52 PM PDT 24 336417230000 ps
T90 /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.386596636 Jul 22 04:26:29 PM PDT 24 Jul 22 04:58:19 PM PDT 24 336646190000 ps
T91 /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.3852120894 Jul 22 04:20:56 PM PDT 24 Jul 22 04:54:02 PM PDT 24 337053370000 ps
T92 /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.2372868012 Jul 22 04:26:42 PM PDT 24 Jul 22 04:55:44 PM PDT 24 336791970000 ps
T93 /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.635343494 Jul 22 04:24:59 PM PDT 24 Jul 22 04:57:32 PM PDT 24 336944010000 ps
T94 /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.550731585 Jul 22 04:24:19 PM PDT 24 Jul 22 04:51:00 PM PDT 24 336418050000 ps
T95 /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.2839064781 Jul 22 04:26:45 PM PDT 24 Jul 22 05:01:19 PM PDT 24 336926850000 ps
T96 /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.1031595984 Jul 22 04:26:57 PM PDT 24 Jul 22 04:58:21 PM PDT 24 336704790000 ps
T97 /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.1346199686 Jul 22 04:25:30 PM PDT 24 Jul 22 04:54:00 PM PDT 24 336858190000 ps
T98 /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.1243497270 Jul 22 04:26:04 PM PDT 24 Jul 22 04:52:16 PM PDT 24 336902990000 ps
T99 /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.3021820105 Jul 22 04:20:56 PM PDT 24 Jul 22 04:54:05 PM PDT 24 336681470000 ps
T100 /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.1448437288 Jul 22 04:25:29 PM PDT 24 Jul 22 04:54:19 PM PDT 24 336423430000 ps
T101 /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.1092422548 Jul 22 04:25:05 PM PDT 24 Jul 22 05:03:28 PM PDT 24 336908530000 ps
T102 /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.1641714609 Jul 22 04:23:31 PM PDT 24 Jul 22 04:53:18 PM PDT 24 336844630000 ps
T103 /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.1810000388 Jul 22 04:26:43 PM PDT 24 Jul 22 04:53:42 PM PDT 24 336773230000 ps
T104 /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.2613235509 Jul 22 04:20:41 PM PDT 24 Jul 22 04:57:50 PM PDT 24 336632210000 ps
T105 /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.3800959042 Jul 22 04:20:34 PM PDT 24 Jul 22 04:46:44 PM PDT 24 336645630000 ps
T106 /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.3267611151 Jul 22 04:26:41 PM PDT 24 Jul 22 04:55:33 PM PDT 24 336814350000 ps
T107 /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.1871079204 Jul 22 04:21:52 PM PDT 24 Jul 22 05:00:00 PM PDT 24 336656390000 ps
T108 /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.3493685783 Jul 22 04:26:16 PM PDT 24 Jul 22 04:58:02 PM PDT 24 336594250000 ps
T109 /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.1621081700 Jul 22 04:20:47 PM PDT 24 Jul 22 04:48:58 PM PDT 24 336711050000 ps
T110 /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.1793253794 Jul 22 04:20:42 PM PDT 24 Jul 22 04:45:50 PM PDT 24 336391170000 ps
T111 /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.3041369743 Jul 22 06:20:38 PM PDT 24 Jul 22 06:20:50 PM PDT 24 1531090000 ps
T112 /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.170734887 Jul 22 06:23:01 PM PDT 24 Jul 22 06:23:09 PM PDT 24 1488050000 ps
T113 /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.609408891 Jul 22 06:20:38 PM PDT 24 Jul 22 06:20:49 PM PDT 24 1303310000 ps
T114 /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.1119585955 Jul 22 06:20:44 PM PDT 24 Jul 22 06:20:55 PM PDT 24 1452870000 ps
T115 /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.4262642339 Jul 22 06:20:40 PM PDT 24 Jul 22 06:20:49 PM PDT 24 1338330000 ps
T116 /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.3536598313 Jul 22 06:20:39 PM PDT 24 Jul 22 06:20:49 PM PDT 24 1547610000 ps
T117 /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.3000266183 Jul 22 06:20:38 PM PDT 24 Jul 22 06:20:48 PM PDT 24 1503430000 ps
T118 /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.2674644806 Jul 22 06:20:35 PM PDT 24 Jul 22 06:20:47 PM PDT 24 1559430000 ps
T119 /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.2217017770 Jul 22 06:20:37 PM PDT 24 Jul 22 06:20:47 PM PDT 24 1431350000 ps
T120 /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1710278243 Jul 22 06:21:02 PM PDT 24 Jul 22 06:21:12 PM PDT 24 1577070000 ps
T121 /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.2614477120 Jul 22 06:20:38 PM PDT 24 Jul 22 06:20:48 PM PDT 24 1435990000 ps
T122 /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.3527616268 Jul 22 06:20:39 PM PDT 24 Jul 22 06:20:50 PM PDT 24 1349090000 ps
T123 /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.2226305146 Jul 22 06:21:04 PM PDT 24 Jul 22 06:21:12 PM PDT 24 1477830000 ps
T124 /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.1797271034 Jul 22 06:22:18 PM PDT 24 Jul 22 06:22:26 PM PDT 24 1283190000 ps
T125 /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3464059283 Jul 22 06:20:38 PM PDT 24 Jul 22 06:20:50 PM PDT 24 1572330000 ps
T126 /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.1675465063 Jul 22 06:22:27 PM PDT 24 Jul 22 06:22:36 PM PDT 24 1475170000 ps
T127 /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.526752181 Jul 22 06:20:39 PM PDT 24 Jul 22 06:20:47 PM PDT 24 1127950000 ps
T128 /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.3981385225 Jul 22 06:20:38 PM PDT 24 Jul 22 06:20:49 PM PDT 24 1554270000 ps
T129 /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.996719600 Jul 22 06:20:33 PM PDT 24 Jul 22 06:20:44 PM PDT 24 1534270000 ps
T130 /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.2124629861 Jul 22 06:20:32 PM PDT 24 Jul 22 06:20:42 PM PDT 24 1382430000 ps
T131 /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.2194950333 Jul 22 06:20:38 PM PDT 24 Jul 22 06:20:49 PM PDT 24 1352290000 ps
T132 /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1011727970 Jul 22 06:20:35 PM PDT 24 Jul 22 06:20:45 PM PDT 24 1290670000 ps
T133 /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.3775492882 Jul 22 06:20:38 PM PDT 24 Jul 22 06:20:47 PM PDT 24 1322230000 ps
T134 /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.3696485916 Jul 22 06:20:38 PM PDT 24 Jul 22 06:20:47 PM PDT 24 1455050000 ps
T135 /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.3176076528 Jul 22 06:20:38 PM PDT 24 Jul 22 06:20:50 PM PDT 24 1438650000 ps
T136 /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.1639331396 Jul 22 06:20:38 PM PDT 24 Jul 22 06:20:49 PM PDT 24 1479830000 ps
T137 /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2283282327 Jul 22 06:21:10 PM PDT 24 Jul 22 06:21:19 PM PDT 24 1536950000 ps
T138 /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.3689135890 Jul 22 06:20:35 PM PDT 24 Jul 22 06:20:46 PM PDT 24 1558610000 ps
T139 /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.1957919782 Jul 22 06:20:38 PM PDT 24 Jul 22 06:20:48 PM PDT 24 1286010000 ps
T140 /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.1117301247 Jul 22 06:20:38 PM PDT 24 Jul 22 06:20:49 PM PDT 24 1361610000 ps
T141 /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.3163941510 Jul 22 06:21:04 PM PDT 24 Jul 22 06:21:12 PM PDT 24 1589250000 ps
T142 /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.3854698811 Jul 22 06:22:12 PM PDT 24 Jul 22 06:22:21 PM PDT 24 1646010000 ps
T143 /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.1089274941 Jul 22 06:20:43 PM PDT 24 Jul 22 06:20:53 PM PDT 24 1352590000 ps
T144 /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.1364168168 Jul 22 06:20:39 PM PDT 24 Jul 22 06:20:49 PM PDT 24 1404950000 ps
T145 /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.3491605420 Jul 22 06:20:40 PM PDT 24 Jul 22 06:20:50 PM PDT 24 1322170000 ps
T146 /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.790365404 Jul 22 06:20:54 PM PDT 24 Jul 22 06:21:01 PM PDT 24 1317770000 ps
T147 /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.3709761837 Jul 22 06:20:37 PM PDT 24 Jul 22 06:20:45 PM PDT 24 1387430000 ps
T148 /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.3082256225 Jul 22 06:20:39 PM PDT 24 Jul 22 06:20:50 PM PDT 24 1512370000 ps
T149 /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.2803343307 Jul 22 06:20:38 PM PDT 24 Jul 22 06:20:49 PM PDT 24 1500470000 ps
T150 /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.19881716 Jul 22 06:20:38 PM PDT 24 Jul 22 06:20:49 PM PDT 24 1456770000 ps
T151 /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.2686357580 Jul 22 06:20:32 PM PDT 24 Jul 22 06:20:42 PM PDT 24 1390310000 ps
T152 /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.312415097 Jul 22 06:20:37 PM PDT 24 Jul 22 06:20:47 PM PDT 24 1514890000 ps
T153 /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.1461972963 Jul 22 06:20:38 PM PDT 24 Jul 22 06:20:50 PM PDT 24 1584870000 ps
T154 /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.3352909747 Jul 22 06:20:39 PM PDT 24 Jul 22 06:20:51 PM PDT 24 1577790000 ps
T155 /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.984298656 Jul 22 06:20:41 PM PDT 24 Jul 22 06:20:50 PM PDT 24 1422670000 ps
T156 /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.3907080348 Jul 22 06:20:37 PM PDT 24 Jul 22 06:20:47 PM PDT 24 1448710000 ps
T157 /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.3687689744 Jul 22 06:20:41 PM PDT 24 Jul 22 06:20:52 PM PDT 24 1466550000 ps
T158 /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.3391448663 Jul 22 06:20:38 PM PDT 24 Jul 22 06:20:49 PM PDT 24 1404590000 ps
T159 /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.806812498 Jul 22 06:20:42 PM PDT 24 Jul 22 06:20:51 PM PDT 24 1469930000 ps
T160 /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.2185459109 Jul 22 06:20:44 PM PDT 24 Jul 22 06:20:54 PM PDT 24 1544070000 ps
T21 /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.2993975164 Jul 22 06:20:50 PM PDT 24 Jul 22 06:53:48 PM PDT 24 336979390000 ps
T22 /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.2835226614 Jul 22 06:21:25 PM PDT 24 Jul 22 06:50:08 PM PDT 24 337001930000 ps
T23 /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.3560536079 Jul 22 06:22:24 PM PDT 24 Jul 22 06:48:23 PM PDT 24 336871070000 ps
T24 /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.4288011010 Jul 22 06:20:50 PM PDT 24 Jul 22 06:53:41 PM PDT 24 336552670000 ps
T25 /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.3345988412 Jul 22 06:21:26 PM PDT 24 Jul 22 06:52:02 PM PDT 24 336655150000 ps
T26 /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.1458441336 Jul 22 06:20:39 PM PDT 24 Jul 22 06:51:12 PM PDT 24 336671050000 ps
T27 /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.2816519825 Jul 22 06:20:41 PM PDT 24 Jul 22 06:51:28 PM PDT 24 337143370000 ps
T28 /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.4040281038 Jul 22 06:20:51 PM PDT 24 Jul 22 06:51:28 PM PDT 24 336916230000 ps
T29 /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.695499224 Jul 22 06:20:51 PM PDT 24 Jul 22 06:48:00 PM PDT 24 336645470000 ps
T30 /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.118097089 Jul 22 06:20:40 PM PDT 24 Jul 22 06:52:49 PM PDT 24 337062970000 ps
T161 /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.249967532 Jul 22 06:20:37 PM PDT 24 Jul 22 06:51:10 PM PDT 24 336837770000 ps
T162 /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.737286257 Jul 22 06:20:53 PM PDT 24 Jul 22 06:50:28 PM PDT 24 336572290000 ps
T163 /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.1737524945 Jul 22 06:21:09 PM PDT 24 Jul 22 06:44:25 PM PDT 24 337115690000 ps
T164 /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.631165212 Jul 22 06:20:39 PM PDT 24 Jul 22 06:52:50 PM PDT 24 336523150000 ps
T165 /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.3023308306 Jul 22 06:21:25 PM PDT 24 Jul 22 06:50:19 PM PDT 24 337037390000 ps
T166 /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.2771234783 Jul 22 06:20:50 PM PDT 24 Jul 22 06:51:16 PM PDT 24 336999930000 ps
T167 /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.1704337694 Jul 22 06:20:44 PM PDT 24 Jul 22 06:46:48 PM PDT 24 336370230000 ps
T168 /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.302996549 Jul 22 06:20:58 PM PDT 24 Jul 22 06:50:34 PM PDT 24 336452610000 ps
T169 /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.3823329673 Jul 22 06:20:50 PM PDT 24 Jul 22 06:50:20 PM PDT 24 336926170000 ps
T170 /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.2664094398 Jul 22 06:20:52 PM PDT 24 Jul 22 06:51:26 PM PDT 24 336950890000 ps
T171 /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.3622687585 Jul 22 06:20:53 PM PDT 24 Jul 22 06:59:04 PM PDT 24 336650810000 ps
T172 /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.1971646599 Jul 22 06:20:39 PM PDT 24 Jul 22 06:51:19 PM PDT 24 336438650000 ps
T173 /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.718908225 Jul 22 06:20:39 PM PDT 24 Jul 22 06:51:00 PM PDT 24 336905450000 ps
T174 /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.630767379 Jul 22 06:20:53 PM PDT 24 Jul 22 06:58:58 PM PDT 24 336722710000 ps
T175 /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.3945786609 Jul 22 06:20:46 PM PDT 24 Jul 22 06:49:54 PM PDT 24 336356150000 ps
T176 /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.1907205473 Jul 22 06:20:39 PM PDT 24 Jul 22 06:51:18 PM PDT 24 336727370000 ps
T177 /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.1612788267 Jul 22 06:20:38 PM PDT 24 Jul 22 06:53:51 PM PDT 24 336742770000 ps
T178 /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.3267603863 Jul 22 06:20:50 PM PDT 24 Jul 22 06:51:17 PM PDT 24 337080030000 ps
T179 /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.1743538175 Jul 22 06:20:49 PM PDT 24 Jul 22 06:51:28 PM PDT 24 336393470000 ps
T180 /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.110579131 Jul 22 06:20:39 PM PDT 24 Jul 22 06:52:52 PM PDT 24 336473090000 ps
T181 /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.3764903508 Jul 22 06:20:47 PM PDT 24 Jul 22 06:51:14 PM PDT 24 336884190000 ps
T182 /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.511966296 Jul 22 06:20:39 PM PDT 24 Jul 22 06:51:14 PM PDT 24 336952110000 ps
T183 /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.1442461590 Jul 22 06:20:41 PM PDT 24 Jul 22 06:51:45 PM PDT 24 336338810000 ps
T184 /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.3956922108 Jul 22 06:21:16 PM PDT 24 Jul 22 06:55:08 PM PDT 24 336496370000 ps
T185 /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.3134829618 Jul 22 06:20:53 PM PDT 24 Jul 22 06:59:04 PM PDT 24 336620010000 ps
T186 /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.1561039853 Jul 22 06:21:16 PM PDT 24 Jul 22 06:55:06 PM PDT 24 336752050000 ps
T187 /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.1381319673 Jul 22 06:20:40 PM PDT 24 Jul 22 06:52:59 PM PDT 24 336548030000 ps
T188 /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.4114613701 Jul 22 06:21:13 PM PDT 24 Jul 22 06:54:30 PM PDT 24 337019230000 ps
T189 /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.1303199165 Jul 22 06:20:43 PM PDT 24 Jul 22 06:47:03 PM PDT 24 337085990000 ps
T190 /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.671314216 Jul 22 06:20:55 PM PDT 24 Jul 22 06:53:14 PM PDT 24 336463730000 ps
T191 /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.3126891107 Jul 22 06:20:51 PM PDT 24 Jul 22 06:50:08 PM PDT 24 336491910000 ps
T192 /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.272935676 Jul 22 06:21:18 PM PDT 24 Jul 22 06:55:14 PM PDT 24 336885070000 ps
T193 /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.2529058343 Jul 22 06:20:52 PM PDT 24 Jul 22 06:49:57 PM PDT 24 336703950000 ps
T194 /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.977863834 Jul 22 06:20:39 PM PDT 24 Jul 22 06:50:50 PM PDT 24 336399970000 ps
T195 /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.435461922 Jul 22 06:20:49 PM PDT 24 Jul 22 06:51:30 PM PDT 24 336862310000 ps
T196 /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.2794667400 Jul 22 06:20:49 PM PDT 24 Jul 22 06:50:52 PM PDT 24 336464230000 ps
T197 /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.1350685585 Jul 22 06:20:41 PM PDT 24 Jul 22 06:52:17 PM PDT 24 336460310000 ps
T198 /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.3212533248 Jul 22 06:20:49 PM PDT 24 Jul 22 06:50:56 PM PDT 24 336596030000 ps
T199 /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.2893763370 Jul 22 06:20:49 PM PDT 24 Jul 22 06:52:56 PM PDT 24 336399970000 ps
T200 /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.2559892885 Jul 22 06:20:47 PM PDT 24 Jul 22 06:53:42 PM PDT 24 336578890000 ps

Test location /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.1525528488
Short name T3
Test name
Test status
Simulation time 1471230000 ps
CPU time 4.84 seconds
Started Jul 22 04:56:53 PM PDT 24
Finished Jul 22 04:57:05 PM PDT 24
Peak memory 164876 kb
Host smart-0a472a9d-1b5f-4598-bda1-e74663cbeb86
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1525528488 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.1525528488
Directory /workspace/10.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.3471581650
Short name T19
Test name
Test status
Simulation time 336632090000 ps
CPU time 630.97 seconds
Started Jul 22 04:20:33 PM PDT 24
Finished Jul 22 04:46:46 PM PDT 24
Peak memory 160868 kb
Host smart-a8162ef0-7d6a-4d57-93be-24ad671918f5
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3471581650 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.3471581650
Directory /workspace/0.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.2816519825
Short name T27
Test name
Test status
Simulation time 337143370000 ps
CPU time 745.64 seconds
Started Jul 22 06:20:41 PM PDT 24
Finished Jul 22 06:51:28 PM PDT 24
Peak memory 160676 kb
Host smart-d914e635-c13a-491f-b19c-d27daedc0422
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2816519825 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.2816519825
Directory /workspace/10.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.4879280
Short name T84
Test name
Test status
Simulation time 336889290000 ps
CPU time 1006.78 seconds
Started Jul 22 04:20:37 PM PDT 24
Finished Jul 22 05:02:47 PM PDT 24
Peak memory 159628 kb
Host smart-bdd3501d-6469-4cab-91ed-a4fbb7fe50bc
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4879280 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.4879280
Directory /workspace/1.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.1720355867
Short name T76
Test name
Test status
Simulation time 336388010000 ps
CPU time 782.85 seconds
Started Jul 22 04:24:17 PM PDT 24
Finished Jul 22 04:55:56 PM PDT 24
Peak memory 160580 kb
Host smart-9716b92f-de8b-4a64-ab34-4ac495447d0a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1720355867 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.1720355867
Directory /workspace/10.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.3267611151
Short name T106
Test name
Test status
Simulation time 336814350000 ps
CPU time 685.32 seconds
Started Jul 22 04:26:41 PM PDT 24
Finished Jul 22 04:55:33 PM PDT 24
Peak memory 159568 kb
Host smart-cea9a760-2128-4d42-b499-c037d20078c5
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3267611151 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.3267611151
Directory /workspace/11.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.1810000388
Short name T103
Test name
Test status
Simulation time 336773230000 ps
CPU time 662.01 seconds
Started Jul 22 04:26:43 PM PDT 24
Finished Jul 22 04:53:42 PM PDT 24
Peak memory 160420 kb
Host smart-60ee7b05-5e01-4f35-bd4d-1c129d7db099
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1810000388 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.1810000388
Directory /workspace/12.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.2840589829
Short name T80
Test name
Test status
Simulation time 336725770000 ps
CPU time 774.77 seconds
Started Jul 22 04:26:55 PM PDT 24
Finished Jul 22 04:58:33 PM PDT 24
Peak memory 160364 kb
Host smart-fd92b773-57bb-4bcd-a4e0-d3f689955e79
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2840589829 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.2840589829
Directory /workspace/13.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.2372868012
Short name T92
Test name
Test status
Simulation time 336791970000 ps
CPU time 686.41 seconds
Started Jul 22 04:26:42 PM PDT 24
Finished Jul 22 04:55:44 PM PDT 24
Peak memory 160200 kb
Host smart-3632179e-e579-4866-8581-fbe68b4a05d0
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2372868012 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.2372868012
Directory /workspace/14.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.550731585
Short name T94
Test name
Test status
Simulation time 336418050000 ps
CPU time 648.16 seconds
Started Jul 22 04:24:19 PM PDT 24
Finished Jul 22 04:51:00 PM PDT 24
Peak memory 160644 kb
Host smart-b49a19c5-e2d1-447f-8452-103012747d98
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=550731585 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.550731585
Directory /workspace/15.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.1092422548
Short name T101
Test name
Test status
Simulation time 336908530000 ps
CPU time 943.97 seconds
Started Jul 22 04:25:05 PM PDT 24
Finished Jul 22 05:03:28 PM PDT 24
Peak memory 160616 kb
Host smart-7a780a91-9f62-4406-9e47-9ecf49ead0cc
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1092422548 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.1092422548
Directory /workspace/16.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.406095412
Short name T75
Test name
Test status
Simulation time 336775690000 ps
CPU time 837.98 seconds
Started Jul 22 04:26:44 PM PDT 24
Finished Jul 22 05:01:18 PM PDT 24
Peak memory 160616 kb
Host smart-8ea60484-0d2a-4ea4-90f3-c327afa4c0f9
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=406095412 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.406095412
Directory /workspace/17.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.799170898
Short name T81
Test name
Test status
Simulation time 336636330000 ps
CPU time 701.07 seconds
Started Jul 22 04:26:27 PM PDT 24
Finished Jul 22 04:55:16 PM PDT 24
Peak memory 160332 kb
Host smart-f4eb9d6e-d31a-494b-bf65-c3514f34347d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=799170898 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.799170898
Directory /workspace/18.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.25063680
Short name T6
Test name
Test status
Simulation time 336845390000 ps
CPU time 853.83 seconds
Started Jul 22 04:26:44 PM PDT 24
Finished Jul 22 05:01:42 PM PDT 24
Peak memory 160612 kb
Host smart-046a4b06-4c2b-4847-9e7d-2a921fb031bc
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=25063680 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.25063680
Directory /workspace/19.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.1565490708
Short name T77
Test name
Test status
Simulation time 336723590000 ps
CPU time 1014.41 seconds
Started Jul 22 04:20:37 PM PDT 24
Finished Jul 22 05:02:50 PM PDT 24
Peak memory 159556 kb
Host smart-394a12a8-d6f5-4388-b184-103484df60dc
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1565490708 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.1565490708
Directory /workspace/2.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.921094860
Short name T83
Test name
Test status
Simulation time 336774230000 ps
CPU time 639.97 seconds
Started Jul 22 04:26:04 PM PDT 24
Finished Jul 22 04:52:36 PM PDT 24
Peak memory 160440 kb
Host smart-d258bd3e-86e4-48e4-b66b-2b95b2fa95d7
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=921094860 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.921094860
Directory /workspace/20.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.3494083438
Short name T79
Test name
Test status
Simulation time 337044650000 ps
CPU time 711.27 seconds
Started Jul 22 04:26:26 PM PDT 24
Finished Jul 22 04:55:26 PM PDT 24
Peak memory 160316 kb
Host smart-6ae5b688-b45b-4b8d-a7e0-b54414505442
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3494083438 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.3494083438
Directory /workspace/21.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.2839064781
Short name T95
Test name
Test status
Simulation time 336926850000 ps
CPU time 842.21 seconds
Started Jul 22 04:26:45 PM PDT 24
Finished Jul 22 05:01:19 PM PDT 24
Peak memory 160624 kb
Host smart-d548b685-033f-415f-a42d-fc6bc6a53396
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2839064781 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.2839064781
Directory /workspace/22.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.1243497270
Short name T98
Test name
Test status
Simulation time 336902990000 ps
CPU time 628.46 seconds
Started Jul 22 04:26:04 PM PDT 24
Finished Jul 22 04:52:16 PM PDT 24
Peak memory 160440 kb
Host smart-8b007f97-817b-4069-ae9a-d4b173dee582
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1243497270 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.1243497270
Directory /workspace/23.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.2685044260
Short name T5
Test name
Test status
Simulation time 336964970000 ps
CPU time 959.34 seconds
Started Jul 22 04:24:40 PM PDT 24
Finished Jul 22 05:03:17 PM PDT 24
Peak memory 160616 kb
Host smart-16953006-6af5-41ab-8ca7-f34b58f727b1
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2685044260 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.2685044260
Directory /workspace/24.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.4039543391
Short name T73
Test name
Test status
Simulation time 336515890000 ps
CPU time 633.41 seconds
Started Jul 22 04:26:04 PM PDT 24
Finished Jul 22 04:52:29 PM PDT 24
Peak memory 160440 kb
Host smart-f299fad7-b45a-4f0f-941c-f073bb40573f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4039543391 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.4039543391
Directory /workspace/25.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.386596636
Short name T90
Test name
Test status
Simulation time 336646190000 ps
CPU time 774.44 seconds
Started Jul 22 04:26:29 PM PDT 24
Finished Jul 22 04:58:19 PM PDT 24
Peak memory 159740 kb
Host smart-b15f827d-0727-4749-9b1f-fe23574948b8
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=386596636 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.386596636
Directory /workspace/26.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.1031595984
Short name T96
Test name
Test status
Simulation time 336704790000 ps
CPU time 767.47 seconds
Started Jul 22 04:26:57 PM PDT 24
Finished Jul 22 04:58:21 PM PDT 24
Peak memory 160364 kb
Host smart-e0438708-3917-48b9-993c-f1acf979641f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1031595984 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.1031595984
Directory /workspace/27.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.4205465133
Short name T15
Test name
Test status
Simulation time 336770490000 ps
CPU time 708.84 seconds
Started Jul 22 04:25:26 PM PDT 24
Finished Jul 22 04:54:23 PM PDT 24
Peak memory 159768 kb
Host smart-66191123-6fd3-4700-9ccf-6efd37aa20b6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4205465133 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.4205465133
Directory /workspace/28.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.198236472
Short name T72
Test name
Test status
Simulation time 336466730000 ps
CPU time 660.22 seconds
Started Jul 22 04:25:26 PM PDT 24
Finished Jul 22 04:53:10 PM PDT 24
Peak memory 160344 kb
Host smart-58e7d07a-e083-4ec1-9a28-c5489970edbb
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=198236472 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.198236472
Directory /workspace/29.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.1787671160
Short name T20
Test name
Test status
Simulation time 336449570000 ps
CPU time 676.55 seconds
Started Jul 22 04:20:47 PM PDT 24
Finished Jul 22 04:48:44 PM PDT 24
Peak memory 159772 kb
Host smart-36ee24e6-743d-4d0e-a31b-225db01daa3f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1787671160 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.1787671160
Directory /workspace/3.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.635343494
Short name T93
Test name
Test status
Simulation time 336944010000 ps
CPU time 817.76 seconds
Started Jul 22 04:24:59 PM PDT 24
Finished Jul 22 04:57:32 PM PDT 24
Peak memory 160596 kb
Host smart-afb6d19a-2972-4556-bb11-7d7d24fcc6fc
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=635343494 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.635343494
Directory /workspace/30.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.1762375034
Short name T18
Test name
Test status
Simulation time 336991790000 ps
CPU time 692.93 seconds
Started Jul 22 04:25:10 PM PDT 24
Finished Jul 22 04:54:39 PM PDT 24
Peak memory 160584 kb
Host smart-da4da475-12f3-43c3-983c-17827a42c981
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1762375034 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.1762375034
Directory /workspace/31.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.1582238661
Short name T71
Test name
Test status
Simulation time 337018430000 ps
CPU time 891.55 seconds
Started Jul 22 04:21:52 PM PDT 24
Finished Jul 22 04:59:45 PM PDT 24
Peak memory 160504 kb
Host smart-7eb89338-ce14-40e3-a296-be511e44f3fe
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1582238661 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.1582238661
Directory /workspace/32.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.1871079204
Short name T107
Test name
Test status
Simulation time 336656390000 ps
CPU time 907.47 seconds
Started Jul 22 04:21:52 PM PDT 24
Finished Jul 22 05:00:00 PM PDT 24
Peak memory 160576 kb
Host smart-1c81d7e9-c17c-42ca-8215-a2bc58b960d9
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1871079204 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.1871079204
Directory /workspace/33.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.82384685
Short name T82
Test name
Test status
Simulation time 337007110000 ps
CPU time 747.52 seconds
Started Jul 22 04:21:29 PM PDT 24
Finished Jul 22 04:51:32 PM PDT 24
Peak memory 160844 kb
Host smart-b05a9ab5-db67-44a6-9403-c078b21f3586
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=82384685 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.82384685
Directory /workspace/34.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.924822254
Short name T85
Test name
Test status
Simulation time 336747970000 ps
CPU time 1004.42 seconds
Started Jul 22 04:21:20 PM PDT 24
Finished Jul 22 05:03:24 PM PDT 24
Peak memory 160596 kb
Host smart-acc5b9d5-d5c3-4b93-b825-a77d64ad1ded
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=924822254 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.924822254
Directory /workspace/35.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.433942048
Short name T14
Test name
Test status
Simulation time 337008970000 ps
CPU time 785.77 seconds
Started Jul 22 04:23:02 PM PDT 24
Finished Jul 22 04:54:28 PM PDT 24
Peak memory 160628 kb
Host smart-8146427c-22ba-4f8b-9036-0a5b0c27e572
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=433942048 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.433942048
Directory /workspace/36.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.3341046115
Short name T17
Test name
Test status
Simulation time 336939830000 ps
CPU time 742.17 seconds
Started Jul 22 04:22:11 PM PDT 24
Finished Jul 22 04:53:24 PM PDT 24
Peak memory 160584 kb
Host smart-96abaa7a-d71d-4a97-8a8d-492088bc6fc8
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3341046115 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.3341046115
Directory /workspace/37.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.3852120894
Short name T91
Test name
Test status
Simulation time 337053370000 ps
CPU time 796.04 seconds
Started Jul 22 04:20:56 PM PDT 24
Finished Jul 22 04:54:02 PM PDT 24
Peak memory 159292 kb
Host smart-7e85a2dc-ed53-4804-baac-64ff7026c58f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3852120894 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.3852120894
Directory /workspace/38.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.516138565
Short name T4
Test name
Test status
Simulation time 336819210000 ps
CPU time 795.7 seconds
Started Jul 22 04:21:28 PM PDT 24
Finished Jul 22 04:54:31 PM PDT 24
Peak memory 160256 kb
Host smart-6559c1b1-75b9-4b9d-8610-50eec24be670
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=516138565 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.516138565
Directory /workspace/39.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.1621081700
Short name T109
Test name
Test status
Simulation time 336711050000 ps
CPU time 673.78 seconds
Started Jul 22 04:20:47 PM PDT 24
Finished Jul 22 04:48:58 PM PDT 24
Peak memory 160184 kb
Host smart-901b9dfa-2d08-46a0-bdfd-86993369c6d6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1621081700 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.1621081700
Directory /workspace/4.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.3649049587
Short name T88
Test name
Test status
Simulation time 336470430000 ps
CPU time 695.28 seconds
Started Jul 22 04:21:58 PM PDT 24
Finished Jul 22 04:51:31 PM PDT 24
Peak memory 160380 kb
Host smart-27638680-3b89-4e02-a825-dff0d640d96c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3649049587 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.3649049587
Directory /workspace/40.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.3431694508
Short name T74
Test name
Test status
Simulation time 336379730000 ps
CPU time 697.5 seconds
Started Jul 22 04:21:58 PM PDT 24
Finished Jul 22 04:51:43 PM PDT 24
Peak memory 160384 kb
Host smart-c964afbe-73c3-4a2b-9e7e-45da1d172adf
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3431694508 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.3431694508
Directory /workspace/41.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.1945146040
Short name T86
Test name
Test status
Simulation time 336654030000 ps
CPU time 689.92 seconds
Started Jul 22 04:25:29 PM PDT 24
Finished Jul 22 04:54:19 PM PDT 24
Peak memory 159492 kb
Host smart-867bd301-0e32-429e-a5c4-b650f8ebbd68
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1945146040 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.1945146040
Directory /workspace/42.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.3021820105
Short name T99
Test name
Test status
Simulation time 336681470000 ps
CPU time 798.94 seconds
Started Jul 22 04:20:56 PM PDT 24
Finished Jul 22 04:54:05 PM PDT 24
Peak memory 159248 kb
Host smart-cafa82bc-298f-44fe-b6c1-9212194fc504
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3021820105 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.3021820105
Directory /workspace/43.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.1448437288
Short name T100
Test name
Test status
Simulation time 336423430000 ps
CPU time 690.05 seconds
Started Jul 22 04:25:29 PM PDT 24
Finished Jul 22 04:54:19 PM PDT 24
Peak memory 159468 kb
Host smart-39f38e86-acee-4a07-b88a-ada94d3dab45
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1448437288 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.1448437288
Directory /workspace/44.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.1346199686
Short name T97
Test name
Test status
Simulation time 336858190000 ps
CPU time 680.1 seconds
Started Jul 22 04:25:30 PM PDT 24
Finished Jul 22 04:54:00 PM PDT 24
Peak memory 160268 kb
Host smart-d26072b2-e627-4389-85a0-629addfb3b54
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1346199686 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.1346199686
Directory /workspace/45.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.383936397
Short name T16
Test name
Test status
Simulation time 336781770000 ps
CPU time 708.33 seconds
Started Jul 22 04:25:44 PM PDT 24
Finished Jul 22 04:55:01 PM PDT 24
Peak memory 160396 kb
Host smart-1ab2775f-f46b-4f90-a10b-302f3a29abf9
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=383936397 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.383936397
Directory /workspace/46.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.867395543
Short name T89
Test name
Test status
Simulation time 336417230000 ps
CPU time 827.11 seconds
Started Jul 22 04:26:41 PM PDT 24
Finished Jul 22 04:59:52 PM PDT 24
Peak memory 160576 kb
Host smart-8fbdbb9c-5f05-4fbf-9d93-679439363fb7
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=867395543 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.867395543
Directory /workspace/47.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.1641714609
Short name T102
Test name
Test status
Simulation time 336844630000 ps
CPU time 700.78 seconds
Started Jul 22 04:23:31 PM PDT 24
Finished Jul 22 04:53:18 PM PDT 24
Peak memory 160584 kb
Host smart-2fa0de0d-b4e6-4c8d-8104-a6764314a4c0
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1641714609 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.1641714609
Directory /workspace/48.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.3493685783
Short name T108
Test name
Test status
Simulation time 336594250000 ps
CPU time 787.78 seconds
Started Jul 22 04:26:16 PM PDT 24
Finished Jul 22 04:58:02 PM PDT 24
Peak memory 160492 kb
Host smart-271e8790-c6d9-469f-9a00-513e659f2d56
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3493685783 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.3493685783
Directory /workspace/49.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.4047940322
Short name T78
Test name
Test status
Simulation time 336471950000 ps
CPU time 660.61 seconds
Started Jul 22 04:20:48 PM PDT 24
Finished Jul 22 04:48:16 PM PDT 24
Peak memory 160248 kb
Host smart-9e36b99a-0ead-4e80-b45f-3eb241f55199
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4047940322 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.4047940322
Directory /workspace/5.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.1793253794
Short name T110
Test name
Test status
Simulation time 336391170000 ps
CPU time 617.47 seconds
Started Jul 22 04:20:42 PM PDT 24
Finished Jul 22 04:45:50 PM PDT 24
Peak memory 159772 kb
Host smart-a73d3f21-dc08-404d-9afd-e31e53f7678e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1793253794 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.1793253794
Directory /workspace/6.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.3800959042
Short name T105
Test name
Test status
Simulation time 336645630000 ps
CPU time 626.66 seconds
Started Jul 22 04:20:34 PM PDT 24
Finished Jul 22 04:46:44 PM PDT 24
Peak memory 160868 kb
Host smart-d49b781d-93b0-4612-9436-fd5d31b9332b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3800959042 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.3800959042
Directory /workspace/7.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.2613235509
Short name T104
Test name
Test status
Simulation time 336632210000 ps
CPU time 876.94 seconds
Started Jul 22 04:20:41 PM PDT 24
Finished Jul 22 04:57:50 PM PDT 24
Peak memory 160240 kb
Host smart-51793fc5-c69e-4c12-bdb0-90b11dcc272a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2613235509 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.2613235509
Directory /workspace/8.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.1106059619
Short name T87
Test name
Test status
Simulation time 336567030000 ps
CPU time 866.26 seconds
Started Jul 22 04:20:39 PM PDT 24
Finished Jul 22 04:57:53 PM PDT 24
Peak memory 159764 kb
Host smart-1357f695-5a72-402b-a7ac-43b4f484ac3c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1106059619 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.1106059619
Directory /workspace/9.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.1381319673
Short name T187
Test name
Test status
Simulation time 336548030000 ps
CPU time 788.36 seconds
Started Jul 22 06:20:40 PM PDT 24
Finished Jul 22 06:52:59 PM PDT 24
Peak memory 160820 kb
Host smart-78647a42-d51a-492d-9105-c644c6904336
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1381319673 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.1381319673
Directory /workspace/0.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.1907205473
Short name T176
Test name
Test status
Simulation time 336727370000 ps
CPU time 756.59 seconds
Started Jul 22 06:20:39 PM PDT 24
Finished Jul 22 06:51:18 PM PDT 24
Peak memory 160808 kb
Host smart-808f4122-d056-4dc9-b009-e0a2d0021aba
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1907205473 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.1907205473
Directory /workspace/1.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.1612788267
Short name T177
Test name
Test status
Simulation time 336742770000 ps
CPU time 807.41 seconds
Started Jul 22 06:20:38 PM PDT 24
Finished Jul 22 06:53:51 PM PDT 24
Peak memory 160804 kb
Host smart-69cca482-5725-4992-88e5-e9b1719d9010
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1612788267 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.1612788267
Directory /workspace/11.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.110579131
Short name T180
Test name
Test status
Simulation time 336473090000 ps
CPU time 785.29 seconds
Started Jul 22 06:20:39 PM PDT 24
Finished Jul 22 06:52:52 PM PDT 24
Peak memory 160820 kb
Host smart-67c805b6-500c-4675-8674-d482b4216b99
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=110579131 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.110579131
Directory /workspace/12.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.977863834
Short name T194
Test name
Test status
Simulation time 336399970000 ps
CPU time 737.99 seconds
Started Jul 22 06:20:39 PM PDT 24
Finished Jul 22 06:50:50 PM PDT 24
Peak memory 160760 kb
Host smart-004aabee-e13f-4153-80cd-76d764b3d4e9
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=977863834 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.977863834
Directory /workspace/13.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.2835226614
Short name T22
Test name
Test status
Simulation time 337001930000 ps
CPU time 699.39 seconds
Started Jul 22 06:21:25 PM PDT 24
Finished Jul 22 06:50:08 PM PDT 24
Peak memory 160756 kb
Host smart-9c9baca0-7bdd-4d6d-a481-4a89a2d98e22
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2835226614 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.2835226614
Directory /workspace/14.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.1442461590
Short name T183
Test name
Test status
Simulation time 336338810000 ps
CPU time 763.01 seconds
Started Jul 22 06:20:41 PM PDT 24
Finished Jul 22 06:51:45 PM PDT 24
Peak memory 160816 kb
Host smart-c4cf2fcf-4559-4b39-80db-742ca21b5f3d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1442461590 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.1442461590
Directory /workspace/15.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.511966296
Short name T182
Test name
Test status
Simulation time 336952110000 ps
CPU time 754.78 seconds
Started Jul 22 06:20:39 PM PDT 24
Finished Jul 22 06:51:14 PM PDT 24
Peak memory 160760 kb
Host smart-98043b89-33d3-489b-8804-ae0d2d53e6cb
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=511966296 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.511966296
Directory /workspace/16.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.1350685585
Short name T197
Test name
Test status
Simulation time 336460310000 ps
CPU time 774.77 seconds
Started Jul 22 06:20:41 PM PDT 24
Finished Jul 22 06:52:17 PM PDT 24
Peak memory 160824 kb
Host smart-c8e21054-c81c-4ad4-9f5c-21b2fdd73ee1
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1350685585 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.1350685585
Directory /workspace/17.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.1458441336
Short name T26
Test name
Test status
Simulation time 336671050000 ps
CPU time 745.82 seconds
Started Jul 22 06:20:39 PM PDT 24
Finished Jul 22 06:51:12 PM PDT 24
Peak memory 160632 kb
Host smart-f7ea0e9f-15fd-4c70-93f8-aee75375eb46
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1458441336 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.1458441336
Directory /workspace/18.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.3956922108
Short name T184
Test name
Test status
Simulation time 336496370000 ps
CPU time 821.59 seconds
Started Jul 22 06:21:16 PM PDT 24
Finished Jul 22 06:55:08 PM PDT 24
Peak memory 160792 kb
Host smart-8e237456-8580-4604-bee4-125d244def64
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3956922108 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.3956922108
Directory /workspace/19.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.3023308306
Short name T165
Test name
Test status
Simulation time 337037390000 ps
CPU time 707.71 seconds
Started Jul 22 06:21:25 PM PDT 24
Finished Jul 22 06:50:19 PM PDT 24
Peak memory 160748 kb
Host smart-a31cb8b6-f25f-4bf0-9d54-c5b3c0ed9445
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3023308306 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.3023308306
Directory /workspace/2.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.249967532
Short name T161
Test name
Test status
Simulation time 336837770000 ps
CPU time 748.13 seconds
Started Jul 22 06:20:37 PM PDT 24
Finished Jul 22 06:51:10 PM PDT 24
Peak memory 160772 kb
Host smart-a6f39619-4865-47a9-870a-950e27f42f21
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=249967532 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.249967532
Directory /workspace/20.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.2771234783
Short name T166
Test name
Test status
Simulation time 336999930000 ps
CPU time 746.45 seconds
Started Jul 22 06:20:50 PM PDT 24
Finished Jul 22 06:51:16 PM PDT 24
Peak memory 160676 kb
Host smart-a6f144d2-16f9-408f-bff5-26381dab7f38
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2771234783 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.2771234783
Directory /workspace/21.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.3945786609
Short name T175
Test name
Test status
Simulation time 336356150000 ps
CPU time 713.36 seconds
Started Jul 22 06:20:46 PM PDT 24
Finished Jul 22 06:49:54 PM PDT 24
Peak memory 160812 kb
Host smart-2014497f-9350-465c-9a27-bd9427ae18e3
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3945786609 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.3945786609
Directory /workspace/22.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.3134829618
Short name T185
Test name
Test status
Simulation time 336620010000 ps
CPU time 929.56 seconds
Started Jul 22 06:20:53 PM PDT 24
Finished Jul 22 06:59:04 PM PDT 24
Peak memory 160788 kb
Host smart-5afa5a20-a8c5-42b4-bf48-b6149e2dd7e4
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3134829618 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.3134829618
Directory /workspace/23.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.3560536079
Short name T23
Test name
Test status
Simulation time 336871070000 ps
CPU time 618.04 seconds
Started Jul 22 06:22:24 PM PDT 24
Finished Jul 22 06:48:23 PM PDT 24
Peak memory 160760 kb
Host smart-9ae90e59-1866-40c8-9bcd-4aa3f9b61c0c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3560536079 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.3560536079
Directory /workspace/24.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.630767379
Short name T174
Test name
Test status
Simulation time 336722710000 ps
CPU time 927.6 seconds
Started Jul 22 06:20:53 PM PDT 24
Finished Jul 22 06:58:58 PM PDT 24
Peak memory 160788 kb
Host smart-03983eb1-26af-435a-bff2-5990f678dd2d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=630767379 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.630767379
Directory /workspace/25.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.435461922
Short name T195
Test name
Test status
Simulation time 336862310000 ps
CPU time 754.17 seconds
Started Jul 22 06:20:49 PM PDT 24
Finished Jul 22 06:51:30 PM PDT 24
Peak memory 160764 kb
Host smart-b111fb7a-79d8-403b-adb2-b9f2d6fcb96b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=435461922 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.435461922
Directory /workspace/26.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.737286257
Short name T162
Test name
Test status
Simulation time 336572290000 ps
CPU time 730.21 seconds
Started Jul 22 06:20:53 PM PDT 24
Finished Jul 22 06:50:28 PM PDT 24
Peak memory 160736 kb
Host smart-07e5ff9a-8d49-4d4d-a4bd-51d0e8373f75
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=737286257 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.737286257
Directory /workspace/27.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.2529058343
Short name T193
Test name
Test status
Simulation time 336703950000 ps
CPU time 710.12 seconds
Started Jul 22 06:20:52 PM PDT 24
Finished Jul 22 06:49:57 PM PDT 24
Peak memory 160800 kb
Host smart-deb1601d-d552-4c5d-b695-4307631effcc
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2529058343 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.2529058343
Directory /workspace/28.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.1743538175
Short name T179
Test name
Test status
Simulation time 336393470000 ps
CPU time 748.4 seconds
Started Jul 22 06:20:49 PM PDT 24
Finished Jul 22 06:51:28 PM PDT 24
Peak memory 160772 kb
Host smart-06217706-ec11-4d96-a14f-5870952956a9
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1743538175 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.1743538175
Directory /workspace/29.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.718908225
Short name T173
Test name
Test status
Simulation time 336905450000 ps
CPU time 740.4 seconds
Started Jul 22 06:20:39 PM PDT 24
Finished Jul 22 06:51:00 PM PDT 24
Peak memory 160616 kb
Host smart-8b29907d-fa71-4652-9b51-d3d757de75a8
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=718908225 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.718908225
Directory /workspace/3.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.3345988412
Short name T25
Test name
Test status
Simulation time 336655150000 ps
CPU time 748.42 seconds
Started Jul 22 06:21:26 PM PDT 24
Finished Jul 22 06:52:02 PM PDT 24
Peak memory 160796 kb
Host smart-ca9b534e-85ba-48be-856f-047b3baf5721
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3345988412 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.3345988412
Directory /workspace/30.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.3622687585
Short name T171
Test name
Test status
Simulation time 336650810000 ps
CPU time 923.76 seconds
Started Jul 22 06:20:53 PM PDT 24
Finished Jul 22 06:59:04 PM PDT 24
Peak memory 160788 kb
Host smart-20ec901e-e775-40bf-ba5e-6fc1af36aab1
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3622687585 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.3622687585
Directory /workspace/31.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.2993975164
Short name T21
Test name
Test status
Simulation time 336979390000 ps
CPU time 802.03 seconds
Started Jul 22 06:20:50 PM PDT 24
Finished Jul 22 06:53:48 PM PDT 24
Peak memory 160792 kb
Host smart-b60fdc8c-798a-4305-8d34-3046ccd1601c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2993975164 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.2993975164
Directory /workspace/32.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.272935676
Short name T192
Test name
Test status
Simulation time 336885070000 ps
CPU time 816.32 seconds
Started Jul 22 06:21:18 PM PDT 24
Finished Jul 22 06:55:14 PM PDT 24
Peak memory 160792 kb
Host smart-19fd7300-7434-4fa5-b1ec-ed1d5ff6986d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=272935676 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.272935676
Directory /workspace/33.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.3823329673
Short name T169
Test name
Test status
Simulation time 336926170000 ps
CPU time 729.76 seconds
Started Jul 22 06:20:50 PM PDT 24
Finished Jul 22 06:50:20 PM PDT 24
Peak memory 160772 kb
Host smart-45fde334-3cb8-42d8-8589-7f130f8d1038
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3823329673 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.3823329673
Directory /workspace/34.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.3764903508
Short name T181
Test name
Test status
Simulation time 336884190000 ps
CPU time 753.12 seconds
Started Jul 22 06:20:47 PM PDT 24
Finished Jul 22 06:51:14 PM PDT 24
Peak memory 160800 kb
Host smart-c03ac3ff-f4a4-4e1a-86aa-7aba5c66ea7c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3764903508 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.3764903508
Directory /workspace/35.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.4288011010
Short name T24
Test name
Test status
Simulation time 336552670000 ps
CPU time 803.12 seconds
Started Jul 22 06:20:50 PM PDT 24
Finished Jul 22 06:53:41 PM PDT 24
Peak memory 160692 kb
Host smart-b4e9acf7-093c-4f8e-bb05-7d7d09f9efce
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4288011010 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.4288011010
Directory /workspace/36.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.2893763370
Short name T199
Test name
Test status
Simulation time 336399970000 ps
CPU time 788.73 seconds
Started Jul 22 06:20:49 PM PDT 24
Finished Jul 22 06:52:56 PM PDT 24
Peak memory 160824 kb
Host smart-12453f9b-9ffd-406f-9276-6ed1d8f87dde
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2893763370 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.2893763370
Directory /workspace/37.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.4114613701
Short name T188
Test name
Test status
Simulation time 337019230000 ps
CPU time 810.98 seconds
Started Jul 22 06:21:13 PM PDT 24
Finished Jul 22 06:54:30 PM PDT 24
Peak memory 160792 kb
Host smart-3811642d-7ba6-404a-8388-468b9a496fe8
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4114613701 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.4114613701
Directory /workspace/38.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.695499224
Short name T29
Test name
Test status
Simulation time 336645470000 ps
CPU time 660.13 seconds
Started Jul 22 06:20:51 PM PDT 24
Finished Jul 22 06:48:00 PM PDT 24
Peak memory 160816 kb
Host smart-458c035f-9d94-4d9d-83d8-f575f386f2e6
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=695499224 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.695499224
Directory /workspace/39.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.1737524945
Short name T163
Test name
Test status
Simulation time 337115690000 ps
CPU time 548.68 seconds
Started Jul 22 06:21:09 PM PDT 24
Finished Jul 22 06:44:25 PM PDT 24
Peak memory 160800 kb
Host smart-c5d3dc8e-a0d5-42ce-8fde-1a0b4b84216d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1737524945 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.1737524945
Directory /workspace/4.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.671314216
Short name T190
Test name
Test status
Simulation time 336463730000 ps
CPU time 798.2 seconds
Started Jul 22 06:20:55 PM PDT 24
Finished Jul 22 06:53:14 PM PDT 24
Peak memory 160784 kb
Host smart-479952e8-5dc4-45b0-8562-9bafa5f94b8a
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=671314216 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.671314216
Directory /workspace/40.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.2664094398
Short name T170
Test name
Test status
Simulation time 336950890000 ps
CPU time 757.25 seconds
Started Jul 22 06:20:52 PM PDT 24
Finished Jul 22 06:51:26 PM PDT 24
Peak memory 160908 kb
Host smart-5f3a30a9-29d7-4ccb-b6d7-c8d521e429c3
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2664094398 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.2664094398
Directory /workspace/41.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.3212533248
Short name T198
Test name
Test status
Simulation time 336596030000 ps
CPU time 738.63 seconds
Started Jul 22 06:20:49 PM PDT 24
Finished Jul 22 06:50:56 PM PDT 24
Peak memory 160808 kb
Host smart-1dc4df55-63e6-434f-91ff-78433a0dd609
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3212533248 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.3212533248
Directory /workspace/42.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.3126891107
Short name T191
Test name
Test status
Simulation time 336491910000 ps
CPU time 722.61 seconds
Started Jul 22 06:20:51 PM PDT 24
Finished Jul 22 06:50:08 PM PDT 24
Peak memory 160848 kb
Host smart-33a080ae-96e8-4cb7-9950-95d59971be63
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3126891107 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.3126891107
Directory /workspace/43.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.1561039853
Short name T186
Test name
Test status
Simulation time 336752050000 ps
CPU time 816.7 seconds
Started Jul 22 06:21:16 PM PDT 24
Finished Jul 22 06:55:06 PM PDT 24
Peak memory 160792 kb
Host smart-07b3d528-7a09-454c-b0f2-3932e5eb3138
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1561039853 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.1561039853
Directory /workspace/44.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.4040281038
Short name T28
Test name
Test status
Simulation time 336916230000 ps
CPU time 754.41 seconds
Started Jul 22 06:20:51 PM PDT 24
Finished Jul 22 06:51:28 PM PDT 24
Peak memory 160836 kb
Host smart-fcab293e-3328-4d27-b605-4182c6022464
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4040281038 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.4040281038
Directory /workspace/45.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.302996549
Short name T168
Test name
Test status
Simulation time 336452610000 ps
CPU time 723.19 seconds
Started Jul 22 06:20:58 PM PDT 24
Finished Jul 22 06:50:34 PM PDT 24
Peak memory 160820 kb
Host smart-dcc8b1ca-af76-4b08-b3d1-75cc222e1489
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=302996549 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.302996549
Directory /workspace/46.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.2559892885
Short name T200
Test name
Test status
Simulation time 336578890000 ps
CPU time 805.3 seconds
Started Jul 22 06:20:47 PM PDT 24
Finished Jul 22 06:53:42 PM PDT 24
Peak memory 160804 kb
Host smart-934d0c12-7c0f-4c93-9d92-3f24d93ed317
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2559892885 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.2559892885
Directory /workspace/47.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.3267603863
Short name T178
Test name
Test status
Simulation time 337080030000 ps
CPU time 751.3 seconds
Started Jul 22 06:20:50 PM PDT 24
Finished Jul 22 06:51:17 PM PDT 24
Peak memory 160784 kb
Host smart-1ac27e00-a72d-4a52-a7fd-08a3cfa35958
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3267603863 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.3267603863
Directory /workspace/48.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.2794667400
Short name T196
Test name
Test status
Simulation time 336464230000 ps
CPU time 736.73 seconds
Started Jul 22 06:20:49 PM PDT 24
Finished Jul 22 06:50:52 PM PDT 24
Peak memory 160808 kb
Host smart-abd3f3e3-412a-4f77-8f3d-94d95dad2fd7
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2794667400 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.2794667400
Directory /workspace/49.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.1303199165
Short name T189
Test name
Test status
Simulation time 337085990000 ps
CPU time 647.28 seconds
Started Jul 22 06:20:43 PM PDT 24
Finished Jul 22 06:47:03 PM PDT 24
Peak memory 160800 kb
Host smart-29d234ae-1683-4873-bd1d-4bd387bb0df5
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1303199165 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.1303199165
Directory /workspace/5.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.118097089
Short name T30
Test name
Test status
Simulation time 337062970000 ps
CPU time 789.78 seconds
Started Jul 22 06:20:40 PM PDT 24
Finished Jul 22 06:52:49 PM PDT 24
Peak memory 160792 kb
Host smart-02490bf3-3a97-4999-b8fe-b0dc206bbab5
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=118097089 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.118097089
Directory /workspace/6.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.631165212
Short name T164
Test name
Test status
Simulation time 336523150000 ps
CPU time 785.55 seconds
Started Jul 22 06:20:39 PM PDT 24
Finished Jul 22 06:52:50 PM PDT 24
Peak memory 160820 kb
Host smart-2fb76b20-7c04-42a7-a614-8b25fb5e620e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=631165212 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.631165212
Directory /workspace/7.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.1971646599
Short name T172
Test name
Test status
Simulation time 336438650000 ps
CPU time 759.66 seconds
Started Jul 22 06:20:39 PM PDT 24
Finished Jul 22 06:51:19 PM PDT 24
Peak memory 160808 kb
Host smart-bce16417-c008-4f8a-a108-665d6d36821d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1971646599 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.1971646599
Directory /workspace/8.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.1704337694
Short name T167
Test name
Test status
Simulation time 336370230000 ps
CPU time 640.61 seconds
Started Jul 22 06:20:44 PM PDT 24
Finished Jul 22 06:46:48 PM PDT 24
Peak memory 160800 kb
Host smart-ac9d8039-c8f9-4419-86cd-4a86f218cf0f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1704337694 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.1704337694
Directory /workspace/9.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.3352909747
Short name T154
Test name
Test status
Simulation time 1577790000 ps
CPU time 5 seconds
Started Jul 22 06:20:39 PM PDT 24
Finished Jul 22 06:20:51 PM PDT 24
Peak memory 164940 kb
Host smart-daa44e9e-fd04-47d9-b2cc-9f12e6869ad7
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3352909747 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.3352909747
Directory /workspace/0.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.996719600
Short name T129
Test name
Test status
Simulation time 1534270000 ps
CPU time 4.19 seconds
Started Jul 22 06:20:33 PM PDT 24
Finished Jul 22 06:20:44 PM PDT 24
Peak memory 164888 kb
Host smart-5d68b285-5738-4e6c-9a02-9d489cac2c71
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=996719600 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.996719600
Directory /workspace/1.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.3689135890
Short name T138
Test name
Test status
Simulation time 1558610000 ps
CPU time 4.73 seconds
Started Jul 22 06:20:35 PM PDT 24
Finished Jul 22 06:20:46 PM PDT 24
Peak memory 164856 kb
Host smart-62888f66-101d-4c29-87f7-d776d63c3f54
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3689135890 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.3689135890
Directory /workspace/10.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.3041369743
Short name T111
Test name
Test status
Simulation time 1531090000 ps
CPU time 4.68 seconds
Started Jul 22 06:20:38 PM PDT 24
Finished Jul 22 06:20:50 PM PDT 24
Peak memory 164968 kb
Host smart-750dbd95-c3ec-41fc-b060-89b01dbad7a8
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3041369743 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.3041369743
Directory /workspace/11.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.3854698811
Short name T142
Test name
Test status
Simulation time 1646010000 ps
CPU time 3.11 seconds
Started Jul 22 06:22:12 PM PDT 24
Finished Jul 22 06:22:21 PM PDT 24
Peak memory 164944 kb
Host smart-80f85be3-05c1-4c0c-ba36-60df07c35571
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3854698811 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.3854698811
Directory /workspace/12.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.1461972963
Short name T153
Test name
Test status
Simulation time 1584870000 ps
CPU time 4.84 seconds
Started Jul 22 06:20:38 PM PDT 24
Finished Jul 22 06:20:50 PM PDT 24
Peak memory 164968 kb
Host smart-19f6d14e-526a-4b28-b25e-509bec53554b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1461972963 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.1461972963
Directory /workspace/13.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.1957919782
Short name T139
Test name
Test status
Simulation time 1286010000 ps
CPU time 3.79 seconds
Started Jul 22 06:20:38 PM PDT 24
Finished Jul 22 06:20:48 PM PDT 24
Peak memory 164968 kb
Host smart-229672bf-bf71-4fb5-b8ff-df620a32baec
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1957919782 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.1957919782
Directory /workspace/14.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.3082256225
Short name T148
Test name
Test status
Simulation time 1512370000 ps
CPU time 4.48 seconds
Started Jul 22 06:20:39 PM PDT 24
Finished Jul 22 06:20:50 PM PDT 24
Peak memory 164964 kb
Host smart-f53b2d20-8a49-4a36-9fcd-6c42c3ca8f64
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3082256225 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.3082256225
Directory /workspace/15.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.2803343307
Short name T149
Test name
Test status
Simulation time 1500470000 ps
CPU time 4.4 seconds
Started Jul 22 06:20:38 PM PDT 24
Finished Jul 22 06:20:49 PM PDT 24
Peak memory 164964 kb
Host smart-c779518b-9e3f-41ef-9148-3de6480739a3
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2803343307 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.2803343307
Directory /workspace/16.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.3176076528
Short name T135
Test name
Test status
Simulation time 1438650000 ps
CPU time 4.61 seconds
Started Jul 22 06:20:38 PM PDT 24
Finished Jul 22 06:20:50 PM PDT 24
Peak memory 164968 kb
Host smart-90f4ed08-711a-488f-80e4-5e458bb6ab43
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3176076528 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.3176076528
Directory /workspace/17.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.609408891
Short name T113
Test name
Test status
Simulation time 1303310000 ps
CPU time 4 seconds
Started Jul 22 06:20:38 PM PDT 24
Finished Jul 22 06:20:49 PM PDT 24
Peak memory 164960 kb
Host smart-8b5ff536-17d2-4015-90bb-7d99bfa79448
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=609408891 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.609408891
Directory /workspace/18.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.3527616268
Short name T122
Test name
Test status
Simulation time 1349090000 ps
CPU time 4.36 seconds
Started Jul 22 06:20:39 PM PDT 24
Finished Jul 22 06:20:50 PM PDT 24
Peak memory 164940 kb
Host smart-1bbdff41-70ae-46c7-8f18-844307cff769
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3527616268 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.3527616268
Directory /workspace/19.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.3687689744
Short name T157
Test name
Test status
Simulation time 1466550000 ps
CPU time 4.7 seconds
Started Jul 22 06:20:41 PM PDT 24
Finished Jul 22 06:20:52 PM PDT 24
Peak memory 164980 kb
Host smart-24b15103-8b48-4273-a730-e955d070fd36
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3687689744 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.3687689744
Directory /workspace/2.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.790365404
Short name T146
Test name
Test status
Simulation time 1317770000 ps
CPU time 2.92 seconds
Started Jul 22 06:20:54 PM PDT 24
Finished Jul 22 06:21:01 PM PDT 24
Peak memory 164916 kb
Host smart-10929dea-ccbb-4fcc-8e68-320d39dac1f0
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=790365404 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.790365404
Directory /workspace/20.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3464059283
Short name T125
Test name
Test status
Simulation time 1572330000 ps
CPU time 4.42 seconds
Started Jul 22 06:20:38 PM PDT 24
Finished Jul 22 06:20:50 PM PDT 24
Peak memory 164964 kb
Host smart-136c623f-d87e-4161-949b-7e2b85d180d9
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3464059283 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.3464059283
Directory /workspace/21.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.19881716
Short name T150
Test name
Test status
Simulation time 1456770000 ps
CPU time 4.4 seconds
Started Jul 22 06:20:38 PM PDT 24
Finished Jul 22 06:20:49 PM PDT 24
Peak memory 164888 kb
Host smart-e2e0547b-c904-4903-be4a-fe2c9c6cb0c0
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=19881716 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.19881716
Directory /workspace/22.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.312415097
Short name T152
Test name
Test status
Simulation time 1514890000 ps
CPU time 4.14 seconds
Started Jul 22 06:20:37 PM PDT 24
Finished Jul 22 06:20:47 PM PDT 24
Peak memory 164960 kb
Host smart-59d77be3-63d5-4303-99bf-8079c33375fd
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=312415097 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.312415097
Directory /workspace/23.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.3907080348
Short name T156
Test name
Test status
Simulation time 1448710000 ps
CPU time 4.48 seconds
Started Jul 22 06:20:37 PM PDT 24
Finished Jul 22 06:20:47 PM PDT 24
Peak memory 164948 kb
Host smart-f9c2d0b3-631f-4037-90e5-53e2e6855d14
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3907080348 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.3907080348
Directory /workspace/24.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.984298656
Short name T155
Test name
Test status
Simulation time 1422670000 ps
CPU time 3.72 seconds
Started Jul 22 06:20:41 PM PDT 24
Finished Jul 22 06:20:50 PM PDT 24
Peak memory 164968 kb
Host smart-38a31610-9a0d-40d0-83a7-fd22d2d0fc4c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=984298656 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.984298656
Directory /workspace/25.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2283282327
Short name T137
Test name
Test status
Simulation time 1536950000 ps
CPU time 3.89 seconds
Started Jul 22 06:21:10 PM PDT 24
Finished Jul 22 06:21:19 PM PDT 24
Peak memory 164964 kb
Host smart-39483457-3d06-4d4d-a90b-866011095648
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2283282327 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.2283282327
Directory /workspace/26.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.3163941510
Short name T141
Test name
Test status
Simulation time 1589250000 ps
CPU time 3.76 seconds
Started Jul 22 06:21:04 PM PDT 24
Finished Jul 22 06:21:12 PM PDT 24
Peak memory 164932 kb
Host smart-bd407661-b5ad-4404-be80-e245edcad0f7
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3163941510 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.3163941510
Directory /workspace/27.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.1797271034
Short name T124
Test name
Test status
Simulation time 1283190000 ps
CPU time 3.34 seconds
Started Jul 22 06:22:18 PM PDT 24
Finished Jul 22 06:22:26 PM PDT 24
Peak memory 164908 kb
Host smart-c3ffa16e-9e2e-4b32-b0ad-03c52ca6eaac
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1797271034 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.1797271034
Directory /workspace/28.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.3491605420
Short name T145
Test name
Test status
Simulation time 1322170000 ps
CPU time 4.14 seconds
Started Jul 22 06:20:40 PM PDT 24
Finished Jul 22 06:20:50 PM PDT 24
Peak memory 164968 kb
Host smart-d04472d5-5aa4-47e7-b370-722475ab2ea9
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3491605420 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.3491605420
Directory /workspace/29.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.2226305146
Short name T123
Test name
Test status
Simulation time 1477830000 ps
CPU time 3.43 seconds
Started Jul 22 06:21:04 PM PDT 24
Finished Jul 22 06:21:12 PM PDT 24
Peak memory 164944 kb
Host smart-955ac122-af45-4c72-a418-a4465c7fb726
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2226305146 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.2226305146
Directory /workspace/3.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.170734887
Short name T112
Test name
Test status
Simulation time 1488050000 ps
CPU time 2.97 seconds
Started Jul 22 06:23:01 PM PDT 24
Finished Jul 22 06:23:09 PM PDT 24
Peak memory 164908 kb
Host smart-43425cda-8590-47de-9dc8-385bf57bf824
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=170734887 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.170734887
Directory /workspace/30.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.1089274941
Short name T143
Test name
Test status
Simulation time 1352590000 ps
CPU time 4.15 seconds
Started Jul 22 06:20:43 PM PDT 24
Finished Jul 22 06:20:53 PM PDT 24
Peak memory 164940 kb
Host smart-5cdc127d-77f0-4f2e-9b0c-44d7e7722db1
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1089274941 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.1089274941
Directory /workspace/31.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.3696485916
Short name T134
Test name
Test status
Simulation time 1455050000 ps
CPU time 3.97 seconds
Started Jul 22 06:20:38 PM PDT 24
Finished Jul 22 06:20:47 PM PDT 24
Peak memory 164972 kb
Host smart-f7977e66-fd6b-4cdf-aa67-52d9528ce520
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3696485916 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.3696485916
Directory /workspace/32.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.2614477120
Short name T121
Test name
Test status
Simulation time 1435990000 ps
CPU time 4.86 seconds
Started Jul 22 06:20:38 PM PDT 24
Finished Jul 22 06:20:48 PM PDT 24
Peak memory 164984 kb
Host smart-4edfc996-7ec8-44ea-8116-8c189bd80c9e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2614477120 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.2614477120
Directory /workspace/33.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.526752181
Short name T127
Test name
Test status
Simulation time 1127950000 ps
CPU time 3.16 seconds
Started Jul 22 06:20:39 PM PDT 24
Finished Jul 22 06:20:47 PM PDT 24
Peak memory 164912 kb
Host smart-4140ffc9-6c84-4d13-bb84-89205a1377a1
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=526752181 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.526752181
Directory /workspace/34.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.2194950333
Short name T131
Test name
Test status
Simulation time 1352290000 ps
CPU time 4.59 seconds
Started Jul 22 06:20:38 PM PDT 24
Finished Jul 22 06:20:49 PM PDT 24
Peak memory 164964 kb
Host smart-f27ddf6c-738d-40b3-a9e5-ffec6ee204da
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2194950333 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.2194950333
Directory /workspace/35.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.1675465063
Short name T126
Test name
Test status
Simulation time 1475170000 ps
CPU time 3.01 seconds
Started Jul 22 06:22:27 PM PDT 24
Finished Jul 22 06:22:36 PM PDT 24
Peak memory 164972 kb
Host smart-e68f7ccd-3685-43c4-a541-63040abfb474
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1675465063 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.1675465063
Directory /workspace/36.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.4262642339
Short name T115
Test name
Test status
Simulation time 1338330000 ps
CPU time 3.74 seconds
Started Jul 22 06:20:40 PM PDT 24
Finished Jul 22 06:20:49 PM PDT 24
Peak memory 164956 kb
Host smart-115d962d-93b7-443f-82f4-c5f8e384babf
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4262642339 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.4262642339
Directory /workspace/37.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.2185459109
Short name T160
Test name
Test status
Simulation time 1544070000 ps
CPU time 4.55 seconds
Started Jul 22 06:20:44 PM PDT 24
Finished Jul 22 06:20:54 PM PDT 24
Peak memory 164940 kb
Host smart-802ad9e7-aae7-4a83-ac63-3fe904e136bf
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2185459109 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.2185459109
Directory /workspace/38.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.1119585955
Short name T114
Test name
Test status
Simulation time 1452870000 ps
CPU time 4.75 seconds
Started Jul 22 06:20:44 PM PDT 24
Finished Jul 22 06:20:55 PM PDT 24
Peak memory 164940 kb
Host smart-e8dab9ab-bae9-4a21-ba5d-3eeacd6c01bf
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1119585955 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.1119585955
Directory /workspace/39.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.2124629861
Short name T130
Test name
Test status
Simulation time 1382430000 ps
CPU time 3.55 seconds
Started Jul 22 06:20:32 PM PDT 24
Finished Jul 22 06:20:42 PM PDT 24
Peak memory 164984 kb
Host smart-dd0c0fcb-2953-416e-aa72-6830a1d720d5
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2124629861 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.2124629861
Directory /workspace/4.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.3775492882
Short name T133
Test name
Test status
Simulation time 1322230000 ps
CPU time 3.45 seconds
Started Jul 22 06:20:38 PM PDT 24
Finished Jul 22 06:20:47 PM PDT 24
Peak memory 165056 kb
Host smart-7029922c-bb91-4d5c-93e8-d211b2878c11
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3775492882 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.3775492882
Directory /workspace/40.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.1117301247
Short name T140
Test name
Test status
Simulation time 1361610000 ps
CPU time 4.54 seconds
Started Jul 22 06:20:38 PM PDT 24
Finished Jul 22 06:20:49 PM PDT 24
Peak memory 164964 kb
Host smart-37bea556-13ca-4613-baea-e7dea9b02194
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1117301247 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.1117301247
Directory /workspace/41.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.2217017770
Short name T119
Test name
Test status
Simulation time 1431350000 ps
CPU time 4.28 seconds
Started Jul 22 06:20:37 PM PDT 24
Finished Jul 22 06:20:47 PM PDT 24
Peak memory 164924 kb
Host smart-7a82b6f6-21fc-4c3f-8084-f0368c8368f8
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2217017770 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.2217017770
Directory /workspace/42.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1710278243
Short name T120
Test name
Test status
Simulation time 1577070000 ps
CPU time 4.35 seconds
Started Jul 22 06:21:02 PM PDT 24
Finished Jul 22 06:21:12 PM PDT 24
Peak memory 164972 kb
Host smart-5b922ecc-7f43-41e8-8acc-1a6a4cef38b3
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1710278243 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.1710278243
Directory /workspace/43.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.806812498
Short name T159
Test name
Test status
Simulation time 1469930000 ps
CPU time 4.09 seconds
Started Jul 22 06:20:42 PM PDT 24
Finished Jul 22 06:20:51 PM PDT 24
Peak memory 164880 kb
Host smart-57bc7c2b-7645-4990-b116-04ff8fbc1e56
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=806812498 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.806812498
Directory /workspace/44.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.1639331396
Short name T136
Test name
Test status
Simulation time 1479830000 ps
CPU time 4.01 seconds
Started Jul 22 06:20:38 PM PDT 24
Finished Jul 22 06:20:49 PM PDT 24
Peak memory 164972 kb
Host smart-a52811a8-9078-45d6-8045-3fce5b21d388
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1639331396 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.1639331396
Directory /workspace/45.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.3536598313
Short name T116
Test name
Test status
Simulation time 1547610000 ps
CPU time 4.01 seconds
Started Jul 22 06:20:39 PM PDT 24
Finished Jul 22 06:20:49 PM PDT 24
Peak memory 164840 kb
Host smart-d7caad39-a369-4560-94bb-c52cf7cefa3d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3536598313 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.3536598313
Directory /workspace/46.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.3709761837
Short name T147
Test name
Test status
Simulation time 1387430000 ps
CPU time 3.81 seconds
Started Jul 22 06:20:37 PM PDT 24
Finished Jul 22 06:20:45 PM PDT 24
Peak memory 164948 kb
Host smart-6ddaf23f-d0a6-4dbd-ac31-34044f9e4675
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3709761837 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.3709761837
Directory /workspace/47.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.1364168168
Short name T144
Test name
Test status
Simulation time 1404950000 ps
CPU time 3.84 seconds
Started Jul 22 06:20:39 PM PDT 24
Finished Jul 22 06:20:49 PM PDT 24
Peak memory 164924 kb
Host smart-81344ac4-db56-429c-b0e8-0f2e2be9f644
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1364168168 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.1364168168
Directory /workspace/48.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.3000266183
Short name T117
Test name
Test status
Simulation time 1503430000 ps
CPU time 3.73 seconds
Started Jul 22 06:20:38 PM PDT 24
Finished Jul 22 06:20:48 PM PDT 24
Peak memory 164916 kb
Host smart-dc9c43a0-cc86-4924-bd4b-16603c0c529f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3000266183 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.3000266183
Directory /workspace/49.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.2674644806
Short name T118
Test name
Test status
Simulation time 1559430000 ps
CPU time 4.92 seconds
Started Jul 22 06:20:35 PM PDT 24
Finished Jul 22 06:20:47 PM PDT 24
Peak memory 164948 kb
Host smart-af743486-6053-472b-bf40-f410a2bf24dd
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2674644806 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.2674644806
Directory /workspace/5.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.2686357580
Short name T151
Test name
Test status
Simulation time 1390310000 ps
CPU time 3.79 seconds
Started Jul 22 06:20:32 PM PDT 24
Finished Jul 22 06:20:42 PM PDT 24
Peak memory 164972 kb
Host smart-3f0b223e-da9b-4df5-a84d-2706dd25a733
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2686357580 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.2686357580
Directory /workspace/6.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.3981385225
Short name T128
Test name
Test status
Simulation time 1554270000 ps
CPU time 4.66 seconds
Started Jul 22 06:20:38 PM PDT 24
Finished Jul 22 06:20:49 PM PDT 24
Peak memory 164940 kb
Host smart-c68d29e3-1e93-42c1-a873-5fcea359ed43
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3981385225 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.3981385225
Directory /workspace/7.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1011727970
Short name T132
Test name
Test status
Simulation time 1290670000 ps
CPU time 4.27 seconds
Started Jul 22 06:20:35 PM PDT 24
Finished Jul 22 06:20:45 PM PDT 24
Peak memory 164856 kb
Host smart-15c560c3-163d-478b-98df-7c80bf4fd9f1
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1011727970 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.1011727970
Directory /workspace/8.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.3391448663
Short name T158
Test name
Test status
Simulation time 1404590000 ps
CPU time 4.24 seconds
Started Jul 22 06:20:38 PM PDT 24
Finished Jul 22 06:20:49 PM PDT 24
Peak memory 164968 kb
Host smart-c480fe1e-826e-429a-aed3-30cc7989418f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3391448663 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.3391448663
Directory /workspace/9.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.837001472
Short name T61
Test name
Test status
Simulation time 1519770000 ps
CPU time 3.49 seconds
Started Jul 22 04:59:35 PM PDT 24
Finished Jul 22 04:59:43 PM PDT 24
Peak memory 164880 kb
Host smart-c0f043f1-deb6-4894-b00a-83f4023aa4bd
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=837001472 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.837001472
Directory /workspace/0.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.347289786
Short name T51
Test name
Test status
Simulation time 1506170000 ps
CPU time 5.22 seconds
Started Jul 22 04:56:56 PM PDT 24
Finished Jul 22 04:57:08 PM PDT 24
Peak memory 164840 kb
Host smart-bacdd05a-d7be-4f3c-8b0a-62357b9b321f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=347289786 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.347289786
Directory /workspace/1.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.3808310
Short name T65
Test name
Test status
Simulation time 1355750000 ps
CPU time 3.93 seconds
Started Jul 22 04:56:54 PM PDT 24
Finished Jul 22 04:57:03 PM PDT 24
Peak memory 164812 kb
Host smart-5d470358-1de5-42fd-9e4b-0ed128e17e6c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3808310 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.3808310
Directory /workspace/11.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.2341052974
Short name T38
Test name
Test status
Simulation time 1625850000 ps
CPU time 4.16 seconds
Started Jul 22 04:56:59 PM PDT 24
Finished Jul 22 04:57:09 PM PDT 24
Peak memory 164928 kb
Host smart-7c24351b-b32b-4c41-a2f6-81f0a07300f8
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2341052974 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.2341052974
Directory /workspace/12.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.1518244233
Short name T42
Test name
Test status
Simulation time 1429990000 ps
CPU time 3.91 seconds
Started Jul 22 04:56:53 PM PDT 24
Finished Jul 22 04:57:02 PM PDT 24
Peak memory 164824 kb
Host smart-53597319-a1a4-4f68-83df-39d11db926ec
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1518244233 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.1518244233
Directory /workspace/13.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.787878121
Short name T46
Test name
Test status
Simulation time 1540850000 ps
CPU time 5 seconds
Started Jul 22 04:56:54 PM PDT 24
Finished Jul 22 04:57:06 PM PDT 24
Peak memory 164852 kb
Host smart-293f599a-0f24-4db3-a91c-c76eef554f58
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=787878121 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.787878121
Directory /workspace/14.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.2349063245
Short name T45
Test name
Test status
Simulation time 1298210000 ps
CPU time 4.39 seconds
Started Jul 22 04:56:54 PM PDT 24
Finished Jul 22 04:57:04 PM PDT 24
Peak memory 164876 kb
Host smart-3838ad16-9459-46bc-b8b5-16c5c1be3770
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2349063245 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.2349063245
Directory /workspace/15.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.2200882902
Short name T11
Test name
Test status
Simulation time 1428970000 ps
CPU time 4.05 seconds
Started Jul 22 04:56:59 PM PDT 24
Finished Jul 22 04:57:08 PM PDT 24
Peak memory 164928 kb
Host smart-89a51978-dc36-40c1-bd27-9572c0c215b6
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2200882902 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.2200882902
Directory /workspace/16.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.2349391882
Short name T7
Test name
Test status
Simulation time 1391950000 ps
CPU time 3.9 seconds
Started Jul 22 04:56:59 PM PDT 24
Finished Jul 22 04:57:08 PM PDT 24
Peak memory 164944 kb
Host smart-cb7b937a-859f-4154-80e3-b16f92d490ac
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2349391882 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.2349391882
Directory /workspace/17.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.1960255040
Short name T60
Test name
Test status
Simulation time 1394450000 ps
CPU time 3.6 seconds
Started Jul 22 04:56:52 PM PDT 24
Finished Jul 22 04:57:01 PM PDT 24
Peak memory 164848 kb
Host smart-0b197d1b-9fb3-4703-908d-a6b24c09da68
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1960255040 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.1960255040
Directory /workspace/18.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.2851127053
Short name T34
Test name
Test status
Simulation time 1436010000 ps
CPU time 4.94 seconds
Started Jul 22 04:56:57 PM PDT 24
Finished Jul 22 04:57:08 PM PDT 24
Peak memory 164916 kb
Host smart-2561ba5d-bbb0-41aa-9786-96ca0cf8051c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2851127053 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.2851127053
Directory /workspace/19.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.149083519
Short name T70
Test name
Test status
Simulation time 1529570000 ps
CPU time 5.62 seconds
Started Jul 22 04:56:53 PM PDT 24
Finished Jul 22 04:57:07 PM PDT 24
Peak memory 164776 kb
Host smart-f2a7bcf7-5c8a-406f-975a-8f904f619c3e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=149083519 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.149083519
Directory /workspace/2.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.1345563198
Short name T12
Test name
Test status
Simulation time 1429250000 ps
CPU time 3.44 seconds
Started Jul 22 04:56:52 PM PDT 24
Finished Jul 22 04:57:00 PM PDT 24
Peak memory 164920 kb
Host smart-be746a18-b0ad-499d-a2e4-904ab8bde4d6
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1345563198 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.1345563198
Directory /workspace/20.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.680411137
Short name T67
Test name
Test status
Simulation time 1317730000 ps
CPU time 3.76 seconds
Started Jul 22 04:56:54 PM PDT 24
Finished Jul 22 04:57:02 PM PDT 24
Peak memory 164984 kb
Host smart-5fb9893a-899a-4fc4-8b24-de2ccb46b2e3
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=680411137 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.680411137
Directory /workspace/21.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.3501428850
Short name T49
Test name
Test status
Simulation time 1559970000 ps
CPU time 5.98 seconds
Started Jul 22 04:56:53 PM PDT 24
Finished Jul 22 04:57:07 PM PDT 24
Peak memory 164920 kb
Host smart-afdc7e37-08be-494a-83c7-6e7f4f460ef1
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3501428850 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.3501428850
Directory /workspace/22.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.2840430322
Short name T66
Test name
Test status
Simulation time 1379070000 ps
CPU time 4.64 seconds
Started Jul 22 04:56:55 PM PDT 24
Finished Jul 22 04:57:06 PM PDT 24
Peak memory 164928 kb
Host smart-1328fb96-ac72-46c6-9e98-a7854ef6e545
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2840430322 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.2840430322
Directory /workspace/23.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.2730540460
Short name T44
Test name
Test status
Simulation time 1450790000 ps
CPU time 4.92 seconds
Started Jul 22 04:56:56 PM PDT 24
Finished Jul 22 04:57:07 PM PDT 24
Peak memory 164928 kb
Host smart-d6433fbe-e489-4cd8-bd2c-c0d9814aceb8
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2730540460 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.2730540460
Directory /workspace/24.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.3273879714
Short name T33
Test name
Test status
Simulation time 1520470000 ps
CPU time 3.93 seconds
Started Jul 22 04:56:59 PM PDT 24
Finished Jul 22 04:57:08 PM PDT 24
Peak memory 164944 kb
Host smart-e94f693e-d4b6-4167-b853-e9282d882390
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3273879714 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.3273879714
Directory /workspace/25.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.3025381766
Short name T41
Test name
Test status
Simulation time 1521250000 ps
CPU time 4.02 seconds
Started Jul 22 04:56:52 PM PDT 24
Finished Jul 22 04:57:02 PM PDT 24
Peak memory 164944 kb
Host smart-4bcef0cf-888f-4ccc-9b65-549756b6f14e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3025381766 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.3025381766
Directory /workspace/26.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.2061368495
Short name T68
Test name
Test status
Simulation time 1547430000 ps
CPU time 5.37 seconds
Started Jul 22 04:56:52 PM PDT 24
Finished Jul 22 04:57:04 PM PDT 24
Peak memory 164836 kb
Host smart-6c493407-6422-461c-a466-62f335fd16bc
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2061368495 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.2061368495
Directory /workspace/27.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.39470856
Short name T47
Test name
Test status
Simulation time 1451330000 ps
CPU time 4.14 seconds
Started Jul 22 04:56:51 PM PDT 24
Finished Jul 22 04:57:01 PM PDT 24
Peak memory 164860 kb
Host smart-4d228e90-11ad-440e-aeaa-8e03f7571138
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=39470856 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.39470856
Directory /workspace/28.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.3339402853
Short name T64
Test name
Test status
Simulation time 1294370000 ps
CPU time 4.47 seconds
Started Jul 22 04:56:54 PM PDT 24
Finished Jul 22 04:57:04 PM PDT 24
Peak memory 164796 kb
Host smart-5b2bab01-5fe7-4271-88a6-5adcbc151a21
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3339402853 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.3339402853
Directory /workspace/29.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.2043125051
Short name T40
Test name
Test status
Simulation time 1497770000 ps
CPU time 4.33 seconds
Started Jul 22 04:56:55 PM PDT 24
Finished Jul 22 04:57:04 PM PDT 24
Peak memory 164892 kb
Host smart-88a1e42c-69a7-452a-a65e-0a782df20571
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2043125051 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.2043125051
Directory /workspace/3.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.855660640
Short name T59
Test name
Test status
Simulation time 1352390000 ps
CPU time 3.69 seconds
Started Jul 22 04:56:59 PM PDT 24
Finished Jul 22 04:57:08 PM PDT 24
Peak memory 164940 kb
Host smart-151d71e8-da73-4b60-82ae-0b869a3aa206
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=855660640 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.855660640
Directory /workspace/30.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.2082249683
Short name T63
Test name
Test status
Simulation time 1395230000 ps
CPU time 3.78 seconds
Started Jul 22 04:56:53 PM PDT 24
Finished Jul 22 04:57:02 PM PDT 24
Peak memory 164844 kb
Host smart-1acfdce4-f89a-4ec5-b615-37a8a5cfd0e4
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2082249683 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.2082249683
Directory /workspace/31.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.1166232885
Short name T35
Test name
Test status
Simulation time 1560090000 ps
CPU time 5.12 seconds
Started Jul 22 04:56:54 PM PDT 24
Finished Jul 22 04:57:06 PM PDT 24
Peak memory 164876 kb
Host smart-37d38fe6-b5ad-4fbc-9497-abf35d59b6eb
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1166232885 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.1166232885
Directory /workspace/32.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.800726849
Short name T13
Test name
Test status
Simulation time 1578170000 ps
CPU time 4.49 seconds
Started Jul 22 04:56:52 PM PDT 24
Finished Jul 22 04:57:03 PM PDT 24
Peak memory 164864 kb
Host smart-e8ed83d0-e3c9-4c5f-a4ac-5b315737250b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=800726849 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.800726849
Directory /workspace/33.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.3467237847
Short name T8
Test name
Test status
Simulation time 1544050000 ps
CPU time 4.84 seconds
Started Jul 22 04:56:56 PM PDT 24
Finished Jul 22 04:57:07 PM PDT 24
Peak memory 164928 kb
Host smart-74bb5f07-d5f0-460e-aa6b-fa50d11f09f9
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3467237847 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.3467237847
Directory /workspace/34.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.1281326448
Short name T48
Test name
Test status
Simulation time 1184750000 ps
CPU time 3.31 seconds
Started Jul 22 04:57:02 PM PDT 24
Finished Jul 22 04:57:10 PM PDT 24
Peak memory 164896 kb
Host smart-91fa6aa9-e005-41b4-89b6-b0cd24b33767
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1281326448 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.1281326448
Directory /workspace/35.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.1963116772
Short name T69
Test name
Test status
Simulation time 1481630000 ps
CPU time 3.56 seconds
Started Jul 22 04:57:05 PM PDT 24
Finished Jul 22 04:57:13 PM PDT 24
Peak memory 164944 kb
Host smart-1bcb8b7e-0e80-4298-8fc2-2269692b5db4
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1963116772 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.1963116772
Directory /workspace/36.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.4279410313
Short name T2
Test name
Test status
Simulation time 1523990000 ps
CPU time 5 seconds
Started Jul 22 04:57:00 PM PDT 24
Finished Jul 22 04:57:12 PM PDT 24
Peak memory 164932 kb
Host smart-cfd7e1eb-c563-4672-9bd7-944f7ebef21b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4279410313 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.4279410313
Directory /workspace/37.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.214279601
Short name T32
Test name
Test status
Simulation time 1563290000 ps
CPU time 4.58 seconds
Started Jul 22 04:57:05 PM PDT 24
Finished Jul 22 04:57:15 PM PDT 24
Peak memory 164864 kb
Host smart-5cc75695-064e-469e-823d-e84f3a031721
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=214279601 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.214279601
Directory /workspace/38.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.362026119
Short name T1
Test name
Test status
Simulation time 1514290000 ps
CPU time 3.23 seconds
Started Jul 22 04:57:02 PM PDT 24
Finished Jul 22 04:57:09 PM PDT 24
Peak memory 164864 kb
Host smart-48ea254e-35dd-45d1-9d2d-9b9c55f2bece
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=362026119 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.362026119
Directory /workspace/39.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.1257800350
Short name T54
Test name
Test status
Simulation time 1241810000 ps
CPU time 4.89 seconds
Started Jul 22 04:56:51 PM PDT 24
Finished Jul 22 04:57:02 PM PDT 24
Peak memory 164868 kb
Host smart-e516cb94-9f93-4006-967a-22fd4dace5ca
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1257800350 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.1257800350
Directory /workspace/4.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.3622042931
Short name T57
Test name
Test status
Simulation time 1623610000 ps
CPU time 4.19 seconds
Started Jul 22 04:57:03 PM PDT 24
Finished Jul 22 04:57:13 PM PDT 24
Peak memory 164948 kb
Host smart-03bcae67-1a62-4e6a-9fae-413a05280405
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3622042931 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.3622042931
Directory /workspace/40.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.3362276842
Short name T10
Test name
Test status
Simulation time 1377830000 ps
CPU time 4.58 seconds
Started Jul 22 04:57:02 PM PDT 24
Finished Jul 22 04:57:12 PM PDT 24
Peak memory 164868 kb
Host smart-012e509f-2079-45e6-a521-434f9d5c53a4
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3362276842 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.3362276842
Directory /workspace/41.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.1012074747
Short name T56
Test name
Test status
Simulation time 1467750000 ps
CPU time 4.7 seconds
Started Jul 22 04:57:03 PM PDT 24
Finished Jul 22 04:57:14 PM PDT 24
Peak memory 164920 kb
Host smart-3ed72aa6-2b4d-4944-8fc8-5cab35391266
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1012074747 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.1012074747
Directory /workspace/42.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.1136907513
Short name T39
Test name
Test status
Simulation time 1429050000 ps
CPU time 3.7 seconds
Started Jul 22 04:57:02 PM PDT 24
Finished Jul 22 04:57:11 PM PDT 24
Peak memory 164928 kb
Host smart-7ecbc5b6-8ac4-4ea4-8869-874433764b5a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1136907513 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.1136907513
Directory /workspace/43.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.90767057
Short name T55
Test name
Test status
Simulation time 1581750000 ps
CPU time 5.11 seconds
Started Jul 22 04:57:02 PM PDT 24
Finished Jul 22 04:57:13 PM PDT 24
Peak memory 164872 kb
Host smart-cb8911d7-627b-40dd-9f77-1eb64577f94a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=90767057 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.90767057
Directory /workspace/44.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.3163428672
Short name T58
Test name
Test status
Simulation time 1471950000 ps
CPU time 3.55 seconds
Started Jul 22 04:57:01 PM PDT 24
Finished Jul 22 04:57:10 PM PDT 24
Peak memory 164916 kb
Host smart-1364cef5-3a95-4ef2-bf12-e0f7dd932882
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3163428672 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.3163428672
Directory /workspace/45.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.1431204510
Short name T36
Test name
Test status
Simulation time 1397530000 ps
CPU time 4.63 seconds
Started Jul 22 04:57:01 PM PDT 24
Finished Jul 22 04:57:11 PM PDT 24
Peak memory 164940 kb
Host smart-916e4021-e073-4fb9-8f51-cadb5cee6415
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1431204510 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.1431204510
Directory /workspace/46.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.3682834117
Short name T31
Test name
Test status
Simulation time 1545050000 ps
CPU time 3.41 seconds
Started Jul 22 04:57:10 PM PDT 24
Finished Jul 22 04:57:19 PM PDT 24
Peak memory 164848 kb
Host smart-b8e23bec-fe48-4990-a223-de011592216d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3682834117 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.3682834117
Directory /workspace/47.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.1740820416
Short name T52
Test name
Test status
Simulation time 1395830000 ps
CPU time 2.76 seconds
Started Jul 22 04:57:11 PM PDT 24
Finished Jul 22 04:57:18 PM PDT 24
Peak memory 164680 kb
Host smart-96463e79-b9e1-46b0-9d07-76a87cc5875a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1740820416 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.1740820416
Directory /workspace/48.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.2269902645
Short name T37
Test name
Test status
Simulation time 1350390000 ps
CPU time 3.34 seconds
Started Jul 22 04:57:03 PM PDT 24
Finished Jul 22 04:57:11 PM PDT 24
Peak memory 164848 kb
Host smart-0ab2bd8c-4c00-4c7d-a06d-260d6299ba9e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2269902645 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.2269902645
Directory /workspace/49.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.2832233753
Short name T43
Test name
Test status
Simulation time 1086590000 ps
CPU time 3.7 seconds
Started Jul 22 04:56:51 PM PDT 24
Finished Jul 22 04:56:59 PM PDT 24
Peak memory 164940 kb
Host smart-6c373702-861e-4c5b-ba30-872d93386138
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2832233753 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.2832233753
Directory /workspace/5.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.3175529378
Short name T9
Test name
Test status
Simulation time 1489550000 ps
CPU time 4.03 seconds
Started Jul 22 04:56:59 PM PDT 24
Finished Jul 22 04:57:08 PM PDT 24
Peak memory 164928 kb
Host smart-b05c1a92-f229-49e4-a552-746ec138ba7d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3175529378 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.3175529378
Directory /workspace/6.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.2891451277
Short name T50
Test name
Test status
Simulation time 1520850000 ps
CPU time 5.34 seconds
Started Jul 22 04:56:54 PM PDT 24
Finished Jul 22 04:57:06 PM PDT 24
Peak memory 164920 kb
Host smart-c3b88cc3-6145-4736-85fe-d4db669ba717
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2891451277 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.2891451277
Directory /workspace/7.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.2996907932
Short name T62
Test name
Test status
Simulation time 1477050000 ps
CPU time 4.67 seconds
Started Jul 22 04:56:52 PM PDT 24
Finished Jul 22 04:57:03 PM PDT 24
Peak memory 164944 kb
Host smart-a5607577-4cb2-4f86-853f-f7b124d1a4ea
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2996907932 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.2996907932
Directory /workspace/8.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.1749643793
Short name T53
Test name
Test status
Simulation time 1374630000 ps
CPU time 4.66 seconds
Started Jul 22 04:56:55 PM PDT 24
Finished Jul 22 04:57:06 PM PDT 24
Peak memory 164928 kb
Host smart-3fbd32d2-46a7-4e22-b0bb-ec64b5444ad1
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1749643793 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.1749643793
Directory /workspace/9.prim_lfsr_gal_smoke/latest
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