Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.31 100.00 96.55 100.00 100.00 95.00


Total tests in report: 200
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
87.31 87.31 100.00 100.00 96.55 96.55 100.00 100.00 100.00 100.00 40.00 40.00 /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.2556767600
96.81 9.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 87.50 47.50 /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.2790995015
98.31 1.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 95.00 7.50 /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.4255549225

Tests that do not contribute to grading

Name
/workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.3754929594
/workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.3694265311
/workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.1730215194
/workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.4153768723
/workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.2269575552
/workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.479221051
/workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.961633914
/workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.2465252976
/workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.4099113982
/workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.615547745
/workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.494432296
/workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.694566799
/workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.425117225
/workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.4281575658
/workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.291310656
/workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.3695963174
/workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.2675694631
/workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.438173842
/workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1112550294
/workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.3168698269
/workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.1884081087
/workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.1034127847
/workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.1305203741
/workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3372090134
/workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.2168629121
/workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.1907574788
/workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.2049134993
/workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.1012829121
/workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.3121859838
/workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.3488895258
/workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.1180103853
/workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.4235408973
/workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.1727333754
/workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.4264952166
/workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.2777409350
/workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.1471812818
/workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.1407943601
/workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.841775671
/workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.3086711613
/workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.857615526
/workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.1054223196
/workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.3394783506
/workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.3011424272
/workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.3723478560
/workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.2412034149
/workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.372943713
/workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.2984049308
/workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1268476338
/workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.3695503717
/workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.643952203
/workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.358925982
/workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.951131457
/workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.2413803497
/workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.874287483
/workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.245544148
/workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.4192278305
/workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.2567213615
/workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.1869259041
/workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.1256928771
/workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.924780091
/workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.2424901193
/workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.1615290009
/workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3529154742
/workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.2966660449
/workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.1724143332
/workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.2208395767
/workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.4042441000
/workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.1253767046
/workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.1031090700
/workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.2961168420
/workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.3149564183
/workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.110526034
/workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.265751
/workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.2852346139
/workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.1663630042
/workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.4217743451
/workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.2985426281
/workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.3283898923
/workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.1303588907
/workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.1554857450
/workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.681173345
/workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.2473927953
/workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.1902385016
/workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.153920042
/workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.3279136229
/workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.2037891060
/workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.909820848
/workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.1143948554
/workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.3259198582
/workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.148280958
/workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.3641770187
/workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.4089343551
/workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.47261158
/workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.3245637558
/workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.64507637
/workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.2625183663
/workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.2188394452
/workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.2001892961
/workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.975475411
/workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.2187489520
/workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.2310276599
/workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.511583324
/workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.2821234298
/workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.2597002478
/workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.1100653795
/workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.1166118496
/workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.2537154095
/workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.2579473775
/workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.1260262332
/workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.1794619040
/workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.4051213028
/workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.2766948453
/workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.1967791103
/workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.1186344997
/workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.1077200681
/workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.1781355130
/workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.1907544261
/workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.3685169925
/workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.776598956
/workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.4245413780
/workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.2622502880
/workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.3260769105
/workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.142977057
/workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.674806858
/workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.202551186
/workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.1327822189
/workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.4165903288
/workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.1018281891
/workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.1414030781
/workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.4222846778
/workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.1216589873
/workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.26773452
/workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.4007007574
/workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.3009875460
/workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.1919755606
/workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.3618656584
/workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1144430100
/workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.357379610
/workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.2758709326
/workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.3850427032
/workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.925169673
/workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.3929014029
/workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.3145186310
/workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.2818850120
/workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.4207664582
/workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.3495204314
/workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.4119105112
/workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.1149100336
/workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.2335361387
/workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.785024439
/workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.659210722
/workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.3766752339
/workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.1836321444
/workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.3901845223
/workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.3353623923
/workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.271091838
/workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.962616238
/workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.3257534388
/workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.3746797943
/workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.4264502186
/workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.2973034738
/workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.3876299843
/workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.3594248564
/workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.693828809
/workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.62307668
/workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.2792285269
/workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.675841557
/workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.3673082703
/workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.806334362
/workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.18279570
/workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.2919846241
/workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.1994980621
/workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.3410738225
/workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.4170168300
/workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.4224514108
/workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.2257750540
/workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.1108136956
/workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.2685463516
/workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.3032338968
/workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.812896281
/workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.1267861135
/workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.2424906731
/workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.772553458
/workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.2138291425
/workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.1545152038
/workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.1623240469
/workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.518017470
/workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.1680670135
/workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.3721037016
/workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.631914954
/workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.322140280
/workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.3555752253
/workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.3385815673
/workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.1273833364
/workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.286430120
/workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.909404128
/workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.1058515725



Total test records in report: 200
tests.html | tests1.html | tests2.html | tests3.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.2556767600 Jul 23 05:18:05 PM PDT 24 Jul 23 05:18:16 PM PDT 24 1297270000 ps
T2 /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.3385815673 Jul 23 05:18:04 PM PDT 24 Jul 23 05:18:13 PM PDT 24 1121990000 ps
T3 /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.675841557 Jul 23 05:18:16 PM PDT 24 Jul 23 05:18:28 PM PDT 24 1471050000 ps
T7 /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.962616238 Jul 23 05:18:13 PM PDT 24 Jul 23 05:18:25 PM PDT 24 1507070000 ps
T8 /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.3766752339 Jul 23 05:18:05 PM PDT 24 Jul 23 05:18:17 PM PDT 24 1405670000 ps
T9 /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.3746797943 Jul 23 05:18:10 PM PDT 24 Jul 23 05:18:20 PM PDT 24 1584910000 ps
T10 /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.1108136956 Jul 23 05:18:12 PM PDT 24 Jul 23 05:18:22 PM PDT 24 1506850000 ps
T11 /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.2919846241 Jul 23 05:18:05 PM PDT 24 Jul 23 05:18:18 PM PDT 24 1237050000 ps
T12 /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.18279570 Jul 23 05:18:12 PM PDT 24 Jul 23 05:18:26 PM PDT 24 1557570000 ps
T13 /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.631914954 Jul 23 05:18:21 PM PDT 24 Jul 23 05:18:34 PM PDT 24 1596090000 ps
T31 /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.2685463516 Jul 23 05:18:14 PM PDT 24 Jul 23 05:18:27 PM PDT 24 1446370000 ps
T32 /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.785024439 Jul 23 05:18:03 PM PDT 24 Jul 23 05:18:13 PM PDT 24 1304170000 ps
T33 /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.271091838 Jul 23 05:18:13 PM PDT 24 Jul 23 05:18:24 PM PDT 24 1436770000 ps
T34 /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.1545152038 Jul 23 05:18:20 PM PDT 24 Jul 23 05:18:31 PM PDT 24 1300210000 ps
T35 /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.518017470 Jul 23 05:18:21 PM PDT 24 Jul 23 05:18:34 PM PDT 24 1570490000 ps
T36 /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.1267861135 Jul 23 05:18:16 PM PDT 24 Jul 23 05:18:25 PM PDT 24 1438150000 ps
T37 /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.3721037016 Jul 23 05:18:21 PM PDT 24 Jul 23 05:18:33 PM PDT 24 1418270000 ps
T38 /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.806334362 Jul 23 05:18:13 PM PDT 24 Jul 23 05:18:26 PM PDT 24 1555850000 ps
T39 /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.2792285269 Jul 23 05:18:11 PM PDT 24 Jul 23 05:18:21 PM PDT 24 1144570000 ps
T40 /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.4264502186 Jul 23 05:18:03 PM PDT 24 Jul 23 05:18:13 PM PDT 24 1434050000 ps
T41 /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.659210722 Jul 23 05:18:06 PM PDT 24 Jul 23 05:18:17 PM PDT 24 1504390000 ps
T42 /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.3032338968 Jul 23 05:18:14 PM PDT 24 Jul 23 05:18:27 PM PDT 24 1425070000 ps
T43 /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.3257534388 Jul 23 05:18:16 PM PDT 24 Jul 23 05:18:28 PM PDT 24 1460210000 ps
T44 /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.3410738225 Jul 23 05:18:17 PM PDT 24 Jul 23 05:18:27 PM PDT 24 1517430000 ps
T45 /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.812896281 Jul 23 05:18:12 PM PDT 24 Jul 23 05:18:21 PM PDT 24 1500010000 ps
T46 /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.2335361387 Jul 23 05:18:04 PM PDT 24 Jul 23 05:18:17 PM PDT 24 1462670000 ps
T47 /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.2257750540 Jul 23 05:18:16 PM PDT 24 Jul 23 05:18:29 PM PDT 24 1548590000 ps
T48 /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.286430120 Jul 23 05:18:04 PM PDT 24 Jul 23 05:18:15 PM PDT 24 1372850000 ps
T49 /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.1994980621 Jul 23 05:18:12 PM PDT 24 Jul 23 05:18:22 PM PDT 24 1377130000 ps
T50 /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.3673082703 Jul 23 05:18:13 PM PDT 24 Jul 23 05:18:26 PM PDT 24 1382270000 ps
T51 /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.3901845223 Jul 23 05:18:14 PM PDT 24 Jul 23 05:18:23 PM PDT 24 1426590000 ps
T52 /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.1836321444 Jul 23 05:18:17 PM PDT 24 Jul 23 05:18:26 PM PDT 24 1518230000 ps
T53 /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.772553458 Jul 23 05:18:14 PM PDT 24 Jul 23 05:18:24 PM PDT 24 1491170000 ps
T54 /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.1680670135 Jul 23 05:18:21 PM PDT 24 Jul 23 05:18:31 PM PDT 24 1567070000 ps
T55 /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.1273833364 Jul 23 05:18:03 PM PDT 24 Jul 23 05:18:13 PM PDT 24 1329730000 ps
T56 /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.4224514108 Jul 23 05:18:12 PM PDT 24 Jul 23 05:18:26 PM PDT 24 1481530000 ps
T57 /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.1058515725 Jul 23 05:18:04 PM PDT 24 Jul 23 05:18:14 PM PDT 24 1307810000 ps
T58 /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.693828809 Jul 23 05:18:14 PM PDT 24 Jul 23 05:18:26 PM PDT 24 1155370000 ps
T59 /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.2973034738 Jul 23 05:18:11 PM PDT 24 Jul 23 05:18:25 PM PDT 24 1513730000 ps
T60 /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.2424906731 Jul 23 05:18:04 PM PDT 24 Jul 23 05:18:15 PM PDT 24 1291290000 ps
T61 /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.3555752253 Jul 23 05:18:20 PM PDT 24 Jul 23 05:18:34 PM PDT 24 1567770000 ps
T62 /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.322140280 Jul 23 05:18:19 PM PDT 24 Jul 23 05:18:33 PM PDT 24 1502830000 ps
T63 /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.3353623923 Jul 23 05:18:14 PM PDT 24 Jul 23 05:18:24 PM PDT 24 1577710000 ps
T64 /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.2138291425 Jul 23 05:18:22 PM PDT 24 Jul 23 05:18:31 PM PDT 24 1495610000 ps
T65 /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.4170168300 Jul 23 05:18:12 PM PDT 24 Jul 23 05:18:24 PM PDT 24 1556750000 ps
T66 /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.3876299843 Jul 23 05:18:17 PM PDT 24 Jul 23 05:18:26 PM PDT 24 1391550000 ps
T67 /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.909404128 Jul 23 05:18:06 PM PDT 24 Jul 23 05:18:16 PM PDT 24 1354010000 ps
T68 /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.62307668 Jul 23 05:18:12 PM PDT 24 Jul 23 05:18:23 PM PDT 24 1493510000 ps
T69 /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.3594248564 Jul 23 05:18:16 PM PDT 24 Jul 23 05:18:26 PM PDT 24 1516810000 ps
T70 /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.1623240469 Jul 23 05:18:20 PM PDT 24 Jul 23 05:18:29 PM PDT 24 1588870000 ps
T4 /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.2412034149 Jul 23 05:17:45 PM PDT 24 Jul 23 05:50:17 PM PDT 24 336618930000 ps
T5 /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.4153768723 Jul 23 05:17:45 PM PDT 24 Jul 23 05:48:27 PM PDT 24 336436030000 ps
T6 /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.1884081087 Jul 23 05:17:55 PM PDT 24 Jul 23 05:49:16 PM PDT 24 336583910000 ps
T14 /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.3695963174 Jul 23 05:17:53 PM PDT 24 Jul 23 05:47:26 PM PDT 24 336599630000 ps
T15 /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.2269575552 Jul 23 05:17:44 PM PDT 24 Jul 23 05:47:40 PM PDT 24 336378190000 ps
T16 /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1112550294 Jul 23 05:17:55 PM PDT 24 Jul 23 05:51:20 PM PDT 24 336414250000 ps
T17 /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.2790995015 Jul 23 05:17:46 PM PDT 24 Jul 23 05:45:57 PM PDT 24 337009330000 ps
T18 /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.3121859838 Jul 23 05:17:55 PM PDT 24 Jul 23 05:48:39 PM PDT 24 336498330000 ps
T19 /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.1305203741 Jul 23 05:17:46 PM PDT 24 Jul 23 05:51:16 PM PDT 24 336726590000 ps
T20 /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.425117225 Jul 23 05:17:55 PM PDT 24 Jul 23 05:50:58 PM PDT 24 336802450000 ps
T71 /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.479221051 Jul 23 05:17:46 PM PDT 24 Jul 23 05:47:12 PM PDT 24 336355790000 ps
T72 /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.615547745 Jul 23 05:17:55 PM PDT 24 Jul 23 05:48:18 PM PDT 24 336460670000 ps
T73 /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.438173842 Jul 23 05:17:54 PM PDT 24 Jul 23 05:53:17 PM PDT 24 337032010000 ps
T74 /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.4264952166 Jul 23 05:17:44 PM PDT 24 Jul 23 05:44:20 PM PDT 24 336351150000 ps
T75 /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.857615526 Jul 23 05:18:03 PM PDT 24 Jul 23 05:48:45 PM PDT 24 336958730000 ps
T76 /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.4281575658 Jul 23 05:17:54 PM PDT 24 Jul 23 05:54:56 PM PDT 24 336580570000 ps
T77 /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.3168698269 Jul 23 05:17:55 PM PDT 24 Jul 23 05:47:41 PM PDT 24 336721330000 ps
T78 /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.1012829121 Jul 23 05:17:54 PM PDT 24 Jul 23 05:49:18 PM PDT 24 336980870000 ps
T79 /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.4099113982 Jul 23 05:17:56 PM PDT 24 Jul 23 05:46:02 PM PDT 24 336500250000 ps
T80 /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.3086711613 Jul 23 05:18:04 PM PDT 24 Jul 23 05:49:33 PM PDT 24 336550590000 ps
T81 /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.1907574788 Jul 23 05:17:54 PM PDT 24 Jul 23 05:52:17 PM PDT 24 336867130000 ps
T82 /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.961633914 Jul 23 05:17:46 PM PDT 24 Jul 23 05:47:23 PM PDT 24 336450430000 ps
T83 /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.2465252976 Jul 23 05:17:44 PM PDT 24 Jul 23 05:53:08 PM PDT 24 336791770000 ps
T84 /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.3488895258 Jul 23 05:17:55 PM PDT 24 Jul 23 05:49:08 PM PDT 24 336508570000 ps
T85 /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.3754929594 Jul 23 05:17:36 PM PDT 24 Jul 23 05:47:37 PM PDT 24 336923210000 ps
T86 /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.494432296 Jul 23 05:17:54 PM PDT 24 Jul 23 05:50:19 PM PDT 24 336430490000 ps
T87 /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.372943713 Jul 23 05:17:45 PM PDT 24 Jul 23 05:46:20 PM PDT 24 336367390000 ps
T88 /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.2984049308 Jul 23 05:17:47 PM PDT 24 Jul 23 05:53:37 PM PDT 24 337054870000 ps
T89 /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3372090134 Jul 23 05:17:53 PM PDT 24 Jul 23 05:50:34 PM PDT 24 336598630000 ps
T90 /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1268476338 Jul 23 05:17:46 PM PDT 24 Jul 23 05:50:20 PM PDT 24 336320590000 ps
T91 /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.2675694631 Jul 23 05:17:53 PM PDT 24 Jul 23 05:47:06 PM PDT 24 336490370000 ps
T92 /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.2168629121 Jul 23 05:17:55 PM PDT 24 Jul 23 05:49:07 PM PDT 24 337018550000 ps
T93 /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.1727333754 Jul 23 05:17:56 PM PDT 24 Jul 23 05:44:00 PM PDT 24 336792530000 ps
T94 /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.1471812818 Jul 23 05:17:55 PM PDT 24 Jul 23 05:50:14 PM PDT 24 336579030000 ps
T95 /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.2777409350 Jul 23 05:17:56 PM PDT 24 Jul 23 05:43:36 PM PDT 24 336318010000 ps
T96 /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.2049134993 Jul 23 05:17:54 PM PDT 24 Jul 23 05:51:26 PM PDT 24 336483870000 ps
T97 /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.1054223196 Jul 23 05:18:06 PM PDT 24 Jul 23 05:47:28 PM PDT 24 336334710000 ps
T98 /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.3694265311 Jul 23 05:17:34 PM PDT 24 Jul 23 05:49:48 PM PDT 24 336642450000 ps
T99 /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.291310656 Jul 23 05:17:53 PM PDT 24 Jul 23 05:47:39 PM PDT 24 336442170000 ps
T100 /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.3011424272 Jul 23 05:18:05 PM PDT 24 Jul 23 05:48:25 PM PDT 24 336469790000 ps
T101 /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.694566799 Jul 23 05:17:31 PM PDT 24 Jul 23 05:43:12 PM PDT 24 336628830000 ps
T102 /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.1180103853 Jul 23 05:17:55 PM PDT 24 Jul 23 05:47:42 PM PDT 24 336832410000 ps
T103 /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.1407943601 Jul 23 05:18:04 PM PDT 24 Jul 23 05:54:24 PM PDT 24 337033050000 ps
T104 /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.4235408973 Jul 23 05:17:57 PM PDT 24 Jul 23 05:48:43 PM PDT 24 336839990000 ps
T105 /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.3394783506 Jul 23 05:18:03 PM PDT 24 Jul 23 05:50:40 PM PDT 24 337023110000 ps
T106 /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.1034127847 Jul 23 05:17:54 PM PDT 24 Jul 23 05:50:19 PM PDT 24 337050030000 ps
T107 /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.841775671 Jul 23 05:18:03 PM PDT 24 Jul 23 05:48:43 PM PDT 24 337112530000 ps
T108 /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.3723478560 Jul 23 05:18:05 PM PDT 24 Jul 23 05:53:09 PM PDT 24 336661130000 ps
T109 /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.1730215194 Jul 23 05:17:46 PM PDT 24 Jul 23 05:46:28 PM PDT 24 337002830000 ps
T110 /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.3695503717 Jul 23 05:17:48 PM PDT 24 Jul 23 05:51:10 PM PDT 24 336619730000 ps
T111 /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.1781355130 Jul 23 04:38:07 PM PDT 24 Jul 23 04:38:17 PM PDT 24 1557190000 ps
T112 /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.2818850120 Jul 23 04:37:59 PM PDT 24 Jul 23 04:38:06 PM PDT 24 1434250000 ps
T113 /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.2187489520 Jul 23 04:38:05 PM PDT 24 Jul 23 04:38:14 PM PDT 24 1551010000 ps
T114 /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.2537154095 Jul 23 04:38:08 PM PDT 24 Jul 23 04:38:18 PM PDT 24 1509510000 ps
T115 /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.1907544261 Jul 23 04:38:04 PM PDT 24 Jul 23 04:38:13 PM PDT 24 1153830000 ps
T116 /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.1018281891 Jul 23 04:38:04 PM PDT 24 Jul 23 04:38:12 PM PDT 24 1197230000 ps
T117 /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.2310276599 Jul 23 04:38:03 PM PDT 24 Jul 23 04:38:13 PM PDT 24 1393850000 ps
T118 /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.3685169925 Jul 23 04:38:06 PM PDT 24 Jul 23 04:38:16 PM PDT 24 1514450000 ps
T119 /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.3495204314 Jul 23 04:38:04 PM PDT 24 Jul 23 04:38:14 PM PDT 24 1369210000 ps
T120 /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.4007007574 Jul 23 04:38:02 PM PDT 24 Jul 23 04:38:12 PM PDT 24 1533270000 ps
T121 /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.357379610 Jul 23 04:39:08 PM PDT 24 Jul 23 04:39:17 PM PDT 24 1418050000 ps
T122 /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.1967791103 Jul 23 04:38:02 PM PDT 24 Jul 23 04:38:13 PM PDT 24 1470650000 ps
T123 /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.4245413780 Jul 23 04:38:05 PM PDT 24 Jul 23 04:38:17 PM PDT 24 1475690000 ps
T124 /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.1260262332 Jul 23 04:38:05 PM PDT 24 Jul 23 04:38:14 PM PDT 24 1363870000 ps
T125 /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1144430100 Jul 23 04:39:08 PM PDT 24 Jul 23 04:39:18 PM PDT 24 1643970000 ps
T126 /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.925169673 Jul 23 04:38:01 PM PDT 24 Jul 23 04:38:13 PM PDT 24 1573610000 ps
T127 /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.3009875460 Jul 23 04:39:08 PM PDT 24 Jul 23 04:39:16 PM PDT 24 1357670000 ps
T128 /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.1149100336 Jul 23 04:38:02 PM PDT 24 Jul 23 04:38:11 PM PDT 24 1457090000 ps
T129 /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.1327822189 Jul 23 04:38:05 PM PDT 24 Jul 23 04:38:26 PM PDT 24 1484770000 ps
T130 /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.3145186310 Jul 23 04:38:05 PM PDT 24 Jul 23 04:38:14 PM PDT 24 1422210000 ps
T131 /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.2597002478 Jul 23 04:38:05 PM PDT 24 Jul 23 04:38:16 PM PDT 24 1506630000 ps
T132 /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.1216589873 Jul 23 04:38:03 PM PDT 24 Jul 23 04:38:13 PM PDT 24 1489050000 ps
T133 /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.2579473775 Jul 23 04:38:02 PM PDT 24 Jul 23 04:38:13 PM PDT 24 1487150000 ps
T134 /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.2622502880 Jul 23 04:38:02 PM PDT 24 Jul 23 04:38:10 PM PDT 24 1271350000 ps
T135 /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.3618656584 Jul 23 04:38:05 PM PDT 24 Jul 23 04:38:17 PM PDT 24 1442450000 ps
T136 /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.4222846778 Jul 23 04:38:04 PM PDT 24 Jul 23 04:38:21 PM PDT 24 1515210000 ps
T137 /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.202551186 Jul 23 04:38:03 PM PDT 24 Jul 23 04:38:12 PM PDT 24 1239710000 ps
T138 /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.1166118496 Jul 23 04:38:02 PM PDT 24 Jul 23 04:38:12 PM PDT 24 1436910000 ps
T139 /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.3850427032 Jul 23 04:38:05 PM PDT 24 Jul 23 04:38:17 PM PDT 24 1488430000 ps
T140 /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.1100653795 Jul 23 04:38:01 PM PDT 24 Jul 23 04:38:12 PM PDT 24 1385790000 ps
T141 /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.1919755606 Jul 23 04:39:25 PM PDT 24 Jul 23 04:39:33 PM PDT 24 1518030000 ps
T142 /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.142977057 Jul 23 04:38:05 PM PDT 24 Jul 23 04:38:15 PM PDT 24 1580090000 ps
T143 /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.3929014029 Jul 23 04:38:00 PM PDT 24 Jul 23 04:38:11 PM PDT 24 1441430000 ps
T144 /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.511583324 Jul 23 04:38:04 PM PDT 24 Jul 23 04:38:14 PM PDT 24 1435730000 ps
T145 /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.26773452 Jul 23 04:38:04 PM PDT 24 Jul 23 04:38:14 PM PDT 24 1574070000 ps
T146 /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.4119105112 Jul 23 04:38:03 PM PDT 24 Jul 23 04:38:11 PM PDT 24 1359010000 ps
T147 /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.2758709326 Jul 23 04:39:08 PM PDT 24 Jul 23 04:39:17 PM PDT 24 1407470000 ps
T148 /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.4207664582 Jul 23 04:38:04 PM PDT 24 Jul 23 04:38:14 PM PDT 24 1605570000 ps
T149 /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.4165903288 Jul 23 04:38:06 PM PDT 24 Jul 23 04:38:16 PM PDT 24 1551110000 ps
T150 /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.975475411 Jul 23 04:38:06 PM PDT 24 Jul 23 04:38:17 PM PDT 24 1462510000 ps
T151 /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.1077200681 Jul 23 04:38:03 PM PDT 24 Jul 23 04:38:11 PM PDT 24 1396270000 ps
T152 /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.1186344997 Jul 23 04:38:03 PM PDT 24 Jul 23 04:38:13 PM PDT 24 1418790000 ps
T153 /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.776598956 Jul 23 04:38:03 PM PDT 24 Jul 23 04:38:12 PM PDT 24 1467930000 ps
T154 /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.674806858 Jul 23 04:38:04 PM PDT 24 Jul 23 04:38:14 PM PDT 24 1456970000 ps
T155 /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.2766948453 Jul 23 04:38:04 PM PDT 24 Jul 23 04:38:14 PM PDT 24 1432770000 ps
T156 /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.2821234298 Jul 23 04:38:06 PM PDT 24 Jul 23 04:38:18 PM PDT 24 1531870000 ps
T157 /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.3260769105 Jul 23 04:38:05 PM PDT 24 Jul 23 04:38:17 PM PDT 24 1580790000 ps
T158 /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.1794619040 Jul 23 04:38:04 PM PDT 24 Jul 23 04:38:14 PM PDT 24 1573750000 ps
T159 /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.1414030781 Jul 23 04:38:02 PM PDT 24 Jul 23 04:38:12 PM PDT 24 1317030000 ps
T160 /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.4051213028 Jul 23 04:38:01 PM PDT 24 Jul 23 04:38:09 PM PDT 24 1246270000 ps
T21 /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.2001892961 Jul 23 04:39:59 PM PDT 24 Jul 23 05:11:30 PM PDT 24 336506270000 ps
T22 /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.2852346139 Jul 23 04:40:13 PM PDT 24 Jul 23 05:09:50 PM PDT 24 336947410000 ps
T23 /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.265751 Jul 23 04:40:12 PM PDT 24 Jul 23 05:17:47 PM PDT 24 336466290000 ps
T24 /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.4255549225 Jul 23 04:39:57 PM PDT 24 Jul 23 05:16:44 PM PDT 24 336489670000 ps
T25 /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.909820848 Jul 23 04:40:11 PM PDT 24 Jul 23 05:19:42 PM PDT 24 336404310000 ps
T26 /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.4089343551 Jul 23 04:40:11 PM PDT 24 Jul 23 05:09:53 PM PDT 24 336309790000 ps
T27 /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.110526034 Jul 23 04:39:57 PM PDT 24 Jul 23 05:08:42 PM PDT 24 336919910000 ps
T28 /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.681173345 Jul 23 04:40:12 PM PDT 24 Jul 23 05:09:10 PM PDT 24 337004630000 ps
T29 /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.3283898923 Jul 23 04:40:19 PM PDT 24 Jul 23 05:14:51 PM PDT 24 336778390000 ps
T30 /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.3149564183 Jul 23 04:40:10 PM PDT 24 Jul 23 05:10:03 PM PDT 24 336727770000 ps
T161 /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.1253767046 Jul 23 04:40:13 PM PDT 24 Jul 23 05:08:38 PM PDT 24 337070150000 ps
T162 /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.358925982 Jul 23 04:39:58 PM PDT 24 Jul 23 05:09:02 PM PDT 24 337018950000 ps
T163 /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.924780091 Jul 23 04:40:10 PM PDT 24 Jul 23 05:13:47 PM PDT 24 337017150000 ps
T164 /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.3259198582 Jul 23 04:40:09 PM PDT 24 Jul 23 05:16:39 PM PDT 24 336738130000 ps
T165 /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.3641770187 Jul 23 04:40:10 PM PDT 24 Jul 23 05:06:38 PM PDT 24 336721370000 ps
T166 /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.1554857450 Jul 23 04:40:11 PM PDT 24 Jul 23 05:19:45 PM PDT 24 336631470000 ps
T167 /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.148280958 Jul 23 04:40:15 PM PDT 24 Jul 23 05:10:52 PM PDT 24 336819250000 ps
T168 /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.4042441000 Jul 23 04:40:14 PM PDT 24 Jul 23 05:07:55 PM PDT 24 336901650000 ps
T169 /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.2985426281 Jul 23 04:40:09 PM PDT 24 Jul 23 05:12:52 PM PDT 24 336688170000 ps
T170 /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.1663630042 Jul 23 04:40:10 PM PDT 24 Jul 23 05:20:09 PM PDT 24 336367690000 ps
T171 /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.2208395767 Jul 23 04:40:10 PM PDT 24 Jul 23 05:10:23 PM PDT 24 337112850000 ps
T172 /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.64507637 Jul 23 04:39:59 PM PDT 24 Jul 23 05:14:13 PM PDT 24 336469530000 ps
T173 /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.2966660449 Jul 23 04:40:10 PM PDT 24 Jul 23 05:12:49 PM PDT 24 336354070000 ps
T174 /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.245544148 Jul 23 04:40:03 PM PDT 24 Jul 23 05:10:47 PM PDT 24 336591850000 ps
T175 /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.1303588907 Jul 23 04:40:13 PM PDT 24 Jul 23 05:09:18 PM PDT 24 336866410000 ps
T176 /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.1143948554 Jul 23 04:40:19 PM PDT 24 Jul 23 05:15:44 PM PDT 24 336524330000 ps
T177 /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.1256928771 Jul 23 04:40:13 PM PDT 24 Jul 23 05:17:57 PM PDT 24 336725630000 ps
T178 /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.153920042 Jul 23 04:40:10 PM PDT 24 Jul 23 05:15:18 PM PDT 24 336975310000 ps
T179 /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.951131457 Jul 23 04:39:59 PM PDT 24 Jul 23 05:12:06 PM PDT 24 336729970000 ps
T180 /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.2424901193 Jul 23 04:39:57 PM PDT 24 Jul 23 05:15:41 PM PDT 24 337003070000 ps
T181 /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.1869259041 Jul 23 04:40:11 PM PDT 24 Jul 23 05:10:28 PM PDT 24 336602370000 ps
T182 /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.1902385016 Jul 23 04:39:58 PM PDT 24 Jul 23 05:16:35 PM PDT 24 336738290000 ps
T183 /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.2188394452 Jul 23 04:40:03 PM PDT 24 Jul 23 05:12:14 PM PDT 24 336968310000 ps
T184 /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.1031090700 Jul 23 04:40:12 PM PDT 24 Jul 23 05:11:56 PM PDT 24 336733270000 ps
T185 /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.2567213615 Jul 23 04:40:09 PM PDT 24 Jul 23 05:08:20 PM PDT 24 336426770000 ps
T186 /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.3279136229 Jul 23 04:40:11 PM PDT 24 Jul 23 05:09:53 PM PDT 24 336575510000 ps
T187 /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.2413803497 Jul 23 04:39:56 PM PDT 24 Jul 23 05:07:26 PM PDT 24 336726110000 ps
T188 /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.2961168420 Jul 23 04:40:14 PM PDT 24 Jul 23 05:10:42 PM PDT 24 336539930000 ps
T189 /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.3245637558 Jul 23 04:39:59 PM PDT 24 Jul 23 05:06:11 PM PDT 24 336446450000 ps
T190 /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.47261158 Jul 23 04:40:10 PM PDT 24 Jul 23 05:06:41 PM PDT 24 336371810000 ps
T191 /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.1615290009 Jul 23 04:40:08 PM PDT 24 Jul 23 05:10:26 PM PDT 24 336826470000 ps
T192 /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.2037891060 Jul 23 04:40:15 PM PDT 24 Jul 23 05:12:00 PM PDT 24 336783510000 ps
T193 /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.643952203 Jul 23 04:40:00 PM PDT 24 Jul 23 05:14:10 PM PDT 24 336802390000 ps
T194 /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.2625183663 Jul 23 04:40:00 PM PDT 24 Jul 23 05:16:26 PM PDT 24 336269190000 ps
T195 /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.874287483 Jul 23 04:39:58 PM PDT 24 Jul 23 05:11:54 PM PDT 24 336885690000 ps
T196 /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3529154742 Jul 23 04:40:11 PM PDT 24 Jul 23 05:06:36 PM PDT 24 336729370000 ps
T197 /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.1724143332 Jul 23 04:40:16 PM PDT 24 Jul 23 05:14:45 PM PDT 24 336949010000 ps
T198 /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.2473927953 Jul 23 04:40:13 PM PDT 24 Jul 23 05:06:49 PM PDT 24 336819470000 ps
T199 /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.4217743451 Jul 23 04:40:09 PM PDT 24 Jul 23 05:12:35 PM PDT 24 336425110000 ps
T200 /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.4192278305 Jul 23 04:40:11 PM PDT 24 Jul 23 05:10:11 PM PDT 24 336615530000 ps

Test location /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.2556767600
Short name T1
Test name
Test status
Simulation time 1297270000 ps
CPU time 4.87 seconds
Started Jul 23 05:18:05 PM PDT 24
Finished Jul 23 05:18:16 PM PDT 24
Peak memory 164908 kb
Host smart-c3c469c6-a4e2-401f-bdab-a5e0c6d828ab
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2556767600 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.2556767600
Directory /workspace/1.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.2790995015
Short name T17
Test name
Test status
Simulation time 337009330000 ps
CPU time 685.16 seconds
Started Jul 23 05:17:46 PM PDT 24
Finished Jul 23 05:45:57 PM PDT 24
Peak memory 160796 kb
Host smart-a0ddd6cd-23fc-48e0-a3ac-bc0a875a2635
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2790995015 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.2790995015
Directory /workspace/11.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.4255549225
Short name T24
Test name
Test status
Simulation time 336489670000 ps
CPU time 887.58 seconds
Started Jul 23 04:39:57 PM PDT 24
Finished Jul 23 05:16:44 PM PDT 24
Peak memory 160728 kb
Host smart-5085183e-5a2b-4fc1-89c6-61838d3127d4
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4255549225 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.4255549225
Directory /workspace/11.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.3754929594
Short name T85
Test name
Test status
Simulation time 336923210000 ps
CPU time 741.2 seconds
Started Jul 23 05:17:36 PM PDT 24
Finished Jul 23 05:47:37 PM PDT 24
Peak memory 160744 kb
Host smart-4a1e7b04-f7a9-4828-bd70-6531aff66872
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3754929594 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.3754929594
Directory /workspace/0.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.3694265311
Short name T98
Test name
Test status
Simulation time 336642450000 ps
CPU time 768.7 seconds
Started Jul 23 05:17:34 PM PDT 24
Finished Jul 23 05:49:48 PM PDT 24
Peak memory 160716 kb
Host smart-9d390ffa-0135-440a-ade1-7ebe0bcfc5ca
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3694265311 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.3694265311
Directory /workspace/1.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.1730215194
Short name T109
Test name
Test status
Simulation time 337002830000 ps
CPU time 703.36 seconds
Started Jul 23 05:17:46 PM PDT 24
Finished Jul 23 05:46:28 PM PDT 24
Peak memory 160752 kb
Host smart-f43c7384-9e39-4520-a5f9-006c7cc29379
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1730215194 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.1730215194
Directory /workspace/10.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.4153768723
Short name T5
Test name
Test status
Simulation time 336436030000 ps
CPU time 750.13 seconds
Started Jul 23 05:17:45 PM PDT 24
Finished Jul 23 05:48:27 PM PDT 24
Peak memory 160784 kb
Host smart-547aefaf-cb4d-4b01-b387-e98ddaa8e809
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4153768723 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.4153768723
Directory /workspace/12.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.2269575552
Short name T15
Test name
Test status
Simulation time 336378190000 ps
CPU time 737.04 seconds
Started Jul 23 05:17:44 PM PDT 24
Finished Jul 23 05:47:40 PM PDT 24
Peak memory 160816 kb
Host smart-72c41b68-9bbe-4e8a-b18f-d31147c5f393
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2269575552 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.2269575552
Directory /workspace/13.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.479221051
Short name T71
Test name
Test status
Simulation time 336355790000 ps
CPU time 724.81 seconds
Started Jul 23 05:17:46 PM PDT 24
Finished Jul 23 05:47:12 PM PDT 24
Peak memory 160916 kb
Host smart-83629ade-2aa1-44cd-ba2c-ea370410c815
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=479221051 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.479221051
Directory /workspace/14.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.961633914
Short name T82
Test name
Test status
Simulation time 336450430000 ps
CPU time 719.69 seconds
Started Jul 23 05:17:46 PM PDT 24
Finished Jul 23 05:47:23 PM PDT 24
Peak memory 160772 kb
Host smart-4aac1b66-ae06-40dd-834b-07e9c9406235
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=961633914 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.961633914
Directory /workspace/15.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.2465252976
Short name T83
Test name
Test status
Simulation time 336791770000 ps
CPU time 869.74 seconds
Started Jul 23 05:17:44 PM PDT 24
Finished Jul 23 05:53:08 PM PDT 24
Peak memory 160772 kb
Host smart-de54a3df-38a4-49ae-8ccc-7eb31f9677dc
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2465252976 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.2465252976
Directory /workspace/16.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.4099113982
Short name T79
Test name
Test status
Simulation time 336500250000 ps
CPU time 678.52 seconds
Started Jul 23 05:17:56 PM PDT 24
Finished Jul 23 05:46:02 PM PDT 24
Peak memory 160796 kb
Host smart-e16d8bb5-0221-4e5c-9a5f-946bfdba3455
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4099113982 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.4099113982
Directory /workspace/17.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.615547745
Short name T72
Test name
Test status
Simulation time 336460670000 ps
CPU time 722.52 seconds
Started Jul 23 05:17:55 PM PDT 24
Finished Jul 23 05:48:18 PM PDT 24
Peak memory 160812 kb
Host smart-2091e04a-b95e-401c-bcc5-eb11086d134f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=615547745 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.615547745
Directory /workspace/18.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.494432296
Short name T86
Test name
Test status
Simulation time 336430490000 ps
CPU time 795 seconds
Started Jul 23 05:17:54 PM PDT 24
Finished Jul 23 05:50:19 PM PDT 24
Peak memory 160796 kb
Host smart-527b514e-45eb-4110-a39a-eb72732bf05f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=494432296 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.494432296
Directory /workspace/19.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.694566799
Short name T101
Test name
Test status
Simulation time 336628830000 ps
CPU time 619.49 seconds
Started Jul 23 05:17:31 PM PDT 24
Finished Jul 23 05:43:12 PM PDT 24
Peak memory 160700 kb
Host smart-32e2b775-8d42-40ac-b2de-5f46ecac8e81
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=694566799 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.694566799
Directory /workspace/2.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.425117225
Short name T20
Test name
Test status
Simulation time 336802450000 ps
CPU time 815.79 seconds
Started Jul 23 05:17:55 PM PDT 24
Finished Jul 23 05:50:58 PM PDT 24
Peak memory 160740 kb
Host smart-98548adf-c0c6-4531-9895-63a806f484c3
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=425117225 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.425117225
Directory /workspace/20.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.4281575658
Short name T76
Test name
Test status
Simulation time 336580570000 ps
CPU time 935.1 seconds
Started Jul 23 05:17:54 PM PDT 24
Finished Jul 23 05:54:56 PM PDT 24
Peak memory 160776 kb
Host smart-ff71f852-7372-449b-9d2c-c44ea327c02c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4281575658 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.4281575658
Directory /workspace/21.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.291310656
Short name T99
Test name
Test status
Simulation time 336442170000 ps
CPU time 730.25 seconds
Started Jul 23 05:17:53 PM PDT 24
Finished Jul 23 05:47:39 PM PDT 24
Peak memory 160732 kb
Host smart-bec5d74c-c760-4419-b0c6-5c780dc86b96
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=291310656 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.291310656
Directory /workspace/22.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.3695963174
Short name T14
Test name
Test status
Simulation time 336599630000 ps
CPU time 732.18 seconds
Started Jul 23 05:17:53 PM PDT 24
Finished Jul 23 05:47:26 PM PDT 24
Peak memory 160752 kb
Host smart-c061cc3d-2bdc-4675-8354-004d8788f935
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3695963174 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.3695963174
Directory /workspace/23.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.2675694631
Short name T91
Test name
Test status
Simulation time 336490370000 ps
CPU time 712.24 seconds
Started Jul 23 05:17:53 PM PDT 24
Finished Jul 23 05:47:06 PM PDT 24
Peak memory 160804 kb
Host smart-4ed2cf78-f0b1-494a-b2e5-9e161f8e5021
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2675694631 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.2675694631
Directory /workspace/24.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.438173842
Short name T73
Test name
Test status
Simulation time 337032010000 ps
CPU time 868.04 seconds
Started Jul 23 05:17:54 PM PDT 24
Finished Jul 23 05:53:17 PM PDT 24
Peak memory 160764 kb
Host smart-0eea6277-20a0-4083-9d11-808541675a5f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=438173842 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.438173842
Directory /workspace/25.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1112550294
Short name T16
Test name
Test status
Simulation time 336414250000 ps
CPU time 811.5 seconds
Started Jul 23 05:17:55 PM PDT 24
Finished Jul 23 05:51:20 PM PDT 24
Peak memory 160792 kb
Host smart-c89abcf4-e710-46c0-8e66-075f6cb974f6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1112550294 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.1112550294
Directory /workspace/26.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.3168698269
Short name T77
Test name
Test status
Simulation time 336721330000 ps
CPU time 722.93 seconds
Started Jul 23 05:17:55 PM PDT 24
Finished Jul 23 05:47:41 PM PDT 24
Peak memory 160780 kb
Host smart-3e5d082f-bd3a-4b67-9807-132487b165e2
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3168698269 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.3168698269
Directory /workspace/27.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.1884081087
Short name T6
Test name
Test status
Simulation time 336583910000 ps
CPU time 779.34 seconds
Started Jul 23 05:17:55 PM PDT 24
Finished Jul 23 05:49:16 PM PDT 24
Peak memory 160800 kb
Host smart-60f226e4-f1d6-4d04-9737-52235bf12d51
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1884081087 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.1884081087
Directory /workspace/28.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.1034127847
Short name T106
Test name
Test status
Simulation time 337050030000 ps
CPU time 778.76 seconds
Started Jul 23 05:17:54 PM PDT 24
Finished Jul 23 05:50:19 PM PDT 24
Peak memory 160796 kb
Host smart-936b82e3-9a30-443a-9549-7d3428afebb3
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1034127847 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.1034127847
Directory /workspace/29.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.1305203741
Short name T19
Test name
Test status
Simulation time 336726590000 ps
CPU time 805.34 seconds
Started Jul 23 05:17:46 PM PDT 24
Finished Jul 23 05:51:16 PM PDT 24
Peak memory 160716 kb
Host smart-8228832a-e002-4961-b615-700e780744b0
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1305203741 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.1305203741
Directory /workspace/3.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3372090134
Short name T89
Test name
Test status
Simulation time 336598630000 ps
CPU time 816.35 seconds
Started Jul 23 05:17:53 PM PDT 24
Finished Jul 23 05:50:34 PM PDT 24
Peak memory 160796 kb
Host smart-ec8a2f94-5e47-453e-a5a8-e70e9c5e09a0
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3372090134 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.3372090134
Directory /workspace/30.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.2168629121
Short name T92
Test name
Test status
Simulation time 337018550000 ps
CPU time 758.43 seconds
Started Jul 23 05:17:55 PM PDT 24
Finished Jul 23 05:49:07 PM PDT 24
Peak memory 160740 kb
Host smart-29631f42-e3bb-40ca-ab4c-f7cb33c89ae5
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2168629121 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.2168629121
Directory /workspace/31.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.1907574788
Short name T81
Test name
Test status
Simulation time 336867130000 ps
CPU time 838.31 seconds
Started Jul 23 05:17:54 PM PDT 24
Finished Jul 23 05:52:17 PM PDT 24
Peak memory 160716 kb
Host smart-c4523678-a0b3-4ba7-b6e4-5585c105b31a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1907574788 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.1907574788
Directory /workspace/32.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.2049134993
Short name T96
Test name
Test status
Simulation time 336483870000 ps
CPU time 814.4 seconds
Started Jul 23 05:17:54 PM PDT 24
Finished Jul 23 05:51:26 PM PDT 24
Peak memory 160792 kb
Host smart-99c879bf-da11-4d93-85a4-feec706ff7a8
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2049134993 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.2049134993
Directory /workspace/33.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.1012829121
Short name T78
Test name
Test status
Simulation time 336980870000 ps
CPU time 769.95 seconds
Started Jul 23 05:17:54 PM PDT 24
Finished Jul 23 05:49:18 PM PDT 24
Peak memory 160724 kb
Host smart-0c626453-00e1-48b4-a76d-61baa149e06f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1012829121 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.1012829121
Directory /workspace/34.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.3121859838
Short name T18
Test name
Test status
Simulation time 336498330000 ps
CPU time 749 seconds
Started Jul 23 05:17:55 PM PDT 24
Finished Jul 23 05:48:39 PM PDT 24
Peak memory 160724 kb
Host smart-7b0e363e-088f-44b9-8a79-8141d517a398
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3121859838 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.3121859838
Directory /workspace/35.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.3488895258
Short name T84
Test name
Test status
Simulation time 336508570000 ps
CPU time 759.11 seconds
Started Jul 23 05:17:55 PM PDT 24
Finished Jul 23 05:49:08 PM PDT 24
Peak memory 160784 kb
Host smart-fd557d5f-f933-4d2b-b672-86efbfbee3b9
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3488895258 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.3488895258
Directory /workspace/36.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.1180103853
Short name T102
Test name
Test status
Simulation time 336832410000 ps
CPU time 732.76 seconds
Started Jul 23 05:17:55 PM PDT 24
Finished Jul 23 05:47:42 PM PDT 24
Peak memory 160756 kb
Host smart-a557e84c-b2f4-47df-b6c1-501e291dda97
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1180103853 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.1180103853
Directory /workspace/37.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.4235408973
Short name T104
Test name
Test status
Simulation time 336839990000 ps
CPU time 734.79 seconds
Started Jul 23 05:17:57 PM PDT 24
Finished Jul 23 05:48:43 PM PDT 24
Peak memory 160820 kb
Host smart-e51d69a2-9239-4a9b-9f72-b6ce415825b7
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4235408973 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.4235408973
Directory /workspace/38.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.1727333754
Short name T93
Test name
Test status
Simulation time 336792530000 ps
CPU time 619.87 seconds
Started Jul 23 05:17:56 PM PDT 24
Finished Jul 23 05:44:00 PM PDT 24
Peak memory 160704 kb
Host smart-dee04c7e-951b-493f-b712-e47e973331d3
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1727333754 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.1727333754
Directory /workspace/39.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.4264952166
Short name T74
Test name
Test status
Simulation time 336351150000 ps
CPU time 648.94 seconds
Started Jul 23 05:17:44 PM PDT 24
Finished Jul 23 05:44:20 PM PDT 24
Peak memory 160776 kb
Host smart-275f3cfa-fad2-4fc8-a33d-f37ca8482e40
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4264952166 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.4264952166
Directory /workspace/4.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.2777409350
Short name T95
Test name
Test status
Simulation time 336318010000 ps
CPU time 612.52 seconds
Started Jul 23 05:17:56 PM PDT 24
Finished Jul 23 05:43:36 PM PDT 24
Peak memory 160712 kb
Host smart-5084adbe-5188-4403-8539-eef749d01597
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2777409350 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.2777409350
Directory /workspace/40.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.1471812818
Short name T94
Test name
Test status
Simulation time 336579030000 ps
CPU time 790.28 seconds
Started Jul 23 05:17:55 PM PDT 24
Finished Jul 23 05:50:14 PM PDT 24
Peak memory 160732 kb
Host smart-742f6281-0476-4c5e-bc9e-8ae65391e634
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1471812818 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.1471812818
Directory /workspace/41.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.1407943601
Short name T103
Test name
Test status
Simulation time 337033050000 ps
CPU time 886.9 seconds
Started Jul 23 05:18:04 PM PDT 24
Finished Jul 23 05:54:24 PM PDT 24
Peak memory 160788 kb
Host smart-9b8001d2-e91c-4e74-90ba-15fd344e7ce8
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1407943601 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.1407943601
Directory /workspace/42.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.841775671
Short name T107
Test name
Test status
Simulation time 337112530000 ps
CPU time 735.25 seconds
Started Jul 23 05:18:03 PM PDT 24
Finished Jul 23 05:48:43 PM PDT 24
Peak memory 160776 kb
Host smart-339d8122-c696-478f-a3b2-11bb91336f0d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=841775671 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.841775671
Directory /workspace/43.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.3086711613
Short name T80
Test name
Test status
Simulation time 336550590000 ps
CPU time 782.31 seconds
Started Jul 23 05:18:04 PM PDT 24
Finished Jul 23 05:49:33 PM PDT 24
Peak memory 160796 kb
Host smart-11bee409-1e3d-4cf7-b897-143f6fa7da0d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3086711613 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.3086711613
Directory /workspace/44.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.857615526
Short name T75
Test name
Test status
Simulation time 336958730000 ps
CPU time 733.98 seconds
Started Jul 23 05:18:03 PM PDT 24
Finished Jul 23 05:48:45 PM PDT 24
Peak memory 160812 kb
Host smart-91ba2063-9b80-4631-86c6-6ec770b48ee6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=857615526 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.857615526
Directory /workspace/45.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.1054223196
Short name T97
Test name
Test status
Simulation time 336334710000 ps
CPU time 727.42 seconds
Started Jul 23 05:18:06 PM PDT 24
Finished Jul 23 05:47:28 PM PDT 24
Peak memory 160816 kb
Host smart-5599beed-0afa-4d51-80c7-9cd7b5b45b75
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1054223196 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.1054223196
Directory /workspace/46.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.3394783506
Short name T105
Test name
Test status
Simulation time 337023110000 ps
CPU time 803.01 seconds
Started Jul 23 05:18:03 PM PDT 24
Finished Jul 23 05:50:40 PM PDT 24
Peak memory 160796 kb
Host smart-dfcda040-d009-4158-8485-75c32cb78a60
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3394783506 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.3394783506
Directory /workspace/47.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.3011424272
Short name T100
Test name
Test status
Simulation time 336469790000 ps
CPU time 737.3 seconds
Started Jul 23 05:18:05 PM PDT 24
Finished Jul 23 05:48:25 PM PDT 24
Peak memory 160724 kb
Host smart-81323b1e-35a5-4c59-911e-a8764885d72b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3011424272 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.3011424272
Directory /workspace/48.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.3723478560
Short name T108
Test name
Test status
Simulation time 336661130000 ps
CPU time 872.3 seconds
Started Jul 23 05:18:05 PM PDT 24
Finished Jul 23 05:53:09 PM PDT 24
Peak memory 160796 kb
Host smart-e30aa06e-0d09-4dc4-a4b6-d7f3dd89df09
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3723478560 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.3723478560
Directory /workspace/49.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.2412034149
Short name T4
Test name
Test status
Simulation time 336618930000 ps
CPU time 783.76 seconds
Started Jul 23 05:17:45 PM PDT 24
Finished Jul 23 05:50:17 PM PDT 24
Peak memory 160796 kb
Host smart-25a93def-e242-421f-bf17-f6041ad53423
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2412034149 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.2412034149
Directory /workspace/5.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.372943713
Short name T87
Test name
Test status
Simulation time 336367390000 ps
CPU time 695.82 seconds
Started Jul 23 05:17:45 PM PDT 24
Finished Jul 23 05:46:20 PM PDT 24
Peak memory 160792 kb
Host smart-244f274a-0415-4746-8125-7f3461fe2801
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=372943713 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.372943713
Directory /workspace/6.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.2984049308
Short name T88
Test name
Test status
Simulation time 337054870000 ps
CPU time 875.98 seconds
Started Jul 23 05:17:47 PM PDT 24
Finished Jul 23 05:53:37 PM PDT 24
Peak memory 160788 kb
Host smart-82c218f6-b33d-4230-a644-200aadc8ac9f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2984049308 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.2984049308
Directory /workspace/7.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1268476338
Short name T90
Test name
Test status
Simulation time 336320590000 ps
CPU time 813.15 seconds
Started Jul 23 05:17:46 PM PDT 24
Finished Jul 23 05:50:20 PM PDT 24
Peak memory 160748 kb
Host smart-b60ca545-5534-4c89-8459-3e5605558465
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1268476338 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.1268476338
Directory /workspace/8.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.3695503717
Short name T110
Test name
Test status
Simulation time 336619730000 ps
CPU time 831.12 seconds
Started Jul 23 05:17:48 PM PDT 24
Finished Jul 23 05:51:10 PM PDT 24
Peak memory 160752 kb
Host smart-abd6c4c2-18f7-4629-8bb7-387fc4e3b1ee
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3695503717 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.3695503717
Directory /workspace/9.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.643952203
Short name T193
Test name
Test status
Simulation time 336802390000 ps
CPU time 837.26 seconds
Started Jul 23 04:40:00 PM PDT 24
Finished Jul 23 05:14:10 PM PDT 24
Peak memory 160676 kb
Host smart-b2fec312-6e92-4950-834c-083dccd08258
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=643952203 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.643952203
Directory /workspace/0.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.358925982
Short name T162
Test name
Test status
Simulation time 337018950000 ps
CPU time 711.4 seconds
Started Jul 23 04:39:58 PM PDT 24
Finished Jul 23 05:09:02 PM PDT 24
Peak memory 160724 kb
Host smart-168e98ab-949b-40d5-874a-88a84ddfa3c3
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=358925982 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.358925982
Directory /workspace/1.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.951131457
Short name T179
Test name
Test status
Simulation time 336729970000 ps
CPU time 786.44 seconds
Started Jul 23 04:39:59 PM PDT 24
Finished Jul 23 05:12:06 PM PDT 24
Peak memory 160740 kb
Host smart-d519fba3-1bd3-4b57-8ee9-f6a1fe6dd241
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=951131457 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.951131457
Directory /workspace/10.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.2413803497
Short name T187
Test name
Test status
Simulation time 336726110000 ps
CPU time 677.28 seconds
Started Jul 23 04:39:56 PM PDT 24
Finished Jul 23 05:07:26 PM PDT 24
Peak memory 160788 kb
Host smart-3405f007-ebcf-49b3-a6e4-bd5c08123e48
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2413803497 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.2413803497
Directory /workspace/12.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.874287483
Short name T195
Test name
Test status
Simulation time 336885690000 ps
CPU time 790.69 seconds
Started Jul 23 04:39:58 PM PDT 24
Finished Jul 23 05:11:54 PM PDT 24
Peak memory 160728 kb
Host smart-d19b81c6-d72e-4fa7-9e70-c45be7307c2f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=874287483 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.874287483
Directory /workspace/13.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.245544148
Short name T174
Test name
Test status
Simulation time 336591850000 ps
CPU time 738.98 seconds
Started Jul 23 04:40:03 PM PDT 24
Finished Jul 23 05:10:47 PM PDT 24
Peak memory 160732 kb
Host smart-18b28848-57b6-4391-85bf-498acc108def
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=245544148 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.245544148
Directory /workspace/14.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.4192278305
Short name T200
Test name
Test status
Simulation time 336615530000 ps
CPU time 735.41 seconds
Started Jul 23 04:40:11 PM PDT 24
Finished Jul 23 05:10:11 PM PDT 24
Peak memory 160740 kb
Host smart-a8a7e772-f2a9-417b-a3d8-784e1fe37eaf
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4192278305 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.4192278305
Directory /workspace/15.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.2567213615
Short name T185
Test name
Test status
Simulation time 336426770000 ps
CPU time 685.82 seconds
Started Jul 23 04:40:09 PM PDT 24
Finished Jul 23 05:08:20 PM PDT 24
Peak memory 160788 kb
Host smart-899cb1ed-3e37-4765-b67e-e0aeedc0b096
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2567213615 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.2567213615
Directory /workspace/16.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.1869259041
Short name T181
Test name
Test status
Simulation time 336602370000 ps
CPU time 748.1 seconds
Started Jul 23 04:40:11 PM PDT 24
Finished Jul 23 05:10:28 PM PDT 24
Peak memory 160752 kb
Host smart-9b8b2fcf-d021-42d7-afcf-936ad2892283
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1869259041 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.1869259041
Directory /workspace/17.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.1256928771
Short name T177
Test name
Test status
Simulation time 336725630000 ps
CPU time 898.78 seconds
Started Jul 23 04:40:13 PM PDT 24
Finished Jul 23 05:17:57 PM PDT 24
Peak memory 160676 kb
Host smart-fd1f1557-590d-4208-8e60-2d6026f27155
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1256928771 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.1256928771
Directory /workspace/18.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.924780091
Short name T163
Test name
Test status
Simulation time 337017150000 ps
CPU time 829.96 seconds
Started Jul 23 04:40:10 PM PDT 24
Finished Jul 23 05:13:47 PM PDT 24
Peak memory 160708 kb
Host smart-9278661a-a8de-43f3-ba39-617943fe1df7
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=924780091 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.924780091
Directory /workspace/19.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.2424901193
Short name T180
Test name
Test status
Simulation time 337003070000 ps
CPU time 884.89 seconds
Started Jul 23 04:39:57 PM PDT 24
Finished Jul 23 05:15:41 PM PDT 24
Peak memory 160708 kb
Host smart-8c6eb32d-1d89-4657-96ff-49bffca4e2e1
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2424901193 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.2424901193
Directory /workspace/2.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.1615290009
Short name T191
Test name
Test status
Simulation time 336826470000 ps
CPU time 754.4 seconds
Started Jul 23 04:40:08 PM PDT 24
Finished Jul 23 05:10:26 PM PDT 24
Peak memory 160728 kb
Host smart-72568b6b-cd13-4e08-8f53-fc415ed5aa65
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1615290009 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.1615290009
Directory /workspace/20.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3529154742
Short name T196
Test name
Test status
Simulation time 336729370000 ps
CPU time 627.27 seconds
Started Jul 23 04:40:11 PM PDT 24
Finished Jul 23 05:06:36 PM PDT 24
Peak memory 160728 kb
Host smart-e5e00e2a-d4ea-43ba-84ea-e5931dc158a7
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3529154742 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.3529154742
Directory /workspace/21.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.2966660449
Short name T173
Test name
Test status
Simulation time 336354070000 ps
CPU time 794.36 seconds
Started Jul 23 04:40:10 PM PDT 24
Finished Jul 23 05:12:49 PM PDT 24
Peak memory 160748 kb
Host smart-938d6a63-2410-4014-9435-e7c2a6c1fa34
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2966660449 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.2966660449
Directory /workspace/22.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.1724143332
Short name T197
Test name
Test status
Simulation time 336949010000 ps
CPU time 818.54 seconds
Started Jul 23 04:40:16 PM PDT 24
Finished Jul 23 05:14:45 PM PDT 24
Peak memory 160780 kb
Host smart-c803c58e-0fdd-4cea-9429-5b593caef6ba
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1724143332 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.1724143332
Directory /workspace/23.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.2208395767
Short name T171
Test name
Test status
Simulation time 337112850000 ps
CPU time 750.14 seconds
Started Jul 23 04:40:10 PM PDT 24
Finished Jul 23 05:10:23 PM PDT 24
Peak memory 160748 kb
Host smart-23ec85b7-f784-4280-98bc-95cf24a548f3
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2208395767 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.2208395767
Directory /workspace/24.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.4042441000
Short name T168
Test name
Test status
Simulation time 336901650000 ps
CPU time 673.58 seconds
Started Jul 23 04:40:14 PM PDT 24
Finished Jul 23 05:07:55 PM PDT 24
Peak memory 160732 kb
Host smart-c8a96c23-37a1-49d3-8e44-86a7bb843b30
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4042441000 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.4042441000
Directory /workspace/25.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.1253767046
Short name T161
Test name
Test status
Simulation time 337070150000 ps
CPU time 692.64 seconds
Started Jul 23 04:40:13 PM PDT 24
Finished Jul 23 05:08:38 PM PDT 24
Peak memory 160736 kb
Host smart-66ffc423-6b30-4a8e-9251-e856557840cb
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1253767046 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.1253767046
Directory /workspace/26.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.1031090700
Short name T184
Test name
Test status
Simulation time 336733270000 ps
CPU time 771.69 seconds
Started Jul 23 04:40:12 PM PDT 24
Finished Jul 23 05:11:56 PM PDT 24
Peak memory 160748 kb
Host smart-c1be70bf-c575-4798-8375-10e9c9f40bbe
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1031090700 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.1031090700
Directory /workspace/27.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.2961168420
Short name T188
Test name
Test status
Simulation time 336539930000 ps
CPU time 728.06 seconds
Started Jul 23 04:40:14 PM PDT 24
Finished Jul 23 05:10:42 PM PDT 24
Peak memory 160732 kb
Host smart-0daf3d2b-f443-4c1a-822d-03e3c10aa667
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2961168420 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.2961168420
Directory /workspace/28.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.3149564183
Short name T30
Test name
Test status
Simulation time 336727770000 ps
CPU time 736.56 seconds
Started Jul 23 04:40:10 PM PDT 24
Finished Jul 23 05:10:03 PM PDT 24
Peak memory 160728 kb
Host smart-2285c9d7-04d4-4fed-bd30-abe89bd3d46b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3149564183 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.3149564183
Directory /workspace/29.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.110526034
Short name T27
Test name
Test status
Simulation time 336919910000 ps
CPU time 710.88 seconds
Started Jul 23 04:39:57 PM PDT 24
Finished Jul 23 05:08:42 PM PDT 24
Peak memory 160784 kb
Host smart-e5018c16-9bf7-4584-9c24-10063643d041
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=110526034 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.110526034
Directory /workspace/3.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.265751
Short name T23
Test name
Test status
Simulation time 336466290000 ps
CPU time 894.5 seconds
Started Jul 23 04:40:12 PM PDT 24
Finished Jul 23 05:17:47 PM PDT 24
Peak memory 160660 kb
Host smart-c6d16d68-51c9-478f-aa7f-184c551a8b99
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=265751 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.265751
Directory /workspace/30.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.2852346139
Short name T22
Test name
Test status
Simulation time 336947410000 ps
CPU time 702.19 seconds
Started Jul 23 04:40:13 PM PDT 24
Finished Jul 23 05:09:50 PM PDT 24
Peak memory 160732 kb
Host smart-9e6cd50d-b67a-4f2d-892c-dee3514c0e6d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2852346139 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.2852346139
Directory /workspace/31.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.1663630042
Short name T170
Test name
Test status
Simulation time 336367690000 ps
CPU time 952.5 seconds
Started Jul 23 04:40:10 PM PDT 24
Finished Jul 23 05:20:09 PM PDT 24
Peak memory 160728 kb
Host smart-3ffa0015-1109-44f0-a39d-95f4490d4486
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1663630042 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.1663630042
Directory /workspace/32.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.4217743451
Short name T199
Test name
Test status
Simulation time 336425110000 ps
CPU time 794.8 seconds
Started Jul 23 04:40:09 PM PDT 24
Finished Jul 23 05:12:35 PM PDT 24
Peak memory 160748 kb
Host smart-d23e5cc4-5851-418c-9223-469ffdcea892
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4217743451 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.4217743451
Directory /workspace/33.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.2985426281
Short name T169
Test name
Test status
Simulation time 336688170000 ps
CPU time 813.03 seconds
Started Jul 23 04:40:09 PM PDT 24
Finished Jul 23 05:12:52 PM PDT 24
Peak memory 160792 kb
Host smart-8e4ad041-892e-40b2-a649-c3d3ade84707
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2985426281 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.2985426281
Directory /workspace/34.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.3283898923
Short name T29
Test name
Test status
Simulation time 336778390000 ps
CPU time 815 seconds
Started Jul 23 04:40:19 PM PDT 24
Finished Jul 23 05:14:51 PM PDT 24
Peak memory 160784 kb
Host smart-3a18d2c8-1eaf-4d51-921c-58a621839730
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3283898923 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.3283898923
Directory /workspace/35.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.1303588907
Short name T175
Test name
Test status
Simulation time 336866410000 ps
CPU time 712.24 seconds
Started Jul 23 04:40:13 PM PDT 24
Finished Jul 23 05:09:18 PM PDT 24
Peak memory 160704 kb
Host smart-ca9c93d6-277d-4bc7-ace1-bd919837a369
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1303588907 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.1303588907
Directory /workspace/36.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.1554857450
Short name T166
Test name
Test status
Simulation time 336631470000 ps
CPU time 932.94 seconds
Started Jul 23 04:40:11 PM PDT 24
Finished Jul 23 05:19:45 PM PDT 24
Peak memory 160728 kb
Host smart-33eea3a2-8fb8-455c-b572-643c14b3858b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1554857450 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.1554857450
Directory /workspace/37.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.681173345
Short name T28
Test name
Test status
Simulation time 337004630000 ps
CPU time 700.2 seconds
Started Jul 23 04:40:12 PM PDT 24
Finished Jul 23 05:09:10 PM PDT 24
Peak memory 160740 kb
Host smart-38d154eb-c69e-4718-989b-370c179400ed
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=681173345 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.681173345
Directory /workspace/38.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.2473927953
Short name T198
Test name
Test status
Simulation time 336819470000 ps
CPU time 638.88 seconds
Started Jul 23 04:40:13 PM PDT 24
Finished Jul 23 05:06:49 PM PDT 24
Peak memory 160736 kb
Host smart-45eebb6c-e419-4483-b1a8-8f90a2ce89cc
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2473927953 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.2473927953
Directory /workspace/39.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.1902385016
Short name T182
Test name
Test status
Simulation time 336738290000 ps
CPU time 886.53 seconds
Started Jul 23 04:39:58 PM PDT 24
Finished Jul 23 05:16:35 PM PDT 24
Peak memory 160728 kb
Host smart-a21ca622-ea33-4fe8-af69-78ca57c59569
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1902385016 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.1902385016
Directory /workspace/4.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.153920042
Short name T178
Test name
Test status
Simulation time 336975310000 ps
CPU time 858.68 seconds
Started Jul 23 04:40:10 PM PDT 24
Finished Jul 23 05:15:18 PM PDT 24
Peak memory 160732 kb
Host smart-becd1481-d335-4e2a-8880-d276a59f8280
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=153920042 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.153920042
Directory /workspace/40.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.3279136229
Short name T186
Test name
Test status
Simulation time 336575510000 ps
CPU time 721.99 seconds
Started Jul 23 04:40:11 PM PDT 24
Finished Jul 23 05:09:53 PM PDT 24
Peak memory 160748 kb
Host smart-af082f9b-0933-4eaa-a6d6-990f23076be0
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3279136229 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.3279136229
Directory /workspace/41.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.2037891060
Short name T192
Test name
Test status
Simulation time 336783510000 ps
CPU time 789.46 seconds
Started Jul 23 04:40:15 PM PDT 24
Finished Jul 23 05:12:00 PM PDT 24
Peak memory 160680 kb
Host smart-e96c1337-9e27-4c00-9348-36db6d1fd43c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2037891060 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.2037891060
Directory /workspace/42.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.909820848
Short name T25
Test name
Test status
Simulation time 336404310000 ps
CPU time 932.9 seconds
Started Jul 23 04:40:11 PM PDT 24
Finished Jul 23 05:19:42 PM PDT 24
Peak memory 160728 kb
Host smart-0df889b0-4149-4382-bb6a-5843aac52862
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=909820848 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.909820848
Directory /workspace/43.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.1143948554
Short name T176
Test name
Test status
Simulation time 336524330000 ps
CPU time 843.13 seconds
Started Jul 23 04:40:19 PM PDT 24
Finished Jul 23 05:15:44 PM PDT 24
Peak memory 160784 kb
Host smart-6cfa6d2c-71de-47a6-a050-bcb1e8ccad92
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1143948554 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.1143948554
Directory /workspace/44.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.3259198582
Short name T164
Test name
Test status
Simulation time 336738130000 ps
CPU time 915.35 seconds
Started Jul 23 04:40:09 PM PDT 24
Finished Jul 23 05:16:39 PM PDT 24
Peak memory 160792 kb
Host smart-7d80dbc3-cf0f-47f0-a462-a3ef51362b84
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3259198582 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.3259198582
Directory /workspace/45.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.148280958
Short name T167
Test name
Test status
Simulation time 336819250000 ps
CPU time 732.42 seconds
Started Jul 23 04:40:15 PM PDT 24
Finished Jul 23 05:10:52 PM PDT 24
Peak memory 160732 kb
Host smart-f32cfcbf-1ce9-411c-92dc-61d2fe8e718c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=148280958 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.148280958
Directory /workspace/46.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.3641770187
Short name T165
Test name
Test status
Simulation time 336721370000 ps
CPU time 638.83 seconds
Started Jul 23 04:40:10 PM PDT 24
Finished Jul 23 05:06:38 PM PDT 24
Peak memory 160788 kb
Host smart-3844d8ca-fef7-49a8-9f25-b67067519096
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3641770187 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.3641770187
Directory /workspace/47.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.4089343551
Short name T26
Test name
Test status
Simulation time 336309790000 ps
CPU time 717.97 seconds
Started Jul 23 04:40:11 PM PDT 24
Finished Jul 23 05:09:53 PM PDT 24
Peak memory 160752 kb
Host smart-ef8afd54-2cc8-49cd-aff0-dd11ac75d1e6
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4089343551 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.4089343551
Directory /workspace/48.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.47261158
Short name T190
Test name
Test status
Simulation time 336371810000 ps
CPU time 642.91 seconds
Started Jul 23 04:40:10 PM PDT 24
Finished Jul 23 05:06:41 PM PDT 24
Peak memory 160792 kb
Host smart-a33fc136-0208-4869-8560-0c53c1bb862c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=47261158 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.47261158
Directory /workspace/49.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.3245637558
Short name T189
Test name
Test status
Simulation time 336446450000 ps
CPU time 641.35 seconds
Started Jul 23 04:39:59 PM PDT 24
Finished Jul 23 05:06:11 PM PDT 24
Peak memory 160732 kb
Host smart-503b1f41-0d34-4cac-ba83-b424dd4df118
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3245637558 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.3245637558
Directory /workspace/5.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.64507637
Short name T172
Test name
Test status
Simulation time 336469530000 ps
CPU time 847.18 seconds
Started Jul 23 04:39:59 PM PDT 24
Finished Jul 23 05:14:13 PM PDT 24
Peak memory 160672 kb
Host smart-3cd5ce06-2b8d-4783-a45b-2b20affe7609
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=64507637 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.64507637
Directory /workspace/6.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.2625183663
Short name T194
Test name
Test status
Simulation time 336269190000 ps
CPU time 873.54 seconds
Started Jul 23 04:40:00 PM PDT 24
Finished Jul 23 05:16:26 PM PDT 24
Peak memory 160664 kb
Host smart-86b4d38a-5078-4927-8e45-97e80ea30e00
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2625183663 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.2625183663
Directory /workspace/7.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.2188394452
Short name T183
Test name
Test status
Simulation time 336968310000 ps
CPU time 795.97 seconds
Started Jul 23 04:40:03 PM PDT 24
Finished Jul 23 05:12:14 PM PDT 24
Peak memory 160728 kb
Host smart-8e90662f-ac22-4eec-a3be-22e1a924e0a6
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2188394452 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.2188394452
Directory /workspace/8.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.2001892961
Short name T21
Test name
Test status
Simulation time 336506270000 ps
CPU time 765.74 seconds
Started Jul 23 04:39:59 PM PDT 24
Finished Jul 23 05:11:30 PM PDT 24
Peak memory 160740 kb
Host smart-2eebcc78-4592-4280-8e42-2e57623c8666
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2001892961 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.2001892961
Directory /workspace/9.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.975475411
Short name T150
Test name
Test status
Simulation time 1462510000 ps
CPU time 4.45 seconds
Started Jul 23 04:38:06 PM PDT 24
Finished Jul 23 04:38:17 PM PDT 24
Peak memory 165032 kb
Host smart-8c08dc87-839d-4842-9be5-e291a28f79dd
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=975475411 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.975475411
Directory /workspace/0.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.2187489520
Short name T113
Test name
Test status
Simulation time 1551010000 ps
CPU time 3.9 seconds
Started Jul 23 04:38:05 PM PDT 24
Finished Jul 23 04:38:14 PM PDT 24
Peak memory 164804 kb
Host smart-8b47911d-05ba-4c62-95ee-3d68ee4eaa88
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2187489520 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.2187489520
Directory /workspace/1.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.2310276599
Short name T117
Test name
Test status
Simulation time 1393850000 ps
CPU time 4.04 seconds
Started Jul 23 04:38:03 PM PDT 24
Finished Jul 23 04:38:13 PM PDT 24
Peak memory 165040 kb
Host smart-166fe862-bfa2-45f9-9544-ce2c8837e65d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2310276599 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.2310276599
Directory /workspace/10.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.511583324
Short name T144
Test name
Test status
Simulation time 1435730000 ps
CPU time 4 seconds
Started Jul 23 04:38:04 PM PDT 24
Finished Jul 23 04:38:14 PM PDT 24
Peak memory 164660 kb
Host smart-dc9b0443-b5bd-4b0e-af71-f2d7cb3b20a0
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=511583324 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.511583324
Directory /workspace/11.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.2821234298
Short name T156
Test name
Test status
Simulation time 1531870000 ps
CPU time 4.71 seconds
Started Jul 23 04:38:06 PM PDT 24
Finished Jul 23 04:38:18 PM PDT 24
Peak memory 165040 kb
Host smart-f8c95d04-8607-4ee2-82b1-1f10771e26ef
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2821234298 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.2821234298
Directory /workspace/12.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.2597002478
Short name T131
Test name
Test status
Simulation time 1506630000 ps
CPU time 4.7 seconds
Started Jul 23 04:38:05 PM PDT 24
Finished Jul 23 04:38:16 PM PDT 24
Peak memory 164728 kb
Host smart-48eb162b-49a1-415c-8db9-236943bdf231
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2597002478 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.2597002478
Directory /workspace/13.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.1100653795
Short name T140
Test name
Test status
Simulation time 1385790000 ps
CPU time 4.62 seconds
Started Jul 23 04:38:01 PM PDT 24
Finished Jul 23 04:38:12 PM PDT 24
Peak memory 164772 kb
Host smart-e1ec96b5-ca2b-425d-b326-3da50d3c2058
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1100653795 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.1100653795
Directory /workspace/14.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.1166118496
Short name T138
Test name
Test status
Simulation time 1436910000 ps
CPU time 4.16 seconds
Started Jul 23 04:38:02 PM PDT 24
Finished Jul 23 04:38:12 PM PDT 24
Peak memory 164552 kb
Host smart-62e5f6a3-fc60-41f1-959c-21e9f78dcd64
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1166118496 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.1166118496
Directory /workspace/15.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.2537154095
Short name T114
Test name
Test status
Simulation time 1509510000 ps
CPU time 4.12 seconds
Started Jul 23 04:38:08 PM PDT 24
Finished Jul 23 04:38:18 PM PDT 24
Peak memory 164828 kb
Host smart-faa4b117-1525-49e1-883d-d6a0455f98b1
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2537154095 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.2537154095
Directory /workspace/16.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.2579473775
Short name T133
Test name
Test status
Simulation time 1487150000 ps
CPU time 4.48 seconds
Started Jul 23 04:38:02 PM PDT 24
Finished Jul 23 04:38:13 PM PDT 24
Peak memory 164736 kb
Host smart-4a73a2ed-3299-49bf-a343-b41516da4b99
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2579473775 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.2579473775
Directory /workspace/17.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.1260262332
Short name T124
Test name
Test status
Simulation time 1363870000 ps
CPU time 3.52 seconds
Started Jul 23 04:38:05 PM PDT 24
Finished Jul 23 04:38:14 PM PDT 24
Peak memory 164756 kb
Host smart-1f1ad1d6-4546-46ca-889b-48ba0770ed3c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1260262332 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.1260262332
Directory /workspace/18.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.1794619040
Short name T158
Test name
Test status
Simulation time 1573750000 ps
CPU time 3.77 seconds
Started Jul 23 04:38:04 PM PDT 24
Finished Jul 23 04:38:14 PM PDT 24
Peak memory 164804 kb
Host smart-3015acd1-5a35-4672-9e66-4157aa2cb590
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1794619040 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.1794619040
Directory /workspace/19.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.4051213028
Short name T160
Test name
Test status
Simulation time 1246270000 ps
CPU time 3.29 seconds
Started Jul 23 04:38:01 PM PDT 24
Finished Jul 23 04:38:09 PM PDT 24
Peak memory 164772 kb
Host smart-76b84f61-df01-470d-babe-9e9dda845fbe
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4051213028 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.4051213028
Directory /workspace/2.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.2766948453
Short name T155
Test name
Test status
Simulation time 1432770000 ps
CPU time 3.86 seconds
Started Jul 23 04:38:04 PM PDT 24
Finished Jul 23 04:38:14 PM PDT 24
Peak memory 164736 kb
Host smart-6441ae93-38d9-4721-acc7-65de0541a8c7
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2766948453 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.2766948453
Directory /workspace/20.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.1967791103
Short name T122
Test name
Test status
Simulation time 1470650000 ps
CPU time 4.7 seconds
Started Jul 23 04:38:02 PM PDT 24
Finished Jul 23 04:38:13 PM PDT 24
Peak memory 164424 kb
Host smart-9e848c5b-fab3-47a0-94df-3c769a1fa0b7
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1967791103 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.1967791103
Directory /workspace/21.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.1186344997
Short name T152
Test name
Test status
Simulation time 1418790000 ps
CPU time 3.96 seconds
Started Jul 23 04:38:03 PM PDT 24
Finished Jul 23 04:38:13 PM PDT 24
Peak memory 164656 kb
Host smart-e0584b28-8e11-4f5b-aed3-5c68373042d4
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1186344997 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.1186344997
Directory /workspace/22.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.1077200681
Short name T151
Test name
Test status
Simulation time 1396270000 ps
CPU time 3.33 seconds
Started Jul 23 04:38:03 PM PDT 24
Finished Jul 23 04:38:11 PM PDT 24
Peak memory 164740 kb
Host smart-8bdc2dfb-006d-4951-9a6b-e3b22d69c0d1
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1077200681 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.1077200681
Directory /workspace/23.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.1781355130
Short name T111
Test name
Test status
Simulation time 1557190000 ps
CPU time 4.41 seconds
Started Jul 23 04:38:07 PM PDT 24
Finished Jul 23 04:38:17 PM PDT 24
Peak memory 164820 kb
Host smart-256b441e-11af-4fad-8f40-0ee3b15248dc
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1781355130 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.1781355130
Directory /workspace/24.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.1907544261
Short name T115
Test name
Test status
Simulation time 1153830000 ps
CPU time 3.66 seconds
Started Jul 23 04:38:04 PM PDT 24
Finished Jul 23 04:38:13 PM PDT 24
Peak memory 164784 kb
Host smart-6b4eea99-ef9f-421d-bb40-db680bdfae90
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1907544261 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.1907544261
Directory /workspace/25.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.3685169925
Short name T118
Test name
Test status
Simulation time 1514450000 ps
CPU time 4.08 seconds
Started Jul 23 04:38:06 PM PDT 24
Finished Jul 23 04:38:16 PM PDT 24
Peak memory 164728 kb
Host smart-d634c216-15db-4da1-af4a-0f5f3485c778
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3685169925 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.3685169925
Directory /workspace/26.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.776598956
Short name T153
Test name
Test status
Simulation time 1467930000 ps
CPU time 3.8 seconds
Started Jul 23 04:38:03 PM PDT 24
Finished Jul 23 04:38:12 PM PDT 24
Peak memory 164720 kb
Host smart-546ae5da-9da7-4e44-b810-64e05398c211
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=776598956 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.776598956
Directory /workspace/27.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.4245413780
Short name T123
Test name
Test status
Simulation time 1475690000 ps
CPU time 5.02 seconds
Started Jul 23 04:38:05 PM PDT 24
Finished Jul 23 04:38:17 PM PDT 24
Peak memory 164784 kb
Host smart-86e702ba-b52e-4904-9df5-c71fd177646e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4245413780 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.4245413780
Directory /workspace/28.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.2622502880
Short name T134
Test name
Test status
Simulation time 1271350000 ps
CPU time 3.54 seconds
Started Jul 23 04:38:02 PM PDT 24
Finished Jul 23 04:38:10 PM PDT 24
Peak memory 164700 kb
Host smart-96396290-1e97-4f11-9e50-0fd7bf830c49
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2622502880 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.2622502880
Directory /workspace/29.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.3260769105
Short name T157
Test name
Test status
Simulation time 1580790000 ps
CPU time 2.93 seconds
Started Jul 23 04:38:05 PM PDT 24
Finished Jul 23 04:38:17 PM PDT 24
Peak memory 164396 kb
Host smart-9b5081bd-ae5d-45e6-b5be-ed608c4cbddb
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3260769105 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.3260769105
Directory /workspace/3.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.142977057
Short name T142
Test name
Test status
Simulation time 1580090000 ps
CPU time 4.29 seconds
Started Jul 23 04:38:05 PM PDT 24
Finished Jul 23 04:38:15 PM PDT 24
Peak memory 164700 kb
Host smart-e56b1b27-28cf-445b-8e22-44467ff7f5a2
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=142977057 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.142977057
Directory /workspace/30.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.674806858
Short name T154
Test name
Test status
Simulation time 1456970000 ps
CPU time 4.1 seconds
Started Jul 23 04:38:04 PM PDT 24
Finished Jul 23 04:38:14 PM PDT 24
Peak memory 164732 kb
Host smart-ade76cfc-a051-445c-a232-6f3e8fff1306
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=674806858 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.674806858
Directory /workspace/31.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.202551186
Short name T137
Test name
Test status
Simulation time 1239710000 ps
CPU time 3.98 seconds
Started Jul 23 04:38:03 PM PDT 24
Finished Jul 23 04:38:12 PM PDT 24
Peak memory 164728 kb
Host smart-4db8d1f9-3cee-4f9b-be3a-588ac55e5646
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=202551186 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.202551186
Directory /workspace/32.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.1327822189
Short name T129
Test name
Test status
Simulation time 1484770000 ps
CPU time 4.19 seconds
Started Jul 23 04:38:05 PM PDT 24
Finished Jul 23 04:38:26 PM PDT 24
Peak memory 164784 kb
Host smart-14622fbd-6f86-438d-9021-a53447a59164
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1327822189 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.1327822189
Directory /workspace/33.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.4165903288
Short name T149
Test name
Test status
Simulation time 1551110000 ps
CPU time 3.95 seconds
Started Jul 23 04:38:06 PM PDT 24
Finished Jul 23 04:38:16 PM PDT 24
Peak memory 164732 kb
Host smart-aa224f28-a022-428d-be12-23cb1d0438d2
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4165903288 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.4165903288
Directory /workspace/34.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.1018281891
Short name T116
Test name
Test status
Simulation time 1197230000 ps
CPU time 3.3 seconds
Started Jul 23 04:38:04 PM PDT 24
Finished Jul 23 04:38:12 PM PDT 24
Peak memory 164748 kb
Host smart-54f8dd9f-58fe-43c7-b7a4-e0481056214e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1018281891 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.1018281891
Directory /workspace/35.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.1414030781
Short name T159
Test name
Test status
Simulation time 1317030000 ps
CPU time 4.04 seconds
Started Jul 23 04:38:02 PM PDT 24
Finished Jul 23 04:38:12 PM PDT 24
Peak memory 164736 kb
Host smart-2873f8ea-cebb-47e2-9638-2ba3101e2b58
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1414030781 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.1414030781
Directory /workspace/36.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.4222846778
Short name T136
Test name
Test status
Simulation time 1515210000 ps
CPU time 5.41 seconds
Started Jul 23 04:38:04 PM PDT 24
Finished Jul 23 04:38:21 PM PDT 24
Peak memory 164748 kb
Host smart-66fe9428-7f77-4ee0-9dba-362939e888ba
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4222846778 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.4222846778
Directory /workspace/37.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.1216589873
Short name T132
Test name
Test status
Simulation time 1489050000 ps
CPU time 3.8 seconds
Started Jul 23 04:38:03 PM PDT 24
Finished Jul 23 04:38:13 PM PDT 24
Peak memory 164748 kb
Host smart-4b3618b8-3cf6-4159-9839-af0ce6e79684
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1216589873 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.1216589873
Directory /workspace/38.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.26773452
Short name T145
Test name
Test status
Simulation time 1574070000 ps
CPU time 4.16 seconds
Started Jul 23 04:38:04 PM PDT 24
Finished Jul 23 04:38:14 PM PDT 24
Peak memory 164672 kb
Host smart-702e05c5-c570-4b00-926a-b4a65576b6b7
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=26773452 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.26773452
Directory /workspace/39.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.4007007574
Short name T120
Test name
Test status
Simulation time 1533270000 ps
CPU time 4.28 seconds
Started Jul 23 04:38:02 PM PDT 24
Finished Jul 23 04:38:12 PM PDT 24
Peak memory 164776 kb
Host smart-e6500e34-11a4-4dfb-947c-0833e1280fd5
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4007007574 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.4007007574
Directory /workspace/4.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.3009875460
Short name T127
Test name
Test status
Simulation time 1357670000 ps
CPU time 3.41 seconds
Started Jul 23 04:39:08 PM PDT 24
Finished Jul 23 04:39:16 PM PDT 24
Peak memory 163128 kb
Host smart-7463dbbf-4841-475f-8da3-608d688387ca
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3009875460 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.3009875460
Directory /workspace/40.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.1919755606
Short name T141
Test name
Test status
Simulation time 1518030000 ps
CPU time 3.07 seconds
Started Jul 23 04:39:25 PM PDT 24
Finished Jul 23 04:39:33 PM PDT 24
Peak memory 164496 kb
Host smart-c9199357-657a-45df-be40-8fd2347901e1
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1919755606 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.1919755606
Directory /workspace/41.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.3618656584
Short name T135
Test name
Test status
Simulation time 1442450000 ps
CPU time 4.84 seconds
Started Jul 23 04:38:05 PM PDT 24
Finished Jul 23 04:38:17 PM PDT 24
Peak memory 164784 kb
Host smart-15167336-d6d5-41e4-81f1-a2ba55dbd8d3
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3618656584 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.3618656584
Directory /workspace/42.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1144430100
Short name T125
Test name
Test status
Simulation time 1643970000 ps
CPU time 4.09 seconds
Started Jul 23 04:39:08 PM PDT 24
Finished Jul 23 04:39:18 PM PDT 24
Peak memory 162592 kb
Host smart-aa8c7e54-ba54-48fb-8653-fd334f2ebe51
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1144430100 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.1144430100
Directory /workspace/43.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.357379610
Short name T121
Test name
Test status
Simulation time 1418050000 ps
CPU time 3.6 seconds
Started Jul 23 04:39:08 PM PDT 24
Finished Jul 23 04:39:17 PM PDT 24
Peak memory 162284 kb
Host smart-51c8f793-97f4-4a4b-a223-27cc800ed267
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=357379610 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.357379610
Directory /workspace/44.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.2758709326
Short name T147
Test name
Test status
Simulation time 1407470000 ps
CPU time 3.59 seconds
Started Jul 23 04:39:08 PM PDT 24
Finished Jul 23 04:39:17 PM PDT 24
Peak memory 162332 kb
Host smart-fd4ab21a-4538-4cae-b119-75565d091373
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2758709326 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.2758709326
Directory /workspace/45.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.3850427032
Short name T139
Test name
Test status
Simulation time 1488430000 ps
CPU time 4.49 seconds
Started Jul 23 04:38:05 PM PDT 24
Finished Jul 23 04:38:17 PM PDT 24
Peak memory 165040 kb
Host smart-570be918-7778-435b-9958-ebf3ece20111
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3850427032 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.3850427032
Directory /workspace/46.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.925169673
Short name T126
Test name
Test status
Simulation time 1573610000 ps
CPU time 4.88 seconds
Started Jul 23 04:38:01 PM PDT 24
Finished Jul 23 04:38:13 PM PDT 24
Peak memory 164700 kb
Host smart-daa1600e-2a5c-49f7-ae6d-20d021ad2f1c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=925169673 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.925169673
Directory /workspace/47.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.3929014029
Short name T143
Test name
Test status
Simulation time 1441430000 ps
CPU time 4.95 seconds
Started Jul 23 04:38:00 PM PDT 24
Finished Jul 23 04:38:11 PM PDT 24
Peak memory 164756 kb
Host smart-3720ea59-f865-48ab-bf9c-ff797c29003b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3929014029 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.3929014029
Directory /workspace/48.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.3145186310
Short name T130
Test name
Test status
Simulation time 1422210000 ps
CPU time 3.5 seconds
Started Jul 23 04:38:05 PM PDT 24
Finished Jul 23 04:38:14 PM PDT 24
Peak memory 164756 kb
Host smart-482006a2-92dc-4524-b818-863fd5646f42
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3145186310 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.3145186310
Directory /workspace/49.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.2818850120
Short name T112
Test name
Test status
Simulation time 1434250000 ps
CPU time 3 seconds
Started Jul 23 04:37:59 PM PDT 24
Finished Jul 23 04:38:06 PM PDT 24
Peak memory 164752 kb
Host smart-693359b2-cb4e-41aa-8075-7a5a1325786e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2818850120 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.2818850120
Directory /workspace/5.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.4207664582
Short name T148
Test name
Test status
Simulation time 1605570000 ps
CPU time 4.33 seconds
Started Jul 23 04:38:04 PM PDT 24
Finished Jul 23 04:38:14 PM PDT 24
Peak memory 164772 kb
Host smart-65c1d201-ba9b-4a56-9d58-3791a4521db7
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4207664582 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.4207664582
Directory /workspace/6.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.3495204314
Short name T119
Test name
Test status
Simulation time 1369210000 ps
CPU time 4.31 seconds
Started Jul 23 04:38:04 PM PDT 24
Finished Jul 23 04:38:14 PM PDT 24
Peak memory 164728 kb
Host smart-d94e01f4-6ded-4edb-b78d-683eb77df037
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3495204314 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.3495204314
Directory /workspace/7.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.4119105112
Short name T146
Test name
Test status
Simulation time 1359010000 ps
CPU time 3.37 seconds
Started Jul 23 04:38:03 PM PDT 24
Finished Jul 23 04:38:11 PM PDT 24
Peak memory 164756 kb
Host smart-c8864503-48b3-4c0e-becd-f96de42ebbdb
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4119105112 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.4119105112
Directory /workspace/8.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.1149100336
Short name T128
Test name
Test status
Simulation time 1457090000 ps
CPU time 3.35 seconds
Started Jul 23 04:38:02 PM PDT 24
Finished Jul 23 04:38:11 PM PDT 24
Peak memory 164740 kb
Host smart-cfcce821-b467-450f-aec6-77c637f93995
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1149100336 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.1149100336
Directory /workspace/9.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.2335361387
Short name T46
Test name
Test status
Simulation time 1462670000 ps
CPU time 5.21 seconds
Started Jul 23 05:18:04 PM PDT 24
Finished Jul 23 05:18:17 PM PDT 24
Peak memory 164932 kb
Host smart-fa4f3788-ac35-4f12-91da-9b49b7a91794
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2335361387 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.2335361387
Directory /workspace/0.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.785024439
Short name T32
Test name
Test status
Simulation time 1304170000 ps
CPU time 3.98 seconds
Started Jul 23 05:18:03 PM PDT 24
Finished Jul 23 05:18:13 PM PDT 24
Peak memory 164916 kb
Host smart-275f63f5-3538-4e6f-a8c5-6bfbb6eb6055
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=785024439 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.785024439
Directory /workspace/10.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.659210722
Short name T41
Test name
Test status
Simulation time 1504390000 ps
CPU time 4.75 seconds
Started Jul 23 05:18:06 PM PDT 24
Finished Jul 23 05:18:17 PM PDT 24
Peak memory 164964 kb
Host smart-ba9c1268-f4e8-4435-ad8c-2c2a65e62809
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=659210722 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.659210722
Directory /workspace/11.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.3766752339
Short name T8
Test name
Test status
Simulation time 1405670000 ps
CPU time 4.9 seconds
Started Jul 23 05:18:05 PM PDT 24
Finished Jul 23 05:18:17 PM PDT 24
Peak memory 164908 kb
Host smart-9849d2e6-00ba-426d-a0f6-d1ed9fbe561b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3766752339 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.3766752339
Directory /workspace/12.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.1836321444
Short name T52
Test name
Test status
Simulation time 1518230000 ps
CPU time 3.58 seconds
Started Jul 23 05:18:17 PM PDT 24
Finished Jul 23 05:18:26 PM PDT 24
Peak memory 166204 kb
Host smart-a060d917-7a4d-4307-88e5-c945af29db32
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1836321444 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.1836321444
Directory /workspace/13.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.3901845223
Short name T51
Test name
Test status
Simulation time 1426590000 ps
CPU time 3.85 seconds
Started Jul 23 05:18:14 PM PDT 24
Finished Jul 23 05:18:23 PM PDT 24
Peak memory 164908 kb
Host smart-956cfb2b-7b8e-4ae5-8bf1-5c4b644cab4f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3901845223 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.3901845223
Directory /workspace/14.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.3353623923
Short name T63
Test name
Test status
Simulation time 1577710000 ps
CPU time 4.23 seconds
Started Jul 23 05:18:14 PM PDT 24
Finished Jul 23 05:18:24 PM PDT 24
Peak memory 164972 kb
Host smart-4b5dfb69-70f9-4a95-ad17-163a01273340
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3353623923 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.3353623923
Directory /workspace/15.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.271091838
Short name T33
Test name
Test status
Simulation time 1436770000 ps
CPU time 4.27 seconds
Started Jul 23 05:18:13 PM PDT 24
Finished Jul 23 05:18:24 PM PDT 24
Peak memory 164964 kb
Host smart-426c274d-07f7-4ea7-af08-65478ebca744
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=271091838 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.271091838
Directory /workspace/16.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.962616238
Short name T7
Test name
Test status
Simulation time 1507070000 ps
CPU time 4.68 seconds
Started Jul 23 05:18:13 PM PDT 24
Finished Jul 23 05:18:25 PM PDT 24
Peak memory 164928 kb
Host smart-938a81ed-7503-48c3-849d-98e07d414b01
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=962616238 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.962616238
Directory /workspace/17.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.3257534388
Short name T43
Test name
Test status
Simulation time 1460210000 ps
CPU time 4.71 seconds
Started Jul 23 05:18:16 PM PDT 24
Finished Jul 23 05:18:28 PM PDT 24
Peak memory 164912 kb
Host smart-2aef99f0-3c99-4c63-af87-ad16fca40d45
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3257534388 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.3257534388
Directory /workspace/18.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.3746797943
Short name T9
Test name
Test status
Simulation time 1584910000 ps
CPU time 3.93 seconds
Started Jul 23 05:18:10 PM PDT 24
Finished Jul 23 05:18:20 PM PDT 24
Peak memory 164916 kb
Host smart-ecbf246f-527e-4c8e-bd34-1234b06f788d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3746797943 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.3746797943
Directory /workspace/19.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.4264502186
Short name T40
Test name
Test status
Simulation time 1434050000 ps
CPU time 4.34 seconds
Started Jul 23 05:18:03 PM PDT 24
Finished Jul 23 05:18:13 PM PDT 24
Peak memory 164900 kb
Host smart-1fa92496-ede2-4fbe-9796-dbee7bb56dd5
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4264502186 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.4264502186
Directory /workspace/2.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.2973034738
Short name T59
Test name
Test status
Simulation time 1513730000 ps
CPU time 5.88 seconds
Started Jul 23 05:18:11 PM PDT 24
Finished Jul 23 05:18:25 PM PDT 24
Peak memory 164876 kb
Host smart-c1668ae8-d2dd-491b-84ff-0bf7ae5c0508
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2973034738 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.2973034738
Directory /workspace/20.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.3876299843
Short name T66
Test name
Test status
Simulation time 1391550000 ps
CPU time 3.69 seconds
Started Jul 23 05:18:17 PM PDT 24
Finished Jul 23 05:18:26 PM PDT 24
Peak memory 164940 kb
Host smart-d195a570-01ae-437e-8824-14dc8dc4c87b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3876299843 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.3876299843
Directory /workspace/21.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.3594248564
Short name T69
Test name
Test status
Simulation time 1516810000 ps
CPU time 3.59 seconds
Started Jul 23 05:18:16 PM PDT 24
Finished Jul 23 05:18:26 PM PDT 24
Peak memory 164880 kb
Host smart-0a7806a5-cbd0-4c59-b81a-3a53df68c248
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3594248564 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.3594248564
Directory /workspace/22.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.693828809
Short name T58
Test name
Test status
Simulation time 1155370000 ps
CPU time 4.94 seconds
Started Jul 23 05:18:14 PM PDT 24
Finished Jul 23 05:18:26 PM PDT 24
Peak memory 164956 kb
Host smart-e9acface-7738-4ac7-9516-8171b3ab610f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=693828809 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.693828809
Directory /workspace/23.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.62307668
Short name T68
Test name
Test status
Simulation time 1493510000 ps
CPU time 4.65 seconds
Started Jul 23 05:18:12 PM PDT 24
Finished Jul 23 05:18:23 PM PDT 24
Peak memory 164860 kb
Host smart-aaa42fb3-09e6-4b34-b830-05419b20fa13
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=62307668 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.62307668
Directory /workspace/24.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.2792285269
Short name T39
Test name
Test status
Simulation time 1144570000 ps
CPU time 4.1 seconds
Started Jul 23 05:18:11 PM PDT 24
Finished Jul 23 05:18:21 PM PDT 24
Peak memory 164920 kb
Host smart-a03f66f1-0770-4073-8240-44892dfbbcee
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2792285269 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.2792285269
Directory /workspace/25.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.675841557
Short name T3
Test name
Test status
Simulation time 1471050000 ps
CPU time 4.9 seconds
Started Jul 23 05:18:16 PM PDT 24
Finished Jul 23 05:18:28 PM PDT 24
Peak memory 164908 kb
Host smart-0637c9e5-46b0-4b86-a031-239a74c2e384
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=675841557 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.675841557
Directory /workspace/26.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.3673082703
Short name T50
Test name
Test status
Simulation time 1382270000 ps
CPU time 5.76 seconds
Started Jul 23 05:18:13 PM PDT 24
Finished Jul 23 05:18:26 PM PDT 24
Peak memory 164960 kb
Host smart-77edb326-8d98-48fc-8ac7-a9e74c989c85
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3673082703 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.3673082703
Directory /workspace/27.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.806334362
Short name T38
Test name
Test status
Simulation time 1555850000 ps
CPU time 5.47 seconds
Started Jul 23 05:18:13 PM PDT 24
Finished Jul 23 05:18:26 PM PDT 24
Peak memory 164924 kb
Host smart-ef827a5a-145e-4f85-b0e6-ee46347e419f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=806334362 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.806334362
Directory /workspace/28.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.18279570
Short name T12
Test name
Test status
Simulation time 1557570000 ps
CPU time 5.72 seconds
Started Jul 23 05:18:12 PM PDT 24
Finished Jul 23 05:18:26 PM PDT 24
Peak memory 164820 kb
Host smart-71463ad2-e562-4935-b19f-ce888b702c97
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=18279570 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.18279570
Directory /workspace/29.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.2919846241
Short name T11
Test name
Test status
Simulation time 1237050000 ps
CPU time 4.9 seconds
Started Jul 23 05:18:05 PM PDT 24
Finished Jul 23 05:18:18 PM PDT 24
Peak memory 164972 kb
Host smart-172c1440-f738-4524-b41c-8d35159e99c9
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2919846241 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.2919846241
Directory /workspace/3.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.1994980621
Short name T49
Test name
Test status
Simulation time 1377130000 ps
CPU time 3.7 seconds
Started Jul 23 05:18:12 PM PDT 24
Finished Jul 23 05:18:22 PM PDT 24
Peak memory 164896 kb
Host smart-060abf00-473c-4319-b39d-202cb61eda30
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1994980621 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.1994980621
Directory /workspace/30.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.3410738225
Short name T44
Test name
Test status
Simulation time 1517430000 ps
CPU time 3.65 seconds
Started Jul 23 05:18:17 PM PDT 24
Finished Jul 23 05:18:27 PM PDT 24
Peak memory 164940 kb
Host smart-7c364ed0-245c-4de9-806c-6403c9aa9bfe
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3410738225 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.3410738225
Directory /workspace/31.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.4170168300
Short name T65
Test name
Test status
Simulation time 1556750000 ps
CPU time 4.8 seconds
Started Jul 23 05:18:12 PM PDT 24
Finished Jul 23 05:18:24 PM PDT 24
Peak memory 164892 kb
Host smart-578e629a-6b46-43f7-8cd9-1794d7831101
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4170168300 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.4170168300
Directory /workspace/32.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.4224514108
Short name T56
Test name
Test status
Simulation time 1481530000 ps
CPU time 5.1 seconds
Started Jul 23 05:18:12 PM PDT 24
Finished Jul 23 05:18:26 PM PDT 24
Peak memory 164936 kb
Host smart-5975da26-98ba-4439-a393-27957cb3ee2e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4224514108 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.4224514108
Directory /workspace/33.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.2257750540
Short name T47
Test name
Test status
Simulation time 1548590000 ps
CPU time 5 seconds
Started Jul 23 05:18:16 PM PDT 24
Finished Jul 23 05:18:29 PM PDT 24
Peak memory 164912 kb
Host smart-038b2d18-2e00-45dd-b696-859b2b1d845d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2257750540 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.2257750540
Directory /workspace/34.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.1108136956
Short name T10
Test name
Test status
Simulation time 1506850000 ps
CPU time 4.33 seconds
Started Jul 23 05:18:12 PM PDT 24
Finished Jul 23 05:18:22 PM PDT 24
Peak memory 164916 kb
Host smart-73f24f2f-3107-4750-b4eb-c7e4e25c509b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1108136956 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.1108136956
Directory /workspace/35.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.2685463516
Short name T31
Test name
Test status
Simulation time 1446370000 ps
CPU time 5.13 seconds
Started Jul 23 05:18:14 PM PDT 24
Finished Jul 23 05:18:27 PM PDT 24
Peak memory 164936 kb
Host smart-3c206f00-7fb3-4e57-a098-b7acaae7dae0
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2685463516 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.2685463516
Directory /workspace/36.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.3032338968
Short name T42
Test name
Test status
Simulation time 1425070000 ps
CPU time 5.15 seconds
Started Jul 23 05:18:14 PM PDT 24
Finished Jul 23 05:18:27 PM PDT 24
Peak memory 164928 kb
Host smart-55bd44f1-9d98-4ec0-906f-591353554291
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3032338968 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.3032338968
Directory /workspace/37.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.812896281
Short name T45
Test name
Test status
Simulation time 1500010000 ps
CPU time 3.69 seconds
Started Jul 23 05:18:12 PM PDT 24
Finished Jul 23 05:18:21 PM PDT 24
Peak memory 164816 kb
Host smart-830b6175-517e-4435-ad99-e06f63f4981e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=812896281 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.812896281
Directory /workspace/38.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.1267861135
Short name T36
Test name
Test status
Simulation time 1438150000 ps
CPU time 3.58 seconds
Started Jul 23 05:18:16 PM PDT 24
Finished Jul 23 05:18:25 PM PDT 24
Peak memory 164940 kb
Host smart-0467097c-031f-4ee1-851c-ff747e3d6d09
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1267861135 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.1267861135
Directory /workspace/39.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.2424906731
Short name T60
Test name
Test status
Simulation time 1291290000 ps
CPU time 4.96 seconds
Started Jul 23 05:18:04 PM PDT 24
Finished Jul 23 05:18:15 PM PDT 24
Peak memory 164948 kb
Host smart-cf0074d0-9b67-47e6-8ed1-168bbc8f2354
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2424906731 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.2424906731
Directory /workspace/4.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.772553458
Short name T53
Test name
Test status
Simulation time 1491170000 ps
CPU time 4.4 seconds
Started Jul 23 05:18:14 PM PDT 24
Finished Jul 23 05:18:24 PM PDT 24
Peak memory 164904 kb
Host smart-1cbb1033-8e5e-4c7c-8cb5-212585fce786
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=772553458 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.772553458
Directory /workspace/40.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.2138291425
Short name T64
Test name
Test status
Simulation time 1495610000 ps
CPU time 4.11 seconds
Started Jul 23 05:18:22 PM PDT 24
Finished Jul 23 05:18:31 PM PDT 24
Peak memory 164916 kb
Host smart-a06e3eab-b3fc-4216-9752-a1f01973cf1d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2138291425 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.2138291425
Directory /workspace/41.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.1545152038
Short name T34
Test name
Test status
Simulation time 1300210000 ps
CPU time 3.93 seconds
Started Jul 23 05:18:20 PM PDT 24
Finished Jul 23 05:18:31 PM PDT 24
Peak memory 164904 kb
Host smart-e8e0c737-c3a8-483b-809e-01eb65cb8944
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1545152038 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.1545152038
Directory /workspace/42.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.1623240469
Short name T70
Test name
Test status
Simulation time 1588870000 ps
CPU time 3.42 seconds
Started Jul 23 05:18:20 PM PDT 24
Finished Jul 23 05:18:29 PM PDT 24
Peak memory 164900 kb
Host smart-5c719968-787e-442d-a351-a2295305c448
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1623240469 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.1623240469
Directory /workspace/43.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.518017470
Short name T35
Test name
Test status
Simulation time 1570490000 ps
CPU time 5.71 seconds
Started Jul 23 05:18:21 PM PDT 24
Finished Jul 23 05:18:34 PM PDT 24
Peak memory 164912 kb
Host smart-a0855a83-be1f-48c1-992b-a2f43841a141
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=518017470 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.518017470
Directory /workspace/44.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.1680670135
Short name T54
Test name
Test status
Simulation time 1567070000 ps
CPU time 4.38 seconds
Started Jul 23 05:18:21 PM PDT 24
Finished Jul 23 05:18:31 PM PDT 24
Peak memory 164932 kb
Host smart-7de1d3f3-3c89-4bb4-aaee-b9a5aa48871f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1680670135 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.1680670135
Directory /workspace/45.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.3721037016
Short name T37
Test name
Test status
Simulation time 1418270000 ps
CPU time 5.48 seconds
Started Jul 23 05:18:21 PM PDT 24
Finished Jul 23 05:18:33 PM PDT 24
Peak memory 164932 kb
Host smart-f2ef8c6d-af73-45f3-bb02-ad07c4008085
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3721037016 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.3721037016
Directory /workspace/46.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.631914954
Short name T13
Test name
Test status
Simulation time 1596090000 ps
CPU time 6.22 seconds
Started Jul 23 05:18:21 PM PDT 24
Finished Jul 23 05:18:34 PM PDT 24
Peak memory 164916 kb
Host smart-166cecd6-0d8b-4862-a863-4be756419e69
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=631914954 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.631914954
Directory /workspace/47.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.322140280
Short name T62
Test name
Test status
Simulation time 1502830000 ps
CPU time 5.36 seconds
Started Jul 23 05:18:19 PM PDT 24
Finished Jul 23 05:18:33 PM PDT 24
Peak memory 164876 kb
Host smart-2c08f259-339d-448a-9cb3-4d8ebbd8ceae
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=322140280 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.322140280
Directory /workspace/48.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.3555752253
Short name T61
Test name
Test status
Simulation time 1567770000 ps
CPU time 5.57 seconds
Started Jul 23 05:18:20 PM PDT 24
Finished Jul 23 05:18:34 PM PDT 24
Peak memory 164944 kb
Host smart-e0a66f76-4e62-46a5-a601-112c0690ca3c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3555752253 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.3555752253
Directory /workspace/49.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.3385815673
Short name T2
Test name
Test status
Simulation time 1121990000 ps
CPU time 3.82 seconds
Started Jul 23 05:18:04 PM PDT 24
Finished Jul 23 05:18:13 PM PDT 24
Peak memory 164972 kb
Host smart-e68b9c28-0991-4d7d-b1bb-884a1bd822f2
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3385815673 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.3385815673
Directory /workspace/5.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.1273833364
Short name T55
Test name
Test status
Simulation time 1329730000 ps
CPU time 4.39 seconds
Started Jul 23 05:18:03 PM PDT 24
Finished Jul 23 05:18:13 PM PDT 24
Peak memory 164932 kb
Host smart-830d5a2a-68b7-415a-adcc-10ece2ba9d09
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1273833364 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.1273833364
Directory /workspace/6.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.286430120
Short name T48
Test name
Test status
Simulation time 1372850000 ps
CPU time 4.39 seconds
Started Jul 23 05:18:04 PM PDT 24
Finished Jul 23 05:18:15 PM PDT 24
Peak memory 164828 kb
Host smart-18b6ebcd-5a44-4ba4-ab90-899c83d1b5ac
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=286430120 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.286430120
Directory /workspace/7.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.909404128
Short name T67
Test name
Test status
Simulation time 1354010000 ps
CPU time 4.32 seconds
Started Jul 23 05:18:06 PM PDT 24
Finished Jul 23 05:18:16 PM PDT 24
Peak memory 164892 kb
Host smart-4ce3428e-a3c6-41cc-8d7c-7f7820a425ec
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=909404128 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.909404128
Directory /workspace/8.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.1058515725
Short name T57
Test name
Test status
Simulation time 1307810000 ps
CPU time 3.92 seconds
Started Jul 23 05:18:04 PM PDT 24
Finished Jul 23 05:18:14 PM PDT 24
Peak memory 164916 kb
Host smart-d1b8c85e-082f-4270-9dd1-c1e3310a2aa2
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1058515725 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.1058515725
Directory /workspace/9.prim_lfsr_gal_smoke/latest
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