| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 98.31 | 100.00 | 96.55 | 100.00 | 100.00 | 95.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 87.31 | 87.31 | 100.00 | 100.00 | 96.55 | 96.55 | 100.00 | 100.00 | 100.00 | 100.00 | 40.00 | 40.00 | /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.958375027 | ||
| 96.81 | 9.50 | 100.00 | 0.00 | 96.55 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 87.50 | 47.50 | /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.3910665203 | ||
| 98.31 | 1.50 | 100.00 | 0.00 | 96.55 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 95.00 | 7.50 | /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.2118430593 | ||
| Name |
|---|
| /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.3081058120 |
| /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.94075111 |
| /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.430144156 |
| /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.2738920439 |
| /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.2563164586 |
| /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.1288011128 |
| /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.1967829471 |
| /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.1265139445 |
| /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.420986685 |
| /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.1630129297 |
| /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.3609697534 |
| /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.3579341613 |
| /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.4286199796 |
| /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.3140025097 |
| /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.4068859158 |
| /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.2354629018 |
| /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.1842668811 |
| /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.43111227 |
| /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.3158419317 |
| /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.4071260049 |
| /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.4177319838 |
| /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.3613761108 |
| /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.1783628857 |
| /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.1165622761 |
| /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.410133132 |
| /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.3987310536 |
| /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.1573704289 |
| /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.3724678322 |
| /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.1887251521 |
| /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.509931291 |
| /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.115821447 |
| /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.3071835960 |
| /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.175870369 |
| /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.3831168936 |
| /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.1409609918 |
| /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.3005804453 |
| /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.395579603 |
| /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.771894622 |
| /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.973910553 |
| /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.1863225061 |
| /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.206960829 |
| /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.52146386 |
| /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.1856313312 |
| /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.2475001508 |
| /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.277454451 |
| /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.4268265249 |
| /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.2084939453 |
| /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.120191535 |
| /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.4104874943 |
| /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.4217227797 |
| /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.2008842449 |
| /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.1052548643 |
| /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.1229386013 |
| /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.1515088932 |
| /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.4094445440 |
| /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.3380651070 |
| /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.3843588931 |
| /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.1917601337 |
| /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.232220063 |
| /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.691781890 |
| /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.1675949879 |
| /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.120946572 |
| /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3965860644 |
| /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.3208123867 |
| /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.2825997357 |
| /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.2448588850 |
| /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.1108570442 |
| /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.2491285964 |
| /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.855130484 |
| /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.3812752910 |
| /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.4238230312 |
| /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.3573856731 |
| /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.460143003 |
| /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.4121335178 |
| /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.970043147 |
| /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.3731636988 |
| /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.1207896083 |
| /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.241873099 |
| /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.3090583297 |
| /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.2595792925 |
| /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3990016997 |
| /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.1456931526 |
| /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.1218736982 |
| /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.82914600 |
| /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.3230463779 |
| /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.730027742 |
| /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.2446137436 |
| /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.2927146806 |
| /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.1575157235 |
| /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.3402636495 |
| /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.2145493201 |
| /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1993098448 |
| /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.1176924087 |
| /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.2759941473 |
| /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.887344595 |
| /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.1267565911 |
| /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.1375347018 |
| /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.2940790741 |
| /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.1099735785 |
| /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.1907483416 |
| /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.577039305 |
| /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.4272282425 |
| /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.2985006431 |
| /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.1243718498 |
| /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.1949743200 |
| /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.448772739 |
| /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.3794010110 |
| /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.1060663600 |
| /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.2800589473 |
| /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.578343816 |
| /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.1847021853 |
| /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.2550928526 |
| /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.934726961 |
| /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.2003648844 |
| /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.555033716 |
| /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.1443910553 |
| /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.4140020456 |
| /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.3294418265 |
| /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.483234533 |
| /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.733025046 |
| /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.2770130266 |
| /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.3235349060 |
| /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.2737655753 |
| /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.3798417105 |
| /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.2791936823 |
| /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.3936911843 |
| /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.3468197890 |
| /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.1439660227 |
| /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.3310886328 |
| /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.2619604633 |
| /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.2745306529 |
| /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.3511701153 |
| /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.227210233 |
| /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.1245164047 |
| /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.1713900778 |
| /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.1062348534 |
| /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.3313528828 |
| /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.2160838896 |
| /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.1581666589 |
| /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.3235166323 |
| /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.3974546882 |
| /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.1664913256 |
| /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.1491236390 |
| /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.2636542615 |
| /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.4282923654 |
| /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.3923640440 |
| /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.538411454 |
| /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.452033741 |
| /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.3070640898 |
| /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.4184758491 |
| /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.501942410 |
| /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.1811612119 |
| /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.2434713734 |
| /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.3326452024 |
| /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.3457215579 |
| /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.605249276 |
| /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.2905385208 |
| /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.2423394553 |
| /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.2997959043 |
| /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.2101766803 |
| /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.3314642564 |
| /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.2637402774 |
| /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.3571258154 |
| /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.2529364718 |
| /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.577682844 |
| /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.4070284558 |
| /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.192366549 |
| /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.1563357387 |
| /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.244887745 |
| /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.837830137 |
| /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.611533887 |
| /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.2412831094 |
| /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.3818368587 |
| /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.498720365 |
| /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.1112051346 |
| /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.3590575351 |
| /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.1191755725 |
| /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.4180297555 |
| /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.2092340408 |
| /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.96292645 |
| /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.2573155847 |
| /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.1447988757 |
| /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.296258008 |
| /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.455350910 |
| /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.2031303909 |
| /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.3303074844 |
| /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.3951457086 |
| /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.1697646387 |
| /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.1022700352 |
| /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.3555400698 |
| /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.130732410 |
| /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.3360739074 |
| /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.3084051481 |
| /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.2913536266 |
| /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.477728620 |
| /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.435594027 |
| /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.1340179092 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.611533887 | Jul 25 04:24:57 PM PDT 24 | Jul 25 04:25:06 PM PDT 24 | 1327910000 ps | ||
| T2 | /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.1340179092 | Jul 25 04:24:36 PM PDT 24 | Jul 25 04:24:45 PM PDT 24 | 1429950000 ps | ||
| T3 | /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.2101766803 | Jul 25 04:23:06 PM PDT 24 | Jul 25 04:23:18 PM PDT 24 | 1666130000 ps | ||
| T7 | /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.1697646387 | Jul 25 04:24:12 PM PDT 24 | Jul 25 04:24:22 PM PDT 24 | 1533910000 ps | ||
| T8 | /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.4184758491 | Jul 25 04:24:29 PM PDT 24 | Jul 25 04:24:38 PM PDT 24 | 1591510000 ps | ||
| T9 | /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.244887745 | Jul 25 04:24:13 PM PDT 24 | Jul 25 04:24:20 PM PDT 24 | 1397370000 ps | ||
| T10 | /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.605249276 | Jul 25 04:24:48 PM PDT 24 | Jul 25 04:24:56 PM PDT 24 | 1342950000 ps | ||
| T11 | /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.2031303909 | Jul 25 04:20:20 PM PDT 24 | Jul 25 04:20:29 PM PDT 24 | 1435550000 ps | ||
| T12 | /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.958375027 | Jul 25 04:20:10 PM PDT 24 | Jul 25 04:20:22 PM PDT 24 | 1438530000 ps | ||
| T13 | /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.96292645 | Jul 25 04:25:03 PM PDT 24 | Jul 25 04:25:11 PM PDT 24 | 1474990000 ps | ||
| T31 | /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.2905385208 | Jul 25 04:24:48 PM PDT 24 | Jul 25 04:24:55 PM PDT 24 | 1497430000 ps | ||
| T32 | /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.501942410 | Jul 25 04:24:20 PM PDT 24 | Jul 25 04:24:26 PM PDT 24 | 1375550000 ps | ||
| T33 | /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.2434713734 | Jul 25 04:21:57 PM PDT 24 | Jul 25 04:22:07 PM PDT 24 | 1545550000 ps | ||
| T34 | /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.3084051481 | Jul 25 04:21:22 PM PDT 24 | Jul 25 04:21:32 PM PDT 24 | 1381190000 ps | ||
| T35 | /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.1563357387 | Jul 25 04:24:36 PM PDT 24 | Jul 25 04:24:45 PM PDT 24 | 1489630000 ps | ||
| T36 | /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.3326452024 | Jul 25 04:21:38 PM PDT 24 | Jul 25 04:21:48 PM PDT 24 | 1461170000 ps | ||
| T37 | /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.2637402774 | Jul 25 04:21:09 PM PDT 24 | Jul 25 04:21:17 PM PDT 24 | 1493070000 ps | ||
| T38 | /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.2423394553 | Jul 25 04:24:49 PM PDT 24 | Jul 25 04:24:54 PM PDT 24 | 1081910000 ps | ||
| T39 | /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.3555400698 | Jul 25 04:24:29 PM PDT 24 | Jul 25 04:24:37 PM PDT 24 | 1418210000 ps | ||
| T40 | /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.3571258154 | Jul 25 04:21:53 PM PDT 24 | Jul 25 04:22:04 PM PDT 24 | 1517530000 ps | ||
| T41 | /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.498720365 | Jul 25 04:24:11 PM PDT 24 | Jul 25 04:24:19 PM PDT 24 | 1483270000 ps | ||
| T42 | /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.2997959043 | Jul 25 04:19:29 PM PDT 24 | Jul 25 04:19:37 PM PDT 24 | 1234610000 ps | ||
| T43 | /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.3314642564 | Jul 25 04:22:16 PM PDT 24 | Jul 25 04:22:27 PM PDT 24 | 1550990000 ps | ||
| T44 | /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.3951457086 | Jul 25 04:24:22 PM PDT 24 | Jul 25 04:24:31 PM PDT 24 | 1553810000 ps | ||
| T45 | /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.1191755725 | Jul 25 04:22:34 PM PDT 24 | Jul 25 04:22:46 PM PDT 24 | 1610850000 ps | ||
| T46 | /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.2529364718 | Jul 25 04:21:09 PM PDT 24 | Jul 25 04:21:21 PM PDT 24 | 1607230000 ps | ||
| T47 | /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.837830137 | Jul 25 04:22:41 PM PDT 24 | Jul 25 04:22:51 PM PDT 24 | 1371290000 ps | ||
| T48 | /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.1811612119 | Jul 25 04:24:30 PM PDT 24 | Jul 25 04:24:37 PM PDT 24 | 1515910000 ps | ||
| T49 | /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.4070284558 | Jul 25 04:20:26 PM PDT 24 | Jul 25 04:20:34 PM PDT 24 | 1269730000 ps | ||
| T50 | /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.3360739074 | Jul 25 04:25:06 PM PDT 24 | Jul 25 04:25:14 PM PDT 24 | 1296190000 ps | ||
| T51 | /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.296258008 | Jul 25 04:24:31 PM PDT 24 | Jul 25 04:24:38 PM PDT 24 | 1521330000 ps | ||
| T52 | /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.455350910 | Jul 25 04:25:04 PM PDT 24 | Jul 25 04:25:12 PM PDT 24 | 1529890000 ps | ||
| T53 | /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.192366549 | Jul 25 04:22:29 PM PDT 24 | Jul 25 04:22:39 PM PDT 24 | 1491390000 ps | ||
| T54 | /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.3457215579 | Jul 25 04:24:37 PM PDT 24 | Jul 25 04:24:46 PM PDT 24 | 1503210000 ps | ||
| T55 | /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.2913536266 | Jul 25 04:20:09 PM PDT 24 | Jul 25 04:20:21 PM PDT 24 | 1538610000 ps | ||
| T56 | /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.130732410 | Jul 25 04:24:13 PM PDT 24 | Jul 25 04:24:20 PM PDT 24 | 1510610000 ps | ||
| T57 | /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.3818368587 | Jul 25 04:24:35 PM PDT 24 | Jul 25 04:24:44 PM PDT 24 | 1481530000 ps | ||
| T58 | /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.477728620 | Jul 25 04:20:36 PM PDT 24 | Jul 25 04:20:46 PM PDT 24 | 1431290000 ps | ||
| T59 | /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.1112051346 | Jul 25 04:24:26 PM PDT 24 | Jul 25 04:24:33 PM PDT 24 | 1537950000 ps | ||
| T60 | /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.3303074844 | Jul 25 04:24:23 PM PDT 24 | Jul 25 04:24:31 PM PDT 24 | 1528270000 ps | ||
| T61 | /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.2092340408 | Jul 25 04:24:01 PM PDT 24 | Jul 25 04:24:09 PM PDT 24 | 1420310000 ps | ||
| T62 | /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.1022700352 | Jul 25 04:23:09 PM PDT 24 | Jul 25 04:23:20 PM PDT 24 | 1575550000 ps | ||
| T63 | /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.435594027 | Jul 25 04:24:36 PM PDT 24 | Jul 25 04:24:45 PM PDT 24 | 1493590000 ps | ||
| T64 | /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.2412831094 | Jul 25 04:24:13 PM PDT 24 | Jul 25 04:24:20 PM PDT 24 | 1301350000 ps | ||
| T65 | /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.4180297555 | Jul 25 04:22:29 PM PDT 24 | Jul 25 04:22:39 PM PDT 24 | 1577830000 ps | ||
| T66 | /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.3070640898 | Jul 25 04:22:35 PM PDT 24 | Jul 25 04:22:45 PM PDT 24 | 1563730000 ps | ||
| T67 | /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.2573155847 | Jul 25 04:24:12 PM PDT 24 | Jul 25 04:24:22 PM PDT 24 | 1490310000 ps | ||
| T68 | /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.3590575351 | Jul 25 04:24:11 PM PDT 24 | Jul 25 04:24:19 PM PDT 24 | 1369090000 ps | ||
| T69 | /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.577682844 | Jul 25 04:24:24 PM PDT 24 | Jul 25 04:24:35 PM PDT 24 | 1563970000 ps | ||
| T70 | /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.1447988757 | Jul 25 04:24:29 PM PDT 24 | Jul 25 04:24:38 PM PDT 24 | 1467390000 ps | ||
| T4 | /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.277454451 | Jul 25 04:19:25 PM PDT 24 | Jul 25 04:51:36 PM PDT 24 | 336459550000 ps | ||
| T5 | /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.973910553 | Jul 25 04:21:09 PM PDT 24 | Jul 25 04:54:34 PM PDT 24 | 336463910000 ps | ||
| T6 | /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.115821447 | Jul 25 04:24:12 PM PDT 24 | Jul 25 04:52:20 PM PDT 24 | 336415170000 ps | ||
| T14 | /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.3910665203 | Jul 25 04:20:07 PM PDT 24 | Jul 25 04:54:21 PM PDT 24 | 336402030000 ps | ||
| T15 | /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.1573704289 | Jul 25 04:22:41 PM PDT 24 | Jul 25 04:55:58 PM PDT 24 | 336378450000 ps | ||
| T16 | /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.3987310536 | Jul 25 04:24:56 PM PDT 24 | Jul 25 04:51:16 PM PDT 24 | 336561330000 ps | ||
| T17 | /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.4071260049 | Jul 25 04:24:24 PM PDT 24 | Jul 25 04:53:40 PM PDT 24 | 337050530000 ps | ||
| T18 | /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.1165622761 | Jul 25 04:21:09 PM PDT 24 | Jul 25 04:48:46 PM PDT 24 | 336613390000 ps | ||
| T19 | /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.120191535 | Jul 25 04:19:28 PM PDT 24 | Jul 25 04:52:01 PM PDT 24 | 336902970000 ps | ||
| T20 | /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.4104874943 | Jul 25 04:19:28 PM PDT 24 | Jul 25 04:48:39 PM PDT 24 | 336525350000 ps | ||
| T71 | /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.1783628857 | Jul 25 04:19:27 PM PDT 24 | Jul 25 04:51:11 PM PDT 24 | 336945250000 ps | ||
| T72 | /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.3071835960 | Jul 25 04:20:22 PM PDT 24 | Jul 25 04:54:44 PM PDT 24 | 336859690000 ps | ||
| T73 | /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.52146386 | Jul 25 04:21:05 PM PDT 24 | Jul 25 04:51:03 PM PDT 24 | 336367590000 ps | ||
| T74 | /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.771894622 | Jul 25 04:24:26 PM PDT 24 | Jul 25 04:54:49 PM PDT 24 | 337090570000 ps | ||
| T75 | /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.2563164586 | Jul 25 04:20:22 PM PDT 24 | Jul 25 04:46:57 PM PDT 24 | 336648250000 ps | ||
| T76 | /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.509931291 | Jul 25 04:22:02 PM PDT 24 | Jul 25 04:49:12 PM PDT 24 | 336888530000 ps | ||
| T77 | /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.3609697534 | Jul 25 04:20:28 PM PDT 24 | Jul 25 04:49:07 PM PDT 24 | 337046010000 ps | ||
| T78 | /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.430144156 | Jul 25 04:20:26 PM PDT 24 | Jul 25 04:50:08 PM PDT 24 | 336415230000 ps | ||
| T79 | /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.1409609918 | Jul 25 04:24:29 PM PDT 24 | Jul 25 04:49:47 PM PDT 24 | 337056110000 ps | ||
| T80 | /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.206960829 | Jul 25 04:24:19 PM PDT 24 | Jul 25 04:49:04 PM PDT 24 | 336467390000 ps | ||
| T81 | /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.175870369 | Jul 25 04:20:20 PM PDT 24 | Jul 25 04:54:15 PM PDT 24 | 336829330000 ps | ||
| T82 | /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.3613761108 | Jul 25 04:22:46 PM PDT 24 | Jul 25 04:52:49 PM PDT 24 | 336898870000 ps | ||
| T83 | /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.3724678322 | Jul 25 04:24:23 PM PDT 24 | Jul 25 04:54:00 PM PDT 24 | 336624630000 ps | ||
| T84 | /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.1265139445 | Jul 25 04:20:07 PM PDT 24 | Jul 25 04:54:17 PM PDT 24 | 337019470000 ps | ||
| T85 | /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.3158419317 | Jul 25 04:23:13 PM PDT 24 | Jul 25 04:57:09 PM PDT 24 | 337037310000 ps | ||
| T86 | /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.4268265249 | Jul 25 04:19:27 PM PDT 24 | Jul 25 04:52:37 PM PDT 24 | 337068190000 ps | ||
| T87 | /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.1863225061 | Jul 25 04:21:09 PM PDT 24 | Jul 25 04:54:24 PM PDT 24 | 336975170000 ps | ||
| T88 | /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.1856313312 | Jul 25 04:21:03 PM PDT 24 | Jul 25 04:51:01 PM PDT 24 | 336706670000 ps | ||
| T89 | /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.410133132 | Jul 25 04:20:07 PM PDT 24 | Jul 25 04:52:25 PM PDT 24 | 336740870000 ps | ||
| T90 | /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.1630129297 | Jul 25 04:24:24 PM PDT 24 | Jul 25 04:55:14 PM PDT 24 | 336646110000 ps | ||
| T91 | /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.94075111 | Jul 25 04:20:42 PM PDT 24 | Jul 25 04:52:38 PM PDT 24 | 336463710000 ps | ||
| T92 | /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.4068859158 | Jul 25 04:20:44 PM PDT 24 | Jul 25 04:49:12 PM PDT 24 | 336310810000 ps | ||
| T93 | /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.2354629018 | Jul 25 04:20:10 PM PDT 24 | Jul 25 04:53:43 PM PDT 24 | 336810390000 ps | ||
| T94 | /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.2475001508 | Jul 25 04:20:54 PM PDT 24 | Jul 25 04:53:51 PM PDT 24 | 336866570000 ps | ||
| T95 | /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.4177319838 | Jul 25 04:24:48 PM PDT 24 | Jul 25 04:51:21 PM PDT 24 | 336760510000 ps | ||
| T96 | /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.1967829471 | Jul 25 04:22:30 PM PDT 24 | Jul 25 04:56:28 PM PDT 24 | 336348690000 ps | ||
| T97 | /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.2738920439 | Jul 25 04:19:28 PM PDT 24 | Jul 25 04:49:16 PM PDT 24 | 336747210000 ps | ||
| T98 | /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.1288011128 | Jul 25 04:20:44 PM PDT 24 | Jul 25 04:53:24 PM PDT 24 | 337043150000 ps | ||
| T99 | /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.3831168936 | Jul 25 04:19:27 PM PDT 24 | Jul 25 04:51:41 PM PDT 24 | 336594550000 ps | ||
| T100 | /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.43111227 | Jul 25 04:21:25 PM PDT 24 | Jul 25 04:52:58 PM PDT 24 | 336335750000 ps | ||
| T101 | /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.2084939453 | Jul 25 04:19:25 PM PDT 24 | Jul 25 04:47:44 PM PDT 24 | 336593370000 ps | ||
| T102 | /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.3081058120 | Jul 25 04:20:42 PM PDT 24 | Jul 25 04:51:57 PM PDT 24 | 337077350000 ps | ||
| T103 | /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.3005804453 | Jul 25 04:20:59 PM PDT 24 | Jul 25 04:53:02 PM PDT 24 | 336776910000 ps | ||
| T104 | /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.3140025097 | Jul 25 04:24:32 PM PDT 24 | Jul 25 04:55:22 PM PDT 24 | 337043770000 ps | ||
| T105 | /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.1842668811 | Jul 25 04:24:23 PM PDT 24 | Jul 25 04:55:49 PM PDT 24 | 336689170000 ps | ||
| T106 | /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.420986685 | Jul 25 04:24:32 PM PDT 24 | Jul 25 04:56:30 PM PDT 24 | 336623910000 ps | ||
| T107 | /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.1887251521 | Jul 25 04:20:19 PM PDT 24 | Jul 25 04:49:21 PM PDT 24 | 336527670000 ps | ||
| T108 | /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.4286199796 | Jul 25 04:20:29 PM PDT 24 | Jul 25 04:47:20 PM PDT 24 | 337008250000 ps | ||
| T109 | /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.395579603 | Jul 25 04:24:09 PM PDT 24 | Jul 25 04:51:41 PM PDT 24 | 336669750000 ps | ||
| T110 | /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.3579341613 | Jul 25 04:19:27 PM PDT 24 | Jul 25 04:51:56 PM PDT 24 | 336460570000 ps | ||
| T111 | /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.3798417105 | Jul 25 04:26:42 PM PDT 24 | Jul 25 04:26:51 PM PDT 24 | 1134010000 ps | ||
| T112 | /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.577039305 | Jul 25 04:19:26 PM PDT 24 | Jul 25 04:19:37 PM PDT 24 | 1536330000 ps | ||
| T113 | /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.3235166323 | Jul 25 04:26:31 PM PDT 24 | Jul 25 04:26:40 PM PDT 24 | 1627890000 ps | ||
| T114 | /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.538411454 | Jul 25 04:19:27 PM PDT 24 | Jul 25 04:19:36 PM PDT 24 | 1504050000 ps | ||
| T115 | /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.1581666589 | Jul 25 04:26:40 PM PDT 24 | Jul 25 04:26:48 PM PDT 24 | 1413170000 ps | ||
| T116 | /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.555033716 | Jul 25 04:26:36 PM PDT 24 | Jul 25 04:26:46 PM PDT 24 | 1535630000 ps | ||
| T117 | /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.3310886328 | Jul 25 04:26:52 PM PDT 24 | Jul 25 04:27:00 PM PDT 24 | 1566010000 ps | ||
| T118 | /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.578343816 | Jul 25 04:19:28 PM PDT 24 | Jul 25 04:19:35 PM PDT 24 | 1207850000 ps | ||
| T119 | /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.3294418265 | Jul 25 04:26:40 PM PDT 24 | Jul 25 04:26:50 PM PDT 24 | 1495750000 ps | ||
| T120 | /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.227210233 | Jul 25 04:19:26 PM PDT 24 | Jul 25 04:19:37 PM PDT 24 | 1600730000 ps | ||
| T121 | /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.1245164047 | Jul 25 04:26:44 PM PDT 24 | Jul 25 04:26:50 PM PDT 24 | 1036330000 ps | ||
| T122 | /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.3936911843 | Jul 25 04:26:31 PM PDT 24 | Jul 25 04:26:40 PM PDT 24 | 1414690000 ps | ||
| T123 | /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.3235349060 | Jul 25 04:19:28 PM PDT 24 | Jul 25 04:19:36 PM PDT 24 | 1417190000 ps | ||
| T124 | /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.3511701153 | Jul 25 04:26:34 PM PDT 24 | Jul 25 04:26:42 PM PDT 24 | 1474230000 ps | ||
| T125 | /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.2550928526 | Jul 25 04:26:37 PM PDT 24 | Jul 25 04:26:44 PM PDT 24 | 1429610000 ps | ||
| T126 | /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.1243718498 | Jul 25 04:20:27 PM PDT 24 | Jul 25 04:20:35 PM PDT 24 | 1545370000 ps | ||
| T127 | /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.1060663600 | Jul 25 04:19:26 PM PDT 24 | Jul 25 04:19:36 PM PDT 24 | 1407610000 ps | ||
| T128 | /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.452033741 | Jul 25 04:19:25 PM PDT 24 | Jul 25 04:19:37 PM PDT 24 | 1532890000 ps | ||
| T129 | /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.2800589473 | Jul 25 04:19:29 PM PDT 24 | Jul 25 04:19:39 PM PDT 24 | 1529090000 ps | ||
| T130 | /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.3923640440 | Jul 25 04:19:25 PM PDT 24 | Jul 25 04:19:34 PM PDT 24 | 1469870000 ps | ||
| T131 | /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.934726961 | Jul 25 04:26:39 PM PDT 24 | Jul 25 04:26:46 PM PDT 24 | 1537650000 ps | ||
| T132 | /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.2985006431 | Jul 25 04:19:27 PM PDT 24 | Jul 25 04:19:37 PM PDT 24 | 1384830000 ps | ||
| T133 | /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.1847021853 | Jul 25 04:19:27 PM PDT 24 | Jul 25 04:19:36 PM PDT 24 | 1533770000 ps | ||
| T134 | /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.2636542615 | Jul 25 04:20:42 PM PDT 24 | Jul 25 04:20:53 PM PDT 24 | 1432730000 ps | ||
| T135 | /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.2003648844 | Jul 25 04:26:34 PM PDT 24 | Jul 25 04:26:42 PM PDT 24 | 1557910000 ps | ||
| T136 | /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.1439660227 | Jul 25 04:26:47 PM PDT 24 | Jul 25 04:26:55 PM PDT 24 | 1412830000 ps | ||
| T137 | /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.3974546882 | Jul 25 04:26:43 PM PDT 24 | Jul 25 04:26:51 PM PDT 24 | 1420550000 ps | ||
| T138 | /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.1491236390 | Jul 25 04:26:36 PM PDT 24 | Jul 25 04:26:43 PM PDT 24 | 1411290000 ps | ||
| T139 | /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.3794010110 | Jul 25 04:19:29 PM PDT 24 | Jul 25 04:19:37 PM PDT 24 | 1285110000 ps | ||
| T140 | /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.4140020456 | Jul 25 04:26:37 PM PDT 24 | Jul 25 04:26:45 PM PDT 24 | 1470550000 ps | ||
| T141 | /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.1713900778 | Jul 25 04:26:37 PM PDT 24 | Jul 25 04:26:45 PM PDT 24 | 1493270000 ps | ||
| T142 | /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.1949743200 | Jul 25 04:19:26 PM PDT 24 | Jul 25 04:19:37 PM PDT 24 | 1625770000 ps | ||
| T143 | /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.3313528828 | Jul 25 04:26:22 PM PDT 24 | Jul 25 04:26:30 PM PDT 24 | 1438030000 ps | ||
| T144 | /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.2160838896 | Jul 25 04:26:31 PM PDT 24 | Jul 25 04:26:39 PM PDT 24 | 1509410000 ps | ||
| T145 | /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.1443910553 | Jul 25 04:26:38 PM PDT 24 | Jul 25 04:26:48 PM PDT 24 | 1537430000 ps | ||
| T146 | /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.2745306529 | Jul 25 04:26:32 PM PDT 24 | Jul 25 04:26:38 PM PDT 24 | 1142430000 ps | ||
| T147 | /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.3468197890 | Jul 25 04:26:42 PM PDT 24 | Jul 25 04:26:52 PM PDT 24 | 1376050000 ps | ||
| T148 | /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.2770130266 | Jul 25 04:26:27 PM PDT 24 | Jul 25 04:26:36 PM PDT 24 | 1526010000 ps | ||
| T149 | /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.1664913256 | Jul 25 04:26:37 PM PDT 24 | Jul 25 04:26:45 PM PDT 24 | 1537790000 ps | ||
| T150 | /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.4282923654 | Jul 25 04:19:26 PM PDT 24 | Jul 25 04:19:33 PM PDT 24 | 1140630000 ps | ||
| T151 | /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.4272282425 | Jul 25 04:19:29 PM PDT 24 | Jul 25 04:19:39 PM PDT 24 | 1507870000 ps | ||
| T152 | /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.1099735785 | Jul 25 04:19:25 PM PDT 24 | Jul 25 04:19:35 PM PDT 24 | 1598670000 ps | ||
| T153 | /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.1062348534 | Jul 25 04:26:36 PM PDT 24 | Jul 25 04:26:46 PM PDT 24 | 1559730000 ps | ||
| T154 | /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.2737655753 | Jul 25 04:26:34 PM PDT 24 | Jul 25 04:26:41 PM PDT 24 | 1450670000 ps | ||
| T155 | /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.1907483416 | Jul 25 04:19:26 PM PDT 24 | Jul 25 04:19:35 PM PDT 24 | 1290650000 ps | ||
| T156 | /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.2791936823 | Jul 25 04:26:39 PM PDT 24 | Jul 25 04:26:47 PM PDT 24 | 1406370000 ps | ||
| T157 | /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.2619604633 | Jul 25 04:26:30 PM PDT 24 | Jul 25 04:26:37 PM PDT 24 | 1524970000 ps | ||
| T158 | /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.733025046 | Jul 25 04:26:37 PM PDT 24 | Jul 25 04:26:45 PM PDT 24 | 1264830000 ps | ||
| T159 | /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.483234533 | Jul 25 04:26:30 PM PDT 24 | Jul 25 04:26:37 PM PDT 24 | 1399990000 ps | ||
| T160 | /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.448772739 | Jul 25 04:19:25 PM PDT 24 | Jul 25 04:19:35 PM PDT 24 | 1474850000 ps | ||
| T21 | /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.1917601337 | Jul 25 05:02:54 PM PDT 24 | Jul 25 05:33:32 PM PDT 24 | 336456610000 ps | ||
| T22 | /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.1515088932 | Jul 25 05:02:35 PM PDT 24 | Jul 25 05:33:09 PM PDT 24 | 337008690000 ps | ||
| T23 | /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.855130484 | Jul 25 05:02:49 PM PDT 24 | Jul 25 05:30:59 PM PDT 24 | 336691790000 ps | ||
| T24 | /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.241873099 | Jul 25 05:02:48 PM PDT 24 | Jul 25 05:40:34 PM PDT 24 | 336478090000 ps | ||
| T25 | /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.2118430593 | Jul 25 05:02:38 PM PDT 24 | Jul 25 05:39:05 PM PDT 24 | 336921670000 ps | ||
| T26 | /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.2491285964 | Jul 25 05:02:53 PM PDT 24 | Jul 25 05:37:51 PM PDT 24 | 336935610000 ps | ||
| T27 | /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.232220063 | Jul 25 05:02:48 PM PDT 24 | Jul 25 05:41:23 PM PDT 24 | 336966490000 ps | ||
| T28 | /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.1375347018 | Jul 25 05:02:38 PM PDT 24 | Jul 25 05:40:29 PM PDT 24 | 336671510000 ps | ||
| T29 | /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.1218736982 | Jul 25 05:02:37 PM PDT 24 | Jul 25 05:38:49 PM PDT 24 | 336591310000 ps | ||
| T30 | /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.1456931526 | Jul 25 05:02:47 PM PDT 24 | Jul 25 05:41:13 PM PDT 24 | 336463410000 ps | ||
| T161 | /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.1229386013 | Jul 25 05:02:38 PM PDT 24 | Jul 25 05:40:24 PM PDT 24 | 336371530000 ps | ||
| T162 | /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.4238230312 | Jul 25 05:02:48 PM PDT 24 | Jul 25 05:32:43 PM PDT 24 | 336928290000 ps | ||
| T163 | /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.3731636988 | Jul 25 05:02:57 PM PDT 24 | Jul 25 05:40:35 PM PDT 24 | 336327970000 ps | ||
| T164 | /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3965860644 | Jul 25 05:02:48 PM PDT 24 | Jul 25 05:33:31 PM PDT 24 | 337006990000 ps | ||
| T165 | /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.82914600 | Jul 25 05:02:45 PM PDT 24 | Jul 25 05:34:40 PM PDT 24 | 336584290000 ps | ||
| T166 | /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.4121335178 | Jul 25 05:02:48 PM PDT 24 | Jul 25 05:41:28 PM PDT 24 | 336766230000 ps | ||
| T167 | /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.3812752910 | Jul 25 05:02:46 PM PDT 24 | Jul 25 05:36:14 PM PDT 24 | 336975770000 ps | ||
| T168 | /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.2825997357 | Jul 25 05:02:57 PM PDT 24 | Jul 25 05:41:12 PM PDT 24 | 336864030000 ps | ||
| T169 | /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.1207896083 | Jul 25 05:02:53 PM PDT 24 | Jul 25 05:35:46 PM PDT 24 | 336369470000 ps | ||
| T170 | /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.2595792925 | Jul 25 05:02:47 PM PDT 24 | Jul 25 05:33:17 PM PDT 24 | 336731230000 ps | ||
| T171 | /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.460143003 | Jul 25 05:02:47 PM PDT 24 | Jul 25 05:35:24 PM PDT 24 | 336673830000 ps | ||
| T172 | /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.4094445440 | Jul 25 05:02:37 PM PDT 24 | Jul 25 05:38:27 PM PDT 24 | 336652930000 ps | ||
| T173 | /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.970043147 | Jul 25 05:02:48 PM PDT 24 | Jul 25 05:30:29 PM PDT 24 | 336738450000 ps | ||
| T174 | /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.2940790741 | Jul 25 05:02:38 PM PDT 24 | Jul 25 05:33:36 PM PDT 24 | 336536010000 ps | ||
| T175 | /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.3090583297 | Jul 25 05:02:46 PM PDT 24 | Jul 25 05:33:59 PM PDT 24 | 336854130000 ps | ||
| T176 | /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.1675949879 | Jul 25 05:02:37 PM PDT 24 | Jul 25 05:34:10 PM PDT 24 | 336921970000 ps | ||
| T177 | /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.2448588850 | Jul 25 05:02:47 PM PDT 24 | Jul 25 05:36:23 PM PDT 24 | 336885870000 ps | ||
| T178 | /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.3843588931 | Jul 25 05:02:47 PM PDT 24 | Jul 25 05:30:46 PM PDT 24 | 336592230000 ps | ||
| T179 | /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.2008842449 | Jul 25 05:02:37 PM PDT 24 | Jul 25 05:36:32 PM PDT 24 | 336715090000 ps | ||
| T180 | /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.3573856731 | Jul 25 05:02:38 PM PDT 24 | Jul 25 05:33:11 PM PDT 24 | 336522010000 ps | ||
| T181 | /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.2759941473 | Jul 25 05:02:36 PM PDT 24 | Jul 25 05:41:02 PM PDT 24 | 336912130000 ps | ||
| T182 | /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.3380651070 | Jul 25 05:02:48 PM PDT 24 | Jul 25 05:31:19 PM PDT 24 | 337029570000 ps | ||
| T183 | /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.1108570442 | Jul 25 05:02:48 PM PDT 24 | Jul 25 05:36:56 PM PDT 24 | 336935310000 ps | ||
| T184 | /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.1267565911 | Jul 25 05:02:37 PM PDT 24 | Jul 25 05:38:24 PM PDT 24 | 336833130000 ps | ||
| T185 | /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3990016997 | Jul 25 05:02:53 PM PDT 24 | Jul 25 05:37:05 PM PDT 24 | 336746890000 ps | ||
| T186 | /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.3402636495 | Jul 25 05:02:50 PM PDT 24 | Jul 25 05:36:56 PM PDT 24 | 336717070000 ps | ||
| T187 | /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.120946572 | Jul 25 05:02:46 PM PDT 24 | Jul 25 05:36:51 PM PDT 24 | 337060930000 ps | ||
| T188 | /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.1176924087 | Jul 25 05:02:59 PM PDT 24 | Jul 25 05:33:19 PM PDT 24 | 336946330000 ps | ||
| T189 | /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.691781890 | Jul 25 05:02:49 PM PDT 24 | Jul 25 05:37:31 PM PDT 24 | 336430310000 ps | ||
| T190 | /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.1575157235 | Jul 25 05:02:47 PM PDT 24 | Jul 25 05:34:14 PM PDT 24 | 336940150000 ps | ||
| T191 | /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.3208123867 | Jul 25 05:02:55 PM PDT 24 | Jul 25 05:39:14 PM PDT 24 | 336315450000 ps | ||
| T192 | /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.2446137436 | Jul 25 05:02:55 PM PDT 24 | Jul 25 05:39:51 PM PDT 24 | 336830110000 ps | ||
| T193 | /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.1052548643 | Jul 25 05:02:38 PM PDT 24 | Jul 25 05:38:41 PM PDT 24 | 336500870000 ps | ||
| T194 | /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.887344595 | Jul 25 05:02:37 PM PDT 24 | Jul 25 05:32:14 PM PDT 24 | 336450270000 ps | ||
| T195 | /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.3230463779 | Jul 25 05:02:49 PM PDT 24 | Jul 25 05:28:53 PM PDT 24 | 336982150000 ps | ||
| T196 | /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.730027742 | Jul 25 05:02:46 PM PDT 24 | Jul 25 05:32:37 PM PDT 24 | 336456930000 ps | ||
| T197 | /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.2927146806 | Jul 25 05:02:55 PM PDT 24 | Jul 25 05:40:22 PM PDT 24 | 336665850000 ps | ||
| T198 | /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.2145493201 | Jul 25 05:02:58 PM PDT 24 | Jul 25 05:29:48 PM PDT 24 | 336580370000 ps | ||
| T199 | /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.4217227797 | Jul 25 05:02:38 PM PDT 24 | Jul 25 05:33:13 PM PDT 24 | 336660290000 ps | ||
| T200 | /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1993098448 | Jul 25 05:02:58 PM PDT 24 | Jul 25 05:34:31 PM PDT 24 | 336788850000 ps |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.958375027 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 1438530000 ps |
| CPU time | 5.38 seconds |
| Started | Jul 25 04:20:10 PM PDT 24 |
| Finished | Jul 25 04:20:22 PM PDT 24 |
| Peak memory | 164552 kb |
| Host | smart-9e73d85a-edf0-42d2-949b-b42a9655e3fd |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=958375027 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.958375027 |
| Directory | /workspace/1.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.3910665203 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 336402030000 ps |
| CPU time | 831 seconds |
| Started | Jul 25 04:20:07 PM PDT 24 |
| Finished | Jul 25 04:54:21 PM PDT 24 |
| Peak memory | 160872 kb |
| Host | smart-574dce52-893c-4817-a3b7-ce1ccc520bc3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3910665203 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.3910665203 |
| Directory | /workspace/12.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.2118430593 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 336921670000 ps |
| CPU time | 878.12 seconds |
| Started | Jul 25 05:02:38 PM PDT 24 |
| Finished | Jul 25 05:39:05 PM PDT 24 |
| Peak memory | 160704 kb |
| Host | smart-4ab4b712-7816-456c-bc28-8225e88e696a |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2118430593 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.2118430593 |
| Directory | /workspace/0.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.3081058120 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 337077350000 ps |
| CPU time | 765.73 seconds |
| Started | Jul 25 04:20:42 PM PDT 24 |
| Finished | Jul 25 04:51:57 PM PDT 24 |
| Peak memory | 160472 kb |
| Host | smart-4817d5f7-93ae-46f7-b610-309ee3ad63ff |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3081058120 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.3081058120 |
| Directory | /workspace/0.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.94075111 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 336463710000 ps |
| CPU time | 785.78 seconds |
| Started | Jul 25 04:20:42 PM PDT 24 |
| Finished | Jul 25 04:52:38 PM PDT 24 |
| Peak memory | 160472 kb |
| Host | smart-2e35f72c-4283-42ea-ab4e-8301596bb1a6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=94075111 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.94075111 |
| Directory | /workspace/1.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.430144156 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 336415230000 ps |
| CPU time | 729.89 seconds |
| Started | Jul 25 04:20:26 PM PDT 24 |
| Finished | Jul 25 04:50:08 PM PDT 24 |
| Peak memory | 159380 kb |
| Host | smart-288f35eb-31e5-4dfb-a3ab-ca15e405227d |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=430144156 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.430144156 |
| Directory | /workspace/10.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.2738920439 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 336747210000 ps |
| CPU time | 730.82 seconds |
| Started | Jul 25 04:19:28 PM PDT 24 |
| Finished | Jul 25 04:49:16 PM PDT 24 |
| Peak memory | 159756 kb |
| Host | smart-c294469e-37e5-4023-b5b9-64c4415e0da9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2738920439 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.2738920439 |
| Directory | /workspace/11.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.2563164586 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 336648250000 ps |
| CPU time | 650.61 seconds |
| Started | Jul 25 04:20:22 PM PDT 24 |
| Finished | Jul 25 04:46:57 PM PDT 24 |
| Peak memory | 160592 kb |
| Host | smart-3efbd0a4-c39b-4ac1-96de-2bbfdfd902b2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2563164586 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.2563164586 |
| Directory | /workspace/13.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.1288011128 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 337043150000 ps |
| CPU time | 805.07 seconds |
| Started | Jul 25 04:20:44 PM PDT 24 |
| Finished | Jul 25 04:53:24 PM PDT 24 |
| Peak memory | 160616 kb |
| Host | smart-1b86ddd3-07df-4d20-8350-ada1774f88a3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1288011128 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.1288011128 |
| Directory | /workspace/14.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.1967829471 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 336348690000 ps |
| CPU time | 821.23 seconds |
| Started | Jul 25 04:22:30 PM PDT 24 |
| Finished | Jul 25 04:56:28 PM PDT 24 |
| Peak memory | 160872 kb |
| Host | smart-4c0f9785-27da-4c7d-ad7e-414bce7d5921 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1967829471 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.1967829471 |
| Directory | /workspace/15.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.1265139445 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 337019470000 ps |
| CPU time | 825.69 seconds |
| Started | Jul 25 04:20:07 PM PDT 24 |
| Finished | Jul 25 04:54:17 PM PDT 24 |
| Peak memory | 160872 kb |
| Host | smart-8a9cb632-05b7-487b-adfc-f74e94028500 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1265139445 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.1265139445 |
| Directory | /workspace/16.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.420986685 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 336623910000 ps |
| CPU time | 779.25 seconds |
| Started | Jul 25 04:24:32 PM PDT 24 |
| Finished | Jul 25 04:56:30 PM PDT 24 |
| Peak memory | 160280 kb |
| Host | smart-2a9fd549-b5b6-4752-b70d-c0ab5ff3078a |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=420986685 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.420986685 |
| Directory | /workspace/17.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.1630129297 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 336646110000 ps |
| CPU time | 745.32 seconds |
| Started | Jul 25 04:24:24 PM PDT 24 |
| Finished | Jul 25 04:55:14 PM PDT 24 |
| Peak memory | 160212 kb |
| Host | smart-c528d30e-c3f1-4fa3-b246-1ff12b7d8996 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1630129297 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.1630129297 |
| Directory | /workspace/18.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.3609697534 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 337046010000 ps |
| CPU time | 702.52 seconds |
| Started | Jul 25 04:20:28 PM PDT 24 |
| Finished | Jul 25 04:49:07 PM PDT 24 |
| Peak memory | 159484 kb |
| Host | smart-f700f34e-b419-4971-9fcd-687e536c748b |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3609697534 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.3609697534 |
| Directory | /workspace/19.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.3579341613 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 336460570000 ps |
| CPU time | 775.1 seconds |
| Started | Jul 25 04:19:27 PM PDT 24 |
| Finished | Jul 25 04:51:56 PM PDT 24 |
| Peak memory | 160188 kb |
| Host | smart-06c53cc2-8ee4-408f-9816-b5f0f321288e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3579341613 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.3579341613 |
| Directory | /workspace/2.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.4286199796 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 337008250000 ps |
| CPU time | 653 seconds |
| Started | Jul 25 04:20:29 PM PDT 24 |
| Finished | Jul 25 04:47:20 PM PDT 24 |
| Peak memory | 160128 kb |
| Host | smart-39c8f68c-e364-4b6d-b4ea-9fea046e8935 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4286199796 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.4286199796 |
| Directory | /workspace/20.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.3140025097 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 337043770000 ps |
| CPU time | 747.48 seconds |
| Started | Jul 25 04:24:32 PM PDT 24 |
| Finished | Jul 25 04:55:22 PM PDT 24 |
| Peak memory | 160304 kb |
| Host | smart-e4fb5d31-c311-4a27-9512-eda256b28211 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3140025097 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.3140025097 |
| Directory | /workspace/21.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.4068859158 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 336310810000 ps |
| CPU time | 694.84 seconds |
| Started | Jul 25 04:20:44 PM PDT 24 |
| Finished | Jul 25 04:49:12 PM PDT 24 |
| Peak memory | 160360 kb |
| Host | smart-993c211f-0767-4eac-a580-0dcd6588b758 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4068859158 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.4068859158 |
| Directory | /workspace/22.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.2354629018 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 336810390000 ps |
| CPU time | 820.84 seconds |
| Started | Jul 25 04:20:10 PM PDT 24 |
| Finished | Jul 25 04:53:43 PM PDT 24 |
| Peak memory | 160580 kb |
| Host | smart-70412fa1-00cb-48b3-b2c9-4bd53600ee24 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2354629018 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.2354629018 |
| Directory | /workspace/23.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.1842668811 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 336689170000 ps |
| CPU time | 763.93 seconds |
| Started | Jul 25 04:24:23 PM PDT 24 |
| Finished | Jul 25 04:55:49 PM PDT 24 |
| Peak memory | 159784 kb |
| Host | smart-11f146e0-49f0-43df-94c5-f76db53ccabd |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1842668811 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.1842668811 |
| Directory | /workspace/24.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.43111227 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 336335750000 ps |
| CPU time | 772.77 seconds |
| Started | Jul 25 04:21:25 PM PDT 24 |
| Finished | Jul 25 04:52:58 PM PDT 24 |
| Peak memory | 160468 kb |
| Host | smart-ba550e65-a047-445e-bfa9-e7a33f77606e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=43111227 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.43111227 |
| Directory | /workspace/25.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.3158419317 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 337037310000 ps |
| CPU time | 819.78 seconds |
| Started | Jul 25 04:23:13 PM PDT 24 |
| Finished | Jul 25 04:57:09 PM PDT 24 |
| Peak memory | 160872 kb |
| Host | smart-c1a2a25c-7626-4a75-91d4-d5af6be1936c |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3158419317 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.3158419317 |
| Directory | /workspace/26.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.4071260049 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 337050530000 ps |
| CPU time | 703.47 seconds |
| Started | Jul 25 04:24:24 PM PDT 24 |
| Finished | Jul 25 04:53:40 PM PDT 24 |
| Peak memory | 160304 kb |
| Host | smart-79c4e4e9-12fe-4587-992f-c589a0868542 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4071260049 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.4071260049 |
| Directory | /workspace/27.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.4177319838 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 336760510000 ps |
| CPU time | 639.2 seconds |
| Started | Jul 25 04:24:48 PM PDT 24 |
| Finished | Jul 25 04:51:21 PM PDT 24 |
| Peak memory | 159392 kb |
| Host | smart-9ca04482-094e-4f26-b58e-7348277d9773 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4177319838 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.4177319838 |
| Directory | /workspace/28.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.3613761108 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 336898870000 ps |
| CPU time | 732.05 seconds |
| Started | Jul 25 04:22:46 PM PDT 24 |
| Finished | Jul 25 04:52:49 PM PDT 24 |
| Peak memory | 160660 kb |
| Host | smart-210e7310-1c86-4b86-b6d2-6035d55e45cd |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3613761108 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.3613761108 |
| Directory | /workspace/29.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.1783628857 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 336945250000 ps |
| CPU time | 791.39 seconds |
| Started | Jul 25 04:19:27 PM PDT 24 |
| Finished | Jul 25 04:51:11 PM PDT 24 |
| Peak memory | 160368 kb |
| Host | smart-1f75d03c-5973-4af5-a50a-6002088aac26 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1783628857 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.1783628857 |
| Directory | /workspace/3.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.1165622761 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 336613390000 ps |
| CPU time | 678.69 seconds |
| Started | Jul 25 04:21:09 PM PDT 24 |
| Finished | Jul 25 04:48:46 PM PDT 24 |
| Peak memory | 160592 kb |
| Host | smart-f3b844b6-15fc-4c57-89ee-42133a5b45c4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1165622761 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.1165622761 |
| Directory | /workspace/30.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.410133132 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 336740870000 ps |
| CPU time | 769.82 seconds |
| Started | Jul 25 04:20:07 PM PDT 24 |
| Finished | Jul 25 04:52:25 PM PDT 24 |
| Peak memory | 160620 kb |
| Host | smart-fe1f1006-5302-4db3-8537-16e81a10dc74 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=410133132 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.410133132 |
| Directory | /workspace/31.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.3987310536 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 336561330000 ps |
| CPU time | 635.01 seconds |
| Started | Jul 25 04:24:56 PM PDT 24 |
| Finished | Jul 25 04:51:16 PM PDT 24 |
| Peak memory | 159756 kb |
| Host | smart-8a80b63f-a881-431d-a41c-756c628a764c |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3987310536 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.3987310536 |
| Directory | /workspace/32.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.1573704289 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 336378450000 ps |
| CPU time | 815.29 seconds |
| Started | Jul 25 04:22:41 PM PDT 24 |
| Finished | Jul 25 04:55:58 PM PDT 24 |
| Peak memory | 160616 kb |
| Host | smart-bd892103-6e28-40d2-b960-2e77a2959656 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1573704289 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.1573704289 |
| Directory | /workspace/33.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.3724678322 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 336624630000 ps |
| CPU time | 717.53 seconds |
| Started | Jul 25 04:24:23 PM PDT 24 |
| Finished | Jul 25 04:54:00 PM PDT 24 |
| Peak memory | 160256 kb |
| Host | smart-97bfed4d-ab80-4bfb-a758-739657d2fb56 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3724678322 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.3724678322 |
| Directory | /workspace/34.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.1887251521 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 336527670000 ps |
| CPU time | 701.72 seconds |
| Started | Jul 25 04:20:19 PM PDT 24 |
| Finished | Jul 25 04:49:21 PM PDT 24 |
| Peak memory | 160624 kb |
| Host | smart-6e008d62-bf51-4def-a0da-0aaaf42d753f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1887251521 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.1887251521 |
| Directory | /workspace/35.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.509931291 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 336888530000 ps |
| CPU time | 657.43 seconds |
| Started | Jul 25 04:22:02 PM PDT 24 |
| Finished | Jul 25 04:49:12 PM PDT 24 |
| Peak memory | 160636 kb |
| Host | smart-cb7a2772-1b5f-4a0e-aadf-750f64eb06cd |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=509931291 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.509931291 |
| Directory | /workspace/36.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.115821447 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 336415170000 ps |
| CPU time | 691.28 seconds |
| Started | Jul 25 04:24:12 PM PDT 24 |
| Finished | Jul 25 04:52:20 PM PDT 24 |
| Peak memory | 159736 kb |
| Host | smart-c2583b68-41be-4dfb-b7bf-88ef516742a0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=115821447 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.115821447 |
| Directory | /workspace/37.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.3071835960 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 336859690000 ps |
| CPU time | 845.03 seconds |
| Started | Jul 25 04:20:22 PM PDT 24 |
| Finished | Jul 25 04:54:44 PM PDT 24 |
| Peak memory | 160580 kb |
| Host | smart-b8ebfbcc-0f35-415a-ad17-7d068041b8bb |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3071835960 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.3071835960 |
| Directory | /workspace/38.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.175870369 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 336829330000 ps |
| CPU time | 825.61 seconds |
| Started | Jul 25 04:20:20 PM PDT 24 |
| Finished | Jul 25 04:54:15 PM PDT 24 |
| Peak memory | 160616 kb |
| Host | smart-d2e77552-f4c6-446a-9f61-be3e827d84e1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=175870369 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.175870369 |
| Directory | /workspace/39.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.3831168936 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 336594550000 ps |
| CPU time | 783.07 seconds |
| Started | Jul 25 04:19:27 PM PDT 24 |
| Finished | Jul 25 04:51:41 PM PDT 24 |
| Peak memory | 160556 kb |
| Host | smart-f4dbb95a-c500-4ecf-8350-34e548072efb |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3831168936 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.3831168936 |
| Directory | /workspace/4.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.1409609918 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 337056110000 ps |
| CPU time | 606.03 seconds |
| Started | Jul 25 04:24:29 PM PDT 24 |
| Finished | Jul 25 04:49:47 PM PDT 24 |
| Peak memory | 160256 kb |
| Host | smart-55fe8b3d-beae-40ec-a04c-705c110701ae |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1409609918 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.1409609918 |
| Directory | /workspace/40.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.3005804453 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 336776910000 ps |
| CPU time | 791.08 seconds |
| Started | Jul 25 04:20:59 PM PDT 24 |
| Finished | Jul 25 04:53:02 PM PDT 24 |
| Peak memory | 160616 kb |
| Host | smart-dc77a4aa-474e-4d59-ad07-4b62e62108ed |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3005804453 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.3005804453 |
| Directory | /workspace/41.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.395579603 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 336669750000 ps |
| CPU time | 673.25 seconds |
| Started | Jul 25 04:24:09 PM PDT 24 |
| Finished | Jul 25 04:51:41 PM PDT 24 |
| Peak memory | 159736 kb |
| Host | smart-3cfd17bc-bb1c-4089-9648-d25bd7bca16b |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=395579603 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.395579603 |
| Directory | /workspace/42.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.771894622 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 337090570000 ps |
| CPU time | 740.19 seconds |
| Started | Jul 25 04:24:26 PM PDT 24 |
| Finished | Jul 25 04:54:49 PM PDT 24 |
| Peak memory | 160432 kb |
| Host | smart-7127b489-e2a9-4de3-a317-b15b54c8fa9d |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=771894622 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.771894622 |
| Directory | /workspace/43.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.973910553 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 336463910000 ps |
| CPU time | 816 seconds |
| Started | Jul 25 04:21:09 PM PDT 24 |
| Finished | Jul 25 04:54:34 PM PDT 24 |
| Peak memory | 160616 kb |
| Host | smart-82d40b6e-05fb-4590-9208-a341d7bdbcfa |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=973910553 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.973910553 |
| Directory | /workspace/44.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.1863225061 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 336975170000 ps |
| CPU time | 810.14 seconds |
| Started | Jul 25 04:21:09 PM PDT 24 |
| Finished | Jul 25 04:54:24 PM PDT 24 |
| Peak memory | 160616 kb |
| Host | smart-e2f24962-768f-424d-9b27-fe250074b063 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1863225061 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.1863225061 |
| Directory | /workspace/45.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.206960829 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 336467390000 ps |
| CPU time | 606.01 seconds |
| Started | Jul 25 04:24:19 PM PDT 24 |
| Finished | Jul 25 04:49:04 PM PDT 24 |
| Peak memory | 159748 kb |
| Host | smart-b0246358-7f82-4ee9-b862-30b342435349 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=206960829 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.206960829 |
| Directory | /workspace/46.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.52146386 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 336367590000 ps |
| CPU time | 735.25 seconds |
| Started | Jul 25 04:21:05 PM PDT 24 |
| Finished | Jul 25 04:51:03 PM PDT 24 |
| Peak memory | 160552 kb |
| Host | smart-843ba380-c020-44c7-a2fd-f9a068bfe541 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=52146386 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.52146386 |
| Directory | /workspace/47.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.1856313312 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 336706670000 ps |
| CPU time | 731.58 seconds |
| Started | Jul 25 04:21:03 PM PDT 24 |
| Finished | Jul 25 04:51:01 PM PDT 24 |
| Peak memory | 160644 kb |
| Host | smart-ea91c6ea-a5a6-4144-920a-5aed01c5f9a7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1856313312 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.1856313312 |
| Directory | /workspace/48.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.2475001508 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 336866570000 ps |
| CPU time | 793.7 seconds |
| Started | Jul 25 04:20:54 PM PDT 24 |
| Finished | Jul 25 04:53:51 PM PDT 24 |
| Peak memory | 160588 kb |
| Host | smart-3baea00d-69ed-47a9-b76c-c1db0879e017 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2475001508 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.2475001508 |
| Directory | /workspace/49.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.277454451 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 336459550000 ps |
| CPU time | 783.38 seconds |
| Started | Jul 25 04:19:25 PM PDT 24 |
| Finished | Jul 25 04:51:36 PM PDT 24 |
| Peak memory | 159584 kb |
| Host | smart-55c58eed-5659-4b06-a3a4-4dfb65c3cf2e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=277454451 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.277454451 |
| Directory | /workspace/5.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.4268265249 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 337068190000 ps |
| CPU time | 789.89 seconds |
| Started | Jul 25 04:19:27 PM PDT 24 |
| Finished | Jul 25 04:52:37 PM PDT 24 |
| Peak memory | 160332 kb |
| Host | smart-1291adce-052f-4878-97c0-cd4b0df227f1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4268265249 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.4268265249 |
| Directory | /workspace/6.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.2084939453 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 336593370000 ps |
| CPU time | 697.03 seconds |
| Started | Jul 25 04:19:25 PM PDT 24 |
| Finished | Jul 25 04:47:44 PM PDT 24 |
| Peak memory | 160344 kb |
| Host | smart-b34dc390-b5c4-4016-aeed-d224a7ac136f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2084939453 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.2084939453 |
| Directory | /workspace/7.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.120191535 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 336902970000 ps |
| CPU time | 773.69 seconds |
| Started | Jul 25 04:19:28 PM PDT 24 |
| Finished | Jul 25 04:52:01 PM PDT 24 |
| Peak memory | 160460 kb |
| Host | smart-6dd74c25-ceb6-48c1-96e7-01da09dffda2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=120191535 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.120191535 |
| Directory | /workspace/8.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.4104874943 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 336525350000 ps |
| CPU time | 712.03 seconds |
| Started | Jul 25 04:19:28 PM PDT 24 |
| Finished | Jul 25 04:48:39 PM PDT 24 |
| Peak memory | 160376 kb |
| Host | smart-2a78a30b-4b7b-447d-ae7d-c8c67848e2bb |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4104874943 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.4104874943 |
| Directory | /workspace/9.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.4217227797 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 336660290000 ps |
| CPU time | 754.54 seconds |
| Started | Jul 25 05:02:38 PM PDT 24 |
| Finished | Jul 25 05:33:13 PM PDT 24 |
| Peak memory | 160720 kb |
| Host | smart-37eb5797-9f6e-4a2e-8e0a-6797c8e6040b |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4217227797 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.4217227797 |
| Directory | /workspace/1.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.2008842449 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 336715090000 ps |
| CPU time | 826.46 seconds |
| Started | Jul 25 05:02:37 PM PDT 24 |
| Finished | Jul 25 05:36:32 PM PDT 24 |
| Peak memory | 160804 kb |
| Host | smart-13947bf6-6a9c-45f5-a222-2d5df8792a68 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2008842449 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.2008842449 |
| Directory | /workspace/10.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.1052548643 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 336500870000 ps |
| CPU time | 848.56 seconds |
| Started | Jul 25 05:02:38 PM PDT 24 |
| Finished | Jul 25 05:38:41 PM PDT 24 |
| Peak memory | 160800 kb |
| Host | smart-25a65341-c9de-49c8-b12c-d8c16cdeb520 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1052548643 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.1052548643 |
| Directory | /workspace/11.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.1229386013 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 336371530000 ps |
| CPU time | 912.92 seconds |
| Started | Jul 25 05:02:38 PM PDT 24 |
| Finished | Jul 25 05:40:24 PM PDT 24 |
| Peak memory | 160812 kb |
| Host | smart-a15fd87f-4441-4604-97d2-6a635c7d7cdd |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1229386013 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.1229386013 |
| Directory | /workspace/12.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.1515088932 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 337008690000 ps |
| CPU time | 738.31 seconds |
| Started | Jul 25 05:02:35 PM PDT 24 |
| Finished | Jul 25 05:33:09 PM PDT 24 |
| Peak memory | 160812 kb |
| Host | smart-ad89bafd-b311-4f32-b774-8e05887d1bc1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1515088932 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.1515088932 |
| Directory | /workspace/13.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.4094445440 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 336652930000 ps |
| CPU time | 845.57 seconds |
| Started | Jul 25 05:02:37 PM PDT 24 |
| Finished | Jul 25 05:38:27 PM PDT 24 |
| Peak memory | 160800 kb |
| Host | smart-7f1ccec8-44c8-4141-8c59-6f0ad22f97ab |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4094445440 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.4094445440 |
| Directory | /workspace/14.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.3380651070 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 337029570000 ps |
| CPU time | 700.07 seconds |
| Started | Jul 25 05:02:48 PM PDT 24 |
| Finished | Jul 25 05:31:19 PM PDT 24 |
| Peak memory | 160788 kb |
| Host | smart-4b2669b0-684c-46f2-bfff-5dd624d6f735 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3380651070 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.3380651070 |
| Directory | /workspace/15.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.3843588931 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 336592230000 ps |
| CPU time | 675.89 seconds |
| Started | Jul 25 05:02:47 PM PDT 24 |
| Finished | Jul 25 05:30:46 PM PDT 24 |
| Peak memory | 160800 kb |
| Host | smart-2e813fe4-1bcc-4bc4-90ef-c2a3f32b6367 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3843588931 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.3843588931 |
| Directory | /workspace/16.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.1917601337 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 336456610000 ps |
| CPU time | 745.08 seconds |
| Started | Jul 25 05:02:54 PM PDT 24 |
| Finished | Jul 25 05:33:32 PM PDT 24 |
| Peak memory | 160808 kb |
| Host | smart-eea4cef2-539c-481c-9c49-b6656285661c |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1917601337 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.1917601337 |
| Directory | /workspace/17.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.232220063 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 336966490000 ps |
| CPU time | 933.39 seconds |
| Started | Jul 25 05:02:48 PM PDT 24 |
| Finished | Jul 25 05:41:23 PM PDT 24 |
| Peak memory | 160808 kb |
| Host | smart-5fb82bdd-4d43-4701-bcda-7b2f6ac9906c |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=232220063 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.232220063 |
| Directory | /workspace/18.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.691781890 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 336430310000 ps |
| CPU time | 876.34 seconds |
| Started | Jul 25 05:02:49 PM PDT 24 |
| Finished | Jul 25 05:37:31 PM PDT 24 |
| Peak memory | 160708 kb |
| Host | smart-db467b41-83bc-4407-be82-f9abaaf3bd41 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=691781890 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.691781890 |
| Directory | /workspace/19.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.1675949879 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 336921970000 ps |
| CPU time | 780.99 seconds |
| Started | Jul 25 05:02:37 PM PDT 24 |
| Finished | Jul 25 05:34:10 PM PDT 24 |
| Peak memory | 160732 kb |
| Host | smart-bb0a70f2-7e7b-496d-9bb1-625bf8ff82d0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1675949879 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.1675949879 |
| Directory | /workspace/2.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.120946572 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 337060930000 ps |
| CPU time | 854.13 seconds |
| Started | Jul 25 05:02:46 PM PDT 24 |
| Finished | Jul 25 05:36:51 PM PDT 24 |
| Peak memory | 160784 kb |
| Host | smart-f85ee68c-6a28-464f-b8bd-6933f6cca871 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=120946572 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.120946572 |
| Directory | /workspace/20.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3965860644 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 337006990000 ps |
| CPU time | 745.37 seconds |
| Started | Jul 25 05:02:48 PM PDT 24 |
| Finished | Jul 25 05:33:31 PM PDT 24 |
| Peak memory | 160808 kb |
| Host | smart-36370d16-66ce-4ce3-8065-ff54a36ebaca |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3965860644 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.3965860644 |
| Directory | /workspace/21.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.3208123867 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 336315450000 ps |
| CPU time | 874.62 seconds |
| Started | Jul 25 05:02:55 PM PDT 24 |
| Finished | Jul 25 05:39:14 PM PDT 24 |
| Peak memory | 160712 kb |
| Host | smart-0ef96a92-54e5-4be9-a669-a5c6d13972a5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3208123867 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.3208123867 |
| Directory | /workspace/22.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.2825997357 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 336864030000 ps |
| CPU time | 908.4 seconds |
| Started | Jul 25 05:02:57 PM PDT 24 |
| Finished | Jul 25 05:41:12 PM PDT 24 |
| Peak memory | 160804 kb |
| Host | smart-aacadabb-cff8-441f-ae6f-fe5ec8eee960 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2825997357 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.2825997357 |
| Directory | /workspace/23.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.2448588850 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 336885870000 ps |
| CPU time | 810.8 seconds |
| Started | Jul 25 05:02:47 PM PDT 24 |
| Finished | Jul 25 05:36:23 PM PDT 24 |
| Peak memory | 160804 kb |
| Host | smart-f7b66868-ff6c-4a52-81a0-42f793b33248 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2448588850 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.2448588850 |
| Directory | /workspace/24.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.1108570442 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 336935310000 ps |
| CPU time | 824.35 seconds |
| Started | Jul 25 05:02:48 PM PDT 24 |
| Finished | Jul 25 05:36:56 PM PDT 24 |
| Peak memory | 160876 kb |
| Host | smart-9f633502-f028-47ed-b099-b3e9e3aacb4f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1108570442 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.1108570442 |
| Directory | /workspace/25.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.2491285964 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 336935610000 ps |
| CPU time | 807.01 seconds |
| Started | Jul 25 05:02:53 PM PDT 24 |
| Finished | Jul 25 05:37:51 PM PDT 24 |
| Peak memory | 160796 kb |
| Host | smart-412f9da4-29aa-4ecf-851b-82b7f9de73aa |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2491285964 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.2491285964 |
| Directory | /workspace/26.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.855130484 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 336691790000 ps |
| CPU time | 686.03 seconds |
| Started | Jul 25 05:02:49 PM PDT 24 |
| Finished | Jul 25 05:30:59 PM PDT 24 |
| Peak memory | 160756 kb |
| Host | smart-7aeec863-4b00-4b18-9720-f5fbf8aa5848 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=855130484 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.855130484 |
| Directory | /workspace/27.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.3812752910 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 336975770000 ps |
| CPU time | 842.74 seconds |
| Started | Jul 25 05:02:46 PM PDT 24 |
| Finished | Jul 25 05:36:14 PM PDT 24 |
| Peak memory | 160740 kb |
| Host | smart-153086b2-c721-4ee8-81ef-332228dbce74 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3812752910 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.3812752910 |
| Directory | /workspace/28.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.4238230312 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 336928290000 ps |
| CPU time | 747.41 seconds |
| Started | Jul 25 05:02:48 PM PDT 24 |
| Finished | Jul 25 05:32:43 PM PDT 24 |
| Peak memory | 160808 kb |
| Host | smart-14835688-5b5f-41c6-880c-41b4be40cb70 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4238230312 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.4238230312 |
| Directory | /workspace/29.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.3573856731 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 336522010000 ps |
| CPU time | 754.19 seconds |
| Started | Jul 25 05:02:38 PM PDT 24 |
| Finished | Jul 25 05:33:11 PM PDT 24 |
| Peak memory | 160792 kb |
| Host | smart-9f259059-2a7d-4be4-bb1e-5a0ea4796529 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3573856731 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.3573856731 |
| Directory | /workspace/3.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.460143003 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 336673830000 ps |
| CPU time | 800.11 seconds |
| Started | Jul 25 05:02:47 PM PDT 24 |
| Finished | Jul 25 05:35:24 PM PDT 24 |
| Peak memory | 160784 kb |
| Host | smart-7076d237-ae7c-4a57-abe2-8fb1367c1262 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=460143003 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.460143003 |
| Directory | /workspace/30.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.4121335178 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 336766230000 ps |
| CPU time | 938.33 seconds |
| Started | Jul 25 05:02:48 PM PDT 24 |
| Finished | Jul 25 05:41:28 PM PDT 24 |
| Peak memory | 160820 kb |
| Host | smart-7aa62e33-d85c-4d45-8ec3-01448042e808 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4121335178 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.4121335178 |
| Directory | /workspace/31.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.970043147 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 336738450000 ps |
| CPU time | 658.99 seconds |
| Started | Jul 25 05:02:48 PM PDT 24 |
| Finished | Jul 25 05:30:29 PM PDT 24 |
| Peak memory | 160776 kb |
| Host | smart-4b8e21e7-f8c6-47be-9553-ff186e9430ec |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=970043147 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.970043147 |
| Directory | /workspace/32.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.3731636988 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 336327970000 ps |
| CPU time | 911.21 seconds |
| Started | Jul 25 05:02:57 PM PDT 24 |
| Finished | Jul 25 05:40:35 PM PDT 24 |
| Peak memory | 160804 kb |
| Host | smart-d040218e-3969-4956-82d4-3349e24151ae |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3731636988 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.3731636988 |
| Directory | /workspace/33.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.1207896083 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 336369470000 ps |
| CPU time | 805.82 seconds |
| Started | Jul 25 05:02:53 PM PDT 24 |
| Finished | Jul 25 05:35:46 PM PDT 24 |
| Peak memory | 160804 kb |
| Host | smart-cb2b6ee2-c4a8-4909-855f-dacb39991dae |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1207896083 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.1207896083 |
| Directory | /workspace/34.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.241873099 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 336478090000 ps |
| CPU time | 906.78 seconds |
| Started | Jul 25 05:02:48 PM PDT 24 |
| Finished | Jul 25 05:40:34 PM PDT 24 |
| Peak memory | 160788 kb |
| Host | smart-53eef144-8f3a-4ab5-8e1f-88a65bd2836b |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=241873099 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.241873099 |
| Directory | /workspace/35.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.3090583297 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 336854130000 ps |
| CPU time | 764.54 seconds |
| Started | Jul 25 05:02:46 PM PDT 24 |
| Finished | Jul 25 05:33:59 PM PDT 24 |
| Peak memory | 160792 kb |
| Host | smart-2cf6ebb0-5522-4239-9004-4dd3d67f26d1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3090583297 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.3090583297 |
| Directory | /workspace/36.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.2595792925 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 336731230000 ps |
| CPU time | 743.49 seconds |
| Started | Jul 25 05:02:47 PM PDT 24 |
| Finished | Jul 25 05:33:17 PM PDT 24 |
| Peak memory | 160812 kb |
| Host | smart-3c9dc103-87f6-48c9-be54-de5e30c0273a |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2595792925 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.2595792925 |
| Directory | /workspace/37.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3990016997 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 336746890000 ps |
| CPU time | 861.09 seconds |
| Started | Jul 25 05:02:53 PM PDT 24 |
| Finished | Jul 25 05:37:05 PM PDT 24 |
| Peak memory | 160812 kb |
| Host | smart-39703e89-9350-40bd-b0a0-1d82bd9a68d6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3990016997 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.3990016997 |
| Directory | /workspace/38.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.1456931526 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 336463410000 ps |
| CPU time | 925.44 seconds |
| Started | Jul 25 05:02:47 PM PDT 24 |
| Finished | Jul 25 05:41:13 PM PDT 24 |
| Peak memory | 160808 kb |
| Host | smart-b496d6eb-1191-4113-b67e-c881af0e6e78 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1456931526 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.1456931526 |
| Directory | /workspace/39.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.1218736982 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 336591310000 ps |
| CPU time | 907.42 seconds |
| Started | Jul 25 05:02:37 PM PDT 24 |
| Finished | Jul 25 05:38:49 PM PDT 24 |
| Peak memory | 160796 kb |
| Host | smart-a27d78eb-bcde-4584-a9a9-26c038f7f2a0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1218736982 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.1218736982 |
| Directory | /workspace/4.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.82914600 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 336584290000 ps |
| CPU time | 797.19 seconds |
| Started | Jul 25 05:02:45 PM PDT 24 |
| Finished | Jul 25 05:34:40 PM PDT 24 |
| Peak memory | 160776 kb |
| Host | smart-4450d75e-b517-4406-b60e-aec06668217e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=82914600 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.82914600 |
| Directory | /workspace/40.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.3230463779 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 336982150000 ps |
| CPU time | 628.17 seconds |
| Started | Jul 25 05:02:49 PM PDT 24 |
| Finished | Jul 25 05:28:53 PM PDT 24 |
| Peak memory | 160780 kb |
| Host | smart-6577c41c-28ef-4722-b81c-65baee1da0b2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3230463779 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.3230463779 |
| Directory | /workspace/41.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.730027742 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 336456930000 ps |
| CPU time | 726.62 seconds |
| Started | Jul 25 05:02:46 PM PDT 24 |
| Finished | Jul 25 05:32:37 PM PDT 24 |
| Peak memory | 160792 kb |
| Host | smart-78d2cf89-6551-49b8-b093-0224fc927806 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=730027742 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.730027742 |
| Directory | /workspace/42.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.2446137436 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 336830110000 ps |
| CPU time | 896.33 seconds |
| Started | Jul 25 05:02:55 PM PDT 24 |
| Finished | Jul 25 05:39:51 PM PDT 24 |
| Peak memory | 160784 kb |
| Host | smart-761334bc-5544-4ca0-abee-dee3ab475c6d |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2446137436 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.2446137436 |
| Directory | /workspace/43.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.2927146806 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 336665850000 ps |
| CPU time | 917.35 seconds |
| Started | Jul 25 05:02:55 PM PDT 24 |
| Finished | Jul 25 05:40:22 PM PDT 24 |
| Peak memory | 160788 kb |
| Host | smart-ffdfb275-416e-4267-933d-76c165eec9d8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2927146806 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.2927146806 |
| Directory | /workspace/44.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.1575157235 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 336940150000 ps |
| CPU time | 781.12 seconds |
| Started | Jul 25 05:02:47 PM PDT 24 |
| Finished | Jul 25 05:34:14 PM PDT 24 |
| Peak memory | 160812 kb |
| Host | smart-81c754a4-f342-4706-8750-842a1dd9a3b6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1575157235 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.1575157235 |
| Directory | /workspace/45.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.3402636495 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 336717070000 ps |
| CPU time | 826.28 seconds |
| Started | Jul 25 05:02:50 PM PDT 24 |
| Finished | Jul 25 05:36:56 PM PDT 24 |
| Peak memory | 160876 kb |
| Host | smart-3469f0da-1487-4651-98cb-bd9c5bd79fae |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3402636495 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.3402636495 |
| Directory | /workspace/46.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.2145493201 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 336580370000 ps |
| CPU time | 648.09 seconds |
| Started | Jul 25 05:02:58 PM PDT 24 |
| Finished | Jul 25 05:29:48 PM PDT 24 |
| Peak memory | 160788 kb |
| Host | smart-acf8d70d-755f-4d3c-a35a-35d71aae6a31 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2145493201 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.2145493201 |
| Directory | /workspace/47.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1993098448 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 336788850000 ps |
| CPU time | 767.62 seconds |
| Started | Jul 25 05:02:58 PM PDT 24 |
| Finished | Jul 25 05:34:31 PM PDT 24 |
| Peak memory | 160792 kb |
| Host | smart-1709d9fb-b567-40e1-9db2-ad100d5cce40 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1993098448 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.1993098448 |
| Directory | /workspace/48.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.1176924087 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 336946330000 ps |
| CPU time | 747 seconds |
| Started | Jul 25 05:02:59 PM PDT 24 |
| Finished | Jul 25 05:33:19 PM PDT 24 |
| Peak memory | 160788 kb |
| Host | smart-10ee8c08-9693-47e4-adb8-d171fcff54ff |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1176924087 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.1176924087 |
| Directory | /workspace/49.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.2759941473 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 336912130000 ps |
| CPU time | 930.25 seconds |
| Started | Jul 25 05:02:36 PM PDT 24 |
| Finished | Jul 25 05:41:02 PM PDT 24 |
| Peak memory | 160784 kb |
| Host | smart-0412a856-97ab-4326-9d05-36a651dd5f39 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2759941473 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.2759941473 |
| Directory | /workspace/5.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.887344595 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 336450270000 ps |
| CPU time | 723.27 seconds |
| Started | Jul 25 05:02:37 PM PDT 24 |
| Finished | Jul 25 05:32:14 PM PDT 24 |
| Peak memory | 160788 kb |
| Host | smart-565c15f7-9f83-4d68-a8bd-adbe188600c7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=887344595 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.887344595 |
| Directory | /workspace/6.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.1267565911 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 336833130000 ps |
| CPU time | 840.46 seconds |
| Started | Jul 25 05:02:37 PM PDT 24 |
| Finished | Jul 25 05:38:24 PM PDT 24 |
| Peak memory | 160788 kb |
| Host | smart-4af8d357-7b2b-4bda-83e9-9f4c7696e80a |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1267565911 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.1267565911 |
| Directory | /workspace/7.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.1375347018 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 336671510000 ps |
| CPU time | 913.53 seconds |
| Started | Jul 25 05:02:38 PM PDT 24 |
| Finished | Jul 25 05:40:29 PM PDT 24 |
| Peak memory | 160788 kb |
| Host | smart-a7650b33-f392-4407-afac-f42e85e1b282 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1375347018 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.1375347018 |
| Directory | /workspace/8.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.2940790741 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 336536010000 ps |
| CPU time | 774.3 seconds |
| Started | Jul 25 05:02:38 PM PDT 24 |
| Finished | Jul 25 05:33:36 PM PDT 24 |
| Peak memory | 160720 kb |
| Host | smart-a07abd72-1922-4a6e-a972-d5368b8c4f25 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2940790741 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.2940790741 |
| Directory | /workspace/9.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.1099735785 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 1598670000 ps |
| CPU time | 4.16 seconds |
| Started | Jul 25 04:19:25 PM PDT 24 |
| Finished | Jul 25 04:19:35 PM PDT 24 |
| Peak memory | 164336 kb |
| Host | smart-d8d75faa-f3a4-43a2-a31b-b8243738eb47 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1099735785 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.1099735785 |
| Directory | /workspace/0.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.1907483416 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 1290650000 ps |
| CPU time | 4.38 seconds |
| Started | Jul 25 04:19:26 PM PDT 24 |
| Finished | Jul 25 04:19:35 PM PDT 24 |
| Peak memory | 164136 kb |
| Host | smart-f06c3ef2-f7cd-42ed-a63b-e47fbd6b9b47 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1907483416 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.1907483416 |
| Directory | /workspace/1.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.577039305 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 1536330000 ps |
| CPU time | 5 seconds |
| Started | Jul 25 04:19:26 PM PDT 24 |
| Finished | Jul 25 04:19:37 PM PDT 24 |
| Peak memory | 164424 kb |
| Host | smart-92a17c5d-3a2e-408d-a3c2-f5c1f166ab98 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=577039305 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.577039305 |
| Directory | /workspace/10.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.4272282425 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 1507870000 ps |
| CPU time | 4.61 seconds |
| Started | Jul 25 04:19:29 PM PDT 24 |
| Finished | Jul 25 04:19:39 PM PDT 24 |
| Peak memory | 164592 kb |
| Host | smart-3b445b41-ff5b-45b7-bc1d-284b061eb41a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4272282425 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.4272282425 |
| Directory | /workspace/11.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.2985006431 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 1384830000 ps |
| CPU time | 4.31 seconds |
| Started | Jul 25 04:19:27 PM PDT 24 |
| Finished | Jul 25 04:19:37 PM PDT 24 |
| Peak memory | 164580 kb |
| Host | smart-e8158b5d-701b-42a5-a3f8-55231569cc73 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2985006431 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.2985006431 |
| Directory | /workspace/12.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.1243718498 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 1545370000 ps |
| CPU time | 3.86 seconds |
| Started | Jul 25 04:20:27 PM PDT 24 |
| Finished | Jul 25 04:20:35 PM PDT 24 |
| Peak memory | 164568 kb |
| Host | smart-be61c3fc-85d8-432a-86eb-9ca93116635c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1243718498 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.1243718498 |
| Directory | /workspace/13.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.1949743200 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 1625770000 ps |
| CPU time | 4.73 seconds |
| Started | Jul 25 04:19:26 PM PDT 24 |
| Finished | Jul 25 04:19:37 PM PDT 24 |
| Peak memory | 164300 kb |
| Host | smart-dfcc6399-db02-4629-b185-4848cb507c54 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1949743200 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.1949743200 |
| Directory | /workspace/14.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.448772739 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 1474850000 ps |
| CPU time | 4.07 seconds |
| Started | Jul 25 04:19:25 PM PDT 24 |
| Finished | Jul 25 04:19:35 PM PDT 24 |
| Peak memory | 164316 kb |
| Host | smart-ed8c47c6-4934-4622-a020-8ad3849fc09e |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=448772739 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.448772739 |
| Directory | /workspace/15.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.3794010110 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 1285110000 ps |
| CPU time | 3.87 seconds |
| Started | Jul 25 04:19:29 PM PDT 24 |
| Finished | Jul 25 04:19:37 PM PDT 24 |
| Peak memory | 163664 kb |
| Host | smart-ff554617-0f42-49c9-bcc9-96294ac5d445 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3794010110 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.3794010110 |
| Directory | /workspace/16.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.1060663600 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 1407610000 ps |
| CPU time | 4.72 seconds |
| Started | Jul 25 04:19:26 PM PDT 24 |
| Finished | Jul 25 04:19:36 PM PDT 24 |
| Peak memory | 164376 kb |
| Host | smart-eea4dd20-3be2-4311-a496-fc670bea9077 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1060663600 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.1060663600 |
| Directory | /workspace/17.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.2800589473 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 1529090000 ps |
| CPU time | 4.3 seconds |
| Started | Jul 25 04:19:29 PM PDT 24 |
| Finished | Jul 25 04:19:39 PM PDT 24 |
| Peak memory | 164176 kb |
| Host | smart-83585a4f-8a22-4261-9e11-ed88a09083ec |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2800589473 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.2800589473 |
| Directory | /workspace/18.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.578343816 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 1207850000 ps |
| CPU time | 3.06 seconds |
| Started | Jul 25 04:19:28 PM PDT 24 |
| Finished | Jul 25 04:19:35 PM PDT 24 |
| Peak memory | 164356 kb |
| Host | smart-dc4c63ec-29d8-49a0-9d09-4ff8ca9d3f14 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=578343816 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.578343816 |
| Directory | /workspace/19.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.1847021853 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 1533770000 ps |
| CPU time | 3.66 seconds |
| Started | Jul 25 04:19:27 PM PDT 24 |
| Finished | Jul 25 04:19:36 PM PDT 24 |
| Peak memory | 164656 kb |
| Host | smart-9873674b-7dd1-4a11-83ce-13fc01b601e8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1847021853 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.1847021853 |
| Directory | /workspace/2.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.2550928526 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 1429610000 ps |
| CPU time | 2.85 seconds |
| Started | Jul 25 04:26:37 PM PDT 24 |
| Finished | Jul 25 04:26:44 PM PDT 24 |
| Peak memory | 164748 kb |
| Host | smart-6d72c7c3-abba-4d8f-8993-dd35eb7f2468 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2550928526 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.2550928526 |
| Directory | /workspace/20.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.934726961 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 1537650000 ps |
| CPU time | 3.07 seconds |
| Started | Jul 25 04:26:39 PM PDT 24 |
| Finished | Jul 25 04:26:46 PM PDT 24 |
| Peak memory | 164744 kb |
| Host | smart-def4b27e-4dfc-4ddc-943d-c4e944afca3a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=934726961 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.934726961 |
| Directory | /workspace/21.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.2003648844 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 1557910000 ps |
| CPU time | 3.42 seconds |
| Started | Jul 25 04:26:34 PM PDT 24 |
| Finished | Jul 25 04:26:42 PM PDT 24 |
| Peak memory | 164668 kb |
| Host | smart-5350a784-36e7-42c2-8b0f-ab13dc4f429f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2003648844 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.2003648844 |
| Directory | /workspace/22.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.555033716 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 1535630000 ps |
| CPU time | 4.1 seconds |
| Started | Jul 25 04:26:36 PM PDT 24 |
| Finished | Jul 25 04:26:46 PM PDT 24 |
| Peak memory | 164704 kb |
| Host | smart-e52bfb19-fe60-4e9a-a4a1-96a492bfbc58 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=555033716 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.555033716 |
| Directory | /workspace/23.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.1443910553 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 1537430000 ps |
| CPU time | 4.16 seconds |
| Started | Jul 25 04:26:38 PM PDT 24 |
| Finished | Jul 25 04:26:48 PM PDT 24 |
| Peak memory | 164680 kb |
| Host | smart-a06d8222-90de-4323-b0a6-8998fc7b9fcb |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1443910553 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.1443910553 |
| Directory | /workspace/24.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.4140020456 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 1470550000 ps |
| CPU time | 3.3 seconds |
| Started | Jul 25 04:26:37 PM PDT 24 |
| Finished | Jul 25 04:26:45 PM PDT 24 |
| Peak memory | 164748 kb |
| Host | smart-aa525e5d-e022-4915-b15d-0329079b1aa5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4140020456 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.4140020456 |
| Directory | /workspace/25.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.3294418265 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 1495750000 ps |
| CPU time | 4.58 seconds |
| Started | Jul 25 04:26:40 PM PDT 24 |
| Finished | Jul 25 04:26:50 PM PDT 24 |
| Peak memory | 164680 kb |
| Host | smart-b4b4537a-3947-4f9c-80f5-3bbe89214aef |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3294418265 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.3294418265 |
| Directory | /workspace/26.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.483234533 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 1399990000 ps |
| CPU time | 3.09 seconds |
| Started | Jul 25 04:26:30 PM PDT 24 |
| Finished | Jul 25 04:26:37 PM PDT 24 |
| Peak memory | 164684 kb |
| Host | smart-63f97e5c-5dfe-4318-946d-d33d4193dc3a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=483234533 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.483234533 |
| Directory | /workspace/27.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.733025046 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 1264830000 ps |
| CPU time | 3.3 seconds |
| Started | Jul 25 04:26:37 PM PDT 24 |
| Finished | Jul 25 04:26:45 PM PDT 24 |
| Peak memory | 164788 kb |
| Host | smart-f3f3f4a7-8d66-41ab-a359-316953e8dbb2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=733025046 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.733025046 |
| Directory | /workspace/28.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.2770130266 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 1526010000 ps |
| CPU time | 3.98 seconds |
| Started | Jul 25 04:26:27 PM PDT 24 |
| Finished | Jul 25 04:26:36 PM PDT 24 |
| Peak memory | 164680 kb |
| Host | smart-0631273b-734d-4a27-be23-01ea5a1dbef3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2770130266 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.2770130266 |
| Directory | /workspace/29.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.3235349060 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 1417190000 ps |
| CPU time | 3.58 seconds |
| Started | Jul 25 04:19:28 PM PDT 24 |
| Finished | Jul 25 04:19:36 PM PDT 24 |
| Peak memory | 164276 kb |
| Host | smart-40fac35f-a7c5-4f5b-9c40-bc64a7fd29b9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3235349060 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.3235349060 |
| Directory | /workspace/3.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.2737655753 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 1450670000 ps |
| CPU time | 3.02 seconds |
| Started | Jul 25 04:26:34 PM PDT 24 |
| Finished | Jul 25 04:26:41 PM PDT 24 |
| Peak memory | 164680 kb |
| Host | smart-c587a511-fde5-442e-a765-2db29b6f1ba8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2737655753 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.2737655753 |
| Directory | /workspace/30.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.3798417105 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 1134010000 ps |
| CPU time | 3.64 seconds |
| Started | Jul 25 04:26:42 PM PDT 24 |
| Finished | Jul 25 04:26:51 PM PDT 24 |
| Peak memory | 164680 kb |
| Host | smart-21745316-4137-4683-902d-6355dd8710c8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3798417105 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.3798417105 |
| Directory | /workspace/31.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.2791936823 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 1406370000 ps |
| CPU time | 3.48 seconds |
| Started | Jul 25 04:26:39 PM PDT 24 |
| Finished | Jul 25 04:26:47 PM PDT 24 |
| Peak memory | 164748 kb |
| Host | smart-778cd8d2-aea4-453e-984a-0540fa4403e9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2791936823 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.2791936823 |
| Directory | /workspace/32.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.3936911843 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 1414690000 ps |
| CPU time | 4.15 seconds |
| Started | Jul 25 04:26:31 PM PDT 24 |
| Finished | Jul 25 04:26:40 PM PDT 24 |
| Peak memory | 164772 kb |
| Host | smart-f706ead6-89ae-41d4-971f-21a892005caf |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3936911843 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.3936911843 |
| Directory | /workspace/33.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.3468197890 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 1376050000 ps |
| CPU time | 4.48 seconds |
| Started | Jul 25 04:26:42 PM PDT 24 |
| Finished | Jul 25 04:26:52 PM PDT 24 |
| Peak memory | 164680 kb |
| Host | smart-62b3959f-9268-40b0-bb2d-b0dee33f91d3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3468197890 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.3468197890 |
| Directory | /workspace/34.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.1439660227 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 1412830000 ps |
| CPU time | 3.7 seconds |
| Started | Jul 25 04:26:47 PM PDT 24 |
| Finished | Jul 25 04:26:55 PM PDT 24 |
| Peak memory | 164768 kb |
| Host | smart-66c2cca9-5670-4131-8e88-90097697d260 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1439660227 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.1439660227 |
| Directory | /workspace/35.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.3310886328 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 1566010000 ps |
| CPU time | 3.41 seconds |
| Started | Jul 25 04:26:52 PM PDT 24 |
| Finished | Jul 25 04:27:00 PM PDT 24 |
| Peak memory | 164680 kb |
| Host | smart-126918b9-5985-4b71-aa2b-634d30e86a4e |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3310886328 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.3310886328 |
| Directory | /workspace/36.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.2619604633 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 1524970000 ps |
| CPU time | 3.31 seconds |
| Started | Jul 25 04:26:30 PM PDT 24 |
| Finished | Jul 25 04:26:37 PM PDT 24 |
| Peak memory | 164684 kb |
| Host | smart-8554404c-f3e7-4dc2-b15a-93d8fb1f3e2c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2619604633 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.2619604633 |
| Directory | /workspace/37.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.2745306529 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 1142430000 ps |
| CPU time | 2.71 seconds |
| Started | Jul 25 04:26:32 PM PDT 24 |
| Finished | Jul 25 04:26:38 PM PDT 24 |
| Peak memory | 164748 kb |
| Host | smart-771f4193-b90b-423e-b9f4-9b3cddf83917 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2745306529 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.2745306529 |
| Directory | /workspace/38.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.3511701153 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 1474230000 ps |
| CPU time | 3.52 seconds |
| Started | Jul 25 04:26:34 PM PDT 24 |
| Finished | Jul 25 04:26:42 PM PDT 24 |
| Peak memory | 164684 kb |
| Host | smart-f7777918-b536-4ef9-841e-91b5810afa0d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3511701153 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.3511701153 |
| Directory | /workspace/39.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.227210233 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 1600730000 ps |
| CPU time | 4.67 seconds |
| Started | Jul 25 04:19:26 PM PDT 24 |
| Finished | Jul 25 04:19:37 PM PDT 24 |
| Peak memory | 163496 kb |
| Host | smart-c5c7a0df-a1a9-4fcd-be0e-33305443144f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=227210233 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.227210233 |
| Directory | /workspace/4.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.1245164047 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 1036330000 ps |
| CPU time | 2.66 seconds |
| Started | Jul 25 04:26:44 PM PDT 24 |
| Finished | Jul 25 04:26:50 PM PDT 24 |
| Peak memory | 164684 kb |
| Host | smart-b551d02d-c3d1-49e9-b32f-47c2d8aa85c4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1245164047 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.1245164047 |
| Directory | /workspace/40.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.1713900778 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 1493270000 ps |
| CPU time | 3.55 seconds |
| Started | Jul 25 04:26:37 PM PDT 24 |
| Finished | Jul 25 04:26:45 PM PDT 24 |
| Peak memory | 164696 kb |
| Host | smart-670a61d8-72b5-440e-9d6f-130d766f6395 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1713900778 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.1713900778 |
| Directory | /workspace/41.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.1062348534 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 1559730000 ps |
| CPU time | 4.1 seconds |
| Started | Jul 25 04:26:36 PM PDT 24 |
| Finished | Jul 25 04:26:46 PM PDT 24 |
| Peak memory | 164752 kb |
| Host | smart-5d364d83-0672-497e-96c8-7c79dfa587a3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1062348534 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.1062348534 |
| Directory | /workspace/42.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.3313528828 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 1438030000 ps |
| CPU time | 3.36 seconds |
| Started | Jul 25 04:26:22 PM PDT 24 |
| Finished | Jul 25 04:26:30 PM PDT 24 |
| Peak memory | 164896 kb |
| Host | smart-0ca27a18-f37d-464f-8d58-50cada24cdf6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3313528828 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.3313528828 |
| Directory | /workspace/43.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.2160838896 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 1509410000 ps |
| CPU time | 3.67 seconds |
| Started | Jul 25 04:26:31 PM PDT 24 |
| Finished | Jul 25 04:26:39 PM PDT 24 |
| Peak memory | 164680 kb |
| Host | smart-9b6ec3f2-9572-4e1c-948f-0069de14d185 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2160838896 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.2160838896 |
| Directory | /workspace/44.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.1581666589 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 1413170000 ps |
| CPU time | 3.39 seconds |
| Started | Jul 25 04:26:40 PM PDT 24 |
| Finished | Jul 25 04:26:48 PM PDT 24 |
| Peak memory | 164644 kb |
| Host | smart-54f684b5-469b-4b70-ad2c-490fe8a89f9a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1581666589 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.1581666589 |
| Directory | /workspace/45.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.3235166323 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 1627890000 ps |
| CPU time | 4.08 seconds |
| Started | Jul 25 04:26:31 PM PDT 24 |
| Finished | Jul 25 04:26:40 PM PDT 24 |
| Peak memory | 164668 kb |
| Host | smart-67fd3a7a-238e-458f-91ad-ab8f7dbdeef7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3235166323 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.3235166323 |
| Directory | /workspace/46.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.3974546882 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 1420550000 ps |
| CPU time | 3.6 seconds |
| Started | Jul 25 04:26:43 PM PDT 24 |
| Finished | Jul 25 04:26:51 PM PDT 24 |
| Peak memory | 164708 kb |
| Host | smart-3cc68646-48ad-4e55-ab0f-bbcc6eea680b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3974546882 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.3974546882 |
| Directory | /workspace/47.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.1664913256 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 1537790000 ps |
| CPU time | 3.58 seconds |
| Started | Jul 25 04:26:37 PM PDT 24 |
| Finished | Jul 25 04:26:45 PM PDT 24 |
| Peak memory | 164696 kb |
| Host | smart-ee220687-e2f8-4724-9d2a-f4a058a6b26c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1664913256 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.1664913256 |
| Directory | /workspace/48.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.1491236390 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 1411290000 ps |
| CPU time | 3.01 seconds |
| Started | Jul 25 04:26:36 PM PDT 24 |
| Finished | Jul 25 04:26:43 PM PDT 24 |
| Peak memory | 164680 kb |
| Host | smart-fe1e071d-b4b2-475f-bfa3-51402de2f4fe |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1491236390 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.1491236390 |
| Directory | /workspace/49.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.2636542615 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 1432730000 ps |
| CPU time | 4.98 seconds |
| Started | Jul 25 04:20:42 PM PDT 24 |
| Finished | Jul 25 04:20:53 PM PDT 24 |
| Peak memory | 164436 kb |
| Host | smart-ffc50f10-8930-4dff-b746-cd0cc1556004 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2636542615 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.2636542615 |
| Directory | /workspace/5.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.4282923654 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 1140630000 ps |
| CPU time | 3.19 seconds |
| Started | Jul 25 04:19:26 PM PDT 24 |
| Finished | Jul 25 04:19:33 PM PDT 24 |
| Peak memory | 163416 kb |
| Host | smart-8381ff86-eba5-4d65-86a9-0622f9d34b28 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4282923654 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.4282923654 |
| Directory | /workspace/6.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.3923640440 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 1469870000 ps |
| CPU time | 4.25 seconds |
| Started | Jul 25 04:19:25 PM PDT 24 |
| Finished | Jul 25 04:19:34 PM PDT 24 |
| Peak memory | 163272 kb |
| Host | smart-aa1c8e62-3f67-4196-b7c2-681d3cbf7ca5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3923640440 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.3923640440 |
| Directory | /workspace/7.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.538411454 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 1504050000 ps |
| CPU time | 3.77 seconds |
| Started | Jul 25 04:19:27 PM PDT 24 |
| Finished | Jul 25 04:19:36 PM PDT 24 |
| Peak memory | 164392 kb |
| Host | smart-8c86c52f-a6b1-41bc-a855-1f4d0ae567dc |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=538411454 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.538411454 |
| Directory | /workspace/8.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.452033741 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 1532890000 ps |
| CPU time | 5.07 seconds |
| Started | Jul 25 04:19:25 PM PDT 24 |
| Finished | Jul 25 04:19:37 PM PDT 24 |
| Peak memory | 163496 kb |
| Host | smart-80e12756-01a1-4459-9dfc-689dd2949c5b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=452033741 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.452033741 |
| Directory | /workspace/9.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.3070640898 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 1563730000 ps |
| CPU time | 4.96 seconds |
| Started | Jul 25 04:22:35 PM PDT 24 |
| Finished | Jul 25 04:22:45 PM PDT 24 |
| Peak memory | 164768 kb |
| Host | smart-a6ebf384-fc41-4dd8-8659-dbf3b6a114fe |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3070640898 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.3070640898 |
| Directory | /workspace/0.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.4184758491 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 1591510000 ps |
| CPU time | 3.66 seconds |
| Started | Jul 25 04:24:29 PM PDT 24 |
| Finished | Jul 25 04:24:38 PM PDT 24 |
| Peak memory | 163284 kb |
| Host | smart-6600e5fe-99e4-48a4-bfbc-6fe45f7c828b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4184758491 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.4184758491 |
| Directory | /workspace/10.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.501942410 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 1375550000 ps |
| CPU time | 2.78 seconds |
| Started | Jul 25 04:24:20 PM PDT 24 |
| Finished | Jul 25 04:24:26 PM PDT 24 |
| Peak memory | 164324 kb |
| Host | smart-2904b1d5-c0f3-4dae-bfa1-68b5d8b6a363 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=501942410 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.501942410 |
| Directory | /workspace/11.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.1811612119 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 1515910000 ps |
| CPU time | 3.27 seconds |
| Started | Jul 25 04:24:30 PM PDT 24 |
| Finished | Jul 25 04:24:37 PM PDT 24 |
| Peak memory | 164320 kb |
| Host | smart-0dd02801-64a4-4c37-8b0f-44a02579ee53 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1811612119 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.1811612119 |
| Directory | /workspace/12.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.2434713734 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 1545550000 ps |
| CPU time | 4.14 seconds |
| Started | Jul 25 04:21:57 PM PDT 24 |
| Finished | Jul 25 04:22:07 PM PDT 24 |
| Peak memory | 164504 kb |
| Host | smart-696497d8-0464-4754-b55f-3a024f27295b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2434713734 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.2434713734 |
| Directory | /workspace/13.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.3326452024 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 1461170000 ps |
| CPU time | 4.35 seconds |
| Started | Jul 25 04:21:38 PM PDT 24 |
| Finished | Jul 25 04:21:48 PM PDT 24 |
| Peak memory | 164976 kb |
| Host | smart-e6b3b3e3-0c7c-4c62-8df7-5b161ad577c7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3326452024 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.3326452024 |
| Directory | /workspace/14.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.3457215579 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 1503210000 ps |
| CPU time | 4.45 seconds |
| Started | Jul 25 04:24:37 PM PDT 24 |
| Finished | Jul 25 04:24:46 PM PDT 24 |
| Peak memory | 164536 kb |
| Host | smart-7a7a6395-4971-4944-9539-a7c9958fc5b5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3457215579 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.3457215579 |
| Directory | /workspace/15.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.605249276 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 1342950000 ps |
| CPU time | 3.46 seconds |
| Started | Jul 25 04:24:48 PM PDT 24 |
| Finished | Jul 25 04:24:56 PM PDT 24 |
| Peak memory | 163804 kb |
| Host | smart-3d75ab83-8281-481c-baaa-ff233b9f30cd |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=605249276 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.605249276 |
| Directory | /workspace/16.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.2905385208 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 1497430000 ps |
| CPU time | 3.19 seconds |
| Started | Jul 25 04:24:48 PM PDT 24 |
| Finished | Jul 25 04:24:55 PM PDT 24 |
| Peak memory | 164468 kb |
| Host | smart-2d11d07c-029b-4859-8523-9a4a1569f83b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2905385208 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.2905385208 |
| Directory | /workspace/17.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.2423394553 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 1081910000 ps |
| CPU time | 2.49 seconds |
| Started | Jul 25 04:24:49 PM PDT 24 |
| Finished | Jul 25 04:24:54 PM PDT 24 |
| Peak memory | 164468 kb |
| Host | smart-3533eadc-a8b6-4583-9f91-a0a4641181d1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2423394553 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.2423394553 |
| Directory | /workspace/18.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.2997959043 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 1234610000 ps |
| CPU time | 3.43 seconds |
| Started | Jul 25 04:19:29 PM PDT 24 |
| Finished | Jul 25 04:19:37 PM PDT 24 |
| Peak memory | 164364 kb |
| Host | smart-b22c5a11-fe4a-4520-b226-48f25d46501a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2997959043 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.2997959043 |
| Directory | /workspace/19.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.2101766803 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 1666130000 ps |
| CPU time | 5.32 seconds |
| Started | Jul 25 04:23:06 PM PDT 24 |
| Finished | Jul 25 04:23:18 PM PDT 24 |
| Peak memory | 164768 kb |
| Host | smart-71f9fe10-7d24-48f2-9106-c327c2e2c390 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2101766803 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.2101766803 |
| Directory | /workspace/2.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.3314642564 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 1550990000 ps |
| CPU time | 5.19 seconds |
| Started | Jul 25 04:22:16 PM PDT 24 |
| Finished | Jul 25 04:22:27 PM PDT 24 |
| Peak memory | 164616 kb |
| Host | smart-09160a19-2035-4551-99a3-d5e8b2fb1aa6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3314642564 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.3314642564 |
| Directory | /workspace/20.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.2637402774 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 1493070000 ps |
| CPU time | 3.35 seconds |
| Started | Jul 25 04:21:09 PM PDT 24 |
| Finished | Jul 25 04:21:17 PM PDT 24 |
| Peak memory | 164600 kb |
| Host | smart-9bc8c1d3-4897-4845-ba54-347f5ed7a963 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2637402774 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.2637402774 |
| Directory | /workspace/21.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.3571258154 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 1517530000 ps |
| CPU time | 5.09 seconds |
| Started | Jul 25 04:21:53 PM PDT 24 |
| Finished | Jul 25 04:22:04 PM PDT 24 |
| Peak memory | 164708 kb |
| Host | smart-e0c6ad2a-208f-4650-a8c6-1aafa06580b0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3571258154 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.3571258154 |
| Directory | /workspace/22.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.2529364718 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 1607230000 ps |
| CPU time | 5.26 seconds |
| Started | Jul 25 04:21:09 PM PDT 24 |
| Finished | Jul 25 04:21:21 PM PDT 24 |
| Peak memory | 164656 kb |
| Host | smart-da501304-1bed-4a4a-9d8b-14f6c22cf912 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2529364718 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.2529364718 |
| Directory | /workspace/23.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.577682844 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 1563970000 ps |
| CPU time | 4.65 seconds |
| Started | Jul 25 04:24:24 PM PDT 24 |
| Finished | Jul 25 04:24:35 PM PDT 24 |
| Peak memory | 164324 kb |
| Host | smart-9806d81a-802c-40b2-a945-7c4219575f34 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=577682844 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.577682844 |
| Directory | /workspace/24.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.4070284558 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 1269730000 ps |
| CPU time | 3.86 seconds |
| Started | Jul 25 04:20:26 PM PDT 24 |
| Finished | Jul 25 04:20:34 PM PDT 24 |
| Peak memory | 164660 kb |
| Host | smart-30ef6add-cfc4-4e18-88f9-5656b4880381 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4070284558 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.4070284558 |
| Directory | /workspace/25.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.192366549 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 1491390000 ps |
| CPU time | 4.42 seconds |
| Started | Jul 25 04:22:29 PM PDT 24 |
| Finished | Jul 25 04:22:39 PM PDT 24 |
| Peak memory | 164660 kb |
| Host | smart-c8a501b0-94c6-487d-9e5c-8bc19dda5e54 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=192366549 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.192366549 |
| Directory | /workspace/26.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.1563357387 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 1489630000 ps |
| CPU time | 3.92 seconds |
| Started | Jul 25 04:24:36 PM PDT 24 |
| Finished | Jul 25 04:24:45 PM PDT 24 |
| Peak memory | 164348 kb |
| Host | smart-9caeac98-5d55-4662-8a24-076e1ba5fc2a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1563357387 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.1563357387 |
| Directory | /workspace/27.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.244887745 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 1397370000 ps |
| CPU time | 3.01 seconds |
| Started | Jul 25 04:24:13 PM PDT 24 |
| Finished | Jul 25 04:24:20 PM PDT 24 |
| Peak memory | 163252 kb |
| Host | smart-edef10cb-e6b2-4b83-9483-c1cb90a6ab99 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=244887745 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.244887745 |
| Directory | /workspace/28.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.837830137 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 1371290000 ps |
| CPU time | 4.45 seconds |
| Started | Jul 25 04:22:41 PM PDT 24 |
| Finished | Jul 25 04:22:51 PM PDT 24 |
| Peak memory | 164772 kb |
| Host | smart-e1707feb-593b-4fe6-bfc9-72b2d2428c32 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=837830137 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.837830137 |
| Directory | /workspace/29.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.611533887 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 1327910000 ps |
| CPU time | 3.77 seconds |
| Started | Jul 25 04:24:57 PM PDT 24 |
| Finished | Jul 25 04:25:06 PM PDT 24 |
| Peak memory | 164940 kb |
| Host | smart-eee9e735-93a5-4df3-9933-efd78a59925b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=611533887 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.611533887 |
| Directory | /workspace/3.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.2412831094 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 1301350000 ps |
| CPU time | 2.96 seconds |
| Started | Jul 25 04:24:13 PM PDT 24 |
| Finished | Jul 25 04:24:20 PM PDT 24 |
| Peak memory | 164660 kb |
| Host | smart-d8902f81-2536-44b5-b680-89d0e526d3cb |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2412831094 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.2412831094 |
| Directory | /workspace/30.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.3818368587 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 1481530000 ps |
| CPU time | 3.96 seconds |
| Started | Jul 25 04:24:35 PM PDT 24 |
| Finished | Jul 25 04:24:44 PM PDT 24 |
| Peak memory | 164392 kb |
| Host | smart-4c7dc459-5ff4-44b0-8b92-9caab8c92361 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3818368587 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.3818368587 |
| Directory | /workspace/31.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.498720365 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 1483270000 ps |
| CPU time | 3.48 seconds |
| Started | Jul 25 04:24:11 PM PDT 24 |
| Finished | Jul 25 04:24:19 PM PDT 24 |
| Peak memory | 163288 kb |
| Host | smart-ef9de13f-2048-42b5-b959-7f8ea764abbb |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=498720365 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.498720365 |
| Directory | /workspace/32.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.1112051346 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 1537950000 ps |
| CPU time | 3.44 seconds |
| Started | Jul 25 04:24:26 PM PDT 24 |
| Finished | Jul 25 04:24:33 PM PDT 24 |
| Peak memory | 164464 kb |
| Host | smart-b4ccb561-5714-4121-b72e-62a22dde58e9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1112051346 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.1112051346 |
| Directory | /workspace/33.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.3590575351 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 1369090000 ps |
| CPU time | 3.22 seconds |
| Started | Jul 25 04:24:11 PM PDT 24 |
| Finished | Jul 25 04:24:19 PM PDT 24 |
| Peak memory | 163872 kb |
| Host | smart-c653abac-fe5a-4906-8d80-3e3e50c40870 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3590575351 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.3590575351 |
| Directory | /workspace/34.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.1191755725 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 1610850000 ps |
| CPU time | 5.13 seconds |
| Started | Jul 25 04:22:34 PM PDT 24 |
| Finished | Jul 25 04:22:46 PM PDT 24 |
| Peak memory | 164768 kb |
| Host | smart-ae3a7926-6068-4534-9b88-e1e2e089ab8a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1191755725 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.1191755725 |
| Directory | /workspace/35.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.4180297555 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 1577830000 ps |
| CPU time | 4.38 seconds |
| Started | Jul 25 04:22:29 PM PDT 24 |
| Finished | Jul 25 04:22:39 PM PDT 24 |
| Peak memory | 164656 kb |
| Host | smart-1b572ddd-c70e-4e0f-8458-cefab145d475 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4180297555 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.4180297555 |
| Directory | /workspace/36.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.2092340408 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 1420310000 ps |
| CPU time | 3.43 seconds |
| Started | Jul 25 04:24:01 PM PDT 24 |
| Finished | Jul 25 04:24:09 PM PDT 24 |
| Peak memory | 164160 kb |
| Host | smart-b3499fd5-438f-47ed-bc37-fb687f690305 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2092340408 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.2092340408 |
| Directory | /workspace/37.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.96292645 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 1474990000 ps |
| CPU time | 3.33 seconds |
| Started | Jul 25 04:25:03 PM PDT 24 |
| Finished | Jul 25 04:25:11 PM PDT 24 |
| Peak memory | 165004 kb |
| Host | smart-8db742e6-808b-4510-9e5b-c5883d06f677 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=96292645 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.96292645 |
| Directory | /workspace/38.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.2573155847 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 1490310000 ps |
| CPU time | 4.18 seconds |
| Started | Jul 25 04:24:12 PM PDT 24 |
| Finished | Jul 25 04:24:22 PM PDT 24 |
| Peak memory | 163924 kb |
| Host | smart-d8b5c23b-2e24-4da7-811a-bc0831d2bdbd |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2573155847 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.2573155847 |
| Directory | /workspace/39.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.1447988757 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 1467390000 ps |
| CPU time | 3.68 seconds |
| Started | Jul 25 04:24:29 PM PDT 24 |
| Finished | Jul 25 04:24:38 PM PDT 24 |
| Peak memory | 163888 kb |
| Host | smart-4f975dab-0ab3-468d-a939-30bd08c1245b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1447988757 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.1447988757 |
| Directory | /workspace/4.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.296258008 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 1521330000 ps |
| CPU time | 3.36 seconds |
| Started | Jul 25 04:24:31 PM PDT 24 |
| Finished | Jul 25 04:24:38 PM PDT 24 |
| Peak memory | 164320 kb |
| Host | smart-c0bc46b3-6d8a-45cb-8ac7-97be3e521aa7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=296258008 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.296258008 |
| Directory | /workspace/40.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.455350910 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 1529890000 ps |
| CPU time | 3.32 seconds |
| Started | Jul 25 04:25:04 PM PDT 24 |
| Finished | Jul 25 04:25:12 PM PDT 24 |
| Peak memory | 164320 kb |
| Host | smart-2e098f60-c2e6-4b62-97b1-bbbed12a43f5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=455350910 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.455350910 |
| Directory | /workspace/41.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.2031303909 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 1435550000 ps |
| CPU time | 4.15 seconds |
| Started | Jul 25 04:20:20 PM PDT 24 |
| Finished | Jul 25 04:20:29 PM PDT 24 |
| Peak memory | 164660 kb |
| Host | smart-4903db78-f759-4956-b539-822a90fe9b08 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2031303909 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.2031303909 |
| Directory | /workspace/42.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.3303074844 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 1528270000 ps |
| CPU time | 3.3 seconds |
| Started | Jul 25 04:24:23 PM PDT 24 |
| Finished | Jul 25 04:24:31 PM PDT 24 |
| Peak memory | 164020 kb |
| Host | smart-595e9f5b-2f9c-4fb6-bfd6-a95d2d5fe585 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3303074844 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.3303074844 |
| Directory | /workspace/43.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.3951457086 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 1553810000 ps |
| CPU time | 4.12 seconds |
| Started | Jul 25 04:24:22 PM PDT 24 |
| Finished | Jul 25 04:24:31 PM PDT 24 |
| Peak memory | 164348 kb |
| Host | smart-5a8b4650-10e5-45dc-b1c4-4b29495826a3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3951457086 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.3951457086 |
| Directory | /workspace/44.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.1697646387 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 1533910000 ps |
| CPU time | 4.43 seconds |
| Started | Jul 25 04:24:12 PM PDT 24 |
| Finished | Jul 25 04:24:22 PM PDT 24 |
| Peak memory | 163284 kb |
| Host | smart-fdeeadd0-087c-47ee-8273-fdcd564bb737 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1697646387 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.1697646387 |
| Directory | /workspace/45.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.1022700352 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 1575550000 ps |
| CPU time | 4.95 seconds |
| Started | Jul 25 04:23:09 PM PDT 24 |
| Finished | Jul 25 04:23:20 PM PDT 24 |
| Peak memory | 164708 kb |
| Host | smart-598a9328-a4ce-498a-a80c-a1c85e55b0d9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1022700352 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.1022700352 |
| Directory | /workspace/46.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.3555400698 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 1418210000 ps |
| CPU time | 3.62 seconds |
| Started | Jul 25 04:24:29 PM PDT 24 |
| Finished | Jul 25 04:24:37 PM PDT 24 |
| Peak memory | 164536 kb |
| Host | smart-0452aab0-6416-4a7c-bb61-90c9916fcf3f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3555400698 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.3555400698 |
| Directory | /workspace/47.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.130732410 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 1510610000 ps |
| CPU time | 3.26 seconds |
| Started | Jul 25 04:24:13 PM PDT 24 |
| Finished | Jul 25 04:24:20 PM PDT 24 |
| Peak memory | 164324 kb |
| Host | smart-7655b4d2-9e9d-4314-802b-a513e5833d63 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=130732410 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.130732410 |
| Directory | /workspace/48.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.3360739074 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 1296190000 ps |
| CPU time | 3.55 seconds |
| Started | Jul 25 04:25:06 PM PDT 24 |
| Finished | Jul 25 04:25:14 PM PDT 24 |
| Peak memory | 164608 kb |
| Host | smart-441eb52b-a0f6-4390-baef-06300890a2c6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3360739074 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.3360739074 |
| Directory | /workspace/49.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.3084051481 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 1381190000 ps |
| CPU time | 4.28 seconds |
| Started | Jul 25 04:21:22 PM PDT 24 |
| Finished | Jul 25 04:21:32 PM PDT 24 |
| Peak memory | 164656 kb |
| Host | smart-1b64da4b-1c9f-4516-a4e6-b71a2fa2c4ce |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3084051481 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.3084051481 |
| Directory | /workspace/5.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.2913536266 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 1538610000 ps |
| CPU time | 5.11 seconds |
| Started | Jul 25 04:20:09 PM PDT 24 |
| Finished | Jul 25 04:20:21 PM PDT 24 |
| Peak memory | 164520 kb |
| Host | smart-dd48847b-4b06-49a0-8a78-ccec4f6ccdf8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2913536266 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.2913536266 |
| Directory | /workspace/6.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.477728620 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 1431290000 ps |
| CPU time | 4.4 seconds |
| Started | Jul 25 04:20:36 PM PDT 24 |
| Finished | Jul 25 04:20:46 PM PDT 24 |
| Peak memory | 164916 kb |
| Host | smart-8912e675-ec2b-497f-a198-761b62d0feb9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=477728620 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.477728620 |
| Directory | /workspace/7.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.435594027 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 1493590000 ps |
| CPU time | 3.74 seconds |
| Started | Jul 25 04:24:36 PM PDT 24 |
| Finished | Jul 25 04:24:45 PM PDT 24 |
| Peak memory | 164472 kb |
| Host | smart-b916833c-374a-4ec7-a305-fc48130c556b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=435594027 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.435594027 |
| Directory | /workspace/8.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.1340179092 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 1429950000 ps |
| CPU time | 3.85 seconds |
| Started | Jul 25 04:24:36 PM PDT 24 |
| Finished | Jul 25 04:24:45 PM PDT 24 |
| Peak memory | 164468 kb |
| Host | smart-cde17d2f-ec5c-4ad4-8daf-ad669f0a1ba5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1340179092 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.1340179092 |
| Directory | /workspace/9.prim_lfsr_gal_smoke/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |