Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.31 100.00 96.55 100.00 100.00 95.00


Total tests in report: 200
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
87.31 87.31 100.00 100.00 96.55 96.55 100.00 100.00 100.00 100.00 40.00 40.00 /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.1572081693
96.81 9.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 87.50 47.50 /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.2963074047
98.31 1.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 95.00 7.50 /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.3596523337

Tests that do not contribute to grading

Name
/workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.2734257968
/workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.503653736
/workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.4194828709
/workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.1852847161
/workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.759110354
/workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.2795685389
/workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.2947510711
/workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.3800834829
/workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.1827083609
/workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.2156208420
/workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.3381813670
/workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.18543743
/workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.2646501576
/workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.2093744626
/workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.1971941799
/workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.2659887468
/workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.3726169514
/workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.378097787
/workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1467235059
/workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.3084034585
/workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.1854021498
/workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.3352356628
/workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.2207979238
/workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3624092854
/workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.248322735
/workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.1121391866
/workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.3869675260
/workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.4159510386
/workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.343333275
/workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.2755456362
/workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.2468858737
/workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.2071894311
/workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.3653422677
/workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.4125761512
/workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.2788731497
/workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.1154148799
/workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.847035955
/workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.54886889
/workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.4206939543
/workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.130493209
/workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.3680191579
/workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.2056088418
/workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.607831917
/workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.1350498310
/workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.3706101035
/workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.1350174136
/workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.3193650865
/workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.790448714
/workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.3492720748
/workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.1348395884
/workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.1719315060
/workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.1709541764
/workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.914748354
/workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.3896739887
/workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.2046412386
/workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.360869831
/workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.2572721404
/workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.3307862455
/workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.4014361874
/workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.3002577234
/workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.1204046645
/workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.712574570
/workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.1155016678
/workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.2865198607
/workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.494836187
/workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.2305194120
/workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.3504682628
/workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.3487269648
/workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.3711292625
/workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.1128974284
/workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.677445108
/workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.3680062432
/workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.3118692350
/workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.377144050
/workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.1269033028
/workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.1291143158
/workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.3515380104
/workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.3035249439
/workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.505353317
/workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.456856935
/workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.427024483
/workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.38856742
/workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.3291780094
/workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.2126741101
/workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.1437873075
/workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.396033172
/workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.120587945
/workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.4101286464
/workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.789042402
/workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.88611630
/workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.101323200
/workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.869797834
/workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.628883918
/workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.1578977400
/workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.3025600780
/workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.3556966262
/workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.3594252439
/workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.3847220966
/workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.2138198035
/workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.128109599
/workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.137636459
/workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.3954311046
/workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.3355767529
/workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.194738191
/workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.3933943273
/workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.4178135842
/workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.2297815005
/workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.1947995490
/workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.3008404379
/workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.2320664772
/workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.2594550279
/workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.3106701447
/workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.2487174086
/workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.1014029268
/workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.1512339060
/workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.2484813856
/workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.3355829794
/workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.4061142507
/workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.3720355884
/workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.111444707
/workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.604418102
/workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.2342329167
/workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.2771744248
/workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.4280961112
/workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.26558511
/workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.3416388498
/workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.2165510406
/workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.180918881
/workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.574146337
/workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.679629135
/workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.3131293311
/workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.4290698092
/workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3774116507
/workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.3839847987
/workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.2318337635
/workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.3430670447
/workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.2377778362
/workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.3751923823
/workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.710233745
/workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.526859182
/workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.1547809867
/workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.3417200734
/workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.3414605931
/workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.544789277
/workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.4007133937
/workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.1827615775
/workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1643406220
/workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.409346939
/workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.816675890
/workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.1153155077
/workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.3200956977
/workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.1841710190
/workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.1581406717
/workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.255307087
/workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.3164759886
/workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.3226768387
/workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.611307828
/workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.3182505045
/workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.957158423
/workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.2367929773
/workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.467858376
/workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.171535991
/workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.333966543
/workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.785892536
/workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.4130046116
/workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.2047113946
/workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.2363033322
/workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.3535609365
/workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.108225722
/workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.3754173630
/workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.3429555954
/workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.1719259000
/workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.1472832468
/workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.3256314713
/workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.938880444
/workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.1513010996
/workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.3663701524
/workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.664864679
/workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.1834927348
/workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.678296450
/workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.3491433005
/workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.1468505412
/workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.1402103252
/workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.990961886
/workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.2698517742
/workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.1162881013
/workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.4094769249
/workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.3407231291
/workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.3977848371
/workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.2571849840
/workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.3467484600
/workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.2717749340
/workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.1584019235
/workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.1006070424
/workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.1640043059
/workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.480027025
/workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.3091845867



Total test records in report: 200
tests.html | tests1.html | tests2.html | tests3.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.3467484600 Jul 27 04:22:27 PM PDT 24 Jul 27 04:22:36 PM PDT 24 1523170000 ps
T2 /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.467858376 Jul 27 04:22:04 PM PDT 24 Jul 27 04:22:15 PM PDT 24 1528730000 ps
T3 /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.480027025 Jul 27 04:19:59 PM PDT 24 Jul 27 04:20:10 PM PDT 24 1509610000 ps
T7 /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.1572081693 Jul 27 04:18:27 PM PDT 24 Jul 27 04:18:39 PM PDT 24 1522610000 ps
T8 /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.957158423 Jul 27 04:22:01 PM PDT 24 Jul 27 04:22:10 PM PDT 24 1460170000 ps
T9 /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.3491433005 Jul 27 04:22:38 PM PDT 24 Jul 27 04:22:47 PM PDT 24 1346170000 ps
T10 /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.1468505412 Jul 27 04:18:19 PM PDT 24 Jul 27 04:18:30 PM PDT 24 1594550000 ps
T11 /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.333966543 Jul 27 04:18:18 PM PDT 24 Jul 27 04:18:28 PM PDT 24 1416530000 ps
T12 /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.108225722 Jul 27 04:17:36 PM PDT 24 Jul 27 04:17:47 PM PDT 24 1570170000 ps
T13 /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.1513010996 Jul 27 04:22:27 PM PDT 24 Jul 27 04:22:35 PM PDT 24 1213490000 ps
T31 /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.2571849840 Jul 27 04:19:28 PM PDT 24 Jul 27 04:19:36 PM PDT 24 1454870000 ps
T32 /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.1841710190 Jul 27 04:22:07 PM PDT 24 Jul 27 04:22:18 PM PDT 24 1541330000 ps
T33 /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.1162881013 Jul 27 04:22:21 PM PDT 24 Jul 27 04:22:28 PM PDT 24 1519610000 ps
T34 /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.611307828 Jul 27 04:17:57 PM PDT 24 Jul 27 04:18:04 PM PDT 24 1388990000 ps
T35 /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.3977848371 Jul 27 04:22:34 PM PDT 24 Jul 27 04:22:41 PM PDT 24 1437430000 ps
T36 /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.3226768387 Jul 27 04:22:01 PM PDT 24 Jul 27 04:22:09 PM PDT 24 1477290000 ps
T37 /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.2367929773 Jul 27 04:18:05 PM PDT 24 Jul 27 04:18:13 PM PDT 24 1591150000 ps
T38 /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.171535991 Jul 27 04:22:38 PM PDT 24 Jul 27 04:22:46 PM PDT 24 1535510000 ps
T39 /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.1834927348 Jul 27 04:23:04 PM PDT 24 Jul 27 04:23:13 PM PDT 24 1180010000 ps
T40 /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.1581406717 Jul 27 04:22:07 PM PDT 24 Jul 27 04:22:16 PM PDT 24 1128950000 ps
T41 /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.3182505045 Jul 27 04:21:03 PM PDT 24 Jul 27 04:21:14 PM PDT 24 1544330000 ps
T42 /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.3256314713 Jul 27 04:18:41 PM PDT 24 Jul 27 04:18:50 PM PDT 24 1493410000 ps
T43 /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.1472832468 Jul 27 04:18:53 PM PDT 24 Jul 27 04:19:01 PM PDT 24 1288850000 ps
T44 /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.678296450 Jul 27 04:22:30 PM PDT 24 Jul 27 04:22:41 PM PDT 24 1438010000 ps
T45 /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.2698517742 Jul 27 04:22:38 PM PDT 24 Jul 27 04:22:47 PM PDT 24 1464010000 ps
T46 /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.816675890 Jul 27 04:19:34 PM PDT 24 Jul 27 04:19:44 PM PDT 24 1542950000 ps
T47 /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.3535609365 Jul 27 04:18:28 PM PDT 24 Jul 27 04:18:40 PM PDT 24 1548010000 ps
T48 /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.2717749340 Jul 27 04:23:15 PM PDT 24 Jul 27 04:23:23 PM PDT 24 1413210000 ps
T49 /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.3164759886 Jul 27 04:22:20 PM PDT 24 Jul 27 04:22:29 PM PDT 24 1396030000 ps
T50 /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.3429555954 Jul 27 04:18:26 PM PDT 24 Jul 27 04:18:33 PM PDT 24 1527930000 ps
T51 /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.1719259000 Jul 27 04:18:41 PM PDT 24 Jul 27 04:18:49 PM PDT 24 1222490000 ps
T52 /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.990961886 Jul 27 04:23:04 PM PDT 24 Jul 27 04:23:14 PM PDT 24 1467170000 ps
T53 /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.1006070424 Jul 27 04:17:58 PM PDT 24 Jul 27 04:18:09 PM PDT 24 1230030000 ps
T54 /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.4130046116 Jul 27 04:22:33 PM PDT 24 Jul 27 04:22:44 PM PDT 24 1566790000 ps
T55 /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.785892536 Jul 27 04:22:20 PM PDT 24 Jul 27 04:22:28 PM PDT 24 1413750000 ps
T56 /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.3200956977 Jul 27 04:19:59 PM PDT 24 Jul 27 04:20:09 PM PDT 24 1502650000 ps
T57 /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.938880444 Jul 27 04:18:40 PM PDT 24 Jul 27 04:18:50 PM PDT 24 1416930000 ps
T58 /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.3754173630 Jul 27 04:18:02 PM PDT 24 Jul 27 04:18:11 PM PDT 24 1551690000 ps
T59 /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.4094769249 Jul 27 04:22:28 PM PDT 24 Jul 27 04:22:36 PM PDT 24 1415310000 ps
T60 /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.1584019235 Jul 27 04:18:27 PM PDT 24 Jul 27 04:18:35 PM PDT 24 1182370000 ps
T61 /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.3663701524 Jul 27 04:22:32 PM PDT 24 Jul 27 04:22:41 PM PDT 24 1430990000 ps
T62 /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.3091845867 Jul 27 04:22:31 PM PDT 24 Jul 27 04:22:41 PM PDT 24 1445410000 ps
T63 /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.664864679 Jul 27 04:22:38 PM PDT 24 Jul 27 04:22:47 PM PDT 24 1497530000 ps
T64 /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.2047113946 Jul 27 04:22:27 PM PDT 24 Jul 27 04:22:37 PM PDT 24 1434070000 ps
T65 /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.1402103252 Jul 27 04:23:03 PM PDT 24 Jul 27 04:23:13 PM PDT 24 1328630000 ps
T66 /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.1640043059 Jul 27 04:22:32 PM PDT 24 Jul 27 04:22:43 PM PDT 24 1575170000 ps
T67 /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.1153155077 Jul 27 04:19:32 PM PDT 24 Jul 27 04:19:41 PM PDT 24 1551170000 ps
T68 /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.2363033322 Jul 27 04:22:20 PM PDT 24 Jul 27 04:22:30 PM PDT 24 1426810000 ps
T69 /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.3407231291 Jul 27 04:22:25 PM PDT 24 Jul 27 04:22:32 PM PDT 24 1451110000 ps
T70 /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.255307087 Jul 27 04:22:30 PM PDT 24 Jul 27 04:22:39 PM PDT 24 1567650000 ps
T4 /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.2963074047 Jul 27 04:22:22 PM PDT 24 Jul 27 04:58:17 PM PDT 24 336749630000 ps
T5 /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.2156208420 Jul 27 04:22:20 PM PDT 24 Jul 27 04:49:38 PM PDT 24 336387510000 ps
T6 /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.1350174136 Jul 27 04:22:31 PM PDT 24 Jul 27 04:49:56 PM PDT 24 336488690000 ps
T14 /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.378097787 Jul 27 04:18:57 PM PDT 24 Jul 27 04:54:57 PM PDT 24 336509070000 ps
T15 /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.248322735 Jul 27 04:22:18 PM PDT 24 Jul 27 04:55:06 PM PDT 24 336861670000 ps
T16 /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.54886889 Jul 27 04:18:28 PM PDT 24 Jul 27 04:54:24 PM PDT 24 336727630000 ps
T17 /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.2056088418 Jul 27 04:22:22 PM PDT 24 Jul 27 04:51:35 PM PDT 24 337014690000 ps
T18 /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.18543743 Jul 27 04:22:21 PM PDT 24 Jul 27 04:54:54 PM PDT 24 336412230000 ps
T19 /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.3381813670 Jul 27 04:20:34 PM PDT 24 Jul 27 04:55:53 PM PDT 24 337076930000 ps
T20 /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.2788731497 Jul 27 04:22:25 PM PDT 24 Jul 27 04:51:45 PM PDT 24 336870990000 ps
T71 /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.1827083609 Jul 27 04:22:07 PM PDT 24 Jul 27 04:56:26 PM PDT 24 336387670000 ps
T72 /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.4125761512 Jul 27 04:18:48 PM PDT 24 Jul 27 04:48:48 PM PDT 24 336347290000 ps
T73 /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.3869675260 Jul 27 04:22:26 PM PDT 24 Jul 27 04:48:28 PM PDT 24 336338010000 ps
T74 /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.343333275 Jul 27 04:22:20 PM PDT 24 Jul 27 04:54:43 PM PDT 24 336486170000 ps
T75 /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.3193650865 Jul 27 04:22:23 PM PDT 24 Jul 27 04:46:27 PM PDT 24 337069470000 ps
T76 /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.3726169514 Jul 27 04:22:26 PM PDT 24 Jul 27 04:47:46 PM PDT 24 336430030000 ps
T77 /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.4194828709 Jul 27 04:20:34 PM PDT 24 Jul 27 04:49:53 PM PDT 24 337105910000 ps
T78 /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.3653422677 Jul 27 04:22:33 PM PDT 24 Jul 27 04:50:06 PM PDT 24 336483290000 ps
T79 /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.3352356628 Jul 27 04:22:21 PM PDT 24 Jul 27 04:54:33 PM PDT 24 336638950000 ps
T80 /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.2947510711 Jul 27 04:19:16 PM PDT 24 Jul 27 04:50:54 PM PDT 24 337047870000 ps
T81 /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.503653736 Jul 27 04:22:21 PM PDT 24 Jul 27 04:54:42 PM PDT 24 336736450000 ps
T82 /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.3680191579 Jul 27 04:22:27 PM PDT 24 Jul 27 04:51:19 PM PDT 24 336889670000 ps
T83 /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.1350498310 Jul 27 04:22:20 PM PDT 24 Jul 27 04:51:57 PM PDT 24 336516190000 ps
T84 /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.2468858737 Jul 27 04:19:15 PM PDT 24 Jul 27 05:00:13 PM PDT 24 336572770000 ps
T85 /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.3084034585 Jul 27 04:22:27 PM PDT 24 Jul 27 04:48:07 PM PDT 24 337170270000 ps
T86 /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.3706101035 Jul 27 04:22:33 PM PDT 24 Jul 27 04:47:20 PM PDT 24 336658370000 ps
T87 /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.759110354 Jul 27 04:22:06 PM PDT 24 Jul 27 04:56:49 PM PDT 24 336588390000 ps
T88 /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.3492720748 Jul 27 04:22:07 PM PDT 24 Jul 27 04:55:58 PM PDT 24 336970250000 ps
T89 /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.130493209 Jul 27 04:22:06 PM PDT 24 Jul 27 04:50:28 PM PDT 24 336457410000 ps
T90 /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.2734257968 Jul 27 04:22:22 PM PDT 24 Jul 27 04:54:42 PM PDT 24 336367730000 ps
T91 /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.607831917 Jul 27 04:22:22 PM PDT 24 Jul 27 04:52:15 PM PDT 24 336930770000 ps
T92 /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.847035955 Jul 27 04:23:12 PM PDT 24 Jul 27 04:54:04 PM PDT 24 336978710000 ps
T93 /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.2795685389 Jul 27 04:21:01 PM PDT 24 Jul 27 04:52:14 PM PDT 24 336806070000 ps
T94 /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.4206939543 Jul 27 04:22:06 PM PDT 24 Jul 27 04:49:28 PM PDT 24 336627510000 ps
T95 /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.1971941799 Jul 27 04:22:05 PM PDT 24 Jul 27 04:51:54 PM PDT 24 336856850000 ps
T96 /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.1854021498 Jul 27 04:20:05 PM PDT 24 Jul 27 05:00:58 PM PDT 24 336729530000 ps
T97 /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.2071894311 Jul 27 04:22:31 PM PDT 24 Jul 27 04:49:58 PM PDT 24 336344310000 ps
T98 /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.1852847161 Jul 27 04:20:38 PM PDT 24 Jul 27 04:52:26 PM PDT 24 336862870000 ps
T99 /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1467235059 Jul 27 04:22:33 PM PDT 24 Jul 27 04:52:57 PM PDT 24 336780010000 ps
T100 /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.4159510386 Jul 27 04:18:26 PM PDT 24 Jul 27 04:54:43 PM PDT 24 336280310000 ps
T101 /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.3800834829 Jul 27 04:18:41 PM PDT 24 Jul 27 04:51:21 PM PDT 24 337094850000 ps
T102 /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.2646501576 Jul 27 04:22:20 PM PDT 24 Jul 27 04:49:47 PM PDT 24 336395690000 ps
T103 /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3624092854 Jul 27 04:19:00 PM PDT 24 Jul 27 04:48:54 PM PDT 24 336420230000 ps
T104 /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.2093744626 Jul 27 04:22:17 PM PDT 24 Jul 27 04:52:16 PM PDT 24 337039370000 ps
T105 /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.790448714 Jul 27 04:18:28 PM PDT 24 Jul 27 04:54:27 PM PDT 24 336331810000 ps
T106 /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.1121391866 Jul 27 04:22:21 PM PDT 24 Jul 27 04:49:27 PM PDT 24 336686050000 ps
T107 /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.2207979238 Jul 27 04:18:25 PM PDT 24 Jul 27 04:51:29 PM PDT 24 336908790000 ps
T108 /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.2659887468 Jul 27 04:22:16 PM PDT 24 Jul 27 04:50:08 PM PDT 24 336580610000 ps
T109 /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.2755456362 Jul 27 04:18:26 PM PDT 24 Jul 27 04:54:44 PM PDT 24 336405770000 ps
T110 /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.1154148799 Jul 27 04:20:53 PM PDT 24 Jul 27 04:50:52 PM PDT 24 337059370000 ps
T111 /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.128109599 Jul 27 04:20:12 PM PDT 24 Jul 27 04:20:19 PM PDT 24 1385810000 ps
T112 /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.574146337 Jul 27 04:22:40 PM PDT 24 Jul 27 04:22:48 PM PDT 24 1483210000 ps
T113 /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.4280961112 Jul 27 04:22:38 PM PDT 24 Jul 27 04:22:47 PM PDT 24 1389650000 ps
T114 /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.604418102 Jul 27 04:18:41 PM PDT 24 Jul 27 04:18:51 PM PDT 24 1434190000 ps
T115 /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.3933943273 Jul 27 04:22:21 PM PDT 24 Jul 27 04:22:30 PM PDT 24 1290250000 ps
T116 /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.3751923823 Jul 27 04:19:07 PM PDT 24 Jul 27 04:19:18 PM PDT 24 1518330000 ps
T117 /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.679629135 Jul 27 04:22:25 PM PDT 24 Jul 27 04:22:33 PM PDT 24 1421010000 ps
T118 /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.4007133937 Jul 27 04:20:46 PM PDT 24 Jul 27 04:20:58 PM PDT 24 1537410000 ps
T119 /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1643406220 Jul 27 04:22:23 PM PDT 24 Jul 27 04:22:31 PM PDT 24 1459770000 ps
T120 /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.3954311046 Jul 27 04:17:40 PM PDT 24 Jul 27 04:17:50 PM PDT 24 1421290000 ps
T121 /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.544789277 Jul 27 04:17:45 PM PDT 24 Jul 27 04:17:54 PM PDT 24 1345510000 ps
T122 /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.1512339060 Jul 27 04:18:40 PM PDT 24 Jul 27 04:18:50 PM PDT 24 1365630000 ps
T123 /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.2484813856 Jul 27 04:18:41 PM PDT 24 Jul 27 04:18:51 PM PDT 24 1455330000 ps
T124 /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.2138198035 Jul 27 04:22:36 PM PDT 24 Jul 27 04:22:44 PM PDT 24 1345430000 ps
T125 /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.2342329167 Jul 27 04:17:47 PM PDT 24 Jul 27 04:17:55 PM PDT 24 1561450000 ps
T126 /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.2318337635 Jul 27 04:23:42 PM PDT 24 Jul 27 04:23:51 PM PDT 24 1534210000 ps
T127 /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.2297815005 Jul 27 04:18:41 PM PDT 24 Jul 27 04:18:51 PM PDT 24 1466010000 ps
T128 /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.3839847987 Jul 27 04:18:30 PM PDT 24 Jul 27 04:18:39 PM PDT 24 1465910000 ps
T129 /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3774116507 Jul 27 04:17:41 PM PDT 24 Jul 27 04:17:51 PM PDT 24 1499830000 ps
T130 /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.26558511 Jul 27 04:22:39 PM PDT 24 Jul 27 04:22:47 PM PDT 24 1424010000 ps
T131 /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.3131293311 Jul 27 04:23:08 PM PDT 24 Jul 27 04:23:17 PM PDT 24 1483830000 ps
T132 /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.2377778362 Jul 27 04:22:10 PM PDT 24 Jul 27 04:22:18 PM PDT 24 1499250000 ps
T133 /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.180918881 Jul 27 04:23:07 PM PDT 24 Jul 27 04:23:16 PM PDT 24 1409070000 ps
T134 /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.2594550279 Jul 27 04:22:08 PM PDT 24 Jul 27 04:22:17 PM PDT 24 1421070000 ps
T135 /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.3355829794 Jul 27 04:22:37 PM PDT 24 Jul 27 04:22:45 PM PDT 24 1342930000 ps
T136 /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.4178135842 Jul 27 04:20:33 PM PDT 24 Jul 27 04:20:44 PM PDT 24 1629750000 ps
T137 /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.2320664772 Jul 27 04:22:38 PM PDT 24 Jul 27 04:22:46 PM PDT 24 1551050000 ps
T138 /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.3106701447 Jul 27 04:17:40 PM PDT 24 Jul 27 04:17:49 PM PDT 24 1279750000 ps
T139 /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.3417200734 Jul 27 04:23:21 PM PDT 24 Jul 27 04:23:28 PM PDT 24 1254310000 ps
T140 /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.2487174086 Jul 27 04:20:19 PM PDT 24 Jul 27 04:20:27 PM PDT 24 1163730000 ps
T141 /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.4290698092 Jul 27 04:19:47 PM PDT 24 Jul 27 04:19:58 PM PDT 24 1545410000 ps
T142 /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.137636459 Jul 27 04:22:28 PM PDT 24 Jul 27 04:22:37 PM PDT 24 1428970000 ps
T143 /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.194738191 Jul 27 04:18:53 PM PDT 24 Jul 27 04:19:02 PM PDT 24 1421310000 ps
T144 /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.3720355884 Jul 27 04:22:31 PM PDT 24 Jul 27 04:22:40 PM PDT 24 1214770000 ps
T145 /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.1947995490 Jul 27 04:18:49 PM PDT 24 Jul 27 04:18:58 PM PDT 24 1544470000 ps
T146 /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.409346939 Jul 27 04:22:06 PM PDT 24 Jul 27 04:22:14 PM PDT 24 1429950000 ps
T147 /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.710233745 Jul 27 04:23:42 PM PDT 24 Jul 27 04:23:49 PM PDT 24 1299830000 ps
T148 /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.1827615775 Jul 27 04:19:45 PM PDT 24 Jul 27 04:19:56 PM PDT 24 1558150000 ps
T149 /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.4061142507 Jul 27 04:22:49 PM PDT 24 Jul 27 04:22:58 PM PDT 24 1385090000 ps
T150 /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.3414605931 Jul 27 04:19:43 PM PDT 24 Jul 27 04:19:52 PM PDT 24 1444210000 ps
T151 /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.3008404379 Jul 27 04:17:41 PM PDT 24 Jul 27 04:17:51 PM PDT 24 1487110000 ps
T152 /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.3416388498 Jul 27 04:23:17 PM PDT 24 Jul 27 04:23:25 PM PDT 24 1334270000 ps
T153 /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.3430670447 Jul 27 04:23:40 PM PDT 24 Jul 27 04:23:48 PM PDT 24 1464390000 ps
T154 /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.526859182 Jul 27 04:20:15 PM PDT 24 Jul 27 04:20:24 PM PDT 24 1465230000 ps
T155 /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.111444707 Jul 27 04:18:40 PM PDT 24 Jul 27 04:18:52 PM PDT 24 1607650000 ps
T156 /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.2771744248 Jul 27 04:23:03 PM PDT 24 Jul 27 04:23:15 PM PDT 24 1540970000 ps
T157 /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.3355767529 Jul 27 04:18:40 PM PDT 24 Jul 27 04:18:51 PM PDT 24 1536230000 ps
T158 /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.1547809867 Jul 27 04:23:21 PM PDT 24 Jul 27 04:23:28 PM PDT 24 1331550000 ps
T159 /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.1014029268 Jul 27 04:18:49 PM PDT 24 Jul 27 04:18:58 PM PDT 24 1307770000 ps
T160 /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.2165510406 Jul 27 04:23:03 PM PDT 24 Jul 27 04:23:12 PM PDT 24 1231750000 ps
T21 /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.505353317 Jul 27 04:19:28 PM PDT 24 Jul 27 04:52:41 PM PDT 24 336706850000 ps
T22 /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.3594252439 Jul 27 04:22:15 PM PDT 24 Jul 27 04:58:44 PM PDT 24 337066690000 ps
T23 /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.377144050 Jul 27 04:22:09 PM PDT 24 Jul 27 04:48:30 PM PDT 24 336888570000 ps
T24 /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.3847220966 Jul 27 04:23:15 PM PDT 24 Jul 27 04:48:21 PM PDT 24 336829050000 ps
T25 /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.2305194120 Jul 27 04:22:08 PM PDT 24 Jul 27 04:48:02 PM PDT 24 336713790000 ps
T26 /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.1437873075 Jul 27 04:23:01 PM PDT 24 Jul 27 04:52:35 PM PDT 24 336737350000 ps
T27 /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.3596523337 Jul 27 04:22:21 PM PDT 24 Jul 27 04:58:16 PM PDT 24 336664010000 ps
T28 /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.1291143158 Jul 27 04:22:18 PM PDT 24 Jul 27 04:50:52 PM PDT 24 336425810000 ps
T29 /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.88611630 Jul 27 04:20:34 PM PDT 24 Jul 27 04:54:36 PM PDT 24 336909150000 ps
T30 /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.789042402 Jul 27 04:21:28 PM PDT 24 Jul 27 05:01:23 PM PDT 24 336493510000 ps
T161 /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.3307862455 Jul 27 04:22:30 PM PDT 24 Jul 27 04:49:51 PM PDT 24 336517070000 ps
T162 /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.396033172 Jul 27 04:22:33 PM PDT 24 Jul 27 04:46:42 PM PDT 24 336606650000 ps
T163 /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.3515380104 Jul 27 04:17:48 PM PDT 24 Jul 27 04:57:58 PM PDT 24 336794790000 ps
T164 /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.360869831 Jul 27 04:17:36 PM PDT 24 Jul 27 04:57:51 PM PDT 24 336642430000 ps
T165 /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.427024483 Jul 27 04:22:25 PM PDT 24 Jul 27 04:50:14 PM PDT 24 336800070000 ps
T166 /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.3711292625 Jul 27 04:22:06 PM PDT 24 Jul 27 04:50:29 PM PDT 24 336687410000 ps
T167 /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.677445108 Jul 27 04:23:07 PM PDT 24 Jul 27 04:48:20 PM PDT 24 336832370000 ps
T168 /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.101323200 Jul 27 04:18:11 PM PDT 24 Jul 27 04:49:18 PM PDT 24 336512810000 ps
T169 /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.628883918 Jul 27 04:18:13 PM PDT 24 Jul 27 04:52:35 PM PDT 24 336473310000 ps
T170 /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.3896739887 Jul 27 04:22:18 PM PDT 24 Jul 27 04:48:53 PM PDT 24 337113870000 ps
T171 /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.120587945 Jul 27 04:22:20 PM PDT 24 Jul 27 04:52:11 PM PDT 24 336529590000 ps
T172 /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.1719315060 Jul 27 04:22:15 PM PDT 24 Jul 27 04:58:42 PM PDT 24 336907170000 ps
T173 /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.2126741101 Jul 27 04:22:26 PM PDT 24 Jul 27 04:51:16 PM PDT 24 336594270000 ps
T174 /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.4014361874 Jul 27 04:23:15 PM PDT 24 Jul 27 04:49:43 PM PDT 24 336759550000 ps
T175 /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.3556966262 Jul 27 04:18:10 PM PDT 24 Jul 27 04:48:48 PM PDT 24 336577110000 ps
T176 /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.1204046645 Jul 27 04:18:40 PM PDT 24 Jul 27 04:51:55 PM PDT 24 337047430000 ps
T177 /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.1155016678 Jul 27 04:22:32 PM PDT 24 Jul 27 04:49:51 PM PDT 24 337046370000 ps
T178 /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.3035249439 Jul 27 04:22:27 PM PDT 24 Jul 27 04:51:06 PM PDT 24 336453250000 ps
T179 /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.456856935 Jul 27 04:19:44 PM PDT 24 Jul 27 04:52:50 PM PDT 24 336999090000 ps
T180 /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.3680062432 Jul 27 04:18:41 PM PDT 24 Jul 27 04:52:11 PM PDT 24 336657110000 ps
T181 /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.3291780094 Jul 27 04:18:10 PM PDT 24 Jul 27 04:50:37 PM PDT 24 336440010000 ps
T182 /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.1269033028 Jul 27 04:20:42 PM PDT 24 Jul 27 04:50:25 PM PDT 24 336483590000 ps
T183 /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.3025600780 Jul 27 04:18:40 PM PDT 24 Jul 27 04:48:21 PM PDT 24 336782550000 ps
T184 /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.2865198607 Jul 27 04:22:30 PM PDT 24 Jul 27 04:49:57 PM PDT 24 336662570000 ps
T185 /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.3118692350 Jul 27 04:22:41 PM PDT 24 Jul 27 04:47:57 PM PDT 24 336963430000 ps
T186 /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.1128974284 Jul 27 04:22:51 PM PDT 24 Jul 27 04:48:32 PM PDT 24 337027210000 ps
T187 /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.494836187 Jul 27 04:22:06 PM PDT 24 Jul 27 04:56:52 PM PDT 24 337135870000 ps
T188 /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.2572721404 Jul 27 04:20:33 PM PDT 24 Jul 27 04:50:23 PM PDT 24 337145930000 ps
T189 /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.1578977400 Jul 27 04:22:01 PM PDT 24 Jul 27 04:55:46 PM PDT 24 336746430000 ps
T190 /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.3487269648 Jul 27 04:22:19 PM PDT 24 Jul 27 04:53:38 PM PDT 24 336713910000 ps
T191 /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.869797834 Jul 27 04:21:14 PM PDT 24 Jul 27 04:56:47 PM PDT 24 336452450000 ps
T192 /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.38856742 Jul 27 04:22:06 PM PDT 24 Jul 27 04:47:45 PM PDT 24 336405810000 ps
T193 /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.4101286464 Jul 27 04:20:50 PM PDT 24 Jul 27 05:01:34 PM PDT 24 337063690000 ps
T194 /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.1348395884 Jul 27 04:22:01 PM PDT 24 Jul 27 04:56:09 PM PDT 24 336832830000 ps
T195 /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.2046412386 Jul 27 04:19:33 PM PDT 24 Jul 27 04:52:07 PM PDT 24 337101730000 ps
T196 /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.3504682628 Jul 27 04:22:26 PM PDT 24 Jul 27 04:46:16 PM PDT 24 337100670000 ps
T197 /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.3002577234 Jul 27 04:20:36 PM PDT 24 Jul 27 04:48:00 PM PDT 24 337059750000 ps
T198 /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.712574570 Jul 27 04:22:15 PM PDT 24 Jul 27 04:58:32 PM PDT 24 336330470000 ps
T199 /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.1709541764 Jul 27 04:18:40 PM PDT 24 Jul 27 04:52:04 PM PDT 24 336922070000 ps
T200 /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.914748354 Jul 27 04:22:01 PM PDT 24 Jul 27 04:55:50 PM PDT 24 336419250000 ps

Test location /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.1572081693
Short name T7
Test name
Test status
Simulation time 1522610000 ps
CPU time 5.36 seconds
Started Jul 27 04:18:27 PM PDT 24
Finished Jul 27 04:18:39 PM PDT 24
Peak memory 164676 kb
Host smart-c320abff-54fa-4d47-8e7f-c842b0b4a959
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1572081693 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.1572081693
Directory /workspace/12.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.2963074047
Short name T4
Test name
Test status
Simulation time 336749630000 ps
CPU time 884.81 seconds
Started Jul 27 04:22:22 PM PDT 24
Finished Jul 27 04:58:17 PM PDT 24
Peak memory 160292 kb
Host smart-90f9538d-4f74-481a-ba8f-0f9f1546fccd
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2963074047 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.2963074047
Directory /workspace/10.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.3596523337
Short name T27
Test name
Test status
Simulation time 336664010000 ps
CPU time 881.48 seconds
Started Jul 27 04:22:21 PM PDT 24
Finished Jul 27 04:58:16 PM PDT 24
Peak memory 160296 kb
Host smart-c5b34978-7a18-4abc-a3da-35fc8f420895
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3596523337 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.3596523337
Directory /workspace/15.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.2734257968
Short name T90
Test name
Test status
Simulation time 336367730000 ps
CPU time 768.31 seconds
Started Jul 27 04:22:22 PM PDT 24
Finished Jul 27 04:54:42 PM PDT 24
Peak memory 160344 kb
Host smart-ff536528-86a1-4051-81c7-0c548419ffd8
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2734257968 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.2734257968
Directory /workspace/0.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.503653736
Short name T81
Test name
Test status
Simulation time 336736450000 ps
CPU time 768.38 seconds
Started Jul 27 04:22:21 PM PDT 24
Finished Jul 27 04:54:42 PM PDT 24
Peak memory 160116 kb
Host smart-ce099c1c-35fe-412c-bff1-0a79c4e15f07
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=503653736 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.503653736
Directory /workspace/1.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.4194828709
Short name T77
Test name
Test status
Simulation time 337105910000 ps
CPU time 698.61 seconds
Started Jul 27 04:20:34 PM PDT 24
Finished Jul 27 04:49:53 PM PDT 24
Peak memory 160608 kb
Host smart-f1f44952-5116-4c37-b17e-98aa7d7f71fa
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4194828709 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.4194828709
Directory /workspace/11.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.1852847161
Short name T98
Test name
Test status
Simulation time 336862870000 ps
CPU time 772.43 seconds
Started Jul 27 04:20:38 PM PDT 24
Finished Jul 27 04:52:26 PM PDT 24
Peak memory 160696 kb
Host smart-591f7eb4-ebad-4ce0-b412-c2f74b933683
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1852847161 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.1852847161
Directory /workspace/12.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.759110354
Short name T87
Test name
Test status
Simulation time 336588390000 ps
CPU time 831.12 seconds
Started Jul 27 04:22:06 PM PDT 24
Finished Jul 27 04:56:49 PM PDT 24
Peak memory 158996 kb
Host smart-df368ca7-fee5-41f0-92a4-ab224f475452
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=759110354 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.759110354
Directory /workspace/13.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.2795685389
Short name T93
Test name
Test status
Simulation time 336806070000 ps
CPU time 768.9 seconds
Started Jul 27 04:21:01 PM PDT 24
Finished Jul 27 04:52:14 PM PDT 24
Peak memory 160692 kb
Host smart-4c967fd6-8cde-4a4f-bab0-162933b5a284
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2795685389 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.2795685389
Directory /workspace/14.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.2947510711
Short name T80
Test name
Test status
Simulation time 337047870000 ps
CPU time 772.75 seconds
Started Jul 27 04:19:16 PM PDT 24
Finished Jul 27 04:50:54 PM PDT 24
Peak memory 160696 kb
Host smart-9318d399-9311-460c-804a-062530f4650e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2947510711 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.2947510711
Directory /workspace/15.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.3800834829
Short name T101
Test name
Test status
Simulation time 337094850000 ps
CPU time 806.26 seconds
Started Jul 27 04:18:41 PM PDT 24
Finished Jul 27 04:51:21 PM PDT 24
Peak memory 160616 kb
Host smart-d0dfcfd8-9f24-4807-b141-2bd3fbaf2f52
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3800834829 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.3800834829
Directory /workspace/16.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.1827083609
Short name T71
Test name
Test status
Simulation time 336387670000 ps
CPU time 834.8 seconds
Started Jul 27 04:22:07 PM PDT 24
Finished Jul 27 04:56:26 PM PDT 24
Peak memory 159536 kb
Host smart-e29ab2e6-86e0-4ef9-b91b-0b4db6b52bce
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1827083609 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.1827083609
Directory /workspace/17.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.2156208420
Short name T5
Test name
Test status
Simulation time 336387510000 ps
CPU time 657.33 seconds
Started Jul 27 04:22:20 PM PDT 24
Finished Jul 27 04:49:38 PM PDT 24
Peak memory 160156 kb
Host smart-40aabfa7-5980-468e-8c44-5567374fa985
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2156208420 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.2156208420
Directory /workspace/18.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.3381813670
Short name T19
Test name
Test status
Simulation time 337076930000 ps
CPU time 867.13 seconds
Started Jul 27 04:20:34 PM PDT 24
Finished Jul 27 04:55:53 PM PDT 24
Peak memory 160692 kb
Host smart-1268cfa5-1c24-4a01-9b63-96832206a3a4
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3381813670 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.3381813670
Directory /workspace/19.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.18543743
Short name T18
Test name
Test status
Simulation time 336412230000 ps
CPU time 777.12 seconds
Started Jul 27 04:22:21 PM PDT 24
Finished Jul 27 04:54:54 PM PDT 24
Peak memory 160180 kb
Host smart-ae7d7f43-67c2-4386-aeec-ec39bdcb8aa2
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=18543743 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.18543743
Directory /workspace/2.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.2646501576
Short name T102
Test name
Test status
Simulation time 336395690000 ps
CPU time 666.41 seconds
Started Jul 27 04:22:20 PM PDT 24
Finished Jul 27 04:49:47 PM PDT 24
Peak memory 159568 kb
Host smart-7638533d-920e-45cd-979a-cafb7361f56d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2646501576 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.2646501576
Directory /workspace/20.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.2093744626
Short name T104
Test name
Test status
Simulation time 337039370000 ps
CPU time 726.84 seconds
Started Jul 27 04:22:17 PM PDT 24
Finished Jul 27 04:52:16 PM PDT 24
Peak memory 160512 kb
Host smart-fb12eddd-bec7-47f2-980f-364991775f42
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2093744626 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.2093744626
Directory /workspace/21.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.1971941799
Short name T95
Test name
Test status
Simulation time 336856850000 ps
CPU time 726.14 seconds
Started Jul 27 04:22:05 PM PDT 24
Finished Jul 27 04:51:54 PM PDT 24
Peak memory 160260 kb
Host smart-d6751925-c8b3-4626-8fe2-e22bf35720f1
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1971941799 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.1971941799
Directory /workspace/22.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.2659887468
Short name T108
Test name
Test status
Simulation time 336580610000 ps
CPU time 676.85 seconds
Started Jul 27 04:22:16 PM PDT 24
Finished Jul 27 04:50:08 PM PDT 24
Peak memory 160648 kb
Host smart-4d7ff331-121e-4259-a091-dcd87c6048bd
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2659887468 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.2659887468
Directory /workspace/23.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.3726169514
Short name T76
Test name
Test status
Simulation time 336430030000 ps
CPU time 611.38 seconds
Started Jul 27 04:22:26 PM PDT 24
Finished Jul 27 04:47:46 PM PDT 24
Peak memory 160440 kb
Host smart-39643094-56de-4334-b1b0-61fd24f87e17
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3726169514 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.3726169514
Directory /workspace/24.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.378097787
Short name T14
Test name
Test status
Simulation time 336509070000 ps
CPU time 879.02 seconds
Started Jul 27 04:18:57 PM PDT 24
Finished Jul 27 04:54:57 PM PDT 24
Peak memory 160876 kb
Host smart-02258033-38ba-433c-8cdf-870bdb61ebcf
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=378097787 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.378097787
Directory /workspace/25.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1467235059
Short name T99
Test name
Test status
Simulation time 336780010000 ps
CPU time 742.03 seconds
Started Jul 27 04:22:33 PM PDT 24
Finished Jul 27 04:52:57 PM PDT 24
Peak memory 160616 kb
Host smart-3bc6e76f-a34a-4eb3-989a-e2a1e40a56bc
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1467235059 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.1467235059
Directory /workspace/26.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.3084034585
Short name T85
Test name
Test status
Simulation time 337170270000 ps
CPU time 628.69 seconds
Started Jul 27 04:22:27 PM PDT 24
Finished Jul 27 04:48:07 PM PDT 24
Peak memory 160440 kb
Host smart-4cb936e1-fa8f-4144-9dfd-d9f1eac0db75
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3084034585 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.3084034585
Directory /workspace/27.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.1854021498
Short name T96
Test name
Test status
Simulation time 336729530000 ps
CPU time 991.09 seconds
Started Jul 27 04:20:05 PM PDT 24
Finished Jul 27 05:00:58 PM PDT 24
Peak memory 160624 kb
Host smart-922b2c79-f782-4585-a557-1293e2df530d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1854021498 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.1854021498
Directory /workspace/28.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.3352356628
Short name T79
Test name
Test status
Simulation time 336638950000 ps
CPU time 768.6 seconds
Started Jul 27 04:22:21 PM PDT 24
Finished Jul 27 04:54:33 PM PDT 24
Peak memory 159768 kb
Host smart-d2a6128b-22ca-4ad4-a78e-3d1250ce1601
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3352356628 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.3352356628
Directory /workspace/29.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.2207979238
Short name T107
Test name
Test status
Simulation time 336908790000 ps
CPU time 813.65 seconds
Started Jul 27 04:18:25 PM PDT 24
Finished Jul 27 04:51:29 PM PDT 24
Peak memory 160676 kb
Host smart-158128be-ec0d-4faf-aeff-3b356cf72d41
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2207979238 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.2207979238
Directory /workspace/3.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3624092854
Short name T103
Test name
Test status
Simulation time 336420230000 ps
CPU time 717.37 seconds
Started Jul 27 04:19:00 PM PDT 24
Finished Jul 27 04:48:54 PM PDT 24
Peak memory 160860 kb
Host smart-38b4d2e7-6f62-4433-b4cc-534412063ac4
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3624092854 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.3624092854
Directory /workspace/30.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.248322735
Short name T15
Test name
Test status
Simulation time 336861670000 ps
CPU time 801.29 seconds
Started Jul 27 04:22:18 PM PDT 24
Finished Jul 27 04:55:06 PM PDT 24
Peak memory 160524 kb
Host smart-1f6f1334-f43b-4d07-a73e-8c49de2c4962
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=248322735 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.248322735
Directory /workspace/31.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.1121391866
Short name T106
Test name
Test status
Simulation time 336686050000 ps
CPU time 658.48 seconds
Started Jul 27 04:22:21 PM PDT 24
Finished Jul 27 04:49:27 PM PDT 24
Peak memory 160336 kb
Host smart-71de1b83-065e-4f6c-a774-aa8a70944728
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1121391866 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.1121391866
Directory /workspace/32.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.3869675260
Short name T73
Test name
Test status
Simulation time 336338010000 ps
CPU time 641.08 seconds
Started Jul 27 04:22:26 PM PDT 24
Finished Jul 27 04:48:28 PM PDT 24
Peak memory 160424 kb
Host smart-37a1d01d-8ab1-4c9c-9061-fde5c3e22c6a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3869675260 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.3869675260
Directory /workspace/33.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.4159510386
Short name T100
Test name
Test status
Simulation time 336280310000 ps
CPU time 889.85 seconds
Started Jul 27 04:18:26 PM PDT 24
Finished Jul 27 04:54:43 PM PDT 24
Peak memory 160900 kb
Host smart-f3795e4d-5166-46c6-b39d-e3f66c0d2983
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4159510386 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.4159510386
Directory /workspace/34.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.343333275
Short name T74
Test name
Test status
Simulation time 336486170000 ps
CPU time 775.37 seconds
Started Jul 27 04:22:20 PM PDT 24
Finished Jul 27 04:54:43 PM PDT 24
Peak memory 159524 kb
Host smart-cef6d5c3-e4e2-4474-8d5e-d502bf4c5d91
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=343333275 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.343333275
Directory /workspace/35.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.2755456362
Short name T109
Test name
Test status
Simulation time 336405770000 ps
CPU time 888.08 seconds
Started Jul 27 04:18:26 PM PDT 24
Finished Jul 27 04:54:44 PM PDT 24
Peak memory 160900 kb
Host smart-56856509-9017-4f5e-954c-c33ccd75f5a5
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2755456362 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.2755456362
Directory /workspace/36.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.2468858737
Short name T84
Test name
Test status
Simulation time 336572770000 ps
CPU time 989.79 seconds
Started Jul 27 04:19:15 PM PDT 24
Finished Jul 27 05:00:13 PM PDT 24
Peak memory 160624 kb
Host smart-885275a2-c052-4dae-9eb5-3a60b8c0737b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2468858737 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.2468858737
Directory /workspace/37.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.2071894311
Short name T97
Test name
Test status
Simulation time 336344310000 ps
CPU time 662.37 seconds
Started Jul 27 04:22:31 PM PDT 24
Finished Jul 27 04:49:58 PM PDT 24
Peak memory 160232 kb
Host smart-f72af574-25cb-4a8e-a2b0-94fd422a6b6f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2071894311 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.2071894311
Directory /workspace/38.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.3653422677
Short name T78
Test name
Test status
Simulation time 336483290000 ps
CPU time 660.45 seconds
Started Jul 27 04:22:33 PM PDT 24
Finished Jul 27 04:50:06 PM PDT 24
Peak memory 160444 kb
Host smart-d225fba2-7c80-4690-9cfc-6c38e74d3434
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3653422677 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.3653422677
Directory /workspace/39.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.4125761512
Short name T72
Test name
Test status
Simulation time 336347290000 ps
CPU time 722.51 seconds
Started Jul 27 04:18:48 PM PDT 24
Finished Jul 27 04:48:48 PM PDT 24
Peak memory 160852 kb
Host smart-0cdbf7c1-4bdc-495b-953a-3e642fa67b5e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4125761512 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.4125761512
Directory /workspace/4.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.2788731497
Short name T20
Test name
Test status
Simulation time 336870990000 ps
CPU time 712.44 seconds
Started Jul 27 04:22:25 PM PDT 24
Finished Jul 27 04:51:45 PM PDT 24
Peak memory 160108 kb
Host smart-af9a25d2-1112-46d5-a6cc-47ac5beb8fbc
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2788731497 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.2788731497
Directory /workspace/40.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.1154148799
Short name T110
Test name
Test status
Simulation time 337059370000 ps
CPU time 733.83 seconds
Started Jul 27 04:20:53 PM PDT 24
Finished Jul 27 04:50:52 PM PDT 24
Peak memory 160532 kb
Host smart-bebcf720-422f-4d73-aa16-4579701a3481
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1154148799 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.1154148799
Directory /workspace/41.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.847035955
Short name T92
Test name
Test status
Simulation time 336978710000 ps
CPU time 747.08 seconds
Started Jul 27 04:23:12 PM PDT 24
Finished Jul 27 04:54:04 PM PDT 24
Peak memory 160544 kb
Host smart-977a4e89-23ba-4dac-b6d9-b01966771966
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=847035955 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.847035955
Directory /workspace/42.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.54886889
Short name T16
Test name
Test status
Simulation time 336727630000 ps
CPU time 883.05 seconds
Started Jul 27 04:18:28 PM PDT 24
Finished Jul 27 04:54:24 PM PDT 24
Peak memory 160684 kb
Host smart-1bd4e4c6-7c97-4e16-9e0b-4fbf52da56d4
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=54886889 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.54886889
Directory /workspace/43.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.4206939543
Short name T94
Test name
Test status
Simulation time 336627510000 ps
CPU time 670 seconds
Started Jul 27 04:22:06 PM PDT 24
Finished Jul 27 04:49:28 PM PDT 24
Peak memory 160320 kb
Host smart-f27d0890-2608-4fb3-a40e-9863069f64b7
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4206939543 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.4206939543
Directory /workspace/44.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.130493209
Short name T89
Test name
Test status
Simulation time 336457410000 ps
CPU time 691.5 seconds
Started Jul 27 04:22:06 PM PDT 24
Finished Jul 27 04:50:28 PM PDT 24
Peak memory 159848 kb
Host smart-b4229567-3290-4529-bb31-ee253c5d1e29
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=130493209 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.130493209
Directory /workspace/45.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.3680191579
Short name T82
Test name
Test status
Simulation time 336889670000 ps
CPU time 694.58 seconds
Started Jul 27 04:22:27 PM PDT 24
Finished Jul 27 04:51:19 PM PDT 24
Peak memory 160364 kb
Host smart-27b178d6-7dcf-4919-bccf-34091e800271
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3680191579 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.3680191579
Directory /workspace/46.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.2056088418
Short name T17
Test name
Test status
Simulation time 337014690000 ps
CPU time 705.88 seconds
Started Jul 27 04:22:22 PM PDT 24
Finished Jul 27 04:51:35 PM PDT 24
Peak memory 160392 kb
Host smart-7fd47ec0-781d-417d-a5cb-3ec19f49f9d1
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2056088418 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.2056088418
Directory /workspace/47.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.607831917
Short name T91
Test name
Test status
Simulation time 336930770000 ps
CPU time 731.49 seconds
Started Jul 27 04:22:22 PM PDT 24
Finished Jul 27 04:52:15 PM PDT 24
Peak memory 160592 kb
Host smart-77d81e9c-6619-44a6-b079-2c47deb5d42d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=607831917 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.607831917
Directory /workspace/48.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.1350498310
Short name T83
Test name
Test status
Simulation time 336516190000 ps
CPU time 719.37 seconds
Started Jul 27 04:22:20 PM PDT 24
Finished Jul 27 04:51:57 PM PDT 24
Peak memory 159560 kb
Host smart-15f788be-3668-4878-b8d2-8cdb6b405631
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1350498310 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.1350498310
Directory /workspace/49.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.3706101035
Short name T86
Test name
Test status
Simulation time 336658370000 ps
CPU time 601.53 seconds
Started Jul 27 04:22:33 PM PDT 24
Finished Jul 27 04:47:20 PM PDT 24
Peak memory 160440 kb
Host smart-ec9628e3-8c74-4760-b098-a3b9cb35797d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3706101035 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.3706101035
Directory /workspace/5.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.1350174136
Short name T6
Test name
Test status
Simulation time 336488690000 ps
CPU time 661.43 seconds
Started Jul 27 04:22:31 PM PDT 24
Finished Jul 27 04:49:56 PM PDT 24
Peak memory 160164 kb
Host smart-1dbee4be-f902-4f30-adb1-59790e35890b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1350174136 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.1350174136
Directory /workspace/6.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.3193650865
Short name T75
Test name
Test status
Simulation time 337069470000 ps
CPU time 582.34 seconds
Started Jul 27 04:22:23 PM PDT 24
Finished Jul 27 04:46:27 PM PDT 24
Peak memory 160328 kb
Host smart-c95db01b-8543-4b45-8cbe-e14d6561f527
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3193650865 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.3193650865
Directory /workspace/7.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.790448714
Short name T105
Test name
Test status
Simulation time 336331810000 ps
CPU time 881.9 seconds
Started Jul 27 04:18:28 PM PDT 24
Finished Jul 27 04:54:27 PM PDT 24
Peak memory 160684 kb
Host smart-9adde153-cf76-4b32-83ef-d0954bf5c440
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=790448714 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.790448714
Directory /workspace/8.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.3492720748
Short name T88
Test name
Test status
Simulation time 336970250000 ps
CPU time 815.82 seconds
Started Jul 27 04:22:07 PM PDT 24
Finished Jul 27 04:55:58 PM PDT 24
Peak memory 160076 kb
Host smart-9de25854-6d04-4c2c-ae43-aedb55b3f101
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3492720748 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.3492720748
Directory /workspace/9.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.1348395884
Short name T194
Test name
Test status
Simulation time 336832830000 ps
CPU time 814.39 seconds
Started Jul 27 04:22:01 PM PDT 24
Finished Jul 27 04:56:09 PM PDT 24
Peak memory 158732 kb
Host smart-4f6a46dd-af03-4321-9746-7c11b7a07978
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1348395884 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.1348395884
Directory /workspace/0.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.1719315060
Short name T172
Test name
Test status
Simulation time 336907170000 ps
CPU time 895 seconds
Started Jul 27 04:22:15 PM PDT 24
Finished Jul 27 04:58:42 PM PDT 24
Peak memory 160484 kb
Host smart-003a65a8-7d1f-4f60-ac34-1dbc56fcf0a6
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1719315060 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.1719315060
Directory /workspace/1.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.1709541764
Short name T199
Test name
Test status
Simulation time 336922070000 ps
CPU time 801.93 seconds
Started Jul 27 04:18:40 PM PDT 24
Finished Jul 27 04:52:04 PM PDT 24
Peak memory 158584 kb
Host smart-3b7daa73-3e86-45d7-8639-eb7f6d04905a
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1709541764 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.1709541764
Directory /workspace/10.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.914748354
Short name T200
Test name
Test status
Simulation time 336419250000 ps
CPU time 812 seconds
Started Jul 27 04:22:01 PM PDT 24
Finished Jul 27 04:55:50 PM PDT 24
Peak memory 159164 kb
Host smart-63a127c5-7bc6-408e-99ef-78388b8d9ba3
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=914748354 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.914748354
Directory /workspace/11.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.3896739887
Short name T170
Test name
Test status
Simulation time 337113870000 ps
CPU time 631.65 seconds
Started Jul 27 04:22:18 PM PDT 24
Finished Jul 27 04:48:53 PM PDT 24
Peak memory 160560 kb
Host smart-f2ac83bc-bd72-4aac-a14c-516f2b3d0de8
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3896739887 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.3896739887
Directory /workspace/12.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.2046412386
Short name T195
Test name
Test status
Simulation time 337101730000 ps
CPU time 797.44 seconds
Started Jul 27 04:19:33 PM PDT 24
Finished Jul 27 04:52:07 PM PDT 24
Peak memory 160700 kb
Host smart-9d6ba43e-3661-4d18-acc3-7a7d81c5ca82
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2046412386 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.2046412386
Directory /workspace/13.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.360869831
Short name T164
Test name
Test status
Simulation time 336642430000 ps
CPU time 969.5 seconds
Started Jul 27 04:17:36 PM PDT 24
Finished Jul 27 04:57:51 PM PDT 24
Peak memory 159612 kb
Host smart-c81464d7-3c72-4ae3-82de-a684aa8a0d27
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=360869831 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.360869831
Directory /workspace/14.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.2572721404
Short name T188
Test name
Test status
Simulation time 337145930000 ps
CPU time 709.71 seconds
Started Jul 27 04:20:33 PM PDT 24
Finished Jul 27 04:50:23 PM PDT 24
Peak memory 160612 kb
Host smart-358e226b-1a80-45e9-b59c-f27abcf77e95
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2572721404 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.2572721404
Directory /workspace/16.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.3307862455
Short name T161
Test name
Test status
Simulation time 336517070000 ps
CPU time 657.53 seconds
Started Jul 27 04:22:30 PM PDT 24
Finished Jul 27 04:49:51 PM PDT 24
Peak memory 160464 kb
Host smart-80f5ac15-6c35-4c45-a4e5-83ff0e6017b4
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3307862455 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.3307862455
Directory /workspace/17.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.4014361874
Short name T174
Test name
Test status
Simulation time 336759550000 ps
CPU time 643.48 seconds
Started Jul 27 04:23:15 PM PDT 24
Finished Jul 27 04:49:43 PM PDT 24
Peak memory 160468 kb
Host smart-82bfa3fb-ed92-4a24-8509-d314c5fb2e7b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4014361874 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.4014361874
Directory /workspace/18.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.3002577234
Short name T197
Test name
Test status
Simulation time 337059750000 ps
CPU time 667.08 seconds
Started Jul 27 04:20:36 PM PDT 24
Finished Jul 27 04:48:00 PM PDT 24
Peak memory 160620 kb
Host smart-8be48fba-547e-4231-8168-6e1f6f85d254
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3002577234 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.3002577234
Directory /workspace/19.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.1204046645
Short name T176
Test name
Test status
Simulation time 337047430000 ps
CPU time 798.62 seconds
Started Jul 27 04:18:40 PM PDT 24
Finished Jul 27 04:51:55 PM PDT 24
Peak memory 158444 kb
Host smart-85d993dc-a727-4e65-91d9-318249453a43
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1204046645 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.1204046645
Directory /workspace/2.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.712574570
Short name T198
Test name
Test status
Simulation time 336330470000 ps
CPU time 893.56 seconds
Started Jul 27 04:22:15 PM PDT 24
Finished Jul 27 04:58:32 PM PDT 24
Peak memory 160612 kb
Host smart-bd479c85-803d-467d-a4c5-5cef02b70c44
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=712574570 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.712574570
Directory /workspace/20.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.1155016678
Short name T177
Test name
Test status
Simulation time 337046370000 ps
CPU time 659.62 seconds
Started Jul 27 04:22:32 PM PDT 24
Finished Jul 27 04:49:51 PM PDT 24
Peak memory 160464 kb
Host smart-956ace43-2d9e-4f26-a00e-cd1dcce5ebeb
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1155016678 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.1155016678
Directory /workspace/21.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.2865198607
Short name T184
Test name
Test status
Simulation time 336662570000 ps
CPU time 664.68 seconds
Started Jul 27 04:22:30 PM PDT 24
Finished Jul 27 04:49:57 PM PDT 24
Peak memory 160464 kb
Host smart-1e2c6887-4cad-4649-9ad2-358d6c94ce61
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2865198607 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.2865198607
Directory /workspace/22.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.494836187
Short name T187
Test name
Test status
Simulation time 337135870000 ps
CPU time 832.43 seconds
Started Jul 27 04:22:06 PM PDT 24
Finished Jul 27 04:56:52 PM PDT 24
Peak memory 159024 kb
Host smart-208ce1d2-e860-4228-9f1a-4dd45ab19789
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=494836187 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.494836187
Directory /workspace/23.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.2305194120
Short name T25
Test name
Test status
Simulation time 336713790000 ps
CPU time 625.15 seconds
Started Jul 27 04:22:08 PM PDT 24
Finished Jul 27 04:48:02 PM PDT 24
Peak memory 160352 kb
Host smart-1efd301a-eeb5-4b5e-a679-22eeaaca9fa2
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2305194120 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.2305194120
Directory /workspace/24.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.3504682628
Short name T196
Test name
Test status
Simulation time 337100670000 ps
CPU time 582.36 seconds
Started Jul 27 04:22:26 PM PDT 24
Finished Jul 27 04:46:16 PM PDT 24
Peak memory 160444 kb
Host smart-33a9f27d-d491-4ea4-a9fc-b83967372bcf
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3504682628 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.3504682628
Directory /workspace/25.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.3487269648
Short name T190
Test name
Test status
Simulation time 336713910000 ps
CPU time 761.63 seconds
Started Jul 27 04:22:19 PM PDT 24
Finished Jul 27 04:53:38 PM PDT 24
Peak memory 160616 kb
Host smart-385b486c-b232-4e78-860b-e984226ca540
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3487269648 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.3487269648
Directory /workspace/26.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.3711292625
Short name T166
Test name
Test status
Simulation time 336687410000 ps
CPU time 691.96 seconds
Started Jul 27 04:22:06 PM PDT 24
Finished Jul 27 04:50:29 PM PDT 24
Peak memory 160404 kb
Host smart-19fde443-6677-4173-8806-36662eba67ed
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3711292625 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.3711292625
Directory /workspace/27.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.1128974284
Short name T186
Test name
Test status
Simulation time 337027210000 ps
CPU time 623.53 seconds
Started Jul 27 04:22:51 PM PDT 24
Finished Jul 27 04:48:32 PM PDT 24
Peak memory 160408 kb
Host smart-b4c80fef-8d18-4a8f-bc68-6021e2134cf9
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1128974284 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.1128974284
Directory /workspace/28.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.677445108
Short name T167
Test name
Test status
Simulation time 336832370000 ps
CPU time 608.83 seconds
Started Jul 27 04:23:07 PM PDT 24
Finished Jul 27 04:48:20 PM PDT 24
Peak memory 159300 kb
Host smart-5b87e1d5-c436-4d48-b963-a6c522c183a8
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=677445108 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.677445108
Directory /workspace/29.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.3680062432
Short name T180
Test name
Test status
Simulation time 336657110000 ps
CPU time 811.23 seconds
Started Jul 27 04:18:41 PM PDT 24
Finished Jul 27 04:52:11 PM PDT 24
Peak memory 160328 kb
Host smart-829a0bd1-f151-4891-bb26-85fdaff21197
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3680062432 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.3680062432
Directory /workspace/3.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.3118692350
Short name T185
Test name
Test status
Simulation time 336963430000 ps
CPU time 622.46 seconds
Started Jul 27 04:22:41 PM PDT 24
Finished Jul 27 04:47:57 PM PDT 24
Peak memory 159848 kb
Host smart-1f578432-41d4-4f08-bf61-b80c71b0958a
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3118692350 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.3118692350
Directory /workspace/30.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.377144050
Short name T23
Test name
Test status
Simulation time 336888570000 ps
CPU time 637.61 seconds
Started Jul 27 04:22:09 PM PDT 24
Finished Jul 27 04:48:30 PM PDT 24
Peak memory 159436 kb
Host smart-cd367cc7-0c0d-4f0f-8ac6-5303e06afa73
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=377144050 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.377144050
Directory /workspace/31.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.1269033028
Short name T182
Test name
Test status
Simulation time 336483590000 ps
CPU time 708.9 seconds
Started Jul 27 04:20:42 PM PDT 24
Finished Jul 27 04:50:25 PM PDT 24
Peak memory 160864 kb
Host smart-01e36d5f-5b60-4333-bd5a-3cb18ccaf45d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1269033028 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.1269033028
Directory /workspace/32.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.1291143158
Short name T28
Test name
Test status
Simulation time 336425810000 ps
CPU time 691.04 seconds
Started Jul 27 04:22:18 PM PDT 24
Finished Jul 27 04:50:52 PM PDT 24
Peak memory 160576 kb
Host smart-f37b7282-c6e2-4ffe-9088-9e2f183aea84
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1291143158 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.1291143158
Directory /workspace/33.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.3515380104
Short name T163
Test name
Test status
Simulation time 336794790000 ps
CPU time 959.29 seconds
Started Jul 27 04:17:48 PM PDT 24
Finished Jul 27 04:57:58 PM PDT 24
Peak memory 160624 kb
Host smart-34cf1cdb-d4b7-487e-81c7-ee8fd0615c8c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3515380104 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.3515380104
Directory /workspace/34.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.3035249439
Short name T178
Test name
Test status
Simulation time 336453250000 ps
CPU time 690.38 seconds
Started Jul 27 04:22:27 PM PDT 24
Finished Jul 27 04:51:06 PM PDT 24
Peak memory 160372 kb
Host smart-652f019f-f44d-480b-bd12-688be174543f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3035249439 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.3035249439
Directory /workspace/35.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.505353317
Short name T21
Test name
Test status
Simulation time 336706850000 ps
CPU time 806.83 seconds
Started Jul 27 04:19:28 PM PDT 24
Finished Jul 27 04:52:41 PM PDT 24
Peak memory 160512 kb
Host smart-93731921-619f-4864-b8d2-76fd5d3471f1
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=505353317 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.505353317
Directory /workspace/36.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.456856935
Short name T179
Test name
Test status
Simulation time 336999090000 ps
CPU time 816.65 seconds
Started Jul 27 04:19:44 PM PDT 24
Finished Jul 27 04:52:50 PM PDT 24
Peak memory 160616 kb
Host smart-699294c6-a55b-4f79-a652-dea717fda219
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=456856935 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.456856935
Directory /workspace/37.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.427024483
Short name T165
Test name
Test status
Simulation time 336800070000 ps
CPU time 667.06 seconds
Started Jul 27 04:22:25 PM PDT 24
Finished Jul 27 04:50:14 PM PDT 24
Peak memory 160204 kb
Host smart-2ec82e35-4455-435f-b0e2-3c62dc1f27c2
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=427024483 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.427024483
Directory /workspace/38.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.38856742
Short name T192
Test name
Test status
Simulation time 336405810000 ps
CPU time 622.56 seconds
Started Jul 27 04:22:06 PM PDT 24
Finished Jul 27 04:47:45 PM PDT 24
Peak memory 160324 kb
Host smart-a70b8730-968f-47f8-bfa1-597f221d7667
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=38856742 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.38856742
Directory /workspace/39.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.3291780094
Short name T181
Test name
Test status
Simulation time 336440010000 ps
CPU time 788.8 seconds
Started Jul 27 04:18:10 PM PDT 24
Finished Jul 27 04:50:37 PM PDT 24
Peak memory 160656 kb
Host smart-74ab98e6-4c37-4b04-b415-b5828e7bdd12
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3291780094 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.3291780094
Directory /workspace/4.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.2126741101
Short name T173
Test name
Test status
Simulation time 336594270000 ps
CPU time 697.44 seconds
Started Jul 27 04:22:26 PM PDT 24
Finished Jul 27 04:51:16 PM PDT 24
Peak memory 160368 kb
Host smart-2a23f789-dea2-4bb9-b8e5-9da4b1f58187
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2126741101 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.2126741101
Directory /workspace/40.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.1437873075
Short name T26
Test name
Test status
Simulation time 336737350000 ps
CPU time 720.43 seconds
Started Jul 27 04:23:01 PM PDT 24
Finished Jul 27 04:52:35 PM PDT 24
Peak memory 159480 kb
Host smart-ca9e0e4c-bbb7-4405-86bd-4b0b0ea9e741
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1437873075 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.1437873075
Directory /workspace/41.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.396033172
Short name T162
Test name
Test status
Simulation time 336606650000 ps
CPU time 579.13 seconds
Started Jul 27 04:22:33 PM PDT 24
Finished Jul 27 04:46:42 PM PDT 24
Peak memory 160484 kb
Host smart-f4be768c-444e-4cb3-a62a-9346707f12c7
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=396033172 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.396033172
Directory /workspace/42.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.120587945
Short name T171
Test name
Test status
Simulation time 336529590000 ps
CPU time 732.42 seconds
Started Jul 27 04:22:20 PM PDT 24
Finished Jul 27 04:52:11 PM PDT 24
Peak memory 160596 kb
Host smart-e163b4e1-7264-4249-944e-f18780e0c677
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=120587945 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.120587945
Directory /workspace/43.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.4101286464
Short name T193
Test name
Test status
Simulation time 337063690000 ps
CPU time 988.7 seconds
Started Jul 27 04:20:50 PM PDT 24
Finished Jul 27 05:01:34 PM PDT 24
Peak memory 160628 kb
Host smart-a4c5253a-0d04-4e2d-b87c-bd0ee6e4c061
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4101286464 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.4101286464
Directory /workspace/44.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.789042402
Short name T30
Test name
Test status
Simulation time 336493510000 ps
CPU time 961 seconds
Started Jul 27 04:21:28 PM PDT 24
Finished Jul 27 05:01:23 PM PDT 24
Peak memory 160616 kb
Host smart-513638e4-b402-4d19-8358-45950a563063
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=789042402 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.789042402
Directory /workspace/45.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.88611630
Short name T29
Test name
Test status
Simulation time 336909150000 ps
CPU time 826.16 seconds
Started Jul 27 04:20:34 PM PDT 24
Finished Jul 27 04:54:36 PM PDT 24
Peak memory 160524 kb
Host smart-038190a2-f2ad-4d26-bc7f-c731807b61fa
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=88611630 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.88611630
Directory /workspace/46.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.101323200
Short name T168
Test name
Test status
Simulation time 336512810000 ps
CPU time 745.11 seconds
Started Jul 27 04:18:11 PM PDT 24
Finished Jul 27 04:49:18 PM PDT 24
Peak memory 160680 kb
Host smart-4b2264dd-4f77-4443-95b1-1f67fa9a7cd5
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=101323200 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.101323200
Directory /workspace/47.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.869797834
Short name T191
Test name
Test status
Simulation time 336452450000 ps
CPU time 869.88 seconds
Started Jul 27 04:21:14 PM PDT 24
Finished Jul 27 04:56:47 PM PDT 24
Peak memory 160880 kb
Host smart-067ce0a5-9929-4f22-9e28-478f94102ec0
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=869797834 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.869797834
Directory /workspace/48.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.628883918
Short name T169
Test name
Test status
Simulation time 336473310000 ps
CPU time 841.61 seconds
Started Jul 27 04:18:13 PM PDT 24
Finished Jul 27 04:52:35 PM PDT 24
Peak memory 160684 kb
Host smart-cace45cb-974d-42df-887b-a0d1e0297228
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=628883918 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.628883918
Directory /workspace/49.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.1578977400
Short name T189
Test name
Test status
Simulation time 336746430000 ps
CPU time 812.42 seconds
Started Jul 27 04:22:01 PM PDT 24
Finished Jul 27 04:55:46 PM PDT 24
Peak memory 158968 kb
Host smart-dda39109-88a5-4b88-8a38-d89152f5f3cc
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1578977400 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.1578977400
Directory /workspace/5.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.3025600780
Short name T183
Test name
Test status
Simulation time 336782550000 ps
CPU time 715.92 seconds
Started Jul 27 04:18:40 PM PDT 24
Finished Jul 27 04:48:21 PM PDT 24
Peak memory 159268 kb
Host smart-3b411192-b6e4-4456-9b29-da71a0efb264
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3025600780 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.3025600780
Directory /workspace/6.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.3556966262
Short name T175
Test name
Test status
Simulation time 336577110000 ps
CPU time 738.83 seconds
Started Jul 27 04:18:10 PM PDT 24
Finished Jul 27 04:48:48 PM PDT 24
Peak memory 160656 kb
Host smart-392ee24b-fa02-4beb-9675-e9de0b7781ed
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3556966262 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.3556966262
Directory /workspace/7.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.3594252439
Short name T22
Test name
Test status
Simulation time 337066690000 ps
CPU time 892.8 seconds
Started Jul 27 04:22:15 PM PDT 24
Finished Jul 27 04:58:44 PM PDT 24
Peak memory 160608 kb
Host smart-289d8638-ea97-4e5f-b2c2-26a6153cd268
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3594252439 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.3594252439
Directory /workspace/8.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.3847220966
Short name T24
Test name
Test status
Simulation time 336829050000 ps
CPU time 610.98 seconds
Started Jul 27 04:23:15 PM PDT 24
Finished Jul 27 04:48:21 PM PDT 24
Peak memory 160448 kb
Host smart-34cf5385-af82-4670-9a4c-3e3a5fdc3c8c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3847220966 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.3847220966
Directory /workspace/9.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.2138198035
Short name T124
Test name
Test status
Simulation time 1345430000 ps
CPU time 3.34 seconds
Started Jul 27 04:22:36 PM PDT 24
Finished Jul 27 04:22:44 PM PDT 24
Peak memory 164704 kb
Host smart-a3cf2e5c-e928-4e5d-8058-f2e091573879
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2138198035 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.2138198035
Directory /workspace/0.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.128109599
Short name T111
Test name
Test status
Simulation time 1385810000 ps
CPU time 3.41 seconds
Started Jul 27 04:20:12 PM PDT 24
Finished Jul 27 04:20:19 PM PDT 24
Peak memory 164848 kb
Host smart-fe58ff85-9027-4378-a0dc-5527025eb8de
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=128109599 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.128109599
Directory /workspace/1.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.137636459
Short name T142
Test name
Test status
Simulation time 1428970000 ps
CPU time 3.86 seconds
Started Jul 27 04:22:28 PM PDT 24
Finished Jul 27 04:22:37 PM PDT 24
Peak memory 165148 kb
Host smart-45eb4775-4b57-4a37-8a5f-e1063b9da391
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=137636459 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.137636459
Directory /workspace/10.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.3954311046
Short name T120
Test name
Test status
Simulation time 1421290000 ps
CPU time 4.48 seconds
Started Jul 27 04:17:40 PM PDT 24
Finished Jul 27 04:17:50 PM PDT 24
Peak memory 165028 kb
Host smart-201461fb-8d39-4d63-8a94-e763d8f0d7b1
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3954311046 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.3954311046
Directory /workspace/11.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.3355767529
Short name T157
Test name
Test status
Simulation time 1536230000 ps
CPU time 4.94 seconds
Started Jul 27 04:18:40 PM PDT 24
Finished Jul 27 04:18:51 PM PDT 24
Peak memory 161968 kb
Host smart-73526fab-eac8-48bc-b83c-3e0d8995c59d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3355767529 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.3355767529
Directory /workspace/12.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.194738191
Short name T143
Test name
Test status
Simulation time 1421310000 ps
CPU time 4 seconds
Started Jul 27 04:18:53 PM PDT 24
Finished Jul 27 04:19:02 PM PDT 24
Peak memory 164464 kb
Host smart-dc2a1bd6-ecb3-49a8-a17b-0ee1a29d0316
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=194738191 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.194738191
Directory /workspace/13.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.3933943273
Short name T115
Test name
Test status
Simulation time 1290250000 ps
CPU time 4.21 seconds
Started Jul 27 04:22:21 PM PDT 24
Finished Jul 27 04:22:30 PM PDT 24
Peak memory 164844 kb
Host smart-761b7112-ff70-45ba-9204-0b580f327dc3
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3933943273 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.3933943273
Directory /workspace/14.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.4178135842
Short name T136
Test name
Test status
Simulation time 1629750000 ps
CPU time 5.14 seconds
Started Jul 27 04:20:33 PM PDT 24
Finished Jul 27 04:20:44 PM PDT 24
Peak memory 164716 kb
Host smart-4ab00aa3-e763-41cb-84f9-167ea546b72a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4178135842 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.4178135842
Directory /workspace/15.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.2297815005
Short name T127
Test name
Test status
Simulation time 1466010000 ps
CPU time 4.62 seconds
Started Jul 27 04:18:41 PM PDT 24
Finished Jul 27 04:18:51 PM PDT 24
Peak memory 162764 kb
Host smart-7bb9e6b3-929b-45c6-9222-bb5cc722b929
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2297815005 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.2297815005
Directory /workspace/16.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.1947995490
Short name T145
Test name
Test status
Simulation time 1544470000 ps
CPU time 4.21 seconds
Started Jul 27 04:18:49 PM PDT 24
Finished Jul 27 04:18:58 PM PDT 24
Peak memory 164528 kb
Host smart-899ee411-a981-4024-b65b-00c1d64b446c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1947995490 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.1947995490
Directory /workspace/17.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.3008404379
Short name T151
Test name
Test status
Simulation time 1487110000 ps
CPU time 4.81 seconds
Started Jul 27 04:17:41 PM PDT 24
Finished Jul 27 04:17:51 PM PDT 24
Peak memory 165028 kb
Host smart-48b266c8-c931-4583-99e9-2cf27bf7ea70
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3008404379 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.3008404379
Directory /workspace/18.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.2320664772
Short name T137
Test name
Test status
Simulation time 1551050000 ps
CPU time 3.55 seconds
Started Jul 27 04:22:38 PM PDT 24
Finished Jul 27 04:22:46 PM PDT 24
Peak memory 164740 kb
Host smart-a4f1573b-9a00-44b5-a92b-db197691eaab
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2320664772 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.2320664772
Directory /workspace/19.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.2594550279
Short name T134
Test name
Test status
Simulation time 1421070000 ps
CPU time 4.13 seconds
Started Jul 27 04:22:08 PM PDT 24
Finished Jul 27 04:22:17 PM PDT 24
Peak memory 164360 kb
Host smart-d0958f5b-8f9c-4e14-8c62-2499e5e7e379
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2594550279 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.2594550279
Directory /workspace/2.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.3106701447
Short name T138
Test name
Test status
Simulation time 1279750000 ps
CPU time 4.31 seconds
Started Jul 27 04:17:40 PM PDT 24
Finished Jul 27 04:17:49 PM PDT 24
Peak memory 165028 kb
Host smart-3a63b277-16cf-48ff-a87b-e818ca0838e1
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3106701447 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.3106701447
Directory /workspace/20.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.2487174086
Short name T140
Test name
Test status
Simulation time 1163730000 ps
CPU time 4.01 seconds
Started Jul 27 04:20:19 PM PDT 24
Finished Jul 27 04:20:27 PM PDT 24
Peak memory 164696 kb
Host smart-e304bbb0-09ba-4c8e-b5e2-ab9f0e225a43
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2487174086 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.2487174086
Directory /workspace/21.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.1014029268
Short name T159
Test name
Test status
Simulation time 1307770000 ps
CPU time 3.94 seconds
Started Jul 27 04:18:49 PM PDT 24
Finished Jul 27 04:18:58 PM PDT 24
Peak memory 164408 kb
Host smart-c9147385-ce23-4d60-88d8-d640fb0ed859
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1014029268 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.1014029268
Directory /workspace/22.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.1512339060
Short name T122
Test name
Test status
Simulation time 1365630000 ps
CPU time 3.94 seconds
Started Jul 27 04:18:40 PM PDT 24
Finished Jul 27 04:18:50 PM PDT 24
Peak memory 164072 kb
Host smart-23e439cd-f52a-41b1-a523-008787d7da59
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1512339060 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.1512339060
Directory /workspace/23.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.2484813856
Short name T123
Test name
Test status
Simulation time 1455330000 ps
CPU time 4.74 seconds
Started Jul 27 04:18:41 PM PDT 24
Finished Jul 27 04:18:51 PM PDT 24
Peak memory 164268 kb
Host smart-0a7c8f1c-cc39-41ec-a428-92757e8c05f0
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2484813856 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.2484813856
Directory /workspace/24.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.3355829794
Short name T135
Test name
Test status
Simulation time 1342930000 ps
CPU time 3.6 seconds
Started Jul 27 04:22:37 PM PDT 24
Finished Jul 27 04:22:45 PM PDT 24
Peak memory 164740 kb
Host smart-0c0639e6-f6e1-47f6-a21b-8d7d13945129
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3355829794 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.3355829794
Directory /workspace/25.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.4061142507
Short name T149
Test name
Test status
Simulation time 1385090000 ps
CPU time 4 seconds
Started Jul 27 04:22:49 PM PDT 24
Finished Jul 27 04:22:58 PM PDT 24
Peak memory 164580 kb
Host smart-0b75ebd2-1c3c-4a8d-86fb-4b359bf4218f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4061142507 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.4061142507
Directory /workspace/26.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.3720355884
Short name T144
Test name
Test status
Simulation time 1214770000 ps
CPU time 3.53 seconds
Started Jul 27 04:22:31 PM PDT 24
Finished Jul 27 04:22:40 PM PDT 24
Peak memory 164484 kb
Host smart-4bf63e6f-c164-41a8-a76f-fbd427e8a77b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3720355884 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.3720355884
Directory /workspace/27.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.111444707
Short name T155
Test name
Test status
Simulation time 1607650000 ps
CPU time 5.21 seconds
Started Jul 27 04:18:40 PM PDT 24
Finished Jul 27 04:18:52 PM PDT 24
Peak memory 161932 kb
Host smart-02423960-5eef-43a9-a861-17a67e27d5fe
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=111444707 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.111444707
Directory /workspace/28.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.604418102
Short name T114
Test name
Test status
Simulation time 1434190000 ps
CPU time 4.24 seconds
Started Jul 27 04:18:41 PM PDT 24
Finished Jul 27 04:18:51 PM PDT 24
Peak memory 164464 kb
Host smart-690db320-cae2-4f2e-a376-13d76501b01d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=604418102 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.604418102
Directory /workspace/29.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.2342329167
Short name T125
Test name
Test status
Simulation time 1561450000 ps
CPU time 3.4 seconds
Started Jul 27 04:17:47 PM PDT 24
Finished Jul 27 04:17:55 PM PDT 24
Peak memory 164748 kb
Host smart-8a5074b2-b46c-4460-bbd0-2a330fcd8a25
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2342329167 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.2342329167
Directory /workspace/3.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.2771744248
Short name T156
Test name
Test status
Simulation time 1540970000 ps
CPU time 5.63 seconds
Started Jul 27 04:23:03 PM PDT 24
Finished Jul 27 04:23:15 PM PDT 24
Peak memory 162920 kb
Host smart-05ea7471-9d56-48aa-966d-3691b19bdd56
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2771744248 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.2771744248
Directory /workspace/30.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.4280961112
Short name T113
Test name
Test status
Simulation time 1389650000 ps
CPU time 4.21 seconds
Started Jul 27 04:22:38 PM PDT 24
Finished Jul 27 04:22:47 PM PDT 24
Peak memory 164268 kb
Host smart-46698df3-bf05-49ca-96fb-745e817db705
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4280961112 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.4280961112
Directory /workspace/31.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.26558511
Short name T130
Test name
Test status
Simulation time 1424010000 ps
CPU time 3.95 seconds
Started Jul 27 04:22:39 PM PDT 24
Finished Jul 27 04:22:47 PM PDT 24
Peak memory 164488 kb
Host smart-cebce007-d825-4613-8734-c95c9a65612c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=26558511 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.26558511
Directory /workspace/32.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.3416388498
Short name T152
Test name
Test status
Simulation time 1334270000 ps
CPU time 3.46 seconds
Started Jul 27 04:23:17 PM PDT 24
Finished Jul 27 04:23:25 PM PDT 24
Peak memory 164556 kb
Host smart-1d677871-a4a7-43be-9ab8-f6ccc855ae23
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3416388498 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.3416388498
Directory /workspace/33.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.2165510406
Short name T160
Test name
Test status
Simulation time 1231750000 ps
CPU time 4.29 seconds
Started Jul 27 04:23:03 PM PDT 24
Finished Jul 27 04:23:12 PM PDT 24
Peak memory 163012 kb
Host smart-bf2087a3-2952-47c4-a7cc-8496d047eba4
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2165510406 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.2165510406
Directory /workspace/34.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.180918881
Short name T133
Test name
Test status
Simulation time 1409070000 ps
CPU time 3.77 seconds
Started Jul 27 04:23:07 PM PDT 24
Finished Jul 27 04:23:16 PM PDT 24
Peak memory 164128 kb
Host smart-d84a6546-95ec-4752-96f8-37ba853719fe
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=180918881 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.180918881
Directory /workspace/35.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.574146337
Short name T112
Test name
Test status
Simulation time 1483210000 ps
CPU time 3.52 seconds
Started Jul 27 04:22:40 PM PDT 24
Finished Jul 27 04:22:48 PM PDT 24
Peak memory 164692 kb
Host smart-d01fdf18-6574-42c8-999b-a60e3bbac160
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=574146337 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.574146337
Directory /workspace/36.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.679629135
Short name T117
Test name
Test status
Simulation time 1421010000 ps
CPU time 3.45 seconds
Started Jul 27 04:22:25 PM PDT 24
Finished Jul 27 04:22:33 PM PDT 24
Peak memory 163996 kb
Host smart-8d5adaf0-3637-4a9b-9433-b6a57a6aa0ad
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=679629135 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.679629135
Directory /workspace/37.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.3131293311
Short name T131
Test name
Test status
Simulation time 1483830000 ps
CPU time 4.01 seconds
Started Jul 27 04:23:08 PM PDT 24
Finished Jul 27 04:23:17 PM PDT 24
Peak memory 164400 kb
Host smart-9dd61772-a8a3-4d3a-943f-d941f6d76e45
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3131293311 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.3131293311
Directory /workspace/38.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.4290698092
Short name T141
Test name
Test status
Simulation time 1545410000 ps
CPU time 4.57 seconds
Started Jul 27 04:19:47 PM PDT 24
Finished Jul 27 04:19:58 PM PDT 24
Peak memory 164808 kb
Host smart-5461ade5-b661-4c9d-9c86-2521c5ff047b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4290698092 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.4290698092
Directory /workspace/39.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3774116507
Short name T129
Test name
Test status
Simulation time 1499830000 ps
CPU time 4.94 seconds
Started Jul 27 04:17:41 PM PDT 24
Finished Jul 27 04:17:51 PM PDT 24
Peak memory 164964 kb
Host smart-4cad9d52-72fa-4abf-80c7-7dc4f6a95b04
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3774116507 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.3774116507
Directory /workspace/4.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.3839847987
Short name T128
Test name
Test status
Simulation time 1465910000 ps
CPU time 3.92 seconds
Started Jul 27 04:18:30 PM PDT 24
Finished Jul 27 04:18:39 PM PDT 24
Peak memory 164752 kb
Host smart-96526eb9-a8df-4a04-a5e4-fa0179c23387
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3839847987 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.3839847987
Directory /workspace/40.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.2318337635
Short name T126
Test name
Test status
Simulation time 1534210000 ps
CPU time 3.94 seconds
Started Jul 27 04:23:42 PM PDT 24
Finished Jul 27 04:23:51 PM PDT 24
Peak memory 164496 kb
Host smart-c7bb41ee-861b-4185-9ee4-0c9b60f1b1d3
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2318337635 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.2318337635
Directory /workspace/41.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.3430670447
Short name T153
Test name
Test status
Simulation time 1464390000 ps
CPU time 3.7 seconds
Started Jul 27 04:23:40 PM PDT 24
Finished Jul 27 04:23:48 PM PDT 24
Peak memory 164292 kb
Host smart-e95ac592-0b6c-4612-8367-1ecd03721325
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3430670447 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.3430670447
Directory /workspace/42.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.2377778362
Short name T132
Test name
Test status
Simulation time 1499250000 ps
CPU time 3.78 seconds
Started Jul 27 04:22:10 PM PDT 24
Finished Jul 27 04:22:18 PM PDT 24
Peak memory 163636 kb
Host smart-418d3283-bb4e-4299-b115-94584f11cdb8
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2377778362 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.2377778362
Directory /workspace/43.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.3751923823
Short name T116
Test name
Test status
Simulation time 1518330000 ps
CPU time 5.02 seconds
Started Jul 27 04:19:07 PM PDT 24
Finished Jul 27 04:19:18 PM PDT 24
Peak memory 164676 kb
Host smart-0af7d9bd-7c96-4ee3-b88d-a48fac14bd91
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3751923823 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.3751923823
Directory /workspace/44.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.710233745
Short name T147
Test name
Test status
Simulation time 1299830000 ps
CPU time 3.39 seconds
Started Jul 27 04:23:42 PM PDT 24
Finished Jul 27 04:23:49 PM PDT 24
Peak memory 164556 kb
Host smart-4e37e540-d525-496f-83af-806829653674
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=710233745 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.710233745
Directory /workspace/45.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.526859182
Short name T154
Test name
Test status
Simulation time 1465230000 ps
CPU time 3.93 seconds
Started Jul 27 04:20:15 PM PDT 24
Finished Jul 27 04:20:24 PM PDT 24
Peak memory 164624 kb
Host smart-8bf800d9-20dd-468a-8fc9-1570ee22e77d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=526859182 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.526859182
Directory /workspace/46.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.1547809867
Short name T158
Test name
Test status
Simulation time 1331550000 ps
CPU time 3.49 seconds
Started Jul 27 04:23:21 PM PDT 24
Finished Jul 27 04:23:28 PM PDT 24
Peak memory 164460 kb
Host smart-173d48a2-2d35-4f35-98a3-1312f2e29b03
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1547809867 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.1547809867
Directory /workspace/47.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.3417200734
Short name T139
Test name
Test status
Simulation time 1254310000 ps
CPU time 3.32 seconds
Started Jul 27 04:23:21 PM PDT 24
Finished Jul 27 04:23:28 PM PDT 24
Peak memory 164460 kb
Host smart-e82676a3-515f-4f08-b80e-0e6faa8ea845
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3417200734 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.3417200734
Directory /workspace/48.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.3414605931
Short name T150
Test name
Test status
Simulation time 1444210000 ps
CPU time 4.37 seconds
Started Jul 27 04:19:43 PM PDT 24
Finished Jul 27 04:19:52 PM PDT 24
Peak memory 164716 kb
Host smart-e10e4bf3-ed9b-4601-bba0-4e6e4a47038e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3414605931 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.3414605931
Directory /workspace/49.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.544789277
Short name T121
Test name
Test status
Simulation time 1345510000 ps
CPU time 4.36 seconds
Started Jul 27 04:17:45 PM PDT 24
Finished Jul 27 04:17:54 PM PDT 24
Peak memory 164840 kb
Host smart-7fe3f687-5c38-4051-a85f-5b70362266d4
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=544789277 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.544789277
Directory /workspace/5.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.4007133937
Short name T118
Test name
Test status
Simulation time 1537410000 ps
CPU time 5.33 seconds
Started Jul 27 04:20:46 PM PDT 24
Finished Jul 27 04:20:58 PM PDT 24
Peak memory 164964 kb
Host smart-ac4333bd-bf07-42e6-82f9-334fd56d7756
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4007133937 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.4007133937
Directory /workspace/6.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.1827615775
Short name T148
Test name
Test status
Simulation time 1558150000 ps
CPU time 4.91 seconds
Started Jul 27 04:19:45 PM PDT 24
Finished Jul 27 04:19:56 PM PDT 24
Peak memory 164752 kb
Host smart-c2d884a7-fe4a-474a-af1d-3f55b8213f8b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1827615775 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.1827615775
Directory /workspace/7.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1643406220
Short name T119
Test name
Test status
Simulation time 1459770000 ps
CPU time 3.59 seconds
Started Jul 27 04:22:23 PM PDT 24
Finished Jul 27 04:22:31 PM PDT 24
Peak memory 163616 kb
Host smart-d820ce50-c551-4040-8ced-4266c1c698a5
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1643406220 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.1643406220
Directory /workspace/8.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.409346939
Short name T146
Test name
Test status
Simulation time 1429950000 ps
CPU time 3.56 seconds
Started Jul 27 04:22:06 PM PDT 24
Finished Jul 27 04:22:14 PM PDT 24
Peak memory 164424 kb
Host smart-a688054d-8530-47bf-b2ef-4ac128440c5c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=409346939 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.409346939
Directory /workspace/9.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.816675890
Short name T46
Test name
Test status
Simulation time 1542950000 ps
CPU time 4.56 seconds
Started Jul 27 04:19:34 PM PDT 24
Finished Jul 27 04:19:44 PM PDT 24
Peak memory 164748 kb
Host smart-55721bf9-dee3-4739-adda-49cba06b0f0a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=816675890 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.816675890
Directory /workspace/0.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.1153155077
Short name T67
Test name
Test status
Simulation time 1551170000 ps
CPU time 4.13 seconds
Started Jul 27 04:19:32 PM PDT 24
Finished Jul 27 04:19:41 PM PDT 24
Peak memory 164912 kb
Host smart-d45c8de4-11d5-4dd6-a35a-b115913ee44b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1153155077 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.1153155077
Directory /workspace/1.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.3200956977
Short name T56
Test name
Test status
Simulation time 1502650000 ps
CPU time 4.6 seconds
Started Jul 27 04:19:59 PM PDT 24
Finished Jul 27 04:20:09 PM PDT 24
Peak memory 165028 kb
Host smart-066a3b09-fccb-431c-9e33-f128974fa85c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3200956977 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.3200956977
Directory /workspace/10.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.1841710190
Short name T32
Test name
Test status
Simulation time 1541330000 ps
CPU time 4.87 seconds
Started Jul 27 04:22:07 PM PDT 24
Finished Jul 27 04:22:18 PM PDT 24
Peak memory 163300 kb
Host smart-ea6f2119-3c2d-4c9b-86dc-f3dac79f8dfa
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1841710190 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.1841710190
Directory /workspace/11.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.1581406717
Short name T40
Test name
Test status
Simulation time 1128950000 ps
CPU time 3.72 seconds
Started Jul 27 04:22:07 PM PDT 24
Finished Jul 27 04:22:16 PM PDT 24
Peak memory 164016 kb
Host smart-48b32d7a-3fb3-4f4d-bb91-a017f448a005
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1581406717 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.1581406717
Directory /workspace/13.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.255307087
Short name T70
Test name
Test status
Simulation time 1567650000 ps
CPU time 3.99 seconds
Started Jul 27 04:22:30 PM PDT 24
Finished Jul 27 04:22:39 PM PDT 24
Peak memory 164516 kb
Host smart-fcf3b2f9-430c-4d7b-8a84-c4afd147d261
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=255307087 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.255307087
Directory /workspace/14.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.3164759886
Short name T49
Test name
Test status
Simulation time 1396030000 ps
CPU time 3.56 seconds
Started Jul 27 04:22:20 PM PDT 24
Finished Jul 27 04:22:29 PM PDT 24
Peak memory 163432 kb
Host smart-eb41c0c2-a829-433e-9b38-49dbd8a81985
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3164759886 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.3164759886
Directory /workspace/15.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.3226768387
Short name T36
Test name
Test status
Simulation time 1477290000 ps
CPU time 3.63 seconds
Started Jul 27 04:22:01 PM PDT 24
Finished Jul 27 04:22:09 PM PDT 24
Peak memory 163688 kb
Host smart-c1d2d57d-f867-4ae6-95c5-2280a1fb214f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3226768387 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.3226768387
Directory /workspace/16.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.611307828
Short name T34
Test name
Test status
Simulation time 1388990000 ps
CPU time 2.9 seconds
Started Jul 27 04:17:57 PM PDT 24
Finished Jul 27 04:18:04 PM PDT 24
Peak memory 163748 kb
Host smart-20aa1189-8800-4059-9971-a040250a0c82
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=611307828 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.611307828
Directory /workspace/17.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.3182505045
Short name T41
Test name
Test status
Simulation time 1544330000 ps
CPU time 4.78 seconds
Started Jul 27 04:21:03 PM PDT 24
Finished Jul 27 04:21:14 PM PDT 24
Peak memory 164724 kb
Host smart-bbcf08fb-6eea-4327-94c2-3bc81ef1efd6
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3182505045 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.3182505045
Directory /workspace/18.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.957158423
Short name T8
Test name
Test status
Simulation time 1460170000 ps
CPU time 3.84 seconds
Started Jul 27 04:22:01 PM PDT 24
Finished Jul 27 04:22:10 PM PDT 24
Peak memory 163448 kb
Host smart-d7a47885-b3b0-41cd-b560-d584fd516358
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=957158423 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.957158423
Directory /workspace/19.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.2367929773
Short name T37
Test name
Test status
Simulation time 1591150000 ps
CPU time 3.88 seconds
Started Jul 27 04:18:05 PM PDT 24
Finished Jul 27 04:18:13 PM PDT 24
Peak memory 164740 kb
Host smart-0b625ec7-1bc9-4cd0-9459-838143de07d6
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2367929773 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.2367929773
Directory /workspace/2.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.467858376
Short name T2
Test name
Test status
Simulation time 1528730000 ps
CPU time 4.33 seconds
Started Jul 27 04:22:04 PM PDT 24
Finished Jul 27 04:22:15 PM PDT 24
Peak memory 163040 kb
Host smart-6b78cc7d-1eef-4b1e-8ebb-0550eb201b15
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=467858376 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.467858376
Directory /workspace/20.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.171535991
Short name T38
Test name
Test status
Simulation time 1535510000 ps
CPU time 3.22 seconds
Started Jul 27 04:22:38 PM PDT 24
Finished Jul 27 04:22:46 PM PDT 24
Peak memory 164300 kb
Host smart-aa9975f0-0f86-4d57-b726-f7efe85257ed
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=171535991 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.171535991
Directory /workspace/21.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.333966543
Short name T11
Test name
Test status
Simulation time 1416530000 ps
CPU time 4.8 seconds
Started Jul 27 04:18:18 PM PDT 24
Finished Jul 27 04:18:28 PM PDT 24
Peak memory 164916 kb
Host smart-aeee5247-1210-4bc6-9526-8a9e822996c9
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=333966543 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.333966543
Directory /workspace/22.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.785892536
Short name T55
Test name
Test status
Simulation time 1413750000 ps
CPU time 3.93 seconds
Started Jul 27 04:22:20 PM PDT 24
Finished Jul 27 04:22:28 PM PDT 24
Peak memory 163548 kb
Host smart-6e087c4e-1b7e-40b3-8826-864bdd67a7a7
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=785892536 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.785892536
Directory /workspace/23.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.4130046116
Short name T54
Test name
Test status
Simulation time 1566790000 ps
CPU time 4.71 seconds
Started Jul 27 04:22:33 PM PDT 24
Finished Jul 27 04:22:44 PM PDT 24
Peak memory 164540 kb
Host smart-7f02bcdc-b215-4e8f-870c-386f16c7a3c3
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4130046116 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.4130046116
Directory /workspace/24.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.2047113946
Short name T64
Test name
Test status
Simulation time 1434070000 ps
CPU time 4.32 seconds
Started Jul 27 04:22:27 PM PDT 24
Finished Jul 27 04:22:37 PM PDT 24
Peak memory 164468 kb
Host smart-ef2382ef-00f7-4b9a-a594-d81d39495937
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2047113946 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.2047113946
Directory /workspace/25.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.2363033322
Short name T68
Test name
Test status
Simulation time 1426810000 ps
CPU time 4.06 seconds
Started Jul 27 04:22:20 PM PDT 24
Finished Jul 27 04:22:30 PM PDT 24
Peak memory 163520 kb
Host smart-4a649496-a6fa-4c2f-b71e-653e9270d22b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2363033322 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.2363033322
Directory /workspace/26.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.3535609365
Short name T47
Test name
Test status
Simulation time 1548010000 ps
CPU time 5.47 seconds
Started Jul 27 04:18:28 PM PDT 24
Finished Jul 27 04:18:40 PM PDT 24
Peak memory 164676 kb
Host smart-d04dce3a-de01-49e6-8d07-7c3bba99da2f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3535609365 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.3535609365
Directory /workspace/27.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.108225722
Short name T12
Test name
Test status
Simulation time 1570170000 ps
CPU time 4.94 seconds
Started Jul 27 04:17:36 PM PDT 24
Finished Jul 27 04:17:47 PM PDT 24
Peak memory 163708 kb
Host smart-376df2c9-111b-4d68-aacd-5894c389286d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=108225722 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.108225722
Directory /workspace/28.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.3754173630
Short name T58
Test name
Test status
Simulation time 1551690000 ps
CPU time 4.08 seconds
Started Jul 27 04:18:02 PM PDT 24
Finished Jul 27 04:18:11 PM PDT 24
Peak memory 164508 kb
Host smart-0c38d2d8-206b-446c-adc1-ab43b712b097
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3754173630 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.3754173630
Directory /workspace/29.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.3429555954
Short name T50
Test name
Test status
Simulation time 1527930000 ps
CPU time 3.2 seconds
Started Jul 27 04:18:26 PM PDT 24
Finished Jul 27 04:18:33 PM PDT 24
Peak memory 164932 kb
Host smart-884fdc93-e33f-4c60-8d20-28a3fd222b1a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3429555954 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.3429555954
Directory /workspace/3.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.1719259000
Short name T51
Test name
Test status
Simulation time 1222490000 ps
CPU time 3.59 seconds
Started Jul 27 04:18:41 PM PDT 24
Finished Jul 27 04:18:49 PM PDT 24
Peak memory 164792 kb
Host smart-52ce810b-cd97-434b-9db8-50632bbd186c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1719259000 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.1719259000
Directory /workspace/30.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.1472832468
Short name T43
Test name
Test status
Simulation time 1288850000 ps
CPU time 3.75 seconds
Started Jul 27 04:18:53 PM PDT 24
Finished Jul 27 04:19:01 PM PDT 24
Peak memory 164432 kb
Host smart-16f8f14e-35da-40ee-9997-64abc6823528
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1472832468 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.1472832468
Directory /workspace/31.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.3256314713
Short name T42
Test name
Test status
Simulation time 1493410000 ps
CPU time 4.33 seconds
Started Jul 27 04:18:41 PM PDT 24
Finished Jul 27 04:18:50 PM PDT 24
Peak memory 162872 kb
Host smart-3100fdd7-1029-4983-a036-78ad0ca82bc3
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3256314713 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.3256314713
Directory /workspace/32.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.938880444
Short name T57
Test name
Test status
Simulation time 1416930000 ps
CPU time 4 seconds
Started Jul 27 04:18:40 PM PDT 24
Finished Jul 27 04:18:50 PM PDT 24
Peak memory 163004 kb
Host smart-46e120bd-8020-47f8-97e9-0d51fb68ad4d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=938880444 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.938880444
Directory /workspace/33.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.1513010996
Short name T13
Test name
Test status
Simulation time 1213490000 ps
CPU time 3.41 seconds
Started Jul 27 04:22:27 PM PDT 24
Finished Jul 27 04:22:35 PM PDT 24
Peak memory 163612 kb
Host smart-09699e65-61b6-4bd8-8057-ae4ff36ead84
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1513010996 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.1513010996
Directory /workspace/34.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.3663701524
Short name T61
Test name
Test status
Simulation time 1430990000 ps
CPU time 4.1 seconds
Started Jul 27 04:22:32 PM PDT 24
Finished Jul 27 04:22:41 PM PDT 24
Peak memory 164496 kb
Host smart-aa2a27c2-f191-484e-8279-fa36ca5f92aa
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3663701524 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.3663701524
Directory /workspace/35.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.664864679
Short name T63
Test name
Test status
Simulation time 1497530000 ps
CPU time 4.2 seconds
Started Jul 27 04:22:38 PM PDT 24
Finished Jul 27 04:22:47 PM PDT 24
Peak memory 164208 kb
Host smart-c71b5012-c7c6-4753-86d9-f1532bd23b58
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=664864679 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.664864679
Directory /workspace/36.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.1834927348
Short name T39
Test name
Test status
Simulation time 1180010000 ps
CPU time 4.03 seconds
Started Jul 27 04:23:04 PM PDT 24
Finished Jul 27 04:23:13 PM PDT 24
Peak memory 164428 kb
Host smart-478309c5-6853-4e9e-a2a5-9f245ad112cf
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1834927348 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.1834927348
Directory /workspace/37.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.678296450
Short name T44
Test name
Test status
Simulation time 1438010000 ps
CPU time 4.39 seconds
Started Jul 27 04:22:30 PM PDT 24
Finished Jul 27 04:22:41 PM PDT 24
Peak memory 163120 kb
Host smart-c2998f54-eb5f-4bac-81c0-7850578a578f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=678296450 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.678296450
Directory /workspace/38.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.3491433005
Short name T9
Test name
Test status
Simulation time 1346170000 ps
CPU time 4.09 seconds
Started Jul 27 04:22:38 PM PDT 24
Finished Jul 27 04:22:47 PM PDT 24
Peak memory 164152 kb
Host smart-4dbb92bc-6bd5-45bf-b066-0abf1c614f01
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3491433005 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.3491433005
Directory /workspace/39.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.1468505412
Short name T10
Test name
Test status
Simulation time 1594550000 ps
CPU time 5.33 seconds
Started Jul 27 04:18:19 PM PDT 24
Finished Jul 27 04:18:30 PM PDT 24
Peak memory 164912 kb
Host smart-4652a3a4-456c-4939-ac0e-b2bf33a67390
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1468505412 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.1468505412
Directory /workspace/4.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.1402103252
Short name T65
Test name
Test status
Simulation time 1328630000 ps
CPU time 4.7 seconds
Started Jul 27 04:23:03 PM PDT 24
Finished Jul 27 04:23:13 PM PDT 24
Peak memory 162976 kb
Host smart-d13d83d7-ff85-4675-940b-d5e3b634f570
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1402103252 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.1402103252
Directory /workspace/40.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.990961886
Short name T52
Test name
Test status
Simulation time 1467170000 ps
CPU time 4.88 seconds
Started Jul 27 04:23:04 PM PDT 24
Finished Jul 27 04:23:14 PM PDT 24
Peak memory 164424 kb
Host smart-4b6386dc-e6b5-45ee-ad46-b6fb7e5e7c01
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=990961886 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.990961886
Directory /workspace/41.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.2698517742
Short name T45
Test name
Test status
Simulation time 1464010000 ps
CPU time 4.04 seconds
Started Jul 27 04:22:38 PM PDT 24
Finished Jul 27 04:22:47 PM PDT 24
Peak memory 164148 kb
Host smart-b36a1255-1ab2-4629-8b9d-92802bc7895c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2698517742 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.2698517742
Directory /workspace/42.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.1162881013
Short name T33
Test name
Test status
Simulation time 1519610000 ps
CPU time 3.13 seconds
Started Jul 27 04:22:21 PM PDT 24
Finished Jul 27 04:22:28 PM PDT 24
Peak memory 163300 kb
Host smart-fb1a1f88-ef6e-4266-8671-5640c77e798b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1162881013 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.1162881013
Directory /workspace/43.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.4094769249
Short name T59
Test name
Test status
Simulation time 1415310000 ps
CPU time 3.5 seconds
Started Jul 27 04:22:28 PM PDT 24
Finished Jul 27 04:22:36 PM PDT 24
Peak memory 164544 kb
Host smart-ffbe6140-dab1-4907-81e7-0fde7708caff
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4094769249 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.4094769249
Directory /workspace/44.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.3407231291
Short name T69
Test name
Test status
Simulation time 1451110000 ps
CPU time 3.09 seconds
Started Jul 27 04:22:25 PM PDT 24
Finished Jul 27 04:22:32 PM PDT 24
Peak memory 164452 kb
Host smart-1d79c539-2095-4442-9c60-5515d9762d1a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3407231291 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.3407231291
Directory /workspace/45.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.3977848371
Short name T35
Test name
Test status
Simulation time 1437430000 ps
CPU time 3.08 seconds
Started Jul 27 04:22:34 PM PDT 24
Finished Jul 27 04:22:41 PM PDT 24
Peak memory 164540 kb
Host smart-602bbaef-99e7-4e7d-afad-187e6b1aeae6
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3977848371 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.3977848371
Directory /workspace/46.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.2571849840
Short name T31
Test name
Test status
Simulation time 1454870000 ps
CPU time 3.56 seconds
Started Jul 27 04:19:28 PM PDT 24
Finished Jul 27 04:19:36 PM PDT 24
Peak memory 164432 kb
Host smart-153f629f-92ed-40a5-afba-08f6a6d58eb1
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2571849840 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.2571849840
Directory /workspace/47.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.3467484600
Short name T1
Test name
Test status
Simulation time 1523170000 ps
CPU time 3.97 seconds
Started Jul 27 04:22:27 PM PDT 24
Finished Jul 27 04:22:36 PM PDT 24
Peak memory 163652 kb
Host smart-8a0445c7-e3a9-4050-a329-f67c98800b6a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3467484600 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.3467484600
Directory /workspace/48.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.2717749340
Short name T48
Test name
Test status
Simulation time 1413210000 ps
CPU time 3.55 seconds
Started Jul 27 04:23:15 PM PDT 24
Finished Jul 27 04:23:23 PM PDT 24
Peak memory 164952 kb
Host smart-c5fff8bc-909c-4111-a847-d7ab85e01e6d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2717749340 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.2717749340
Directory /workspace/49.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.1584019235
Short name T60
Test name
Test status
Simulation time 1182370000 ps
CPU time 4.16 seconds
Started Jul 27 04:18:27 PM PDT 24
Finished Jul 27 04:18:35 PM PDT 24
Peak memory 164912 kb
Host smart-238c0231-0e29-4dbb-9acc-060f664f7649
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1584019235 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.1584019235
Directory /workspace/5.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.1006070424
Short name T53
Test name
Test status
Simulation time 1230030000 ps
CPU time 5.06 seconds
Started Jul 27 04:17:58 PM PDT 24
Finished Jul 27 04:18:09 PM PDT 24
Peak memory 164732 kb
Host smart-db5a9fa4-299b-450e-8904-42b8b58b051d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1006070424 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.1006070424
Directory /workspace/6.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.1640043059
Short name T66
Test name
Test status
Simulation time 1575170000 ps
CPU time 4.78 seconds
Started Jul 27 04:22:32 PM PDT 24
Finished Jul 27 04:22:43 PM PDT 24
Peak memory 164476 kb
Host smart-22b2f3a6-aa0f-4b90-bc31-b26a79698d50
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1640043059 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.1640043059
Directory /workspace/7.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.480027025
Short name T3
Test name
Test status
Simulation time 1509610000 ps
CPU time 5.12 seconds
Started Jul 27 04:19:59 PM PDT 24
Finished Jul 27 04:20:10 PM PDT 24
Peak memory 164788 kb
Host smart-105c6963-df2a-4358-9298-7bdc41d63821
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=480027025 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.480027025
Directory /workspace/8.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.3091845867
Short name T62
Test name
Test status
Simulation time 1445410000 ps
CPU time 4.81 seconds
Started Jul 27 04:22:31 PM PDT 24
Finished Jul 27 04:22:41 PM PDT 24
Peak memory 163520 kb
Host smart-6799fec8-2631-4779-ac76-f55bc3c229d5
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3091845867 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.3091845867
Directory /workspace/9.prim_lfsr_gal_smoke/latest
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