Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.31 100.00 96.55 100.00 100.00 95.00


Total tests in report: 200
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
87.31 87.31 100.00 100.00 96.55 96.55 100.00 100.00 100.00 100.00 40.00 40.00 /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.1629304674
96.81 9.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 87.50 47.50 /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.3310047907
98.31 1.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 95.00 7.50 /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.3938024426

Tests that do not contribute to grading

Name
/workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.2257791395
/workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.381213271
/workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.3278204339
/workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.1518819725
/workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.3203165462
/workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.2452757328
/workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.1403915867
/workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.3471835742
/workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.4257856332
/workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.418284987
/workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.1868052296
/workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.944842544
/workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.3558778283
/workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.3168985387
/workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.3634225298
/workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.3813927397
/workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.3107450494
/workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.4272153785
/workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.2957786352
/workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.4005609141
/workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.3774325789
/workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.1428102081
/workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.1955840873
/workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.1757916160
/workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.955067815
/workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.1019296843
/workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.3446985578
/workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.1412109432
/workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.2904474227
/workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.307090875
/workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.535683299
/workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.432757014
/workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.1621564691
/workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.4115811081
/workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.1721375805
/workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.3169163381
/workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.126739884
/workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.308538544
/workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.1829189334
/workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.3874430223
/workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.762099005
/workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.3238495976
/workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.1345251837
/workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.1894413350
/workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.3111553831
/workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.4130052776
/workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.1514558659
/workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.487933845
/workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.3319701791
/workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.33804861
/workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.263473959
/workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.260903890
/workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.3685648336
/workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.215073904
/workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.2745917567
/workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.3476408719
/workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.1034215477
/workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.365229355
/workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.1956699488
/workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.4055040127
/workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.2440344557
/workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.664055400
/workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.977839640
/workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.2194433721
/workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.693787829
/workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.1631017303
/workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.2598747938
/workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.1664282980
/workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.3895998197
/workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.4222820094
/workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.1000607323
/workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.820062233
/workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.1424466537
/workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.77233421
/workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.846673750
/workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.1948997351
/workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.2631894804
/workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.88625874
/workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.810435564
/workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.659446478
/workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.2271893612
/workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.1761136939
/workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.3140647842
/workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.323271151
/workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.2957283341
/workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.3134000828
/workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.958967376
/workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.4192369330
/workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.558604679
/workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.2562294812
/workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.1216521585
/workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.3806186537
/workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.2248192417
/workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.2464722716
/workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.632689983
/workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.3854461743
/workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.2133079529
/workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.644250955
/workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.663108383
/workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.3356252682
/workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.2177019612
/workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.4193338667
/workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.3351637110
/workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.287219836
/workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.2884671138
/workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.2595768505
/workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.2331796833
/workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.4040425628
/workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.2243367214
/workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.3270263863
/workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.2244751996
/workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.4203379646
/workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3911573974
/workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.1769608384
/workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.3587177252
/workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.4205289129
/workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.151603485
/workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.840476829
/workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.303875380
/workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.910595431
/workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.1770791588
/workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.2693621712
/workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.759551631
/workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.868390660
/workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.3066109957
/workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.668856563
/workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.4097281310
/workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.296711340
/workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.2338201620
/workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.3637461686
/workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.2200227166
/workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.3920149797
/workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.1665615558
/workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.561710440
/workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.11264587
/workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.3272952081
/workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.3707635355
/workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.3595227014
/workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.739198262
/workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.2330095915
/workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.255436320
/workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.3002982515
/workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.1112971535
/workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.1424095402
/workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.159677567
/workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.1055862401
/workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.3482646586
/workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.4119082283
/workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.3430412194
/workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.2801145322
/workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.2235126190
/workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.3347567244
/workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.2949439468
/workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.2982014943
/workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.1669700753
/workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.2556099075
/workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.793989559
/workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.3603622490
/workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.3390376005
/workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.1244802852
/workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.4160269284
/workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.2812156086
/workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.3069106543
/workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.2654044335
/workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.3291907728
/workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.3217018594
/workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.145852418
/workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.2556507558
/workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.1047695138
/workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.204023879
/workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.1177809370
/workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.712195137
/workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.310987924
/workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.4124975399
/workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.1030939023
/workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.1811955177
/workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.2358757510
/workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.3867286338
/workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.3968637671
/workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.864658513
/workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.1223268239
/workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.1986616024
/workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.2957098616
/workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.2226595301
/workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.205243749
/workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.3677054444
/workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.2726820841
/workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.2917525048
/workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.1240414051
/workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.2072085806
/workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.3369536548
/workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.809875819
/workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.851661009
/workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.2122168086
/workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.635262006
/workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.299008485
/workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.3178126276



Total test records in report: 200
tests.html | tests1.html | tests2.html | tests3.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.712195137 Jul 28 04:19:29 PM PDT 24 Jul 28 04:19:40 PM PDT 24 1506770000 ps
T2 /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.4124975399 Jul 28 04:19:30 PM PDT 24 Jul 28 04:19:43 PM PDT 24 1585810000 ps
T3 /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.3390376005 Jul 28 04:19:24 PM PDT 24 Jul 28 04:19:34 PM PDT 24 1594470000 ps
T7 /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.1629304674 Jul 28 04:19:30 PM PDT 24 Jul 28 04:19:42 PM PDT 24 1609550000 ps
T8 /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.1223268239 Jul 28 04:19:24 PM PDT 24 Jul 28 04:19:32 PM PDT 24 1578490000 ps
T9 /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.851661009 Jul 28 04:19:29 PM PDT 24 Jul 28 04:19:40 PM PDT 24 1448870000 ps
T10 /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.4160269284 Jul 28 04:19:30 PM PDT 24 Jul 28 04:19:40 PM PDT 24 1395290000 ps
T11 /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.2556099075 Jul 28 04:19:30 PM PDT 24 Jul 28 04:19:40 PM PDT 24 1554350000 ps
T12 /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.310987924 Jul 28 04:19:24 PM PDT 24 Jul 28 04:19:30 PM PDT 24 1413450000 ps
T13 /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.1177809370 Jul 28 04:19:32 PM PDT 24 Jul 28 04:19:43 PM PDT 24 1634750000 ps
T31 /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.205243749 Jul 28 04:19:24 PM PDT 24 Jul 28 04:19:34 PM PDT 24 1430910000 ps
T32 /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.2358757510 Jul 28 04:19:32 PM PDT 24 Jul 28 04:19:41 PM PDT 24 1277910000 ps
T33 /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.2812156086 Jul 28 04:19:33 PM PDT 24 Jul 28 04:19:42 PM PDT 24 1305230000 ps
T34 /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.1047695138 Jul 28 04:19:30 PM PDT 24 Jul 28 04:19:41 PM PDT 24 1538050000 ps
T35 /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.3603622490 Jul 28 04:19:33 PM PDT 24 Jul 28 04:19:43 PM PDT 24 1534190000 ps
T36 /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.3867286338 Jul 28 04:19:29 PM PDT 24 Jul 28 04:19:38 PM PDT 24 1252510000 ps
T37 /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.1669700753 Jul 28 04:19:24 PM PDT 24 Jul 28 04:19:34 PM PDT 24 1539410000 ps
T38 /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.3677054444 Jul 28 04:19:29 PM PDT 24 Jul 28 04:19:38 PM PDT 24 1369870000 ps
T39 /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.809875819 Jul 28 04:19:33 PM PDT 24 Jul 28 04:19:44 PM PDT 24 1551310000 ps
T40 /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.2949439468 Jul 28 04:19:32 PM PDT 24 Jul 28 04:19:41 PM PDT 24 1350450000 ps
T41 /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.3178126276 Jul 28 04:19:29 PM PDT 24 Jul 28 04:19:40 PM PDT 24 1552210000 ps
T42 /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.1244802852 Jul 28 04:19:29 PM PDT 24 Jul 28 04:19:41 PM PDT 24 1565870000 ps
T43 /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.864658513 Jul 28 04:19:30 PM PDT 24 Jul 28 04:19:38 PM PDT 24 1172050000 ps
T44 /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.2235126190 Jul 28 04:19:32 PM PDT 24 Jul 28 04:19:43 PM PDT 24 1491890000 ps
T45 /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.3968637671 Jul 28 04:19:29 PM PDT 24 Jul 28 04:19:38 PM PDT 24 1388890000 ps
T46 /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.1030939023 Jul 28 04:20:11 PM PDT 24 Jul 28 04:20:20 PM PDT 24 1496770000 ps
T47 /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.793989559 Jul 28 04:19:30 PM PDT 24 Jul 28 04:19:40 PM PDT 24 1548970000 ps
T48 /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.3347567244 Jul 28 04:19:33 PM PDT 24 Jul 28 04:19:43 PM PDT 24 1435050000 ps
T49 /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.3430412194 Jul 28 04:19:24 PM PDT 24 Jul 28 04:19:31 PM PDT 24 1456190000 ps
T50 /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.2982014943 Jul 28 04:19:34 PM PDT 24 Jul 28 04:19:44 PM PDT 24 1530250000 ps
T51 /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.1986616024 Jul 28 04:19:30 PM PDT 24 Jul 28 04:19:41 PM PDT 24 1602750000 ps
T52 /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.2654044335 Jul 28 04:19:31 PM PDT 24 Jul 28 04:19:39 PM PDT 24 1590530000 ps
T53 /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.2072085806 Jul 28 04:19:29 PM PDT 24 Jul 28 04:19:40 PM PDT 24 1479770000 ps
T54 /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.3217018594 Jul 28 04:19:30 PM PDT 24 Jul 28 04:19:40 PM PDT 24 1444770000 ps
T55 /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.2556507558 Jul 28 04:19:24 PM PDT 24 Jul 28 04:19:34 PM PDT 24 1415430000 ps
T56 /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.2801145322 Jul 28 04:19:30 PM PDT 24 Jul 28 04:19:40 PM PDT 24 1446010000 ps
T57 /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.2226595301 Jul 28 04:19:28 PM PDT 24 Jul 28 04:19:38 PM PDT 24 1438410000 ps
T58 /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.2122168086 Jul 28 04:19:30 PM PDT 24 Jul 28 04:19:42 PM PDT 24 1587970000 ps
T59 /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.3069106543 Jul 28 04:19:29 PM PDT 24 Jul 28 04:19:40 PM PDT 24 1554150000 ps
T60 /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.2726820841 Jul 28 04:19:33 PM PDT 24 Jul 28 04:19:41 PM PDT 24 1187810000 ps
T61 /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.3291907728 Jul 28 04:19:32 PM PDT 24 Jul 28 04:19:42 PM PDT 24 1516410000 ps
T62 /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.3369536548 Jul 28 04:19:28 PM PDT 24 Jul 28 04:19:38 PM PDT 24 1537770000 ps
T63 /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.1240414051 Jul 28 04:19:33 PM PDT 24 Jul 28 04:19:43 PM PDT 24 1420990000 ps
T64 /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.145852418 Jul 28 04:20:08 PM PDT 24 Jul 28 04:20:15 PM PDT 24 1452510000 ps
T65 /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.635262006 Jul 28 04:19:29 PM PDT 24 Jul 28 04:19:40 PM PDT 24 1437350000 ps
T66 /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.1811955177 Jul 28 04:19:32 PM PDT 24 Jul 28 04:19:42 PM PDT 24 1470610000 ps
T67 /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.2917525048 Jul 28 04:19:29 PM PDT 24 Jul 28 04:19:40 PM PDT 24 1524990000 ps
T68 /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.2957098616 Jul 28 04:19:23 PM PDT 24 Jul 28 04:19:31 PM PDT 24 1558010000 ps
T69 /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.299008485 Jul 28 04:19:29 PM PDT 24 Jul 28 04:19:39 PM PDT 24 1350770000 ps
T70 /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.204023879 Jul 28 04:19:33 PM PDT 24 Jul 28 04:19:42 PM PDT 24 1387790000 ps
T4 /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.3446985578 Jul 28 04:24:57 PM PDT 24 Jul 28 04:52:32 PM PDT 24 337113410000 ps
T5 /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.1955840873 Jul 28 04:21:24 PM PDT 24 Jul 28 04:56:43 PM PDT 24 337003110000 ps
T6 /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.944842544 Jul 28 04:25:17 PM PDT 24 Jul 28 04:52:31 PM PDT 24 336847790000 ps
T14 /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.1757916160 Jul 28 04:25:03 PM PDT 24 Jul 28 04:57:23 PM PDT 24 336376670000 ps
T15 /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.3107450494 Jul 28 04:21:04 PM PDT 24 Jul 28 04:56:24 PM PDT 24 337028070000 ps
T16 /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.4257856332 Jul 28 04:21:15 PM PDT 24 Jul 28 04:53:11 PM PDT 24 336956850000 ps
T17 /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.3169163381 Jul 28 04:22:51 PM PDT 24 Jul 28 04:54:35 PM PDT 24 336508190000 ps
T18 /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.4005609141 Jul 28 04:22:31 PM PDT 24 Jul 28 04:50:20 PM PDT 24 336843350000 ps
T19 /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.3310047907 Jul 28 04:21:24 PM PDT 24 Jul 28 04:50:38 PM PDT 24 336989370000 ps
T20 /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.1721375805 Jul 28 04:24:50 PM PDT 24 Jul 28 04:53:34 PM PDT 24 336950690000 ps
T71 /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.3774325789 Jul 28 04:25:03 PM PDT 24 Jul 28 04:57:49 PM PDT 24 336694230000 ps
T72 /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.487933845 Jul 28 04:21:15 PM PDT 24 Jul 28 04:57:03 PM PDT 24 336399110000 ps
T73 /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.1868052296 Jul 28 04:20:08 PM PDT 24 Jul 28 04:43:55 PM PDT 24 336351050000 ps
T74 /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.1514558659 Jul 28 04:20:14 PM PDT 24 Jul 28 04:53:38 PM PDT 24 336610670000 ps
T75 /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.1894413350 Jul 28 04:21:58 PM PDT 24 Jul 28 04:50:13 PM PDT 24 336638910000 ps
T76 /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.1621564691 Jul 28 04:21:04 PM PDT 24 Jul 28 04:49:04 PM PDT 24 336697270000 ps
T77 /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.3111553831 Jul 28 04:20:49 PM PDT 24 Jul 28 04:55:25 PM PDT 24 336786030000 ps
T78 /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.1403915867 Jul 28 04:21:25 PM PDT 24 Jul 28 04:53:35 PM PDT 24 336410130000 ps
T79 /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.4130052776 Jul 28 04:20:14 PM PDT 24 Jul 28 04:53:16 PM PDT 24 336405370000 ps
T80 /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.3278204339 Jul 28 04:20:45 PM PDT 24 Jul 28 04:54:16 PM PDT 24 336560050000 ps
T81 /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.2257791395 Jul 28 04:21:08 PM PDT 24 Jul 28 04:53:46 PM PDT 24 337013990000 ps
T82 /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.535683299 Jul 28 04:25:31 PM PDT 24 Jul 28 04:51:34 PM PDT 24 336887430000 ps
T83 /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.3168985387 Jul 28 04:24:52 PM PDT 24 Jul 28 04:51:51 PM PDT 24 336506210000 ps
T84 /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.2452757328 Jul 28 04:21:23 PM PDT 24 Jul 28 04:56:47 PM PDT 24 337071830000 ps
T85 /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.3203165462 Jul 28 04:21:24 PM PDT 24 Jul 28 04:56:52 PM PDT 24 336438170000 ps
T86 /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.762099005 Jul 28 04:21:28 PM PDT 24 Jul 28 04:55:04 PM PDT 24 336734810000 ps
T87 /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.4115811081 Jul 28 04:21:25 PM PDT 24 Jul 28 04:53:05 PM PDT 24 336670290000 ps
T88 /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.418284987 Jul 28 04:21:07 PM PDT 24 Jul 28 04:52:45 PM PDT 24 336818910000 ps
T89 /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.307090875 Jul 28 04:20:27 PM PDT 24 Jul 28 04:51:37 PM PDT 24 336870930000 ps
T90 /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.3558778283 Jul 28 04:24:57 PM PDT 24 Jul 28 04:49:10 PM PDT 24 336823750000 ps
T91 /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.1829189334 Jul 28 04:24:55 PM PDT 24 Jul 28 04:53:31 PM PDT 24 336633690000 ps
T92 /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.2957786352 Jul 28 04:20:28 PM PDT 24 Jul 28 04:48:44 PM PDT 24 336975010000 ps
T93 /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.3634225298 Jul 28 04:25:15 PM PDT 24 Jul 28 04:53:30 PM PDT 24 336796150000 ps
T94 /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.381213271 Jul 28 04:25:15 PM PDT 24 Jul 28 04:50:20 PM PDT 24 336846570000 ps
T95 /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.432757014 Jul 28 04:22:13 PM PDT 24 Jul 28 04:52:00 PM PDT 24 336536950000 ps
T96 /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.4272153785 Jul 28 04:23:45 PM PDT 24 Jul 28 04:59:58 PM PDT 24 336687670000 ps
T97 /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.3471835742 Jul 28 04:21:25 PM PDT 24 Jul 28 04:53:21 PM PDT 24 336958010000 ps
T98 /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.308538544 Jul 28 04:21:49 PM PDT 24 Jul 28 04:57:34 PM PDT 24 336981950000 ps
T99 /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.3319701791 Jul 28 04:21:15 PM PDT 24 Jul 28 04:57:20 PM PDT 24 336441450000 ps
T100 /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.1412109432 Jul 28 04:24:57 PM PDT 24 Jul 28 04:52:47 PM PDT 24 336942550000 ps
T101 /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.3238495976 Jul 28 04:20:58 PM PDT 24 Jul 28 04:51:50 PM PDT 24 336570330000 ps
T102 /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.1019296843 Jul 28 04:25:46 PM PDT 24 Jul 28 04:50:04 PM PDT 24 336443370000 ps
T103 /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.1345251837 Jul 28 04:23:24 PM PDT 24 Jul 28 04:59:34 PM PDT 24 336579710000 ps
T104 /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.3813927397 Jul 28 04:24:52 PM PDT 24 Jul 28 04:51:47 PM PDT 24 336323890000 ps
T105 /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.1518819725 Jul 28 04:21:14 PM PDT 24 Jul 28 04:49:35 PM PDT 24 336406430000 ps
T106 /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.3874430223 Jul 28 04:20:31 PM PDT 24 Jul 28 04:51:29 PM PDT 24 337147650000 ps
T107 /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.126739884 Jul 28 04:24:51 PM PDT 24 Jul 28 04:53:02 PM PDT 24 336622930000 ps
T108 /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.955067815 Jul 28 04:21:21 PM PDT 24 Jul 28 04:54:16 PM PDT 24 336299510000 ps
T109 /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.2904474227 Jul 28 04:20:25 PM PDT 24 Jul 28 04:47:56 PM PDT 24 336701050000 ps
T110 /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.1428102081 Jul 28 04:24:50 PM PDT 24 Jul 28 04:53:23 PM PDT 24 336434970000 ps
T111 /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.3920149797 Jul 28 04:24:58 PM PDT 24 Jul 28 04:25:07 PM PDT 24 1499950000 ps
T112 /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.3595227014 Jul 28 04:25:10 PM PDT 24 Jul 28 04:25:22 PM PDT 24 1467670000 ps
T113 /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.2200227166 Jul 28 04:22:58 PM PDT 24 Jul 28 04:23:08 PM PDT 24 1417070000 ps
T114 /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.4040425628 Jul 28 04:25:05 PM PDT 24 Jul 28 04:25:17 PM PDT 24 1555430000 ps
T115 /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.840476829 Jul 28 04:24:58 PM PDT 24 Jul 28 04:25:08 PM PDT 24 1417610000 ps
T116 /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.159677567 Jul 28 04:21:29 PM PDT 24 Jul 28 04:21:41 PM PDT 24 1557950000 ps
T117 /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.11264587 Jul 28 04:24:52 PM PDT 24 Jul 28 04:25:03 PM PDT 24 1427850000 ps
T118 /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.1665615558 Jul 28 04:22:31 PM PDT 24 Jul 28 04:22:42 PM PDT 24 1448090000 ps
T119 /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.2884671138 Jul 28 04:21:58 PM PDT 24 Jul 28 04:22:08 PM PDT 24 1463070000 ps
T120 /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.151603485 Jul 28 04:25:11 PM PDT 24 Jul 28 04:25:17 PM PDT 24 1221630000 ps
T121 /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.3272952081 Jul 28 04:24:52 PM PDT 24 Jul 28 04:25:03 PM PDT 24 1591910000 ps
T122 /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.2693621712 Jul 28 04:21:29 PM PDT 24 Jul 28 04:21:40 PM PDT 24 1393870000 ps
T123 /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.2331796833 Jul 28 04:21:51 PM PDT 24 Jul 28 04:22:01 PM PDT 24 1527970000 ps
T124 /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.2338201620 Jul 28 04:22:07 PM PDT 24 Jul 28 04:22:18 PM PDT 24 1620610000 ps
T125 /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.3356252682 Jul 28 04:21:19 PM PDT 24 Jul 28 04:21:28 PM PDT 24 1464070000 ps
T126 /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.1055862401 Jul 28 04:21:17 PM PDT 24 Jul 28 04:21:27 PM PDT 24 1377150000 ps
T127 /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.4205289129 Jul 28 04:24:52 PM PDT 24 Jul 28 04:25:03 PM PDT 24 1431530000 ps
T128 /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.868390660 Jul 28 04:25:38 PM PDT 24 Jul 28 04:25:46 PM PDT 24 1403230000 ps
T129 /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.739198262 Jul 28 04:23:35 PM PDT 24 Jul 28 04:23:45 PM PDT 24 1463570000 ps
T130 /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.2243367214 Jul 28 04:24:47 PM PDT 24 Jul 28 04:24:56 PM PDT 24 1456670000 ps
T131 /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.1769608384 Jul 28 04:20:27 PM PDT 24 Jul 28 04:20:34 PM PDT 24 1221830000 ps
T132 /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.3707635355 Jul 28 04:24:52 PM PDT 24 Jul 28 04:25:04 PM PDT 24 1545030000 ps
T133 /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.1770791588 Jul 28 04:21:55 PM PDT 24 Jul 28 04:22:08 PM PDT 24 1492110000 ps
T134 /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.3066109957 Jul 28 04:25:21 PM PDT 24 Jul 28 04:25:29 PM PDT 24 1227890000 ps
T135 /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.910595431 Jul 28 04:25:02 PM PDT 24 Jul 28 04:25:12 PM PDT 24 1571770000 ps
T136 /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.561710440 Jul 28 04:24:50 PM PDT 24 Jul 28 04:25:02 PM PDT 24 1580650000 ps
T137 /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.2595768505 Jul 28 04:21:50 PM PDT 24 Jul 28 04:21:58 PM PDT 24 1530950000 ps
T138 /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.4097281310 Jul 28 04:20:15 PM PDT 24 Jul 28 04:20:23 PM PDT 24 1458570000 ps
T139 /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.3482646586 Jul 28 04:22:10 PM PDT 24 Jul 28 04:22:20 PM PDT 24 1469710000 ps
T140 /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.3351637110 Jul 28 04:20:27 PM PDT 24 Jul 28 04:20:36 PM PDT 24 1387010000 ps
T141 /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.668856563 Jul 28 04:24:55 PM PDT 24 Jul 28 04:25:02 PM PDT 24 1492010000 ps
T142 /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.3637461686 Jul 28 04:24:37 PM PDT 24 Jul 28 04:24:44 PM PDT 24 1400910000 ps
T143 /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.3002982515 Jul 28 04:22:20 PM PDT 24 Jul 28 04:22:31 PM PDT 24 1378510000 ps
T144 /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.759551631 Jul 28 04:23:26 PM PDT 24 Jul 28 04:23:34 PM PDT 24 1485910000 ps
T145 /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.1424095402 Jul 28 04:21:29 PM PDT 24 Jul 28 04:21:39 PM PDT 24 1281790000 ps
T146 /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.287219836 Jul 28 04:21:57 PM PDT 24 Jul 28 04:22:06 PM PDT 24 1514030000 ps
T147 /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.4193338667 Jul 28 04:23:14 PM PDT 24 Jul 28 04:23:25 PM PDT 24 1433550000 ps
T148 /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.296711340 Jul 28 04:24:48 PM PDT 24 Jul 28 04:24:57 PM PDT 24 1519210000 ps
T149 /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.4203379646 Jul 28 04:25:02 PM PDT 24 Jul 28 04:25:10 PM PDT 24 1550290000 ps
T150 /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.3270263863 Jul 28 04:21:06 PM PDT 24 Jul 28 04:21:16 PM PDT 24 1561930000 ps
T151 /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.303875380 Jul 28 04:21:08 PM PDT 24 Jul 28 04:21:19 PM PDT 24 1510310000 ps
T152 /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.2244751996 Jul 28 04:21:19 PM PDT 24 Jul 28 04:21:28 PM PDT 24 1504630000 ps
T153 /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3911573974 Jul 28 04:22:29 PM PDT 24 Jul 28 04:22:39 PM PDT 24 1398510000 ps
T154 /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.663108383 Jul 28 04:21:20 PM PDT 24 Jul 28 04:21:28 PM PDT 24 1209970000 ps
T155 /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.2177019612 Jul 28 04:21:09 PM PDT 24 Jul 28 04:21:18 PM PDT 24 1383450000 ps
T156 /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.2330095915 Jul 28 04:22:05 PM PDT 24 Jul 28 04:22:15 PM PDT 24 1428150000 ps
T157 /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.4119082283 Jul 28 04:21:14 PM PDT 24 Jul 28 04:21:22 PM PDT 24 1517990000 ps
T158 /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.3587177252 Jul 28 04:21:03 PM PDT 24 Jul 28 04:21:12 PM PDT 24 1601590000 ps
T159 /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.255436320 Jul 28 04:23:25 PM PDT 24 Jul 28 04:23:34 PM PDT 24 1565170000 ps
T160 /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.1112971535 Jul 28 04:22:06 PM PDT 24 Jul 28 04:22:18 PM PDT 24 1651110000 ps
T21 /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.2248192417 Jul 28 04:20:29 PM PDT 24 Jul 28 04:48:35 PM PDT 24 336619890000 ps
T22 /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.846673750 Jul 28 04:24:48 PM PDT 24 Jul 28 04:51:57 PM PDT 24 336320230000 ps
T23 /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.3140647842 Jul 28 04:20:15 PM PDT 24 Jul 28 04:48:07 PM PDT 24 336993450000 ps
T24 /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.3134000828 Jul 28 04:22:20 PM PDT 24 Jul 28 05:00:25 PM PDT 24 336436850000 ps
T25 /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.3938024426 Jul 28 04:21:18 PM PDT 24 Jul 28 04:52:42 PM PDT 24 336327130000 ps
T26 /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.1761136939 Jul 28 04:24:56 PM PDT 24 Jul 28 04:53:39 PM PDT 24 336657030000 ps
T27 /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.2562294812 Jul 28 04:23:13 PM PDT 24 Jul 28 04:52:57 PM PDT 24 336426310000 ps
T28 /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.2271893612 Jul 28 04:23:09 PM PDT 24 Jul 28 05:01:03 PM PDT 24 336521710000 ps
T29 /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.2957283341 Jul 28 04:22:12 PM PDT 24 Jul 28 04:53:29 PM PDT 24 336578970000 ps
T30 /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.664055400 Jul 28 04:22:19 PM PDT 24 Jul 28 04:59:51 PM PDT 24 336673030000 ps
T161 /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.693787829 Jul 28 04:25:35 PM PDT 24 Jul 28 04:56:37 PM PDT 24 336370250000 ps
T162 /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.1034215477 Jul 28 04:22:09 PM PDT 24 Jul 28 04:52:01 PM PDT 24 336477330000 ps
T163 /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.88625874 Jul 28 04:20:16 PM PDT 24 Jul 28 04:51:39 PM PDT 24 336554350000 ps
T164 /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.2133079529 Jul 28 04:25:03 PM PDT 24 Jul 28 04:56:53 PM PDT 24 337026130000 ps
T165 /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.644250955 Jul 28 04:23:28 PM PDT 24 Jul 28 04:56:00 PM PDT 24 337100290000 ps
T166 /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.3685648336 Jul 28 04:20:24 PM PDT 24 Jul 28 04:52:03 PM PDT 24 336730570000 ps
T167 /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.215073904 Jul 28 04:24:56 PM PDT 24 Jul 28 04:53:12 PM PDT 24 336537890000 ps
T168 /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.2440344557 Jul 28 04:24:48 PM PDT 24 Jul 28 04:52:30 PM PDT 24 337038710000 ps
T169 /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.2631894804 Jul 28 04:22:30 PM PDT 24 Jul 28 04:53:36 PM PDT 24 336373510000 ps
T170 /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.33804861 Jul 28 04:21:17 PM PDT 24 Jul 28 04:52:53 PM PDT 24 337103350000 ps
T171 /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.1631017303 Jul 28 04:23:23 PM PDT 24 Jul 28 04:52:22 PM PDT 24 336936010000 ps
T172 /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.4192369330 Jul 28 04:25:36 PM PDT 24 Jul 28 04:50:54 PM PDT 24 336381870000 ps
T173 /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.4055040127 Jul 28 04:25:38 PM PDT 24 Jul 28 04:55:08 PM PDT 24 336490490000 ps
T174 /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.1948997351 Jul 28 04:21:45 PM PDT 24 Jul 28 04:58:23 PM PDT 24 336396110000 ps
T175 /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.2464722716 Jul 28 04:23:28 PM PDT 24 Jul 28 05:01:21 PM PDT 24 336544010000 ps
T176 /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.820062233 Jul 28 04:24:50 PM PDT 24 Jul 28 04:56:42 PM PDT 24 336604930000 ps
T177 /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.1424466537 Jul 28 04:25:05 PM PDT 24 Jul 28 04:58:25 PM PDT 24 336611190000 ps
T178 /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.3806186537 Jul 28 04:25:41 PM PDT 24 Jul 28 04:52:31 PM PDT 24 337024210000 ps
T179 /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.977839640 Jul 28 04:23:06 PM PDT 24 Jul 28 04:52:48 PM PDT 24 337062950000 ps
T180 /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.958967376 Jul 28 04:22:29 PM PDT 24 Jul 28 04:50:36 PM PDT 24 336899990000 ps
T181 /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.1216521585 Jul 28 04:22:22 PM PDT 24 Jul 28 04:57:05 PM PDT 24 336511510000 ps
T182 /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.1000607323 Jul 28 04:22:17 PM PDT 24 Jul 28 04:59:15 PM PDT 24 336853290000 ps
T183 /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.3895998197 Jul 28 04:24:50 PM PDT 24 Jul 28 04:56:50 PM PDT 24 336381210000 ps
T184 /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.365229355 Jul 28 04:25:33 PM PDT 24 Jul 28 04:55:02 PM PDT 24 336676050000 ps
T185 /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.1664282980 Jul 28 04:25:10 PM PDT 24 Jul 28 04:56:12 PM PDT 24 336530590000 ps
T186 /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.260903890 Jul 28 04:21:55 PM PDT 24 Jul 28 04:54:31 PM PDT 24 337071770000 ps
T187 /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.659446478 Jul 28 04:24:50 PM PDT 24 Jul 28 04:57:09 PM PDT 24 336817570000 ps
T188 /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.2194433721 Jul 28 04:21:03 PM PDT 24 Jul 28 04:54:29 PM PDT 24 336534190000 ps
T189 /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.3854461743 Jul 28 04:21:16 PM PDT 24 Jul 28 04:58:22 PM PDT 24 336427310000 ps
T190 /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.2745917567 Jul 28 04:25:10 PM PDT 24 Jul 28 04:55:53 PM PDT 24 336881930000 ps
T191 /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.558604679 Jul 28 04:22:11 PM PDT 24 Jul 28 04:58:41 PM PDT 24 337105490000 ps
T192 /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.3476408719 Jul 28 04:25:10 PM PDT 24 Jul 28 04:55:43 PM PDT 24 336689370000 ps
T193 /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.77233421 Jul 28 04:22:09 PM PDT 24 Jul 28 04:51:43 PM PDT 24 336975830000 ps
T194 /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.1956699488 Jul 28 04:22:17 PM PDT 24 Jul 28 04:53:01 PM PDT 24 336878870000 ps
T195 /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.2598747938 Jul 28 04:22:22 PM PDT 24 Jul 28 04:58:44 PM PDT 24 337093270000 ps
T196 /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.263473959 Jul 28 04:21:08 PM PDT 24 Jul 28 04:53:04 PM PDT 24 336848730000 ps
T197 /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.632689983 Jul 28 04:25:03 PM PDT 24 Jul 28 04:56:47 PM PDT 24 336528670000 ps
T198 /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.4222820094 Jul 28 04:25:08 PM PDT 24 Jul 28 04:56:26 PM PDT 24 336991070000 ps
T199 /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.323271151 Jul 28 04:22:25 PM PDT 24 Jul 28 04:58:54 PM PDT 24 336328270000 ps
T200 /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.810435564 Jul 28 04:25:22 PM PDT 24 Jul 28 04:54:08 PM PDT 24 336947110000 ps

Test location /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.1629304674
Short name T7
Test name
Test status
Simulation time 1609550000 ps
CPU time 5.28 seconds
Started Jul 28 04:19:30 PM PDT 24
Finished Jul 28 04:19:42 PM PDT 24
Peak memory 164304 kb
Host smart-6a228938-ba1b-410b-88bf-68e2da2527c9
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1629304674 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.1629304674
Directory /workspace/13.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.3310047907
Short name T19
Test name
Test status
Simulation time 336989370000 ps
CPU time 707.04 seconds
Started Jul 28 04:21:24 PM PDT 24
Finished Jul 28 04:50:38 PM PDT 24
Peak memory 160600 kb
Host smart-346917d9-fc39-476a-8cef-9b801d63fe47
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3310047907 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.3310047907
Directory /workspace/16.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.3938024426
Short name T25
Test name
Test status
Simulation time 336327130000 ps
CPU time 755.34 seconds
Started Jul 28 04:21:18 PM PDT 24
Finished Jul 28 04:52:42 PM PDT 24
Peak memory 160276 kb
Host smart-9aa83ec3-b030-4b6a-b925-3b878658caed
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3938024426 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.3938024426
Directory /workspace/2.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.2257791395
Short name T81
Test name
Test status
Simulation time 337013990000 ps
CPU time 789.51 seconds
Started Jul 28 04:21:08 PM PDT 24
Finished Jul 28 04:53:46 PM PDT 24
Peak memory 160652 kb
Host smart-b98da0f2-5ba1-422d-987a-9302779506bb
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2257791395 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.2257791395
Directory /workspace/0.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.381213271
Short name T94
Test name
Test status
Simulation time 336846570000 ps
CPU time 598.61 seconds
Started Jul 28 04:25:15 PM PDT 24
Finished Jul 28 04:50:20 PM PDT 24
Peak memory 160604 kb
Host smart-5b2f9463-b68a-4ad5-bc82-0b74e403769f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=381213271 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.381213271
Directory /workspace/1.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.3278204339
Short name T80
Test name
Test status
Simulation time 336560050000 ps
CPU time 817.14 seconds
Started Jul 28 04:20:45 PM PDT 24
Finished Jul 28 04:54:16 PM PDT 24
Peak memory 160648 kb
Host smart-de42780f-17d1-40b2-a6cc-28705ae39bdb
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3278204339 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.3278204339
Directory /workspace/10.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.1518819725
Short name T105
Test name
Test status
Simulation time 336406430000 ps
CPU time 695.23 seconds
Started Jul 28 04:21:14 PM PDT 24
Finished Jul 28 04:49:35 PM PDT 24
Peak memory 159416 kb
Host smart-e5475352-e72b-44f6-a442-454a8bb374d8
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1518819725 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.1518819725
Directory /workspace/11.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.3203165462
Short name T85
Test name
Test status
Simulation time 336438170000 ps
CPU time 834.27 seconds
Started Jul 28 04:21:24 PM PDT 24
Finished Jul 28 04:56:52 PM PDT 24
Peak memory 160428 kb
Host smart-7a245fb4-33f9-4b3a-a537-f7fffdf3b825
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3203165462 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.3203165462
Directory /workspace/12.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.2452757328
Short name T84
Test name
Test status
Simulation time 337071830000 ps
CPU time 832.91 seconds
Started Jul 28 04:21:23 PM PDT 24
Finished Jul 28 04:56:47 PM PDT 24
Peak memory 160428 kb
Host smart-43a12502-fc20-40a7-848e-4dfc18462bc4
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2452757328 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.2452757328
Directory /workspace/13.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.1403915867
Short name T78
Test name
Test status
Simulation time 336410130000 ps
CPU time 760.44 seconds
Started Jul 28 04:21:25 PM PDT 24
Finished Jul 28 04:53:35 PM PDT 24
Peak memory 160412 kb
Host smart-af294a18-2587-436a-b9e4-259148d44e62
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1403915867 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.1403915867
Directory /workspace/14.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.3471835742
Short name T97
Test name
Test status
Simulation time 336958010000 ps
CPU time 753.37 seconds
Started Jul 28 04:21:25 PM PDT 24
Finished Jul 28 04:53:21 PM PDT 24
Peak memory 160380 kb
Host smart-8dd4a9d4-e43b-4812-903a-16c6e1d6b540
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3471835742 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.3471835742
Directory /workspace/15.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.4257856332
Short name T16
Test name
Test status
Simulation time 336956850000 ps
CPU time 750.54 seconds
Started Jul 28 04:21:15 PM PDT 24
Finished Jul 28 04:53:11 PM PDT 24
Peak memory 159396 kb
Host smart-e7cb9377-84b3-40a6-893c-783a8497cfb7
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4257856332 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.4257856332
Directory /workspace/17.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.418284987
Short name T88
Test name
Test status
Simulation time 336818910000 ps
CPU time 777.2 seconds
Started Jul 28 04:21:07 PM PDT 24
Finished Jul 28 04:52:45 PM PDT 24
Peak memory 160704 kb
Host smart-2aac7a5b-96dd-46c1-86b7-e1a83fcf3c41
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=418284987 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.418284987
Directory /workspace/18.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.1868052296
Short name T73
Test name
Test status
Simulation time 336351050000 ps
CPU time 553.08 seconds
Started Jul 28 04:20:08 PM PDT 24
Finished Jul 28 04:43:55 PM PDT 24
Peak memory 160908 kb
Host smart-9244e76e-b237-48c0-98c5-06cf2fe6b622
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1868052296 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.1868052296
Directory /workspace/19.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.944842544
Short name T6
Test name
Test status
Simulation time 336847790000 ps
CPU time 665.57 seconds
Started Jul 28 04:25:17 PM PDT 24
Finished Jul 28 04:52:31 PM PDT 24
Peak memory 160436 kb
Host smart-4309d812-7bb9-448c-9000-a75597bddc57
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=944842544 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.944842544
Directory /workspace/2.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.3558778283
Short name T90
Test name
Test status
Simulation time 336823750000 ps
CPU time 588.7 seconds
Started Jul 28 04:24:57 PM PDT 24
Finished Jul 28 04:49:10 PM PDT 24
Peak memory 160396 kb
Host smart-7ab0ce35-1564-4a60-ba2c-28967de51aa0
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3558778283 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.3558778283
Directory /workspace/20.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.3168985387
Short name T83
Test name
Test status
Simulation time 336506210000 ps
CPU time 654.22 seconds
Started Jul 28 04:24:52 PM PDT 24
Finished Jul 28 04:51:51 PM PDT 24
Peak memory 158748 kb
Host smart-94b635e7-d2e9-41a8-9b89-38d63e5b7e40
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3168985387 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.3168985387
Directory /workspace/21.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.3634225298
Short name T93
Test name
Test status
Simulation time 336796150000 ps
CPU time 691.65 seconds
Started Jul 28 04:25:15 PM PDT 24
Finished Jul 28 04:53:30 PM PDT 24
Peak memory 160636 kb
Host smart-2040cd19-28b7-498f-9f57-8c1f459d80b0
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3634225298 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.3634225298
Directory /workspace/22.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.3813927397
Short name T104
Test name
Test status
Simulation time 336323890000 ps
CPU time 651.3 seconds
Started Jul 28 04:24:52 PM PDT 24
Finished Jul 28 04:51:47 PM PDT 24
Peak memory 158828 kb
Host smart-ed5dda0f-47df-474a-9cac-4f96f6e4a52f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3813927397 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.3813927397
Directory /workspace/23.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.3107450494
Short name T15
Test name
Test status
Simulation time 337028070000 ps
CPU time 881.95 seconds
Started Jul 28 04:21:04 PM PDT 24
Finished Jul 28 04:56:24 PM PDT 24
Peak memory 160672 kb
Host smart-fff7b60d-35d2-4413-9684-d82f2ee9158e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3107450494 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.3107450494
Directory /workspace/24.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.4272153785
Short name T96
Test name
Test status
Simulation time 336687670000 ps
CPU time 878.57 seconds
Started Jul 28 04:23:45 PM PDT 24
Finished Jul 28 04:59:58 PM PDT 24
Peak memory 160668 kb
Host smart-f8914e9f-adf5-4747-b073-5867417a4944
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4272153785 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.4272153785
Directory /workspace/25.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.2957786352
Short name T92
Test name
Test status
Simulation time 336975010000 ps
CPU time 688.71 seconds
Started Jul 28 04:20:28 PM PDT 24
Finished Jul 28 04:48:44 PM PDT 24
Peak memory 160684 kb
Host smart-707c9388-3053-49c8-9c9c-57770a19ae7e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2957786352 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.2957786352
Directory /workspace/26.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.4005609141
Short name T18
Test name
Test status
Simulation time 336843350000 ps
CPU time 678.71 seconds
Started Jul 28 04:22:31 PM PDT 24
Finished Jul 28 04:50:20 PM PDT 24
Peak memory 160648 kb
Host smart-1adbc052-cda2-43b1-8b28-dcfc9662e573
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4005609141 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.4005609141
Directory /workspace/27.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.3774325789
Short name T71
Test name
Test status
Simulation time 336694230000 ps
CPU time 800.31 seconds
Started Jul 28 04:25:03 PM PDT 24
Finished Jul 28 04:57:49 PM PDT 24
Peak memory 160732 kb
Host smart-d5bea54f-471b-48e7-ac6b-9782e9553466
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3774325789 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.3774325789
Directory /workspace/28.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.1428102081
Short name T110
Test name
Test status
Simulation time 336434970000 ps
CPU time 683.13 seconds
Started Jul 28 04:24:50 PM PDT 24
Finished Jul 28 04:53:23 PM PDT 24
Peak memory 160476 kb
Host smart-42e1ceaa-3ed0-4206-9b8d-31715f7764b1
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1428102081 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.1428102081
Directory /workspace/29.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.1955840873
Short name T5
Test name
Test status
Simulation time 337003110000 ps
CPU time 822.67 seconds
Started Jul 28 04:21:24 PM PDT 24
Finished Jul 28 04:56:43 PM PDT 24
Peak memory 160424 kb
Host smart-69e6a3a2-19fa-4da6-9d03-49f240b06d45
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1955840873 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.1955840873
Directory /workspace/3.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.1757916160
Short name T14
Test name
Test status
Simulation time 336376670000 ps
CPU time 787.44 seconds
Started Jul 28 04:25:03 PM PDT 24
Finished Jul 28 04:57:23 PM PDT 24
Peak memory 160732 kb
Host smart-6e910949-4b2c-47e1-adea-ceb9c404705b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1757916160 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.1757916160
Directory /workspace/30.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.955067815
Short name T108
Test name
Test status
Simulation time 336299510000 ps
CPU time 800.44 seconds
Started Jul 28 04:21:21 PM PDT 24
Finished Jul 28 04:54:16 PM PDT 24
Peak memory 160644 kb
Host smart-b72ef9d4-8867-48d0-829c-814ae42971d5
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=955067815 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.955067815
Directory /workspace/31.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.1019296843
Short name T102
Test name
Test status
Simulation time 336443370000 ps
CPU time 594.59 seconds
Started Jul 28 04:25:46 PM PDT 24
Finished Jul 28 04:50:04 PM PDT 24
Peak memory 160440 kb
Host smart-074e701a-6372-464d-ab0c-e5fa6934b4ab
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1019296843 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.1019296843
Directory /workspace/32.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.3446985578
Short name T4
Test name
Test status
Simulation time 337113410000 ps
CPU time 665.79 seconds
Started Jul 28 04:24:57 PM PDT 24
Finished Jul 28 04:52:32 PM PDT 24
Peak memory 160340 kb
Host smart-ec99991b-e290-4356-92f2-97c04dd87ec6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3446985578 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.3446985578
Directory /workspace/33.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.1412109432
Short name T100
Test name
Test status
Simulation time 336942550000 ps
CPU time 675.76 seconds
Started Jul 28 04:24:57 PM PDT 24
Finished Jul 28 04:52:47 PM PDT 24
Peak memory 160340 kb
Host smart-769d0911-104a-4e4c-b61c-2e93c5c257d1
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1412109432 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.1412109432
Directory /workspace/34.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.2904474227
Short name T109
Test name
Test status
Simulation time 336701050000 ps
CPU time 676.24 seconds
Started Jul 28 04:20:25 PM PDT 24
Finished Jul 28 04:47:56 PM PDT 24
Peak memory 160680 kb
Host smart-dd8886a6-cf54-447e-aa21-0c537b14f1a2
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2904474227 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.2904474227
Directory /workspace/35.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.307090875
Short name T89
Test name
Test status
Simulation time 336870930000 ps
CPU time 769.93 seconds
Started Jul 28 04:20:27 PM PDT 24
Finished Jul 28 04:51:37 PM PDT 24
Peak memory 160644 kb
Host smart-9b4d6b40-063c-435a-b998-bf8b07598500
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=307090875 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.307090875
Directory /workspace/36.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.535683299
Short name T82
Test name
Test status
Simulation time 336887430000 ps
CPU time 639.81 seconds
Started Jul 28 04:25:31 PM PDT 24
Finished Jul 28 04:51:34 PM PDT 24
Peak memory 160452 kb
Host smart-3f3a8f55-d8ba-409b-aebb-0e8b5ad42892
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=535683299 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.535683299
Directory /workspace/37.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.432757014
Short name T95
Test name
Test status
Simulation time 336536950000 ps
CPU time 722.93 seconds
Started Jul 28 04:22:13 PM PDT 24
Finished Jul 28 04:52:00 PM PDT 24
Peak memory 160572 kb
Host smart-5c3fc806-e437-4092-ba71-f04ee907cb13
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=432757014 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.432757014
Directory /workspace/38.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.1621564691
Short name T76
Test name
Test status
Simulation time 336697270000 ps
CPU time 685.64 seconds
Started Jul 28 04:21:04 PM PDT 24
Finished Jul 28 04:49:04 PM PDT 24
Peak memory 160644 kb
Host smart-e2056bbb-7ec6-42e0-a43d-5f3bfdbe04ba
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1621564691 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.1621564691
Directory /workspace/39.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.4115811081
Short name T87
Test name
Test status
Simulation time 336670290000 ps
CPU time 747.11 seconds
Started Jul 28 04:21:25 PM PDT 24
Finished Jul 28 04:53:05 PM PDT 24
Peak memory 160400 kb
Host smart-9d350a09-6cda-4fe6-8bb0-eb7bd4800447
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4115811081 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.4115811081
Directory /workspace/4.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.1721375805
Short name T20
Test name
Test status
Simulation time 336950690000 ps
CPU time 698.42 seconds
Started Jul 28 04:24:50 PM PDT 24
Finished Jul 28 04:53:34 PM PDT 24
Peak memory 159564 kb
Host smart-cc2d39be-0a36-4e7b-aada-9d5e89f828dc
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1721375805 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.1721375805
Directory /workspace/40.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.3169163381
Short name T17
Test name
Test status
Simulation time 336508190000 ps
CPU time 768.34 seconds
Started Jul 28 04:22:51 PM PDT 24
Finished Jul 28 04:54:35 PM PDT 24
Peak memory 160648 kb
Host smart-21fb0af2-4fcf-4866-aa94-7ad0b9043d65
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3169163381 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.3169163381
Directory /workspace/41.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.126739884
Short name T107
Test name
Test status
Simulation time 336622930000 ps
CPU time 685.57 seconds
Started Jul 28 04:24:51 PM PDT 24
Finished Jul 28 04:53:02 PM PDT 24
Peak memory 160452 kb
Host smart-628dfbc0-876b-47a9-8f76-9c892f64ed76
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=126739884 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.126739884
Directory /workspace/42.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.308538544
Short name T98
Test name
Test status
Simulation time 336981950000 ps
CPU time 861.94 seconds
Started Jul 28 04:21:49 PM PDT 24
Finished Jul 28 04:57:34 PM PDT 24
Peak memory 160676 kb
Host smart-e01f845a-0e3c-45a1-ab68-5b8ee2a15023
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=308538544 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.308538544
Directory /workspace/43.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.1829189334
Short name T91
Test name
Test status
Simulation time 336633690000 ps
CPU time 699.97 seconds
Started Jul 28 04:24:55 PM PDT 24
Finished Jul 28 04:53:31 PM PDT 24
Peak memory 159372 kb
Host smart-ee7faa49-4f53-4fe2-98ad-7e10e43d2b01
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1829189334 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.1829189334
Directory /workspace/44.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.3874430223
Short name T106
Test name
Test status
Simulation time 337147650000 ps
CPU time 764.65 seconds
Started Jul 28 04:20:31 PM PDT 24
Finished Jul 28 04:51:29 PM PDT 24
Peak memory 160864 kb
Host smart-58468e28-43e0-4c9f-ac5a-d21d18f8c8e7
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3874430223 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.3874430223
Directory /workspace/45.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.762099005
Short name T86
Test name
Test status
Simulation time 336734810000 ps
CPU time 815.94 seconds
Started Jul 28 04:21:28 PM PDT 24
Finished Jul 28 04:55:04 PM PDT 24
Peak memory 160676 kb
Host smart-1295f6df-b59d-4549-816b-05a19fe66f13
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=762099005 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.762099005
Directory /workspace/46.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.3238495976
Short name T101
Test name
Test status
Simulation time 336570330000 ps
CPU time 753.51 seconds
Started Jul 28 04:20:58 PM PDT 24
Finished Jul 28 04:51:50 PM PDT 24
Peak memory 160764 kb
Host smart-8257f934-4fd5-43f2-bf4e-1e4e179dc80c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3238495976 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.3238495976
Directory /workspace/47.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.1345251837
Short name T103
Test name
Test status
Simulation time 336579710000 ps
CPU time 875.83 seconds
Started Jul 28 04:23:24 PM PDT 24
Finished Jul 28 04:59:34 PM PDT 24
Peak memory 160644 kb
Host smart-296bc279-607c-491a-aac0-08eb59b69de5
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1345251837 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.1345251837
Directory /workspace/48.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.1894413350
Short name T75
Test name
Test status
Simulation time 336638910000 ps
CPU time 690.32 seconds
Started Jul 28 04:21:58 PM PDT 24
Finished Jul 28 04:50:13 PM PDT 24
Peak memory 160680 kb
Host smart-94c6a953-b30c-47bd-9b0c-daff3b0d6640
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1894413350 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.1894413350
Directory /workspace/49.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.3111553831
Short name T77
Test name
Test status
Simulation time 336786030000 ps
CPU time 861 seconds
Started Jul 28 04:20:49 PM PDT 24
Finished Jul 28 04:55:25 PM PDT 24
Peak memory 160608 kb
Host smart-a30ffd56-9aa5-427b-8dfc-32a0d45e3541
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3111553831 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.3111553831
Directory /workspace/5.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.4130052776
Short name T79
Test name
Test status
Simulation time 336405370000 ps
CPU time 805.42 seconds
Started Jul 28 04:20:14 PM PDT 24
Finished Jul 28 04:53:16 PM PDT 24
Peak memory 159356 kb
Host smart-e1004365-f625-48ed-a36c-b20b2be455d3
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4130052776 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.4130052776
Directory /workspace/6.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.1514558659
Short name T74
Test name
Test status
Simulation time 336610670000 ps
CPU time 817.04 seconds
Started Jul 28 04:20:14 PM PDT 24
Finished Jul 28 04:53:38 PM PDT 24
Peak memory 159392 kb
Host smart-c43a96b2-ee94-4e04-8649-cfd1f0a3b357
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1514558659 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.1514558659
Directory /workspace/7.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.487933845
Short name T72
Test name
Test status
Simulation time 336399110000 ps
CPU time 849.56 seconds
Started Jul 28 04:21:15 PM PDT 24
Finished Jul 28 04:57:03 PM PDT 24
Peak memory 158872 kb
Host smart-93e5f993-3b68-4694-9741-6eafe2ff90dc
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=487933845 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.487933845
Directory /workspace/8.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.3319701791
Short name T99
Test name
Test status
Simulation time 336441450000 ps
CPU time 859.71 seconds
Started Jul 28 04:21:15 PM PDT 24
Finished Jul 28 04:57:20 PM PDT 24
Peak memory 158824 kb
Host smart-c306222b-bc66-4d81-b106-90f7b4831b36
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3319701791 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.3319701791
Directory /workspace/9.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.33804861
Short name T170
Test name
Test status
Simulation time 337103350000 ps
CPU time 762.99 seconds
Started Jul 28 04:21:17 PM PDT 24
Finished Jul 28 04:52:53 PM PDT 24
Peak memory 159336 kb
Host smart-c3b3275c-3c38-4205-95e1-c2e9bdd27f65
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=33804861 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.33804861
Directory /workspace/0.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.263473959
Short name T196
Test name
Test status
Simulation time 336848730000 ps
CPU time 772.64 seconds
Started Jul 28 04:21:08 PM PDT 24
Finished Jul 28 04:53:04 PM PDT 24
Peak memory 160644 kb
Host smart-647405ae-8354-4ebe-a14c-827ccc155d96
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=263473959 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.263473959
Directory /workspace/1.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.260903890
Short name T186
Test name
Test status
Simulation time 337071770000 ps
CPU time 790.18 seconds
Started Jul 28 04:21:55 PM PDT 24
Finished Jul 28 04:54:31 PM PDT 24
Peak memory 160608 kb
Host smart-bb88b395-b4fd-4087-a7af-f079bdf8d9ee
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=260903890 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.260903890
Directory /workspace/10.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.3685648336
Short name T166
Test name
Test status
Simulation time 336730570000 ps
CPU time 781.53 seconds
Started Jul 28 04:20:24 PM PDT 24
Finished Jul 28 04:52:03 PM PDT 24
Peak memory 160700 kb
Host smart-492fbecd-c3fc-462f-9384-209018182dff
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3685648336 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.3685648336
Directory /workspace/11.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.215073904
Short name T167
Test name
Test status
Simulation time 336537890000 ps
CPU time 686.58 seconds
Started Jul 28 04:24:56 PM PDT 24
Finished Jul 28 04:53:12 PM PDT 24
Peak memory 159792 kb
Host smart-9cec21ed-263b-48bf-bae2-33347c710579
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=215073904 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.215073904
Directory /workspace/12.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.2745917567
Short name T190
Test name
Test status
Simulation time 336881930000 ps
CPU time 750.09 seconds
Started Jul 28 04:25:10 PM PDT 24
Finished Jul 28 04:55:53 PM PDT 24
Peak memory 160624 kb
Host smart-9f7ba30d-d937-4bbc-88c7-eb8104f17db2
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2745917567 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.2745917567
Directory /workspace/13.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.3476408719
Short name T192
Test name
Test status
Simulation time 336689370000 ps
CPU time 743.78 seconds
Started Jul 28 04:25:10 PM PDT 24
Finished Jul 28 04:55:43 PM PDT 24
Peak memory 160624 kb
Host smart-210e3f7a-087f-4341-a1a5-830f3a637d58
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3476408719 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.3476408719
Directory /workspace/14.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.1034215477
Short name T162
Test name
Test status
Simulation time 336477330000 ps
CPU time 738.14 seconds
Started Jul 28 04:22:09 PM PDT 24
Finished Jul 28 04:52:01 PM PDT 24
Peak memory 160612 kb
Host smart-df66c3c6-e671-4340-8f52-8e149dcf2ae4
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1034215477 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.1034215477
Directory /workspace/15.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.365229355
Short name T184
Test name
Test status
Simulation time 336676050000 ps
CPU time 708.17 seconds
Started Jul 28 04:25:33 PM PDT 24
Finished Jul 28 04:55:02 PM PDT 24
Peak memory 160612 kb
Host smart-43dc571b-bbe2-4b27-8faa-b5412ea79a48
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=365229355 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.365229355
Directory /workspace/16.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.1956699488
Short name T194
Test name
Test status
Simulation time 336878870000 ps
CPU time 759.37 seconds
Started Jul 28 04:22:17 PM PDT 24
Finished Jul 28 04:53:01 PM PDT 24
Peak memory 160868 kb
Host smart-b7adc357-7644-4c21-89cb-f3a4bb5e996b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1956699488 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.1956699488
Directory /workspace/17.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.4055040127
Short name T173
Test name
Test status
Simulation time 336490490000 ps
CPU time 712.28 seconds
Started Jul 28 04:25:38 PM PDT 24
Finished Jul 28 04:55:08 PM PDT 24
Peak memory 160528 kb
Host smart-7812184d-51f2-44de-90cd-38038dd5073c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4055040127 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.4055040127
Directory /workspace/18.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.2440344557
Short name T168
Test name
Test status
Simulation time 337038710000 ps
CPU time 672.38 seconds
Started Jul 28 04:24:48 PM PDT 24
Finished Jul 28 04:52:30 PM PDT 24
Peak memory 159300 kb
Host smart-1a500c0f-a95c-423c-9f0e-961fcc9971e3
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2440344557 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.2440344557
Directory /workspace/19.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.664055400
Short name T30
Test name
Test status
Simulation time 336673030000 ps
CPU time 903.47 seconds
Started Jul 28 04:22:19 PM PDT 24
Finished Jul 28 04:59:51 PM PDT 24
Peak memory 160820 kb
Host smart-7dc911d7-58ed-4cdb-ac73-83e22633cbdc
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=664055400 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.664055400
Directory /workspace/20.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.977839640
Short name T179
Test name
Test status
Simulation time 337062950000 ps
CPU time 718.6 seconds
Started Jul 28 04:23:06 PM PDT 24
Finished Jul 28 04:52:48 PM PDT 24
Peak memory 160608 kb
Host smart-6069d457-5863-4990-91d7-e39d7527d076
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=977839640 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.977839640
Directory /workspace/21.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.2194433721
Short name T188
Test name
Test status
Simulation time 336534190000 ps
CPU time 812.98 seconds
Started Jul 28 04:21:03 PM PDT 24
Finished Jul 28 04:54:29 PM PDT 24
Peak memory 160652 kb
Host smart-7ad518f8-1f5b-46dd-acb6-f863e73c837a
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2194433721 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.2194433721
Directory /workspace/22.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.693787829
Short name T161
Test name
Test status
Simulation time 336370250000 ps
CPU time 757.02 seconds
Started Jul 28 04:25:35 PM PDT 24
Finished Jul 28 04:56:37 PM PDT 24
Peak memory 160576 kb
Host smart-2b93cb54-a120-4574-bc1d-b1a695e4b4dd
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=693787829 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.693787829
Directory /workspace/23.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.1631017303
Short name T171
Test name
Test status
Simulation time 336936010000 ps
CPU time 700.93 seconds
Started Jul 28 04:23:23 PM PDT 24
Finished Jul 28 04:52:22 PM PDT 24
Peak memory 160632 kb
Host smart-605249ef-928e-46f6-9a97-cac95de85583
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1631017303 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.1631017303
Directory /workspace/24.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.2598747938
Short name T195
Test name
Test status
Simulation time 337093270000 ps
CPU time 877.03 seconds
Started Jul 28 04:22:22 PM PDT 24
Finished Jul 28 04:58:44 PM PDT 24
Peak memory 160680 kb
Host smart-8fc265cc-6792-4900-8e02-671b69168ce2
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2598747938 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.2598747938
Directory /workspace/25.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.1664282980
Short name T185
Test name
Test status
Simulation time 336530590000 ps
CPU time 760.22 seconds
Started Jul 28 04:25:10 PM PDT 24
Finished Jul 28 04:56:12 PM PDT 24
Peak memory 160596 kb
Host smart-7e6f5894-48c5-4464-afb0-e1f4c9cb0cd3
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1664282980 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.1664282980
Directory /workspace/26.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.3895998197
Short name T183
Test name
Test status
Simulation time 336381210000 ps
CPU time 763.85 seconds
Started Jul 28 04:24:50 PM PDT 24
Finished Jul 28 04:56:50 PM PDT 24
Peak memory 158896 kb
Host smart-edae77dd-8a2b-48d6-88b1-0cb6f1c63869
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3895998197 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.3895998197
Directory /workspace/27.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.4222820094
Short name T198
Test name
Test status
Simulation time 336991070000 ps
CPU time 765.93 seconds
Started Jul 28 04:25:08 PM PDT 24
Finished Jul 28 04:56:26 PM PDT 24
Peak memory 160596 kb
Host smart-d0a90495-d86b-4059-a462-c0742d2ffe4f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4222820094 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.4222820094
Directory /workspace/28.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.1000607323
Short name T182
Test name
Test status
Simulation time 336853290000 ps
CPU time 906.46 seconds
Started Jul 28 04:22:17 PM PDT 24
Finished Jul 28 04:59:15 PM PDT 24
Peak memory 160612 kb
Host smart-de1fe2b8-5738-4259-9b96-ebe50194f104
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1000607323 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.1000607323
Directory /workspace/29.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.820062233
Short name T176
Test name
Test status
Simulation time 336604930000 ps
CPU time 747.45 seconds
Started Jul 28 04:24:50 PM PDT 24
Finished Jul 28 04:56:42 PM PDT 24
Peak memory 158656 kb
Host smart-f4a46fb8-4d76-4421-be72-f1c2da15e00c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=820062233 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.820062233
Directory /workspace/3.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.1424466537
Short name T177
Test name
Test status
Simulation time 336611190000 ps
CPU time 803.01 seconds
Started Jul 28 04:25:05 PM PDT 24
Finished Jul 28 04:58:25 PM PDT 24
Peak memory 160604 kb
Host smart-22aa1460-d8cd-4553-8975-c1f27a7c9289
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1424466537 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.1424466537
Directory /workspace/30.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.77233421
Short name T193
Test name
Test status
Simulation time 336975830000 ps
CPU time 728.9 seconds
Started Jul 28 04:22:09 PM PDT 24
Finished Jul 28 04:51:43 PM PDT 24
Peak memory 160584 kb
Host smart-6b6a8061-4f49-432b-ac9c-6f3fc1a03833
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=77233421 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.77233421
Directory /workspace/31.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.846673750
Short name T22
Test name
Test status
Simulation time 336320230000 ps
CPU time 657.8 seconds
Started Jul 28 04:24:48 PM PDT 24
Finished Jul 28 04:51:57 PM PDT 24
Peak memory 159432 kb
Host smart-c057cfd8-86e2-4e06-93b9-8b739fab90ce
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=846673750 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.846673750
Directory /workspace/32.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.1948997351
Short name T174
Test name
Test status
Simulation time 336396110000 ps
CPU time 891.73 seconds
Started Jul 28 04:21:45 PM PDT 24
Finished Jul 28 04:58:23 PM PDT 24
Peak memory 160672 kb
Host smart-d3b8bf34-1f3c-4c5c-bcd6-d6f074108440
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1948997351 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.1948997351
Directory /workspace/33.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.2631894804
Short name T169
Test name
Test status
Simulation time 336373510000 ps
CPU time 762.44 seconds
Started Jul 28 04:22:30 PM PDT 24
Finished Jul 28 04:53:36 PM PDT 24
Peak memory 160688 kb
Host smart-6effb63a-e1fc-4ce7-a4c0-058e61c3cc2a
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2631894804 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.2631894804
Directory /workspace/34.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.88625874
Short name T163
Test name
Test status
Simulation time 336554350000 ps
CPU time 766.44 seconds
Started Jul 28 04:20:16 PM PDT 24
Finished Jul 28 04:51:39 PM PDT 24
Peak memory 160508 kb
Host smart-8fdf4f87-906b-4f0e-a853-c3f57a3926e5
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=88625874 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.88625874
Directory /workspace/35.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.810435564
Short name T200
Test name
Test status
Simulation time 336947110000 ps
CPU time 696.18 seconds
Started Jul 28 04:25:22 PM PDT 24
Finished Jul 28 04:54:08 PM PDT 24
Peak memory 159700 kb
Host smart-9bc5feaf-da6d-46eb-b991-9ee34975512c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=810435564 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.810435564
Directory /workspace/36.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.659446478
Short name T187
Test name
Test status
Simulation time 336817570000 ps
CPU time 764.83 seconds
Started Jul 28 04:24:50 PM PDT 24
Finished Jul 28 04:57:09 PM PDT 24
Peak memory 158824 kb
Host smart-c75741f6-9e6e-451f-9fc9-4a3436a62625
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=659446478 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.659446478
Directory /workspace/37.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.2271893612
Short name T28
Test name
Test status
Simulation time 336521710000 ps
CPU time 915.65 seconds
Started Jul 28 04:23:09 PM PDT 24
Finished Jul 28 05:01:03 PM PDT 24
Peak memory 160840 kb
Host smart-e2694785-578a-4944-9a08-29c3ff2c207f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2271893612 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.2271893612
Directory /workspace/38.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.1761136939
Short name T26
Test name
Test status
Simulation time 336657030000 ps
CPU time 694.96 seconds
Started Jul 28 04:24:56 PM PDT 24
Finished Jul 28 04:53:39 PM PDT 24
Peak memory 159788 kb
Host smart-efbf89b4-ae8b-4ec8-b007-f442219cfb68
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1761136939 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.1761136939
Directory /workspace/39.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.3140647842
Short name T23
Test name
Test status
Simulation time 336993450000 ps
CPU time 677.55 seconds
Started Jul 28 04:20:15 PM PDT 24
Finished Jul 28 04:48:07 PM PDT 24
Peak memory 160584 kb
Host smart-8c8f8cc0-6d97-48f9-baa5-82184302da20
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3140647842 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.3140647842
Directory /workspace/4.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.323271151
Short name T199
Test name
Test status
Simulation time 336328270000 ps
CPU time 884.94 seconds
Started Jul 28 04:22:25 PM PDT 24
Finished Jul 28 04:58:54 PM PDT 24
Peak memory 160672 kb
Host smart-046565e8-ae6d-4d97-a9f9-fcdd0e9445dc
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=323271151 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.323271151
Directory /workspace/40.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.2957283341
Short name T29
Test name
Test status
Simulation time 336578970000 ps
CPU time 735.39 seconds
Started Jul 28 04:22:12 PM PDT 24
Finished Jul 28 04:53:29 PM PDT 24
Peak memory 160608 kb
Host smart-58739fa2-5935-40c7-8016-1d8c22638ccf
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2957283341 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.2957283341
Directory /workspace/41.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.3134000828
Short name T24
Test name
Test status
Simulation time 336436850000 ps
CPU time 916.97 seconds
Started Jul 28 04:22:20 PM PDT 24
Finished Jul 28 05:00:25 PM PDT 24
Peak memory 160856 kb
Host smart-5bdbc3fc-d631-44af-b372-83a40e2a849e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3134000828 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.3134000828
Directory /workspace/42.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.958967376
Short name T180
Test name
Test status
Simulation time 336899990000 ps
CPU time 684.8 seconds
Started Jul 28 04:22:29 PM PDT 24
Finished Jul 28 04:50:36 PM PDT 24
Peak memory 160628 kb
Host smart-46498cad-4bdb-42e5-8741-1fa5fd59fa7e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=958967376 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.958967376
Directory /workspace/43.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.4192369330
Short name T172
Test name
Test status
Simulation time 336381870000 ps
CPU time 615.34 seconds
Started Jul 28 04:25:36 PM PDT 24
Finished Jul 28 04:50:54 PM PDT 24
Peak memory 160468 kb
Host smart-97400f20-8331-4f07-8d95-d7441760cd37
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4192369330 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.4192369330
Directory /workspace/44.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.558604679
Short name T191
Test name
Test status
Simulation time 337105490000 ps
CPU time 878.49 seconds
Started Jul 28 04:22:11 PM PDT 24
Finished Jul 28 04:58:41 PM PDT 24
Peak memory 160680 kb
Host smart-73684137-3ff1-45a9-b53f-c96fd58d810a
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=558604679 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.558604679
Directory /workspace/45.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.2562294812
Short name T27
Test name
Test status
Simulation time 336426310000 ps
CPU time 723.13 seconds
Started Jul 28 04:23:13 PM PDT 24
Finished Jul 28 04:52:57 PM PDT 24
Peak memory 160616 kb
Host smart-ccd517da-c5b1-4940-a07f-5b974c27064b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2562294812 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.2562294812
Directory /workspace/46.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.1216521585
Short name T181
Test name
Test status
Simulation time 336511510000 ps
CPU time 843.93 seconds
Started Jul 28 04:22:22 PM PDT 24
Finished Jul 28 04:57:05 PM PDT 24
Peak memory 160672 kb
Host smart-e05fe7fb-4cfd-4da9-8265-3c877c60c4bd
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1216521585 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.1216521585
Directory /workspace/47.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.3806186537
Short name T178
Test name
Test status
Simulation time 337024210000 ps
CPU time 651.82 seconds
Started Jul 28 04:25:41 PM PDT 24
Finished Jul 28 04:52:31 PM PDT 24
Peak memory 159880 kb
Host smart-63c25159-6ba3-49a2-ac6f-a45b8759edb6
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3806186537 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.3806186537
Directory /workspace/48.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.2248192417
Short name T21
Test name
Test status
Simulation time 336619890000 ps
CPU time 689.02 seconds
Started Jul 28 04:20:29 PM PDT 24
Finished Jul 28 04:48:35 PM PDT 24
Peak memory 160700 kb
Host smart-625fe579-7951-470e-8f70-3140e7af542e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2248192417 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.2248192417
Directory /workspace/49.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.2464722716
Short name T175
Test name
Test status
Simulation time 336544010000 ps
CPU time 914.72 seconds
Started Jul 28 04:23:28 PM PDT 24
Finished Jul 28 05:01:21 PM PDT 24
Peak memory 160832 kb
Host smart-03a3bffc-516d-49d9-ac00-a03dbe403111
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2464722716 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.2464722716
Directory /workspace/5.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.632689983
Short name T197
Test name
Test status
Simulation time 336528670000 ps
CPU time 768.56 seconds
Started Jul 28 04:25:03 PM PDT 24
Finished Jul 28 04:56:47 PM PDT 24
Peak memory 160572 kb
Host smart-c73e6320-3783-4460-85ee-eb77e34ee41c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=632689983 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.632689983
Directory /workspace/6.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.3854461743
Short name T189
Test name
Test status
Simulation time 336427310000 ps
CPU time 904.34 seconds
Started Jul 28 04:21:16 PM PDT 24
Finished Jul 28 04:58:22 PM PDT 24
Peak memory 160832 kb
Host smart-91faac8b-d136-4356-aab4-1da3c43734b8
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3854461743 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.3854461743
Directory /workspace/7.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.2133079529
Short name T164
Test name
Test status
Simulation time 337026130000 ps
CPU time 774.62 seconds
Started Jul 28 04:25:03 PM PDT 24
Finished Jul 28 04:56:53 PM PDT 24
Peak memory 160580 kb
Host smart-cb6bd8f3-0fa2-40ad-a38a-94241e2d3499
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2133079529 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.2133079529
Directory /workspace/8.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.644250955
Short name T165
Test name
Test status
Simulation time 337100290000 ps
CPU time 789.3 seconds
Started Jul 28 04:23:28 PM PDT 24
Finished Jul 28 04:56:00 PM PDT 24
Peak memory 160612 kb
Host smart-ff95ac08-de0e-4576-aeea-f490cda12aca
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=644250955 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.644250955
Directory /workspace/9.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.663108383
Short name T154
Test name
Test status
Simulation time 1209970000 ps
CPU time 3.44 seconds
Started Jul 28 04:21:20 PM PDT 24
Finished Jul 28 04:21:28 PM PDT 24
Peak memory 164344 kb
Host smart-590a5d82-8d4f-427a-8e1b-98a0ac6a1a19
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=663108383 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.663108383
Directory /workspace/0.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.3356252682
Short name T125
Test name
Test status
Simulation time 1464070000 ps
CPU time 4.06 seconds
Started Jul 28 04:21:19 PM PDT 24
Finished Jul 28 04:21:28 PM PDT 24
Peak memory 164244 kb
Host smart-98b431c9-7561-4df5-bcba-3f2bce53cccb
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3356252682 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.3356252682
Directory /workspace/1.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.2177019612
Short name T155
Test name
Test status
Simulation time 1383450000 ps
CPU time 4.23 seconds
Started Jul 28 04:21:09 PM PDT 24
Finished Jul 28 04:21:18 PM PDT 24
Peak memory 164772 kb
Host smart-3f1d636d-36e7-4f02-922a-fb12cc5d255e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2177019612 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.2177019612
Directory /workspace/10.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.4193338667
Short name T147
Test name
Test status
Simulation time 1433550000 ps
CPU time 5 seconds
Started Jul 28 04:23:14 PM PDT 24
Finished Jul 28 04:23:25 PM PDT 24
Peak memory 164736 kb
Host smart-8c2dafd4-7e42-463f-911d-7c5cb394c1e9
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4193338667 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.4193338667
Directory /workspace/11.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.3351637110
Short name T140
Test name
Test status
Simulation time 1387010000 ps
CPU time 3.95 seconds
Started Jul 28 04:20:27 PM PDT 24
Finished Jul 28 04:20:36 PM PDT 24
Peak memory 164768 kb
Host smart-b6c3a99a-7b53-445c-a34b-ed496d5547eb
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3351637110 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.3351637110
Directory /workspace/12.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.287219836
Short name T146
Test name
Test status
Simulation time 1514030000 ps
CPU time 4.24 seconds
Started Jul 28 04:21:57 PM PDT 24
Finished Jul 28 04:22:06 PM PDT 24
Peak memory 164716 kb
Host smart-781018c7-3518-4cdc-9899-7060ea5efb4b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=287219836 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.287219836
Directory /workspace/13.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.2884671138
Short name T119
Test name
Test status
Simulation time 1463070000 ps
CPU time 4.58 seconds
Started Jul 28 04:21:58 PM PDT 24
Finished Jul 28 04:22:08 PM PDT 24
Peak memory 164724 kb
Host smart-385fe39f-739c-4bc6-a30f-c31267a4a4e8
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2884671138 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.2884671138
Directory /workspace/14.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.2595768505
Short name T137
Test name
Test status
Simulation time 1530950000 ps
CPU time 3.41 seconds
Started Jul 28 04:21:50 PM PDT 24
Finished Jul 28 04:21:58 PM PDT 24
Peak memory 164788 kb
Host smart-8eaec561-6c5a-426c-85ab-c19c5861833d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2595768505 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.2595768505
Directory /workspace/15.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.2331796833
Short name T123
Test name
Test status
Simulation time 1527970000 ps
CPU time 4.59 seconds
Started Jul 28 04:21:51 PM PDT 24
Finished Jul 28 04:22:01 PM PDT 24
Peak memory 164896 kb
Host smart-7c2042b8-6eed-41b4-8823-4e393af65a8d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2331796833 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.2331796833
Directory /workspace/16.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.4040425628
Short name T114
Test name
Test status
Simulation time 1555430000 ps
CPU time 5.1 seconds
Started Jul 28 04:25:05 PM PDT 24
Finished Jul 28 04:25:17 PM PDT 24
Peak memory 164676 kb
Host smart-ffb0aca1-fbbb-4a49-ab5b-7e4077942961
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4040425628 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.4040425628
Directory /workspace/17.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.2243367214
Short name T130
Test name
Test status
Simulation time 1456670000 ps
CPU time 3.99 seconds
Started Jul 28 04:24:47 PM PDT 24
Finished Jul 28 04:24:56 PM PDT 24
Peak memory 163176 kb
Host smart-764e1edb-20d1-4bcd-901c-643e8396df1f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2243367214 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.2243367214
Directory /workspace/18.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.3270263863
Short name T150
Test name
Test status
Simulation time 1561930000 ps
CPU time 4.18 seconds
Started Jul 28 04:21:06 PM PDT 24
Finished Jul 28 04:21:16 PM PDT 24
Peak memory 164812 kb
Host smart-d9a05a08-f6fd-412e-8829-de5813f7270d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3270263863 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.3270263863
Directory /workspace/19.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.2244751996
Short name T152
Test name
Test status
Simulation time 1504630000 ps
CPU time 4.2 seconds
Started Jul 28 04:21:19 PM PDT 24
Finished Jul 28 04:21:28 PM PDT 24
Peak memory 163628 kb
Host smart-a136c38f-a057-4015-9da1-9422fbeaf9cc
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2244751996 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.2244751996
Directory /workspace/2.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.4203379646
Short name T149
Test name
Test status
Simulation time 1550290000 ps
CPU time 3.46 seconds
Started Jul 28 04:25:02 PM PDT 24
Finished Jul 28 04:25:10 PM PDT 24
Peak memory 164720 kb
Host smart-0b3e1325-b07f-47bb-b1c1-81318fe96d6d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4203379646 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.4203379646
Directory /workspace/20.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3911573974
Short name T153
Test name
Test status
Simulation time 1398510000 ps
CPU time 4.89 seconds
Started Jul 28 04:22:29 PM PDT 24
Finished Jul 28 04:22:39 PM PDT 24
Peak memory 164896 kb
Host smart-246e7319-e25d-4c34-b0a5-e3714938a577
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3911573974 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.3911573974
Directory /workspace/21.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.1769608384
Short name T131
Test name
Test status
Simulation time 1221830000 ps
CPU time 2.82 seconds
Started Jul 28 04:20:27 PM PDT 24
Finished Jul 28 04:20:34 PM PDT 24
Peak memory 164828 kb
Host smart-f727e026-96aa-4b22-a752-6b1cc3a08fc0
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1769608384 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.1769608384
Directory /workspace/22.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.3587177252
Short name T158
Test name
Test status
Simulation time 1601590000 ps
CPU time 3.93 seconds
Started Jul 28 04:21:03 PM PDT 24
Finished Jul 28 04:21:12 PM PDT 24
Peak memory 164764 kb
Host smart-f7f2eedd-9cb9-49c9-8384-cb75bf609465
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3587177252 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.3587177252
Directory /workspace/23.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.4205289129
Short name T127
Test name
Test status
Simulation time 1431530000 ps
CPU time 4.8 seconds
Started Jul 28 04:24:52 PM PDT 24
Finished Jul 28 04:25:03 PM PDT 24
Peak memory 164520 kb
Host smart-260ab612-43c2-4afe-a3d0-d5fb3ffe543c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4205289129 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.4205289129
Directory /workspace/24.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.151603485
Short name T120
Test name
Test status
Simulation time 1221630000 ps
CPU time 2.83 seconds
Started Jul 28 04:25:11 PM PDT 24
Finished Jul 28 04:25:17 PM PDT 24
Peak memory 164692 kb
Host smart-1daa3d1f-5b94-4c03-98ec-5ac2cf7c3e56
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=151603485 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.151603485
Directory /workspace/25.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.840476829
Short name T115
Test name
Test status
Simulation time 1417610000 ps
CPU time 4.55 seconds
Started Jul 28 04:24:58 PM PDT 24
Finished Jul 28 04:25:08 PM PDT 24
Peak memory 162784 kb
Host smart-91c55889-c0da-40c8-939f-592ba6d6ca0f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=840476829 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.840476829
Directory /workspace/26.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.303875380
Short name T151
Test name
Test status
Simulation time 1510310000 ps
CPU time 4.85 seconds
Started Jul 28 04:21:08 PM PDT 24
Finished Jul 28 04:21:19 PM PDT 24
Peak memory 164724 kb
Host smart-973acd99-57c3-4f2f-b86d-c42d71591c3d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=303875380 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.303875380
Directory /workspace/27.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.910595431
Short name T135
Test name
Test status
Simulation time 1571770000 ps
CPU time 4.22 seconds
Started Jul 28 04:25:02 PM PDT 24
Finished Jul 28 04:25:12 PM PDT 24
Peak memory 164648 kb
Host smart-df477cd0-9562-47db-abf6-a393b9a3ca02
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=910595431 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.910595431
Directory /workspace/28.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.1770791588
Short name T133
Test name
Test status
Simulation time 1492110000 ps
CPU time 5.55 seconds
Started Jul 28 04:21:55 PM PDT 24
Finished Jul 28 04:22:08 PM PDT 24
Peak memory 164828 kb
Host smart-51e7df9f-c48a-4fc1-b80c-db98ecdb04fc
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1770791588 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.1770791588
Directory /workspace/29.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.2693621712
Short name T122
Test name
Test status
Simulation time 1393870000 ps
CPU time 4.89 seconds
Started Jul 28 04:21:29 PM PDT 24
Finished Jul 28 04:21:40 PM PDT 24
Peak memory 164620 kb
Host smart-0d7f7dcc-314f-4869-8ecf-868cc231a9d7
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2693621712 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.2693621712
Directory /workspace/3.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.759551631
Short name T144
Test name
Test status
Simulation time 1485910000 ps
CPU time 3.82 seconds
Started Jul 28 04:23:26 PM PDT 24
Finished Jul 28 04:23:34 PM PDT 24
Peak memory 164884 kb
Host smart-f7031eaa-93bb-46ef-ae25-17ec50bed233
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=759551631 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.759551631
Directory /workspace/30.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.868390660
Short name T128
Test name
Test status
Simulation time 1403230000 ps
CPU time 3.73 seconds
Started Jul 28 04:25:38 PM PDT 24
Finished Jul 28 04:25:46 PM PDT 24
Peak memory 164688 kb
Host smart-a4e18544-04eb-44da-acf0-b0ae4887ac46
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=868390660 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.868390660
Directory /workspace/31.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.3066109957
Short name T134
Test name
Test status
Simulation time 1227890000 ps
CPU time 3.39 seconds
Started Jul 28 04:25:21 PM PDT 24
Finished Jul 28 04:25:29 PM PDT 24
Peak memory 164944 kb
Host smart-d8759677-634f-4356-9004-a4a1ba07651a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3066109957 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.3066109957
Directory /workspace/32.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.668856563
Short name T141
Test name
Test status
Simulation time 1492010000 ps
CPU time 3.23 seconds
Started Jul 28 04:24:55 PM PDT 24
Finished Jul 28 04:25:02 PM PDT 24
Peak memory 163276 kb
Host smart-ebc33fa2-aec5-4dca-bc44-150ca5566f38
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=668856563 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.668856563
Directory /workspace/33.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.4097281310
Short name T138
Test name
Test status
Simulation time 1458570000 ps
CPU time 3.73 seconds
Started Jul 28 04:20:15 PM PDT 24
Finished Jul 28 04:20:23 PM PDT 24
Peak memory 164824 kb
Host smart-a40315b4-9d11-4e9d-9279-a7539a0f37b8
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4097281310 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.4097281310
Directory /workspace/34.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.296711340
Short name T148
Test name
Test status
Simulation time 1519210000 ps
CPU time 3.74 seconds
Started Jul 28 04:24:48 PM PDT 24
Finished Jul 28 04:24:57 PM PDT 24
Peak memory 163352 kb
Host smart-7fc98e74-a28c-41f0-a90c-1b09254a2a56
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=296711340 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.296711340
Directory /workspace/35.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.2338201620
Short name T124
Test name
Test status
Simulation time 1620610000 ps
CPU time 4.92 seconds
Started Jul 28 04:22:07 PM PDT 24
Finished Jul 28 04:22:18 PM PDT 24
Peak memory 164636 kb
Host smart-533d5b24-a459-4cd8-9f3f-6940349f3f0b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2338201620 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.2338201620
Directory /workspace/36.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.3637461686
Short name T142
Test name
Test status
Simulation time 1400910000 ps
CPU time 2.91 seconds
Started Jul 28 04:24:37 PM PDT 24
Finished Jul 28 04:24:44 PM PDT 24
Peak memory 163372 kb
Host smart-8d4969d7-b539-4809-bbab-92be0e6bb2c5
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3637461686 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.3637461686
Directory /workspace/37.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.2200227166
Short name T113
Test name
Test status
Simulation time 1417070000 ps
CPU time 4.37 seconds
Started Jul 28 04:22:58 PM PDT 24
Finished Jul 28 04:23:08 PM PDT 24
Peak memory 164816 kb
Host smart-875b0922-0c9d-4f51-b371-631dc37d1844
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2200227166 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.2200227166
Directory /workspace/38.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.3920149797
Short name T111
Test name
Test status
Simulation time 1499950000 ps
CPU time 4.09 seconds
Started Jul 28 04:24:58 PM PDT 24
Finished Jul 28 04:25:07 PM PDT 24
Peak memory 162848 kb
Host smart-1dd6d270-51f1-467c-ac98-d9d31121f02b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3920149797 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.3920149797
Directory /workspace/39.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.1665615558
Short name T118
Test name
Test status
Simulation time 1448090000 ps
CPU time 4.83 seconds
Started Jul 28 04:22:31 PM PDT 24
Finished Jul 28 04:22:42 PM PDT 24
Peak memory 164896 kb
Host smart-3cb01010-67e7-49b7-b723-4d7df6035521
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1665615558 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.1665615558
Directory /workspace/4.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.561710440
Short name T136
Test name
Test status
Simulation time 1580650000 ps
CPU time 5.21 seconds
Started Jul 28 04:24:50 PM PDT 24
Finished Jul 28 04:25:02 PM PDT 24
Peak memory 164640 kb
Host smart-3d601fce-7484-4eed-a765-745d27c7bc3b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=561710440 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.561710440
Directory /workspace/40.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.11264587
Short name T117
Test name
Test status
Simulation time 1427850000 ps
CPU time 4.68 seconds
Started Jul 28 04:24:52 PM PDT 24
Finished Jul 28 04:25:03 PM PDT 24
Peak memory 164632 kb
Host smart-18f7283a-4fc5-484c-a311-c12698cd4aac
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=11264587 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.11264587
Directory /workspace/41.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.3272952081
Short name T121
Test name
Test status
Simulation time 1591910000 ps
CPU time 4.99 seconds
Started Jul 28 04:24:52 PM PDT 24
Finished Jul 28 04:25:03 PM PDT 24
Peak memory 164520 kb
Host smart-c2e78b44-3229-443f-b942-8db77bebb5a1
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3272952081 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.3272952081
Directory /workspace/42.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.3707635355
Short name T132
Test name
Test status
Simulation time 1545030000 ps
CPU time 5.13 seconds
Started Jul 28 04:24:52 PM PDT 24
Finished Jul 28 04:25:04 PM PDT 24
Peak memory 164696 kb
Host smart-87f0ca4c-8a9a-4d43-b908-a86457d2aebd
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3707635355 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.3707635355
Directory /workspace/43.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.3595227014
Short name T112
Test name
Test status
Simulation time 1467670000 ps
CPU time 5.48 seconds
Started Jul 28 04:25:10 PM PDT 24
Finished Jul 28 04:25:22 PM PDT 24
Peak memory 164688 kb
Host smart-1d1aa063-9f2a-4a10-840a-f42a0726414e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3595227014 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.3595227014
Directory /workspace/44.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.739198262
Short name T129
Test name
Test status
Simulation time 1463570000 ps
CPU time 4.51 seconds
Started Jul 28 04:23:35 PM PDT 24
Finished Jul 28 04:23:45 PM PDT 24
Peak memory 164748 kb
Host smart-cc27a564-9749-4b25-ac6a-bf2f23be9ffe
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=739198262 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.739198262
Directory /workspace/45.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.2330095915
Short name T156
Test name
Test status
Simulation time 1428150000 ps
CPU time 4.48 seconds
Started Jul 28 04:22:05 PM PDT 24
Finished Jul 28 04:22:15 PM PDT 24
Peak memory 164744 kb
Host smart-a2fcf5d5-4722-4871-8e46-8f83d1f1400b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2330095915 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.2330095915
Directory /workspace/46.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.255436320
Short name T159
Test name
Test status
Simulation time 1565170000 ps
CPU time 3.82 seconds
Started Jul 28 04:23:25 PM PDT 24
Finished Jul 28 04:23:34 PM PDT 24
Peak memory 164724 kb
Host smart-609041bd-b3ed-4faf-ac7e-a636ef6f9795
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=255436320 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.255436320
Directory /workspace/47.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.3002982515
Short name T143
Test name
Test status
Simulation time 1378510000 ps
CPU time 4.87 seconds
Started Jul 28 04:22:20 PM PDT 24
Finished Jul 28 04:22:31 PM PDT 24
Peak memory 164940 kb
Host smart-b160f716-73a4-41d3-9e60-15f7bfaecee3
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3002982515 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.3002982515
Directory /workspace/48.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.1112971535
Short name T160
Test name
Test status
Simulation time 1651110000 ps
CPU time 5.43 seconds
Started Jul 28 04:22:06 PM PDT 24
Finished Jul 28 04:22:18 PM PDT 24
Peak memory 164708 kb
Host smart-28f6b3a8-38ed-46ef-87e7-4c5c2edcf56a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1112971535 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.1112971535
Directory /workspace/49.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.1424095402
Short name T145
Test name
Test status
Simulation time 1281790000 ps
CPU time 4.49 seconds
Started Jul 28 04:21:29 PM PDT 24
Finished Jul 28 04:21:39 PM PDT 24
Peak memory 164620 kb
Host smart-d6f4b616-f315-40a8-99b4-3fba86c320da
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1424095402 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.1424095402
Directory /workspace/5.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.159677567
Short name T116
Test name
Test status
Simulation time 1557950000 ps
CPU time 5.6 seconds
Started Jul 28 04:21:29 PM PDT 24
Finished Jul 28 04:21:41 PM PDT 24
Peak memory 164676 kb
Host smart-26a79d61-5328-4c25-84d3-609688eb8731
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=159677567 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.159677567
Directory /workspace/6.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.1055862401
Short name T126
Test name
Test status
Simulation time 1377150000 ps
CPU time 4.3 seconds
Started Jul 28 04:21:17 PM PDT 24
Finished Jul 28 04:21:27 PM PDT 24
Peak memory 162976 kb
Host smart-fc84d5c0-4894-4bcb-be44-32d63016cc5f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1055862401 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.1055862401
Directory /workspace/7.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.3482646586
Short name T139
Test name
Test status
Simulation time 1469710000 ps
CPU time 4.32 seconds
Started Jul 28 04:22:10 PM PDT 24
Finished Jul 28 04:22:20 PM PDT 24
Peak memory 164632 kb
Host smart-2bc65d26-2ab1-4153-8138-5c4083eca213
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3482646586 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.3482646586
Directory /workspace/8.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.4119082283
Short name T157
Test name
Test status
Simulation time 1517990000 ps
CPU time 3.55 seconds
Started Jul 28 04:21:14 PM PDT 24
Finished Jul 28 04:21:22 PM PDT 24
Peak memory 164356 kb
Host smart-16fa3338-b576-4603-9884-0904a7f93871
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4119082283 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.4119082283
Directory /workspace/9.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.3430412194
Short name T49
Test name
Test status
Simulation time 1456190000 ps
CPU time 3.39 seconds
Started Jul 28 04:19:24 PM PDT 24
Finished Jul 28 04:19:31 PM PDT 24
Peak memory 165032 kb
Host smart-8fb9bdd3-596a-4b0f-b9ed-e909379a4f76
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3430412194 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.3430412194
Directory /workspace/0.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.2801145322
Short name T56
Test name
Test status
Simulation time 1446010000 ps
CPU time 4.48 seconds
Started Jul 28 04:19:30 PM PDT 24
Finished Jul 28 04:19:40 PM PDT 24
Peak memory 164168 kb
Host smart-53101c3e-8e2b-447a-8daa-46a2ed133644
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2801145322 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.2801145322
Directory /workspace/1.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.2235126190
Short name T44
Test name
Test status
Simulation time 1491890000 ps
CPU time 4.77 seconds
Started Jul 28 04:19:32 PM PDT 24
Finished Jul 28 04:19:43 PM PDT 24
Peak memory 164948 kb
Host smart-9edb3423-306d-4082-b015-45d76505f2ce
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2235126190 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.2235126190
Directory /workspace/10.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.3347567244
Short name T48
Test name
Test status
Simulation time 1435050000 ps
CPU time 4.51 seconds
Started Jul 28 04:19:33 PM PDT 24
Finished Jul 28 04:19:43 PM PDT 24
Peak memory 164948 kb
Host smart-5fac58bd-d1ba-4451-90cd-cdb001f4d557
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3347567244 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.3347567244
Directory /workspace/11.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.2949439468
Short name T40
Test name
Test status
Simulation time 1350450000 ps
CPU time 3.77 seconds
Started Jul 28 04:19:32 PM PDT 24
Finished Jul 28 04:19:41 PM PDT 24
Peak memory 164236 kb
Host smart-d62b960a-28e5-4316-9796-2f6d39776840
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2949439468 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.2949439468
Directory /workspace/12.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.2982014943
Short name T50
Test name
Test status
Simulation time 1530250000 ps
CPU time 4.63 seconds
Started Jul 28 04:19:34 PM PDT 24
Finished Jul 28 04:19:44 PM PDT 24
Peak memory 164948 kb
Host smart-4bedc7a0-b712-4e54-9f82-f383f7a3f76c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2982014943 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.2982014943
Directory /workspace/14.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.1669700753
Short name T37
Test name
Test status
Simulation time 1539410000 ps
CPU time 4.25 seconds
Started Jul 28 04:19:24 PM PDT 24
Finished Jul 28 04:19:34 PM PDT 24
Peak memory 163496 kb
Host smart-62a87794-0e4d-4d2c-92a9-1227139e18ba
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1669700753 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.1669700753
Directory /workspace/15.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.2556099075
Short name T11
Test name
Test status
Simulation time 1554350000 ps
CPU time 4.36 seconds
Started Jul 28 04:19:30 PM PDT 24
Finished Jul 28 04:19:40 PM PDT 24
Peak memory 164288 kb
Host smart-afe630d9-3126-4202-a64f-55bf2c8ad94f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2556099075 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.2556099075
Directory /workspace/16.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.793989559
Short name T47
Test name
Test status
Simulation time 1548970000 ps
CPU time 4.29 seconds
Started Jul 28 04:19:30 PM PDT 24
Finished Jul 28 04:19:40 PM PDT 24
Peak memory 164336 kb
Host smart-69f62f91-ad40-4189-b288-f3dadd497c16
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=793989559 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.793989559
Directory /workspace/17.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.3603622490
Short name T35
Test name
Test status
Simulation time 1534190000 ps
CPU time 4.3 seconds
Started Jul 28 04:19:33 PM PDT 24
Finished Jul 28 04:19:43 PM PDT 24
Peak memory 164348 kb
Host smart-2d5de88b-05b6-4dd4-b1cf-3f06956bbae9
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3603622490 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.3603622490
Directory /workspace/18.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.3390376005
Short name T3
Test name
Test status
Simulation time 1594470000 ps
CPU time 4.25 seconds
Started Jul 28 04:19:24 PM PDT 24
Finished Jul 28 04:19:34 PM PDT 24
Peak memory 163940 kb
Host smart-361f4f6a-c4db-4c48-a858-ca316e20c9ba
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3390376005 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.3390376005
Directory /workspace/19.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.1244802852
Short name T42
Test name
Test status
Simulation time 1565870000 ps
CPU time 5.24 seconds
Started Jul 28 04:19:29 PM PDT 24
Finished Jul 28 04:19:41 PM PDT 24
Peak memory 162232 kb
Host smart-e7c9bd10-b2ca-46cb-b990-888915a0c8b5
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1244802852 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.1244802852
Directory /workspace/2.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.4160269284
Short name T10
Test name
Test status
Simulation time 1395290000 ps
CPU time 4.58 seconds
Started Jul 28 04:19:30 PM PDT 24
Finished Jul 28 04:19:40 PM PDT 24
Peak memory 164312 kb
Host smart-a70b5509-9c1d-44c1-9bfe-9b5e1fbe6f83
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4160269284 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.4160269284
Directory /workspace/20.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.2812156086
Short name T33
Test name
Test status
Simulation time 1305230000 ps
CPU time 3.91 seconds
Started Jul 28 04:19:33 PM PDT 24
Finished Jul 28 04:19:42 PM PDT 24
Peak memory 164348 kb
Host smart-734eed5d-9881-4416-9d79-d711c4d2f481
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2812156086 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.2812156086
Directory /workspace/21.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.3069106543
Short name T59
Test name
Test status
Simulation time 1554150000 ps
CPU time 5.01 seconds
Started Jul 28 04:19:29 PM PDT 24
Finished Jul 28 04:19:40 PM PDT 24
Peak memory 162688 kb
Host smart-08a48d11-238d-4679-81c6-ee8a72cbf9b2
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3069106543 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.3069106543
Directory /workspace/22.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.2654044335
Short name T52
Test name
Test status
Simulation time 1590530000 ps
CPU time 3.98 seconds
Started Jul 28 04:19:31 PM PDT 24
Finished Jul 28 04:19:39 PM PDT 24
Peak memory 164300 kb
Host smart-13c4bf12-a7d4-4404-8e75-ee6222f1d61d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2654044335 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.2654044335
Directory /workspace/23.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.3291907728
Short name T61
Test name
Test status
Simulation time 1516410000 ps
CPU time 4.21 seconds
Started Jul 28 04:19:32 PM PDT 24
Finished Jul 28 04:19:42 PM PDT 24
Peak memory 164240 kb
Host smart-aa918ccb-550b-456c-b202-dcf847ab760d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3291907728 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.3291907728
Directory /workspace/24.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.3217018594
Short name T54
Test name
Test status
Simulation time 1444770000 ps
CPU time 4.43 seconds
Started Jul 28 04:19:30 PM PDT 24
Finished Jul 28 04:19:40 PM PDT 24
Peak memory 164288 kb
Host smart-416f3886-8447-4f89-9bf2-ab3511cd3f48
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3217018594 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.3217018594
Directory /workspace/25.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.145852418
Short name T64
Test name
Test status
Simulation time 1452510000 ps
CPU time 3.45 seconds
Started Jul 28 04:20:08 PM PDT 24
Finished Jul 28 04:20:15 PM PDT 24
Peak memory 164568 kb
Host smart-9cb54370-4562-4a92-b8e2-9a151eebb7e9
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=145852418 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.145852418
Directory /workspace/26.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.2556507558
Short name T55
Test name
Test status
Simulation time 1415430000 ps
CPU time 3.88 seconds
Started Jul 28 04:19:24 PM PDT 24
Finished Jul 28 04:19:34 PM PDT 24
Peak memory 163744 kb
Host smart-df623154-6b73-4b8c-8e7f-36de3de773de
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2556507558 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.2556507558
Directory /workspace/27.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.1047695138
Short name T34
Test name
Test status
Simulation time 1538050000 ps
CPU time 4.6 seconds
Started Jul 28 04:19:30 PM PDT 24
Finished Jul 28 04:19:41 PM PDT 24
Peak memory 164288 kb
Host smart-9eee35ba-36c0-4e8c-853a-11ec39f2be03
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1047695138 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.1047695138
Directory /workspace/28.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.204023879
Short name T70
Test name
Test status
Simulation time 1387790000 ps
CPU time 3.81 seconds
Started Jul 28 04:19:33 PM PDT 24
Finished Jul 28 04:19:42 PM PDT 24
Peak memory 164396 kb
Host smart-77b6646b-4d2b-4a39-a2f3-f992e4e1f50e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=204023879 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.204023879
Directory /workspace/29.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.1177809370
Short name T13
Test name
Test status
Simulation time 1634750000 ps
CPU time 5.04 seconds
Started Jul 28 04:19:32 PM PDT 24
Finished Jul 28 04:19:43 PM PDT 24
Peak memory 164900 kb
Host smart-6d559701-4e76-4de1-80ea-7d2c282c3261
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1177809370 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.1177809370
Directory /workspace/3.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.712195137
Short name T1
Test name
Test status
Simulation time 1506770000 ps
CPU time 4.93 seconds
Started Jul 28 04:19:29 PM PDT 24
Finished Jul 28 04:19:40 PM PDT 24
Peak memory 164160 kb
Host smart-937fac97-e49a-4e4e-b470-d7a83a0165ec
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=712195137 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.712195137
Directory /workspace/30.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.310987924
Short name T12
Test name
Test status
Simulation time 1413450000 ps
CPU time 2.54 seconds
Started Jul 28 04:19:24 PM PDT 24
Finished Jul 28 04:19:30 PM PDT 24
Peak memory 164256 kb
Host smart-fc3614ba-b984-475f-a5a2-5600aaa31adb
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=310987924 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.310987924
Directory /workspace/31.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.4124975399
Short name T2
Test name
Test status
Simulation time 1585810000 ps
CPU time 5.52 seconds
Started Jul 28 04:19:30 PM PDT 24
Finished Jul 28 04:19:43 PM PDT 24
Peak memory 164304 kb
Host smart-033a5e65-8a81-43d5-9587-5b01bac33300
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4124975399 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.4124975399
Directory /workspace/32.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.1030939023
Short name T46
Test name
Test status
Simulation time 1496770000 ps
CPU time 3.83 seconds
Started Jul 28 04:20:11 PM PDT 24
Finished Jul 28 04:20:20 PM PDT 24
Peak memory 164724 kb
Host smart-077846e8-72ae-47c0-8ab8-82342bd2b5a4
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1030939023 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.1030939023
Directory /workspace/33.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.1811955177
Short name T66
Test name
Test status
Simulation time 1470610000 ps
CPU time 4.62 seconds
Started Jul 28 04:19:32 PM PDT 24
Finished Jul 28 04:19:42 PM PDT 24
Peak memory 164948 kb
Host smart-71cba21c-ef42-4ecf-bb90-1ff16253cb0f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1811955177 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.1811955177
Directory /workspace/34.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.2358757510
Short name T32
Test name
Test status
Simulation time 1277910000 ps
CPU time 3.84 seconds
Started Jul 28 04:19:32 PM PDT 24
Finished Jul 28 04:19:41 PM PDT 24
Peak memory 163684 kb
Host smart-8c4bc984-615c-4179-9b7e-57e6fdfe1df0
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2358757510 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.2358757510
Directory /workspace/35.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.3867286338
Short name T36
Test name
Test status
Simulation time 1252510000 ps
CPU time 3.72 seconds
Started Jul 28 04:19:29 PM PDT 24
Finished Jul 28 04:19:38 PM PDT 24
Peak memory 164840 kb
Host smart-f7989731-eca4-41fe-b0c1-5548a7344459
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3867286338 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.3867286338
Directory /workspace/36.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.3968637671
Short name T45
Test name
Test status
Simulation time 1388890000 ps
CPU time 3.69 seconds
Started Jul 28 04:19:29 PM PDT 24
Finished Jul 28 04:19:38 PM PDT 24
Peak memory 164888 kb
Host smart-2f1ff05c-c740-420e-a824-c3d646c4ce9a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3968637671 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.3968637671
Directory /workspace/37.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.864658513
Short name T43
Test name
Test status
Simulation time 1172050000 ps
CPU time 3.54 seconds
Started Jul 28 04:19:30 PM PDT 24
Finished Jul 28 04:19:38 PM PDT 24
Peak memory 164336 kb
Host smart-806819d0-9ca5-49c6-98b6-7c3aef7f53f1
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=864658513 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.864658513
Directory /workspace/38.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.1223268239
Short name T8
Test name
Test status
Simulation time 1578490000 ps
CPU time 3.71 seconds
Started Jul 28 04:19:24 PM PDT 24
Finished Jul 28 04:19:32 PM PDT 24
Peak memory 164984 kb
Host smart-edbbd516-c2bb-4af1-9278-05dfeed20b4c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1223268239 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.1223268239
Directory /workspace/39.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.1986616024
Short name T51
Test name
Test status
Simulation time 1602750000 ps
CPU time 4.96 seconds
Started Jul 28 04:19:30 PM PDT 24
Finished Jul 28 04:19:41 PM PDT 24
Peak memory 164296 kb
Host smart-a7cc3977-1960-4ad6-8f63-274501eba719
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1986616024 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.1986616024
Directory /workspace/4.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.2957098616
Short name T68
Test name
Test status
Simulation time 1558010000 ps
CPU time 3.59 seconds
Started Jul 28 04:19:23 PM PDT 24
Finished Jul 28 04:19:31 PM PDT 24
Peak memory 164984 kb
Host smart-301600a3-7045-47ec-8185-2efccd356425
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2957098616 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.2957098616
Directory /workspace/40.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.2226595301
Short name T57
Test name
Test status
Simulation time 1438410000 ps
CPU time 4.03 seconds
Started Jul 28 04:19:28 PM PDT 24
Finished Jul 28 04:19:38 PM PDT 24
Peak memory 164480 kb
Host smart-1f617d7e-eeee-4771-9a0f-15afb0bd3611
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2226595301 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.2226595301
Directory /workspace/41.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.205243749
Short name T31
Test name
Test status
Simulation time 1430910000 ps
CPU time 4.03 seconds
Started Jul 28 04:19:24 PM PDT 24
Finished Jul 28 04:19:34 PM PDT 24
Peak memory 163200 kb
Host smart-ab882818-8113-4374-9d40-83429c850aae
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=205243749 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.205243749
Directory /workspace/42.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.3677054444
Short name T38
Test name
Test status
Simulation time 1369870000 ps
CPU time 3.75 seconds
Started Jul 28 04:19:29 PM PDT 24
Finished Jul 28 04:19:38 PM PDT 24
Peak memory 164300 kb
Host smart-b0252407-f3e0-4754-8f37-8fa0b8a59df4
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3677054444 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.3677054444
Directory /workspace/43.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.2726820841
Short name T60
Test name
Test status
Simulation time 1187810000 ps
CPU time 3.96 seconds
Started Jul 28 04:19:33 PM PDT 24
Finished Jul 28 04:19:41 PM PDT 24
Peak memory 164948 kb
Host smart-1c026edf-5258-44df-a333-272c33302b64
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2726820841 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.2726820841
Directory /workspace/44.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.2917525048
Short name T67
Test name
Test status
Simulation time 1524990000 ps
CPU time 5.17 seconds
Started Jul 28 04:19:29 PM PDT 24
Finished Jul 28 04:19:40 PM PDT 24
Peak memory 162004 kb
Host smart-e71e4f19-51f4-420d-a66e-1b442442f1b3
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2917525048 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.2917525048
Directory /workspace/45.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.1240414051
Short name T63
Test name
Test status
Simulation time 1420990000 ps
CPU time 4.4 seconds
Started Jul 28 04:19:33 PM PDT 24
Finished Jul 28 04:19:43 PM PDT 24
Peak memory 164948 kb
Host smart-7b5bc72f-7116-4859-a683-7d51b278c456
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1240414051 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.1240414051
Directory /workspace/46.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.2072085806
Short name T53
Test name
Test status
Simulation time 1479770000 ps
CPU time 4.91 seconds
Started Jul 28 04:19:29 PM PDT 24
Finished Jul 28 04:19:40 PM PDT 24
Peak memory 164236 kb
Host smart-cb5e4d71-a090-47a3-92de-141d353eb5f1
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2072085806 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.2072085806
Directory /workspace/47.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.3369536548
Short name T62
Test name
Test status
Simulation time 1537770000 ps
CPU time 4.04 seconds
Started Jul 28 04:19:28 PM PDT 24
Finished Jul 28 04:19:38 PM PDT 24
Peak memory 163176 kb
Host smart-edee889e-091c-4f74-b4b1-81bc7608f18e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3369536548 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.3369536548
Directory /workspace/48.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.809875819
Short name T39
Test name
Test status
Simulation time 1551310000 ps
CPU time 4.8 seconds
Started Jul 28 04:19:33 PM PDT 24
Finished Jul 28 04:19:44 PM PDT 24
Peak memory 164996 kb
Host smart-5931e51b-2d31-4488-a7e6-2428ed6a50c1
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=809875819 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.809875819
Directory /workspace/49.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.851661009
Short name T9
Test name
Test status
Simulation time 1448870000 ps
CPU time 4.68 seconds
Started Jul 28 04:19:29 PM PDT 24
Finished Jul 28 04:19:40 PM PDT 24
Peak memory 165868 kb
Host smart-ec510bb6-e741-4457-82a0-4f1b4f4fc157
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=851661009 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.851661009
Directory /workspace/5.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.2122168086
Short name T58
Test name
Test status
Simulation time 1587970000 ps
CPU time 5.33 seconds
Started Jul 28 04:19:30 PM PDT 24
Finished Jul 28 04:19:42 PM PDT 24
Peak memory 164288 kb
Host smart-a2aaf089-50ae-4885-b02f-4d68e8ce1de1
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2122168086 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.2122168086
Directory /workspace/6.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.635262006
Short name T65
Test name
Test status
Simulation time 1437350000 ps
CPU time 4.78 seconds
Started Jul 28 04:19:29 PM PDT 24
Finished Jul 28 04:19:40 PM PDT 24
Peak memory 165172 kb
Host smart-0bc150bd-4807-45e8-bb44-1464696d017e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=635262006 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.635262006
Directory /workspace/7.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.299008485
Short name T69
Test name
Test status
Simulation time 1350770000 ps
CPU time 4.42 seconds
Started Jul 28 04:19:29 PM PDT 24
Finished Jul 28 04:19:39 PM PDT 24
Peak memory 163968 kb
Host smart-446eeb3d-043c-499d-a5bf-86c1d21616a2
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=299008485 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.299008485
Directory /workspace/8.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.3178126276
Short name T41
Test name
Test status
Simulation time 1552210000 ps
CPU time 4.56 seconds
Started Jul 28 04:19:29 PM PDT 24
Finished Jul 28 04:19:40 PM PDT 24
Peak memory 163628 kb
Host smart-34c9e1ff-d4c4-4fc7-9001-22f61162338f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3178126276 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.3178126276
Directory /workspace/9.prim_lfsr_gal_smoke/latest
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