Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.31 100.00 96.55 100.00 100.00 95.00


Total tests in report: 200
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
87.31 87.31 100.00 100.00 96.55 96.55 100.00 100.00 100.00 100.00 40.00 40.00 /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.3473419594
96.81 9.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 87.50 47.50 /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.400205729
98.31 1.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 95.00 7.50 /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.3893945000

Tests that do not contribute to grading

Name
/workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.2512053087
/workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.1716565050
/workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.830601933
/workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.4104138038
/workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.3547727527
/workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.2303827528
/workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.3717982415
/workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.3058397924
/workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.1136074087
/workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.4150635076
/workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2013590149
/workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.3505093549
/workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.2511171497
/workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.428923001
/workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.3942173658
/workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.1835930068
/workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.3680565759
/workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.3085788927
/workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1801139024
/workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.1234571266
/workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.3681429500
/workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.3429442006
/workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.3739537950
/workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3740556990
/workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.1045042308
/workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.2321752511
/workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.967855554
/workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.602515852
/workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.2605052262
/workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.1950152706
/workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.447782900
/workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.277385466
/workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.2745695714
/workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.76469569
/workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.2019420679
/workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.939072051
/workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.3528116738
/workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.2173109250
/workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.819349409
/workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.3819856755
/workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.3241000655
/workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.13755036
/workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.3544779838
/workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.2226963510
/workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.4123718136
/workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.1578035202
/workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.3831986845
/workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.2864888919
/workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.645092801
/workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.4143901439
/workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.3091440114
/workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.3625880409
/workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.3187871736
/workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.3463817632
/workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.1643236401
/workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.3923480232
/workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.1734937475
/workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.3980780878
/workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.760489333
/workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.128853836
/workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.1517209830
/workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.76479155
/workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3458167436
/workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.2884888553
/workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.3461834177
/workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.3497576798
/workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.4064233748
/workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.3185950657
/workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.4060164391
/workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.2433165832
/workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.2931452838
/workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.4043700483
/workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.3232698277
/workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.3286130920
/workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.3183844317
/workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.2201542181
/workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.348285516
/workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.4108143866
/workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.3167953424
/workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.2947688363
/workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.362615571
/workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.2046646919
/workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.4211681407
/workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.1207189039
/workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.3207505855
/workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.3046501612
/workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.4005603237
/workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.3368550933
/workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.3890347129
/workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.2645401123
/workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.1372255245
/workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1684101379
/workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.3015655902
/workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.2573581838
/workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.1260553494
/workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.506886287
/workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.1800461744
/workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.101518991
/workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.3264023586
/workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.789257990
/workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.1122781341
/workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.1338766032
/workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.2602070960
/workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.100046999
/workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.606055491
/workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.4335764
/workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.2546955964
/workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.3807516424
/workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.4153146122
/workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.3920260780
/workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.88112380
/workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.1177139010
/workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.1835677130
/workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.1022501819
/workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.3817519987
/workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.594047791
/workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.4020999614
/workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.1911523976
/workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.3590815686
/workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.1547748389
/workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.618889564
/workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.2570741006
/workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.1088074819
/workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.2984926834
/workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.2379925048
/workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.3479088999
/workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.2922934641
/workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.179494083
/workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.1910488608
/workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1828414678
/workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.3862313521
/workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.107885814
/workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.1355458779
/workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.3018846702
/workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.3547089899
/workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.60692126
/workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.3893431093
/workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.2918991361
/workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.3612915471
/workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.2534516003
/workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.1986461717
/workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.3075502954
/workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.4285558500
/workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.1673090089
/workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.1662263878
/workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.2769215417
/workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.85133099
/workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.979645572
/workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.2439466604
/workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.3194085091
/workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.2188389130
/workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.358727196
/workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.2594139888
/workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.3171687898
/workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.818443652
/workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.2366406034
/workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.2423614373
/workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.1942313824
/workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.3196743476
/workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.2264837233
/workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.3210451981
/workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.617572015
/workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.3784195198
/workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.867154412
/workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.3769481354
/workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.524756962
/workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.3620110019
/workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.790859926
/workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.4260950372
/workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.871988018
/workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.2641001736
/workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.2581025241
/workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.1602910103
/workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.3695346095
/workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.3339358340
/workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.3158183532
/workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.1295816044
/workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.1472536310
/workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.753975591
/workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.1305685793
/workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.3921898963
/workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.973472342
/workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.429777726
/workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.1314837137
/workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.3347740906
/workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.3621802691
/workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.660412018
/workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.2015580143
/workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.1558637298
/workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.871354068
/workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.3792029847
/workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.1715563112
/workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.2390718013
/workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.1370221705
/workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.2058802455
/workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.2789325539
/workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.47160535



Total test records in report: 200
tests.html | tests1.html | tests2.html | tests3.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.3473419594 Jul 29 04:20:20 PM PDT 24 Jul 29 04:20:28 PM PDT 24 1472170000 ps
T2 /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.47160535 Jul 29 04:25:27 PM PDT 24 Jul 29 04:25:33 PM PDT 24 1339790000 ps
T3 /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.1942313824 Jul 29 04:24:10 PM PDT 24 Jul 29 04:24:16 PM PDT 24 1269110000 ps
T4 /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.2789325539 Jul 29 04:25:37 PM PDT 24 Jul 29 04:25:46 PM PDT 24 1479210000 ps
T8 /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.3171687898 Jul 29 04:25:47 PM PDT 24 Jul 29 04:25:54 PM PDT 24 1455490000 ps
T9 /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.2581025241 Jul 29 04:23:11 PM PDT 24 Jul 29 04:23:21 PM PDT 24 1505510000 ps
T10 /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.617572015 Jul 29 04:20:57 PM PDT 24 Jul 29 04:21:05 PM PDT 24 1596130000 ps
T11 /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.3769481354 Jul 29 04:25:33 PM PDT 24 Jul 29 04:25:41 PM PDT 24 1562430000 ps
T12 /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.660412018 Jul 29 04:21:57 PM PDT 24 Jul 29 04:22:06 PM PDT 24 1401830000 ps
T13 /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.2366406034 Jul 29 04:26:10 PM PDT 24 Jul 29 04:26:18 PM PDT 24 1270530000 ps
T31 /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.3158183532 Jul 29 04:25:02 PM PDT 24 Jul 29 04:25:13 PM PDT 24 1549450000 ps
T32 /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.2439466604 Jul 29 04:25:28 PM PDT 24 Jul 29 04:25:36 PM PDT 24 1560270000 ps
T33 /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.2058802455 Jul 29 04:25:30 PM PDT 24 Jul 29 04:25:37 PM PDT 24 1351090000 ps
T34 /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.3695346095 Jul 29 04:19:43 PM PDT 24 Jul 29 04:19:49 PM PDT 24 1014650000 ps
T35 /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.3621802691 Jul 29 04:20:20 PM PDT 24 Jul 29 04:20:28 PM PDT 24 1380110000 ps
T36 /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.4260950372 Jul 29 04:25:47 PM PDT 24 Jul 29 04:25:55 PM PDT 24 1509490000 ps
T37 /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.358727196 Jul 29 04:24:33 PM PDT 24 Jul 29 04:24:40 PM PDT 24 1158990000 ps
T38 /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.1602910103 Jul 29 04:25:17 PM PDT 24 Jul 29 04:25:27 PM PDT 24 1591230000 ps
T39 /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.2188389130 Jul 29 04:21:26 PM PDT 24 Jul 29 04:21:36 PM PDT 24 1504450000 ps
T40 /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.2390718013 Jul 29 04:25:11 PM PDT 24 Jul 29 04:25:21 PM PDT 24 1271730000 ps
T41 /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.973472342 Jul 29 04:25:18 PM PDT 24 Jul 29 04:25:28 PM PDT 24 1469790000 ps
T42 /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.3784195198 Jul 29 04:25:22 PM PDT 24 Jul 29 04:25:30 PM PDT 24 1503070000 ps
T43 /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.790859926 Jul 29 04:25:51 PM PDT 24 Jul 29 04:26:00 PM PDT 24 1358730000 ps
T44 /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.1314837137 Jul 29 04:25:25 PM PDT 24 Jul 29 04:25:33 PM PDT 24 1291070000 ps
T45 /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.753975591 Jul 29 04:25:50 PM PDT 24 Jul 29 04:25:59 PM PDT 24 1396010000 ps
T46 /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.3210451981 Jul 29 04:25:51 PM PDT 24 Jul 29 04:26:00 PM PDT 24 1357010000 ps
T47 /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.429777726 Jul 29 04:22:35 PM PDT 24 Jul 29 04:22:46 PM PDT 24 1523650000 ps
T48 /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.818443652 Jul 29 04:23:27 PM PDT 24 Jul 29 04:23:36 PM PDT 24 1458250000 ps
T49 /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.867154412 Jul 29 04:21:47 PM PDT 24 Jul 29 04:21:58 PM PDT 24 1564370000 ps
T50 /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.871988018 Jul 29 04:25:37 PM PDT 24 Jul 29 04:25:46 PM PDT 24 1222230000 ps
T51 /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.2594139888 Jul 29 04:25:37 PM PDT 24 Jul 29 04:25:45 PM PDT 24 1366690000 ps
T52 /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.3194085091 Jul 29 04:25:18 PM PDT 24 Jul 29 04:25:26 PM PDT 24 1542070000 ps
T53 /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.2641001736 Jul 29 04:24:56 PM PDT 24 Jul 29 04:25:05 PM PDT 24 1636450000 ps
T54 /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.1715563112 Jul 29 04:25:43 PM PDT 24 Jul 29 04:25:53 PM PDT 24 1551230000 ps
T55 /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.1305685793 Jul 29 04:22:16 PM PDT 24 Jul 29 04:22:25 PM PDT 24 1576930000 ps
T56 /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.1558637298 Jul 29 04:25:02 PM PDT 24 Jul 29 04:25:10 PM PDT 24 1338470000 ps
T57 /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.2423614373 Jul 29 04:21:39 PM PDT 24 Jul 29 04:21:46 PM PDT 24 1466230000 ps
T58 /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.1472536310 Jul 29 04:21:56 PM PDT 24 Jul 29 04:22:06 PM PDT 24 1554170000 ps
T59 /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.1295816044 Jul 29 04:25:56 PM PDT 24 Jul 29 04:26:05 PM PDT 24 1161170000 ps
T60 /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.1370221705 Jul 29 04:25:18 PM PDT 24 Jul 29 04:25:28 PM PDT 24 1317690000 ps
T61 /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.2015580143 Jul 29 04:25:01 PM PDT 24 Jul 29 04:25:10 PM PDT 24 1520910000 ps
T62 /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.3620110019 Jul 29 04:23:20 PM PDT 24 Jul 29 04:23:29 PM PDT 24 1528950000 ps
T63 /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.3196743476 Jul 29 04:21:41 PM PDT 24 Jul 29 04:21:52 PM PDT 24 1473410000 ps
T64 /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.2264837233 Jul 29 04:21:05 PM PDT 24 Jul 29 04:21:14 PM PDT 24 1513610000 ps
T65 /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.3339358340 Jul 29 04:25:24 PM PDT 24 Jul 29 04:25:31 PM PDT 24 1451230000 ps
T66 /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.871354068 Jul 29 04:21:01 PM PDT 24 Jul 29 04:21:09 PM PDT 24 1329810000 ps
T67 /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.3792029847 Jul 29 04:25:44 PM PDT 24 Jul 29 04:25:54 PM PDT 24 1453290000 ps
T68 /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.524756962 Jul 29 04:25:40 PM PDT 24 Jul 29 04:25:47 PM PDT 24 1409950000 ps
T69 /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.3921898963 Jul 29 04:25:50 PM PDT 24 Jul 29 04:26:01 PM PDT 24 1531190000 ps
T70 /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.3347740906 Jul 29 04:25:07 PM PDT 24 Jul 29 04:25:14 PM PDT 24 1497190000 ps
T5 /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.3429442006 Jul 29 04:22:35 PM PDT 24 Jul 29 04:54:12 PM PDT 24 336758050000 ps
T6 /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.1045042308 Jul 29 04:25:56 PM PDT 24 Jul 29 04:51:12 PM PDT 24 336729490000 ps
T7 /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.3505093549 Jul 29 04:20:06 PM PDT 24 Jul 29 04:56:03 PM PDT 24 336430170000 ps
T14 /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.2745695714 Jul 29 04:24:47 PM PDT 24 Jul 29 04:52:07 PM PDT 24 336636830000 ps
T15 /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.277385466 Jul 29 04:25:36 PM PDT 24 Jul 29 04:53:12 PM PDT 24 336487810000 ps
T16 /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.1716565050 Jul 29 04:23:10 PM PDT 24 Jul 29 04:51:46 PM PDT 24 336424950000 ps
T17 /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.400205729 Jul 29 04:19:36 PM PDT 24 Jul 29 04:50:47 PM PDT 24 336957130000 ps
T18 /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.2511171497 Jul 29 04:20:22 PM PDT 24 Jul 29 04:48:25 PM PDT 24 336864030000 ps
T19 /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.3547727527 Jul 29 04:25:45 PM PDT 24 Jul 29 04:53:16 PM PDT 24 336544950000 ps
T20 /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3740556990 Jul 29 04:21:27 PM PDT 24 Jul 29 04:52:07 PM PDT 24 337088270000 ps
T71 /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.4123718136 Jul 29 04:20:38 PM PDT 24 Jul 29 04:56:46 PM PDT 24 336371790000 ps
T72 /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.939072051 Jul 29 04:20:24 PM PDT 24 Jul 29 05:03:55 PM PDT 24 336694870000 ps
T73 /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.2226963510 Jul 29 04:20:20 PM PDT 24 Jul 29 04:48:41 PM PDT 24 336960730000 ps
T74 /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.3544779838 Jul 29 04:25:02 PM PDT 24 Jul 29 04:51:18 PM PDT 24 336712750000 ps
T75 /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.1835930068 Jul 29 04:25:26 PM PDT 24 Jul 29 04:50:19 PM PDT 24 336582510000 ps
T76 /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.428923001 Jul 29 04:25:47 PM PDT 24 Jul 29 04:59:05 PM PDT 24 336609550000 ps
T77 /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.2512053087 Jul 29 04:19:37 PM PDT 24 Jul 29 04:50:09 PM PDT 24 337099130000 ps
T78 /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.3819856755 Jul 29 04:20:37 PM PDT 24 Jul 29 04:56:19 PM PDT 24 336875530000 ps
T79 /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.1136074087 Jul 29 04:22:57 PM PDT 24 Jul 29 04:55:25 PM PDT 24 336985790000 ps
T80 /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.3681429500 Jul 29 04:25:41 PM PDT 24 Jul 29 04:52:24 PM PDT 24 336812950000 ps
T81 /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.76469569 Jul 29 04:19:37 PM PDT 24 Jul 29 04:50:04 PM PDT 24 336598290000 ps
T82 /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.967855554 Jul 29 04:23:49 PM PDT 24 Jul 29 04:53:07 PM PDT 24 336936610000 ps
T83 /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2013590149 Jul 29 04:21:51 PM PDT 24 Jul 29 04:58:47 PM PDT 24 337033530000 ps
T84 /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.3739537950 Jul 29 04:25:03 PM PDT 24 Jul 29 04:48:52 PM PDT 24 336544530000 ps
T85 /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.2605052262 Jul 29 04:25:01 PM PDT 24 Jul 29 04:52:41 PM PDT 24 336854090000 ps
T86 /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.447782900 Jul 29 04:25:02 PM PDT 24 Jul 29 04:53:57 PM PDT 24 336553530000 ps
T87 /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.4104138038 Jul 29 04:25:28 PM PDT 24 Jul 29 04:51:29 PM PDT 24 336723630000 ps
T88 /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.1950152706 Jul 29 04:25:18 PM PDT 24 Jul 29 04:53:55 PM PDT 24 336775430000 ps
T89 /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.819349409 Jul 29 04:20:24 PM PDT 24 Jul 29 05:03:43 PM PDT 24 336743650000 ps
T90 /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1801139024 Jul 29 04:22:40 PM PDT 24 Jul 29 04:54:20 PM PDT 24 336484190000 ps
T91 /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.3717982415 Jul 29 04:21:45 PM PDT 24 Jul 29 04:51:35 PM PDT 24 337049270000 ps
T92 /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.3085788927 Jul 29 04:21:13 PM PDT 24 Jul 29 04:51:57 PM PDT 24 336716430000 ps
T93 /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.3942173658 Jul 29 04:21:08 PM PDT 24 Jul 29 05:02:56 PM PDT 24 336597030000 ps
T94 /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.3241000655 Jul 29 04:21:08 PM PDT 24 Jul 29 05:04:09 PM PDT 24 336494810000 ps
T95 /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.830601933 Jul 29 04:25:27 PM PDT 24 Jul 29 04:51:16 PM PDT 24 336856030000 ps
T96 /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.2173109250 Jul 29 04:24:07 PM PDT 24 Jul 29 04:59:07 PM PDT 24 336689610000 ps
T97 /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.2321752511 Jul 29 04:21:08 PM PDT 24 Jul 29 05:05:12 PM PDT 24 336988670000 ps
T98 /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.3831986845 Jul 29 04:19:40 PM PDT 24 Jul 29 04:53:07 PM PDT 24 336476890000 ps
T99 /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.602515852 Jul 29 04:22:44 PM PDT 24 Jul 29 04:55:26 PM PDT 24 336503150000 ps
T100 /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.13755036 Jul 29 04:20:24 PM PDT 24 Jul 29 04:50:12 PM PDT 24 336527650000 ps
T101 /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.645092801 Jul 29 04:19:40 PM PDT 24 Jul 29 04:53:16 PM PDT 24 336399110000 ps
T102 /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.2303827528 Jul 29 04:24:11 PM PDT 24 Jul 29 04:56:06 PM PDT 24 336771370000 ps
T103 /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.3680565759 Jul 29 04:20:26 PM PDT 24 Jul 29 04:52:33 PM PDT 24 336544890000 ps
T104 /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.3058397924 Jul 29 04:26:11 PM PDT 24 Jul 29 04:53:46 PM PDT 24 336895730000 ps
T105 /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.3528116738 Jul 29 04:19:43 PM PDT 24 Jul 29 04:51:23 PM PDT 24 337018050000 ps
T106 /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.1234571266 Jul 29 04:25:34 PM PDT 24 Jul 29 04:54:20 PM PDT 24 336777330000 ps
T107 /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.2019420679 Jul 29 04:25:36 PM PDT 24 Jul 29 04:53:17 PM PDT 24 336382150000 ps
T108 /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.4150635076 Jul 29 04:25:25 PM PDT 24 Jul 29 04:53:22 PM PDT 24 336407290000 ps
T109 /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.1578035202 Jul 29 04:25:27 PM PDT 24 Jul 29 04:51:38 PM PDT 24 336474610000 ps
T110 /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.2864888919 Jul 29 04:19:39 PM PDT 24 Jul 29 04:52:24 PM PDT 24 336387570000 ps
T111 /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.2918991361 Jul 29 04:32:10 PM PDT 24 Jul 29 04:32:18 PM PDT 24 1342070000 ps
T112 /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1828414678 Jul 29 04:25:56 PM PDT 24 Jul 29 04:26:07 PM PDT 24 1408950000 ps
T113 /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.1986461717 Jul 29 04:32:10 PM PDT 24 Jul 29 04:32:22 PM PDT 24 1507450000 ps
T114 /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.2769215417 Jul 29 04:25:37 PM PDT 24 Jul 29 04:25:44 PM PDT 24 1170890000 ps
T115 /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.4153146122 Jul 29 04:25:31 PM PDT 24 Jul 29 04:25:37 PM PDT 24 1316810000 ps
T116 /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.3018846702 Jul 29 04:32:08 PM PDT 24 Jul 29 04:32:16 PM PDT 24 1088790000 ps
T117 /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.3547089899 Jul 29 04:32:14 PM PDT 24 Jul 29 04:32:20 PM PDT 24 1541630000 ps
T118 /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.2546955964 Jul 29 04:25:02 PM PDT 24 Jul 29 04:25:12 PM PDT 24 1471670000 ps
T119 /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.3075502954 Jul 29 04:32:11 PM PDT 24 Jul 29 04:32:21 PM PDT 24 1474470000 ps
T120 /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.4335764 Jul 29 04:25:30 PM PDT 24 Jul 29 04:25:36 PM PDT 24 1422430000 ps
T121 /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.3893431093 Jul 29 04:32:10 PM PDT 24 Jul 29 04:32:20 PM PDT 24 1480610000 ps
T122 /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.789257990 Jul 29 04:25:18 PM PDT 24 Jul 29 04:25:27 PM PDT 24 1296630000 ps
T123 /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.179494083 Jul 29 04:25:01 PM PDT 24 Jul 29 04:25:11 PM PDT 24 1519890000 ps
T124 /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.1911523976 Jul 29 04:23:48 PM PDT 24 Jul 29 04:23:56 PM PDT 24 1520770000 ps
T125 /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.2570741006 Jul 29 04:25:28 PM PDT 24 Jul 29 04:25:35 PM PDT 24 1471490000 ps
T126 /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.594047791 Jul 29 04:20:35 PM PDT 24 Jul 29 04:20:45 PM PDT 24 1582670000 ps
T127 /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.2379925048 Jul 29 04:21:25 PM PDT 24 Jul 29 04:21:33 PM PDT 24 1290990000 ps
T128 /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.3920260780 Jul 29 04:25:41 PM PDT 24 Jul 29 04:25:50 PM PDT 24 1480290000 ps
T129 /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.1662263878 Jul 29 04:20:33 PM PDT 24 Jul 29 04:20:38 PM PDT 24 1136370000 ps
T130 /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.100046999 Jul 29 04:24:52 PM PDT 24 Jul 29 04:24:59 PM PDT 24 1452930000 ps
T131 /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.60692126 Jul 29 04:32:11 PM PDT 24 Jul 29 04:32:21 PM PDT 24 1404210000 ps
T132 /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.3807516424 Jul 29 04:25:27 PM PDT 24 Jul 29 04:25:35 PM PDT 24 1501270000 ps
T133 /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.1835677130 Jul 29 04:21:38 PM PDT 24 Jul 29 04:21:46 PM PDT 24 1528070000 ps
T134 /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.1338766032 Jul 29 04:25:45 PM PDT 24 Jul 29 04:25:53 PM PDT 24 1518970000 ps
T135 /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.1177139010 Jul 29 04:25:26 PM PDT 24 Jul 29 04:25:36 PM PDT 24 1626850000 ps
T136 /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.3479088999 Jul 29 04:25:40 PM PDT 24 Jul 29 04:25:47 PM PDT 24 1441670000 ps
T137 /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.3817519987 Jul 29 04:26:10 PM PDT 24 Jul 29 04:26:18 PM PDT 24 1303330000 ps
T138 /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.1022501819 Jul 29 04:25:25 PM PDT 24 Jul 29 04:25:32 PM PDT 24 1405070000 ps
T139 /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.1673090089 Jul 29 04:25:15 PM PDT 24 Jul 29 04:25:23 PM PDT 24 1317790000 ps
T140 /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.3612915471 Jul 29 04:32:11 PM PDT 24 Jul 29 04:32:21 PM PDT 24 1537170000 ps
T141 /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.88112380 Jul 29 04:25:18 PM PDT 24 Jul 29 04:25:28 PM PDT 24 1384130000 ps
T142 /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.1910488608 Jul 29 04:22:23 PM PDT 24 Jul 29 04:22:32 PM PDT 24 1573210000 ps
T143 /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.606055491 Jul 29 04:25:42 PM PDT 24 Jul 29 04:25:49 PM PDT 24 1453930000 ps
T144 /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.618889564 Jul 29 04:25:03 PM PDT 24 Jul 29 04:25:11 PM PDT 24 1522270000 ps
T145 /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.2984926834 Jul 29 04:25:31 PM PDT 24 Jul 29 04:25:38 PM PDT 24 1423810000 ps
T146 /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.979645572 Jul 29 04:25:36 PM PDT 24 Jul 29 04:25:45 PM PDT 24 1473950000 ps
T147 /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.1355458779 Jul 29 04:21:11 PM PDT 24 Jul 29 04:21:21 PM PDT 24 1357170000 ps
T148 /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.4020999614 Jul 29 04:22:58 PM PDT 24 Jul 29 04:23:11 PM PDT 24 1583790000 ps
T149 /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.1088074819 Jul 29 04:21:07 PM PDT 24 Jul 29 04:21:20 PM PDT 24 1488830000 ps
T150 /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.85133099 Jul 29 04:23:47 PM PDT 24 Jul 29 04:23:59 PM PDT 24 1367150000 ps
T151 /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.2602070960 Jul 29 04:25:45 PM PDT 24 Jul 29 04:25:53 PM PDT 24 1549390000 ps
T152 /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.107885814 Jul 29 04:25:25 PM PDT 24 Jul 29 04:25:34 PM PDT 24 1494910000 ps
T153 /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.3590815686 Jul 29 04:23:19 PM PDT 24 Jul 29 04:23:28 PM PDT 24 1336010000 ps
T154 /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.1547748389 Jul 29 04:20:30 PM PDT 24 Jul 29 04:20:38 PM PDT 24 1384790000 ps
T155 /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.4285558500 Jul 29 04:32:10 PM PDT 24 Jul 29 04:32:16 PM PDT 24 1400710000 ps
T156 /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.2534516003 Jul 29 04:32:13 PM PDT 24 Jul 29 04:32:21 PM PDT 24 1287270000 ps
T157 /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.2922934641 Jul 29 04:21:08 PM PDT 24 Jul 29 04:21:17 PM PDT 24 1526870000 ps
T158 /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.3862313521 Jul 29 04:20:24 PM PDT 24 Jul 29 04:20:34 PM PDT 24 1391110000 ps
T159 /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.1122781341 Jul 29 04:25:13 PM PDT 24 Jul 29 04:25:21 PM PDT 24 1474750000 ps
T160 /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.3264023586 Jul 29 04:23:19 PM PDT 24 Jul 29 04:23:29 PM PDT 24 1486370000 ps
T21 /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.506886287 Jul 29 04:20:29 PM PDT 24 Jul 29 04:53:59 PM PDT 24 336713390000 ps
T22 /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.3207505855 Jul 29 04:32:20 PM PDT 24 Jul 29 05:00:51 PM PDT 24 336633810000 ps
T23 /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.2573581838 Jul 29 04:24:46 PM PDT 24 Jul 29 04:55:45 PM PDT 24 336752810000 ps
T24 /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3458167436 Jul 29 04:21:57 PM PDT 24 Jul 29 05:02:35 PM PDT 24 336532370000 ps
T25 /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.3893945000 Jul 29 04:25:50 PM PDT 24 Jul 29 04:51:51 PM PDT 24 336593510000 ps
T26 /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.101518991 Jul 29 04:21:15 PM PDT 24 Jul 29 04:54:48 PM PDT 24 336670690000 ps
T27 /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.3183844317 Jul 29 04:32:21 PM PDT 24 Jul 29 04:59:31 PM PDT 24 336394670000 ps
T28 /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.3625880409 Jul 29 04:25:36 PM PDT 24 Jul 29 04:53:12 PM PDT 24 336808950000 ps
T29 /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.1372255245 Jul 29 04:32:14 PM PDT 24 Jul 29 05:05:47 PM PDT 24 336644070000 ps
T30 /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.760489333 Jul 29 04:25:38 PM PDT 24 Jul 29 05:01:32 PM PDT 24 336360790000 ps
T161 /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.3015655902 Jul 29 04:32:17 PM PDT 24 Jul 29 05:03:41 PM PDT 24 336340330000 ps
T162 /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.3890347129 Jul 29 04:32:21 PM PDT 24 Jul 29 05:03:00 PM PDT 24 336400850000 ps
T163 /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1684101379 Jul 29 04:32:16 PM PDT 24 Jul 29 04:59:17 PM PDT 24 336541410000 ps
T164 /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.3167953424 Jul 29 04:32:15 PM PDT 24 Jul 29 05:01:53 PM PDT 24 336332610000 ps
T165 /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.3046501612 Jul 29 04:32:16 PM PDT 24 Jul 29 05:02:10 PM PDT 24 336677510000 ps
T166 /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.3091440114 Jul 29 04:25:22 PM PDT 24 Jul 29 04:52:57 PM PDT 24 336413770000 ps
T167 /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.4060164391 Jul 29 04:21:50 PM PDT 24 Jul 29 05:00:09 PM PDT 24 336694650000 ps
T168 /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.3368550933 Jul 29 04:32:14 PM PDT 24 Jul 29 05:00:11 PM PDT 24 336350610000 ps
T169 /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.3187871736 Jul 29 04:22:20 PM PDT 24 Jul 29 04:56:27 PM PDT 24 336743730000 ps
T170 /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.3497576798 Jul 29 04:25:37 PM PDT 24 Jul 29 05:01:21 PM PDT 24 336903290000 ps
T171 /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.4211681407 Jul 29 04:25:00 PM PDT 24 Jul 29 04:58:29 PM PDT 24 336511950000 ps
T172 /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.2433165832 Jul 29 04:25:39 PM PDT 24 Jul 29 05:01:15 PM PDT 24 336649610000 ps
T173 /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.1800461744 Jul 29 04:25:46 PM PDT 24 Jul 29 04:56:04 PM PDT 24 336603850000 ps
T174 /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.2201542181 Jul 29 04:32:16 PM PDT 24 Jul 29 05:07:39 PM PDT 24 336898950000 ps
T175 /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.2046646919 Jul 29 04:32:15 PM PDT 24 Jul 29 05:02:39 PM PDT 24 336297910000 ps
T176 /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.1734937475 Jul 29 04:22:17 PM PDT 24 Jul 29 05:05:18 PM PDT 24 336513810000 ps
T177 /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.3461834177 Jul 29 04:25:00 PM PDT 24 Jul 29 04:58:33 PM PDT 24 336358150000 ps
T178 /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.3286130920 Jul 29 04:32:14 PM PDT 24 Jul 29 05:00:45 PM PDT 24 336993410000 ps
T179 /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.128853836 Jul 29 04:21:07 PM PDT 24 Jul 29 04:49:14 PM PDT 24 336511150000 ps
T180 /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.1207189039 Jul 29 04:32:15 PM PDT 24 Jul 29 05:03:36 PM PDT 24 336729430000 ps
T181 /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.2931452838 Jul 29 04:25:35 PM PDT 24 Jul 29 04:53:31 PM PDT 24 336765990000 ps
T182 /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.76479155 Jul 29 04:25:46 PM PDT 24 Jul 29 04:55:47 PM PDT 24 336388130000 ps
T183 /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.2645401123 Jul 29 04:32:14 PM PDT 24 Jul 29 05:04:30 PM PDT 24 336641890000 ps
T184 /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.4005603237 Jul 29 04:32:24 PM PDT 24 Jul 29 04:58:47 PM PDT 24 336471770000 ps
T185 /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.3923480232 Jul 29 04:25:47 PM PDT 24 Jul 29 04:59:07 PM PDT 24 337108370000 ps
T186 /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.4143901439 Jul 29 04:25:36 PM PDT 24 Jul 29 04:53:38 PM PDT 24 336780150000 ps
T187 /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.1517209830 Jul 29 04:24:46 PM PDT 24 Jul 29 04:55:33 PM PDT 24 337102630000 ps
T188 /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.3232698277 Jul 29 04:32:10 PM PDT 24 Jul 29 05:05:22 PM PDT 24 336413030000 ps
T189 /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.2884888553 Jul 29 04:25:23 PM PDT 24 Jul 29 04:50:36 PM PDT 24 336862710000 ps
T190 /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.348285516 Jul 29 04:32:16 PM PDT 24 Jul 29 05:03:44 PM PDT 24 336608590000 ps
T191 /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.1260553494 Jul 29 04:20:30 PM PDT 24 Jul 29 04:48:49 PM PDT 24 337069930000 ps
T192 /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.3980780878 Jul 29 04:21:51 PM PDT 24 Jul 29 05:00:10 PM PDT 24 336771590000 ps
T193 /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.4043700483 Jul 29 04:25:47 PM PDT 24 Jul 29 04:58:18 PM PDT 24 337048510000 ps
T194 /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.3185950657 Jul 29 04:25:27 PM PDT 24 Jul 29 04:49:04 PM PDT 24 336623310000 ps
T195 /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.2947688363 Jul 29 04:32:24 PM PDT 24 Jul 29 05:03:50 PM PDT 24 336457350000 ps
T196 /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.4064233748 Jul 29 04:25:35 PM PDT 24 Jul 29 04:53:23 PM PDT 24 336482590000 ps
T197 /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.4108143866 Jul 29 04:32:23 PM PDT 24 Jul 29 04:57:29 PM PDT 24 337090750000 ps
T198 /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.362615571 Jul 29 04:32:16 PM PDT 24 Jul 29 04:59:27 PM PDT 24 336505690000 ps
T199 /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.3463817632 Jul 29 04:21:58 PM PDT 24 Jul 29 04:52:49 PM PDT 24 337049610000 ps
T200 /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.1643236401 Jul 29 04:25:46 PM PDT 24 Jul 29 04:56:25 PM PDT 24 336429090000 ps

Test location /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.3473419594
Short name T1
Test name
Test status
Simulation time 1472170000 ps
CPU time 3.65 seconds
Started Jul 29 04:20:20 PM PDT 24
Finished Jul 29 04:20:28 PM PDT 24
Peak memory 164772 kb
Host smart-17e03a4d-1f1c-48f9-8c16-47a737ba921d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3473419594 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.3473419594
Directory /workspace/13.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.400205729
Short name T17
Test name
Test status
Simulation time 336957130000 ps
CPU time 766.16 seconds
Started Jul 29 04:19:36 PM PDT 24
Finished Jul 29 04:50:47 PM PDT 24
Peak memory 159712 kb
Host smart-d31eacf1-eb09-48b9-b57b-3e650ec2c831
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=400205729 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.400205729
Directory /workspace/0.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.3893945000
Short name T25
Test name
Test status
Simulation time 336593510000 ps
CPU time 628.69 seconds
Started Jul 29 04:25:50 PM PDT 24
Finished Jul 29 04:51:51 PM PDT 24
Peak memory 160616 kb
Host smart-21e7d959-a90a-4214-99ea-6e1e0e00c065
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3893945000 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.3893945000
Directory /workspace/1.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.2512053087
Short name T77
Test name
Test status
Simulation time 337099130000 ps
CPU time 739.98 seconds
Started Jul 29 04:19:37 PM PDT 24
Finished Jul 29 04:50:09 PM PDT 24
Peak memory 160332 kb
Host smart-d9ffd554-145a-4d30-8887-40b52959434c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2512053087 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.2512053087
Directory /workspace/1.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.1716565050
Short name T16
Test name
Test status
Simulation time 336424950000 ps
CPU time 682.26 seconds
Started Jul 29 04:23:10 PM PDT 24
Finished Jul 29 04:51:46 PM PDT 24
Peak memory 160744 kb
Host smart-c78545be-b4a3-4ccf-ac2e-5b19b3663ee6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1716565050 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.1716565050
Directory /workspace/10.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.830601933
Short name T95
Test name
Test status
Simulation time 336856030000 ps
CPU time 628.35 seconds
Started Jul 29 04:25:27 PM PDT 24
Finished Jul 29 04:51:16 PM PDT 24
Peak memory 160448 kb
Host smart-d0480700-b193-40b8-81e1-f3a79def1df4
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=830601933 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.830601933
Directory /workspace/11.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.4104138038
Short name T87
Test name
Test status
Simulation time 336723630000 ps
CPU time 641.69 seconds
Started Jul 29 04:25:28 PM PDT 24
Finished Jul 29 04:51:29 PM PDT 24
Peak memory 159760 kb
Host smart-b608ab77-8f95-4445-8e18-d425b2de1aaa
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4104138038 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.4104138038
Directory /workspace/12.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.3547727527
Short name T19
Test name
Test status
Simulation time 336544950000 ps
CPU time 668.69 seconds
Started Jul 29 04:25:45 PM PDT 24
Finished Jul 29 04:53:16 PM PDT 24
Peak memory 160452 kb
Host smart-2696bc24-c99e-4f6a-9ae7-b5a13e6b4998
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3547727527 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.3547727527
Directory /workspace/13.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.2303827528
Short name T102
Test name
Test status
Simulation time 336771370000 ps
CPU time 778.28 seconds
Started Jul 29 04:24:11 PM PDT 24
Finished Jul 29 04:56:06 PM PDT 24
Peak memory 160636 kb
Host smart-f0be859a-481f-46ed-8205-c02954ab31cf
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2303827528 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.2303827528
Directory /workspace/14.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.3717982415
Short name T91
Test name
Test status
Simulation time 337049270000 ps
CPU time 733.4 seconds
Started Jul 29 04:21:45 PM PDT 24
Finished Jul 29 04:51:35 PM PDT 24
Peak memory 160868 kb
Host smart-034aa103-4fa7-4190-883d-98403ec03132
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3717982415 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.3717982415
Directory /workspace/15.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.3058397924
Short name T104
Test name
Test status
Simulation time 336895730000 ps
CPU time 671.46 seconds
Started Jul 29 04:26:11 PM PDT 24
Finished Jul 29 04:53:46 PM PDT 24
Peak memory 160604 kb
Host smart-96697149-e1b7-49f4-8f9a-8438c2b9e222
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3058397924 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.3058397924
Directory /workspace/16.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.1136074087
Short name T79
Test name
Test status
Simulation time 336985790000 ps
CPU time 801.3 seconds
Started Jul 29 04:22:57 PM PDT 24
Finished Jul 29 04:55:25 PM PDT 24
Peak memory 160852 kb
Host smart-bd2a6261-639e-4623-aefd-ea1aa04331db
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1136074087 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.1136074087
Directory /workspace/17.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.4150635076
Short name T108
Test name
Test status
Simulation time 336407290000 ps
CPU time 675.52 seconds
Started Jul 29 04:25:25 PM PDT 24
Finished Jul 29 04:53:22 PM PDT 24
Peak memory 159760 kb
Host smart-c0eb1256-0b0d-4328-b832-63df969cdcde
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4150635076 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.4150635076
Directory /workspace/18.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2013590149
Short name T83
Test name
Test status
Simulation time 337033530000 ps
CPU time 884.13 seconds
Started Jul 29 04:21:51 PM PDT 24
Finished Jul 29 04:58:47 PM PDT 24
Peak memory 160472 kb
Host smart-ca16949e-76dc-4fd3-a306-239f465b72fd
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2013590149 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.2013590149
Directory /workspace/19.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.3505093549
Short name T7
Test name
Test status
Simulation time 336430170000 ps
CPU time 883.12 seconds
Started Jul 29 04:20:06 PM PDT 24
Finished Jul 29 04:56:03 PM PDT 24
Peak memory 160420 kb
Host smart-fdb02884-7b3c-4da0-820f-6ced8cf9cc4e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3505093549 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.3505093549
Directory /workspace/2.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.2511171497
Short name T18
Test name
Test status
Simulation time 336864030000 ps
CPU time 675.82 seconds
Started Jul 29 04:20:22 PM PDT 24
Finished Jul 29 04:48:25 PM PDT 24
Peak memory 160752 kb
Host smart-7624c947-bafb-42b9-89ed-0a887b4fc654
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2511171497 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.2511171497
Directory /workspace/20.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.428923001
Short name T76
Test name
Test status
Simulation time 336609550000 ps
CPU time 799.12 seconds
Started Jul 29 04:25:47 PM PDT 24
Finished Jul 29 04:59:05 PM PDT 24
Peak memory 159804 kb
Host smart-e5b82078-44b5-4251-9662-b70b835963a5
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=428923001 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.428923001
Directory /workspace/21.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.3942173658
Short name T93
Test name
Test status
Simulation time 336597030000 ps
CPU time 1004.73 seconds
Started Jul 29 04:21:08 PM PDT 24
Finished Jul 29 05:02:56 PM PDT 24
Peak memory 160612 kb
Host smart-b56f432a-b6cb-499d-8f6c-ba70e1f63e17
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3942173658 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.3942173658
Directory /workspace/22.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.1835930068
Short name T75
Test name
Test status
Simulation time 336582510000 ps
CPU time 607.97 seconds
Started Jul 29 04:25:26 PM PDT 24
Finished Jul 29 04:50:19 PM PDT 24
Peak memory 159988 kb
Host smart-4598ca0a-a454-4f95-a189-b3550ec10ad4
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1835930068 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.1835930068
Directory /workspace/23.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.3680565759
Short name T103
Test name
Test status
Simulation time 336544890000 ps
CPU time 785.2 seconds
Started Jul 29 04:20:26 PM PDT 24
Finished Jul 29 04:52:33 PM PDT 24
Peak memory 160652 kb
Host smart-e30a8a0f-9a39-4b91-bcb0-32ebd7403b63
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3680565759 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.3680565759
Directory /workspace/24.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.3085788927
Short name T92
Test name
Test status
Simulation time 336716430000 ps
CPU time 746.68 seconds
Started Jul 29 04:21:13 PM PDT 24
Finished Jul 29 04:51:57 PM PDT 24
Peak memory 160624 kb
Host smart-56660cab-eee1-45cc-81c2-258926d29576
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3085788927 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.3085788927
Directory /workspace/25.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1801139024
Short name T90
Test name
Test status
Simulation time 336484190000 ps
CPU time 776.13 seconds
Started Jul 29 04:22:40 PM PDT 24
Finished Jul 29 04:54:20 PM PDT 24
Peak memory 160636 kb
Host smart-47ed7128-2091-411f-94b1-4ccd57f15b03
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1801139024 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.1801139024
Directory /workspace/26.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.1234571266
Short name T106
Test name
Test status
Simulation time 336777330000 ps
CPU time 705.04 seconds
Started Jul 29 04:25:34 PM PDT 24
Finished Jul 29 04:54:20 PM PDT 24
Peak memory 160648 kb
Host smart-5389a054-b0cb-41ce-9e70-293b965cc81b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1234571266 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.1234571266
Directory /workspace/27.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.3681429500
Short name T80
Test name
Test status
Simulation time 336812950000 ps
CPU time 645.1 seconds
Started Jul 29 04:25:41 PM PDT 24
Finished Jul 29 04:52:24 PM PDT 24
Peak memory 160640 kb
Host smart-6d070530-451b-4552-b143-d88910df6ea8
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3681429500 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.3681429500
Directory /workspace/28.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.3429442006
Short name T5
Test name
Test status
Simulation time 336758050000 ps
CPU time 772.5 seconds
Started Jul 29 04:22:35 PM PDT 24
Finished Jul 29 04:54:12 PM PDT 24
Peak memory 160656 kb
Host smart-96748cf6-28ce-4731-bfcc-afecbe7b69ca
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3429442006 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.3429442006
Directory /workspace/29.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.3739537950
Short name T84
Test name
Test status
Simulation time 336544530000 ps
CPU time 577.63 seconds
Started Jul 29 04:25:03 PM PDT 24
Finished Jul 29 04:48:52 PM PDT 24
Peak memory 159900 kb
Host smart-e2428173-8ee7-4446-a18c-215f8644f6d4
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3739537950 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.3739537950
Directory /workspace/3.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3740556990
Short name T20
Test name
Test status
Simulation time 337088270000 ps
CPU time 741.47 seconds
Started Jul 29 04:21:27 PM PDT 24
Finished Jul 29 04:52:07 PM PDT 24
Peak memory 160756 kb
Host smart-3eee2d4e-97bc-4991-884f-44930427ee25
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3740556990 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.3740556990
Directory /workspace/30.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.1045042308
Short name T6
Test name
Test status
Simulation time 336729490000 ps
CPU time 602.08 seconds
Started Jul 29 04:25:56 PM PDT 24
Finished Jul 29 04:51:12 PM PDT 24
Peak memory 159792 kb
Host smart-74ee29e7-693e-422f-98ea-55bb381556c7
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1045042308 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.1045042308
Directory /workspace/31.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.2321752511
Short name T97
Test name
Test status
Simulation time 336988670000 ps
CPU time 1088.19 seconds
Started Jul 29 04:21:08 PM PDT 24
Finished Jul 29 05:05:12 PM PDT 24
Peak memory 160612 kb
Host smart-72cfc46a-8c5a-4486-ae97-017c7588123c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2321752511 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.2321752511
Directory /workspace/32.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.967855554
Short name T82
Test name
Test status
Simulation time 336936610000 ps
CPU time 722.78 seconds
Started Jul 29 04:23:49 PM PDT 24
Finished Jul 29 04:53:07 PM PDT 24
Peak memory 160636 kb
Host smart-6b73e951-42c1-4955-a37d-fc164b28055a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=967855554 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.967855554
Directory /workspace/33.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.602515852
Short name T99
Test name
Test status
Simulation time 336503150000 ps
CPU time 790.17 seconds
Started Jul 29 04:22:44 PM PDT 24
Finished Jul 29 04:55:26 PM PDT 24
Peak memory 160664 kb
Host smart-394ccb0d-28d1-441c-9b3d-0874b02f0f01
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=602515852 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.602515852
Directory /workspace/34.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.2605052262
Short name T85
Test name
Test status
Simulation time 336854090000 ps
CPU time 674.21 seconds
Started Jul 29 04:25:01 PM PDT 24
Finished Jul 29 04:52:41 PM PDT 24
Peak memory 159760 kb
Host smart-c53f824e-107a-4f1d-aaa1-4275b7fe3b3f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2605052262 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.2605052262
Directory /workspace/35.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.1950152706
Short name T88
Test name
Test status
Simulation time 336775430000 ps
CPU time 685.52 seconds
Started Jul 29 04:25:18 PM PDT 24
Finished Jul 29 04:53:55 PM PDT 24
Peak memory 160636 kb
Host smart-9816c5ec-b401-4da5-ba2c-9112f8afb2a9
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1950152706 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.1950152706
Directory /workspace/36.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.447782900
Short name T86
Test name
Test status
Simulation time 336553530000 ps
CPU time 705.68 seconds
Started Jul 29 04:25:02 PM PDT 24
Finished Jul 29 04:53:57 PM PDT 24
Peak memory 160556 kb
Host smart-9af8f400-3815-4c3c-bd52-657f46b052e6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=447782900 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.447782900
Directory /workspace/37.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.277385466
Short name T15
Test name
Test status
Simulation time 336487810000 ps
CPU time 672 seconds
Started Jul 29 04:25:36 PM PDT 24
Finished Jul 29 04:53:12 PM PDT 24
Peak memory 160452 kb
Host smart-787ce1db-6709-4c53-865c-483d8897d769
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=277385466 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.277385466
Directory /workspace/38.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.2745695714
Short name T14
Test name
Test status
Simulation time 336636830000 ps
CPU time 670.93 seconds
Started Jul 29 04:24:47 PM PDT 24
Finished Jul 29 04:52:07 PM PDT 24
Peak memory 159404 kb
Host smart-4ab059d3-7d19-4e53-a5bf-00562317cc77
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2745695714 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.2745695714
Directory /workspace/39.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.76469569
Short name T81
Test name
Test status
Simulation time 336598290000 ps
CPU time 738.33 seconds
Started Jul 29 04:19:37 PM PDT 24
Finished Jul 29 04:50:04 PM PDT 24
Peak memory 160392 kb
Host smart-ba6afb36-d0b1-4f59-8292-e0eaec7a0cc7
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=76469569 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.76469569
Directory /workspace/4.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.2019420679
Short name T107
Test name
Test status
Simulation time 336382150000 ps
CPU time 670.52 seconds
Started Jul 29 04:25:36 PM PDT 24
Finished Jul 29 04:53:17 PM PDT 24
Peak memory 160464 kb
Host smart-e1029696-1be8-4256-a448-476a8dd635c6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2019420679 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.2019420679
Directory /workspace/40.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.939072051
Short name T72
Test name
Test status
Simulation time 336694870000 ps
CPU time 1059.14 seconds
Started Jul 29 04:20:24 PM PDT 24
Finished Jul 29 05:03:55 PM PDT 24
Peak memory 160580 kb
Host smart-31b3778b-fc64-4b67-a1f8-dfef31b3481f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=939072051 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.939072051
Directory /workspace/41.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.3528116738
Short name T105
Test name
Test status
Simulation time 337018050000 ps
CPU time 775.21 seconds
Started Jul 29 04:19:43 PM PDT 24
Finished Jul 29 04:51:23 PM PDT 24
Peak memory 159632 kb
Host smart-ba395fb7-eccc-421b-a553-b5c543f2680e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3528116738 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.3528116738
Directory /workspace/42.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.2173109250
Short name T96
Test name
Test status
Simulation time 336689610000 ps
CPU time 862.82 seconds
Started Jul 29 04:24:07 PM PDT 24
Finished Jul 29 04:59:07 PM PDT 24
Peak memory 160632 kb
Host smart-5441e460-8c1d-4767-8c0c-d017395fd155
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2173109250 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.2173109250
Directory /workspace/43.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.819349409
Short name T89
Test name
Test status
Simulation time 336743650000 ps
CPU time 1050.17 seconds
Started Jul 29 04:20:24 PM PDT 24
Finished Jul 29 05:03:43 PM PDT 24
Peak memory 160584 kb
Host smart-0d6d1867-fd75-4c4a-8953-b03d350d45f0
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=819349409 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.819349409
Directory /workspace/44.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.3819856755
Short name T78
Test name
Test status
Simulation time 336875530000 ps
CPU time 881.85 seconds
Started Jul 29 04:20:37 PM PDT 24
Finished Jul 29 04:56:19 PM PDT 24
Peak memory 160624 kb
Host smart-9a0667d0-93a4-4b3f-abf7-b637cd910b74
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3819856755 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.3819856755
Directory /workspace/45.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.3241000655
Short name T94
Test name
Test status
Simulation time 336494810000 ps
CPU time 1037.53 seconds
Started Jul 29 04:21:08 PM PDT 24
Finished Jul 29 05:04:09 PM PDT 24
Peak memory 160612 kb
Host smart-9f216dcd-ead6-4578-ae8c-c0ff8a9e6996
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3241000655 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.3241000655
Directory /workspace/46.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.13755036
Short name T100
Test name
Test status
Simulation time 336527650000 ps
CPU time 725.15 seconds
Started Jul 29 04:20:24 PM PDT 24
Finished Jul 29 04:50:12 PM PDT 24
Peak memory 160648 kb
Host smart-398ad330-a0c2-4e34-85f1-34e7a0b250df
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=13755036 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.13755036
Directory /workspace/47.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.3544779838
Short name T74
Test name
Test status
Simulation time 336712750000 ps
CPU time 637.43 seconds
Started Jul 29 04:25:02 PM PDT 24
Finished Jul 29 04:51:18 PM PDT 24
Peak memory 160364 kb
Host smart-c68f6bc9-2466-4e44-93d5-5774121dc0f5
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3544779838 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.3544779838
Directory /workspace/48.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.2226963510
Short name T73
Test name
Test status
Simulation time 336960730000 ps
CPU time 674.02 seconds
Started Jul 29 04:20:20 PM PDT 24
Finished Jul 29 04:48:41 PM PDT 24
Peak memory 160744 kb
Host smart-83d58fc8-ea56-42bc-b874-99d5415da8ef
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2226963510 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.2226963510
Directory /workspace/49.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.4123718136
Short name T71
Test name
Test status
Simulation time 336371790000 ps
CPU time 892.04 seconds
Started Jul 29 04:20:38 PM PDT 24
Finished Jul 29 04:56:46 PM PDT 24
Peak memory 160568 kb
Host smart-a750029a-70b7-43fe-b451-49a1c66c33fb
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4123718136 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.4123718136
Directory /workspace/5.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.1578035202
Short name T109
Test name
Test status
Simulation time 336474610000 ps
CPU time 637.93 seconds
Started Jul 29 04:25:27 PM PDT 24
Finished Jul 29 04:51:38 PM PDT 24
Peak memory 159576 kb
Host smart-03a0b9c2-7f40-41f3-bd08-ff805f0dc1ab
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1578035202 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.1578035202
Directory /workspace/6.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.3831986845
Short name T98
Test name
Test status
Simulation time 336476890000 ps
CPU time 811.04 seconds
Started Jul 29 04:19:40 PM PDT 24
Finished Jul 29 04:53:07 PM PDT 24
Peak memory 160204 kb
Host smart-aba5deda-d5c1-4581-bf4c-1098ac23d8f5
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3831986845 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.3831986845
Directory /workspace/7.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.2864888919
Short name T110
Test name
Test status
Simulation time 336387570000 ps
CPU time 792.31 seconds
Started Jul 29 04:19:39 PM PDT 24
Finished Jul 29 04:52:24 PM PDT 24
Peak memory 159728 kb
Host smart-67ec6228-7684-4e68-bfa0-19d8192ef535
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2864888919 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.2864888919
Directory /workspace/8.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.645092801
Short name T101
Test name
Test status
Simulation time 336399110000 ps
CPU time 817.54 seconds
Started Jul 29 04:19:40 PM PDT 24
Finished Jul 29 04:53:16 PM PDT 24
Peak memory 160240 kb
Host smart-0ccc434d-5100-4f1f-8251-7700525781ed
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=645092801 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.645092801
Directory /workspace/9.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.4143901439
Short name T186
Test name
Test status
Simulation time 336780150000 ps
CPU time 681.01 seconds
Started Jul 29 04:25:36 PM PDT 24
Finished Jul 29 04:53:38 PM PDT 24
Peak memory 160456 kb
Host smart-d141e8ce-f917-47e1-9f25-3d12f672e8cb
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4143901439 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.4143901439
Directory /workspace/0.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.3091440114
Short name T166
Test name
Test status
Simulation time 336413770000 ps
CPU time 670.74 seconds
Started Jul 29 04:25:22 PM PDT 24
Finished Jul 29 04:52:57 PM PDT 24
Peak memory 159444 kb
Host smart-a8578cd0-1cee-4a82-be59-c5724da970fb
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3091440114 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.3091440114
Directory /workspace/10.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.3625880409
Short name T28
Test name
Test status
Simulation time 336808950000 ps
CPU time 656.06 seconds
Started Jul 29 04:25:36 PM PDT 24
Finished Jul 29 04:53:12 PM PDT 24
Peak memory 160456 kb
Host smart-7d21ac4a-a0e7-4806-8b3f-5fe81e7b9930
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3625880409 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.3625880409
Directory /workspace/11.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.3187871736
Short name T169
Test name
Test status
Simulation time 336743730000 ps
CPU time 834.43 seconds
Started Jul 29 04:22:20 PM PDT 24
Finished Jul 29 04:56:27 PM PDT 24
Peak memory 160632 kb
Host smart-523a4506-c682-4681-a0f6-be7561532f6a
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3187871736 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.3187871736
Directory /workspace/12.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.3463817632
Short name T199
Test name
Test status
Simulation time 337049610000 ps
CPU time 751.68 seconds
Started Jul 29 04:21:58 PM PDT 24
Finished Jul 29 04:52:49 PM PDT 24
Peak memory 160872 kb
Host smart-15484d8a-6d20-4d90-9272-93786845345b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3463817632 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.3463817632
Directory /workspace/13.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.1643236401
Short name T200
Test name
Test status
Simulation time 336429090000 ps
CPU time 738.66 seconds
Started Jul 29 04:25:46 PM PDT 24
Finished Jul 29 04:56:25 PM PDT 24
Peak memory 159988 kb
Host smart-134e087c-7a89-47d1-bb29-600baa2f3e7e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1643236401 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.1643236401
Directory /workspace/14.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.3923480232
Short name T185
Test name
Test status
Simulation time 337108370000 ps
CPU time 798.27 seconds
Started Jul 29 04:25:47 PM PDT 24
Finished Jul 29 04:59:07 PM PDT 24
Peak memory 159912 kb
Host smart-a8d17b9f-fd7f-441e-b58c-16d8cb857883
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3923480232 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.3923480232
Directory /workspace/15.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.1734937475
Short name T176
Test name
Test status
Simulation time 336513810000 ps
CPU time 1043.22 seconds
Started Jul 29 04:22:17 PM PDT 24
Finished Jul 29 05:05:18 PM PDT 24
Peak memory 160616 kb
Host smart-2cc6a879-73a1-455c-b392-23dcfda4b0f5
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1734937475 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.1734937475
Directory /workspace/16.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.3980780878
Short name T192
Test name
Test status
Simulation time 336771590000 ps
CPU time 920.28 seconds
Started Jul 29 04:21:51 PM PDT 24
Finished Jul 29 05:00:10 PM PDT 24
Peak memory 160476 kb
Host smart-405a5d8e-7867-40d3-b79a-0aa743ae9d14
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3980780878 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.3980780878
Directory /workspace/17.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.760489333
Short name T30
Test name
Test status
Simulation time 336360790000 ps
CPU time 859.07 seconds
Started Jul 29 04:25:38 PM PDT 24
Finished Jul 29 05:01:32 PM PDT 24
Peak memory 160412 kb
Host smart-a25133c2-09b8-4a28-acc1-01b5c5d57250
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=760489333 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.760489333
Directory /workspace/18.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.128853836
Short name T179
Test name
Test status
Simulation time 336511150000 ps
CPU time 678.71 seconds
Started Jul 29 04:21:07 PM PDT 24
Finished Jul 29 04:49:14 PM PDT 24
Peak memory 160620 kb
Host smart-bb093267-06ab-4fd7-aa11-e7ddce52f2b6
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=128853836 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.128853836
Directory /workspace/19.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.1517209830
Short name T187
Test name
Test status
Simulation time 337102630000 ps
CPU time 747.15 seconds
Started Jul 29 04:24:46 PM PDT 24
Finished Jul 29 04:55:33 PM PDT 24
Peak memory 159084 kb
Host smart-71f81e75-ab67-47b8-b231-017110475837
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1517209830 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.1517209830
Directory /workspace/2.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.76479155
Short name T182
Test name
Test status
Simulation time 336388130000 ps
CPU time 721.96 seconds
Started Jul 29 04:25:46 PM PDT 24
Finished Jul 29 04:55:47 PM PDT 24
Peak memory 160288 kb
Host smart-b9effd62-c60a-4105-be0e-cc9caf648df4
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=76479155 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.76479155
Directory /workspace/20.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3458167436
Short name T24
Test name
Test status
Simulation time 336532370000 ps
CPU time 976.99 seconds
Started Jul 29 04:21:57 PM PDT 24
Finished Jul 29 05:02:35 PM PDT 24
Peak memory 160616 kb
Host smart-3bac08bb-22c6-48fa-9c41-2d2e71f0c543
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3458167436 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.3458167436
Directory /workspace/21.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.2884888553
Short name T189
Test name
Test status
Simulation time 336862710000 ps
CPU time 612.65 seconds
Started Jul 29 04:25:23 PM PDT 24
Finished Jul 29 04:50:36 PM PDT 24
Peak memory 159416 kb
Host smart-e459eca5-f8b4-4656-8bd2-50b2ac99748b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2884888553 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.2884888553
Directory /workspace/22.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.3461834177
Short name T177
Test name
Test status
Simulation time 336358150000 ps
CPU time 825.62 seconds
Started Jul 29 04:25:00 PM PDT 24
Finished Jul 29 04:58:33 PM PDT 24
Peak memory 160600 kb
Host smart-ac19c4e2-d57e-487d-aac0-24a797f6ae20
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3461834177 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.3461834177
Directory /workspace/23.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.3497576798
Short name T170
Test name
Test status
Simulation time 336903290000 ps
CPU time 855.66 seconds
Started Jul 29 04:25:37 PM PDT 24
Finished Jul 29 05:01:21 PM PDT 24
Peak memory 159380 kb
Host smart-6ac27413-1ecd-44db-80b0-93a4cc90ec76
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3497576798 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.3497576798
Directory /workspace/24.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.4064233748
Short name T196
Test name
Test status
Simulation time 336482590000 ps
CPU time 661.44 seconds
Started Jul 29 04:25:35 PM PDT 24
Finished Jul 29 04:53:23 PM PDT 24
Peak memory 160436 kb
Host smart-ae07e636-d774-44cc-a69a-38d28658f1a7
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4064233748 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.4064233748
Directory /workspace/25.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.3185950657
Short name T194
Test name
Test status
Simulation time 336623310000 ps
CPU time 574.05 seconds
Started Jul 29 04:25:27 PM PDT 24
Finished Jul 29 04:49:04 PM PDT 24
Peak memory 160456 kb
Host smart-066728e4-2efb-4122-9096-34846e46dbd3
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3185950657 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.3185950657
Directory /workspace/26.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.4060164391
Short name T167
Test name
Test status
Simulation time 336694650000 ps
CPU time 933.2 seconds
Started Jul 29 04:21:50 PM PDT 24
Finished Jul 29 05:00:09 PM PDT 24
Peak memory 160476 kb
Host smart-e65fc541-ef4f-4e35-a4ec-bd7358f1f5cb
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4060164391 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.4060164391
Directory /workspace/27.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.2433165832
Short name T172
Test name
Test status
Simulation time 336649610000 ps
CPU time 850.88 seconds
Started Jul 29 04:25:39 PM PDT 24
Finished Jul 29 05:01:15 PM PDT 24
Peak memory 160452 kb
Host smart-6f7f5e1a-bb8b-4fa1-a461-20eddfe65fa3
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2433165832 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.2433165832
Directory /workspace/28.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.2931452838
Short name T181
Test name
Test status
Simulation time 336765990000 ps
CPU time 668.66 seconds
Started Jul 29 04:25:35 PM PDT 24
Finished Jul 29 04:53:31 PM PDT 24
Peak memory 160260 kb
Host smart-a6e50821-04c1-4719-a27b-931037a64be3
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2931452838 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.2931452838
Directory /workspace/29.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.4043700483
Short name T193
Test name
Test status
Simulation time 337048510000 ps
CPU time 781.97 seconds
Started Jul 29 04:25:47 PM PDT 24
Finished Jul 29 04:58:18 PM PDT 24
Peak memory 160416 kb
Host smart-4b94bd58-0906-4b7e-98f7-3121a9d072ba
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4043700483 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.4043700483
Directory /workspace/3.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.3232698277
Short name T188
Test name
Test status
Simulation time 336413030000 ps
CPU time 811.48 seconds
Started Jul 29 04:32:10 PM PDT 24
Finished Jul 29 05:05:22 PM PDT 24
Peak memory 160760 kb
Host smart-90ea18be-3c88-4e4f-8305-709add28afa5
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3232698277 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.3232698277
Directory /workspace/30.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.3286130920
Short name T178
Test name
Test status
Simulation time 336993410000 ps
CPU time 702.16 seconds
Started Jul 29 04:32:14 PM PDT 24
Finished Jul 29 05:00:45 PM PDT 24
Peak memory 160624 kb
Host smart-5e5a9338-6a9f-4f71-90c8-f24686e95eb1
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3286130920 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.3286130920
Directory /workspace/31.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.3183844317
Short name T27
Test name
Test status
Simulation time 336394670000 ps
CPU time 651.17 seconds
Started Jul 29 04:32:21 PM PDT 24
Finished Jul 29 04:59:31 PM PDT 24
Peak memory 160564 kb
Host smart-b2059e86-1e42-4ee6-9f87-5d736380b7a4
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3183844317 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.3183844317
Directory /workspace/32.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.2201542181
Short name T174
Test name
Test status
Simulation time 336898950000 ps
CPU time 874.58 seconds
Started Jul 29 04:32:16 PM PDT 24
Finished Jul 29 05:07:39 PM PDT 24
Peak memory 160636 kb
Host smart-42a4ce70-acd5-4fe5-9a0c-93948587e422
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2201542181 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.2201542181
Directory /workspace/33.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.348285516
Short name T190
Test name
Test status
Simulation time 336608590000 ps
CPU time 770.75 seconds
Started Jul 29 04:32:16 PM PDT 24
Finished Jul 29 05:03:44 PM PDT 24
Peak memory 160668 kb
Host smart-d90fef83-4bf6-4bdd-8181-0f9944458851
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=348285516 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.348285516
Directory /workspace/34.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.4108143866
Short name T197
Test name
Test status
Simulation time 337090750000 ps
CPU time 606.45 seconds
Started Jul 29 04:32:23 PM PDT 24
Finished Jul 29 04:57:29 PM PDT 24
Peak memory 160632 kb
Host smart-3ca8d366-da43-4fb5-9721-782d63634257
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4108143866 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.4108143866
Directory /workspace/35.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.3167953424
Short name T164
Test name
Test status
Simulation time 336332610000 ps
CPU time 730.47 seconds
Started Jul 29 04:32:15 PM PDT 24
Finished Jul 29 05:01:53 PM PDT 24
Peak memory 160560 kb
Host smart-59cc0f17-1672-49ed-bcc2-24e9c9491bff
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3167953424 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.3167953424
Directory /workspace/36.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.2947688363
Short name T195
Test name
Test status
Simulation time 336457350000 ps
CPU time 772.06 seconds
Started Jul 29 04:32:24 PM PDT 24
Finished Jul 29 05:03:50 PM PDT 24
Peak memory 160656 kb
Host smart-3e0366fd-b30c-4b20-bca6-ff730df75942
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2947688363 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.2947688363
Directory /workspace/37.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.362615571
Short name T198
Test name
Test status
Simulation time 336505690000 ps
CPU time 661.1 seconds
Started Jul 29 04:32:16 PM PDT 24
Finished Jul 29 04:59:27 PM PDT 24
Peak memory 160620 kb
Host smart-58a39498-8c1d-4b45-a5f8-0b444b6c2564
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=362615571 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.362615571
Directory /workspace/38.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.2046646919
Short name T175
Test name
Test status
Simulation time 336297910000 ps
CPU time 749.02 seconds
Started Jul 29 04:32:15 PM PDT 24
Finished Jul 29 05:02:39 PM PDT 24
Peak memory 160644 kb
Host smart-c0f5fe8a-0e5c-4e1d-bb37-4db9a7e79c2c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2046646919 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.2046646919
Directory /workspace/39.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.4211681407
Short name T171
Test name
Test status
Simulation time 336511950000 ps
CPU time 820.15 seconds
Started Jul 29 04:25:00 PM PDT 24
Finished Jul 29 04:58:29 PM PDT 24
Peak memory 160604 kb
Host smart-5a5dcbfa-5c2e-40c0-9f2c-7eb2c11abf74
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4211681407 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.4211681407
Directory /workspace/4.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.1207189039
Short name T180
Test name
Test status
Simulation time 336729430000 ps
CPU time 774.37 seconds
Started Jul 29 04:32:15 PM PDT 24
Finished Jul 29 05:03:36 PM PDT 24
Peak memory 160656 kb
Host smart-e640752c-508e-49c7-8294-1ab6cea68372
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1207189039 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.1207189039
Directory /workspace/40.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.3207505855
Short name T22
Test name
Test status
Simulation time 336633810000 ps
CPU time 697.34 seconds
Started Jul 29 04:32:20 PM PDT 24
Finished Jul 29 05:00:51 PM PDT 24
Peak memory 160656 kb
Host smart-64e5040a-0968-4628-853b-62667bd44e4c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3207505855 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.3207505855
Directory /workspace/41.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.3046501612
Short name T165
Test name
Test status
Simulation time 336677510000 ps
CPU time 729.16 seconds
Started Jul 29 04:32:16 PM PDT 24
Finished Jul 29 05:02:10 PM PDT 24
Peak memory 160588 kb
Host smart-e88bbcc3-af3f-45eb-bed7-84162a2694b0
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3046501612 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.3046501612
Directory /workspace/42.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.4005603237
Short name T184
Test name
Test status
Simulation time 336471770000 ps
CPU time 651.35 seconds
Started Jul 29 04:32:24 PM PDT 24
Finished Jul 29 04:58:47 PM PDT 24
Peak memory 160604 kb
Host smart-64960f7a-4e3a-4e80-98a0-d82c74d31594
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4005603237 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.4005603237
Directory /workspace/43.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.3368550933
Short name T168
Test name
Test status
Simulation time 336350610000 ps
CPU time 678.7 seconds
Started Jul 29 04:32:14 PM PDT 24
Finished Jul 29 05:00:11 PM PDT 24
Peak memory 160596 kb
Host smart-d93f38d6-4cbb-4c18-bb90-532befea49c3
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3368550933 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.3368550933
Directory /workspace/44.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.3890347129
Short name T162
Test name
Test status
Simulation time 336400850000 ps
CPU time 753.66 seconds
Started Jul 29 04:32:21 PM PDT 24
Finished Jul 29 05:03:00 PM PDT 24
Peak memory 160644 kb
Host smart-b8b437b8-4507-4a41-855d-d915b3bf98cf
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3890347129 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.3890347129
Directory /workspace/45.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.2645401123
Short name T183
Test name
Test status
Simulation time 336641890000 ps
CPU time 795.98 seconds
Started Jul 29 04:32:14 PM PDT 24
Finished Jul 29 05:04:30 PM PDT 24
Peak memory 160856 kb
Host smart-8bc407af-a6a4-4fd2-b4fe-e6a4060b05f3
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2645401123 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.2645401123
Directory /workspace/46.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.1372255245
Short name T29
Test name
Test status
Simulation time 336644070000 ps
CPU time 817.61 seconds
Started Jul 29 04:32:14 PM PDT 24
Finished Jul 29 05:05:47 PM PDT 24
Peak memory 160768 kb
Host smart-a8f318a5-86ad-457d-a160-e7bc2e0be8b8
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1372255245 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.1372255245
Directory /workspace/47.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1684101379
Short name T163
Test name
Test status
Simulation time 336541410000 ps
CPU time 657.71 seconds
Started Jul 29 04:32:16 PM PDT 24
Finished Jul 29 04:59:17 PM PDT 24
Peak memory 160644 kb
Host smart-433cd7be-73c0-4720-b269-51f67452621d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1684101379 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.1684101379
Directory /workspace/48.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.3015655902
Short name T161
Test name
Test status
Simulation time 336340330000 ps
CPU time 774.7 seconds
Started Jul 29 04:32:17 PM PDT 24
Finished Jul 29 05:03:41 PM PDT 24
Peak memory 160620 kb
Host smart-da37cd1d-ae77-4d68-a50d-b38fd79c4f88
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3015655902 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.3015655902
Directory /workspace/49.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.2573581838
Short name T23
Test name
Test status
Simulation time 336752810000 ps
CPU time 749.22 seconds
Started Jul 29 04:24:46 PM PDT 24
Finished Jul 29 04:55:45 PM PDT 24
Peak memory 159404 kb
Host smart-c295ea50-c51f-4199-98cc-32cee18cb111
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2573581838 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.2573581838
Directory /workspace/5.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.1260553494
Short name T191
Test name
Test status
Simulation time 337069930000 ps
CPU time 681.94 seconds
Started Jul 29 04:20:30 PM PDT 24
Finished Jul 29 04:48:49 PM PDT 24
Peak memory 160616 kb
Host smart-07602439-a066-498b-8bae-73f5042dceda
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1260553494 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.1260553494
Directory /workspace/6.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.506886287
Short name T21
Test name
Test status
Simulation time 336713390000 ps
CPU time 809.05 seconds
Started Jul 29 04:20:29 PM PDT 24
Finished Jul 29 04:53:59 PM PDT 24
Peak memory 160500 kb
Host smart-c6013f0a-18fb-46b8-90d7-6c9ba4b4e8ae
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=506886287 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.506886287
Directory /workspace/7.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.1800461744
Short name T173
Test name
Test status
Simulation time 336603850000 ps
CPU time 731.21 seconds
Started Jul 29 04:25:46 PM PDT 24
Finished Jul 29 04:56:04 PM PDT 24
Peak memory 159828 kb
Host smart-bed90367-e164-4d28-a0b4-81420b16af06
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1800461744 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.1800461744
Directory /workspace/8.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.101518991
Short name T26
Test name
Test status
Simulation time 336670690000 ps
CPU time 814.52 seconds
Started Jul 29 04:21:15 PM PDT 24
Finished Jul 29 04:54:48 PM PDT 24
Peak memory 160660 kb
Host smart-e96cf7f7-5252-4a03-990d-e7c92211f7eb
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=101518991 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.101518991
Directory /workspace/9.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.3264023586
Short name T160
Test name
Test status
Simulation time 1486370000 ps
CPU time 4.51 seconds
Started Jul 29 04:23:19 PM PDT 24
Finished Jul 29 04:23:29 PM PDT 24
Peak memory 164696 kb
Host smart-fea9c9f8-c2cf-4c81-bb66-b1498a26c59d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3264023586 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.3264023586
Directory /workspace/0.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.789257990
Short name T122
Test name
Test status
Simulation time 1296630000 ps
CPU time 3.78 seconds
Started Jul 29 04:25:18 PM PDT 24
Finished Jul 29 04:25:27 PM PDT 24
Peak memory 163892 kb
Host smart-f6398de3-840c-45cd-adfa-cef6c1e55f87
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=789257990 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.789257990
Directory /workspace/1.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.1122781341
Short name T159
Test name
Test status
Simulation time 1474750000 ps
CPU time 3.27 seconds
Started Jul 29 04:25:13 PM PDT 24
Finished Jul 29 04:25:21 PM PDT 24
Peak memory 164404 kb
Host smart-606081eb-2347-4293-a5f2-eb5bf9c54056
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1122781341 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.1122781341
Directory /workspace/10.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.1338766032
Short name T134
Test name
Test status
Simulation time 1518970000 ps
CPU time 3.55 seconds
Started Jul 29 04:25:45 PM PDT 24
Finished Jul 29 04:25:53 PM PDT 24
Peak memory 164544 kb
Host smart-c28c1081-043c-4c75-a1f3-71d433435fda
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1338766032 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.1338766032
Directory /workspace/11.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.2602070960
Short name T151
Test name
Test status
Simulation time 1549390000 ps
CPU time 3.58 seconds
Started Jul 29 04:25:45 PM PDT 24
Finished Jul 29 04:25:53 PM PDT 24
Peak memory 164516 kb
Host smart-65c15923-6004-4c12-b1b1-49d7ab98c9f7
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2602070960 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.2602070960
Directory /workspace/12.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.100046999
Short name T130
Test name
Test status
Simulation time 1452930000 ps
CPU time 3.12 seconds
Started Jul 29 04:24:52 PM PDT 24
Finished Jul 29 04:24:59 PM PDT 24
Peak memory 164076 kb
Host smart-c7c2e73d-7775-44fd-8bf8-935204b672e6
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=100046999 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.100046999
Directory /workspace/13.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.606055491
Short name T143
Test name
Test status
Simulation time 1453930000 ps
CPU time 3.14 seconds
Started Jul 29 04:25:42 PM PDT 24
Finished Jul 29 04:25:49 PM PDT 24
Peak memory 164732 kb
Host smart-c42d21fd-4624-496c-8f0a-51ab978614d2
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=606055491 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.606055491
Directory /workspace/14.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.4335764
Short name T120
Test name
Test status
Simulation time 1422430000 ps
CPU time 2.91 seconds
Started Jul 29 04:25:30 PM PDT 24
Finished Jul 29 04:25:36 PM PDT 24
Peak memory 164572 kb
Host smart-0b2e739a-437f-49dd-916b-40ab35b9aa37
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4335764 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.4335764
Directory /workspace/15.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.2546955964
Short name T118
Test name
Test status
Simulation time 1471670000 ps
CPU time 4.95 seconds
Started Jul 29 04:25:02 PM PDT 24
Finished Jul 29 04:25:12 PM PDT 24
Peak memory 164692 kb
Host smart-cf0f0f58-775b-4008-b558-49df8c99072a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2546955964 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.2546955964
Directory /workspace/16.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.3807516424
Short name T132
Test name
Test status
Simulation time 1501270000 ps
CPU time 3.78 seconds
Started Jul 29 04:25:27 PM PDT 24
Finished Jul 29 04:25:35 PM PDT 24
Peak memory 164584 kb
Host smart-67d7009c-4596-46d0-9440-41038683e630
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3807516424 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.3807516424
Directory /workspace/17.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.4153146122
Short name T115
Test name
Test status
Simulation time 1316810000 ps
CPU time 2.74 seconds
Started Jul 29 04:25:31 PM PDT 24
Finished Jul 29 04:25:37 PM PDT 24
Peak memory 164536 kb
Host smart-b3576f3e-7bd2-4019-bf79-d6dcbeeea96f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4153146122 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.4153146122
Directory /workspace/18.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.3920260780
Short name T128
Test name
Test status
Simulation time 1480290000 ps
CPU time 3.58 seconds
Started Jul 29 04:25:41 PM PDT 24
Finished Jul 29 04:25:50 PM PDT 24
Peak memory 164576 kb
Host smart-d46286bb-6a07-4ca0-9b8c-c297e251db44
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3920260780 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.3920260780
Directory /workspace/19.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.88112380
Short name T141
Test name
Test status
Simulation time 1384130000 ps
CPU time 4.05 seconds
Started Jul 29 04:25:18 PM PDT 24
Finished Jul 29 04:25:28 PM PDT 24
Peak memory 162372 kb
Host smart-8a3e17b4-93a1-4f97-a261-8d1c7397fa21
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=88112380 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.88112380
Directory /workspace/2.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.1177139010
Short name T135
Test name
Test status
Simulation time 1626850000 ps
CPU time 4.68 seconds
Started Jul 29 04:25:26 PM PDT 24
Finished Jul 29 04:25:36 PM PDT 24
Peak memory 164584 kb
Host smart-68c9dde9-e835-49ed-9627-bfa7f675682a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1177139010 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.1177139010
Directory /workspace/20.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.1835677130
Short name T133
Test name
Test status
Simulation time 1528070000 ps
CPU time 3.66 seconds
Started Jul 29 04:21:38 PM PDT 24
Finished Jul 29 04:21:46 PM PDT 24
Peak memory 164788 kb
Host smart-ccc54c94-f258-4e4f-9df9-4e2d94d66c5c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1835677130 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.1835677130
Directory /workspace/21.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.1022501819
Short name T138
Test name
Test status
Simulation time 1405070000 ps
CPU time 3.12 seconds
Started Jul 29 04:25:25 PM PDT 24
Finished Jul 29 04:25:32 PM PDT 24
Peak memory 164584 kb
Host smart-4a8e710b-98b7-44fa-bc2f-ec460c1d4db4
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1022501819 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.1022501819
Directory /workspace/22.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.3817519987
Short name T137
Test name
Test status
Simulation time 1303330000 ps
CPU time 3.51 seconds
Started Jul 29 04:26:10 PM PDT 24
Finished Jul 29 04:26:18 PM PDT 24
Peak memory 164588 kb
Host smart-658e0213-3f87-45f9-a45b-848f6aae30f2
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3817519987 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.3817519987
Directory /workspace/23.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.594047791
Short name T126
Test name
Test status
Simulation time 1582670000 ps
CPU time 4.54 seconds
Started Jul 29 04:20:35 PM PDT 24
Finished Jul 29 04:20:45 PM PDT 24
Peak memory 164788 kb
Host smart-8f2e3db0-09cc-4be1-a660-8555e2983d7f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=594047791 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.594047791
Directory /workspace/24.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.4020999614
Short name T148
Test name
Test status
Simulation time 1583790000 ps
CPU time 6 seconds
Started Jul 29 04:22:58 PM PDT 24
Finished Jul 29 04:23:11 PM PDT 24
Peak memory 164704 kb
Host smart-5116f24a-fc68-4de7-b271-d502bedeef46
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4020999614 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.4020999614
Directory /workspace/25.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.1911523976
Short name T124
Test name
Test status
Simulation time 1520770000 ps
CPU time 3.72 seconds
Started Jul 29 04:23:48 PM PDT 24
Finished Jul 29 04:23:56 PM PDT 24
Peak memory 164860 kb
Host smart-09dad613-d924-4a5e-beac-b5fe5b3cd6ce
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1911523976 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.1911523976
Directory /workspace/26.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.3590815686
Short name T153
Test name
Test status
Simulation time 1336010000 ps
CPU time 3.86 seconds
Started Jul 29 04:23:19 PM PDT 24
Finished Jul 29 04:23:28 PM PDT 24
Peak memory 164748 kb
Host smart-431315ca-10d4-4674-b4a7-43ea70b427f7
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3590815686 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.3590815686
Directory /workspace/27.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.1547748389
Short name T154
Test name
Test status
Simulation time 1384790000 ps
CPU time 3.74 seconds
Started Jul 29 04:20:30 PM PDT 24
Finished Jul 29 04:20:38 PM PDT 24
Peak memory 164784 kb
Host smart-cfca12ba-d402-4d41-97c8-7a0616bf568e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1547748389 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.1547748389
Directory /workspace/28.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.618889564
Short name T144
Test name
Test status
Simulation time 1522270000 ps
CPU time 3.22 seconds
Started Jul 29 04:25:03 PM PDT 24
Finished Jul 29 04:25:11 PM PDT 24
Peak memory 163604 kb
Host smart-198befd9-fd6f-4d10-aeea-e215b5591283
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=618889564 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.618889564
Directory /workspace/29.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.2570741006
Short name T125
Test name
Test status
Simulation time 1471490000 ps
CPU time 3.14 seconds
Started Jul 29 04:25:28 PM PDT 24
Finished Jul 29 04:25:35 PM PDT 24
Peak memory 164656 kb
Host smart-9c63cc60-1c21-46f0-bcb5-81670a58e4a2
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2570741006 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.2570741006
Directory /workspace/3.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.1088074819
Short name T149
Test name
Test status
Simulation time 1488830000 ps
CPU time 5.59 seconds
Started Jul 29 04:21:07 PM PDT 24
Finished Jul 29 04:21:20 PM PDT 24
Peak memory 164704 kb
Host smart-940b3cac-b3da-497b-950f-fff5a537dad5
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1088074819 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.1088074819
Directory /workspace/30.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.2984926834
Short name T145
Test name
Test status
Simulation time 1423810000 ps
CPU time 2.7 seconds
Started Jul 29 04:25:31 PM PDT 24
Finished Jul 29 04:25:38 PM PDT 24
Peak memory 164536 kb
Host smart-8d162639-580c-477c-aaf7-5879c1950130
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2984926834 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.2984926834
Directory /workspace/31.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.2379925048
Short name T127
Test name
Test status
Simulation time 1290990000 ps
CPU time 3.51 seconds
Started Jul 29 04:21:25 PM PDT 24
Finished Jul 29 04:21:33 PM PDT 24
Peak memory 164804 kb
Host smart-a79e7231-dc09-41eb-a866-6fc8ce3c08ce
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2379925048 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.2379925048
Directory /workspace/32.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.3479088999
Short name T136
Test name
Test status
Simulation time 1441670000 ps
CPU time 2.81 seconds
Started Jul 29 04:25:40 PM PDT 24
Finished Jul 29 04:25:47 PM PDT 24
Peak memory 164692 kb
Host smart-141dfc1b-8f09-4753-8be7-2d971d445cbc
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3479088999 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.3479088999
Directory /workspace/33.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.2922934641
Short name T157
Test name
Test status
Simulation time 1526870000 ps
CPU time 3.7 seconds
Started Jul 29 04:21:08 PM PDT 24
Finished Jul 29 04:21:17 PM PDT 24
Peak memory 164860 kb
Host smart-d37ffab3-9ed6-4e92-ad33-9d920de06a5c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2922934641 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.2922934641
Directory /workspace/34.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.179494083
Short name T123
Test name
Test status
Simulation time 1519890000 ps
CPU time 4.66 seconds
Started Jul 29 04:25:01 PM PDT 24
Finished Jul 29 04:25:11 PM PDT 24
Peak memory 164720 kb
Host smart-97fe05ec-f83d-4af0-b1dc-799e13ee3aa7
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=179494083 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.179494083
Directory /workspace/35.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.1910488608
Short name T142
Test name
Test status
Simulation time 1573210000 ps
CPU time 4.34 seconds
Started Jul 29 04:22:23 PM PDT 24
Finished Jul 29 04:22:32 PM PDT 24
Peak memory 164860 kb
Host smart-82904a71-4ace-45d8-aac6-90c2fa54cd48
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1910488608 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.1910488608
Directory /workspace/36.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1828414678
Short name T112
Test name
Test status
Simulation time 1408950000 ps
CPU time 4.6 seconds
Started Jul 29 04:25:56 PM PDT 24
Finished Jul 29 04:26:07 PM PDT 24
Peak memory 164460 kb
Host smart-586f4735-2b2b-4ba5-8e8a-20bbd936054b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1828414678 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.1828414678
Directory /workspace/37.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.3862313521
Short name T158
Test name
Test status
Simulation time 1391110000 ps
CPU time 4.23 seconds
Started Jul 29 04:20:24 PM PDT 24
Finished Jul 29 04:20:34 PM PDT 24
Peak memory 164700 kb
Host smart-722d5703-c3b4-4969-8685-9319208b09e3
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3862313521 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.3862313521
Directory /workspace/38.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.107885814
Short name T152
Test name
Test status
Simulation time 1494910000 ps
CPU time 3.64 seconds
Started Jul 29 04:25:25 PM PDT 24
Finished Jul 29 04:25:34 PM PDT 24
Peak memory 164748 kb
Host smart-7d9ef7b1-3b8a-4d2e-8d18-5ed47049629b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=107885814 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.107885814
Directory /workspace/39.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.1355458779
Short name T147
Test name
Test status
Simulation time 1357170000 ps
CPU time 4.74 seconds
Started Jul 29 04:21:11 PM PDT 24
Finished Jul 29 04:21:21 PM PDT 24
Peak memory 164692 kb
Host smart-d1e84671-6167-4fdb-9f96-67c611871cc6
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1355458779 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.1355458779
Directory /workspace/4.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.3018846702
Short name T116
Test name
Test status
Simulation time 1088790000 ps
CPU time 4.11 seconds
Started Jul 29 04:32:08 PM PDT 24
Finished Jul 29 04:32:16 PM PDT 24
Peak memory 164700 kb
Host smart-ae793c55-f1dd-4d72-886b-2d33544f4360
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3018846702 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.3018846702
Directory /workspace/40.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.3547089899
Short name T117
Test name
Test status
Simulation time 1541630000 ps
CPU time 2.95 seconds
Started Jul 29 04:32:14 PM PDT 24
Finished Jul 29 04:32:20 PM PDT 24
Peak memory 164684 kb
Host smart-6a4d8dda-5f12-4110-bb59-c60619a50940
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3547089899 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.3547089899
Directory /workspace/41.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.60692126
Short name T131
Test name
Test status
Simulation time 1404210000 ps
CPU time 4.66 seconds
Started Jul 29 04:32:11 PM PDT 24
Finished Jul 29 04:32:21 PM PDT 24
Peak memory 164708 kb
Host smart-0a99097d-14a9-450e-a0ce-b21e469170b2
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=60692126 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.60692126
Directory /workspace/42.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.3893431093
Short name T121
Test name
Test status
Simulation time 1480610000 ps
CPU time 4.61 seconds
Started Jul 29 04:32:10 PM PDT 24
Finished Jul 29 04:32:20 PM PDT 24
Peak memory 164788 kb
Host smart-78156d24-49cc-4367-be1f-099238083b76
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3893431093 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.3893431093
Directory /workspace/43.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.2918991361
Short name T111
Test name
Test status
Simulation time 1342070000 ps
CPU time 3.7 seconds
Started Jul 29 04:32:10 PM PDT 24
Finished Jul 29 04:32:18 PM PDT 24
Peak memory 164732 kb
Host smart-ed222475-f515-401c-a95f-cc6428d41acb
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2918991361 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.2918991361
Directory /workspace/44.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.3612915471
Short name T140
Test name
Test status
Simulation time 1537170000 ps
CPU time 4.21 seconds
Started Jul 29 04:32:11 PM PDT 24
Finished Jul 29 04:32:21 PM PDT 24
Peak memory 164788 kb
Host smart-933d465d-86f5-4e3c-b37f-ed16541e0dfc
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3612915471 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.3612915471
Directory /workspace/45.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.2534516003
Short name T156
Test name
Test status
Simulation time 1287270000 ps
CPU time 3.51 seconds
Started Jul 29 04:32:13 PM PDT 24
Finished Jul 29 04:32:21 PM PDT 24
Peak memory 164732 kb
Host smart-b0b410de-0b7a-4bba-aebc-9fe2545f3c23
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2534516003 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.2534516003
Directory /workspace/46.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.1986461717
Short name T113
Test name
Test status
Simulation time 1507450000 ps
CPU time 5.85 seconds
Started Jul 29 04:32:10 PM PDT 24
Finished Jul 29 04:32:22 PM PDT 24
Peak memory 164668 kb
Host smart-1f588e4f-b9e4-4b2d-9937-cca182c54c0c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1986461717 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.1986461717
Directory /workspace/47.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.3075502954
Short name T119
Test name
Test status
Simulation time 1474470000 ps
CPU time 4.48 seconds
Started Jul 29 04:32:11 PM PDT 24
Finished Jul 29 04:32:21 PM PDT 24
Peak memory 164796 kb
Host smart-0fd12cfa-13d8-4f3d-ada3-0797224c01d7
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3075502954 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.3075502954
Directory /workspace/48.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.4285558500
Short name T155
Test name
Test status
Simulation time 1400710000 ps
CPU time 2.88 seconds
Started Jul 29 04:32:10 PM PDT 24
Finished Jul 29 04:32:16 PM PDT 24
Peak memory 164700 kb
Host smart-8edb629b-3ba2-46c4-8b17-7340c31fb501
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4285558500 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.4285558500
Directory /workspace/49.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.1673090089
Short name T139
Test name
Test status
Simulation time 1317790000 ps
CPU time 3.43 seconds
Started Jul 29 04:25:15 PM PDT 24
Finished Jul 29 04:25:23 PM PDT 24
Peak memory 164676 kb
Host smart-0cda2a99-9200-41bc-ace6-3453916edc17
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1673090089 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.1673090089
Directory /workspace/5.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.1662263878
Short name T129
Test name
Test status
Simulation time 1136370000 ps
CPU time 2.74 seconds
Started Jul 29 04:20:33 PM PDT 24
Finished Jul 29 04:20:38 PM PDT 24
Peak memory 164780 kb
Host smart-5a99a043-0bc4-42e6-b0ef-9135f6caeb98
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1662263878 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.1662263878
Directory /workspace/6.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.2769215417
Short name T114
Test name
Test status
Simulation time 1170890000 ps
CPU time 3.29 seconds
Started Jul 29 04:25:37 PM PDT 24
Finished Jul 29 04:25:44 PM PDT 24
Peak memory 164500 kb
Host smart-be1e9437-3415-4395-8b10-4d3b90dcdedd
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2769215417 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.2769215417
Directory /workspace/7.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.85133099
Short name T150
Test name
Test status
Simulation time 1367150000 ps
CPU time 5.23 seconds
Started Jul 29 04:23:47 PM PDT 24
Finished Jul 29 04:23:59 PM PDT 24
Peak memory 164644 kb
Host smart-f427f956-aff6-49f3-a4df-2b28fae58bdc
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=85133099 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.85133099
Directory /workspace/8.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.979645572
Short name T146
Test name
Test status
Simulation time 1473950000 ps
CPU time 3.98 seconds
Started Jul 29 04:25:36 PM PDT 24
Finished Jul 29 04:25:45 PM PDT 24
Peak memory 164496 kb
Host smart-79693d31-02e3-4c49-b547-78c202870b6d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=979645572 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.979645572
Directory /workspace/9.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.2439466604
Short name T32
Test name
Test status
Simulation time 1560270000 ps
CPU time 3.5 seconds
Started Jul 29 04:25:28 PM PDT 24
Finished Jul 29 04:25:36 PM PDT 24
Peak memory 164324 kb
Host smart-6c92c646-a5f6-4d3f-b531-6c86d023c158
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2439466604 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.2439466604
Directory /workspace/0.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.3194085091
Short name T52
Test name
Test status
Simulation time 1542070000 ps
CPU time 3.28 seconds
Started Jul 29 04:25:18 PM PDT 24
Finished Jul 29 04:25:26 PM PDT 24
Peak memory 164696 kb
Host smart-c74f2376-47df-484c-b0f9-fc1191c28e3f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3194085091 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.3194085091
Directory /workspace/1.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.2188389130
Short name T39
Test name
Test status
Simulation time 1504450000 ps
CPU time 4.54 seconds
Started Jul 29 04:21:26 PM PDT 24
Finished Jul 29 04:21:36 PM PDT 24
Peak memory 164788 kb
Host smart-9212f3ee-df64-4c73-96dd-c990eb0c0b42
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2188389130 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.2188389130
Directory /workspace/10.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.358727196
Short name T37
Test name
Test status
Simulation time 1158990000 ps
CPU time 3.08 seconds
Started Jul 29 04:24:33 PM PDT 24
Finished Jul 29 04:24:40 PM PDT 24
Peak memory 164872 kb
Host smart-264e822b-28d3-496e-945c-3b8ebad047ce
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=358727196 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.358727196
Directory /workspace/11.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.2594139888
Short name T51
Test name
Test status
Simulation time 1366690000 ps
CPU time 3.63 seconds
Started Jul 29 04:25:37 PM PDT 24
Finished Jul 29 04:25:45 PM PDT 24
Peak memory 164524 kb
Host smart-2e3eeef7-5a50-4559-a8ff-144c55896cf9
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2594139888 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.2594139888
Directory /workspace/12.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.3171687898
Short name T8
Test name
Test status
Simulation time 1455490000 ps
CPU time 3.19 seconds
Started Jul 29 04:25:47 PM PDT 24
Finished Jul 29 04:25:54 PM PDT 24
Peak memory 164580 kb
Host smart-c08df902-aa89-4f1a-ba97-0136cb20cdcd
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3171687898 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.3171687898
Directory /workspace/14.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.818443652
Short name T48
Test name
Test status
Simulation time 1458250000 ps
CPU time 3.92 seconds
Started Jul 29 04:23:27 PM PDT 24
Finished Jul 29 04:23:36 PM PDT 24
Peak memory 164792 kb
Host smart-ec9dd44e-49c7-4cb0-989f-2f316893757d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=818443652 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.818443652
Directory /workspace/15.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.2366406034
Short name T13
Test name
Test status
Simulation time 1270530000 ps
CPU time 3.32 seconds
Started Jul 29 04:26:10 PM PDT 24
Finished Jul 29 04:26:18 PM PDT 24
Peak memory 164676 kb
Host smart-ab0db7ed-00f2-4de5-aed9-61372af8218f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2366406034 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.2366406034
Directory /workspace/16.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.2423614373
Short name T57
Test name
Test status
Simulation time 1466230000 ps
CPU time 3.5 seconds
Started Jul 29 04:21:39 PM PDT 24
Finished Jul 29 04:21:46 PM PDT 24
Peak memory 164860 kb
Host smart-533a706d-69e6-46b7-ab0d-0d7b270d7fcb
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2423614373 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.2423614373
Directory /workspace/17.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.1942313824
Short name T3
Test name
Test status
Simulation time 1269110000 ps
CPU time 2.83 seconds
Started Jul 29 04:24:10 PM PDT 24
Finished Jul 29 04:24:16 PM PDT 24
Peak memory 164864 kb
Host smart-4aa93a3f-da2e-4c5a-8604-720b9620ba54
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1942313824 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.1942313824
Directory /workspace/18.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.3196743476
Short name T63
Test name
Test status
Simulation time 1473410000 ps
CPU time 5.15 seconds
Started Jul 29 04:21:41 PM PDT 24
Finished Jul 29 04:21:52 PM PDT 24
Peak memory 164784 kb
Host smart-a02501f9-6844-4990-bb85-3267c698dc60
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3196743476 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.3196743476
Directory /workspace/19.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.2264837233
Short name T64
Test name
Test status
Simulation time 1513610000 ps
CPU time 4.37 seconds
Started Jul 29 04:21:05 PM PDT 24
Finished Jul 29 04:21:14 PM PDT 24
Peak memory 164784 kb
Host smart-1ab8188e-e45c-4341-8977-fba74f9d45a1
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2264837233 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.2264837233
Directory /workspace/2.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.3210451981
Short name T46
Test name
Test status
Simulation time 1357010000 ps
CPU time 3.8 seconds
Started Jul 29 04:25:51 PM PDT 24
Finished Jul 29 04:26:00 PM PDT 24
Peak memory 164792 kb
Host smart-a49352d2-424a-47a7-bd0e-1b40ae3bbf49
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3210451981 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.3210451981
Directory /workspace/20.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.617572015
Short name T10
Test name
Test status
Simulation time 1596130000 ps
CPU time 3.58 seconds
Started Jul 29 04:20:57 PM PDT 24
Finished Jul 29 04:21:05 PM PDT 24
Peak memory 164736 kb
Host smart-d3058a1d-9d46-4451-acfd-2502e24260c5
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=617572015 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.617572015
Directory /workspace/21.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.3784195198
Short name T42
Test name
Test status
Simulation time 1503070000 ps
CPU time 3.42 seconds
Started Jul 29 04:25:22 PM PDT 24
Finished Jul 29 04:25:30 PM PDT 24
Peak memory 163228 kb
Host smart-9a733867-6c3e-4a4e-872e-ad8a1774bab3
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3784195198 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.3784195198
Directory /workspace/22.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.867154412
Short name T49
Test name
Test status
Simulation time 1564370000 ps
CPU time 5.15 seconds
Started Jul 29 04:21:47 PM PDT 24
Finished Jul 29 04:21:58 PM PDT 24
Peak memory 164752 kb
Host smart-3aa160d0-7c96-48b2-af03-8e9dc86d6c64
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=867154412 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.867154412
Directory /workspace/23.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.3769481354
Short name T11
Test name
Test status
Simulation time 1562430000 ps
CPU time 3.48 seconds
Started Jul 29 04:25:33 PM PDT 24
Finished Jul 29 04:25:41 PM PDT 24
Peak memory 164392 kb
Host smart-76792382-6df1-4e5b-b578-f85f350eca78
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3769481354 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.3769481354
Directory /workspace/24.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.524756962
Short name T68
Test name
Test status
Simulation time 1409950000 ps
CPU time 3.21 seconds
Started Jul 29 04:25:40 PM PDT 24
Finished Jul 29 04:25:47 PM PDT 24
Peak memory 164700 kb
Host smart-727f0b59-3463-4705-a790-bc649f000f6f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=524756962 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.524756962
Directory /workspace/25.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.3620110019
Short name T62
Test name
Test status
Simulation time 1528950000 ps
CPU time 3.89 seconds
Started Jul 29 04:23:20 PM PDT 24
Finished Jul 29 04:23:29 PM PDT 24
Peak memory 164748 kb
Host smart-e288c625-64d7-4833-8470-4bf11fd260c5
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3620110019 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.3620110019
Directory /workspace/26.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.790859926
Short name T43
Test name
Test status
Simulation time 1358730000 ps
CPU time 3.99 seconds
Started Jul 29 04:25:51 PM PDT 24
Finished Jul 29 04:26:00 PM PDT 24
Peak memory 164784 kb
Host smart-db9d5356-9a50-414d-b6de-b2d986a3a8a1
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=790859926 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.790859926
Directory /workspace/27.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.4260950372
Short name T36
Test name
Test status
Simulation time 1509490000 ps
CPU time 3.76 seconds
Started Jul 29 04:25:47 PM PDT 24
Finished Jul 29 04:25:55 PM PDT 24
Peak memory 164536 kb
Host smart-2442fec3-691b-47f3-be1a-1e7e1921256f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4260950372 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.4260950372
Directory /workspace/28.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.871988018
Short name T50
Test name
Test status
Simulation time 1222230000 ps
CPU time 3.77 seconds
Started Jul 29 04:25:37 PM PDT 24
Finished Jul 29 04:25:46 PM PDT 24
Peak memory 163416 kb
Host smart-52274f3b-e6b7-452f-aabb-783356f403da
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=871988018 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.871988018
Directory /workspace/29.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.2641001736
Short name T53
Test name
Test status
Simulation time 1636450000 ps
CPU time 3.87 seconds
Started Jul 29 04:24:56 PM PDT 24
Finished Jul 29 04:25:05 PM PDT 24
Peak memory 163508 kb
Host smart-9f9f8412-20c3-4faa-9646-7a3b0c257c89
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2641001736 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.2641001736
Directory /workspace/3.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.2581025241
Short name T9
Test name
Test status
Simulation time 1505510000 ps
CPU time 4.16 seconds
Started Jul 29 04:23:11 PM PDT 24
Finished Jul 29 04:23:21 PM PDT 24
Peak memory 164784 kb
Host smart-a83b262d-f5ef-42b4-987d-06d66dc8531e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2581025241 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.2581025241
Directory /workspace/30.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.1602910103
Short name T38
Test name
Test status
Simulation time 1591230000 ps
CPU time 4.5 seconds
Started Jul 29 04:25:17 PM PDT 24
Finished Jul 29 04:25:27 PM PDT 24
Peak memory 164696 kb
Host smart-749b0819-92be-4e9a-8202-5f6a3898bf9f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1602910103 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.1602910103
Directory /workspace/31.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.3695346095
Short name T34
Test name
Test status
Simulation time 1014650000 ps
CPU time 2.8 seconds
Started Jul 29 04:19:43 PM PDT 24
Finished Jul 29 04:19:49 PM PDT 24
Peak memory 164128 kb
Host smart-461ea236-28f6-4f18-b1bd-c106e79a6981
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3695346095 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.3695346095
Directory /workspace/32.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.3339358340
Short name T65
Test name
Test status
Simulation time 1451230000 ps
CPU time 3.11 seconds
Started Jul 29 04:25:24 PM PDT 24
Finished Jul 29 04:25:31 PM PDT 24
Peak memory 163560 kb
Host smart-a6fa200d-e019-43d2-a13f-738d9888b01a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3339358340 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.3339358340
Directory /workspace/33.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.3158183532
Short name T31
Test name
Test status
Simulation time 1549450000 ps
CPU time 4.84 seconds
Started Jul 29 04:25:02 PM PDT 24
Finished Jul 29 04:25:13 PM PDT 24
Peak memory 164728 kb
Host smart-8944a62c-9de3-4399-88ab-1aaede1a8ee6
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3158183532 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.3158183532
Directory /workspace/34.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.1295816044
Short name T59
Test name
Test status
Simulation time 1161170000 ps
CPU time 3.81 seconds
Started Jul 29 04:25:56 PM PDT 24
Finished Jul 29 04:26:05 PM PDT 24
Peak memory 164464 kb
Host smart-fa8326f6-d9b1-4f48-b388-daaa2a041402
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1295816044 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.1295816044
Directory /workspace/35.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.1472536310
Short name T58
Test name
Test status
Simulation time 1554170000 ps
CPU time 4.7 seconds
Started Jul 29 04:21:56 PM PDT 24
Finished Jul 29 04:22:06 PM PDT 24
Peak memory 164800 kb
Host smart-a925bc63-9758-4a03-8329-e5c00e6c4ea5
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1472536310 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.1472536310
Directory /workspace/36.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.753975591
Short name T45
Test name
Test status
Simulation time 1396010000 ps
CPU time 4.28 seconds
Started Jul 29 04:25:50 PM PDT 24
Finished Jul 29 04:25:59 PM PDT 24
Peak memory 164696 kb
Host smart-933a96b2-cd6a-4777-a03c-ee633a220b7e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=753975591 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.753975591
Directory /workspace/37.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.1305685793
Short name T55
Test name
Test status
Simulation time 1576930000 ps
CPU time 3.96 seconds
Started Jul 29 04:22:16 PM PDT 24
Finished Jul 29 04:22:25 PM PDT 24
Peak memory 164788 kb
Host smart-5aed0451-1af0-4d7b-bacf-5547e4597807
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1305685793 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.1305685793
Directory /workspace/38.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.3921898963
Short name T69
Test name
Test status
Simulation time 1531190000 ps
CPU time 4.58 seconds
Started Jul 29 04:25:50 PM PDT 24
Finished Jul 29 04:26:01 PM PDT 24
Peak memory 164696 kb
Host smart-72edc911-f9f2-45f5-b729-00f43db7411c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3921898963 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.3921898963
Directory /workspace/39.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.973472342
Short name T41
Test name
Test status
Simulation time 1469790000 ps
CPU time 4.12 seconds
Started Jul 29 04:25:18 PM PDT 24
Finished Jul 29 04:25:28 PM PDT 24
Peak memory 162596 kb
Host smart-6577571a-c33f-4bdf-bceb-33645df61b0e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=973472342 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.973472342
Directory /workspace/4.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.429777726
Short name T47
Test name
Test status
Simulation time 1523650000 ps
CPU time 5.14 seconds
Started Jul 29 04:22:35 PM PDT 24
Finished Jul 29 04:22:46 PM PDT 24
Peak memory 164792 kb
Host smart-2a1e4267-da09-47f9-8beb-e26145671ae3
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=429777726 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.429777726
Directory /workspace/40.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.1314837137
Short name T44
Test name
Test status
Simulation time 1291070000 ps
CPU time 3.35 seconds
Started Jul 29 04:25:25 PM PDT 24
Finished Jul 29 04:25:33 PM PDT 24
Peak memory 164720 kb
Host smart-f1c46d72-feaf-44d7-8080-c7f334320e5e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1314837137 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.1314837137
Directory /workspace/41.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.3347740906
Short name T70
Test name
Test status
Simulation time 1497190000 ps
CPU time 2.94 seconds
Started Jul 29 04:25:07 PM PDT 24
Finished Jul 29 04:25:14 PM PDT 24
Peak memory 164392 kb
Host smart-6be00e3f-cb87-4d20-983b-d5039ada6c84
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3347740906 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.3347740906
Directory /workspace/42.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.3621802691
Short name T35
Test name
Test status
Simulation time 1380110000 ps
CPU time 3.31 seconds
Started Jul 29 04:20:20 PM PDT 24
Finished Jul 29 04:20:28 PM PDT 24
Peak memory 164772 kb
Host smart-65a8f14a-ff44-459b-aae3-f994344fcfc7
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3621802691 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.3621802691
Directory /workspace/43.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.660412018
Short name T12
Test name
Test status
Simulation time 1401830000 ps
CPU time 4.06 seconds
Started Jul 29 04:21:57 PM PDT 24
Finished Jul 29 04:22:06 PM PDT 24
Peak memory 164804 kb
Host smart-a4a3a394-5cfa-4b67-bc10-9effb89efb73
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=660412018 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.660412018
Directory /workspace/44.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.2015580143
Short name T61
Test name
Test status
Simulation time 1520910000 ps
CPU time 3.89 seconds
Started Jul 29 04:25:01 PM PDT 24
Finished Jul 29 04:25:10 PM PDT 24
Peak memory 163436 kb
Host smart-2614b71b-bf3f-4f8f-8ddc-8472b96177ef
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2015580143 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.2015580143
Directory /workspace/45.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.1558637298
Short name T56
Test name
Test status
Simulation time 1338470000 ps
CPU time 3.64 seconds
Started Jul 29 04:25:02 PM PDT 24
Finished Jul 29 04:25:10 PM PDT 24
Peak memory 164488 kb
Host smart-257177b9-7267-4402-9563-75f29683f853
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1558637298 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.1558637298
Directory /workspace/46.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.871354068
Short name T66
Test name
Test status
Simulation time 1329810000 ps
CPU time 3.87 seconds
Started Jul 29 04:21:01 PM PDT 24
Finished Jul 29 04:21:09 PM PDT 24
Peak memory 164692 kb
Host smart-50186519-0215-49f1-8620-a0791d8a9b2c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=871354068 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.871354068
Directory /workspace/47.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.3792029847
Short name T67
Test name
Test status
Simulation time 1453290000 ps
CPU time 4.12 seconds
Started Jul 29 04:25:44 PM PDT 24
Finished Jul 29 04:25:54 PM PDT 24
Peak memory 164760 kb
Host smart-aae4080d-5e82-49eb-953c-c5181cf1a7a6
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3792029847 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.3792029847
Directory /workspace/48.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.1715563112
Short name T54
Test name
Test status
Simulation time 1551230000 ps
CPU time 4.53 seconds
Started Jul 29 04:25:43 PM PDT 24
Finished Jul 29 04:25:53 PM PDT 24
Peak memory 164688 kb
Host smart-feaf7f8c-9795-4153-a915-167b9d016537
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1715563112 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.1715563112
Directory /workspace/49.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.2390718013
Short name T40
Test name
Test status
Simulation time 1271730000 ps
CPU time 4.66 seconds
Started Jul 29 04:25:11 PM PDT 24
Finished Jul 29 04:25:21 PM PDT 24
Peak memory 164644 kb
Host smart-16613342-9101-445c-a2f4-fac37e41e772
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2390718013 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.2390718013
Directory /workspace/5.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.1370221705
Short name T60
Test name
Test status
Simulation time 1317690000 ps
CPU time 3.91 seconds
Started Jul 29 04:25:18 PM PDT 24
Finished Jul 29 04:25:28 PM PDT 24
Peak memory 162584 kb
Host smart-e69bb959-bf72-46ca-8a7c-8ae47cb6c11d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1370221705 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.1370221705
Directory /workspace/6.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.2058802455
Short name T33
Test name
Test status
Simulation time 1351090000 ps
CPU time 3.36 seconds
Started Jul 29 04:25:30 PM PDT 24
Finished Jul 29 04:25:37 PM PDT 24
Peak memory 164664 kb
Host smart-e01ba176-fd61-4d09-93ed-7c03087fea63
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2058802455 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.2058802455
Directory /workspace/7.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.2789325539
Short name T4
Test name
Test status
Simulation time 1479210000 ps
CPU time 3.96 seconds
Started Jul 29 04:25:37 PM PDT 24
Finished Jul 29 04:25:46 PM PDT 24
Peak memory 164500 kb
Host smart-becbf825-de77-46b4-9f4c-9b9c2c11fea3
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2789325539 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.2789325539
Directory /workspace/8.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.47160535
Short name T2
Test name
Test status
Simulation time 1339790000 ps
CPU time 2.65 seconds
Started Jul 29 04:25:27 PM PDT 24
Finished Jul 29 04:25:33 PM PDT 24
Peak memory 164676 kb
Host smart-0c4c5a1d-60fd-4ff2-9f2a-32431225b011
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=47160535 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.47160535
Directory /workspace/9.prim_lfsr_gal_smoke/latest
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