Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.31 100.00 96.55 100.00 100.00 95.00


Total tests in report: 200
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
87.31 87.31 100.00 100.00 96.55 96.55 100.00 100.00 100.00 100.00 40.00 40.00 /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.2738828750
96.81 9.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 87.50 47.50 /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.3107766677
98.31 1.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 95.00 7.50 /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.3408788147

Tests that do not contribute to grading

Name
/workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.3703257577
/workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.4029961474
/workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.846211457
/workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.14341649
/workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.3557519079
/workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.3104417228
/workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.1756208954
/workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.2476926783
/workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.3069140667
/workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.1421122461
/workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2523539441
/workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.2578953477
/workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.764145345
/workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.4033273195
/workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.3849406402
/workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.383694162
/workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.1660905173
/workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.4125413791
/workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.3731954095
/workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.3249130547
/workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.2590263688
/workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.3741819566
/workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.268420031
/workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.540092124
/workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.2844534194
/workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.2711627548
/workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.1141892295
/workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.2651293577
/workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.2065318537
/workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.376369682
/workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.159593188
/workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.3675583252
/workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.3531446968
/workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.2010366452
/workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.1884873011
/workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.4227155180
/workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.4061938677
/workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.1944173893
/workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.2508467750
/workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.2337904523
/workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.1530137428
/workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.1523134839
/workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.2813756085
/workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.2678309324
/workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.3813934804
/workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.234997643
/workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.2122510491
/workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.4266805625
/workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.971944789
/workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.256675409
/workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.2688129379
/workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.1349257321
/workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.66265286
/workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.1906701287
/workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.2051052125
/workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.24471434
/workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.4067998521
/workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.466334319
/workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.2994989882
/workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.467626221
/workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.979550538
/workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.2969008615
/workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3034289381
/workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.2871317302
/workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.1585459188
/workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.3252960549
/workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.1467700799
/workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.3763997536
/workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.4272564812
/workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.3280221308
/workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.988918575
/workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.367659039
/workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.3191920479
/workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.1819628151
/workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.2541993997
/workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.2814751343
/workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.3628779765
/workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.4106092371
/workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.1040788504
/workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.2996096184
/workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.1497918570
/workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.1408925610
/workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.479339072
/workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.4043639886
/workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.1183744408
/workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.2873985808
/workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.2591122231
/workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.2361069997
/workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.1632131361
/workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.2056237251
/workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.1060854910
/workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.17386195
/workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.2679422674
/workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.1585470309
/workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.875564888
/workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.1366620948
/workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.2109195346
/workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.2898635566
/workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.854780529
/workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.3209096125
/workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.2648948629
/workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.1294968795
/workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.520317530
/workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.3036370455
/workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.638655985
/workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.296938071
/workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.1748697003
/workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.937916967
/workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.2434900418
/workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.2384557392
/workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.1127728518
/workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.1331787713
/workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.2620856916
/workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.3201408769
/workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.3444296836
/workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.4000871490
/workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.1193109478
/workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.680162921
/workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.1055393373
/workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.2976588430
/workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.293939266
/workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.3982580782
/workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.1121073489
/workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.3059883411
/workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.2637324839
/workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.1189289762
/workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.4185218057
/workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.362285581
/workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.316736308
/workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.2129012416
/workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.3864997837
/workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.2797041297
/workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3917835422
/workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.471963670
/workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.1096534733
/workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.709371945
/workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.2692788967
/workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.1986337421
/workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.1274195057
/workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.2130263426
/workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.1657641338
/workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.3777099584
/workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.2152388529
/workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.417748776
/workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.1500613673
/workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.1522930243
/workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1745104250
/workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.1185963901
/workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.3858219762
/workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.3279241626
/workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.1928280109
/workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.3585227516
/workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.249027546
/workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.658867833
/workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.358993255
/workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.405085578
/workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.2964615549
/workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.4096980001
/workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.1934731592
/workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.1466739469
/workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.3683387897
/workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.2545596046
/workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.704616090
/workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.2339352227
/workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.1872136048
/workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.3529561451
/workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.1603427952
/workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.2895965497
/workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.1937469568
/workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.1556908168
/workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.1794268604
/workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.2494784127
/workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.3744192801
/workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.299659139
/workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.829971173
/workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.1736205083
/workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.1265632840
/workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.1231824397
/workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.2262318356
/workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.1959805031
/workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.1166195452
/workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.347389985
/workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.1709282266
/workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.209516327
/workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.3148137241
/workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.3089252363
/workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.2378388280
/workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.892153164
/workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.1822238313
/workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.3585239980
/workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.3662831075
/workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.3511985906
/workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.827172309
/workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.279998776
/workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.2810943035
/workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.209702143
/workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.2452473064



Total test records in report: 200
tests.html | tests1.html | tests2.html | tests3.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.2262318356 Jul 30 04:26:49 PM PDT 24 Jul 30 04:26:58 PM PDT 24 1573310000 ps
T2 /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.2378388280 Jul 30 04:27:22 PM PDT 24 Jul 30 04:27:33 PM PDT 24 1396090000 ps
T3 /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.2738828750 Jul 30 04:27:39 PM PDT 24 Jul 30 04:27:49 PM PDT 24 1474890000 ps
T4 /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.2810943035 Jul 30 04:31:01 PM PDT 24 Jul 30 04:31:10 PM PDT 24 1483150000 ps
T8 /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.704616090 Jul 30 04:30:10 PM PDT 24 Jul 30 04:30:20 PM PDT 24 1429850000 ps
T9 /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.3744192801 Jul 30 04:30:53 PM PDT 24 Jul 30 04:30:59 PM PDT 24 1254930000 ps
T10 /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.1603427952 Jul 30 04:30:45 PM PDT 24 Jul 30 04:30:53 PM PDT 24 1511710000 ps
T11 /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.3585239980 Jul 30 04:31:47 PM PDT 24 Jul 30 04:31:54 PM PDT 24 1276550000 ps
T12 /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.827172309 Jul 30 04:28:07 PM PDT 24 Jul 30 04:28:13 PM PDT 24 1237950000 ps
T13 /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.299659139 Jul 30 04:26:46 PM PDT 24 Jul 30 04:26:53 PM PDT 24 1422850000 ps
T31 /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.3662831075 Jul 30 04:28:31 PM PDT 24 Jul 30 04:28:38 PM PDT 24 1561690000 ps
T32 /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.2339352227 Jul 30 04:26:12 PM PDT 24 Jul 30 04:26:21 PM PDT 24 1245530000 ps
T33 /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.1794268604 Jul 30 04:27:29 PM PDT 24 Jul 30 04:27:40 PM PDT 24 1429570000 ps
T34 /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.1231824397 Jul 30 04:30:50 PM PDT 24 Jul 30 04:30:57 PM PDT 24 1533230000 ps
T35 /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.358993255 Jul 30 04:27:30 PM PDT 24 Jul 30 04:27:40 PM PDT 24 1323590000 ps
T36 /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.279998776 Jul 30 04:27:30 PM PDT 24 Jul 30 04:27:40 PM PDT 24 1390610000 ps
T37 /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.4096980001 Jul 30 04:27:30 PM PDT 24 Jul 30 04:27:41 PM PDT 24 1593210000 ps
T38 /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.1556908168 Jul 30 04:26:23 PM PDT 24 Jul 30 04:26:35 PM PDT 24 1501110000 ps
T39 /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.249027546 Jul 30 04:26:54 PM PDT 24 Jul 30 04:27:07 PM PDT 24 1488950000 ps
T40 /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.347389985 Jul 30 04:29:29 PM PDT 24 Jul 30 04:29:36 PM PDT 24 1291930000 ps
T41 /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.1166195452 Jul 30 04:26:33 PM PDT 24 Jul 30 04:26:46 PM PDT 24 1580830000 ps
T42 /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.1466739469 Jul 30 04:27:39 PM PDT 24 Jul 30 04:27:49 PM PDT 24 1459790000 ps
T43 /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.3585227516 Jul 30 04:31:58 PM PDT 24 Jul 30 04:32:06 PM PDT 24 1258670000 ps
T44 /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.209516327 Jul 30 04:26:43 PM PDT 24 Jul 30 04:26:52 PM PDT 24 1377130000 ps
T45 /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.1872136048 Jul 30 04:27:30 PM PDT 24 Jul 30 04:27:41 PM PDT 24 1553450000 ps
T46 /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.3279241626 Jul 30 04:27:43 PM PDT 24 Jul 30 04:27:53 PM PDT 24 1366250000 ps
T47 /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.3511985906 Jul 30 04:28:13 PM PDT 24 Jul 30 04:28:24 PM PDT 24 1416190000 ps
T48 /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.209702143 Jul 30 04:30:14 PM PDT 24 Jul 30 04:30:27 PM PDT 24 1575110000 ps
T49 /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.1934731592 Jul 30 04:27:30 PM PDT 24 Jul 30 04:27:40 PM PDT 24 1410970000 ps
T50 /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.892153164 Jul 30 04:27:00 PM PDT 24 Jul 30 04:27:12 PM PDT 24 1319210000 ps
T51 /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.1736205083 Jul 30 04:31:45 PM PDT 24 Jul 30 04:31:53 PM PDT 24 1474310000 ps
T52 /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.3148137241 Jul 30 04:27:07 PM PDT 24 Jul 30 04:27:18 PM PDT 24 1583830000 ps
T53 /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.2545596046 Jul 30 04:29:21 PM PDT 24 Jul 30 04:29:29 PM PDT 24 1377730000 ps
T54 /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.1959805031 Jul 30 04:26:33 PM PDT 24 Jul 30 04:26:44 PM PDT 24 1453650000 ps
T55 /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.829971173 Jul 30 04:30:49 PM PDT 24 Jul 30 04:30:55 PM PDT 24 1258350000 ps
T56 /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.3529561451 Jul 30 04:31:58 PM PDT 24 Jul 30 04:32:08 PM PDT 24 1546270000 ps
T57 /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.1709282266 Jul 30 04:28:03 PM PDT 24 Jul 30 04:28:12 PM PDT 24 1433810000 ps
T58 /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.1937469568 Jul 30 04:29:09 PM PDT 24 Jul 30 04:29:16 PM PDT 24 1212910000 ps
T59 /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.1822238313 Jul 30 04:28:33 PM PDT 24 Jul 30 04:28:42 PM PDT 24 1521850000 ps
T60 /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.1928280109 Jul 30 04:27:30 PM PDT 24 Jul 30 04:27:41 PM PDT 24 1503070000 ps
T61 /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.3683387897 Jul 30 04:28:14 PM PDT 24 Jul 30 04:28:24 PM PDT 24 1533670000 ps
T62 /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.1265632840 Jul 30 04:31:10 PM PDT 24 Jul 30 04:31:18 PM PDT 24 1426250000 ps
T63 /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.658867833 Jul 30 04:27:30 PM PDT 24 Jul 30 04:27:40 PM PDT 24 1370510000 ps
T64 /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.405085578 Jul 30 04:30:46 PM PDT 24 Jul 30 04:30:53 PM PDT 24 1397810000 ps
T65 /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.2964615549 Jul 30 04:29:21 PM PDT 24 Jul 30 04:29:30 PM PDT 24 1472070000 ps
T66 /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.3858219762 Jul 30 04:30:47 PM PDT 24 Jul 30 04:30:54 PM PDT 24 1289710000 ps
T67 /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.2452473064 Jul 30 04:27:39 PM PDT 24 Jul 30 04:27:49 PM PDT 24 1473410000 ps
T68 /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.2494784127 Jul 30 04:26:56 PM PDT 24 Jul 30 04:27:08 PM PDT 24 1572910000 ps
T69 /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.2895965497 Jul 30 04:29:11 PM PDT 24 Jul 30 04:29:21 PM PDT 24 1459950000 ps
T70 /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.3089252363 Jul 30 04:31:50 PM PDT 24 Jul 30 04:32:01 PM PDT 24 1506910000 ps
T5 /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.383694162 Jul 30 04:26:23 PM PDT 24 Jul 30 05:07:07 PM PDT 24 336412050000 ps
T6 /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.2122510491 Jul 30 04:26:17 PM PDT 24 Jul 30 05:09:24 PM PDT 24 336446670000 ps
T7 /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.846211457 Jul 30 04:26:23 PM PDT 24 Jul 30 05:07:23 PM PDT 24 336962350000 ps
T14 /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.764145345 Jul 30 04:26:15 PM PDT 24 Jul 30 05:03:30 PM PDT 24 336952770000 ps
T15 /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.234997643 Jul 30 04:26:15 PM PDT 24 Jul 30 05:00:38 PM PDT 24 336548030000 ps
T16 /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.2678309324 Jul 30 04:27:21 PM PDT 24 Jul 30 04:59:35 PM PDT 24 336355150000 ps
T17 /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.540092124 Jul 30 04:26:27 PM PDT 24 Jul 30 05:01:31 PM PDT 24 336644070000 ps
T18 /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.2651293577 Jul 30 04:30:45 PM PDT 24 Jul 30 04:55:58 PM PDT 24 337085730000 ps
T19 /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.3107766677 Jul 30 04:26:17 PM PDT 24 Jul 30 05:09:33 PM PDT 24 336778490000 ps
T20 /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.1944173893 Jul 30 04:28:12 PM PDT 24 Jul 30 04:59:20 PM PDT 24 336552850000 ps
T71 /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.2844534194 Jul 30 04:30:47 PM PDT 24 Jul 30 04:52:59 PM PDT 24 336449010000 ps
T72 /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.3104417228 Jul 30 04:26:23 PM PDT 24 Jul 30 05:07:13 PM PDT 24 336350390000 ps
T73 /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.3731954095 Jul 30 04:26:14 PM PDT 24 Jul 30 05:03:06 PM PDT 24 336632450000 ps
T74 /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2523539441 Jul 30 04:26:14 PM PDT 24 Jul 30 05:04:30 PM PDT 24 336662910000 ps
T75 /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.3249130547 Jul 30 04:26:14 PM PDT 24 Jul 30 05:03:31 PM PDT 24 336483110000 ps
T76 /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.971944789 Jul 30 04:26:16 PM PDT 24 Jul 30 05:09:31 PM PDT 24 336934410000 ps
T77 /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.14341649 Jul 30 04:26:13 PM PDT 24 Jul 30 05:03:55 PM PDT 24 337028370000 ps
T78 /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.4266805625 Jul 30 04:26:16 PM PDT 24 Jul 30 05:09:12 PM PDT 24 336655070000 ps
T79 /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.2010366452 Jul 30 04:26:17 PM PDT 24 Jul 30 05:00:35 PM PDT 24 336518610000 ps
T80 /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.4029961474 Jul 30 04:26:15 PM PDT 24 Jul 30 05:03:03 PM PDT 24 336517490000 ps
T81 /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.376369682 Jul 30 04:31:41 PM PDT 24 Jul 30 04:57:53 PM PDT 24 336742630000 ps
T82 /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.3069140667 Jul 30 04:26:23 PM PDT 24 Jul 30 05:07:23 PM PDT 24 336844790000 ps
T83 /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.1421122461 Jul 30 04:26:23 PM PDT 24 Jul 30 05:07:17 PM PDT 24 336389990000 ps
T84 /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.3849406402 Jul 30 04:26:23 PM PDT 24 Jul 30 05:07:18 PM PDT 24 336686970000 ps
T85 /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.2476926783 Jul 30 04:26:15 PM PDT 24 Jul 30 05:02:55 PM PDT 24 336379450000 ps
T86 /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.4125413791 Jul 30 04:26:13 PM PDT 24 Jul 30 05:03:03 PM PDT 24 336350930000 ps
T87 /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.2590263688 Jul 30 04:27:30 PM PDT 24 Jul 30 04:52:19 PM PDT 24 336864810000 ps
T88 /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.3531446968 Jul 30 04:27:49 PM PDT 24 Jul 30 04:56:35 PM PDT 24 336688450000 ps
T89 /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.1884873011 Jul 30 04:28:38 PM PDT 24 Jul 30 04:52:53 PM PDT 24 336846170000 ps
T90 /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.3813934804 Jul 30 04:26:16 PM PDT 24 Jul 30 05:09:08 PM PDT 24 336478630000 ps
T91 /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.159593188 Jul 30 04:31:05 PM PDT 24 Jul 30 05:04:50 PM PDT 24 337027970000 ps
T92 /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.2711627548 Jul 30 04:27:11 PM PDT 24 Jul 30 04:59:12 PM PDT 24 336953410000 ps
T93 /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.268420031 Jul 30 04:26:16 PM PDT 24 Jul 30 05:00:10 PM PDT 24 336358230000 ps
T94 /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.3703257577 Jul 30 04:26:16 PM PDT 24 Jul 30 05:00:10 PM PDT 24 336477050000 ps
T95 /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.2578953477 Jul 30 04:26:16 PM PDT 24 Jul 30 05:09:31 PM PDT 24 336916210000 ps
T96 /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.2337904523 Jul 30 04:28:27 PM PDT 24 Jul 30 05:03:37 PM PDT 24 336575030000 ps
T97 /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.4033273195 Jul 30 04:26:23 PM PDT 24 Jul 30 05:07:24 PM PDT 24 336808730000 ps
T98 /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.2508467750 Jul 30 04:31:05 PM PDT 24 Jul 30 05:04:38 PM PDT 24 336827030000 ps
T99 /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.1530137428 Jul 30 04:31:42 PM PDT 24 Jul 30 04:57:46 PM PDT 24 337119350000 ps
T100 /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.1756208954 Jul 30 04:26:23 PM PDT 24 Jul 30 05:07:18 PM PDT 24 337046290000 ps
T101 /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.3557519079 Jul 30 04:26:23 PM PDT 24 Jul 30 05:07:14 PM PDT 24 336452430000 ps
T102 /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.3675583252 Jul 30 04:28:24 PM PDT 24 Jul 30 05:04:53 PM PDT 24 336657030000 ps
T103 /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.3741819566 Jul 30 04:26:26 PM PDT 24 Jul 30 05:05:15 PM PDT 24 336649550000 ps
T104 /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.1523134839 Jul 30 04:31:06 PM PDT 24 Jul 30 05:01:08 PM PDT 24 336985930000 ps
T105 /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.1660905173 Jul 30 04:26:05 PM PDT 24 Jul 30 04:54:50 PM PDT 24 336929870000 ps
T106 /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.4061938677 Jul 30 04:29:58 PM PDT 24 Jul 30 05:03:10 PM PDT 24 336864330000 ps
T107 /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.1141892295 Jul 30 04:27:27 PM PDT 24 Jul 30 04:50:56 PM PDT 24 336645970000 ps
T108 /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.2813756085 Jul 30 04:31:51 PM PDT 24 Jul 30 04:59:08 PM PDT 24 336673010000 ps
T109 /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.2065318537 Jul 30 04:27:08 PM PDT 24 Jul 30 05:00:52 PM PDT 24 336712310000 ps
T110 /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.4227155180 Jul 30 04:31:02 PM PDT 24 Jul 30 05:01:10 PM PDT 24 336479110000 ps
T111 /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.2384557392 Jul 30 05:20:13 PM PDT 24 Jul 30 05:20:24 PM PDT 24 1537630000 ps
T112 /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.417748776 Jul 30 05:19:53 PM PDT 24 Jul 30 05:20:00 PM PDT 24 1361590000 ps
T113 /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.3777099584 Jul 30 05:20:28 PM PDT 24 Jul 30 05:20:42 PM PDT 24 1469870000 ps
T114 /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.854780529 Jul 30 05:19:54 PM PDT 24 Jul 30 05:20:04 PM PDT 24 1384350000 ps
T115 /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.638655985 Jul 30 05:20:04 PM PDT 24 Jul 30 05:20:15 PM PDT 24 1422870000 ps
T116 /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.2976588430 Jul 30 05:20:06 PM PDT 24 Jul 30 05:20:18 PM PDT 24 1481470000 ps
T117 /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.1331787713 Jul 30 05:20:07 PM PDT 24 Jul 30 05:20:19 PM PDT 24 1454370000 ps
T118 /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3917835422 Jul 30 05:19:53 PM PDT 24 Jul 30 05:20:01 PM PDT 24 1381550000 ps
T119 /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.3982580782 Jul 30 05:19:53 PM PDT 24 Jul 30 05:20:07 PM PDT 24 1628450000 ps
T120 /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.1748697003 Jul 30 05:20:04 PM PDT 24 Jul 30 05:20:17 PM PDT 24 1382530000 ps
T121 /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.4185218057 Jul 30 05:20:12 PM PDT 24 Jul 30 05:20:21 PM PDT 24 1512110000 ps
T122 /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.1185963901 Jul 30 05:19:57 PM PDT 24 Jul 30 05:20:05 PM PDT 24 1533630000 ps
T123 /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.2434900418 Jul 30 05:20:03 PM PDT 24 Jul 30 05:20:12 PM PDT 24 1471810000 ps
T124 /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.316736308 Jul 30 05:20:14 PM PDT 24 Jul 30 05:20:26 PM PDT 24 1413430000 ps
T125 /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.471963670 Jul 30 05:20:17 PM PDT 24 Jul 30 05:20:28 PM PDT 24 1365230000 ps
T126 /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.1294968795 Jul 30 05:20:01 PM PDT 24 Jul 30 05:20:08 PM PDT 24 1425890000 ps
T127 /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.1986337421 Jul 30 05:20:17 PM PDT 24 Jul 30 05:20:23 PM PDT 24 1237130000 ps
T128 /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.1657641338 Jul 30 05:20:21 PM PDT 24 Jul 30 05:20:34 PM PDT 24 1605630000 ps
T129 /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.2637324839 Jul 30 05:20:09 PM PDT 24 Jul 30 05:20:23 PM PDT 24 1507030000 ps
T130 /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.1274195057 Jul 30 05:20:15 PM PDT 24 Jul 30 05:20:22 PM PDT 24 1318690000 ps
T131 /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.680162921 Jul 30 05:20:08 PM PDT 24 Jul 30 05:20:17 PM PDT 24 1483410000 ps
T132 /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.362285581 Jul 30 05:20:12 PM PDT 24 Jul 30 05:20:24 PM PDT 24 1422030000 ps
T133 /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.293939266 Jul 30 05:20:12 PM PDT 24 Jul 30 05:20:23 PM PDT 24 1505470000 ps
T134 /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.2797041297 Jul 30 05:20:13 PM PDT 24 Jul 30 05:20:21 PM PDT 24 1570690000 ps
T135 /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.296938071 Jul 30 05:20:05 PM PDT 24 Jul 30 05:20:14 PM PDT 24 1491670000 ps
T136 /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.2130263426 Jul 30 05:20:19 PM PDT 24 Jul 30 05:20:33 PM PDT 24 1589170000 ps
T137 /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.2152388529 Jul 30 05:20:23 PM PDT 24 Jul 30 05:20:33 PM PDT 24 1527310000 ps
T138 /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.1127728518 Jul 30 05:19:53 PM PDT 24 Jul 30 05:20:00 PM PDT 24 969830000 ps
T139 /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.1096534733 Jul 30 05:20:18 PM PDT 24 Jul 30 05:20:27 PM PDT 24 1449350000 ps
T140 /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.3059883411 Jul 30 05:20:11 PM PDT 24 Jul 30 05:20:20 PM PDT 24 1452830000 ps
T141 /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.2129012416 Jul 30 05:20:13 PM PDT 24 Jul 30 05:20:23 PM PDT 24 1511390000 ps
T142 /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.1121073489 Jul 30 05:20:12 PM PDT 24 Jul 30 05:20:23 PM PDT 24 1489490000 ps
T143 /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.1522930243 Jul 30 05:19:58 PM PDT 24 Jul 30 05:20:07 PM PDT 24 1461750000 ps
T144 /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.3864997837 Jul 30 05:20:14 PM PDT 24 Jul 30 05:20:24 PM PDT 24 1544890000 ps
T145 /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.937916967 Jul 30 05:20:12 PM PDT 24 Jul 30 05:20:25 PM PDT 24 1480470000 ps
T146 /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.4000871490 Jul 30 05:20:10 PM PDT 24 Jul 30 05:20:23 PM PDT 24 1466750000 ps
T147 /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.1500613673 Jul 30 05:19:56 PM PDT 24 Jul 30 05:20:06 PM PDT 24 1339610000 ps
T148 /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.3209096125 Jul 30 05:19:53 PM PDT 24 Jul 30 05:20:02 PM PDT 24 1375370000 ps
T149 /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.3036370455 Jul 30 05:20:03 PM PDT 24 Jul 30 05:20:17 PM PDT 24 1514970000 ps
T150 /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.2648948629 Jul 30 05:19:58 PM PDT 24 Jul 30 05:20:09 PM PDT 24 1330990000 ps
T151 /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1745104250 Jul 30 05:19:59 PM PDT 24 Jul 30 05:20:08 PM PDT 24 1363470000 ps
T152 /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.520317530 Jul 30 05:19:59 PM PDT 24 Jul 30 05:20:11 PM PDT 24 1496070000 ps
T153 /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.3201408769 Jul 30 05:20:13 PM PDT 24 Jul 30 05:20:25 PM PDT 24 1518430000 ps
T154 /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.709371945 Jul 30 05:20:18 PM PDT 24 Jul 30 05:20:24 PM PDT 24 1164950000 ps
T155 /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.1193109478 Jul 30 05:20:07 PM PDT 24 Jul 30 05:20:18 PM PDT 24 1558310000 ps
T156 /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.2692788967 Jul 30 05:20:17 PM PDT 24 Jul 30 05:20:26 PM PDT 24 1516450000 ps
T157 /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.2620856916 Jul 30 05:20:12 PM PDT 24 Jul 30 05:20:23 PM PDT 24 1525710000 ps
T158 /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.1189289762 Jul 30 05:20:12 PM PDT 24 Jul 30 05:20:23 PM PDT 24 1419070000 ps
T159 /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.1055393373 Jul 30 05:20:08 PM PDT 24 Jul 30 05:20:16 PM PDT 24 1445730000 ps
T160 /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.3444296836 Jul 30 05:20:06 PM PDT 24 Jul 30 05:20:15 PM PDT 24 1295050000 ps
T21 /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.3408788147 Jul 30 05:25:16 PM PDT 24 Jul 30 06:06:32 PM PDT 24 336650590000 ps
T22 /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.2688129379 Jul 30 05:25:15 PM PDT 24 Jul 30 05:56:49 PM PDT 24 337136610000 ps
T23 /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.3628779765 Jul 30 05:25:24 PM PDT 24 Jul 30 05:55:19 PM PDT 24 337096190000 ps
T24 /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.3252960549 Jul 30 05:25:23 PM PDT 24 Jul 30 05:54:42 PM PDT 24 337051290000 ps
T25 /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.2994989882 Jul 30 05:25:17 PM PDT 24 Jul 30 06:06:29 PM PDT 24 336528810000 ps
T26 /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.17386195 Jul 30 05:25:23 PM PDT 24 Jul 30 05:56:50 PM PDT 24 336778450000 ps
T27 /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.1632131361 Jul 30 05:25:24 PM PDT 24 Jul 30 06:03:51 PM PDT 24 336386350000 ps
T28 /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.875564888 Jul 30 05:25:13 PM PDT 24 Jul 30 05:58:14 PM PDT 24 336400950000 ps
T29 /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.66265286 Jul 30 05:25:13 PM PDT 24 Jul 30 06:06:59 PM PDT 24 336795450000 ps
T30 /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.2871317302 Jul 30 05:25:19 PM PDT 24 Jul 30 05:57:03 PM PDT 24 336864170000 ps
T161 /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.1040788504 Jul 30 05:25:22 PM PDT 24 Jul 30 06:06:09 PM PDT 24 336379430000 ps
T162 /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.367659039 Jul 30 05:25:09 PM PDT 24 Jul 30 05:55:27 PM PDT 24 336589910000 ps
T163 /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.979550538 Jul 30 05:25:17 PM PDT 24 Jul 30 06:06:42 PM PDT 24 337045110000 ps
T164 /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.2873985808 Jul 30 05:25:23 PM PDT 24 Jul 30 06:00:17 PM PDT 24 336986010000 ps
T165 /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.988918575 Jul 30 05:25:24 PM PDT 24 Jul 30 05:58:52 PM PDT 24 336691670000 ps
T166 /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.2969008615 Jul 30 05:25:24 PM PDT 24 Jul 30 05:59:11 PM PDT 24 336949990000 ps
T167 /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.2541993997 Jul 30 05:25:25 PM PDT 24 Jul 30 05:59:43 PM PDT 24 336367150000 ps
T168 /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.4272564812 Jul 30 05:25:19 PM PDT 24 Jul 30 06:03:56 PM PDT 24 336552070000 ps
T169 /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.2361069997 Jul 30 05:25:23 PM PDT 24 Jul 30 06:05:34 PM PDT 24 336890810000 ps
T170 /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3034289381 Jul 30 05:25:24 PM PDT 24 Jul 30 05:50:17 PM PDT 24 336795570000 ps
T171 /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.3280221308 Jul 30 05:25:21 PM PDT 24 Jul 30 05:47:43 PM PDT 24 336454490000 ps
T172 /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.2679422674 Jul 30 05:25:25 PM PDT 24 Jul 30 05:53:18 PM PDT 24 336572970000 ps
T173 /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.1183744408 Jul 30 05:25:25 PM PDT 24 Jul 30 06:01:16 PM PDT 24 337031910000 ps
T174 /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.1060854910 Jul 30 05:25:22 PM PDT 24 Jul 30 05:59:53 PM PDT 24 336741730000 ps
T175 /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.1349257321 Jul 30 05:25:16 PM PDT 24 Jul 30 06:01:03 PM PDT 24 336920270000 ps
T176 /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.3763997536 Jul 30 05:25:20 PM PDT 24 Jul 30 06:04:19 PM PDT 24 336518870000 ps
T177 /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.2051052125 Jul 30 05:25:16 PM PDT 24 Jul 30 05:58:35 PM PDT 24 336459850000 ps
T178 /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.1366620948 Jul 30 05:25:16 PM PDT 24 Jul 30 06:00:13 PM PDT 24 336597630000 ps
T179 /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.24471434 Jul 30 05:25:16 PM PDT 24 Jul 30 06:00:34 PM PDT 24 336323530000 ps
T180 /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.1467700799 Jul 30 05:25:25 PM PDT 24 Jul 30 05:57:09 PM PDT 24 336690950000 ps
T181 /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.4043639886 Jul 30 05:25:22 PM PDT 24 Jul 30 06:05:29 PM PDT 24 336611550000 ps
T182 /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.479339072 Jul 30 05:25:15 PM PDT 24 Jul 30 05:56:13 PM PDT 24 336399630000 ps
T183 /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.3191920479 Jul 30 05:25:20 PM PDT 24 Jul 30 05:59:54 PM PDT 24 336651570000 ps
T184 /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.1585470309 Jul 30 05:25:15 PM PDT 24 Jul 30 06:03:31 PM PDT 24 337048790000 ps
T185 /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.2056237251 Jul 30 05:25:22 PM PDT 24 Jul 30 05:55:34 PM PDT 24 336673650000 ps
T186 /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.1497918570 Jul 30 05:25:20 PM PDT 24 Jul 30 06:04:21 PM PDT 24 336401710000 ps
T187 /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.1906701287 Jul 30 05:25:12 PM PDT 24 Jul 30 06:06:11 PM PDT 24 336992550000 ps
T188 /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.2591122231 Jul 30 05:25:22 PM PDT 24 Jul 30 05:57:46 PM PDT 24 336937150000 ps
T189 /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.4067998521 Jul 30 05:25:16 PM PDT 24 Jul 30 06:03:53 PM PDT 24 336508590000 ps
T190 /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.4106092371 Jul 30 05:25:17 PM PDT 24 Jul 30 05:54:10 PM PDT 24 336808350000 ps
T191 /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.2109195346 Jul 30 05:25:10 PM PDT 24 Jul 30 05:58:45 PM PDT 24 336382770000 ps
T192 /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.2898635566 Jul 30 05:25:13 PM PDT 24 Jul 30 05:59:26 PM PDT 24 336522710000 ps
T193 /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.1585459188 Jul 30 05:25:22 PM PDT 24 Jul 30 06:01:07 PM PDT 24 336481490000 ps
T194 /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.1819628151 Jul 30 05:25:16 PM PDT 24 Jul 30 05:56:30 PM PDT 24 337022450000 ps
T195 /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.466334319 Jul 30 05:25:13 PM PDT 24 Jul 30 06:05:24 PM PDT 24 336899750000 ps
T196 /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.256675409 Jul 30 05:25:17 PM PDT 24 Jul 30 06:06:38 PM PDT 24 336890430000 ps
T197 /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.1408925610 Jul 30 05:25:25 PM PDT 24 Jul 30 05:58:39 PM PDT 24 336805450000 ps
T198 /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.2996096184 Jul 30 05:25:23 PM PDT 24 Jul 30 05:59:33 PM PDT 24 336386610000 ps
T199 /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.467626221 Jul 30 05:25:17 PM PDT 24 Jul 30 05:58:27 PM PDT 24 336529450000 ps
T200 /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.2814751343 Jul 30 05:25:19 PM PDT 24 Jul 30 06:03:53 PM PDT 24 337100150000 ps

Test location /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.2738828750
Short name T3
Test name
Test status
Simulation time 1474890000 ps
CPU time 4.38 seconds
Started Jul 30 04:27:39 PM PDT 24
Finished Jul 30 04:27:49 PM PDT 24
Peak memory 164328 kb
Host smart-1f026181-c8cf-47de-9dfe-d6b1f3bd1eb6
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2738828750 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.2738828750
Directory /workspace/1.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.3107766677
Short name T19
Test name
Test status
Simulation time 336778490000 ps
CPU time 989.14 seconds
Started Jul 30 04:26:17 PM PDT 24
Finished Jul 30 05:09:33 PM PDT 24
Peak memory 160672 kb
Host smart-4572af0b-d922-417a-9549-6065dde20126
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3107766677 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.3107766677
Directory /workspace/10.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.3408788147
Short name T21
Test name
Test status
Simulation time 336650590000 ps
CPU time 995.19 seconds
Started Jul 30 05:25:16 PM PDT 24
Finished Jul 30 06:06:32 PM PDT 24
Peak memory 160740 kb
Host smart-442b70b5-2c05-425e-a8e4-d26fb79abda6
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3408788147 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.3408788147
Directory /workspace/0.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.3703257577
Short name T94
Test name
Test status
Simulation time 336477050000 ps
CPU time 818.96 seconds
Started Jul 30 04:26:16 PM PDT 24
Finished Jul 30 05:00:10 PM PDT 24
Peak memory 160856 kb
Host smart-762673fa-45e2-478b-bee9-b893d56d4eed
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3703257577 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.3703257577
Directory /workspace/0.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.4029961474
Short name T80
Test name
Test status
Simulation time 336517490000 ps
CPU time 908.67 seconds
Started Jul 30 04:26:15 PM PDT 24
Finished Jul 30 05:03:03 PM PDT 24
Peak memory 160044 kb
Host smart-cf23e339-d8d7-485d-9f8d-f87872cbf9d6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4029961474 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.4029961474
Directory /workspace/1.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.846211457
Short name T7
Test name
Test status
Simulation time 336962350000 ps
CPU time 957.99 seconds
Started Jul 30 04:26:23 PM PDT 24
Finished Jul 30 05:07:23 PM PDT 24
Peak memory 157832 kb
Host smart-9dda709e-e1fa-4024-bf73-be0d4491a6fe
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=846211457 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.846211457
Directory /workspace/11.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.14341649
Short name T77
Test name
Test status
Simulation time 337028370000 ps
CPU time 937.06 seconds
Started Jul 30 04:26:13 PM PDT 24
Finished Jul 30 05:03:55 PM PDT 24
Peak memory 159764 kb
Host smart-6e0aa2fa-0716-45cf-8105-073769afe312
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=14341649 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.14341649
Directory /workspace/12.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.3557519079
Short name T101
Test name
Test status
Simulation time 336452430000 ps
CPU time 951.52 seconds
Started Jul 30 04:26:23 PM PDT 24
Finished Jul 30 05:07:14 PM PDT 24
Peak memory 158708 kb
Host smart-71abc0a9-86e2-4a54-9968-c2122c1afa5c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3557519079 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.3557519079
Directory /workspace/13.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.3104417228
Short name T72
Test name
Test status
Simulation time 336350390000 ps
CPU time 942.78 seconds
Started Jul 30 04:26:23 PM PDT 24
Finished Jul 30 05:07:13 PM PDT 24
Peak memory 158472 kb
Host smart-6250b8e3-2099-4bf5-b94d-2574ad7440bc
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3104417228 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.3104417228
Directory /workspace/14.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.1756208954
Short name T100
Test name
Test status
Simulation time 337046290000 ps
CPU time 950.65 seconds
Started Jul 30 04:26:23 PM PDT 24
Finished Jul 30 05:07:18 PM PDT 24
Peak memory 158316 kb
Host smart-43a5592b-f93b-4ee6-bdeb-c2e517a4cb35
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1756208954 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.1756208954
Directory /workspace/15.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.2476926783
Short name T85
Test name
Test status
Simulation time 336379450000 ps
CPU time 901.9 seconds
Started Jul 30 04:26:15 PM PDT 24
Finished Jul 30 05:02:55 PM PDT 24
Peak memory 160248 kb
Host smart-19edae5c-2e3e-4c5d-a1cb-b38982f09992
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2476926783 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.2476926783
Directory /workspace/16.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.3069140667
Short name T82
Test name
Test status
Simulation time 336844790000 ps
CPU time 948.24 seconds
Started Jul 30 04:26:23 PM PDT 24
Finished Jul 30 05:07:23 PM PDT 24
Peak memory 158408 kb
Host smart-4d3a1f1a-94ac-4b1f-b1c4-f3149fc91e14
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3069140667 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.3069140667
Directory /workspace/17.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.1421122461
Short name T83
Test name
Test status
Simulation time 336389990000 ps
CPU time 949.98 seconds
Started Jul 30 04:26:23 PM PDT 24
Finished Jul 30 05:07:17 PM PDT 24
Peak memory 158856 kb
Host smart-0b8c8225-62d3-43a2-8a04-ed9efe8bdaa0
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1421122461 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.1421122461
Directory /workspace/18.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2523539441
Short name T74
Test name
Test status
Simulation time 336662910000 ps
CPU time 948.6 seconds
Started Jul 30 04:26:14 PM PDT 24
Finished Jul 30 05:04:30 PM PDT 24
Peak memory 160248 kb
Host smart-547241da-9fc3-447d-8bc6-4207ec38f1cd
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2523539441 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.2523539441
Directory /workspace/19.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.2578953477
Short name T95
Test name
Test status
Simulation time 336916210000 ps
CPU time 987.59 seconds
Started Jul 30 04:26:16 PM PDT 24
Finished Jul 30 05:09:31 PM PDT 24
Peak memory 160664 kb
Host smart-c7c4b6a5-b16d-46f5-8309-460a8acf07e4
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2578953477 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.2578953477
Directory /workspace/2.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.764145345
Short name T14
Test name
Test status
Simulation time 336952770000 ps
CPU time 919.88 seconds
Started Jul 30 04:26:15 PM PDT 24
Finished Jul 30 05:03:30 PM PDT 24
Peak memory 160000 kb
Host smart-82cf1868-5c22-4700-a1be-b11398d3a0f5
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=764145345 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.764145345
Directory /workspace/20.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.4033273195
Short name T97
Test name
Test status
Simulation time 336808730000 ps
CPU time 952.28 seconds
Started Jul 30 04:26:23 PM PDT 24
Finished Jul 30 05:07:24 PM PDT 24
Peak memory 158488 kb
Host smart-16d4619e-23f0-43ce-92a7-ac69cc9302aa
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4033273195 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.4033273195
Directory /workspace/21.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.3849406402
Short name T84
Test name
Test status
Simulation time 336686970000 ps
CPU time 960.28 seconds
Started Jul 30 04:26:23 PM PDT 24
Finished Jul 30 05:07:18 PM PDT 24
Peak memory 159376 kb
Host smart-3c7de933-b372-45e4-9191-aaaaaf47a164
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3849406402 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.3849406402
Directory /workspace/22.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.383694162
Short name T5
Test name
Test status
Simulation time 336412050000 ps
CPU time 956.95 seconds
Started Jul 30 04:26:23 PM PDT 24
Finished Jul 30 05:07:07 PM PDT 24
Peak memory 159636 kb
Host smart-fc1fdff7-fe3a-42a8-8986-0423638bb262
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=383694162 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.383694162
Directory /workspace/23.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.1660905173
Short name T105
Test name
Test status
Simulation time 336929870000 ps
CPU time 694.92 seconds
Started Jul 30 04:26:05 PM PDT 24
Finished Jul 30 04:54:50 PM PDT 24
Peak memory 160572 kb
Host smart-40ffd9f0-464a-4291-855f-d4982263787c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1660905173 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.1660905173
Directory /workspace/24.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.4125413791
Short name T86
Test name
Test status
Simulation time 336350930000 ps
CPU time 893.29 seconds
Started Jul 30 04:26:13 PM PDT 24
Finished Jul 30 05:03:03 PM PDT 24
Peak memory 160564 kb
Host smart-21b3b675-af0c-43ae-a418-86264c7f8f4c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4125413791 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.4125413791
Directory /workspace/25.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.3731954095
Short name T73
Test name
Test status
Simulation time 336632450000 ps
CPU time 891.82 seconds
Started Jul 30 04:26:14 PM PDT 24
Finished Jul 30 05:03:06 PM PDT 24
Peak memory 160608 kb
Host smart-df83e6e7-d1dc-4ce1-b9f9-dffb1e7b0296
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3731954095 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.3731954095
Directory /workspace/26.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.3249130547
Short name T75
Test name
Test status
Simulation time 336483110000 ps
CPU time 917.12 seconds
Started Jul 30 04:26:14 PM PDT 24
Finished Jul 30 05:03:31 PM PDT 24
Peak memory 160184 kb
Host smart-a0c8b8c0-5b90-4b1e-8526-cb675aa6226e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3249130547 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.3249130547
Directory /workspace/27.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.2590263688
Short name T87
Test name
Test status
Simulation time 336864810000 ps
CPU time 601.56 seconds
Started Jul 30 04:27:30 PM PDT 24
Finished Jul 30 04:52:19 PM PDT 24
Peak memory 159420 kb
Host smart-0d89b0db-92e0-4f07-a1d8-d07cf3950dca
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2590263688 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.2590263688
Directory /workspace/28.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.3741819566
Short name T103
Test name
Test status
Simulation time 336649550000 ps
CPU time 978.53 seconds
Started Jul 30 04:26:26 PM PDT 24
Finished Jul 30 05:05:15 PM PDT 24
Peak memory 160248 kb
Host smart-7b104b29-5954-4f02-b0b2-1f55665e6663
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3741819566 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.3741819566
Directory /workspace/29.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.268420031
Short name T93
Test name
Test status
Simulation time 336358230000 ps
CPU time 818.16 seconds
Started Jul 30 04:26:16 PM PDT 24
Finished Jul 30 05:00:10 PM PDT 24
Peak memory 160860 kb
Host smart-b05f029f-abd8-455a-869d-fd02192c0f6a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=268420031 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.268420031
Directory /workspace/3.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.540092124
Short name T17
Test name
Test status
Simulation time 336644070000 ps
CPU time 856.15 seconds
Started Jul 30 04:26:27 PM PDT 24
Finished Jul 30 05:01:31 PM PDT 24
Peak memory 160556 kb
Host smart-aaf60e83-14ea-472a-8ee1-60c52ba4c0db
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=540092124 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.540092124
Directory /workspace/30.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.2844534194
Short name T71
Test name
Test status
Simulation time 336449010000 ps
CPU time 525.81 seconds
Started Jul 30 04:30:47 PM PDT 24
Finished Jul 30 04:52:59 PM PDT 24
Peak memory 159096 kb
Host smart-e17dcb19-6298-4c07-8d52-dd5f6b119ee1
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2844534194 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.2844534194
Directory /workspace/31.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.2711627548
Short name T92
Test name
Test status
Simulation time 336953410000 ps
CPU time 792.61 seconds
Started Jul 30 04:27:11 PM PDT 24
Finished Jul 30 04:59:12 PM PDT 24
Peak memory 160668 kb
Host smart-0af00e50-f81f-4525-9e43-798b4331f33f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2711627548 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.2711627548
Directory /workspace/32.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.1141892295
Short name T107
Test name
Test status
Simulation time 336645970000 ps
CPU time 548.8 seconds
Started Jul 30 04:27:27 PM PDT 24
Finished Jul 30 04:50:56 PM PDT 24
Peak memory 160528 kb
Host smart-9fdd8f58-0519-4448-a786-4fc26a631a03
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1141892295 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.1141892295
Directory /workspace/33.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.2651293577
Short name T18
Test name
Test status
Simulation time 337085730000 ps
CPU time 614.59 seconds
Started Jul 30 04:30:45 PM PDT 24
Finished Jul 30 04:55:58 PM PDT 24
Peak memory 159144 kb
Host smart-7c50e6da-6648-485c-adaf-236bbebdbdce
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2651293577 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.2651293577
Directory /workspace/34.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.2065318537
Short name T109
Test name
Test status
Simulation time 336712310000 ps
CPU time 809.88 seconds
Started Jul 30 04:27:08 PM PDT 24
Finished Jul 30 05:00:52 PM PDT 24
Peak memory 160868 kb
Host smart-aed4e405-c6d6-4513-9c68-64a0feca945a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2065318537 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.2065318537
Directory /workspace/35.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.376369682
Short name T81
Test name
Test status
Simulation time 336742630000 ps
CPU time 635.89 seconds
Started Jul 30 04:31:41 PM PDT 24
Finished Jul 30 04:57:53 PM PDT 24
Peak memory 159476 kb
Host smart-da369152-1f57-47b7-88e7-1c75608cf52b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=376369682 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.376369682
Directory /workspace/36.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.159593188
Short name T91
Test name
Test status
Simulation time 337027970000 ps
CPU time 824.14 seconds
Started Jul 30 04:31:05 PM PDT 24
Finished Jul 30 05:04:50 PM PDT 24
Peak memory 160464 kb
Host smart-baa957c3-d342-441c-a883-aeb77c3499a6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=159593188 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.159593188
Directory /workspace/37.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.3675583252
Short name T102
Test name
Test status
Simulation time 336657030000 ps
CPU time 878.51 seconds
Started Jul 30 04:28:24 PM PDT 24
Finished Jul 30 05:04:53 PM PDT 24
Peak memory 160680 kb
Host smart-f88f8405-c318-4e52-a054-9789dfac3c6b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3675583252 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.3675583252
Directory /workspace/38.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.3531446968
Short name T88
Test name
Test status
Simulation time 336688450000 ps
CPU time 704.08 seconds
Started Jul 30 04:27:49 PM PDT 24
Finished Jul 30 04:56:35 PM PDT 24
Peak memory 160652 kb
Host smart-c9974f08-388f-4a63-b3b8-7a0b9275e00b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3531446968 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.3531446968
Directory /workspace/39.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.2010366452
Short name T79
Test name
Test status
Simulation time 336518610000 ps
CPU time 824.09 seconds
Started Jul 30 04:26:17 PM PDT 24
Finished Jul 30 05:00:35 PM PDT 24
Peak memory 160856 kb
Host smart-beb6bebd-c516-4e7f-90a3-64d5e89ad631
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2010366452 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.2010366452
Directory /workspace/4.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.1884873011
Short name T89
Test name
Test status
Simulation time 336846170000 ps
CPU time 593.87 seconds
Started Jul 30 04:28:38 PM PDT 24
Finished Jul 30 04:52:53 PM PDT 24
Peak memory 159760 kb
Host smart-2ba70d1b-c9f1-4baf-9fa4-16cc9e888858
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1884873011 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.1884873011
Directory /workspace/40.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.4227155180
Short name T110
Test name
Test status
Simulation time 336479110000 ps
CPU time 737.79 seconds
Started Jul 30 04:31:02 PM PDT 24
Finished Jul 30 05:01:10 PM PDT 24
Peak memory 160556 kb
Host smart-cd4758c2-726d-4525-885f-43e182c1a6ca
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4227155180 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.4227155180
Directory /workspace/41.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.4061938677
Short name T106
Test name
Test status
Simulation time 336864330000 ps
CPU time 813.76 seconds
Started Jul 30 04:29:58 PM PDT 24
Finished Jul 30 05:03:10 PM PDT 24
Peak memory 160740 kb
Host smart-52112315-f98a-45e9-9f1f-165d8105ab23
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4061938677 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.4061938677
Directory /workspace/42.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.1944173893
Short name T20
Test name
Test status
Simulation time 336552850000 ps
CPU time 762.69 seconds
Started Jul 30 04:28:12 PM PDT 24
Finished Jul 30 04:59:20 PM PDT 24
Peak memory 160680 kb
Host smart-505625fc-8c29-4045-ac2e-6aafc3430e1e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1944173893 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.1944173893
Directory /workspace/43.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.2508467750
Short name T98
Test name
Test status
Simulation time 336827030000 ps
CPU time 814.02 seconds
Started Jul 30 04:31:05 PM PDT 24
Finished Jul 30 05:04:38 PM PDT 24
Peak memory 160480 kb
Host smart-c01f80ae-2857-4294-b762-15379878e32d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2508467750 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.2508467750
Directory /workspace/44.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.2337904523
Short name T96
Test name
Test status
Simulation time 336575030000 ps
CPU time 854.8 seconds
Started Jul 30 04:28:27 PM PDT 24
Finished Jul 30 05:03:37 PM PDT 24
Peak memory 160672 kb
Host smart-9075a7a4-63a4-40d0-91a0-d425a417e21d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2337904523 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.2337904523
Directory /workspace/45.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.1530137428
Short name T99
Test name
Test status
Simulation time 337119350000 ps
CPU time 633.86 seconds
Started Jul 30 04:31:42 PM PDT 24
Finished Jul 30 04:57:46 PM PDT 24
Peak memory 160344 kb
Host smart-fc1d0161-9e19-404d-a872-8526ea5133c1
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1530137428 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.1530137428
Directory /workspace/46.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.1523134839
Short name T104
Test name
Test status
Simulation time 336985930000 ps
CPU time 730.63 seconds
Started Jul 30 04:31:06 PM PDT 24
Finished Jul 30 05:01:08 PM PDT 24
Peak memory 160632 kb
Host smart-46d2fd20-3a2e-4846-ab4f-46607efbd843
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1523134839 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.1523134839
Directory /workspace/47.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.2813756085
Short name T108
Test name
Test status
Simulation time 336673010000 ps
CPU time 664.12 seconds
Started Jul 30 04:31:51 PM PDT 24
Finished Jul 30 04:59:08 PM PDT 24
Peak memory 160632 kb
Host smart-ea0b4c3c-b737-4669-a291-3b68161ab93f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2813756085 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.2813756085
Directory /workspace/48.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.2678309324
Short name T16
Test name
Test status
Simulation time 336355150000 ps
CPU time 794.18 seconds
Started Jul 30 04:27:21 PM PDT 24
Finished Jul 30 04:59:35 PM PDT 24
Peak memory 160740 kb
Host smart-30d6e2d7-f33f-4fbc-b76a-ec76f4af6f7b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2678309324 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.2678309324
Directory /workspace/49.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.3813934804
Short name T90
Test name
Test status
Simulation time 336478630000 ps
CPU time 972.58 seconds
Started Jul 30 04:26:16 PM PDT 24
Finished Jul 30 05:09:08 PM PDT 24
Peak memory 160600 kb
Host smart-f68897cc-6f99-4c35-a7ec-ba5f690c631e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3813934804 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.3813934804
Directory /workspace/5.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.234997643
Short name T15
Test name
Test status
Simulation time 336548030000 ps
CPU time 849.54 seconds
Started Jul 30 04:26:15 PM PDT 24
Finished Jul 30 05:00:38 PM PDT 24
Peak memory 160240 kb
Host smart-89c97be0-4060-4bbf-a630-57e268743813
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=234997643 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.234997643
Directory /workspace/6.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.2122510491
Short name T6
Test name
Test status
Simulation time 336446670000 ps
CPU time 978.31 seconds
Started Jul 30 04:26:17 PM PDT 24
Finished Jul 30 05:09:24 PM PDT 24
Peak memory 160660 kb
Host smart-d70fe9a1-83bf-4a7e-b354-01a9ae85dd92
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2122510491 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.2122510491
Directory /workspace/7.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.4266805625
Short name T78
Test name
Test status
Simulation time 336655070000 ps
CPU time 980.23 seconds
Started Jul 30 04:26:16 PM PDT 24
Finished Jul 30 05:09:12 PM PDT 24
Peak memory 160660 kb
Host smart-90fb4a22-49bc-4c2a-b1f0-e198c8dcc3cc
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4266805625 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.4266805625
Directory /workspace/8.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.971944789
Short name T76
Test name
Test status
Simulation time 336934410000 ps
CPU time 1003.34 seconds
Started Jul 30 04:26:16 PM PDT 24
Finished Jul 30 05:09:31 PM PDT 24
Peak memory 160664 kb
Host smart-c85bc14d-e23c-4d9c-9a05-c9bd845a01f9
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=971944789 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.971944789
Directory /workspace/9.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.256675409
Short name T196
Test name
Test status
Simulation time 336890430000 ps
CPU time 983.13 seconds
Started Jul 30 05:25:17 PM PDT 24
Finished Jul 30 06:06:38 PM PDT 24
Peak memory 160744 kb
Host smart-a35df911-2d0c-40d9-ab56-022277f55be8
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=256675409 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.256675409
Directory /workspace/1.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.2688129379
Short name T22
Test name
Test status
Simulation time 337136610000 ps
CPU time 772.47 seconds
Started Jul 30 05:25:15 PM PDT 24
Finished Jul 30 05:56:49 PM PDT 24
Peak memory 160816 kb
Host smart-de86f7f2-1112-4706-a3f7-b257b53740fe
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2688129379 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.2688129379
Directory /workspace/10.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.1349257321
Short name T175
Test name
Test status
Simulation time 336920270000 ps
CPU time 869.1 seconds
Started Jul 30 05:25:16 PM PDT 24
Finished Jul 30 06:01:03 PM PDT 24
Peak memory 160800 kb
Host smart-29c4c156-0c19-4f64-aaae-2f877cd9a3f2
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1349257321 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.1349257321
Directory /workspace/11.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.66265286
Short name T29
Test name
Test status
Simulation time 336795450000 ps
CPU time 1053.97 seconds
Started Jul 30 05:25:13 PM PDT 24
Finished Jul 30 06:06:59 PM PDT 24
Peak memory 160784 kb
Host smart-70914fdb-f740-44cd-b4c7-55d16a586362
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=66265286 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.66265286
Directory /workspace/12.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.1906701287
Short name T187
Test name
Test status
Simulation time 336992550000 ps
CPU time 1012.83 seconds
Started Jul 30 05:25:12 PM PDT 24
Finished Jul 30 06:06:11 PM PDT 24
Peak memory 160816 kb
Host smart-6ee437a0-646f-4fd9-bc47-553e09789b49
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1906701287 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.1906701287
Directory /workspace/13.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.2051052125
Short name T177
Test name
Test status
Simulation time 336459850000 ps
CPU time 814.43 seconds
Started Jul 30 05:25:16 PM PDT 24
Finished Jul 30 05:58:35 PM PDT 24
Peak memory 160804 kb
Host smart-583b9502-4865-4955-95d6-e3ac9b0ed526
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2051052125 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.2051052125
Directory /workspace/14.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.24471434
Short name T179
Test name
Test status
Simulation time 336323530000 ps
CPU time 851.28 seconds
Started Jul 30 05:25:16 PM PDT 24
Finished Jul 30 06:00:34 PM PDT 24
Peak memory 160792 kb
Host smart-2d3fb61a-d094-4860-a14c-2f1dbd9d6a7a
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=24471434 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.24471434
Directory /workspace/15.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.4067998521
Short name T189
Test name
Test status
Simulation time 336508590000 ps
CPU time 925.35 seconds
Started Jul 30 05:25:16 PM PDT 24
Finished Jul 30 06:03:53 PM PDT 24
Peak memory 160812 kb
Host smart-e15b1e6d-0f59-4939-93fe-cd9dfed9b685
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4067998521 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.4067998521
Directory /workspace/16.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.466334319
Short name T195
Test name
Test status
Simulation time 336899750000 ps
CPU time 983.04 seconds
Started Jul 30 05:25:13 PM PDT 24
Finished Jul 30 06:05:24 PM PDT 24
Peak memory 160796 kb
Host smart-2e1d61cf-9186-4188-a3c3-62858f8e7091
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=466334319 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.466334319
Directory /workspace/17.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.2994989882
Short name T25
Test name
Test status
Simulation time 336528810000 ps
CPU time 984.11 seconds
Started Jul 30 05:25:17 PM PDT 24
Finished Jul 30 06:06:29 PM PDT 24
Peak memory 160748 kb
Host smart-062f3e7e-8ec3-447e-ad88-a44b4252edd4
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2994989882 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.2994989882
Directory /workspace/18.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.467626221
Short name T199
Test name
Test status
Simulation time 336529450000 ps
CPU time 821.44 seconds
Started Jul 30 05:25:17 PM PDT 24
Finished Jul 30 05:58:27 PM PDT 24
Peak memory 160804 kb
Host smart-538aba17-fa80-41df-af42-96a5cd141950
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=467626221 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.467626221
Directory /workspace/19.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.979550538
Short name T163
Test name
Test status
Simulation time 337045110000 ps
CPU time 992.5 seconds
Started Jul 30 05:25:17 PM PDT 24
Finished Jul 30 06:06:42 PM PDT 24
Peak memory 160744 kb
Host smart-01c18fa3-ce43-4cbe-bc7d-c696b83a2ef5
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=979550538 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.979550538
Directory /workspace/2.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.2969008615
Short name T166
Test name
Test status
Simulation time 336949990000 ps
CPU time 810.19 seconds
Started Jul 30 05:25:24 PM PDT 24
Finished Jul 30 05:59:11 PM PDT 24
Peak memory 160812 kb
Host smart-d0b99a8f-7d1f-436c-9a7d-70687acc833f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2969008615 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.2969008615
Directory /workspace/20.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3034289381
Short name T170
Test name
Test status
Simulation time 336795570000 ps
CPU time 596.53 seconds
Started Jul 30 05:25:24 PM PDT 24
Finished Jul 30 05:50:17 PM PDT 24
Peak memory 160756 kb
Host smart-af292a5c-c16d-4a6d-b86a-950263eb7d14
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3034289381 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.3034289381
Directory /workspace/21.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.2871317302
Short name T30
Test name
Test status
Simulation time 336864170000 ps
CPU time 783.55 seconds
Started Jul 30 05:25:19 PM PDT 24
Finished Jul 30 05:57:03 PM PDT 24
Peak memory 160804 kb
Host smart-55d7579d-2093-4196-ba90-c5f258b531dc
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2871317302 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.2871317302
Directory /workspace/22.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.1585459188
Short name T193
Test name
Test status
Simulation time 336481490000 ps
CPU time 884.24 seconds
Started Jul 30 05:25:22 PM PDT 24
Finished Jul 30 06:01:07 PM PDT 24
Peak memory 160856 kb
Host smart-4a236f11-b0b7-47e7-8b9f-cd36a3220444
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1585459188 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.1585459188
Directory /workspace/23.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.3252960549
Short name T24
Test name
Test status
Simulation time 337051290000 ps
CPU time 722.09 seconds
Started Jul 30 05:25:23 PM PDT 24
Finished Jul 30 05:54:42 PM PDT 24
Peak memory 160800 kb
Host smart-8898e349-3e1d-4bec-b79a-fae1a521c6d5
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3252960549 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.3252960549
Directory /workspace/24.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.1467700799
Short name T180
Test name
Test status
Simulation time 336690950000 ps
CPU time 803.49 seconds
Started Jul 30 05:25:25 PM PDT 24
Finished Jul 30 05:57:09 PM PDT 24
Peak memory 160796 kb
Host smart-c2bb3d23-9db6-4190-b8d3-fce10caea90a
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1467700799 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.1467700799
Directory /workspace/25.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.3763997536
Short name T176
Test name
Test status
Simulation time 336518870000 ps
CPU time 909.24 seconds
Started Jul 30 05:25:20 PM PDT 24
Finished Jul 30 06:04:19 PM PDT 24
Peak memory 160804 kb
Host smart-2fd6ac73-9c05-47ec-aca9-668e1eed3f74
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3763997536 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.3763997536
Directory /workspace/26.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.4272564812
Short name T168
Test name
Test status
Simulation time 336552070000 ps
CPU time 897.78 seconds
Started Jul 30 05:25:19 PM PDT 24
Finished Jul 30 06:03:56 PM PDT 24
Peak memory 160804 kb
Host smart-d7d9374f-edca-41b4-969f-e4389bdf23ca
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4272564812 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.4272564812
Directory /workspace/27.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.3280221308
Short name T171
Test name
Test status
Simulation time 336454490000 ps
CPU time 529.57 seconds
Started Jul 30 05:25:21 PM PDT 24
Finished Jul 30 05:47:43 PM PDT 24
Peak memory 160772 kb
Host smart-7fe86c39-e6d1-4f37-9393-17024cf0697b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3280221308 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.3280221308
Directory /workspace/28.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.988918575
Short name T165
Test name
Test status
Simulation time 336691670000 ps
CPU time 822.96 seconds
Started Jul 30 05:25:24 PM PDT 24
Finished Jul 30 05:58:52 PM PDT 24
Peak memory 160824 kb
Host smart-6530b502-3701-4036-9278-379e5282f250
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=988918575 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.988918575
Directory /workspace/29.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.367659039
Short name T162
Test name
Test status
Simulation time 336589910000 ps
CPU time 742.89 seconds
Started Jul 30 05:25:09 PM PDT 24
Finished Jul 30 05:55:27 PM PDT 24
Peak memory 160792 kb
Host smart-3de13a5f-0078-4b7f-b0bd-0b923464dde8
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=367659039 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.367659039
Directory /workspace/3.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.3191920479
Short name T183
Test name
Test status
Simulation time 336651570000 ps
CPU time 863.09 seconds
Started Jul 30 05:25:20 PM PDT 24
Finished Jul 30 05:59:54 PM PDT 24
Peak memory 160812 kb
Host smart-56c98751-d3de-484d-843e-4387b422a83b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3191920479 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.3191920479
Directory /workspace/30.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.1819628151
Short name T194
Test name
Test status
Simulation time 337022450000 ps
CPU time 757.69 seconds
Started Jul 30 05:25:16 PM PDT 24
Finished Jul 30 05:56:30 PM PDT 24
Peak memory 160808 kb
Host smart-119d01a9-a957-4ead-a9ba-4c891e61a06b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1819628151 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.1819628151
Directory /workspace/31.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.2541993997
Short name T167
Test name
Test status
Simulation time 336367150000 ps
CPU time 822.42 seconds
Started Jul 30 05:25:25 PM PDT 24
Finished Jul 30 05:59:43 PM PDT 24
Peak memory 160812 kb
Host smart-643160b6-2426-499a-a37a-d6924264507e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2541993997 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.2541993997
Directory /workspace/32.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.2814751343
Short name T200
Test name
Test status
Simulation time 337100150000 ps
CPU time 895.75 seconds
Started Jul 30 05:25:19 PM PDT 24
Finished Jul 30 06:03:53 PM PDT 24
Peak memory 160804 kb
Host smart-005924e4-5f9e-49b9-94e5-53c55ff443ce
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2814751343 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.2814751343
Directory /workspace/33.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.3628779765
Short name T23
Test name
Test status
Simulation time 337096190000 ps
CPU time 733.76 seconds
Started Jul 30 05:25:24 PM PDT 24
Finished Jul 30 05:55:19 PM PDT 24
Peak memory 160856 kb
Host smart-55198f63-6b90-494a-ac56-f216fe180e03
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3628779765 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.3628779765
Directory /workspace/34.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.4106092371
Short name T190
Test name
Test status
Simulation time 336808350000 ps
CPU time 706.02 seconds
Started Jul 30 05:25:17 PM PDT 24
Finished Jul 30 05:54:10 PM PDT 24
Peak memory 160808 kb
Host smart-b726d06b-73f7-4b7a-a809-04b7fb6eeb1e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4106092371 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.4106092371
Directory /workspace/35.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.1040788504
Short name T161
Test name
Test status
Simulation time 336379430000 ps
CPU time 1003.9 seconds
Started Jul 30 05:25:22 PM PDT 24
Finished Jul 30 06:06:09 PM PDT 24
Peak memory 160816 kb
Host smart-e6aec342-de8f-4436-99b1-67fac9ba9cb0
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1040788504 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.1040788504
Directory /workspace/36.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.2996096184
Short name T198
Test name
Test status
Simulation time 336386610000 ps
CPU time 842.21 seconds
Started Jul 30 05:25:23 PM PDT 24
Finished Jul 30 05:59:33 PM PDT 24
Peak memory 160836 kb
Host smart-d1cd3e7a-478e-48b8-b82a-f7b38473c7a1
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2996096184 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.2996096184
Directory /workspace/37.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.1497918570
Short name T186
Test name
Test status
Simulation time 336401710000 ps
CPU time 912.11 seconds
Started Jul 30 05:25:20 PM PDT 24
Finished Jul 30 06:04:21 PM PDT 24
Peak memory 160804 kb
Host smart-372c44ed-7ab5-463f-ad93-bcd41b23bcee
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1497918570 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.1497918570
Directory /workspace/38.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.1408925610
Short name T197
Test name
Test status
Simulation time 336805450000 ps
CPU time 810.92 seconds
Started Jul 30 05:25:25 PM PDT 24
Finished Jul 30 05:58:39 PM PDT 24
Peak memory 160804 kb
Host smart-a1daef82-d3cc-4a85-b25d-7d01f9ba3cfa
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1408925610 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.1408925610
Directory /workspace/39.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.479339072
Short name T182
Test name
Test status
Simulation time 336399630000 ps
CPU time 763.78 seconds
Started Jul 30 05:25:15 PM PDT 24
Finished Jul 30 05:56:13 PM PDT 24
Peak memory 160764 kb
Host smart-38f1a90b-cc53-454f-8376-74a66b2712f2
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=479339072 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.479339072
Directory /workspace/4.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.4043639886
Short name T181
Test name
Test status
Simulation time 336611550000 ps
CPU time 1005.81 seconds
Started Jul 30 05:25:22 PM PDT 24
Finished Jul 30 06:05:29 PM PDT 24
Peak memory 160856 kb
Host smart-a67b4c1f-3aaf-40b5-a44c-abad03186629
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4043639886 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.4043639886
Directory /workspace/40.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.1183744408
Short name T173
Test name
Test status
Simulation time 337031910000 ps
CPU time 866.29 seconds
Started Jul 30 05:25:25 PM PDT 24
Finished Jul 30 06:01:16 PM PDT 24
Peak memory 160800 kb
Host smart-b3887901-b524-4042-ae41-6e5a646f53e4
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1183744408 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.1183744408
Directory /workspace/41.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.2873985808
Short name T164
Test name
Test status
Simulation time 336986010000 ps
CPU time 879.64 seconds
Started Jul 30 05:25:23 PM PDT 24
Finished Jul 30 06:00:17 PM PDT 24
Peak memory 160824 kb
Host smart-023bdb33-a287-4718-bc6b-df350c0e2af5
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2873985808 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.2873985808
Directory /workspace/42.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.2591122231
Short name T188
Test name
Test status
Simulation time 336937150000 ps
CPU time 807.59 seconds
Started Jul 30 05:25:22 PM PDT 24
Finished Jul 30 05:57:46 PM PDT 24
Peak memory 160788 kb
Host smart-09c11016-b3c8-473a-b1c6-245989d24e8b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2591122231 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.2591122231
Directory /workspace/43.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.2361069997
Short name T169
Test name
Test status
Simulation time 336890810000 ps
CPU time 982.87 seconds
Started Jul 30 05:25:23 PM PDT 24
Finished Jul 30 06:05:34 PM PDT 24
Peak memory 160808 kb
Host smart-6daf3a06-b6ce-4bb8-a86d-cdfb8f9cf0b0
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2361069997 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.2361069997
Directory /workspace/44.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.1632131361
Short name T27
Test name
Test status
Simulation time 336386350000 ps
CPU time 919.52 seconds
Started Jul 30 05:25:24 PM PDT 24
Finished Jul 30 06:03:51 PM PDT 24
Peak memory 160812 kb
Host smart-86ec0052-3ba1-45d9-b0c1-3e0f78974883
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1632131361 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.1632131361
Directory /workspace/45.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.2056237251
Short name T185
Test name
Test status
Simulation time 336673650000 ps
CPU time 738.44 seconds
Started Jul 30 05:25:22 PM PDT 24
Finished Jul 30 05:55:34 PM PDT 24
Peak memory 160800 kb
Host smart-3b29e46f-a9c8-4ba3-b2d1-e69bbc749fad
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2056237251 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.2056237251
Directory /workspace/46.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.1060854910
Short name T174
Test name
Test status
Simulation time 336741730000 ps
CPU time 863.3 seconds
Started Jul 30 05:25:22 PM PDT 24
Finished Jul 30 05:59:53 PM PDT 24
Peak memory 160800 kb
Host smart-f7a1eca4-1e34-4f32-ade9-13d507559446
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1060854910 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.1060854910
Directory /workspace/47.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.17386195
Short name T26
Test name
Test status
Simulation time 336778450000 ps
CPU time 780.2 seconds
Started Jul 30 05:25:23 PM PDT 24
Finished Jul 30 05:56:50 PM PDT 24
Peak memory 160712 kb
Host smart-bcd28e9c-04a3-4a6e-8c1d-904d7631cc94
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=17386195 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.17386195
Directory /workspace/48.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.2679422674
Short name T172
Test name
Test status
Simulation time 336572970000 ps
CPU time 677.65 seconds
Started Jul 30 05:25:25 PM PDT 24
Finished Jul 30 05:53:18 PM PDT 24
Peak memory 160848 kb
Host smart-14d112ce-9944-48f7-93f6-7b8f2ace3b72
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2679422674 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.2679422674
Directory /workspace/49.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.1585470309
Short name T184
Test name
Test status
Simulation time 337048790000 ps
CPU time 918.41 seconds
Started Jul 30 05:25:15 PM PDT 24
Finished Jul 30 06:03:31 PM PDT 24
Peak memory 160804 kb
Host smart-882b6bd8-b39d-40e3-9ad7-cb54e59c0f9f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1585470309 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.1585470309
Directory /workspace/5.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.875564888
Short name T28
Test name
Test status
Simulation time 336400950000 ps
CPU time 824.41 seconds
Started Jul 30 05:25:13 PM PDT 24
Finished Jul 30 05:58:14 PM PDT 24
Peak memory 160836 kb
Host smart-0972e0d6-7dad-42db-87ba-69a445b3655f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=875564888 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.875564888
Directory /workspace/6.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.1366620948
Short name T178
Test name
Test status
Simulation time 336597630000 ps
CPU time 845.52 seconds
Started Jul 30 05:25:16 PM PDT 24
Finished Jul 30 06:00:13 PM PDT 24
Peak memory 160800 kb
Host smart-8ad6bda0-8acc-4dc7-bdc4-1d7957b58439
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1366620948 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.1366620948
Directory /workspace/7.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.2109195346
Short name T191
Test name
Test status
Simulation time 336382770000 ps
CPU time 815.93 seconds
Started Jul 30 05:25:10 PM PDT 24
Finished Jul 30 05:58:45 PM PDT 24
Peak memory 160864 kb
Host smart-eb0b0d06-ad9c-4618-a709-32b70fcc4b89
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2109195346 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.2109195346
Directory /workspace/8.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.2898635566
Short name T192
Test name
Test status
Simulation time 336522710000 ps
CPU time 853.01 seconds
Started Jul 30 05:25:13 PM PDT 24
Finished Jul 30 05:59:26 PM PDT 24
Peak memory 160776 kb
Host smart-cbf07ab2-27b8-40ef-8094-d28b03ba2459
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2898635566 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.2898635566
Directory /workspace/9.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.854780529
Short name T114
Test name
Test status
Simulation time 1384350000 ps
CPU time 4.67 seconds
Started Jul 30 05:19:54 PM PDT 24
Finished Jul 30 05:20:04 PM PDT 24
Peak memory 164868 kb
Host smart-454519cc-284e-4e5d-8a23-c04f1b1d0168
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=854780529 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.854780529
Directory /workspace/0.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.3209096125
Short name T148
Test name
Test status
Simulation time 1375370000 ps
CPU time 3.77 seconds
Started Jul 30 05:19:53 PM PDT 24
Finished Jul 30 05:20:02 PM PDT 24
Peak memory 164876 kb
Host smart-526926b4-2e30-4918-b80e-2bdd193dbdae
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3209096125 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.3209096125
Directory /workspace/1.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.2648948629
Short name T150
Test name
Test status
Simulation time 1330990000 ps
CPU time 5.04 seconds
Started Jul 30 05:19:58 PM PDT 24
Finished Jul 30 05:20:09 PM PDT 24
Peak memory 164944 kb
Host smart-1a03a96f-926b-4a3c-8a7a-3d1e18b756e5
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2648948629 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.2648948629
Directory /workspace/10.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.1294968795
Short name T126
Test name
Test status
Simulation time 1425890000 ps
CPU time 3.4 seconds
Started Jul 30 05:20:01 PM PDT 24
Finished Jul 30 05:20:08 PM PDT 24
Peak memory 164976 kb
Host smart-0e01d0c1-bf7f-43dc-ac55-46b15b244b9e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1294968795 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.1294968795
Directory /workspace/11.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.520317530
Short name T152
Test name
Test status
Simulation time 1496070000 ps
CPU time 5.36 seconds
Started Jul 30 05:19:59 PM PDT 24
Finished Jul 30 05:20:11 PM PDT 24
Peak memory 165008 kb
Host smart-85f5cad0-b575-4bc8-9bc3-c32ae073e407
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=520317530 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.520317530
Directory /workspace/12.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.3036370455
Short name T149
Test name
Test status
Simulation time 1514970000 ps
CPU time 5.85 seconds
Started Jul 30 05:20:03 PM PDT 24
Finished Jul 30 05:20:17 PM PDT 24
Peak memory 164932 kb
Host smart-5bdbf2d3-40c2-44ac-9de2-18cf4ec55533
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3036370455 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.3036370455
Directory /workspace/13.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.638655985
Short name T115
Test name
Test status
Simulation time 1422870000 ps
CPU time 4.81 seconds
Started Jul 30 05:20:04 PM PDT 24
Finished Jul 30 05:20:15 PM PDT 24
Peak memory 164924 kb
Host smart-5911db12-6e9b-4a58-b35c-3c4ebea13bb7
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=638655985 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.638655985
Directory /workspace/14.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.296938071
Short name T135
Test name
Test status
Simulation time 1491670000 ps
CPU time 4.14 seconds
Started Jul 30 05:20:05 PM PDT 24
Finished Jul 30 05:20:14 PM PDT 24
Peak memory 164872 kb
Host smart-b193084c-8621-4980-a4b3-a018a46f113d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=296938071 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.296938071
Directory /workspace/15.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.1748697003
Short name T120
Test name
Test status
Simulation time 1382530000 ps
CPU time 5.67 seconds
Started Jul 30 05:20:04 PM PDT 24
Finished Jul 30 05:20:17 PM PDT 24
Peak memory 164900 kb
Host smart-b1605865-d4f0-4013-a52e-caa3ea7d5628
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1748697003 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.1748697003
Directory /workspace/16.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.937916967
Short name T145
Test name
Test status
Simulation time 1480470000 ps
CPU time 5.59 seconds
Started Jul 30 05:20:12 PM PDT 24
Finished Jul 30 05:20:25 PM PDT 24
Peak memory 164960 kb
Host smart-582d8b28-cf9a-47b4-88bb-558287234c6a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=937916967 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.937916967
Directory /workspace/17.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.2434900418
Short name T123
Test name
Test status
Simulation time 1471810000 ps
CPU time 3.83 seconds
Started Jul 30 05:20:03 PM PDT 24
Finished Jul 30 05:20:12 PM PDT 24
Peak memory 164916 kb
Host smart-0c47c287-32e6-49e6-bd66-86eb90bb2ac6
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2434900418 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.2434900418
Directory /workspace/18.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.2384557392
Short name T111
Test name
Test status
Simulation time 1537630000 ps
CPU time 4.9 seconds
Started Jul 30 05:20:13 PM PDT 24
Finished Jul 30 05:20:24 PM PDT 24
Peak memory 164936 kb
Host smart-f216ff9f-4304-4b45-9a51-c771786d19e2
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2384557392 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.2384557392
Directory /workspace/19.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.1127728518
Short name T138
Test name
Test status
Simulation time 969830000 ps
CPU time 3.1 seconds
Started Jul 30 05:19:53 PM PDT 24
Finished Jul 30 05:20:00 PM PDT 24
Peak memory 164872 kb
Host smart-1b4e6005-5795-4af1-b895-bdeda05023e7
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1127728518 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.1127728518
Directory /workspace/2.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.1331787713
Short name T117
Test name
Test status
Simulation time 1454370000 ps
CPU time 5.37 seconds
Started Jul 30 05:20:07 PM PDT 24
Finished Jul 30 05:20:19 PM PDT 24
Peak memory 164912 kb
Host smart-15a530a3-2aec-447d-86b2-0e96a70fe5af
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1331787713 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.1331787713
Directory /workspace/20.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.2620856916
Short name T157
Test name
Test status
Simulation time 1525710000 ps
CPU time 4.82 seconds
Started Jul 30 05:20:12 PM PDT 24
Finished Jul 30 05:20:23 PM PDT 24
Peak memory 164936 kb
Host smart-c6d753e3-540e-4616-a26b-2a345893f717
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2620856916 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.2620856916
Directory /workspace/21.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.3201408769
Short name T153
Test name
Test status
Simulation time 1518430000 ps
CPU time 4.9 seconds
Started Jul 30 05:20:13 PM PDT 24
Finished Jul 30 05:20:25 PM PDT 24
Peak memory 164936 kb
Host smart-b535524e-8b8f-4038-a462-cb2069f56abe
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3201408769 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.3201408769
Directory /workspace/22.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.3444296836
Short name T160
Test name
Test status
Simulation time 1295050000 ps
CPU time 3.73 seconds
Started Jul 30 05:20:06 PM PDT 24
Finished Jul 30 05:20:15 PM PDT 24
Peak memory 164880 kb
Host smart-96150d4c-f844-4571-9a05-ccc0f62d1b57
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3444296836 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.3444296836
Directory /workspace/23.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.4000871490
Short name T146
Test name
Test status
Simulation time 1466750000 ps
CPU time 6.02 seconds
Started Jul 30 05:20:10 PM PDT 24
Finished Jul 30 05:20:23 PM PDT 24
Peak memory 164800 kb
Host smart-8e189235-3785-4dcb-9c91-db1f333b3d0e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4000871490 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.4000871490
Directory /workspace/24.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.1193109478
Short name T155
Test name
Test status
Simulation time 1558310000 ps
CPU time 5.04 seconds
Started Jul 30 05:20:07 PM PDT 24
Finished Jul 30 05:20:18 PM PDT 24
Peak memory 164960 kb
Host smart-c81458e7-d1e4-4e0c-9381-332b7f549251
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1193109478 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.1193109478
Directory /workspace/25.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.680162921
Short name T131
Test name
Test status
Simulation time 1483410000 ps
CPU time 4.12 seconds
Started Jul 30 05:20:08 PM PDT 24
Finished Jul 30 05:20:17 PM PDT 24
Peak memory 164992 kb
Host smart-43805bae-ca50-4ea9-8c93-63b67861f44c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=680162921 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.680162921
Directory /workspace/26.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.1055393373
Short name T159
Test name
Test status
Simulation time 1445730000 ps
CPU time 3.3 seconds
Started Jul 30 05:20:08 PM PDT 24
Finished Jul 30 05:20:16 PM PDT 24
Peak memory 164988 kb
Host smart-df147076-2ef8-4ab4-89fa-fa089882c6c3
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1055393373 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.1055393373
Directory /workspace/27.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.2976588430
Short name T116
Test name
Test status
Simulation time 1481470000 ps
CPU time 5.53 seconds
Started Jul 30 05:20:06 PM PDT 24
Finished Jul 30 05:20:18 PM PDT 24
Peak memory 164892 kb
Host smart-891fb38e-443f-434f-8973-8c798469057b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2976588430 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.2976588430
Directory /workspace/28.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.293939266
Short name T133
Test name
Test status
Simulation time 1505470000 ps
CPU time 4.77 seconds
Started Jul 30 05:20:12 PM PDT 24
Finished Jul 30 05:20:23 PM PDT 24
Peak memory 164928 kb
Host smart-4e24a2f1-6b90-446f-992d-1ac503166edf
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=293939266 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.293939266
Directory /workspace/29.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.3982580782
Short name T119
Test name
Test status
Simulation time 1628450000 ps
CPU time 5.8 seconds
Started Jul 30 05:19:53 PM PDT 24
Finished Jul 30 05:20:07 PM PDT 24
Peak memory 165008 kb
Host smart-0b7135ba-0cc4-4614-a7fd-490231a5bad1
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3982580782 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.3982580782
Directory /workspace/3.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.1121073489
Short name T142
Test name
Test status
Simulation time 1489490000 ps
CPU time 4.98 seconds
Started Jul 30 05:20:12 PM PDT 24
Finished Jul 30 05:20:23 PM PDT 24
Peak memory 164936 kb
Host smart-a80b924f-d4ef-47b7-b4fd-1d92416d48dc
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1121073489 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.1121073489
Directory /workspace/30.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.3059883411
Short name T140
Test name
Test status
Simulation time 1452830000 ps
CPU time 4.09 seconds
Started Jul 30 05:20:11 PM PDT 24
Finished Jul 30 05:20:20 PM PDT 24
Peak memory 164972 kb
Host smart-6f455bbb-18a7-454a-973b-7fdeb4a002d1
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3059883411 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.3059883411
Directory /workspace/31.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.2637324839
Short name T129
Test name
Test status
Simulation time 1507030000 ps
CPU time 6.18 seconds
Started Jul 30 05:20:09 PM PDT 24
Finished Jul 30 05:20:23 PM PDT 24
Peak memory 164800 kb
Host smart-d53e50b5-f056-4a02-a4c6-b9c9a323ed63
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2637324839 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.2637324839
Directory /workspace/32.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.1189289762
Short name T158
Test name
Test status
Simulation time 1419070000 ps
CPU time 4.46 seconds
Started Jul 30 05:20:12 PM PDT 24
Finished Jul 30 05:20:23 PM PDT 24
Peak memory 164856 kb
Host smart-5325abfd-9bb7-44f9-8920-fd8e0456a27c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1189289762 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.1189289762
Directory /workspace/33.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.4185218057
Short name T121
Test name
Test status
Simulation time 1512110000 ps
CPU time 4.18 seconds
Started Jul 30 05:20:12 PM PDT 24
Finished Jul 30 05:20:21 PM PDT 24
Peak memory 164888 kb
Host smart-2d783198-8584-4b89-8bca-8326e733f492
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4185218057 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.4185218057
Directory /workspace/34.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.362285581
Short name T132
Test name
Test status
Simulation time 1422030000 ps
CPU time 5.46 seconds
Started Jul 30 05:20:12 PM PDT 24
Finished Jul 30 05:20:24 PM PDT 24
Peak memory 164920 kb
Host smart-32fa067e-3afc-41c3-aefc-277b5ad40506
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=362285581 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.362285581
Directory /workspace/35.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.316736308
Short name T124
Test name
Test status
Simulation time 1413430000 ps
CPU time 5.5 seconds
Started Jul 30 05:20:14 PM PDT 24
Finished Jul 30 05:20:26 PM PDT 24
Peak memory 164876 kb
Host smart-4e2704a8-ca7e-4a59-b9a0-d767789956ca
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=316736308 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.316736308
Directory /workspace/36.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.2129012416
Short name T141
Test name
Test status
Simulation time 1511390000 ps
CPU time 4.41 seconds
Started Jul 30 05:20:13 PM PDT 24
Finished Jul 30 05:20:23 PM PDT 24
Peak memory 164872 kb
Host smart-26aaaee3-0257-43dd-8090-e8078fbc096a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2129012416 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.2129012416
Directory /workspace/37.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.3864997837
Short name T144
Test name
Test status
Simulation time 1544890000 ps
CPU time 4.85 seconds
Started Jul 30 05:20:14 PM PDT 24
Finished Jul 30 05:20:24 PM PDT 24
Peak memory 164896 kb
Host smart-3c4d807f-6556-42ef-ab0a-594ffe457d1d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3864997837 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.3864997837
Directory /workspace/38.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.2797041297
Short name T134
Test name
Test status
Simulation time 1570690000 ps
CPU time 3.54 seconds
Started Jul 30 05:20:13 PM PDT 24
Finished Jul 30 05:20:21 PM PDT 24
Peak memory 164988 kb
Host smart-30449be2-8c7e-4b6d-8bb9-b92a5fe43118
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2797041297 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.2797041297
Directory /workspace/39.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3917835422
Short name T118
Test name
Test status
Simulation time 1381550000 ps
CPU time 3.87 seconds
Started Jul 30 05:19:53 PM PDT 24
Finished Jul 30 05:20:01 PM PDT 24
Peak memory 164968 kb
Host smart-a8651621-c6ad-4528-8c11-556e1306a09f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3917835422 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.3917835422
Directory /workspace/4.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.471963670
Short name T125
Test name
Test status
Simulation time 1365230000 ps
CPU time 5.04 seconds
Started Jul 30 05:20:17 PM PDT 24
Finished Jul 30 05:20:28 PM PDT 24
Peak memory 164992 kb
Host smart-759158c4-5dbc-4233-9ab7-2cf298a1e75c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=471963670 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.471963670
Directory /workspace/40.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.1096534733
Short name T139
Test name
Test status
Simulation time 1449350000 ps
CPU time 4.24 seconds
Started Jul 30 05:20:18 PM PDT 24
Finished Jul 30 05:20:27 PM PDT 24
Peak memory 164936 kb
Host smart-b98b6d5d-6683-4f6c-a119-020f9e605360
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1096534733 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.1096534733
Directory /workspace/41.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.709371945
Short name T154
Test name
Test status
Simulation time 1164950000 ps
CPU time 3.05 seconds
Started Jul 30 05:20:18 PM PDT 24
Finished Jul 30 05:20:24 PM PDT 24
Peak memory 164892 kb
Host smart-034a9c9f-8296-4bdb-920f-14d2757414b1
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=709371945 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.709371945
Directory /workspace/42.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.2692788967
Short name T156
Test name
Test status
Simulation time 1516450000 ps
CPU time 4.23 seconds
Started Jul 30 05:20:17 PM PDT 24
Finished Jul 30 05:20:26 PM PDT 24
Peak memory 164972 kb
Host smart-086812e4-cf24-4ba5-b0e3-d86f0cb54810
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2692788967 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.2692788967
Directory /workspace/43.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.1986337421
Short name T127
Test name
Test status
Simulation time 1237130000 ps
CPU time 2.81 seconds
Started Jul 30 05:20:17 PM PDT 24
Finished Jul 30 05:20:23 PM PDT 24
Peak memory 164940 kb
Host smart-5f59bddc-acbc-4747-9c79-789123d888a3
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1986337421 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.1986337421
Directory /workspace/44.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.1274195057
Short name T130
Test name
Test status
Simulation time 1318690000 ps
CPU time 2.86 seconds
Started Jul 30 05:20:15 PM PDT 24
Finished Jul 30 05:20:22 PM PDT 24
Peak memory 164892 kb
Host smart-59c1b42e-0463-438d-b74e-6172c252dd0e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1274195057 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.1274195057
Directory /workspace/45.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.2130263426
Short name T136
Test name
Test status
Simulation time 1589170000 ps
CPU time 5.97 seconds
Started Jul 30 05:20:19 PM PDT 24
Finished Jul 30 05:20:33 PM PDT 24
Peak memory 164880 kb
Host smart-b464f967-6ba8-4d04-8da7-443568c0e33e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2130263426 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.2130263426
Directory /workspace/46.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.1657641338
Short name T128
Test name
Test status
Simulation time 1605630000 ps
CPU time 6.04 seconds
Started Jul 30 05:20:21 PM PDT 24
Finished Jul 30 05:20:34 PM PDT 24
Peak memory 164852 kb
Host smart-55239a48-7e8c-4ec8-bc6c-4d1e1676e24b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1657641338 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.1657641338
Directory /workspace/47.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.3777099584
Short name T113
Test name
Test status
Simulation time 1469870000 ps
CPU time 6.07 seconds
Started Jul 30 05:20:28 PM PDT 24
Finished Jul 30 05:20:42 PM PDT 24
Peak memory 164972 kb
Host smart-1c236d26-c5a5-40b4-b4a9-062d645f3699
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3777099584 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.3777099584
Directory /workspace/48.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.2152388529
Short name T137
Test name
Test status
Simulation time 1527310000 ps
CPU time 4.66 seconds
Started Jul 30 05:20:23 PM PDT 24
Finished Jul 30 05:20:33 PM PDT 24
Peak memory 164976 kb
Host smart-4ef4458c-4f16-4e7e-90d9-9d58169b53ec
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2152388529 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.2152388529
Directory /workspace/49.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.417748776
Short name T112
Test name
Test status
Simulation time 1361590000 ps
CPU time 3.29 seconds
Started Jul 30 05:19:53 PM PDT 24
Finished Jul 30 05:20:00 PM PDT 24
Peak memory 164908 kb
Host smart-c5b7d1de-77ed-467a-882b-7568e84976db
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=417748776 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.417748776
Directory /workspace/5.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.1500613673
Short name T147
Test name
Test status
Simulation time 1339610000 ps
CPU time 4.72 seconds
Started Jul 30 05:19:56 PM PDT 24
Finished Jul 30 05:20:06 PM PDT 24
Peak memory 164912 kb
Host smart-3dc06965-941d-4a1b-b4b9-44d6b4c23586
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1500613673 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.1500613673
Directory /workspace/6.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.1522930243
Short name T143
Test name
Test status
Simulation time 1461750000 ps
CPU time 4.25 seconds
Started Jul 30 05:19:58 PM PDT 24
Finished Jul 30 05:20:07 PM PDT 24
Peak memory 164900 kb
Host smart-e44ffa4e-19d0-4e15-9aea-f456781ced3d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1522930243 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.1522930243
Directory /workspace/7.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1745104250
Short name T151
Test name
Test status
Simulation time 1363470000 ps
CPU time 3.89 seconds
Started Jul 30 05:19:59 PM PDT 24
Finished Jul 30 05:20:08 PM PDT 24
Peak memory 164976 kb
Host smart-f8660a8c-850e-450f-9153-08052223ac0f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1745104250 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.1745104250
Directory /workspace/8.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.1185963901
Short name T122
Test name
Test status
Simulation time 1533630000 ps
CPU time 3.52 seconds
Started Jul 30 05:19:57 PM PDT 24
Finished Jul 30 05:20:05 PM PDT 24
Peak memory 164964 kb
Host smart-a63f7bc6-1890-4edb-818b-4d58910e4185
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1185963901 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.1185963901
Directory /workspace/9.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.3858219762
Short name T66
Test name
Test status
Simulation time 1289710000 ps
CPU time 3.18 seconds
Started Jul 30 04:30:47 PM PDT 24
Finished Jul 30 04:30:54 PM PDT 24
Peak memory 163268 kb
Host smart-f48c2164-3763-4010-b01b-690075a40a5a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3858219762 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.3858219762
Directory /workspace/0.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.3279241626
Short name T46
Test name
Test status
Simulation time 1366250000 ps
CPU time 4.33 seconds
Started Jul 30 04:27:43 PM PDT 24
Finished Jul 30 04:27:53 PM PDT 24
Peak memory 164764 kb
Host smart-2bf71b3e-50b9-4fc8-8f83-7540f70cc70d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3279241626 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.3279241626
Directory /workspace/10.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.1928280109
Short name T60
Test name
Test status
Simulation time 1503070000 ps
CPU time 4.72 seconds
Started Jul 30 04:27:30 PM PDT 24
Finished Jul 30 04:27:41 PM PDT 24
Peak memory 164240 kb
Host smart-14b9d2dd-b792-444a-a103-341bc1030881
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1928280109 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.1928280109
Directory /workspace/11.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.3585227516
Short name T43
Test name
Test status
Simulation time 1258670000 ps
CPU time 3.53 seconds
Started Jul 30 04:31:58 PM PDT 24
Finished Jul 30 04:32:06 PM PDT 24
Peak memory 164756 kb
Host smart-cd529862-161d-4018-ad4f-dc8f2dc6379d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3585227516 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.3585227516
Directory /workspace/12.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.249027546
Short name T39
Test name
Test status
Simulation time 1488950000 ps
CPU time 5.9 seconds
Started Jul 30 04:26:54 PM PDT 24
Finished Jul 30 04:27:07 PM PDT 24
Peak memory 164824 kb
Host smart-f776b923-8b25-4ab2-8c91-0a013985626a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=249027546 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.249027546
Directory /workspace/13.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.658867833
Short name T63
Test name
Test status
Simulation time 1370510000 ps
CPU time 4.45 seconds
Started Jul 30 04:27:30 PM PDT 24
Finished Jul 30 04:27:40 PM PDT 24
Peak memory 164220 kb
Host smart-6437063a-9729-4807-bd6f-dacdc40a2731
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=658867833 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.658867833
Directory /workspace/14.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.358993255
Short name T35
Test name
Test status
Simulation time 1323590000 ps
CPU time 4.38 seconds
Started Jul 30 04:27:30 PM PDT 24
Finished Jul 30 04:27:40 PM PDT 24
Peak memory 165224 kb
Host smart-5cdae13a-a49d-46f9-813f-eb48b01e79ae
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=358993255 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.358993255
Directory /workspace/15.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.405085578
Short name T64
Test name
Test status
Simulation time 1397810000 ps
CPU time 3.09 seconds
Started Jul 30 04:30:46 PM PDT 24
Finished Jul 30 04:30:53 PM PDT 24
Peak memory 164440 kb
Host smart-01d4bca0-6da1-4017-818d-855fe5085484
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=405085578 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.405085578
Directory /workspace/16.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.2964615549
Short name T65
Test name
Test status
Simulation time 1472070000 ps
CPU time 4.08 seconds
Started Jul 30 04:29:21 PM PDT 24
Finished Jul 30 04:29:30 PM PDT 24
Peak memory 164704 kb
Host smart-78c905bc-1069-479f-8268-bb5b66549113
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2964615549 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.2964615549
Directory /workspace/17.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.4096980001
Short name T37
Test name
Test status
Simulation time 1593210000 ps
CPU time 4.85 seconds
Started Jul 30 04:27:30 PM PDT 24
Finished Jul 30 04:27:41 PM PDT 24
Peak memory 164240 kb
Host smart-596a7b3b-bdb9-4ea8-8f68-182ec867b98e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4096980001 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.4096980001
Directory /workspace/18.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.1934731592
Short name T49
Test name
Test status
Simulation time 1410970000 ps
CPU time 4.23 seconds
Started Jul 30 04:27:30 PM PDT 24
Finished Jul 30 04:27:40 PM PDT 24
Peak memory 164496 kb
Host smart-ffedd050-cec3-4090-8ac2-d70f407cd977
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1934731592 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.1934731592
Directory /workspace/19.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.1466739469
Short name T42
Test name
Test status
Simulation time 1459790000 ps
CPU time 4.24 seconds
Started Jul 30 04:27:39 PM PDT 24
Finished Jul 30 04:27:49 PM PDT 24
Peak memory 164328 kb
Host smart-c82f5ebb-baa2-41a1-9a76-e171504115f7
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1466739469 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.1466739469
Directory /workspace/2.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.3683387897
Short name T61
Test name
Test status
Simulation time 1533670000 ps
CPU time 4.33 seconds
Started Jul 30 04:28:14 PM PDT 24
Finished Jul 30 04:28:24 PM PDT 24
Peak memory 164728 kb
Host smart-ab7b381f-cd26-43f5-8fd1-df3dbc9ca4d0
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3683387897 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.3683387897
Directory /workspace/20.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.2545596046
Short name T53
Test name
Test status
Simulation time 1377730000 ps
CPU time 3.82 seconds
Started Jul 30 04:29:21 PM PDT 24
Finished Jul 30 04:29:29 PM PDT 24
Peak memory 164704 kb
Host smart-cb3f2357-ce38-47e3-b574-06ba8e58cfb8
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2545596046 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.2545596046
Directory /workspace/21.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.704616090
Short name T8
Test name
Test status
Simulation time 1429850000 ps
CPU time 4.18 seconds
Started Jul 30 04:30:10 PM PDT 24
Finished Jul 30 04:30:20 PM PDT 24
Peak memory 164784 kb
Host smart-1b63afad-89f3-402d-8284-a1138ee2af3a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=704616090 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.704616090
Directory /workspace/22.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.2339352227
Short name T32
Test name
Test status
Simulation time 1245530000 ps
CPU time 4.35 seconds
Started Jul 30 04:26:12 PM PDT 24
Finished Jul 30 04:26:21 PM PDT 24
Peak memory 164596 kb
Host smart-f0d317d0-9173-47ca-b566-6fa24ac83568
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2339352227 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.2339352227
Directory /workspace/23.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.1872136048
Short name T45
Test name
Test status
Simulation time 1553450000 ps
CPU time 5.13 seconds
Started Jul 30 04:27:30 PM PDT 24
Finished Jul 30 04:27:41 PM PDT 24
Peak memory 163000 kb
Host smart-10e10fb6-9b9a-47d8-b0b1-162b9f0f70d6
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1872136048 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.1872136048
Directory /workspace/24.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.3529561451
Short name T56
Test name
Test status
Simulation time 1546270000 ps
CPU time 4.26 seconds
Started Jul 30 04:31:58 PM PDT 24
Finished Jul 30 04:32:08 PM PDT 24
Peak memory 164756 kb
Host smart-e77ad2a6-1da4-4680-9d35-59f88308c696
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3529561451 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.3529561451
Directory /workspace/25.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.1603427952
Short name T10
Test name
Test status
Simulation time 1511710000 ps
CPU time 3.42 seconds
Started Jul 30 04:30:45 PM PDT 24
Finished Jul 30 04:30:53 PM PDT 24
Peak memory 163084 kb
Host smart-c3b324dd-5d60-420a-b396-7e6195ae2f96
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1603427952 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.1603427952
Directory /workspace/26.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.2895965497
Short name T69
Test name
Test status
Simulation time 1459950000 ps
CPU time 4.27 seconds
Started Jul 30 04:29:11 PM PDT 24
Finished Jul 30 04:29:21 PM PDT 24
Peak memory 164736 kb
Host smart-b691f261-f7de-44a1-bb57-7dc53cb44ce3
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2895965497 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.2895965497
Directory /workspace/27.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.1937469568
Short name T58
Test name
Test status
Simulation time 1212910000 ps
CPU time 3.55 seconds
Started Jul 30 04:29:09 PM PDT 24
Finished Jul 30 04:29:16 PM PDT 24
Peak memory 164740 kb
Host smart-17984292-b137-4ff0-8d75-faf04b241162
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1937469568 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.1937469568
Directory /workspace/28.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.1556908168
Short name T38
Test name
Test status
Simulation time 1501110000 ps
CPU time 5.2 seconds
Started Jul 30 04:26:23 PM PDT 24
Finished Jul 30 04:26:35 PM PDT 24
Peak memory 163212 kb
Host smart-a57a4a61-bea2-41cf-88d0-0bd9da64a71b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1556908168 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.1556908168
Directory /workspace/29.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.1794268604
Short name T33
Test name
Test status
Simulation time 1429570000 ps
CPU time 5.05 seconds
Started Jul 30 04:27:29 PM PDT 24
Finished Jul 30 04:27:40 PM PDT 24
Peak memory 164772 kb
Host smart-4bf78995-1f4e-4f4b-801a-6ef7383615fd
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1794268604 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.1794268604
Directory /workspace/3.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.2494784127
Short name T68
Test name
Test status
Simulation time 1572910000 ps
CPU time 5.42 seconds
Started Jul 30 04:26:56 PM PDT 24
Finished Jul 30 04:27:08 PM PDT 24
Peak memory 165876 kb
Host smart-1dcaf0d0-7f7d-45e1-af21-b5876e5ccdb6
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2494784127 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.2494784127
Directory /workspace/30.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.3744192801
Short name T9
Test name
Test status
Simulation time 1254930000 ps
CPU time 2.54 seconds
Started Jul 30 04:30:53 PM PDT 24
Finished Jul 30 04:30:59 PM PDT 24
Peak memory 163528 kb
Host smart-5b24082b-7546-4e04-a93f-2be8775b5161
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3744192801 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.3744192801
Directory /workspace/31.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.299659139
Short name T13
Test name
Test status
Simulation time 1422850000 ps
CPU time 3.02 seconds
Started Jul 30 04:26:46 PM PDT 24
Finished Jul 30 04:26:53 PM PDT 24
Peak memory 164628 kb
Host smart-d5a37790-1d34-423a-81ae-77b46447909a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=299659139 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.299659139
Directory /workspace/32.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.829971173
Short name T55
Test name
Test status
Simulation time 1258350000 ps
CPU time 2.68 seconds
Started Jul 30 04:30:49 PM PDT 24
Finished Jul 30 04:30:55 PM PDT 24
Peak memory 164324 kb
Host smart-00854255-e462-4de8-96d0-359749b4d2ae
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=829971173 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.829971173
Directory /workspace/33.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.1736205083
Short name T51
Test name
Test status
Simulation time 1474310000 ps
CPU time 3.53 seconds
Started Jul 30 04:31:45 PM PDT 24
Finished Jul 30 04:31:53 PM PDT 24
Peak memory 164200 kb
Host smart-7e10ce78-5d50-4761-9ff1-dfb2647dd5de
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1736205083 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.1736205083
Directory /workspace/34.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.1265632840
Short name T62
Test name
Test status
Simulation time 1426250000 ps
CPU time 3.6 seconds
Started Jul 30 04:31:10 PM PDT 24
Finished Jul 30 04:31:18 PM PDT 24
Peak memory 164752 kb
Host smart-d24a24d2-5c0f-4e40-9820-5df9a58eeff1
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1265632840 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.1265632840
Directory /workspace/35.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.1231824397
Short name T34
Test name
Test status
Simulation time 1533230000 ps
CPU time 3.22 seconds
Started Jul 30 04:30:50 PM PDT 24
Finished Jul 30 04:30:57 PM PDT 24
Peak memory 163088 kb
Host smart-aed5b746-d746-4472-8e4a-3753bdcca717
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1231824397 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.1231824397
Directory /workspace/36.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.2262318356
Short name T1
Test name
Test status
Simulation time 1573310000 ps
CPU time 4.31 seconds
Started Jul 30 04:26:49 PM PDT 24
Finished Jul 30 04:26:58 PM PDT 24
Peak memory 164608 kb
Host smart-93a5dafc-ad62-4c7f-94c9-728cb5887c15
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2262318356 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.2262318356
Directory /workspace/37.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.1959805031
Short name T54
Test name
Test status
Simulation time 1453650000 ps
CPU time 5.42 seconds
Started Jul 30 04:26:33 PM PDT 24
Finished Jul 30 04:26:44 PM PDT 24
Peak memory 164728 kb
Host smart-8ffb2a7a-7ed0-4127-b154-a1b22d1b8a7a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1959805031 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.1959805031
Directory /workspace/38.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.1166195452
Short name T41
Test name
Test status
Simulation time 1580830000 ps
CPU time 6.04 seconds
Started Jul 30 04:26:33 PM PDT 24
Finished Jul 30 04:26:46 PM PDT 24
Peak memory 164728 kb
Host smart-8677743f-da64-4033-99fa-35537ad29905
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1166195452 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.1166195452
Directory /workspace/39.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.347389985
Short name T40
Test name
Test status
Simulation time 1291930000 ps
CPU time 3.13 seconds
Started Jul 30 04:29:29 PM PDT 24
Finished Jul 30 04:29:36 PM PDT 24
Peak memory 164736 kb
Host smart-8b2f097c-41d0-4b20-828c-72d9465aa6d2
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=347389985 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.347389985
Directory /workspace/4.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.1709282266
Short name T57
Test name
Test status
Simulation time 1433810000 ps
CPU time 3.94 seconds
Started Jul 30 04:28:03 PM PDT 24
Finished Jul 30 04:28:12 PM PDT 24
Peak memory 164824 kb
Host smart-0a65de14-44d7-4441-8e28-ea2b6da15e05
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1709282266 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.1709282266
Directory /workspace/40.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.209516327
Short name T44
Test name
Test status
Simulation time 1377130000 ps
CPU time 3.87 seconds
Started Jul 30 04:26:43 PM PDT 24
Finished Jul 30 04:26:52 PM PDT 24
Peak memory 164796 kb
Host smart-17cbb224-e597-4b22-bff1-bba80a26ac1b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=209516327 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.209516327
Directory /workspace/41.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.3148137241
Short name T52
Test name
Test status
Simulation time 1583830000 ps
CPU time 5.11 seconds
Started Jul 30 04:27:07 PM PDT 24
Finished Jul 30 04:27:18 PM PDT 24
Peak memory 164976 kb
Host smart-8ac0a0d4-947f-4852-a13d-d1fdeef1dbd4
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3148137241 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.3148137241
Directory /workspace/42.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.3089252363
Short name T70
Test name
Test status
Simulation time 1506910000 ps
CPU time 4.88 seconds
Started Jul 30 04:31:50 PM PDT 24
Finished Jul 30 04:32:01 PM PDT 24
Peak memory 164716 kb
Host smart-bdb41998-5300-422f-803b-d3daa1015a08
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3089252363 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.3089252363
Directory /workspace/43.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.2378388280
Short name T2
Test name
Test status
Simulation time 1396090000 ps
CPU time 4.98 seconds
Started Jul 30 04:27:22 PM PDT 24
Finished Jul 30 04:27:33 PM PDT 24
Peak memory 164772 kb
Host smart-0c20513a-8e44-42ed-88bd-7c5dc40034a9
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2378388280 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.2378388280
Directory /workspace/44.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.892153164
Short name T50
Test name
Test status
Simulation time 1319210000 ps
CPU time 4.82 seconds
Started Jul 30 04:27:00 PM PDT 24
Finished Jul 30 04:27:12 PM PDT 24
Peak memory 164744 kb
Host smart-a53812e9-0820-40ab-8e1e-6b66db7b7db3
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=892153164 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.892153164
Directory /workspace/45.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.1822238313
Short name T59
Test name
Test status
Simulation time 1521850000 ps
CPU time 4.02 seconds
Started Jul 30 04:28:33 PM PDT 24
Finished Jul 30 04:28:42 PM PDT 24
Peak memory 164736 kb
Host smart-9db44ea2-9683-42df-9908-dda20370496e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1822238313 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.1822238313
Directory /workspace/46.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.3585239980
Short name T11
Test name
Test status
Simulation time 1276550000 ps
CPU time 3.17 seconds
Started Jul 30 04:31:47 PM PDT 24
Finished Jul 30 04:31:54 PM PDT 24
Peak memory 163696 kb
Host smart-2ab686fa-4c93-4137-8bf4-7f2cc73bff55
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3585239980 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.3585239980
Directory /workspace/47.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.3662831075
Short name T31
Test name
Test status
Simulation time 1561690000 ps
CPU time 3.22 seconds
Started Jul 30 04:28:31 PM PDT 24
Finished Jul 30 04:28:38 PM PDT 24
Peak memory 163776 kb
Host smart-38c01608-e9cc-4f6c-9cf8-44bcd469ef7a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3662831075 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.3662831075
Directory /workspace/48.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.3511985906
Short name T47
Test name
Test status
Simulation time 1416190000 ps
CPU time 5.24 seconds
Started Jul 30 04:28:13 PM PDT 24
Finished Jul 30 04:28:24 PM PDT 24
Peak memory 164692 kb
Host smart-9b02f191-3dc6-4871-8193-c019e8e11ce1
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3511985906 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.3511985906
Directory /workspace/49.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.827172309
Short name T12
Test name
Test status
Simulation time 1237950000 ps
CPU time 2.82 seconds
Started Jul 30 04:28:07 PM PDT 24
Finished Jul 30 04:28:13 PM PDT 24
Peak memory 164572 kb
Host smart-c3a9e269-a3c2-4174-b1d9-3069a66bbe28
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=827172309 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.827172309
Directory /workspace/5.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.279998776
Short name T36
Test name
Test status
Simulation time 1390610000 ps
CPU time 4.74 seconds
Started Jul 30 04:27:30 PM PDT 24
Finished Jul 30 04:27:40 PM PDT 24
Peak memory 163028 kb
Host smart-18f35f57-2beb-4b11-a16e-439aaa2fd27a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=279998776 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.279998776
Directory /workspace/6.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.2810943035
Short name T4
Test name
Test status
Simulation time 1483150000 ps
CPU time 4.08 seconds
Started Jul 30 04:31:01 PM PDT 24
Finished Jul 30 04:31:10 PM PDT 24
Peak memory 164636 kb
Host smart-f6e2fee6-3320-40e0-bd54-8819c5455e4a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2810943035 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.2810943035
Directory /workspace/7.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.209702143
Short name T48
Test name
Test status
Simulation time 1575110000 ps
CPU time 5.46 seconds
Started Jul 30 04:30:14 PM PDT 24
Finished Jul 30 04:30:27 PM PDT 24
Peak memory 166304 kb
Host smart-c9462b5a-0b66-4ce1-b70d-73552cdf3a82
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=209702143 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.209702143
Directory /workspace/8.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.2452473064
Short name T67
Test name
Test status
Simulation time 1473410000 ps
CPU time 4.36 seconds
Started Jul 30 04:27:39 PM PDT 24
Finished Jul 30 04:27:49 PM PDT 24
Peak memory 164328 kb
Host smart-501a7331-0d82-4d65-b017-9cd8b2e3633e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2452473064 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.2452473064
Directory /workspace/9.prim_lfsr_gal_smoke/latest
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