Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.31 100.00 96.55 100.00 100.00 95.00


Total tests in report: 200
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
87.31 87.31 100.00 100.00 96.55 96.55 100.00 100.00 100.00 100.00 40.00 40.00 /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.2575383770
96.81 9.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 87.50 47.50 /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2863303776
98.31 1.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 95.00 7.50 /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.3260423555

Tests that do not contribute to grading

Name
/workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.924633235
/workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.1401405472
/workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.1444348689
/workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.1109514506
/workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.983762194
/workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.1796740057
/workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.3137418592
/workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.1204154486
/workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.93529328
/workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.106050841
/workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.3153985319
/workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.2732821940
/workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.3467973681
/workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.335691447
/workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.3599136519
/workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.2190997680
/workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.2044868953
/workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.635062724
/workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.3172421212
/workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.2040941171
/workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.696509951
/workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.1915807177
/workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.1775947976
/workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.2346060328
/workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.1047060924
/workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.2721483807
/workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.2651175222
/workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.1864003702
/workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.109640880
/workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.3657455601
/workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.3820437903
/workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.1450763162
/workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.2045466730
/workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.3492904491
/workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.2836055894
/workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.1098349179
/workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.3031480033
/workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.3503274671
/workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.1056053301
/workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.2596394145
/workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.2050728357
/workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.3274069357
/workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.4053007528
/workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.3186987767
/workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.2161168003
/workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.1066078171
/workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.610096433
/workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1085720690
/workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.1280055582
/workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.4120553612
/workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.2462416561
/workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.1604787432
/workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.3038868280
/workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.3274626964
/workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.576395431
/workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.1264344396
/workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.171559880
/workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.2482267014
/workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.300480712
/workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.1312808485
/workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.2972990108
/workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.1087463369
/workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.386309933
/workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.4194959800
/workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.2640384675
/workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.3783603768
/workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.2089365658
/workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.1962602216
/workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.2336792305
/workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.2762938974
/workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.2069486591
/workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.153315925
/workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.1555052578
/workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.1652300617
/workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.3029617658
/workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.3786428051
/workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.91522846
/workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.153464569
/workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.1985051813
/workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.2586837883
/workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.804936065
/workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.1353824558
/workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.2023141874
/workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.2191929405
/workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.2938087628
/workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.231645110
/workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.1418359099
/workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.15362083
/workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.1281586925
/workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.3769704031
/workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.4259878666
/workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.2489861980
/workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.651670855
/workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.1538262510
/workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.1715790233
/workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.590511996
/workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.2820990643
/workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.3017490926
/workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.484616409
/workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.1694220850
/workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.3267141819
/workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.3561697643
/workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.2552265394
/workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.281684626
/workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.2145784916
/workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.3671158082
/workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.771553033
/workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.3884983011
/workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.3306906189
/workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.1712105318
/workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.3883466445
/workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.2000642294
/workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.1573309363
/workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.1254575249
/workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.740779146
/workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.1359960876
/workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.1161126223
/workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2279451872
/workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.4243145348
/workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.3781993059
/workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.1093612278
/workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.2813259936
/workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.1034217025
/workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.180926896
/workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.665939097
/workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.3145156749
/workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.1848751241
/workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.2177516366
/workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.996257020
/workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1893779650
/workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.4025336791
/workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.1769328588
/workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.2832748230
/workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.3824820213
/workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.1566479741
/workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.3047204214
/workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.2819262136
/workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.861628974
/workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.2077317214
/workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.4192793967
/workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.3898588176
/workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.6833458
/workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.1375539701
/workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.3076165839
/workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.4280801623
/workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.1118047898
/workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.3866978204
/workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.3341688839
/workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.1890092764
/workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.2350973370
/workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.779306428
/workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.2693133843
/workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.2177258776
/workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.2456546555
/workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.1580851738
/workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.3742193188
/workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.4241870912
/workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.2691540820
/workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.3455130245
/workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.549041544
/workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.1425521269
/workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.1536873093
/workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.321371725
/workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.1505960023
/workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.466583517
/workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.4204709731
/workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.2938175897
/workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.900494787
/workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.3135798698
/workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.4033299884
/workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.2859996409
/workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.337983579
/workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.80276812
/workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.1109004440
/workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.2253441633
/workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.3379677893
/workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.590532119
/workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.652362270
/workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.1434010973
/workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.860959793
/workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.146399796
/workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.3740834365
/workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.1613620530
/workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.1795371090
/workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.2386784828
/workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.2350245747
/workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.565012466
/workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.3914209571
/workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.2472906346
/workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.1753319636
/workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.2110232111
/workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.4083411241
/workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.974506698
/workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.3884422685
/workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.2266748816
/workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.2041288567
/workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.2028995270



Total test records in report: 200
tests.html | tests1.html | tests2.html | tests3.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.2386784828 Jul 31 04:56:45 PM PDT 24 Jul 31 04:56:53 PM PDT 24 1274810000 ps
T2 /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.80276812 Jul 31 04:56:44 PM PDT 24 Jul 31 04:56:55 PM PDT 24 1522810000 ps
T3 /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.860959793 Jul 31 04:56:42 PM PDT 24 Jul 31 04:56:53 PM PDT 24 1609250000 ps
T7 /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.2472906346 Jul 31 04:56:47 PM PDT 24 Jul 31 04:56:58 PM PDT 24 1430270000 ps
T8 /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.3914209571 Jul 31 04:56:47 PM PDT 24 Jul 31 04:56:58 PM PDT 24 1426130000 ps
T9 /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.2575383770 Jul 31 04:56:37 PM PDT 24 Jul 31 04:56:47 PM PDT 24 1413690000 ps
T10 /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.1580851738 Jul 31 04:56:41 PM PDT 24 Jul 31 04:56:53 PM PDT 24 1525150000 ps
T11 /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.2350973370 Jul 31 04:56:39 PM PDT 24 Jul 31 04:56:47 PM PDT 24 1464070000 ps
T12 /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.3742193188 Jul 31 04:56:41 PM PDT 24 Jul 31 04:56:53 PM PDT 24 1491270000 ps
T13 /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.2266748816 Jul 31 04:56:38 PM PDT 24 Jul 31 04:56:48 PM PDT 24 1411650000 ps
T31 /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.2253441633 Jul 31 04:56:47 PM PDT 24 Jul 31 04:56:56 PM PDT 24 1211450000 ps
T32 /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.2177258776 Jul 31 04:56:40 PM PDT 24 Jul 31 04:56:50 PM PDT 24 1604730000 ps
T33 /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.466583517 Jul 31 04:56:43 PM PDT 24 Jul 31 04:56:54 PM PDT 24 1539810000 ps
T34 /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.652362270 Jul 31 04:56:45 PM PDT 24 Jul 31 04:56:53 PM PDT 24 1362590000 ps
T35 /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.4033299884 Jul 31 04:56:50 PM PDT 24 Jul 31 04:56:58 PM PDT 24 1475950000 ps
T36 /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.2693133843 Jul 31 04:56:38 PM PDT 24 Jul 31 04:56:48 PM PDT 24 1503970000 ps
T37 /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.1613620530 Jul 31 04:56:47 PM PDT 24 Jul 31 04:56:55 PM PDT 24 1274530000 ps
T38 /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.779306428 Jul 31 04:56:37 PM PDT 24 Jul 31 04:56:46 PM PDT 24 1366110000 ps
T39 /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.2041288567 Jul 31 04:56:38 PM PDT 24 Jul 31 04:56:47 PM PDT 24 1560410000 ps
T40 /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.2859996409 Jul 31 04:56:38 PM PDT 24 Jul 31 04:56:47 PM PDT 24 1508570000 ps
T41 /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.1795371090 Jul 31 04:56:48 PM PDT 24 Jul 31 04:56:57 PM PDT 24 1577310000 ps
T42 /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.1425521269 Jul 31 04:56:38 PM PDT 24 Jul 31 04:56:49 PM PDT 24 1565990000 ps
T43 /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.1536873093 Jul 31 04:56:40 PM PDT 24 Jul 31 04:56:51 PM PDT 24 1601970000 ps
T44 /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.3740834365 Jul 31 04:56:39 PM PDT 24 Jul 31 04:56:46 PM PDT 24 1341730000 ps
T45 /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.3455130245 Jul 31 04:56:40 PM PDT 24 Jul 31 04:56:51 PM PDT 24 1601930000 ps
T46 /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.146399796 Jul 31 04:56:46 PM PDT 24 Jul 31 04:56:55 PM PDT 24 1404990000 ps
T47 /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.1109004440 Jul 31 04:56:44 PM PDT 24 Jul 31 04:56:53 PM PDT 24 1197850000 ps
T48 /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.1753319636 Jul 31 04:56:42 PM PDT 24 Jul 31 04:56:49 PM PDT 24 1318750000 ps
T49 /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.590532119 Jul 31 04:56:45 PM PDT 24 Jul 31 04:56:54 PM PDT 24 1295990000 ps
T50 /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.549041544 Jul 31 04:56:40 PM PDT 24 Jul 31 04:56:50 PM PDT 24 1209950000 ps
T51 /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.2691540820 Jul 31 04:56:41 PM PDT 24 Jul 31 04:56:51 PM PDT 24 1522110000 ps
T52 /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.3135798698 Jul 31 04:56:47 PM PDT 24 Jul 31 04:56:59 PM PDT 24 1467970000 ps
T53 /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.4083411241 Jul 31 04:56:46 PM PDT 24 Jul 31 04:56:54 PM PDT 24 1435630000 ps
T54 /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.2938175897 Jul 31 04:56:46 PM PDT 24 Jul 31 04:56:57 PM PDT 24 1628650000 ps
T55 /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.4241870912 Jul 31 04:56:42 PM PDT 24 Jul 31 04:56:53 PM PDT 24 1550050000 ps
T56 /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.1505960023 Jul 31 04:56:38 PM PDT 24 Jul 31 04:56:50 PM PDT 24 1506510000 ps
T57 /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.974506698 Jul 31 04:56:42 PM PDT 24 Jul 31 04:56:50 PM PDT 24 1324410000 ps
T58 /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.3379677893 Jul 31 04:56:44 PM PDT 24 Jul 31 04:56:55 PM PDT 24 1598490000 ps
T59 /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.900494787 Jul 31 04:57:25 PM PDT 24 Jul 31 04:57:35 PM PDT 24 1494170000 ps
T60 /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.2456546555 Jul 31 04:56:41 PM PDT 24 Jul 31 04:56:52 PM PDT 24 1436750000 ps
T61 /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.2028995270 Jul 31 04:56:38 PM PDT 24 Jul 31 04:56:49 PM PDT 24 1498210000 ps
T62 /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.1434010973 Jul 31 04:56:48 PM PDT 24 Jul 31 04:56:59 PM PDT 24 1556110000 ps
T63 /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.3884422685 Jul 31 04:56:36 PM PDT 24 Jul 31 04:56:47 PM PDT 24 1471370000 ps
T64 /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.4204709731 Jul 31 04:56:43 PM PDT 24 Jul 31 04:56:53 PM PDT 24 1580450000 ps
T65 /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.565012466 Jul 31 04:56:49 PM PDT 24 Jul 31 04:57:00 PM PDT 24 1466250000 ps
T66 /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.321371725 Jul 31 04:56:40 PM PDT 24 Jul 31 04:56:51 PM PDT 24 1422590000 ps
T67 /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.2350245747 Jul 31 04:56:46 PM PDT 24 Jul 31 04:56:57 PM PDT 24 1510990000 ps
T68 /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.1890092764 Jul 31 04:56:29 PM PDT 24 Jul 31 04:56:38 PM PDT 24 1469530000 ps
T69 /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.337983579 Jul 31 04:56:47 PM PDT 24 Jul 31 04:56:58 PM PDT 24 1479910000 ps
T70 /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.2110232111 Jul 31 04:56:45 PM PDT 24 Jul 31 04:56:55 PM PDT 24 1516750000 ps
T4 /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.3186987767 Jul 31 04:20:12 PM PDT 24 Jul 31 04:56:38 PM PDT 24 337069510000 ps
T5 /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.2346060328 Jul 31 04:18:57 PM PDT 24 Jul 31 05:01:22 PM PDT 24 336504150000 ps
T6 /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2863303776 Jul 31 04:18:56 PM PDT 24 Jul 31 05:04:04 PM PDT 24 337004930000 ps
T14 /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.2596394145 Jul 31 04:18:57 PM PDT 24 Jul 31 04:52:23 PM PDT 24 336659830000 ps
T15 /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.3274069357 Jul 31 04:18:58 PM PDT 24 Jul 31 04:54:30 PM PDT 24 336806270000 ps
T16 /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.2161168003 Jul 31 04:18:45 PM PDT 24 Jul 31 04:46:32 PM PDT 24 337020990000 ps
T17 /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.2045466730 Jul 31 04:18:58 PM PDT 24 Jul 31 04:52:54 PM PDT 24 336562250000 ps
T18 /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.2040941171 Jul 31 04:18:58 PM PDT 24 Jul 31 04:58:32 PM PDT 24 336604710000 ps
T19 /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.4053007528 Jul 31 04:20:12 PM PDT 24 Jul 31 04:56:25 PM PDT 24 336874930000 ps
T20 /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.2732821940 Jul 31 04:18:44 PM PDT 24 Jul 31 04:47:16 PM PDT 24 336867070000 ps
T71 /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.2050728357 Jul 31 04:18:58 PM PDT 24 Jul 31 04:49:51 PM PDT 24 336630210000 ps
T72 /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.924633235 Jul 31 04:18:43 PM PDT 24 Jul 31 04:46:46 PM PDT 24 336540630000 ps
T73 /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.1915807177 Jul 31 04:20:14 PM PDT 24 Jul 31 04:57:58 PM PDT 24 336418030000 ps
T74 /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.2836055894 Jul 31 04:18:59 PM PDT 24 Jul 31 04:54:03 PM PDT 24 336533550000 ps
T75 /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.1864003702 Jul 31 04:19:02 PM PDT 24 Jul 31 04:52:33 PM PDT 24 336794990000 ps
T76 /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.3153985319 Jul 31 04:18:56 PM PDT 24 Jul 31 05:04:07 PM PDT 24 337065670000 ps
T77 /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.109640880 Jul 31 04:20:00 PM PDT 24 Jul 31 04:54:28 PM PDT 24 336426770000 ps
T78 /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.1444348689 Jul 31 04:18:54 PM PDT 24 Jul 31 05:04:08 PM PDT 24 336691830000 ps
T79 /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.3599136519 Jul 31 04:18:55 PM PDT 24 Jul 31 05:03:48 PM PDT 24 336969930000 ps
T80 /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.335691447 Jul 31 04:18:57 PM PDT 24 Jul 31 04:56:47 PM PDT 24 336387090000 ps
T81 /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.1280055582 Jul 31 04:18:45 PM PDT 24 Jul 31 04:47:03 PM PDT 24 336849570000 ps
T82 /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.1775947976 Jul 31 04:18:44 PM PDT 24 Jul 31 04:49:31 PM PDT 24 336402110000 ps
T83 /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.3657455601 Jul 31 04:20:00 PM PDT 24 Jul 31 04:55:22 PM PDT 24 337058270000 ps
T84 /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.93529328 Jul 31 04:18:57 PM PDT 24 Jul 31 04:56:45 PM PDT 24 336450730000 ps
T85 /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.3031480033 Jul 31 04:18:57 PM PDT 24 Jul 31 04:54:51 PM PDT 24 336849150000 ps
T86 /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.106050841 Jul 31 04:18:44 PM PDT 24 Jul 31 04:43:22 PM PDT 24 336841010000 ps
T87 /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.2651175222 Jul 31 04:18:57 PM PDT 24 Jul 31 04:56:26 PM PDT 24 336548890000 ps
T88 /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.1066078171 Jul 31 04:18:51 PM PDT 24 Jul 31 04:52:04 PM PDT 24 336873030000 ps
T89 /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.1796740057 Jul 31 04:18:55 PM PDT 24 Jul 31 05:04:09 PM PDT 24 336483330000 ps
T90 /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.2044868953 Jul 31 04:19:02 PM PDT 24 Jul 31 04:52:33 PM PDT 24 336559350000 ps
T91 /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.1098349179 Jul 31 04:20:00 PM PDT 24 Jul 31 04:55:17 PM PDT 24 337022410000 ps
T92 /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.1047060924 Jul 31 04:18:57 PM PDT 24 Jul 31 05:01:23 PM PDT 24 336322330000 ps
T93 /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.610096433 Jul 31 04:18:44 PM PDT 24 Jul 31 04:49:08 PM PDT 24 336810790000 ps
T94 /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.1109514506 Jul 31 04:18:57 PM PDT 24 Jul 31 05:01:27 PM PDT 24 336761230000 ps
T95 /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.2190997680 Jul 31 04:18:57 PM PDT 24 Jul 31 05:01:32 PM PDT 24 337030790000 ps
T96 /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.983762194 Jul 31 04:19:02 PM PDT 24 Jul 31 04:52:27 PM PDT 24 336592150000 ps
T97 /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.3820437903 Jul 31 04:18:58 PM PDT 24 Jul 31 04:54:21 PM PDT 24 336377770000 ps
T98 /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.3467973681 Jul 31 04:18:58 PM PDT 24 Jul 31 04:56:26 PM PDT 24 336973890000 ps
T99 /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.635062724 Jul 31 04:18:57 PM PDT 24 Jul 31 04:56:33 PM PDT 24 336753610000 ps
T100 /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.3172421212 Jul 31 04:20:13 PM PDT 24 Jul 31 04:58:12 PM PDT 24 337146310000 ps
T101 /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.1204154486 Jul 31 04:18:55 PM PDT 24 Jul 31 05:04:01 PM PDT 24 336938450000 ps
T102 /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.1450763162 Jul 31 04:18:58 PM PDT 24 Jul 31 04:51:50 PM PDT 24 336556630000 ps
T103 /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1085720690 Jul 31 04:18:51 PM PDT 24 Jul 31 04:52:03 PM PDT 24 336490630000 ps
T104 /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.696509951 Jul 31 04:20:14 PM PDT 24 Jul 31 04:57:37 PM PDT 24 337070570000 ps
T105 /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.1401405472 Jul 31 04:18:51 PM PDT 24 Jul 31 04:48:05 PM PDT 24 336834810000 ps
T106 /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.3503274671 Jul 31 04:20:00 PM PDT 24 Jul 31 04:55:20 PM PDT 24 336793090000 ps
T107 /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.2721483807 Jul 31 04:18:58 PM PDT 24 Jul 31 04:59:27 PM PDT 24 336330150000 ps
T108 /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.3137418592 Jul 31 04:19:02 PM PDT 24 Jul 31 04:52:39 PM PDT 24 336956190000 ps
T109 /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.1056053301 Jul 31 04:20:00 PM PDT 24 Jul 31 04:55:25 PM PDT 24 336713810000 ps
T110 /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.3492904491 Jul 31 04:18:45 PM PDT 24 Jul 31 04:47:02 PM PDT 24 336501390000 ps
T111 /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.2552265394 Jul 31 04:24:17 PM PDT 24 Jul 31 04:24:30 PM PDT 24 1537810000 ps
T112 /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.2813259936 Jul 31 04:21:28 PM PDT 24 Jul 31 04:21:38 PM PDT 24 1610130000 ps
T113 /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.3306906189 Jul 31 04:20:39 PM PDT 24 Jul 31 04:20:48 PM PDT 24 1532870000 ps
T114 /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.3145156749 Jul 31 04:24:54 PM PDT 24 Jul 31 04:25:02 PM PDT 24 1550030000 ps
T115 /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.1118047898 Jul 31 04:25:22 PM PDT 24 Jul 31 04:25:30 PM PDT 24 1513230000 ps
T116 /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.1161126223 Jul 31 04:24:56 PM PDT 24 Jul 31 04:25:03 PM PDT 24 1241390000 ps
T117 /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.1359960876 Jul 31 04:25:00 PM PDT 24 Jul 31 04:25:08 PM PDT 24 1435550000 ps
T118 /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.281684626 Jul 31 04:22:27 PM PDT 24 Jul 31 04:22:37 PM PDT 24 1461370000 ps
T119 /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.3781993059 Jul 31 04:24:46 PM PDT 24 Jul 31 04:24:54 PM PDT 24 1539610000 ps
T120 /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.3341688839 Jul 31 04:20:58 PM PDT 24 Jul 31 04:21:05 PM PDT 24 1363190000 ps
T121 /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.771553033 Jul 31 04:22:44 PM PDT 24 Jul 31 04:22:53 PM PDT 24 1276470000 ps
T122 /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.3898588176 Jul 31 04:36:23 PM PDT 24 Jul 31 04:36:37 PM PDT 24 1512330000 ps
T123 /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.1254575249 Jul 31 04:24:59 PM PDT 24 Jul 31 04:25:09 PM PDT 24 1496590000 ps
T124 /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.4192793967 Jul 31 04:36:25 PM PDT 24 Jul 31 04:36:35 PM PDT 24 1497910000 ps
T125 /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.1093612278 Jul 31 04:22:43 PM PDT 24 Jul 31 04:22:52 PM PDT 24 1311490000 ps
T126 /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.6833458 Jul 31 04:36:22 PM PDT 24 Jul 31 04:36:30 PM PDT 24 1492330000 ps
T127 /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.2832748230 Jul 31 04:24:44 PM PDT 24 Jul 31 04:24:52 PM PDT 24 1520130000 ps
T128 /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1893779650 Jul 31 04:23:23 PM PDT 24 Jul 31 04:23:33 PM PDT 24 1457070000 ps
T129 /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.2819262136 Jul 31 04:36:23 PM PDT 24 Jul 31 04:36:36 PM PDT 24 1457830000 ps
T130 /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.1848751241 Jul 31 04:22:49 PM PDT 24 Jul 31 04:23:00 PM PDT 24 1592290000 ps
T131 /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.484616409 Jul 31 04:24:56 PM PDT 24 Jul 31 04:25:06 PM PDT 24 1580990000 ps
T132 /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.4280801623 Jul 31 04:20:55 PM PDT 24 Jul 31 04:21:08 PM PDT 24 1529130000 ps
T133 /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.4243145348 Jul 31 04:22:43 PM PDT 24 Jul 31 04:22:54 PM PDT 24 1586770000 ps
T134 /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.3884983011 Jul 31 04:22:49 PM PDT 24 Jul 31 04:22:58 PM PDT 24 1220830000 ps
T135 /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.665939097 Jul 31 04:25:06 PM PDT 24 Jul 31 04:25:15 PM PDT 24 1550590000 ps
T136 /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.180926896 Jul 31 04:24:59 PM PDT 24 Jul 31 04:25:08 PM PDT 24 1362490000 ps
T137 /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.3076165839 Jul 31 04:22:49 PM PDT 24 Jul 31 04:23:00 PM PDT 24 1272410000 ps
T138 /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2279451872 Jul 31 04:22:49 PM PDT 24 Jul 31 04:23:02 PM PDT 24 1537570000 ps
T139 /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.3047204214 Jul 31 04:36:23 PM PDT 24 Jul 31 04:36:36 PM PDT 24 1329670000 ps
T140 /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.1566479741 Jul 31 04:36:17 PM PDT 24 Jul 31 04:36:24 PM PDT 24 1463650000 ps
T141 /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.1573309363 Jul 31 04:25:01 PM PDT 24 Jul 31 04:25:08 PM PDT 24 1203210000 ps
T142 /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.2177516366 Jul 31 04:24:52 PM PDT 24 Jul 31 04:25:01 PM PDT 24 1574050000 ps
T143 /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.2145784916 Jul 31 04:24:59 PM PDT 24 Jul 31 04:25:07 PM PDT 24 1346530000 ps
T144 /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.740779146 Jul 31 04:25:42 PM PDT 24 Jul 31 04:25:50 PM PDT 24 1434510000 ps
T145 /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.3866978204 Jul 31 04:23:17 PM PDT 24 Jul 31 04:23:28 PM PDT 24 1512690000 ps
T146 /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.2077317214 Jul 31 04:36:26 PM PDT 24 Jul 31 04:36:38 PM PDT 24 1540350000 ps
T147 /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.1694220850 Jul 31 04:24:59 PM PDT 24 Jul 31 04:25:07 PM PDT 24 1457610000 ps
T148 /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.2000642294 Jul 31 04:20:42 PM PDT 24 Jul 31 04:20:53 PM PDT 24 1495690000 ps
T149 /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.3671158082 Jul 31 04:25:37 PM PDT 24 Jul 31 04:25:47 PM PDT 24 1247070000 ps
T150 /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.1375539701 Jul 31 04:36:26 PM PDT 24 Jul 31 04:36:35 PM PDT 24 1398910000 ps
T151 /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.1769328588 Jul 31 04:20:58 PM PDT 24 Jul 31 04:21:06 PM PDT 24 1501230000 ps
T152 /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.1712105318 Jul 31 04:23:24 PM PDT 24 Jul 31 04:23:38 PM PDT 24 1447470000 ps
T153 /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.3561697643 Jul 31 04:24:38 PM PDT 24 Jul 31 04:24:45 PM PDT 24 1239750000 ps
T154 /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.996257020 Jul 31 04:23:26 PM PDT 24 Jul 31 04:23:38 PM PDT 24 1605450000 ps
T155 /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.1034217025 Jul 31 04:22:39 PM PDT 24 Jul 31 04:22:51 PM PDT 24 1620470000 ps
T156 /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.4025336791 Jul 31 04:23:17 PM PDT 24 Jul 31 04:23:29 PM PDT 24 1548150000 ps
T157 /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.861628974 Jul 31 04:36:23 PM PDT 24 Jul 31 04:36:29 PM PDT 24 957270000 ps
T158 /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.3267141819 Jul 31 04:20:53 PM PDT 24 Jul 31 04:21:01 PM PDT 24 1575570000 ps
T159 /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.3824820213 Jul 31 04:25:48 PM PDT 24 Jul 31 04:25:56 PM PDT 24 1559210000 ps
T160 /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.3883466445 Jul 31 04:24:51 PM PDT 24 Jul 31 04:24:59 PM PDT 24 1517510000 ps
T21 /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.1555052578 Jul 31 04:38:55 PM PDT 24 Jul 31 05:05:32 PM PDT 24 336780890000 ps
T22 /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.3260423555 Jul 31 04:38:55 PM PDT 24 Jul 31 05:07:57 PM PDT 24 336368750000 ps
T23 /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.3017490926 Jul 31 04:38:50 PM PDT 24 Jul 31 05:06:01 PM PDT 24 336448670000 ps
T24 /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.2089365658 Jul 31 04:39:00 PM PDT 24 Jul 31 05:07:25 PM PDT 24 336450810000 ps
T25 /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.1652300617 Jul 31 04:39:01 PM PDT 24 Jul 31 05:18:35 PM PDT 24 336469230000 ps
T26 /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.1281586925 Jul 31 04:38:56 PM PDT 24 Jul 31 05:09:34 PM PDT 24 336700370000 ps
T27 /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.2336792305 Jul 31 04:39:11 PM PDT 24 Jul 31 05:06:14 PM PDT 24 336294710000 ps
T28 /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.590511996 Jul 31 04:38:54 PM PDT 24 Jul 31 05:11:49 PM PDT 24 336972930000 ps
T29 /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.3783603768 Jul 31 04:38:59 PM PDT 24 Jul 31 05:06:21 PM PDT 24 336859110000 ps
T30 /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.153315925 Jul 31 04:40:10 PM PDT 24 Jul 31 05:12:35 PM PDT 24 337050850000 ps
T161 /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.2938087628 Jul 31 04:39:05 PM PDT 24 Jul 31 05:04:45 PM PDT 24 336843510000 ps
T162 /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.1353824558 Jul 31 04:38:58 PM PDT 24 Jul 31 05:03:36 PM PDT 24 336290550000 ps
T163 /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.171559880 Jul 31 04:38:52 PM PDT 24 Jul 31 05:08:03 PM PDT 24 336480330000 ps
T164 /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.4194959800 Jul 31 04:39:02 PM PDT 24 Jul 31 05:09:06 PM PDT 24 336744650000 ps
T165 /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.1715790233 Jul 31 04:38:48 PM PDT 24 Jul 31 05:11:35 PM PDT 24 337133390000 ps
T166 /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.3038868280 Jul 31 04:38:58 PM PDT 24 Jul 31 05:14:47 PM PDT 24 336414190000 ps
T167 /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.3786428051 Jul 31 04:38:56 PM PDT 24 Jul 31 05:06:13 PM PDT 24 337012930000 ps
T168 /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.15362083 Jul 31 04:38:55 PM PDT 24 Jul 31 05:07:03 PM PDT 24 336744010000 ps
T169 /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.1087463369 Jul 31 04:38:56 PM PDT 24 Jul 31 05:02:26 PM PDT 24 336627230000 ps
T170 /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.91522846 Jul 31 04:38:57 PM PDT 24 Jul 31 05:11:33 PM PDT 24 336986490000 ps
T171 /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.1985051813 Jul 31 04:39:07 PM PDT 24 Jul 31 05:06:04 PM PDT 24 336785010000 ps
T172 /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.4259878666 Jul 31 04:38:56 PM PDT 24 Jul 31 05:09:09 PM PDT 24 336439230000 ps
T173 /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.1264344396 Jul 31 04:39:01 PM PDT 24 Jul 31 05:08:28 PM PDT 24 337015770000 ps
T174 /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.2489861980 Jul 31 04:38:57 PM PDT 24 Jul 31 05:06:05 PM PDT 24 336642370000 ps
T175 /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.386309933 Jul 31 04:39:00 PM PDT 24 Jul 31 05:14:45 PM PDT 24 336347210000 ps
T176 /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.576395431 Jul 31 04:38:58 PM PDT 24 Jul 31 05:11:47 PM PDT 24 336985250000 ps
T177 /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.2820990643 Jul 31 04:38:50 PM PDT 24 Jul 31 05:05:06 PM PDT 24 336864750000 ps
T178 /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.2069486591 Jul 31 04:38:58 PM PDT 24 Jul 31 05:04:35 PM PDT 24 336742830000 ps
T179 /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.2586837883 Jul 31 04:38:57 PM PDT 24 Jul 31 05:08:28 PM PDT 24 337001230000 ps
T180 /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.4120553612 Jul 31 04:39:53 PM PDT 24 Jul 31 05:10:48 PM PDT 24 336607550000 ps
T181 /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.1962602216 Jul 31 04:38:54 PM PDT 24 Jul 31 05:04:47 PM PDT 24 337048130000 ps
T182 /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.3769704031 Jul 31 04:39:10 PM PDT 24 Jul 31 05:05:45 PM PDT 24 336416050000 ps
T183 /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.2762938974 Jul 31 04:39:01 PM PDT 24 Jul 31 05:10:04 PM PDT 24 336515050000 ps
T184 /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.153464569 Jul 31 04:38:57 PM PDT 24 Jul 31 05:05:16 PM PDT 24 336702550000 ps
T185 /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.3274626964 Jul 31 04:38:57 PM PDT 24 Jul 31 05:00:56 PM PDT 24 336749790000 ps
T186 /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.2972990108 Jul 31 04:39:53 PM PDT 24 Jul 31 05:11:09 PM PDT 24 336588670000 ps
T187 /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.2462416561 Jul 31 04:39:53 PM PDT 24 Jul 31 05:11:00 PM PDT 24 336715750000 ps
T188 /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.2023141874 Jul 31 04:38:57 PM PDT 24 Jul 31 05:11:30 PM PDT 24 337103610000 ps
T189 /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.231645110 Jul 31 04:38:57 PM PDT 24 Jul 31 05:06:34 PM PDT 24 336760450000 ps
T190 /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.1418359099 Jul 31 04:39:01 PM PDT 24 Jul 31 05:07:30 PM PDT 24 336323290000 ps
T191 /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.2640384675 Jul 31 04:38:54 PM PDT 24 Jul 31 05:14:37 PM PDT 24 336934270000 ps
T192 /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.2482267014 Jul 31 04:38:55 PM PDT 24 Jul 31 05:06:45 PM PDT 24 336660970000 ps
T193 /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.1312808485 Jul 31 04:38:55 PM PDT 24 Jul 31 05:09:09 PM PDT 24 336404990000 ps
T194 /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.651670855 Jul 31 04:39:01 PM PDT 24 Jul 31 05:03:04 PM PDT 24 337128890000 ps
T195 /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.1604787432 Jul 31 04:38:50 PM PDT 24 Jul 31 05:05:52 PM PDT 24 337019850000 ps
T196 /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.300480712 Jul 31 04:39:07 PM PDT 24 Jul 31 05:08:32 PM PDT 24 336426090000 ps
T197 /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.2191929405 Jul 31 04:39:07 PM PDT 24 Jul 31 05:10:00 PM PDT 24 336661830000 ps
T198 /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.3029617658 Jul 31 04:38:55 PM PDT 24 Jul 31 05:07:56 PM PDT 24 336769330000 ps
T199 /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.804936065 Jul 31 04:38:54 PM PDT 24 Jul 31 05:14:31 PM PDT 24 336949590000 ps
T200 /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.1538262510 Jul 31 04:38:53 PM PDT 24 Jul 31 05:11:58 PM PDT 24 336870450000 ps

Test location /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.2575383770
Short name T9
Test name
Test status
Simulation time 1413690000 ps
CPU time 4.21 seconds
Started Jul 31 04:56:37 PM PDT 24
Finished Jul 31 04:56:47 PM PDT 24
Peak memory 164796 kb
Host smart-a877d969-75f2-42a3-a069-25c51c91a74c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2575383770 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.2575383770
Directory /workspace/13.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2863303776
Short name T6
Test name
Test status
Simulation time 337004930000 ps
CPU time 1025.87 seconds
Started Jul 31 04:18:56 PM PDT 24
Finished Jul 31 05:04:04 PM PDT 24
Peak memory 160872 kb
Host smart-f695b8d7-c9e9-4a09-8b1a-f5d343887bc4
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2863303776 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.2863303776
Directory /workspace/19.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.3260423555
Short name T22
Test name
Test status
Simulation time 336368750000 ps
CPU time 706.51 seconds
Started Jul 31 04:38:55 PM PDT 24
Finished Jul 31 05:07:57 PM PDT 24
Peak memory 160668 kb
Host smart-bd50ff8f-7367-4211-8f19-b0e9e42c4e92
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3260423555 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.3260423555
Directory /workspace/12.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.924633235
Short name T72
Test name
Test status
Simulation time 336540630000 ps
CPU time 664.06 seconds
Started Jul 31 04:18:43 PM PDT 24
Finished Jul 31 04:46:46 PM PDT 24
Peak memory 159752 kb
Host smart-3aecaebe-df00-458f-897e-0696e9df812b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=924633235 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.924633235
Directory /workspace/0.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.1401405472
Short name T105
Test name
Test status
Simulation time 336834810000 ps
CPU time 719.71 seconds
Started Jul 31 04:18:51 PM PDT 24
Finished Jul 31 04:48:05 PM PDT 24
Peak memory 159756 kb
Host smart-bb26c784-308e-47c3-b915-5997f0a811a4
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1401405472 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.1401405472
Directory /workspace/1.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.1444348689
Short name T78
Test name
Test status
Simulation time 336691830000 ps
CPU time 1037.19 seconds
Started Jul 31 04:18:54 PM PDT 24
Finished Jul 31 05:04:08 PM PDT 24
Peak memory 160880 kb
Host smart-c60bbde2-9a2c-4147-8ed8-bd097440ffd4
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1444348689 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.1444348689
Directory /workspace/10.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.1109514506
Short name T94
Test name
Test status
Simulation time 336761230000 ps
CPU time 1043.35 seconds
Started Jul 31 04:18:57 PM PDT 24
Finished Jul 31 05:01:27 PM PDT 24
Peak memory 158764 kb
Host smart-c2f019b6-8151-42a1-86ce-7b6f102a7915
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1109514506 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.1109514506
Directory /workspace/11.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.983762194
Short name T96
Test name
Test status
Simulation time 336592150000 ps
CPU time 795.52 seconds
Started Jul 31 04:19:02 PM PDT 24
Finished Jul 31 04:52:27 PM PDT 24
Peak memory 159184 kb
Host smart-8fa70b89-b917-4897-b3c5-c1a154d3c518
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=983762194 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.983762194
Directory /workspace/12.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.1796740057
Short name T89
Test name
Test status
Simulation time 336483330000 ps
CPU time 1040.36 seconds
Started Jul 31 04:18:55 PM PDT 24
Finished Jul 31 05:04:09 PM PDT 24
Peak memory 160872 kb
Host smart-059abfdb-bdef-4050-8b13-30c215f8c828
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1796740057 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.1796740057
Directory /workspace/13.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.3137418592
Short name T108
Test name
Test status
Simulation time 336956190000 ps
CPU time 802.11 seconds
Started Jul 31 04:19:02 PM PDT 24
Finished Jul 31 04:52:39 PM PDT 24
Peak memory 159004 kb
Host smart-fcf241a5-b6ca-436c-98fc-7ad8f2a63e8b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3137418592 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.3137418592
Directory /workspace/14.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.1204154486
Short name T101
Test name
Test status
Simulation time 336938450000 ps
CPU time 1020.17 seconds
Started Jul 31 04:18:55 PM PDT 24
Finished Jul 31 05:04:01 PM PDT 24
Peak memory 160872 kb
Host smart-86035e30-bbc5-4f9e-9140-6251dfd0aad3
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1204154486 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.1204154486
Directory /workspace/15.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.93529328
Short name T84
Test name
Test status
Simulation time 336450730000 ps
CPU time 899.91 seconds
Started Jul 31 04:18:57 PM PDT 24
Finished Jul 31 04:56:45 PM PDT 24
Peak memory 158808 kb
Host smart-55de1652-9a2e-47b8-b78e-0ca77bc0581b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=93529328 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.93529328
Directory /workspace/16.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.106050841
Short name T86
Test name
Test status
Simulation time 336841010000 ps
CPU time 572.4 seconds
Started Jul 31 04:18:44 PM PDT 24
Finished Jul 31 04:43:22 PM PDT 24
Peak memory 160440 kb
Host smart-1aecda68-1635-4b6b-b15c-35638663e943
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=106050841 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.106050841
Directory /workspace/17.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.3153985319
Short name T76
Test name
Test status
Simulation time 337065670000 ps
CPU time 1035.54 seconds
Started Jul 31 04:18:56 PM PDT 24
Finished Jul 31 05:04:07 PM PDT 24
Peak memory 160872 kb
Host smart-3c716376-1092-4a71-b9cd-219d7df281fd
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3153985319 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.3153985319
Directory /workspace/18.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.2732821940
Short name T20
Test name
Test status
Simulation time 336867070000 ps
CPU time 693.96 seconds
Started Jul 31 04:18:44 PM PDT 24
Finished Jul 31 04:47:16 PM PDT 24
Peak memory 160212 kb
Host smart-63be3761-3b63-4dbc-8fa7-2b97c9b82795
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2732821940 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.2732821940
Directory /workspace/2.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.3467973681
Short name T98
Test name
Test status
Simulation time 336973890000 ps
CPU time 904.47 seconds
Started Jul 31 04:18:58 PM PDT 24
Finished Jul 31 04:56:26 PM PDT 24
Peak memory 160228 kb
Host smart-0258bd3f-a148-406c-b96e-d98382b3676e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3467973681 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.3467973681
Directory /workspace/20.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.335691447
Short name T80
Test name
Test status
Simulation time 336387090000 ps
CPU time 904.75 seconds
Started Jul 31 04:18:57 PM PDT 24
Finished Jul 31 04:56:47 PM PDT 24
Peak memory 158896 kb
Host smart-96462dfa-c7dc-4099-b02e-7ab667817cd7
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=335691447 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.335691447
Directory /workspace/21.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.3599136519
Short name T79
Test name
Test status
Simulation time 336969930000 ps
CPU time 1041.49 seconds
Started Jul 31 04:18:55 PM PDT 24
Finished Jul 31 05:03:48 PM PDT 24
Peak memory 160872 kb
Host smart-c7294dfe-6b55-4a3d-a2f5-2c59d35b68f9
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3599136519 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.3599136519
Directory /workspace/22.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.2190997680
Short name T95
Test name
Test status
Simulation time 337030790000 ps
CPU time 1040 seconds
Started Jul 31 04:18:57 PM PDT 24
Finished Jul 31 05:01:32 PM PDT 24
Peak memory 158860 kb
Host smart-b4e158ec-8c8f-4d18-86ee-9a086ec87b1e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2190997680 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.2190997680
Directory /workspace/23.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.2044868953
Short name T90
Test name
Test status
Simulation time 336559350000 ps
CPU time 797.3 seconds
Started Jul 31 04:19:02 PM PDT 24
Finished Jul 31 04:52:33 PM PDT 24
Peak memory 159080 kb
Host smart-eb65db9e-50e9-4ea3-97e7-4583db946966
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2044868953 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.2044868953
Directory /workspace/24.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.635062724
Short name T99
Test name
Test status
Simulation time 336753610000 ps
CPU time 886.21 seconds
Started Jul 31 04:18:57 PM PDT 24
Finished Jul 31 04:56:33 PM PDT 24
Peak memory 158832 kb
Host smart-54aea6ce-59cb-4c97-b42e-c0b801902e0b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=635062724 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.635062724
Directory /workspace/25.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.3172421212
Short name T100
Test name
Test status
Simulation time 337146310000 ps
CPU time 953.09 seconds
Started Jul 31 04:20:13 PM PDT 24
Finished Jul 31 04:58:12 PM PDT 24
Peak memory 160228 kb
Host smart-f1f778f9-2206-41af-9aa3-750d5f5b002e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3172421212 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.3172421212
Directory /workspace/26.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.2040941171
Short name T18
Test name
Test status
Simulation time 336604710000 ps
CPU time 965.61 seconds
Started Jul 31 04:18:58 PM PDT 24
Finished Jul 31 04:58:32 PM PDT 24
Peak memory 160228 kb
Host smart-18c7d6cb-54a9-4e7b-960d-245da3c3263b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2040941171 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.2040941171
Directory /workspace/27.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.696509951
Short name T104
Test name
Test status
Simulation time 337070570000 ps
CPU time 925.67 seconds
Started Jul 31 04:20:14 PM PDT 24
Finished Jul 31 04:57:37 PM PDT 24
Peak memory 160204 kb
Host smart-2ce12288-08e7-4ce7-b2e3-ff89d938a2e2
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=696509951 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.696509951
Directory /workspace/28.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.1915807177
Short name T73
Test name
Test status
Simulation time 336418030000 ps
CPU time 942.24 seconds
Started Jul 31 04:20:14 PM PDT 24
Finished Jul 31 04:57:58 PM PDT 24
Peak memory 160228 kb
Host smart-e96f5e4d-f8c5-4395-9a85-09cb5f5ba4eb
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1915807177 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.1915807177
Directory /workspace/29.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.1775947976
Short name T82
Test name
Test status
Simulation time 336402110000 ps
CPU time 756.37 seconds
Started Jul 31 04:18:44 PM PDT 24
Finished Jul 31 04:49:31 PM PDT 24
Peak memory 159036 kb
Host smart-d1b4a36f-5266-4c85-b3e0-e68ffd768451
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1775947976 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.1775947976
Directory /workspace/3.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.2346060328
Short name T5
Test name
Test status
Simulation time 336504150000 ps
CPU time 1039.78 seconds
Started Jul 31 04:18:57 PM PDT 24
Finished Jul 31 05:01:22 PM PDT 24
Peak memory 158648 kb
Host smart-43396de5-1368-45bc-a6a5-12310ec6dbc3
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2346060328 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.2346060328
Directory /workspace/30.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.1047060924
Short name T92
Test name
Test status
Simulation time 336322330000 ps
CPU time 1040.03 seconds
Started Jul 31 04:18:57 PM PDT 24
Finished Jul 31 05:01:23 PM PDT 24
Peak memory 158748 kb
Host smart-04cabf74-09ef-4816-a18b-8f0ac48f5146
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1047060924 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.1047060924
Directory /workspace/31.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.2721483807
Short name T107
Test name
Test status
Simulation time 336330150000 ps
CPU time 983.52 seconds
Started Jul 31 04:18:58 PM PDT 24
Finished Jul 31 04:59:27 PM PDT 24
Peak memory 160228 kb
Host smart-9a4bcbbd-bd8f-4416-b212-4e3cf59e506e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2721483807 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.2721483807
Directory /workspace/32.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.2651175222
Short name T87
Test name
Test status
Simulation time 336548890000 ps
CPU time 905.02 seconds
Started Jul 31 04:18:57 PM PDT 24
Finished Jul 31 04:56:26 PM PDT 24
Peak memory 159876 kb
Host smart-1c4c1cce-4fc1-4f30-883b-1d2db2f16e73
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2651175222 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.2651175222
Directory /workspace/33.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.1864003702
Short name T75
Test name
Test status
Simulation time 336794990000 ps
CPU time 799.1 seconds
Started Jul 31 04:19:02 PM PDT 24
Finished Jul 31 04:52:33 PM PDT 24
Peak memory 159080 kb
Host smart-fc57abbe-77fd-4bec-900e-394accab2159
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1864003702 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.1864003702
Directory /workspace/34.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.109640880
Short name T77
Test name
Test status
Simulation time 336426770000 ps
CPU time 830.33 seconds
Started Jul 31 04:20:00 PM PDT 24
Finished Jul 31 04:54:28 PM PDT 24
Peak memory 160112 kb
Host smart-7f93221b-6870-4b02-ac8b-9581cf9d2b1d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=109640880 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.109640880
Directory /workspace/35.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.3657455601
Short name T83
Test name
Test status
Simulation time 337058270000 ps
CPU time 858.67 seconds
Started Jul 31 04:20:00 PM PDT 24
Finished Jul 31 04:55:22 PM PDT 24
Peak memory 160136 kb
Host smart-4b77a16b-c2a0-4bd6-afd8-2842ffe44b37
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3657455601 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.3657455601
Directory /workspace/36.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.3820437903
Short name T97
Test name
Test status
Simulation time 336377770000 ps
CPU time 881.14 seconds
Started Jul 31 04:18:58 PM PDT 24
Finished Jul 31 04:54:21 PM PDT 24
Peak memory 160240 kb
Host smart-e9e6b110-91cf-4900-b6ab-2adb6767abaf
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3820437903 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.3820437903
Directory /workspace/37.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.1450763162
Short name T102
Test name
Test status
Simulation time 336556630000 ps
CPU time 811.81 seconds
Started Jul 31 04:18:58 PM PDT 24
Finished Jul 31 04:51:50 PM PDT 24
Peak memory 160228 kb
Host smart-9638b7f8-57ee-4f2d-8efb-1eb7f573e1fb
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1450763162 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.1450763162
Directory /workspace/38.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.2045466730
Short name T17
Test name
Test status
Simulation time 336562250000 ps
CPU time 834.49 seconds
Started Jul 31 04:18:58 PM PDT 24
Finished Jul 31 04:52:54 PM PDT 24
Peak memory 160232 kb
Host smart-3f91eca8-e307-4703-838c-d53389d54188
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2045466730 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.2045466730
Directory /workspace/39.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.3492904491
Short name T110
Test name
Test status
Simulation time 336501390000 ps
CPU time 670.73 seconds
Started Jul 31 04:18:45 PM PDT 24
Finished Jul 31 04:47:02 PM PDT 24
Peak memory 160220 kb
Host smart-e096c6e5-df48-4f1e-8f9c-5accf53db5c7
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3492904491 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.3492904491
Directory /workspace/4.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.2836055894
Short name T74
Test name
Test status
Simulation time 336533550000 ps
CPU time 863.61 seconds
Started Jul 31 04:18:59 PM PDT 24
Finished Jul 31 04:54:03 PM PDT 24
Peak memory 160240 kb
Host smart-6e6eb55f-fda1-47cc-94fa-5c6804b7270b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2836055894 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.2836055894
Directory /workspace/40.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.1098349179
Short name T91
Test name
Test status
Simulation time 337022410000 ps
CPU time 854.67 seconds
Started Jul 31 04:20:00 PM PDT 24
Finished Jul 31 04:55:17 PM PDT 24
Peak memory 159376 kb
Host smart-cd8fd129-f8bf-424f-82c5-a6d7d0ca8197
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1098349179 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.1098349179
Directory /workspace/41.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.3031480033
Short name T85
Test name
Test status
Simulation time 336849150000 ps
CPU time 898.4 seconds
Started Jul 31 04:18:57 PM PDT 24
Finished Jul 31 04:54:51 PM PDT 24
Peak memory 159452 kb
Host smart-1920c637-b80a-4492-9cde-e9189be5e023
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3031480033 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.3031480033
Directory /workspace/42.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.3503274671
Short name T106
Test name
Test status
Simulation time 336793090000 ps
CPU time 860.95 seconds
Started Jul 31 04:20:00 PM PDT 24
Finished Jul 31 04:55:20 PM PDT 24
Peak memory 160180 kb
Host smart-665dc6a6-4b4f-467c-a518-90efcbcd1575
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3503274671 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.3503274671
Directory /workspace/43.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.1056053301
Short name T109
Test name
Test status
Simulation time 336713810000 ps
CPU time 855.04 seconds
Started Jul 31 04:20:00 PM PDT 24
Finished Jul 31 04:55:25 PM PDT 24
Peak memory 159396 kb
Host smart-0e8eff60-6cd1-4347-811c-29d3924807e2
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1056053301 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.1056053301
Directory /workspace/44.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.2596394145
Short name T14
Test name
Test status
Simulation time 336659830000 ps
CPU time 821.54 seconds
Started Jul 31 04:18:57 PM PDT 24
Finished Jul 31 04:52:23 PM PDT 24
Peak memory 159580 kb
Host smart-be1ae76d-6de0-4567-b856-765a966f315a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2596394145 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.2596394145
Directory /workspace/45.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.2050728357
Short name T71
Test name
Test status
Simulation time 336630210000 ps
CPU time 760.57 seconds
Started Jul 31 04:18:58 PM PDT 24
Finished Jul 31 04:49:51 PM PDT 24
Peak memory 160232 kb
Host smart-c8108246-16e0-41b2-b53b-73fb4def9794
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2050728357 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.2050728357
Directory /workspace/46.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.3274069357
Short name T15
Test name
Test status
Simulation time 336806270000 ps
CPU time 885.19 seconds
Started Jul 31 04:18:58 PM PDT 24
Finished Jul 31 04:54:30 PM PDT 24
Peak memory 160228 kb
Host smart-7d3b690a-0c3d-43bd-b32a-ac1bc211c86e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3274069357 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.3274069357
Directory /workspace/47.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.4053007528
Short name T19
Test name
Test status
Simulation time 336874930000 ps
CPU time 891.56 seconds
Started Jul 31 04:20:12 PM PDT 24
Finished Jul 31 04:56:25 PM PDT 24
Peak memory 159372 kb
Host smart-3a65beca-e8c2-4d56-8e8b-735c28ececee
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4053007528 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.4053007528
Directory /workspace/48.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.3186987767
Short name T4
Test name
Test status
Simulation time 337069510000 ps
CPU time 896.98 seconds
Started Jul 31 04:20:12 PM PDT 24
Finished Jul 31 04:56:38 PM PDT 24
Peak memory 159400 kb
Host smart-04869114-a3d9-4bee-bb68-8aa61b00eb1a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3186987767 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.3186987767
Directory /workspace/49.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.2161168003
Short name T16
Test name
Test status
Simulation time 337020990000 ps
CPU time 657.82 seconds
Started Jul 31 04:18:45 PM PDT 24
Finished Jul 31 04:46:32 PM PDT 24
Peak memory 160220 kb
Host smart-ae64e189-d646-4681-96fd-c9a4f46e871b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2161168003 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.2161168003
Directory /workspace/5.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.1066078171
Short name T88
Test name
Test status
Simulation time 336873030000 ps
CPU time 818.81 seconds
Started Jul 31 04:18:51 PM PDT 24
Finished Jul 31 04:52:04 PM PDT 24
Peak memory 159220 kb
Host smart-fcbf833c-c45d-4f11-87c8-6fa3b9b68230
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1066078171 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.1066078171
Directory /workspace/6.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.610096433
Short name T93
Test name
Test status
Simulation time 336810790000 ps
CPU time 745.54 seconds
Started Jul 31 04:18:44 PM PDT 24
Finished Jul 31 04:49:08 PM PDT 24
Peak memory 159108 kb
Host smart-ef05530b-5bd7-4188-895f-96db41fc0945
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=610096433 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.610096433
Directory /workspace/7.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1085720690
Short name T103
Test name
Test status
Simulation time 336490630000 ps
CPU time 821.35 seconds
Started Jul 31 04:18:51 PM PDT 24
Finished Jul 31 04:52:03 PM PDT 24
Peak memory 159228 kb
Host smart-7667a499-0108-4d36-9d8b-b083cd95e57d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1085720690 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.1085720690
Directory /workspace/8.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.1280055582
Short name T81
Test name
Test status
Simulation time 336849570000 ps
CPU time 673.38 seconds
Started Jul 31 04:18:45 PM PDT 24
Finished Jul 31 04:47:03 PM PDT 24
Peak memory 160220 kb
Host smart-92845b22-a4f1-4d9c-b387-f5c9bd02acf7
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1280055582 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.1280055582
Directory /workspace/9.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.4120553612
Short name T180
Test name
Test status
Simulation time 336607550000 ps
CPU time 742.48 seconds
Started Jul 31 04:39:53 PM PDT 24
Finished Jul 31 05:10:48 PM PDT 24
Peak memory 158508 kb
Host smart-959718c2-95b4-46e5-bb17-5121dfd845f4
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4120553612 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.4120553612
Directory /workspace/0.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.2462416561
Short name T187
Test name
Test status
Simulation time 336715750000 ps
CPU time 747.58 seconds
Started Jul 31 04:39:53 PM PDT 24
Finished Jul 31 05:11:00 PM PDT 24
Peak memory 158556 kb
Host smart-32b9905b-aab9-4097-98b7-14285ffe5554
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2462416561 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.2462416561
Directory /workspace/1.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.1604787432
Short name T195
Test name
Test status
Simulation time 337019850000 ps
CPU time 659.31 seconds
Started Jul 31 04:38:50 PM PDT 24
Finished Jul 31 05:05:52 PM PDT 24
Peak memory 160752 kb
Host smart-8f47a786-26fc-4f49-925a-3cf5e8dfbfb2
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1604787432 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.1604787432
Directory /workspace/10.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.3038868280
Short name T166
Test name
Test status
Simulation time 336414190000 ps
CPU time 863.01 seconds
Started Jul 31 04:38:58 PM PDT 24
Finished Jul 31 05:14:47 PM PDT 24
Peak memory 160720 kb
Host smart-b8427c2b-d300-4cd8-934b-37be412adbb0
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3038868280 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.3038868280
Directory /workspace/11.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.3274626964
Short name T185
Test name
Test status
Simulation time 336749790000 ps
CPU time 518.98 seconds
Started Jul 31 04:38:57 PM PDT 24
Finished Jul 31 05:00:56 PM PDT 24
Peak memory 160712 kb
Host smart-1af0d472-3d58-4d9a-b164-57a55145a638
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3274626964 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.3274626964
Directory /workspace/13.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.576395431
Short name T176
Test name
Test status
Simulation time 336985250000 ps
CPU time 806.05 seconds
Started Jul 31 04:38:58 PM PDT 24
Finished Jul 31 05:11:47 PM PDT 24
Peak memory 160556 kb
Host smart-f4c9cf23-2733-4071-9dba-ec79a40d4b40
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=576395431 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.576395431
Directory /workspace/14.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.1264344396
Short name T173
Test name
Test status
Simulation time 337015770000 ps
CPU time 718.77 seconds
Started Jul 31 04:39:01 PM PDT 24
Finished Jul 31 05:08:28 PM PDT 24
Peak memory 160728 kb
Host smart-8766f798-0139-4e85-82cb-00638d02e1a3
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1264344396 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.1264344396
Directory /workspace/15.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.171559880
Short name T163
Test name
Test status
Simulation time 336480330000 ps
CPU time 705.27 seconds
Started Jul 31 04:38:52 PM PDT 24
Finished Jul 31 05:08:03 PM PDT 24
Peak memory 160632 kb
Host smart-a80c2385-49b1-4585-924d-c2e16ca5ff2f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=171559880 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.171559880
Directory /workspace/16.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.2482267014
Short name T192
Test name
Test status
Simulation time 336660970000 ps
CPU time 670.86 seconds
Started Jul 31 04:38:55 PM PDT 24
Finished Jul 31 05:06:45 PM PDT 24
Peak memory 160648 kb
Host smart-0a249591-6313-4a80-8856-a752fe666c59
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2482267014 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.2482267014
Directory /workspace/17.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.300480712
Short name T196
Test name
Test status
Simulation time 336426090000 ps
CPU time 709.41 seconds
Started Jul 31 04:39:07 PM PDT 24
Finished Jul 31 05:08:32 PM PDT 24
Peak memory 160556 kb
Host smart-81f93661-7af5-4b4e-b27f-bfae92d64865
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=300480712 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.300480712
Directory /workspace/18.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.1312808485
Short name T193
Test name
Test status
Simulation time 336404990000 ps
CPU time 742.94 seconds
Started Jul 31 04:38:55 PM PDT 24
Finished Jul 31 05:09:09 PM PDT 24
Peak memory 160668 kb
Host smart-bbc34be8-fb66-4e34-9707-f1ff7c900ce9
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1312808485 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.1312808485
Directory /workspace/19.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.2972990108
Short name T186
Test name
Test status
Simulation time 336588670000 ps
CPU time 758.85 seconds
Started Jul 31 04:39:53 PM PDT 24
Finished Jul 31 05:11:09 PM PDT 24
Peak memory 159152 kb
Host smart-b5941e63-4bed-4c3d-8756-b7eb37c6ee66
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2972990108 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.2972990108
Directory /workspace/2.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.1087463369
Short name T169
Test name
Test status
Simulation time 336627230000 ps
CPU time 572.39 seconds
Started Jul 31 04:38:56 PM PDT 24
Finished Jul 31 05:02:26 PM PDT 24
Peak memory 160672 kb
Host smart-21a9d428-515f-42e1-b7db-744cba3986b3
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1087463369 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.1087463369
Directory /workspace/20.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.386309933
Short name T175
Test name
Test status
Simulation time 336347210000 ps
CPU time 857.53 seconds
Started Jul 31 04:39:00 PM PDT 24
Finished Jul 31 05:14:45 PM PDT 24
Peak memory 160708 kb
Host smart-05da1390-4a98-4d5b-8020-480fa8191929
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=386309933 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.386309933
Directory /workspace/21.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.4194959800
Short name T164
Test name
Test status
Simulation time 336744650000 ps
CPU time 733.54 seconds
Started Jul 31 04:39:02 PM PDT 24
Finished Jul 31 05:09:06 PM PDT 24
Peak memory 160624 kb
Host smart-e81d52bd-f018-46ba-bc70-d3fdcd267253
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4194959800 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.4194959800
Directory /workspace/22.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.2640384675
Short name T191
Test name
Test status
Simulation time 336934270000 ps
CPU time 862.2 seconds
Started Jul 31 04:38:54 PM PDT 24
Finished Jul 31 05:14:37 PM PDT 24
Peak memory 160716 kb
Host smart-1969dda0-62c2-424d-b111-3de7c522a003
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2640384675 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.2640384675
Directory /workspace/23.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.3783603768
Short name T29
Test name
Test status
Simulation time 336859110000 ps
CPU time 662.01 seconds
Started Jul 31 04:38:59 PM PDT 24
Finished Jul 31 05:06:21 PM PDT 24
Peak memory 160676 kb
Host smart-b177b03b-320b-4710-a37e-aed6a30e1606
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3783603768 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.3783603768
Directory /workspace/24.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.2089365658
Short name T24
Test name
Test status
Simulation time 336450810000 ps
CPU time 694.11 seconds
Started Jul 31 04:39:00 PM PDT 24
Finished Jul 31 05:07:25 PM PDT 24
Peak memory 160672 kb
Host smart-5f7dfd77-e548-4325-85b3-18370ff76562
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2089365658 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.2089365658
Directory /workspace/25.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.1962602216
Short name T181
Test name
Test status
Simulation time 337048130000 ps
CPU time 632.5 seconds
Started Jul 31 04:38:54 PM PDT 24
Finished Jul 31 05:04:47 PM PDT 24
Peak memory 160672 kb
Host smart-f8728276-3826-4ac0-af13-65057e87dfa1
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1962602216 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.1962602216
Directory /workspace/26.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.2336792305
Short name T27
Test name
Test status
Simulation time 336294710000 ps
CPU time 647.96 seconds
Started Jul 31 04:39:11 PM PDT 24
Finished Jul 31 05:06:14 PM PDT 24
Peak memory 160640 kb
Host smart-3e8a5d36-4611-478d-a7ed-31744db7c1e9
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2336792305 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.2336792305
Directory /workspace/27.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.2762938974
Short name T183
Test name
Test status
Simulation time 336515050000 ps
CPU time 756.18 seconds
Started Jul 31 04:39:01 PM PDT 24
Finished Jul 31 05:10:04 PM PDT 24
Peak memory 160652 kb
Host smart-230e2b43-4327-4770-a3a6-6ca6bc4e756e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2762938974 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.2762938974
Directory /workspace/28.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.2069486591
Short name T178
Test name
Test status
Simulation time 336742830000 ps
CPU time 615.77 seconds
Started Jul 31 04:38:58 PM PDT 24
Finished Jul 31 05:04:35 PM PDT 24
Peak memory 160672 kb
Host smart-490ff1d0-a92a-40f4-9346-76f280cdea90
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2069486591 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.2069486591
Directory /workspace/29.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.153315925
Short name T30
Test name
Test status
Simulation time 337050850000 ps
CPU time 792.16 seconds
Started Jul 31 04:40:10 PM PDT 24
Finished Jul 31 05:12:35 PM PDT 24
Peak memory 160228 kb
Host smart-f0d363b4-97bf-4604-b7dd-6add6e8a0f51
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=153315925 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.153315925
Directory /workspace/3.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.1555052578
Short name T21
Test name
Test status
Simulation time 336780890000 ps
CPU time 641.98 seconds
Started Jul 31 04:38:55 PM PDT 24
Finished Jul 31 05:05:32 PM PDT 24
Peak memory 160744 kb
Host smart-68f0ef80-a079-4465-bf0e-e6b823b811fd
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1555052578 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.1555052578
Directory /workspace/30.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.1652300617
Short name T25
Test name
Test status
Simulation time 336469230000 ps
CPU time 944.27 seconds
Started Jul 31 04:39:01 PM PDT 24
Finished Jul 31 05:18:35 PM PDT 24
Peak memory 160884 kb
Host smart-45af59fd-105e-42ca-9700-d4f326b4fe5d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1652300617 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.1652300617
Directory /workspace/31.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.3029617658
Short name T198
Test name
Test status
Simulation time 336769330000 ps
CPU time 704.94 seconds
Started Jul 31 04:38:55 PM PDT 24
Finished Jul 31 05:07:56 PM PDT 24
Peak memory 160672 kb
Host smart-6cccb2b7-6190-44b5-8db3-be07b94105f4
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3029617658 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.3029617658
Directory /workspace/32.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.3786428051
Short name T167
Test name
Test status
Simulation time 337012930000 ps
CPU time 662.39 seconds
Started Jul 31 04:38:56 PM PDT 24
Finished Jul 31 05:06:13 PM PDT 24
Peak memory 160676 kb
Host smart-6938a00f-0787-4101-9c54-44f7fedfa269
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3786428051 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.3786428051
Directory /workspace/33.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.91522846
Short name T170
Test name
Test status
Simulation time 336986490000 ps
CPU time 787.1 seconds
Started Jul 31 04:38:57 PM PDT 24
Finished Jul 31 05:11:33 PM PDT 24
Peak memory 160652 kb
Host smart-8ac0728f-9fe4-4b90-8ae0-08b5dd3cf6ae
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=91522846 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.91522846
Directory /workspace/34.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.153464569
Short name T184
Test name
Test status
Simulation time 336702550000 ps
CPU time 634.06 seconds
Started Jul 31 04:38:57 PM PDT 24
Finished Jul 31 05:05:16 PM PDT 24
Peak memory 160612 kb
Host smart-72b20f23-f130-400c-ad99-7a9fcf5d84b7
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=153464569 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.153464569
Directory /workspace/35.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.1985051813
Short name T171
Test name
Test status
Simulation time 336785010000 ps
CPU time 650.72 seconds
Started Jul 31 04:39:07 PM PDT 24
Finished Jul 31 05:06:04 PM PDT 24
Peak memory 160672 kb
Host smart-9d603b8e-4f5e-4182-ad8d-65b38dfe039c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1985051813 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.1985051813
Directory /workspace/36.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.2586837883
Short name T179
Test name
Test status
Simulation time 337001230000 ps
CPU time 711.17 seconds
Started Jul 31 04:38:57 PM PDT 24
Finished Jul 31 05:08:28 PM PDT 24
Peak memory 160668 kb
Host smart-5901a0d0-a802-41c8-a12e-9cdaac1ec485
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2586837883 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.2586837883
Directory /workspace/37.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.804936065
Short name T199
Test name
Test status
Simulation time 336949590000 ps
CPU time 855.06 seconds
Started Jul 31 04:38:54 PM PDT 24
Finished Jul 31 05:14:31 PM PDT 24
Peak memory 160708 kb
Host smart-0b1d6182-1f25-4885-99ae-8192287e3f1d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=804936065 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.804936065
Directory /workspace/38.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.1353824558
Short name T162
Test name
Test status
Simulation time 336290550000 ps
CPU time 583.69 seconds
Started Jul 31 04:38:58 PM PDT 24
Finished Jul 31 05:03:36 PM PDT 24
Peak memory 160728 kb
Host smart-46354cc8-897f-408a-a1e0-288e789fc32f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1353824558 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.1353824558
Directory /workspace/39.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.2023141874
Short name T188
Test name
Test status
Simulation time 337103610000 ps
CPU time 785.64 seconds
Started Jul 31 04:38:57 PM PDT 24
Finished Jul 31 05:11:30 PM PDT 24
Peak memory 160660 kb
Host smart-e697b3e0-5699-486e-8b72-28dd2cc3637d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2023141874 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.2023141874
Directory /workspace/4.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.2191929405
Short name T197
Test name
Test status
Simulation time 336661830000 ps
CPU time 751.97 seconds
Started Jul 31 04:39:07 PM PDT 24
Finished Jul 31 05:10:00 PM PDT 24
Peak memory 160652 kb
Host smart-4ca567ee-f3c3-4707-9619-641febb4f5df
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2191929405 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.2191929405
Directory /workspace/40.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.2938087628
Short name T161
Test name
Test status
Simulation time 336843510000 ps
CPU time 617.01 seconds
Started Jul 31 04:39:05 PM PDT 24
Finished Jul 31 05:04:45 PM PDT 24
Peak memory 160660 kb
Host smart-c1c3c9c9-522a-4a5e-963c-2b38b4b854d1
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2938087628 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.2938087628
Directory /workspace/41.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.231645110
Short name T189
Test name
Test status
Simulation time 336760450000 ps
CPU time 670.23 seconds
Started Jul 31 04:38:57 PM PDT 24
Finished Jul 31 05:06:34 PM PDT 24
Peak memory 160676 kb
Host smart-3eebf5f4-15c0-4d87-b52b-5ff1944a92d7
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=231645110 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.231645110
Directory /workspace/42.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.1418359099
Short name T190
Test name
Test status
Simulation time 336323290000 ps
CPU time 695.82 seconds
Started Jul 31 04:39:01 PM PDT 24
Finished Jul 31 05:07:30 PM PDT 24
Peak memory 160672 kb
Host smart-0f40c3f3-283f-426d-9314-af4f0c9edbe9
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1418359099 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.1418359099
Directory /workspace/43.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.15362083
Short name T168
Test name
Test status
Simulation time 336744010000 ps
CPU time 684.07 seconds
Started Jul 31 04:38:55 PM PDT 24
Finished Jul 31 05:07:03 PM PDT 24
Peak memory 160584 kb
Host smart-15debd20-9c25-4d0a-9425-c9363c17941a
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=15362083 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.15362083
Directory /workspace/44.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.1281586925
Short name T26
Test name
Test status
Simulation time 336700370000 ps
CPU time 740.83 seconds
Started Jul 31 04:38:56 PM PDT 24
Finished Jul 31 05:09:34 PM PDT 24
Peak memory 160716 kb
Host smart-eb3f00f9-2aa5-444e-ba10-8ff176973df3
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1281586925 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.1281586925
Directory /workspace/45.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.3769704031
Short name T182
Test name
Test status
Simulation time 336416050000 ps
CPU time 644.33 seconds
Started Jul 31 04:39:10 PM PDT 24
Finished Jul 31 05:05:45 PM PDT 24
Peak memory 160688 kb
Host smart-21827f9c-5c1d-4bfd-89c8-e87726d8e75f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3769704031 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.3769704031
Directory /workspace/46.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.4259878666
Short name T172
Test name
Test status
Simulation time 336439230000 ps
CPU time 740.91 seconds
Started Jul 31 04:38:56 PM PDT 24
Finished Jul 31 05:09:09 PM PDT 24
Peak memory 160672 kb
Host smart-7ef1fa6c-644b-44dc-b257-ffa3d407dca3
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4259878666 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.4259878666
Directory /workspace/47.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.2489861980
Short name T174
Test name
Test status
Simulation time 336642370000 ps
CPU time 653.13 seconds
Started Jul 31 04:38:57 PM PDT 24
Finished Jul 31 05:06:05 PM PDT 24
Peak memory 160560 kb
Host smart-7f0b6f66-0a35-4df9-a8b0-e93dd97b224b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2489861980 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.2489861980
Directory /workspace/48.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.651670855
Short name T194
Test name
Test status
Simulation time 337128890000 ps
CPU time 581.91 seconds
Started Jul 31 04:39:01 PM PDT 24
Finished Jul 31 05:03:04 PM PDT 24
Peak memory 160596 kb
Host smart-c153daf9-eb46-4e3d-aaa2-0ada7140e2d9
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=651670855 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.651670855
Directory /workspace/49.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.1538262510
Short name T200
Test name
Test status
Simulation time 336870450000 ps
CPU time 798.33 seconds
Started Jul 31 04:38:53 PM PDT 24
Finished Jul 31 05:11:58 PM PDT 24
Peak memory 160660 kb
Host smart-a9e8d788-b814-4ef0-b1ad-3f28f05915f7
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1538262510 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.1538262510
Directory /workspace/5.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.1715790233
Short name T165
Test name
Test status
Simulation time 337133390000 ps
CPU time 807.57 seconds
Started Jul 31 04:38:48 PM PDT 24
Finished Jul 31 05:11:35 PM PDT 24
Peak memory 160556 kb
Host smart-44b4a877-75b4-4309-a19b-9965ffe3fee1
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1715790233 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.1715790233
Directory /workspace/6.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.590511996
Short name T28
Test name
Test status
Simulation time 336972930000 ps
CPU time 790.33 seconds
Started Jul 31 04:38:54 PM PDT 24
Finished Jul 31 05:11:49 PM PDT 24
Peak memory 160652 kb
Host smart-0756f57e-dc71-472c-9ed7-aacf380cdcfd
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=590511996 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.590511996
Directory /workspace/7.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.2820990643
Short name T177
Test name
Test status
Simulation time 336864750000 ps
CPU time 631.88 seconds
Started Jul 31 04:38:50 PM PDT 24
Finished Jul 31 05:05:06 PM PDT 24
Peak memory 160700 kb
Host smart-7c4a5505-ec4a-421e-a0d1-0f7329709a8d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2820990643 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.2820990643
Directory /workspace/8.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.3017490926
Short name T23
Test name
Test status
Simulation time 336448670000 ps
CPU time 661.58 seconds
Started Jul 31 04:38:50 PM PDT 24
Finished Jul 31 05:06:01 PM PDT 24
Peak memory 160648 kb
Host smart-7391e774-e897-4f52-9aae-0a3dbf7b9198
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3017490926 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.3017490926
Directory /workspace/9.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.484616409
Short name T131
Test name
Test status
Simulation time 1580990000 ps
CPU time 4.67 seconds
Started Jul 31 04:24:56 PM PDT 24
Finished Jul 31 04:25:06 PM PDT 24
Peak memory 164508 kb
Host smart-cc195188-1bd8-4f5f-8723-7a3b06b47d37
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=484616409 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.484616409
Directory /workspace/0.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.1694220850
Short name T147
Test name
Test status
Simulation time 1457610000 ps
CPU time 3.93 seconds
Started Jul 31 04:24:59 PM PDT 24
Finished Jul 31 04:25:07 PM PDT 24
Peak memory 164484 kb
Host smart-2e005aa1-7ef4-4572-bd00-b584cf1d3407
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1694220850 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.1694220850
Directory /workspace/1.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.3267141819
Short name T158
Test name
Test status
Simulation time 1575570000 ps
CPU time 3.54 seconds
Started Jul 31 04:20:53 PM PDT 24
Finished Jul 31 04:21:01 PM PDT 24
Peak memory 164716 kb
Host smart-81e8bae9-af47-42a4-8923-51b5477bf611
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3267141819 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.3267141819
Directory /workspace/10.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.3561697643
Short name T153
Test name
Test status
Simulation time 1239750000 ps
CPU time 2.7 seconds
Started Jul 31 04:24:38 PM PDT 24
Finished Jul 31 04:24:45 PM PDT 24
Peak memory 163676 kb
Host smart-a495f92a-057b-4b3f-b821-0e5908280b01
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3561697643 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.3561697643
Directory /workspace/11.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.2552265394
Short name T111
Test name
Test status
Simulation time 1537810000 ps
CPU time 5.67 seconds
Started Jul 31 04:24:17 PM PDT 24
Finished Jul 31 04:24:30 PM PDT 24
Peak memory 164996 kb
Host smart-6d315dfa-617e-40f2-b8a5-be5242d08233
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2552265394 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.2552265394
Directory /workspace/12.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.281684626
Short name T118
Test name
Test status
Simulation time 1461370000 ps
CPU time 4.3 seconds
Started Jul 31 04:22:27 PM PDT 24
Finished Jul 31 04:22:37 PM PDT 24
Peak memory 164788 kb
Host smart-be162cf3-fced-45ce-a11b-67abb83d388b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=281684626 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.281684626
Directory /workspace/13.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.2145784916
Short name T143
Test name
Test status
Simulation time 1346530000 ps
CPU time 3.72 seconds
Started Jul 31 04:24:59 PM PDT 24
Finished Jul 31 04:25:07 PM PDT 24
Peak memory 164508 kb
Host smart-57a9c9db-c044-4be5-8437-f914f26b2c0a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2145784916 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.2145784916
Directory /workspace/14.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.3671158082
Short name T149
Test name
Test status
Simulation time 1247070000 ps
CPU time 4.58 seconds
Started Jul 31 04:25:37 PM PDT 24
Finished Jul 31 04:25:47 PM PDT 24
Peak memory 164644 kb
Host smart-567a687f-5d70-405f-9314-42a2dd236bac
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3671158082 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.3671158082
Directory /workspace/15.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.771553033
Short name T121
Test name
Test status
Simulation time 1276470000 ps
CPU time 3.93 seconds
Started Jul 31 04:22:44 PM PDT 24
Finished Jul 31 04:22:53 PM PDT 24
Peak memory 164780 kb
Host smart-ee5ef262-0d49-4ef2-b900-445fa9f9e5de
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=771553033 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.771553033
Directory /workspace/16.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.3884983011
Short name T134
Test name
Test status
Simulation time 1220830000 ps
CPU time 4.18 seconds
Started Jul 31 04:22:49 PM PDT 24
Finished Jul 31 04:22:58 PM PDT 24
Peak memory 164788 kb
Host smart-677be58b-581c-4c05-9976-8fae767560ac
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3884983011 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.3884983011
Directory /workspace/17.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.3306906189
Short name T113
Test name
Test status
Simulation time 1532870000 ps
CPU time 4.49 seconds
Started Jul 31 04:20:39 PM PDT 24
Finished Jul 31 04:20:48 PM PDT 24
Peak memory 164704 kb
Host smart-59e2410d-06e2-4bf8-80b3-0905e8a14d4b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3306906189 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.3306906189
Directory /workspace/18.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.1712105318
Short name T152
Test name
Test status
Simulation time 1447470000 ps
CPU time 5.78 seconds
Started Jul 31 04:23:24 PM PDT 24
Finished Jul 31 04:23:38 PM PDT 24
Peak memory 164996 kb
Host smart-e579dfac-e725-453f-8833-9fb8b38136c6
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1712105318 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.1712105318
Directory /workspace/19.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.3883466445
Short name T160
Test name
Test status
Simulation time 1517510000 ps
CPU time 3.56 seconds
Started Jul 31 04:24:51 PM PDT 24
Finished Jul 31 04:24:59 PM PDT 24
Peak memory 164324 kb
Host smart-488c4e95-0fa7-47f1-baf9-94bc11120111
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3883466445 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.3883466445
Directory /workspace/2.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.2000642294
Short name T148
Test name
Test status
Simulation time 1495690000 ps
CPU time 4.93 seconds
Started Jul 31 04:20:42 PM PDT 24
Finished Jul 31 04:20:53 PM PDT 24
Peak memory 164784 kb
Host smart-33866894-fafc-46b3-b3e4-077dda272d94
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2000642294 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.2000642294
Directory /workspace/20.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.1573309363
Short name T141
Test name
Test status
Simulation time 1203210000 ps
CPU time 3.22 seconds
Started Jul 31 04:25:01 PM PDT 24
Finished Jul 31 04:25:08 PM PDT 24
Peak memory 164676 kb
Host smart-a5967671-f10a-4466-bbfe-19f9518bf13a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1573309363 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.1573309363
Directory /workspace/21.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.1254575249
Short name T123
Test name
Test status
Simulation time 1496590000 ps
CPU time 4.24 seconds
Started Jul 31 04:24:59 PM PDT 24
Finished Jul 31 04:25:09 PM PDT 24
Peak memory 164508 kb
Host smart-5010243c-2565-4910-b57c-3e587816ea34
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1254575249 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.1254575249
Directory /workspace/22.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.740779146
Short name T144
Test name
Test status
Simulation time 1434510000 ps
CPU time 3.95 seconds
Started Jul 31 04:25:42 PM PDT 24
Finished Jul 31 04:25:50 PM PDT 24
Peak memory 164480 kb
Host smart-02a75d31-e0e0-4a72-bdf4-9459ec50d9e2
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=740779146 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.740779146
Directory /workspace/23.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.1359960876
Short name T117
Test name
Test status
Simulation time 1435550000 ps
CPU time 3.8 seconds
Started Jul 31 04:25:00 PM PDT 24
Finished Jul 31 04:25:08 PM PDT 24
Peak memory 164672 kb
Host smart-6215c897-4f6b-4449-8372-571833b1a3e7
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1359960876 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.1359960876
Directory /workspace/24.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.1161126223
Short name T116
Test name
Test status
Simulation time 1241390000 ps
CPU time 3.03 seconds
Started Jul 31 04:24:56 PM PDT 24
Finished Jul 31 04:25:03 PM PDT 24
Peak memory 164572 kb
Host smart-047f6841-cc2f-455f-8718-9f2c62a7f973
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1161126223 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.1161126223
Directory /workspace/25.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2279451872
Short name T138
Test name
Test status
Simulation time 1537570000 ps
CPU time 5.96 seconds
Started Jul 31 04:22:49 PM PDT 24
Finished Jul 31 04:23:02 PM PDT 24
Peak memory 164796 kb
Host smart-db29bc84-26f7-46f3-8a76-2213a5343980
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2279451872 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.2279451872
Directory /workspace/26.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.4243145348
Short name T133
Test name
Test status
Simulation time 1586770000 ps
CPU time 5.06 seconds
Started Jul 31 04:22:43 PM PDT 24
Finished Jul 31 04:22:54 PM PDT 24
Peak memory 164716 kb
Host smart-c694d8d7-971f-4095-9546-265ae5f2a15e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4243145348 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.4243145348
Directory /workspace/27.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.3781993059
Short name T119
Test name
Test status
Simulation time 1539610000 ps
CPU time 3.62 seconds
Started Jul 31 04:24:46 PM PDT 24
Finished Jul 31 04:24:54 PM PDT 24
Peak memory 163780 kb
Host smart-f04e08e1-1fdf-425c-ace2-e31d397fe33a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3781993059 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.3781993059
Directory /workspace/28.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.1093612278
Short name T125
Test name
Test status
Simulation time 1311490000 ps
CPU time 4.28 seconds
Started Jul 31 04:22:43 PM PDT 24
Finished Jul 31 04:22:52 PM PDT 24
Peak memory 164716 kb
Host smart-c23d43a4-3f49-4fd6-a4d7-54fdcee55348
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1093612278 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.1093612278
Directory /workspace/29.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.2813259936
Short name T112
Test name
Test status
Simulation time 1610130000 ps
CPU time 4.46 seconds
Started Jul 31 04:21:28 PM PDT 24
Finished Jul 31 04:21:38 PM PDT 24
Peak memory 164776 kb
Host smart-c6704f93-7da2-4d71-bd7d-9c1ba3729960
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2813259936 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.2813259936
Directory /workspace/3.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.1034217025
Short name T155
Test name
Test status
Simulation time 1620470000 ps
CPU time 5.37 seconds
Started Jul 31 04:22:39 PM PDT 24
Finished Jul 31 04:22:51 PM PDT 24
Peak memory 164788 kb
Host smart-32479610-3fad-44f9-8be7-8129f23498ca
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1034217025 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.1034217025
Directory /workspace/30.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.180926896
Short name T136
Test name
Test status
Simulation time 1362490000 ps
CPU time 4.03 seconds
Started Jul 31 04:24:59 PM PDT 24
Finished Jul 31 04:25:08 PM PDT 24
Peak memory 164496 kb
Host smart-f175f602-0c34-4e36-93bd-16bb1f3918eb
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=180926896 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.180926896
Directory /workspace/31.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.665939097
Short name T135
Test name
Test status
Simulation time 1550590000 ps
CPU time 3.97 seconds
Started Jul 31 04:25:06 PM PDT 24
Finished Jul 31 04:25:15 PM PDT 24
Peak memory 164680 kb
Host smart-ec174a0d-8fbf-4e04-aeea-46ca8970326e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=665939097 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.665939097
Directory /workspace/32.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.3145156749
Short name T114
Test name
Test status
Simulation time 1550030000 ps
CPU time 3.97 seconds
Started Jul 31 04:24:54 PM PDT 24
Finished Jul 31 04:25:02 PM PDT 24
Peak memory 163644 kb
Host smart-750f0d99-0b97-40a9-b1b0-caa222e370d9
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3145156749 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.3145156749
Directory /workspace/33.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.1848751241
Short name T130
Test name
Test status
Simulation time 1592290000 ps
CPU time 5.17 seconds
Started Jul 31 04:22:49 PM PDT 24
Finished Jul 31 04:23:00 PM PDT 24
Peak memory 164800 kb
Host smart-9ef27732-8349-4236-98ee-4ef7b164dc4c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1848751241 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.1848751241
Directory /workspace/34.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.2177516366
Short name T142
Test name
Test status
Simulation time 1574050000 ps
CPU time 4.09 seconds
Started Jul 31 04:24:52 PM PDT 24
Finished Jul 31 04:25:01 PM PDT 24
Peak memory 164748 kb
Host smart-04a6a3a9-386c-40f9-83c2-2380131514c9
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2177516366 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.2177516366
Directory /workspace/35.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.996257020
Short name T154
Test name
Test status
Simulation time 1605450000 ps
CPU time 5.59 seconds
Started Jul 31 04:23:26 PM PDT 24
Finished Jul 31 04:23:38 PM PDT 24
Peak memory 164816 kb
Host smart-f78be66a-7dc0-4622-9e37-4c48fc7248d4
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=996257020 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.996257020
Directory /workspace/36.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1893779650
Short name T128
Test name
Test status
Simulation time 1457070000 ps
CPU time 4.71 seconds
Started Jul 31 04:23:23 PM PDT 24
Finished Jul 31 04:23:33 PM PDT 24
Peak memory 164716 kb
Host smart-08fb7d0d-da56-49b6-a655-c3221c27b1a7
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1893779650 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.1893779650
Directory /workspace/37.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.4025336791
Short name T156
Test name
Test status
Simulation time 1548150000 ps
CPU time 5.21 seconds
Started Jul 31 04:23:17 PM PDT 24
Finished Jul 31 04:23:29 PM PDT 24
Peak memory 164724 kb
Host smart-a75ca080-435a-4d83-891a-be6360168810
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4025336791 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.4025336791
Directory /workspace/38.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.1769328588
Short name T151
Test name
Test status
Simulation time 1501230000 ps
CPU time 3.6 seconds
Started Jul 31 04:20:58 PM PDT 24
Finished Jul 31 04:21:06 PM PDT 24
Peak memory 163840 kb
Host smart-1030b061-9ea5-4a36-82ff-0abdbeffece1
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1769328588 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.1769328588
Directory /workspace/39.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.2832748230
Short name T127
Test name
Test status
Simulation time 1520130000 ps
CPU time 3.34 seconds
Started Jul 31 04:24:44 PM PDT 24
Finished Jul 31 04:24:52 PM PDT 24
Peak memory 164516 kb
Host smart-9770b8e8-fd7f-4d67-b676-cf83cad27431
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2832748230 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.2832748230
Directory /workspace/4.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.3824820213
Short name T159
Test name
Test status
Simulation time 1559210000 ps
CPU time 3.5 seconds
Started Jul 31 04:25:48 PM PDT 24
Finished Jul 31 04:25:56 PM PDT 24
Peak memory 164696 kb
Host smart-090c878e-337f-4875-b24b-7383efd9ef34
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3824820213 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.3824820213
Directory /workspace/40.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.1566479741
Short name T140
Test name
Test status
Simulation time 1463650000 ps
CPU time 3.08 seconds
Started Jul 31 04:36:17 PM PDT 24
Finished Jul 31 04:36:24 PM PDT 24
Peak memory 164748 kb
Host smart-c47882ce-e7ec-4d89-8918-7a9f54b8e557
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1566479741 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.1566479741
Directory /workspace/41.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.3047204214
Short name T139
Test name
Test status
Simulation time 1329670000 ps
CPU time 5.59 seconds
Started Jul 31 04:36:23 PM PDT 24
Finished Jul 31 04:36:36 PM PDT 24
Peak memory 164824 kb
Host smart-6c994d8b-dc20-47c4-90be-17866ef9d184
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3047204214 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.3047204214
Directory /workspace/42.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.2819262136
Short name T129
Test name
Test status
Simulation time 1457830000 ps
CPU time 6.09 seconds
Started Jul 31 04:36:23 PM PDT 24
Finished Jul 31 04:36:36 PM PDT 24
Peak memory 164784 kb
Host smart-fe47734a-7942-4a14-8a41-b5e043607c92
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2819262136 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.2819262136
Directory /workspace/43.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.861628974
Short name T157
Test name
Test status
Simulation time 957270000 ps
CPU time 2.78 seconds
Started Jul 31 04:36:23 PM PDT 24
Finished Jul 31 04:36:29 PM PDT 24
Peak memory 164692 kb
Host smart-9373626d-f2bd-4fd9-9a2e-b0e2b77efb63
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=861628974 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.861628974
Directory /workspace/44.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.2077317214
Short name T146
Test name
Test status
Simulation time 1540350000 ps
CPU time 5.76 seconds
Started Jul 31 04:36:26 PM PDT 24
Finished Jul 31 04:36:38 PM PDT 24
Peak memory 164724 kb
Host smart-37425344-5c63-4add-9a80-b68f9b4acb20
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2077317214 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.2077317214
Directory /workspace/45.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.4192793967
Short name T124
Test name
Test status
Simulation time 1497910000 ps
CPU time 4.71 seconds
Started Jul 31 04:36:25 PM PDT 24
Finished Jul 31 04:36:35 PM PDT 24
Peak memory 164728 kb
Host smart-16efed0f-2c6d-48c9-bdc1-ea184cfea71e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4192793967 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.4192793967
Directory /workspace/46.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.3898588176
Short name T122
Test name
Test status
Simulation time 1512330000 ps
CPU time 5.91 seconds
Started Jul 31 04:36:23 PM PDT 24
Finished Jul 31 04:36:37 PM PDT 24
Peak memory 164996 kb
Host smart-00e5b207-542d-445e-9ab2-00b4594b5d56
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3898588176 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.3898588176
Directory /workspace/47.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.6833458
Short name T126
Test name
Test status
Simulation time 1492330000 ps
CPU time 3.78 seconds
Started Jul 31 04:36:22 PM PDT 24
Finished Jul 31 04:36:30 PM PDT 24
Peak memory 164708 kb
Host smart-1e63e88d-6fb5-422d-909f-1690f10877b3
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=6833458 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.6833458
Directory /workspace/48.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.1375539701
Short name T150
Test name
Test status
Simulation time 1398910000 ps
CPU time 4.21 seconds
Started Jul 31 04:36:26 PM PDT 24
Finished Jul 31 04:36:35 PM PDT 24
Peak memory 164796 kb
Host smart-a5281b30-a274-49b1-bba4-2cca82bb64ce
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1375539701 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.1375539701
Directory /workspace/49.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.3076165839
Short name T137
Test name
Test status
Simulation time 1272410000 ps
CPU time 4.92 seconds
Started Jul 31 04:22:49 PM PDT 24
Finished Jul 31 04:23:00 PM PDT 24
Peak memory 164808 kb
Host smart-f1a9f7f6-86c8-436e-add8-48879470553d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3076165839 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.3076165839
Directory /workspace/5.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.4280801623
Short name T132
Test name
Test status
Simulation time 1529130000 ps
CPU time 5.56 seconds
Started Jul 31 04:20:55 PM PDT 24
Finished Jul 31 04:21:08 PM PDT 24
Peak memory 164996 kb
Host smart-ce54e3d8-e112-4618-9780-9075c93a79dc
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4280801623 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.4280801623
Directory /workspace/6.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.1118047898
Short name T115
Test name
Test status
Simulation time 1513230000 ps
CPU time 3.73 seconds
Started Jul 31 04:25:22 PM PDT 24
Finished Jul 31 04:25:30 PM PDT 24
Peak memory 163208 kb
Host smart-999ddcb7-6b04-4316-a55e-aa4efd91c7a8
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1118047898 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.1118047898
Directory /workspace/7.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.3866978204
Short name T145
Test name
Test status
Simulation time 1512690000 ps
CPU time 5.18 seconds
Started Jul 31 04:23:17 PM PDT 24
Finished Jul 31 04:23:28 PM PDT 24
Peak memory 164784 kb
Host smart-f310d65c-8b35-4c5e-ae3a-e8336586cfce
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3866978204 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.3866978204
Directory /workspace/8.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.3341688839
Short name T120
Test name
Test status
Simulation time 1363190000 ps
CPU time 2.88 seconds
Started Jul 31 04:20:58 PM PDT 24
Finished Jul 31 04:21:05 PM PDT 24
Peak memory 164676 kb
Host smart-ebbeb1fe-92a2-48bc-8185-6da02a1c175f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3341688839 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.3341688839
Directory /workspace/9.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.1890092764
Short name T68
Test name
Test status
Simulation time 1469530000 ps
CPU time 3.91 seconds
Started Jul 31 04:56:29 PM PDT 24
Finished Jul 31 04:56:38 PM PDT 24
Peak memory 164728 kb
Host smart-1dd10589-079e-4853-8b97-224b3089f780
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1890092764 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.1890092764
Directory /workspace/0.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.2350973370
Short name T11
Test name
Test status
Simulation time 1464070000 ps
CPU time 3.4 seconds
Started Jul 31 04:56:39 PM PDT 24
Finished Jul 31 04:56:47 PM PDT 24
Peak memory 164752 kb
Host smart-df1a50ac-427c-4dad-8724-e2a5b2888ebf
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2350973370 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.2350973370
Directory /workspace/1.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.779306428
Short name T38
Test name
Test status
Simulation time 1366110000 ps
CPU time 4.05 seconds
Started Jul 31 04:56:37 PM PDT 24
Finished Jul 31 04:56:46 PM PDT 24
Peak memory 164836 kb
Host smart-7c10a5a9-21e2-406f-9765-ef44070d873b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=779306428 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.779306428
Directory /workspace/10.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.2693133843
Short name T36
Test name
Test status
Simulation time 1503970000 ps
CPU time 4.68 seconds
Started Jul 31 04:56:38 PM PDT 24
Finished Jul 31 04:56:48 PM PDT 24
Peak memory 164752 kb
Host smart-01f989c0-cb16-4ce2-b319-de8a050e07f6
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2693133843 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.2693133843
Directory /workspace/11.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.2177258776
Short name T32
Test name
Test status
Simulation time 1604730000 ps
CPU time 4.39 seconds
Started Jul 31 04:56:40 PM PDT 24
Finished Jul 31 04:56:50 PM PDT 24
Peak memory 164764 kb
Host smart-a1e03b47-3707-44a6-b4fe-f68f40d85bed
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2177258776 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.2177258776
Directory /workspace/12.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.2456546555
Short name T60
Test name
Test status
Simulation time 1436750000 ps
CPU time 4.91 seconds
Started Jul 31 04:56:41 PM PDT 24
Finished Jul 31 04:56:52 PM PDT 24
Peak memory 164772 kb
Host smart-eb0f9c3e-bdab-4479-96f6-034091ce61c8
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2456546555 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.2456546555
Directory /workspace/14.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.1580851738
Short name T10
Test name
Test status
Simulation time 1525150000 ps
CPU time 5.17 seconds
Started Jul 31 04:56:41 PM PDT 24
Finished Jul 31 04:56:53 PM PDT 24
Peak memory 164772 kb
Host smart-f38de4e3-4d11-4d77-b819-118efa8908b3
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1580851738 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.1580851738
Directory /workspace/15.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.3742193188
Short name T12
Test name
Test status
Simulation time 1491270000 ps
CPU time 4.99 seconds
Started Jul 31 04:56:41 PM PDT 24
Finished Jul 31 04:56:53 PM PDT 24
Peak memory 164772 kb
Host smart-0f46d3a8-9389-4d1a-980c-9d869dbe8ed5
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3742193188 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.3742193188
Directory /workspace/16.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.4241870912
Short name T55
Test name
Test status
Simulation time 1550050000 ps
CPU time 5.26 seconds
Started Jul 31 04:56:42 PM PDT 24
Finished Jul 31 04:56:53 PM PDT 24
Peak memory 164724 kb
Host smart-39fc340f-c54a-4396-8cfe-7b8e0d6ea867
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4241870912 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.4241870912
Directory /workspace/17.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.2691540820
Short name T51
Test name
Test status
Simulation time 1522110000 ps
CPU time 4.51 seconds
Started Jul 31 04:56:41 PM PDT 24
Finished Jul 31 04:56:51 PM PDT 24
Peak memory 164724 kb
Host smart-243625e2-e514-4505-8adf-018549cabf0d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2691540820 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.2691540820
Directory /workspace/18.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.3455130245
Short name T45
Test name
Test status
Simulation time 1601930000 ps
CPU time 5.15 seconds
Started Jul 31 04:56:40 PM PDT 24
Finished Jul 31 04:56:51 PM PDT 24
Peak memory 164712 kb
Host smart-f1eb7268-f4bf-49b2-bc24-30a9eff8ca8e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3455130245 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.3455130245
Directory /workspace/19.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.549041544
Short name T50
Test name
Test status
Simulation time 1209950000 ps
CPU time 4.66 seconds
Started Jul 31 04:56:40 PM PDT 24
Finished Jul 31 04:56:50 PM PDT 24
Peak memory 164764 kb
Host smart-e2fdd960-5e00-4d12-85c6-ecc7b9949079
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=549041544 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.549041544
Directory /workspace/2.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.1425521269
Short name T42
Test name
Test status
Simulation time 1565990000 ps
CPU time 4.58 seconds
Started Jul 31 04:56:38 PM PDT 24
Finished Jul 31 04:56:49 PM PDT 24
Peak memory 164832 kb
Host smart-737fb90b-37f5-4dca-9f67-95ddc0cb4864
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1425521269 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.1425521269
Directory /workspace/20.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.1536873093
Short name T43
Test name
Test status
Simulation time 1601970000 ps
CPU time 5.06 seconds
Started Jul 31 04:56:40 PM PDT 24
Finished Jul 31 04:56:51 PM PDT 24
Peak memory 164732 kb
Host smart-9374d213-17d2-46de-814f-c38dc3313ada
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1536873093 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.1536873093
Directory /workspace/21.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.321371725
Short name T66
Test name
Test status
Simulation time 1422590000 ps
CPU time 5.33 seconds
Started Jul 31 04:56:40 PM PDT 24
Finished Jul 31 04:56:51 PM PDT 24
Peak memory 164716 kb
Host smart-61b2eca5-b9a0-4d6d-b1f8-be7cff4a4fb3
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=321371725 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.321371725
Directory /workspace/22.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.1505960023
Short name T56
Test name
Test status
Simulation time 1506510000 ps
CPU time 5.68 seconds
Started Jul 31 04:56:38 PM PDT 24
Finished Jul 31 04:56:50 PM PDT 24
Peak memory 164752 kb
Host smart-0aaf277c-4e8a-4d45-b0dc-4c2d89eb6732
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1505960023 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.1505960023
Directory /workspace/23.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.466583517
Short name T33
Test name
Test status
Simulation time 1539810000 ps
CPU time 4.88 seconds
Started Jul 31 04:56:43 PM PDT 24
Finished Jul 31 04:56:54 PM PDT 24
Peak memory 164768 kb
Host smart-c02c1819-e06f-4e23-816d-b6dde7fe1b39
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=466583517 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.466583517
Directory /workspace/24.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.4204709731
Short name T64
Test name
Test status
Simulation time 1580450000 ps
CPU time 4.36 seconds
Started Jul 31 04:56:43 PM PDT 24
Finished Jul 31 04:56:53 PM PDT 24
Peak memory 164844 kb
Host smart-019797d7-0b2a-4512-b788-7260ef9d7e9f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4204709731 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.4204709731
Directory /workspace/25.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.2938175897
Short name T54
Test name
Test status
Simulation time 1628650000 ps
CPU time 4.74 seconds
Started Jul 31 04:56:46 PM PDT 24
Finished Jul 31 04:56:57 PM PDT 24
Peak memory 164652 kb
Host smart-7541f205-e140-40ed-90d7-0d8cf1fb685a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2938175897 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.2938175897
Directory /workspace/26.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.900494787
Short name T59
Test name
Test status
Simulation time 1494170000 ps
CPU time 4.45 seconds
Started Jul 31 04:57:25 PM PDT 24
Finished Jul 31 04:57:35 PM PDT 24
Peak memory 164472 kb
Host smart-3b04cdf3-1702-4a50-b6bf-aced317f6bf5
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=900494787 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.900494787
Directory /workspace/27.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.3135798698
Short name T52
Test name
Test status
Simulation time 1467970000 ps
CPU time 5.4 seconds
Started Jul 31 04:56:47 PM PDT 24
Finished Jul 31 04:56:59 PM PDT 24
Peak memory 164812 kb
Host smart-687b35a7-1fc0-4cde-a577-d32b3c37cd81
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3135798698 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.3135798698
Directory /workspace/28.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.4033299884
Short name T35
Test name
Test status
Simulation time 1475950000 ps
CPU time 3.68 seconds
Started Jul 31 04:56:50 PM PDT 24
Finished Jul 31 04:56:58 PM PDT 24
Peak memory 164732 kb
Host smart-fd40e279-d575-46ee-bcdc-2806181bab68
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4033299884 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.4033299884
Directory /workspace/29.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.2859996409
Short name T40
Test name
Test status
Simulation time 1508570000 ps
CPU time 4.17 seconds
Started Jul 31 04:56:38 PM PDT 24
Finished Jul 31 04:56:47 PM PDT 24
Peak memory 164764 kb
Host smart-b88d9552-644e-434b-ae80-0f0a2442b05e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2859996409 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.2859996409
Directory /workspace/3.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.337983579
Short name T69
Test name
Test status
Simulation time 1479910000 ps
CPU time 4.73 seconds
Started Jul 31 04:56:47 PM PDT 24
Finished Jul 31 04:56:58 PM PDT 24
Peak memory 164740 kb
Host smart-72714d36-ec70-4866-9042-e1830b899445
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=337983579 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.337983579
Directory /workspace/30.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.80276812
Short name T2
Test name
Test status
Simulation time 1522810000 ps
CPU time 4.73 seconds
Started Jul 31 04:56:44 PM PDT 24
Finished Jul 31 04:56:55 PM PDT 24
Peak memory 164780 kb
Host smart-8f2507df-73f4-4975-8c56-8b3485bd891d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=80276812 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.80276812
Directory /workspace/31.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.1109004440
Short name T47
Test name
Test status
Simulation time 1197850000 ps
CPU time 3.87 seconds
Started Jul 31 04:56:44 PM PDT 24
Finished Jul 31 04:56:53 PM PDT 24
Peak memory 164796 kb
Host smart-5e624e0b-83bb-488f-9ae2-0dd0fdd6321e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1109004440 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.1109004440
Directory /workspace/32.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.2253441633
Short name T31
Test name
Test status
Simulation time 1211450000 ps
CPU time 4.52 seconds
Started Jul 31 04:56:47 PM PDT 24
Finished Jul 31 04:56:56 PM PDT 24
Peak memory 164812 kb
Host smart-f266a25c-9c68-4b9b-8267-7c86413f9450
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2253441633 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.2253441633
Directory /workspace/33.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.3379677893
Short name T58
Test name
Test status
Simulation time 1598490000 ps
CPU time 4.83 seconds
Started Jul 31 04:56:44 PM PDT 24
Finished Jul 31 04:56:55 PM PDT 24
Peak memory 164784 kb
Host smart-3bce2ebc-63a3-4015-9ee3-0c0ae83d07e0
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3379677893 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.3379677893
Directory /workspace/34.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.590532119
Short name T49
Test name
Test status
Simulation time 1295990000 ps
CPU time 4.1 seconds
Started Jul 31 04:56:45 PM PDT 24
Finished Jul 31 04:56:54 PM PDT 24
Peak memory 164836 kb
Host smart-998a8f82-1799-4760-af41-d372e68f6712
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=590532119 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.590532119
Directory /workspace/35.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.652362270
Short name T34
Test name
Test status
Simulation time 1362590000 ps
CPU time 3.56 seconds
Started Jul 31 04:56:45 PM PDT 24
Finished Jul 31 04:56:53 PM PDT 24
Peak memory 164852 kb
Host smart-25d99256-e642-4d38-8855-88bb27939eab
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=652362270 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.652362270
Directory /workspace/36.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.1434010973
Short name T62
Test name
Test status
Simulation time 1556110000 ps
CPU time 5.14 seconds
Started Jul 31 04:56:48 PM PDT 24
Finished Jul 31 04:56:59 PM PDT 24
Peak memory 164736 kb
Host smart-90cdd731-46b2-437c-824d-0343b81af01f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1434010973 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.1434010973
Directory /workspace/37.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.860959793
Short name T3
Test name
Test status
Simulation time 1609250000 ps
CPU time 4.97 seconds
Started Jul 31 04:56:42 PM PDT 24
Finished Jul 31 04:56:53 PM PDT 24
Peak memory 164860 kb
Host smart-f2d3b356-c2aa-424b-b4d9-3a3dbc09655c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=860959793 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.860959793
Directory /workspace/38.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.146399796
Short name T46
Test name
Test status
Simulation time 1404990000 ps
CPU time 3.72 seconds
Started Jul 31 04:56:46 PM PDT 24
Finished Jul 31 04:56:55 PM PDT 24
Peak memory 164324 kb
Host smart-090682da-15a9-484c-8bbd-38a76607f9d8
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=146399796 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.146399796
Directory /workspace/39.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.3740834365
Short name T44
Test name
Test status
Simulation time 1341730000 ps
CPU time 3.54 seconds
Started Jul 31 04:56:39 PM PDT 24
Finished Jul 31 04:56:46 PM PDT 24
Peak memory 164708 kb
Host smart-22d0bfcd-afb6-42bc-9425-990a089463b5
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3740834365 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.3740834365
Directory /workspace/4.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.1613620530
Short name T37
Test name
Test status
Simulation time 1274530000 ps
CPU time 3.7 seconds
Started Jul 31 04:56:47 PM PDT 24
Finished Jul 31 04:56:55 PM PDT 24
Peak memory 164812 kb
Host smart-cbc8ce6b-5db0-47e5-91d6-d21554d0025a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1613620530 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.1613620530
Directory /workspace/40.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.1795371090
Short name T41
Test name
Test status
Simulation time 1577310000 ps
CPU time 4.19 seconds
Started Jul 31 04:56:48 PM PDT 24
Finished Jul 31 04:56:57 PM PDT 24
Peak memory 164324 kb
Host smart-3bb08923-fe65-4da8-b8c8-9edd7c777094
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1795371090 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.1795371090
Directory /workspace/41.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.2386784828
Short name T1
Test name
Test status
Simulation time 1274810000 ps
CPU time 4 seconds
Started Jul 31 04:56:45 PM PDT 24
Finished Jul 31 04:56:53 PM PDT 24
Peak memory 164688 kb
Host smart-145fd180-7bd2-4b56-800b-2c3b5c438106
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2386784828 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.2386784828
Directory /workspace/42.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.2350245747
Short name T67
Test name
Test status
Simulation time 1510990000 ps
CPU time 4.78 seconds
Started Jul 31 04:56:46 PM PDT 24
Finished Jul 31 04:56:57 PM PDT 24
Peak memory 164760 kb
Host smart-328fc59a-7ec9-4c2a-8217-85f22671196d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2350245747 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.2350245747
Directory /workspace/43.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.565012466
Short name T65
Test name
Test status
Simulation time 1466250000 ps
CPU time 5.32 seconds
Started Jul 31 04:56:49 PM PDT 24
Finished Jul 31 04:57:00 PM PDT 24
Peak memory 164800 kb
Host smart-85af43e4-cccb-4116-a813-2d86a29b8c92
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=565012466 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.565012466
Directory /workspace/44.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.3914209571
Short name T8
Test name
Test status
Simulation time 1426130000 ps
CPU time 4.97 seconds
Started Jul 31 04:56:47 PM PDT 24
Finished Jul 31 04:56:58 PM PDT 24
Peak memory 164768 kb
Host smart-1f532c3b-7c77-4466-a5cf-e3fe186da4dc
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3914209571 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.3914209571
Directory /workspace/45.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.2472906346
Short name T7
Test name
Test status
Simulation time 1430270000 ps
CPU time 4.92 seconds
Started Jul 31 04:56:47 PM PDT 24
Finished Jul 31 04:56:58 PM PDT 24
Peak memory 164776 kb
Host smart-44949c69-ad43-4346-a16c-16bc0bf2961d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2472906346 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.2472906346
Directory /workspace/46.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.1753319636
Short name T48
Test name
Test status
Simulation time 1318750000 ps
CPU time 2.88 seconds
Started Jul 31 04:56:42 PM PDT 24
Finished Jul 31 04:56:49 PM PDT 24
Peak memory 164820 kb
Host smart-d78caf3a-fe5d-44a2-b105-3ff0407df82a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1753319636 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.1753319636
Directory /workspace/47.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.2110232111
Short name T70
Test name
Test status
Simulation time 1516750000 ps
CPU time 4.54 seconds
Started Jul 31 04:56:45 PM PDT 24
Finished Jul 31 04:56:55 PM PDT 24
Peak memory 164688 kb
Host smart-5a23a481-b710-45f0-91db-f5a09b641afe
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2110232111 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.2110232111
Directory /workspace/48.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.4083411241
Short name T53
Test name
Test status
Simulation time 1435630000 ps
CPU time 3.8 seconds
Started Jul 31 04:56:46 PM PDT 24
Finished Jul 31 04:56:54 PM PDT 24
Peak memory 164860 kb
Host smart-cf777ba2-e134-44cb-aa03-5039aa173aa0
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4083411241 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.4083411241
Directory /workspace/49.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.974506698
Short name T57
Test name
Test status
Simulation time 1324410000 ps
CPU time 3.72 seconds
Started Jul 31 04:56:42 PM PDT 24
Finished Jul 31 04:56:50 PM PDT 24
Peak memory 164776 kb
Host smart-03b7822a-ca51-4ad5-8dfa-7ecf0cc6ca64
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=974506698 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.974506698
Directory /workspace/5.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.3884422685
Short name T63
Test name
Test status
Simulation time 1471370000 ps
CPU time 4.93 seconds
Started Jul 31 04:56:36 PM PDT 24
Finished Jul 31 04:56:47 PM PDT 24
Peak memory 164768 kb
Host smart-c8d694e1-0d9e-4628-aee0-036a755348cf
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3884422685 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.3884422685
Directory /workspace/6.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.2266748816
Short name T13
Test name
Test status
Simulation time 1411650000 ps
CPU time 4.45 seconds
Started Jul 31 04:56:38 PM PDT 24
Finished Jul 31 04:56:48 PM PDT 24
Peak memory 164764 kb
Host smart-df0eb476-ebaa-4c7e-a89f-e51f154fcf67
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2266748816 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.2266748816
Directory /workspace/7.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.2041288567
Short name T39
Test name
Test status
Simulation time 1560410000 ps
CPU time 3.87 seconds
Started Jul 31 04:56:38 PM PDT 24
Finished Jul 31 04:56:47 PM PDT 24
Peak memory 164708 kb
Host smart-a01e3509-e6ba-4cdd-a856-811818aaa1cf
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2041288567 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.2041288567
Directory /workspace/8.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.2028995270
Short name T61
Test name
Test status
Simulation time 1498210000 ps
CPU time 5.11 seconds
Started Jul 31 04:56:38 PM PDT 24
Finished Jul 31 04:56:49 PM PDT 24
Peak memory 164752 kb
Host smart-90ca966b-5e74-4d80-873f-03e36422c408
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2028995270 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.2028995270
Directory /workspace/9.prim_lfsr_gal_smoke/latest
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