Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.31 100.00 96.55 100.00 100.00 95.00


Total tests in report: 200
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
87.31 87.31 100.00 100.00 96.55 96.55 100.00 100.00 100.00 100.00 40.00 40.00 /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.670792648
96.81 9.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 87.50 47.50 /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.1039257803
98.31 1.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 95.00 7.50 /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.797521749

Tests that do not contribute to grading

Name
/workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.1228404052
/workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.2511139573
/workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.3427551215
/workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.1634995895
/workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.3665877599
/workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.2856259330
/workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.1022491222
/workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.2786757200
/workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.2227752828
/workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.2604134063
/workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.3744947652
/workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.3328644881
/workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.1058471288
/workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.3464609747
/workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.2511079978
/workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.2839801172
/workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.2859614180
/workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.1924938475
/workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.113108987
/workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.3955430829
/workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.1887543114
/workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.3061049532
/workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.2196304375
/workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.2140895598
/workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.2175313694
/workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.3829866428
/workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.3244556132
/workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.1661257751
/workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.2551156425
/workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.2017527190
/workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.664267531
/workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.185849990
/workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.4241192290
/workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.1326961767
/workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.3115979872
/workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.578125625
/workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.719262026
/workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.636885994
/workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.993638743
/workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.1770138843
/workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.1740908430
/workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.2808113514
/workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.3888317975
/workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.3983102628
/workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.3829017160
/workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.3652008322
/workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.1742327324
/workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1692442944
/workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.2291356501
/workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.3414245135
/workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.924278384
/workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.41287584
/workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.2976195670
/workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.2623038146
/workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.3260754398
/workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.3966959925
/workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.3575348066
/workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.355999440
/workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.1126040954
/workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.1720135427
/workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.844712237
/workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.3187720729
/workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.2315390912
/workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.1502916994
/workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.1008774033
/workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.2854230450
/workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.3147651223
/workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.1011133803
/workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.4256979662
/workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.969655180
/workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.270351294
/workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.568628958
/workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.922487962
/workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.3595949252
/workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.4097430346
/workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.4014921870
/workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.728401843
/workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.3871825480
/workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.1674296997
/workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.4083528427
/workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3890166665
/workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.3730893440
/workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.10845397
/workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.3202068234
/workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.2761734780
/workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.2998660533
/workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.616177006
/workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.1955604953
/workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.3419832167
/workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.424566634
/workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.1389003560
/workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1189757861
/workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.1619064889
/workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.2139942954
/workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.2984945171
/workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.2517553624
/workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.3407871691
/workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.277327227
/workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.3118067412
/workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.3059709879
/workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.3826389702
/workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.3146749027
/workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.1225387018
/workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.576168
/workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.1446753101
/workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.2762549216
/workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.2728075122
/workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.3096114918
/workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.4061972297
/workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.3143983688
/workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.2696035915
/workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.2249720505
/workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3044616808
/workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.496696868
/workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.576100491
/workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.1092293646
/workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.3860709387
/workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.3925237024
/workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.754020368
/workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.2671674241
/workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.4136217979
/workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.3441205986
/workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.3428156453
/workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.122027989
/workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.2726394596
/workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.378786543
/workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.1344162791
/workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.3316341358
/workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.1449521217
/workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.904802066
/workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.2440542949
/workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.1420672839
/workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.2641463488
/workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.3969274646
/workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.1119703443
/workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.451128744
/workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.3880134990
/workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.3923261631
/workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.1476620148
/workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.3170386142
/workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.226037480
/workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.3665502105
/workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.2690255277
/workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.2297640666
/workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.2137691709
/workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.3347906678
/workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1003914972
/workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.332853529
/workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.2309164443
/workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.2152959783
/workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.3990286626
/workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.2526653847
/workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.3192393321
/workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.432133378
/workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.517916772
/workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.2158287356
/workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.967453905
/workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.180873295
/workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.2833636856
/workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.3453571316
/workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.3964224948
/workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.690167862
/workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.1059992486
/workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.2881058988
/workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.1593330228
/workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.2898335819
/workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.438300011
/workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.3783157693
/workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.238169759
/workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.2837318312
/workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.4013707072
/workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.564590489
/workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.2470701730
/workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.2003459098
/workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.2356755471
/workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.3041623673
/workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.1084775998
/workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.523421409
/workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.3310216828
/workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.4142911032
/workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.3440993110
/workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.807861253
/workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.1573111617
/workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.3182349984
/workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.2067986942
/workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.326104708
/workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.106155336
/workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.1425874412
/workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.1007344482
/workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.2043389181
/workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.58581137
/workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.44285333
/workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.4126999985
/workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.4248418987
/workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.1793620152
/workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.2079036375
/workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.2912863616



Total test records in report: 200
tests.html | tests1.html | tests2.html | tests3.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.3440993110 Aug 01 04:23:02 PM PDT 24 Aug 01 04:23:13 PM PDT 24 1558830000 ps
T2 /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.4248418987 Aug 01 04:17:47 PM PDT 24 Aug 01 04:17:57 PM PDT 24 1384250000 ps
T3 /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.3041623673 Aug 01 04:22:30 PM PDT 24 Aug 01 04:22:40 PM PDT 24 1530870000 ps
T7 /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.1007344482 Aug 01 04:23:02 PM PDT 24 Aug 01 04:23:12 PM PDT 24 1503590000 ps
T8 /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.1084775998 Aug 01 04:22:31 PM PDT 24 Aug 01 04:22:38 PM PDT 24 1126750000 ps
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T137 /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.2690255277 Aug 01 04:22:37 PM PDT 24 Aug 01 04:22:46 PM PDT 24 1513910000 ps
T138 /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.3665502105 Aug 01 04:20:57 PM PDT 24 Aug 01 04:21:10 PM PDT 24 1550870000 ps
T139 /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.3441205986 Aug 01 04:17:45 PM PDT 24 Aug 01 04:17:57 PM PDT 24 1520430000 ps
T140 /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.1476620148 Aug 01 04:24:15 PM PDT 24 Aug 01 04:24:24 PM PDT 24 1408490000 ps
T141 /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.1420672839 Aug 01 04:22:42 PM PDT 24 Aug 01 04:22:52 PM PDT 24 1482330000 ps
T142 /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.332853529 Aug 01 04:17:45 PM PDT 24 Aug 01 04:17:53 PM PDT 24 1320030000 ps
T143 /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.2728075122 Aug 01 04:20:19 PM PDT 24 Aug 01 04:20:28 PM PDT 24 1438430000 ps
T144 /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.451128744 Aug 01 04:22:32 PM PDT 24 Aug 01 04:22:40 PM PDT 24 1465410000 ps
T145 /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.3925237024 Aug 01 04:22:53 PM PDT 24 Aug 01 04:23:01 PM PDT 24 1394710000 ps
T146 /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.576100491 Aug 01 04:22:42 PM PDT 24 Aug 01 04:22:50 PM PDT 24 1423350000 ps
T147 /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.2726394596 Aug 01 04:22:33 PM PDT 24 Aug 01 04:22:41 PM PDT 24 1508670000 ps
T148 /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.3096114918 Aug 01 04:19:39 PM PDT 24 Aug 01 04:19:46 PM PDT 24 1227190000 ps
T149 /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.4061972297 Aug 01 04:17:52 PM PDT 24 Aug 01 04:18:02 PM PDT 24 1397430000 ps
T150 /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.3143983688 Aug 01 04:17:45 PM PDT 24 Aug 01 04:17:52 PM PDT 24 1176710000 ps
T151 /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.3860709387 Aug 01 04:18:19 PM PDT 24 Aug 01 04:18:28 PM PDT 24 1337330000 ps
T152 /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.3347906678 Aug 01 04:17:46 PM PDT 24 Aug 01 04:17:54 PM PDT 24 1299950000 ps
T153 /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.4136217979 Aug 01 04:22:47 PM PDT 24 Aug 01 04:22:52 PM PDT 24 1292550000 ps
T154 /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1003914972 Aug 01 04:17:37 PM PDT 24 Aug 01 04:17:45 PM PDT 24 1332450000 ps
T155 /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.3146749027 Aug 01 04:17:36 PM PDT 24 Aug 01 04:17:43 PM PDT 24 1494630000 ps
T156 /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.754020368 Aug 01 04:22:43 PM PDT 24 Aug 01 04:22:51 PM PDT 24 1440250000 ps
T157 /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.496696868 Aug 01 04:22:25 PM PDT 24 Aug 01 04:22:33 PM PDT 24 1439750000 ps
T158 /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.226037480 Aug 01 04:22:24 PM PDT 24 Aug 01 04:22:34 PM PDT 24 1564790000 ps
T159 /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.3059709879 Aug 01 04:17:38 PM PDT 24 Aug 01 04:17:47 PM PDT 24 1228970000 ps
T160 /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.2762549216 Aug 01 04:17:52 PM PDT 24 Aug 01 04:18:02 PM PDT 24 1337650000 ps
T21 /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3890166665 Aug 01 04:18:37 PM PDT 24 Aug 01 04:54:48 PM PDT 24 336933110000 ps
T22 /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.355999440 Aug 01 04:23:08 PM PDT 24 Aug 01 04:51:34 PM PDT 24 336469970000 ps
T23 /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.3187720729 Aug 01 04:22:59 PM PDT 24 Aug 01 04:49:19 PM PDT 24 336532990000 ps
T24 /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.3871825480 Aug 01 04:20:07 PM PDT 24 Aug 01 04:49:42 PM PDT 24 337069590000 ps
T25 /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.1389003560 Aug 01 04:22:56 PM PDT 24 Aug 01 04:50:34 PM PDT 24 336886110000 ps
T26 /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.797521749 Aug 01 04:17:37 PM PDT 24 Aug 01 04:44:50 PM PDT 24 336773410000 ps
T27 /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.3575348066 Aug 01 04:23:04 PM PDT 24 Aug 01 04:54:13 PM PDT 24 337099670000 ps
T28 /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.568628958 Aug 01 04:17:37 PM PDT 24 Aug 01 04:45:25 PM PDT 24 337056610000 ps
T29 /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.924278384 Aug 01 04:22:19 PM PDT 24 Aug 01 04:48:23 PM PDT 24 336718250000 ps
T30 /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.2623038146 Aug 01 04:22:24 PM PDT 24 Aug 01 04:49:17 PM PDT 24 336360970000 ps
T161 /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.41287584 Aug 01 04:22:37 PM PDT 24 Aug 01 04:48:01 PM PDT 24 336590690000 ps
T162 /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.1502916994 Aug 01 04:22:49 PM PDT 24 Aug 01 04:48:29 PM PDT 24 336360810000 ps
T163 /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.4014921870 Aug 01 04:23:02 PM PDT 24 Aug 01 04:48:11 PM PDT 24 336931570000 ps
T164 /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.277327227 Aug 01 04:17:47 PM PDT 24 Aug 01 04:49:23 PM PDT 24 336925550000 ps
T165 /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.3147651223 Aug 01 04:22:29 PM PDT 24 Aug 01 04:47:15 PM PDT 24 336602910000 ps
T166 /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.2998660533 Aug 01 04:22:49 PM PDT 24 Aug 01 04:51:32 PM PDT 24 336511210000 ps
T167 /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.4256979662 Aug 01 04:22:53 PM PDT 24 Aug 01 04:47:43 PM PDT 24 336945630000 ps
T168 /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.3260754398 Aug 01 04:22:32 PM PDT 24 Aug 01 04:46:56 PM PDT 24 336722930000 ps
T169 /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.2976195670 Aug 01 04:22:23 PM PDT 24 Aug 01 04:47:03 PM PDT 24 337043110000 ps
T170 /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.844712237 Aug 01 04:17:47 PM PDT 24 Aug 01 04:49:44 PM PDT 24 336935510000 ps
T171 /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.616177006 Aug 01 04:23:04 PM PDT 24 Aug 01 04:50:05 PM PDT 24 336799510000 ps
T172 /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.1720135427 Aug 01 04:22:54 PM PDT 24 Aug 01 04:54:01 PM PDT 24 336866010000 ps
T173 /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.270351294 Aug 01 04:22:33 PM PDT 24 Aug 01 04:48:14 PM PDT 24 337027550000 ps
T174 /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.4097430346 Aug 01 04:22:57 PM PDT 24 Aug 01 04:49:14 PM PDT 24 336476450000 ps
T175 /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.10845397 Aug 01 04:17:45 PM PDT 24 Aug 01 04:51:30 PM PDT 24 336395710000 ps
T176 /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.728401843 Aug 01 04:22:49 PM PDT 24 Aug 01 04:51:46 PM PDT 24 336598150000 ps
T177 /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.1619064889 Aug 01 04:22:42 PM PDT 24 Aug 01 04:57:18 PM PDT 24 336364030000 ps
T178 /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.2854230450 Aug 01 04:20:37 PM PDT 24 Aug 01 04:56:51 PM PDT 24 336987670000 ps
T179 /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.4083528427 Aug 01 04:23:13 PM PDT 24 Aug 01 04:52:19 PM PDT 24 336450070000 ps
T180 /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.1126040954 Aug 01 04:23:04 PM PDT 24 Aug 01 04:51:22 PM PDT 24 336514270000 ps
T181 /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.1008774033 Aug 01 04:22:25 PM PDT 24 Aug 01 04:49:37 PM PDT 24 336812530000 ps
T182 /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.3419832167 Aug 01 04:22:49 PM PDT 24 Aug 01 04:52:40 PM PDT 24 336400570000 ps
T183 /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.3595949252 Aug 01 04:22:39 PM PDT 24 Aug 01 04:53:01 PM PDT 24 336778490000 ps
T184 /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.1674296997 Aug 01 04:23:14 PM PDT 24 Aug 01 04:54:28 PM PDT 24 336833730000 ps
T185 /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.3202068234 Aug 01 04:22:27 PM PDT 24 Aug 01 04:47:44 PM PDT 24 336681490000 ps
T186 /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.2315390912 Aug 01 04:22:54 PM PDT 24 Aug 01 04:53:59 PM PDT 24 336324870000 ps
T187 /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.969655180 Aug 01 04:19:37 PM PDT 24 Aug 01 04:52:55 PM PDT 24 336455610000 ps
T188 /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.3407871691 Aug 01 04:17:38 PM PDT 24 Aug 01 04:44:53 PM PDT 24 336794870000 ps
T189 /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.1011133803 Aug 01 04:19:16 PM PDT 24 Aug 01 04:48:40 PM PDT 24 336620490000 ps
T190 /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.3966959925 Aug 01 04:23:04 PM PDT 24 Aug 01 04:54:48 PM PDT 24 336966110000 ps
T191 /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.2517553624 Aug 01 04:17:45 PM PDT 24 Aug 01 04:59:21 PM PDT 24 336878970000 ps
T192 /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.2984945171 Aug 01 04:17:47 PM PDT 24 Aug 01 04:48:36 PM PDT 24 337042950000 ps
T193 /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1189757861 Aug 01 04:22:42 PM PDT 24 Aug 01 04:58:28 PM PDT 24 336671290000 ps
T194 /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.1955604953 Aug 01 04:22:58 PM PDT 24 Aug 01 04:52:17 PM PDT 24 337013810000 ps
T195 /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.2761734780 Aug 01 04:22:37 PM PDT 24 Aug 01 04:49:00 PM PDT 24 336646250000 ps
T196 /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.922487962 Aug 01 04:22:35 PM PDT 24 Aug 01 04:48:22 PM PDT 24 336834890000 ps
T197 /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.3730893440 Aug 01 04:22:41 PM PDT 24 Aug 01 04:57:05 PM PDT 24 336846730000 ps
T198 /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.2139942954 Aug 01 04:17:45 PM PDT 24 Aug 01 04:59:22 PM PDT 24 336295530000 ps
T199 /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.3414245135 Aug 01 04:17:48 PM PDT 24 Aug 01 04:48:46 PM PDT 24 336577810000 ps
T200 /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.424566634 Aug 01 04:22:55 PM PDT 24 Aug 01 04:59:54 PM PDT 24 336447810000 ps

Test location /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.670792648
Short name T13
Test name
Test status
Simulation time 1548910000 ps
CPU time 4.71 seconds
Started Aug 01 04:17:48 PM PDT 24
Finished Aug 01 04:17:58 PM PDT 24
Peak memory 166372 kb
Host smart-fb6ab7f0-9819-46a6-962d-85faac3ceaf4
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=670792648 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.670792648
Directory /workspace/2.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.1039257803
Short name T6
Test name
Test status
Simulation time 336879150000 ps
CPU time 776.24 seconds
Started Aug 01 04:18:22 PM PDT 24
Finished Aug 01 04:50:05 PM PDT 24
Peak memory 160440 kb
Host smart-1ac64441-9ea2-4955-add6-a4cd9b731b9e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1039257803 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.1039257803
Directory /workspace/13.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.797521749
Short name T26
Test name
Test status
Simulation time 336773410000 ps
CPU time 656.24 seconds
Started Aug 01 04:17:37 PM PDT 24
Finished Aug 01 04:44:50 PM PDT 24
Peak memory 160076 kb
Host smart-351bf18f-1298-4be3-b59b-fb948ca93ece
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=797521749 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.797521749
Directory /workspace/1.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.1228404052
Short name T80
Test name
Test status
Simulation time 336733270000 ps
CPU time 625.55 seconds
Started Aug 01 04:23:09 PM PDT 24
Finished Aug 01 04:48:57 PM PDT 24
Peak memory 160612 kb
Host smart-c718b1d4-e1c7-4026-8552-0fe99e62877f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1228404052 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.1228404052
Directory /workspace/0.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.2511139573
Short name T91
Test name
Test status
Simulation time 337011130000 ps
CPU time 655.04 seconds
Started Aug 01 04:22:39 PM PDT 24
Finished Aug 01 04:49:57 PM PDT 24
Peak memory 160408 kb
Host smart-03ed9b6d-08b3-4e3e-a09b-42fe958ecd43
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2511139573 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.2511139573
Directory /workspace/1.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.3427551215
Short name T87
Test name
Test status
Simulation time 337060830000 ps
CPU time 579.16 seconds
Started Aug 01 04:22:49 PM PDT 24
Finished Aug 01 04:46:34 PM PDT 24
Peak memory 160452 kb
Host smart-14fe26e1-c98d-43db-a321-450284146354
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3427551215 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.3427551215
Directory /workspace/10.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.1634995895
Short name T106
Test name
Test status
Simulation time 336369570000 ps
CPU time 840.13 seconds
Started Aug 01 04:22:49 PM PDT 24
Finished Aug 01 04:58:47 PM PDT 24
Peak memory 160364 kb
Host smart-82482675-cb66-4ff3-8b04-dba04ff81371
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1634995895 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.1634995895
Directory /workspace/11.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.3665877599
Short name T109
Test name
Test status
Simulation time 336937730000 ps
CPU time 980.99 seconds
Started Aug 01 04:18:11 PM PDT 24
Finished Aug 01 04:59:57 PM PDT 24
Peak memory 160540 kb
Host smart-91df6ede-aff6-4b59-b0cd-b0525c4c6415
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3665877599 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.3665877599
Directory /workspace/12.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.2856259330
Short name T110
Test name
Test status
Simulation time 337057750000 ps
CPU time 865.55 seconds
Started Aug 01 04:22:39 PM PDT 24
Finished Aug 01 04:59:17 PM PDT 24
Peak memory 159032 kb
Host smart-63e9356f-9b04-4429-8e80-185c16a5b694
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2856259330 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.2856259330
Directory /workspace/14.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.1022491222
Short name T74
Test name
Test status
Simulation time 336817830000 ps
CPU time 650.96 seconds
Started Aug 01 04:22:38 PM PDT 24
Finished Aug 01 04:49:43 PM PDT 24
Peak memory 160332 kb
Host smart-e7a3d9e9-6216-492e-9534-b785aaa13a21
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1022491222 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.1022491222
Directory /workspace/15.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.2786757200
Short name T100
Test name
Test status
Simulation time 337076410000 ps
CPU time 666.01 seconds
Started Aug 01 04:20:56 PM PDT 24
Finished Aug 01 04:48:13 PM PDT 24
Peak memory 160840 kb
Host smart-15152615-70a4-45e8-911b-7719f02537ef
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2786757200 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.2786757200
Directory /workspace/16.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.2227752828
Short name T108
Test name
Test status
Simulation time 336898050000 ps
CPU time 989.79 seconds
Started Aug 01 04:18:23 PM PDT 24
Finished Aug 01 04:59:59 PM PDT 24
Peak memory 160540 kb
Host smart-7b987db2-3199-4b17-ade0-9da4c9c1ee28
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2227752828 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.2227752828
Directory /workspace/17.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.2604134063
Short name T93
Test name
Test status
Simulation time 336372070000 ps
CPU time 675.63 seconds
Started Aug 01 04:18:20 PM PDT 24
Finished Aug 01 04:46:18 PM PDT 24
Peak memory 160664 kb
Host smart-4fa2762e-11f3-445e-b91c-c30011149cc4
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2604134063 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.2604134063
Directory /workspace/18.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.3744947652
Short name T75
Test name
Test status
Simulation time 336794070000 ps
CPU time 857.2 seconds
Started Aug 01 04:22:39 PM PDT 24
Finished Aug 01 04:59:11 PM PDT 24
Peak memory 160252 kb
Host smart-6592ccbc-0cda-4c6d-8ad2-f38e32490991
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3744947652 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.3744947652
Directory /workspace/19.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.3328644881
Short name T92
Test name
Test status
Simulation time 336629150000 ps
CPU time 738.55 seconds
Started Aug 01 04:18:45 PM PDT 24
Finished Aug 01 04:50:31 PM PDT 24
Peak memory 158404 kb
Host smart-5bd34c1d-d7d9-4673-8038-98bddad4a509
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3328644881 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.3328644881
Directory /workspace/2.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.1058471288
Short name T84
Test name
Test status
Simulation time 336548330000 ps
CPU time 792.26 seconds
Started Aug 01 04:18:36 PM PDT 24
Finished Aug 01 04:52:09 PM PDT 24
Peak memory 160852 kb
Host smart-dfab0480-98c0-455d-87dc-442e8ca8a120
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1058471288 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.1058471288
Directory /workspace/20.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.3464609747
Short name T83
Test name
Test status
Simulation time 336779150000 ps
CPU time 660.96 seconds
Started Aug 01 04:22:56 PM PDT 24
Finished Aug 01 04:50:07 PM PDT 24
Peak memory 159588 kb
Host smart-f1c6ebf1-c3d5-4e70-9fea-70b956426f33
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3464609747 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.3464609747
Directory /workspace/21.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.2511079978
Short name T97
Test name
Test status
Simulation time 336818190000 ps
CPU time 891.8 seconds
Started Aug 01 04:21:44 PM PDT 24
Finished Aug 01 04:58:49 PM PDT 24
Peak memory 160740 kb
Host smart-1b049078-a3bf-4153-84d8-57d9e33795e8
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2511079978 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.2511079978
Directory /workspace/22.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.2839801172
Short name T73
Test name
Test status
Simulation time 336588950000 ps
CPU time 729.68 seconds
Started Aug 01 04:23:11 PM PDT 24
Finished Aug 01 04:53:10 PM PDT 24
Peak memory 160376 kb
Host smart-a38da5bc-b08b-42c1-a8e2-9f8851fcba4b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2839801172 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.2839801172
Directory /workspace/23.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.2859614180
Short name T96
Test name
Test status
Simulation time 337058250000 ps
CPU time 702.33 seconds
Started Aug 01 04:22:50 PM PDT 24
Finished Aug 01 04:51:45 PM PDT 24
Peak memory 160256 kb
Host smart-cf09b7d2-417a-4c1b-8372-4fd3e4eb4bdc
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2859614180 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.2859614180
Directory /workspace/24.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.1924938475
Short name T90
Test name
Test status
Simulation time 337113110000 ps
CPU time 755.71 seconds
Started Aug 01 04:18:24 PM PDT 24
Finished Aug 01 04:49:38 PM PDT 24
Peak memory 160440 kb
Host smart-4a0efad2-8940-4013-b3b3-9d17bfe54439
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1924938475 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.1924938475
Directory /workspace/25.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.113108987
Short name T104
Test name
Test status
Simulation time 337034670000 ps
CPU time 728.4 seconds
Started Aug 01 04:22:50 PM PDT 24
Finished Aug 01 04:52:53 PM PDT 24
Peak memory 160232 kb
Host smart-2761f1ae-eed7-433d-b0d8-c10f40292290
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=113108987 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.113108987
Directory /workspace/26.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.3955430829
Short name T103
Test name
Test status
Simulation time 336525590000 ps
CPU time 676.34 seconds
Started Aug 01 04:23:22 PM PDT 24
Finished Aug 01 04:51:22 PM PDT 24
Peak memory 160436 kb
Host smart-27e0930b-a223-42ac-9d19-99bece9f42a0
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3955430829 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.3955430829
Directory /workspace/27.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.1887543114
Short name T15
Test name
Test status
Simulation time 336920670000 ps
CPU time 917.93 seconds
Started Aug 01 04:18:27 PM PDT 24
Finished Aug 01 04:56:33 PM PDT 24
Peak memory 160740 kb
Host smart-04219291-a64c-4ff8-86fb-60405c35e536
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1887543114 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.1887543114
Directory /workspace/28.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.3061049532
Short name T19
Test name
Test status
Simulation time 336470490000 ps
CPU time 678.79 seconds
Started Aug 01 04:23:43 PM PDT 24
Finished Aug 01 04:51:42 PM PDT 24
Peak memory 159336 kb
Host smart-f8767019-ecbd-427c-b2fb-ecd827e20b2b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3061049532 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.3061049532
Directory /workspace/29.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.2196304375
Short name T105
Test name
Test status
Simulation time 336950250000 ps
CPU time 738.8 seconds
Started Aug 01 04:18:45 PM PDT 24
Finished Aug 01 04:50:33 PM PDT 24
Peak memory 158604 kb
Host smart-ac70b5e4-1e13-470e-8981-b55c7516117d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2196304375 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.2196304375
Directory /workspace/3.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.2140895598
Short name T99
Test name
Test status
Simulation time 336538750000 ps
CPU time 782.18 seconds
Started Aug 01 04:23:13 PM PDT 24
Finished Aug 01 04:55:35 PM PDT 24
Peak memory 160368 kb
Host smart-2fc00a28-af7f-4aa3-a07f-e51dbfe0eacd
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2140895598 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.2140895598
Directory /workspace/30.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.2175313694
Short name T101
Test name
Test status
Simulation time 336931530000 ps
CPU time 738.97 seconds
Started Aug 01 04:22:54 PM PDT 24
Finished Aug 01 04:52:48 PM PDT 24
Peak memory 160424 kb
Host smart-e743080b-31cf-4d8f-b139-8f44253dc8f6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2175313694 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.2175313694
Directory /workspace/31.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.3829866428
Short name T72
Test name
Test status
Simulation time 336778870000 ps
CPU time 703.12 seconds
Started Aug 01 04:22:52 PM PDT 24
Finished Aug 01 04:52:04 PM PDT 24
Peak memory 160452 kb
Host smart-8acd24a3-0478-4bd9-a7b3-dcbb3163b12e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3829866428 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.3829866428
Directory /workspace/32.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.3244556132
Short name T77
Test name
Test status
Simulation time 336324970000 ps
CPU time 976.43 seconds
Started Aug 01 04:18:11 PM PDT 24
Finished Aug 01 04:59:45 PM PDT 24
Peak memory 160540 kb
Host smart-9b2ed6c2-ceda-4f2a-bb48-37832401a75a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3244556132 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.3244556132
Directory /workspace/33.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.1661257751
Short name T89
Test name
Test status
Simulation time 336717610000 ps
CPU time 623.73 seconds
Started Aug 01 04:23:08 PM PDT 24
Finished Aug 01 04:48:53 PM PDT 24
Peak memory 159760 kb
Host smart-327824c7-afb0-4bc8-8771-b2c2ec06062a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1661257751 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.1661257751
Directory /workspace/34.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.2551156425
Short name T14
Test name
Test status
Simulation time 337073070000 ps
CPU time 847.56 seconds
Started Aug 01 04:22:39 PM PDT 24
Finished Aug 01 04:59:02 PM PDT 24
Peak memory 158748 kb
Host smart-6884bb0c-f273-4b61-b862-1c8c22ef71d7
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2551156425 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.2551156425
Directory /workspace/35.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.2017527190
Short name T82
Test name
Test status
Simulation time 336354930000 ps
CPU time 726.46 seconds
Started Aug 01 04:23:19 PM PDT 24
Finished Aug 01 04:53:51 PM PDT 24
Peak memory 160224 kb
Host smart-d8d65beb-bec2-4f05-b003-ab9997e2f4d6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2017527190 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.2017527190
Directory /workspace/36.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.664267531
Short name T88
Test name
Test status
Simulation time 336673910000 ps
CPU time 699.85 seconds
Started Aug 01 04:19:18 PM PDT 24
Finished Aug 01 04:48:09 PM PDT 24
Peak memory 160884 kb
Host smart-eb30b23b-2681-4386-a394-44ecec0d8ac6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=664267531 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.664267531
Directory /workspace/37.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.185849990
Short name T102
Test name
Test status
Simulation time 336535190000 ps
CPU time 647.82 seconds
Started Aug 01 04:22:28 PM PDT 24
Finished Aug 01 04:48:56 PM PDT 24
Peak memory 160244 kb
Host smart-aed6ee54-51ae-44fa-b709-fa7507c211bc
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=185849990 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.185849990
Directory /workspace/38.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.4241192290
Short name T20
Test name
Test status
Simulation time 336941150000 ps
CPU time 748.61 seconds
Started Aug 01 04:23:57 PM PDT 24
Finished Aug 01 04:54:46 PM PDT 24
Peak memory 160604 kb
Host smart-acd03ea8-102d-4b90-a152-b206ab814440
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4241192290 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.4241192290
Directory /workspace/39.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.1326961767
Short name T107
Test name
Test status
Simulation time 336563610000 ps
CPU time 731.78 seconds
Started Aug 01 04:18:54 PM PDT 24
Finished Aug 01 04:50:01 PM PDT 24
Peak memory 160236 kb
Host smart-92df1a4b-1efd-44df-8101-ccb39024bcc5
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1326961767 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.1326961767
Directory /workspace/4.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.3115979872
Short name T94
Test name
Test status
Simulation time 336851050000 ps
CPU time 916.67 seconds
Started Aug 01 04:18:27 PM PDT 24
Finished Aug 01 04:56:37 PM PDT 24
Peak memory 160740 kb
Host smart-a299062d-0402-43f8-bcda-0949a870182b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3115979872 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.3115979872
Directory /workspace/40.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.578125625
Short name T95
Test name
Test status
Simulation time 337040010000 ps
CPU time 662.73 seconds
Started Aug 01 04:23:22 PM PDT 24
Finished Aug 01 04:50:43 PM PDT 24
Peak memory 160424 kb
Host smart-6283f45f-8dba-422f-b24b-a3e9c7d4dd28
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=578125625 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.578125625
Directory /workspace/41.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.719262026
Short name T5
Test name
Test status
Simulation time 337117010000 ps
CPU time 717.29 seconds
Started Aug 01 04:23:29 PM PDT 24
Finished Aug 01 04:53:38 PM PDT 24
Peak memory 160400 kb
Host smart-0e25e9f4-d4f2-452d-8828-adb442a5752e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=719262026 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.719262026
Directory /workspace/42.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.636885994
Short name T18
Test name
Test status
Simulation time 336471370000 ps
CPU time 807.71 seconds
Started Aug 01 04:18:35 PM PDT 24
Finished Aug 01 04:51:26 PM PDT 24
Peak memory 160704 kb
Host smart-840a72b0-bd04-4ae7-92f5-3ae3be30a19e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=636885994 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.636885994
Directory /workspace/43.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.993638743
Short name T79
Test name
Test status
Simulation time 336997790000 ps
CPU time 782.68 seconds
Started Aug 01 04:23:13 PM PDT 24
Finished Aug 01 04:55:30 PM PDT 24
Peak memory 160248 kb
Host smart-2644122a-abd6-4941-a8ce-f2a8e55cc0e8
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=993638743 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.993638743
Directory /workspace/44.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.1770138843
Short name T17
Test name
Test status
Simulation time 337103790000 ps
CPU time 609.55 seconds
Started Aug 01 04:23:10 PM PDT 24
Finished Aug 01 04:48:04 PM PDT 24
Peak memory 160268 kb
Host smart-6a7f4692-cb7c-412a-bf11-ac2d44157275
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1770138843 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.1770138843
Directory /workspace/45.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.1740908430
Short name T85
Test name
Test status
Simulation time 337070930000 ps
CPU time 746.33 seconds
Started Aug 01 04:23:24 PM PDT 24
Finished Aug 01 04:53:38 PM PDT 24
Peak memory 160256 kb
Host smart-b5f83024-e44f-4a74-90db-8e676cfe59ac
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1740908430 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.1740908430
Directory /workspace/46.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.2808113514
Short name T71
Test name
Test status
Simulation time 336461350000 ps
CPU time 699.51 seconds
Started Aug 01 04:22:42 PM PDT 24
Finished Aug 01 04:51:29 PM PDT 24
Peak memory 159760 kb
Host smart-a3228b69-38fb-4113-ae82-e7a87999fc3c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2808113514 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.2808113514
Directory /workspace/47.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.3888317975
Short name T16
Test name
Test status
Simulation time 336824630000 ps
CPU time 920.33 seconds
Started Aug 01 04:18:27 PM PDT 24
Finished Aug 01 04:56:38 PM PDT 24
Peak memory 160740 kb
Host smart-2daa0103-b19c-423e-ac24-70cb361ce9b4
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3888317975 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.3888317975
Directory /workspace/48.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.3983102628
Short name T76
Test name
Test status
Simulation time 336433910000 ps
CPU time 792.62 seconds
Started Aug 01 04:18:25 PM PDT 24
Finished Aug 01 04:52:00 PM PDT 24
Peak memory 160856 kb
Host smart-d7dfd622-75d2-4c7e-bc11-8041a156dd8a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3983102628 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.3983102628
Directory /workspace/49.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.3829017160
Short name T86
Test name
Test status
Simulation time 336876650000 ps
CPU time 758.12 seconds
Started Aug 01 04:18:45 PM PDT 24
Finished Aug 01 04:50:58 PM PDT 24
Peak memory 159188 kb
Host smart-aa693f9f-4f72-4d6e-8580-be8a0ecb860e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3829017160 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.3829017160
Directory /workspace/5.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.3652008322
Short name T98
Test name
Test status
Simulation time 337040690000 ps
CPU time 675.7 seconds
Started Aug 01 04:22:37 PM PDT 24
Finished Aug 01 04:50:33 PM PDT 24
Peak memory 159592 kb
Host smart-db092c82-3b40-45fd-893c-8a0ea984146d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3652008322 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.3652008322
Directory /workspace/6.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.1742327324
Short name T78
Test name
Test status
Simulation time 336565310000 ps
CPU time 982.96 seconds
Started Aug 01 04:18:01 PM PDT 24
Finished Aug 01 04:59:29 PM PDT 24
Peak memory 160536 kb
Host smart-4f09c9b7-ed5b-4fa7-833f-0876444583e0
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1742327324 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.1742327324
Directory /workspace/7.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1692442944
Short name T81
Test name
Test status
Simulation time 337100490000 ps
CPU time 855.07 seconds
Started Aug 01 04:22:39 PM PDT 24
Finished Aug 01 04:59:11 PM PDT 24
Peak memory 158716 kb
Host smart-846b7949-12f8-4686-a4df-c6d33466148b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1692442944 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.1692442944
Directory /workspace/8.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.2291356501
Short name T4
Test name
Test status
Simulation time 336918550000 ps
CPU time 857.38 seconds
Started Aug 01 04:22:48 PM PDT 24
Finished Aug 01 04:59:00 PM PDT 24
Peak memory 160360 kb
Host smart-d5edfb76-9c9f-47fa-882d-8db01df84f25
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2291356501 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.2291356501
Directory /workspace/9.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.3414245135
Short name T199
Test name
Test status
Simulation time 336577810000 ps
CPU time 740.97 seconds
Started Aug 01 04:17:48 PM PDT 24
Finished Aug 01 04:48:46 PM PDT 24
Peak memory 160716 kb
Host smart-b7cbe1d7-a2e8-490a-a545-97287babd729
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3414245135 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.3414245135
Directory /workspace/0.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.924278384
Short name T29
Test name
Test status
Simulation time 336718250000 ps
CPU time 640.96 seconds
Started Aug 01 04:22:19 PM PDT 24
Finished Aug 01 04:48:23 PM PDT 24
Peak memory 159152 kb
Host smart-77616754-9846-41bd-aee7-8ce1720fd614
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=924278384 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.924278384
Directory /workspace/10.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.41287584
Short name T161
Test name
Test status
Simulation time 336590690000 ps
CPU time 614.7 seconds
Started Aug 01 04:22:37 PM PDT 24
Finished Aug 01 04:48:01 PM PDT 24
Peak memory 159588 kb
Host smart-715f372d-24a6-4ede-ae36-184aaacc3e7b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=41287584 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.41287584
Directory /workspace/11.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.2976195670
Short name T169
Test name
Test status
Simulation time 337043110000 ps
CPU time 594.76 seconds
Started Aug 01 04:22:23 PM PDT 24
Finished Aug 01 04:47:03 PM PDT 24
Peak memory 159760 kb
Host smart-e393ddbb-f8a1-49ff-afda-17972140727a
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2976195670 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.2976195670
Directory /workspace/12.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.2623038146
Short name T30
Test name
Test status
Simulation time 336360970000 ps
CPU time 654.8 seconds
Started Aug 01 04:22:24 PM PDT 24
Finished Aug 01 04:49:17 PM PDT 24
Peak memory 160372 kb
Host smart-f311e52b-583d-48f7-a01e-229dcec76325
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2623038146 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.2623038146
Directory /workspace/13.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.3260754398
Short name T168
Test name
Test status
Simulation time 336722930000 ps
CPU time 595.39 seconds
Started Aug 01 04:22:32 PM PDT 24
Finished Aug 01 04:46:56 PM PDT 24
Peak memory 160596 kb
Host smart-f06d2c8a-bdfd-4303-bc10-600a74b98a6d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3260754398 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.3260754398
Directory /workspace/14.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.3966959925
Short name T190
Test name
Test status
Simulation time 336966110000 ps
CPU time 753.41 seconds
Started Aug 01 04:23:04 PM PDT 24
Finished Aug 01 04:54:48 PM PDT 24
Peak memory 160432 kb
Host smart-812d7161-c9b9-4ab6-9359-1333511db400
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3966959925 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.3966959925
Directory /workspace/15.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.3575348066
Short name T27
Test name
Test status
Simulation time 337099670000 ps
CPU time 739.54 seconds
Started Aug 01 04:23:04 PM PDT 24
Finished Aug 01 04:54:13 PM PDT 24
Peak memory 160432 kb
Host smart-71813a3d-ff0c-41a7-810d-410250886f31
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3575348066 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.3575348066
Directory /workspace/16.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.355999440
Short name T22
Test name
Test status
Simulation time 336469970000 ps
CPU time 695.37 seconds
Started Aug 01 04:23:08 PM PDT 24
Finished Aug 01 04:51:34 PM PDT 24
Peak memory 160608 kb
Host smart-bf7c6f1b-f89b-4689-a8d4-5f40ea9fc5d1
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=355999440 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.355999440
Directory /workspace/17.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.1126040954
Short name T180
Test name
Test status
Simulation time 336514270000 ps
CPU time 691.94 seconds
Started Aug 01 04:23:04 PM PDT 24
Finished Aug 01 04:51:22 PM PDT 24
Peak memory 160616 kb
Host smart-e0b9d182-6cdd-49c3-a4c8-407e433925fc
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1126040954 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.1126040954
Directory /workspace/18.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.1720135427
Short name T172
Test name
Test status
Simulation time 336866010000 ps
CPU time 732.6 seconds
Started Aug 01 04:22:54 PM PDT 24
Finished Aug 01 04:54:01 PM PDT 24
Peak memory 159328 kb
Host smart-62c86c48-3211-48e2-aa94-7c28be2378b6
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1720135427 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.1720135427
Directory /workspace/19.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.844712237
Short name T170
Test name
Test status
Simulation time 336935510000 ps
CPU time 770.13 seconds
Started Aug 01 04:17:47 PM PDT 24
Finished Aug 01 04:49:44 PM PDT 24
Peak memory 160660 kb
Host smart-f1083e07-6222-4eb7-aad3-2bae58c651f9
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=844712237 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.844712237
Directory /workspace/2.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.3187720729
Short name T23
Test name
Test status
Simulation time 336532990000 ps
CPU time 636.3 seconds
Started Aug 01 04:22:59 PM PDT 24
Finished Aug 01 04:49:19 PM PDT 24
Peak memory 160456 kb
Host smart-8320d6fb-b2b9-4ef7-a0c6-b580304d62b8
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3187720729 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.3187720729
Directory /workspace/20.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.2315390912
Short name T186
Test name
Test status
Simulation time 336324870000 ps
CPU time 734.98 seconds
Started Aug 01 04:22:54 PM PDT 24
Finished Aug 01 04:53:59 PM PDT 24
Peak memory 159288 kb
Host smart-30236898-647b-47ce-8b1d-8e418e6232c6
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2315390912 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.2315390912
Directory /workspace/21.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.1502916994
Short name T162
Test name
Test status
Simulation time 336360810000 ps
CPU time 626.16 seconds
Started Aug 01 04:22:49 PM PDT 24
Finished Aug 01 04:48:29 PM PDT 24
Peak memory 159764 kb
Host smart-97a24e79-7d66-4f10-80f1-c9b5cefb7447
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1502916994 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.1502916994
Directory /workspace/22.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.1008774033
Short name T181
Test name
Test status
Simulation time 336812530000 ps
CPU time 664.86 seconds
Started Aug 01 04:22:25 PM PDT 24
Finished Aug 01 04:49:37 PM PDT 24
Peak memory 159864 kb
Host smart-bd16e1e2-9adc-415c-83c3-2e4a145c0801
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1008774033 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.1008774033
Directory /workspace/23.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.2854230450
Short name T178
Test name
Test status
Simulation time 336987670000 ps
CPU time 873.6 seconds
Started Aug 01 04:20:37 PM PDT 24
Finished Aug 01 04:56:51 PM PDT 24
Peak memory 160744 kb
Host smart-dfba3983-752f-4c3e-9fd3-b9b38aa89f78
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2854230450 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.2854230450
Directory /workspace/24.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.3147651223
Short name T165
Test name
Test status
Simulation time 336602910000 ps
CPU time 601.15 seconds
Started Aug 01 04:22:29 PM PDT 24
Finished Aug 01 04:47:15 PM PDT 24
Peak memory 159524 kb
Host smart-855e7f39-08e5-464f-bed8-c916d4a24144
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3147651223 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.3147651223
Directory /workspace/25.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.1011133803
Short name T189
Test name
Test status
Simulation time 336620490000 ps
CPU time 731.3 seconds
Started Aug 01 04:19:16 PM PDT 24
Finished Aug 01 04:48:40 PM PDT 24
Peak memory 160756 kb
Host smart-8008ef0f-9f29-47c2-87cd-18b7019c781b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1011133803 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.1011133803
Directory /workspace/26.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.4256979662
Short name T167
Test name
Test status
Simulation time 336945630000 ps
CPU time 603.41 seconds
Started Aug 01 04:22:53 PM PDT 24
Finished Aug 01 04:47:43 PM PDT 24
Peak memory 159748 kb
Host smart-81dbe46d-3917-4b8a-ad5d-a74573cc676a
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4256979662 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.4256979662
Directory /workspace/27.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.969655180
Short name T187
Test name
Test status
Simulation time 336455610000 ps
CPU time 787.93 seconds
Started Aug 01 04:19:37 PM PDT 24
Finished Aug 01 04:52:55 PM PDT 24
Peak memory 160844 kb
Host smart-d74c4412-2c1b-4c86-a5f7-fe6f962f0332
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=969655180 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.969655180
Directory /workspace/28.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.270351294
Short name T173
Test name
Test status
Simulation time 337027550000 ps
CPU time 632.81 seconds
Started Aug 01 04:22:33 PM PDT 24
Finished Aug 01 04:48:14 PM PDT 24
Peak memory 160264 kb
Host smart-25786786-4db3-41df-a138-9fcd4e0756be
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=270351294 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.270351294
Directory /workspace/29.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.568628958
Short name T28
Test name
Test status
Simulation time 337056610000 ps
CPU time 674.01 seconds
Started Aug 01 04:17:37 PM PDT 24
Finished Aug 01 04:45:25 PM PDT 24
Peak memory 160428 kb
Host smart-24a84a3e-e67f-4abf-b500-ec67b55b3a4c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=568628958 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.568628958
Directory /workspace/3.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.922487962
Short name T196
Test name
Test status
Simulation time 336834890000 ps
CPU time 630.64 seconds
Started Aug 01 04:22:35 PM PDT 24
Finished Aug 01 04:48:22 PM PDT 24
Peak memory 160448 kb
Host smart-ee6b6b52-ebf7-4a28-add7-77b4fb7d4e0e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=922487962 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.922487962
Directory /workspace/30.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.3595949252
Short name T183
Test name
Test status
Simulation time 336778490000 ps
CPU time 746.62 seconds
Started Aug 01 04:22:39 PM PDT 24
Finished Aug 01 04:53:01 PM PDT 24
Peak memory 160592 kb
Host smart-7fed8d36-bfbb-44a7-b796-e154fb3cda99
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3595949252 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.3595949252
Directory /workspace/31.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.4097430346
Short name T174
Test name
Test status
Simulation time 336476450000 ps
CPU time 643.32 seconds
Started Aug 01 04:22:57 PM PDT 24
Finished Aug 01 04:49:14 PM PDT 24
Peak memory 160460 kb
Host smart-cd6657f0-8556-45d0-9728-d624e8b2edd2
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4097430346 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.4097430346
Directory /workspace/32.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.4014921870
Short name T163
Test name
Test status
Simulation time 336931570000 ps
CPU time 605.06 seconds
Started Aug 01 04:23:02 PM PDT 24
Finished Aug 01 04:48:11 PM PDT 24
Peak memory 160444 kb
Host smart-83e63038-a5f6-470a-821b-7c569c6e46da
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4014921870 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.4014921870
Directory /workspace/33.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.728401843
Short name T176
Test name
Test status
Simulation time 336598150000 ps
CPU time 694.08 seconds
Started Aug 01 04:22:49 PM PDT 24
Finished Aug 01 04:51:46 PM PDT 24
Peak memory 160616 kb
Host smart-3c7c1753-d535-455a-b900-c4259e6720af
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=728401843 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.728401843
Directory /workspace/34.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.3871825480
Short name T24
Test name
Test status
Simulation time 337069590000 ps
CPU time 724.06 seconds
Started Aug 01 04:20:07 PM PDT 24
Finished Aug 01 04:49:42 PM PDT 24
Peak memory 160744 kb
Host smart-47922c23-a0cf-4a04-8a0a-95201d311c82
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3871825480 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.3871825480
Directory /workspace/35.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.1674296997
Short name T184
Test name
Test status
Simulation time 336833730000 ps
CPU time 764.2 seconds
Started Aug 01 04:23:14 PM PDT 24
Finished Aug 01 04:54:28 PM PDT 24
Peak memory 160460 kb
Host smart-53860bbc-14d0-47eb-80e9-0f2494ac605c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1674296997 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.1674296997
Directory /workspace/36.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.4083528427
Short name T179
Test name
Test status
Simulation time 336450070000 ps
CPU time 709.85 seconds
Started Aug 01 04:23:13 PM PDT 24
Finished Aug 01 04:52:19 PM PDT 24
Peak memory 160212 kb
Host smart-aadeb71b-564d-41c8-a9ae-8f206e366135
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4083528427 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.4083528427
Directory /workspace/37.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3890166665
Short name T21
Test name
Test status
Simulation time 336933110000 ps
CPU time 861.4 seconds
Started Aug 01 04:18:37 PM PDT 24
Finished Aug 01 04:54:48 PM PDT 24
Peak memory 160744 kb
Host smart-d9feaa86-775a-4037-863e-45cd5cef67a7
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3890166665 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.3890166665
Directory /workspace/38.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.3730893440
Short name T197
Test name
Test status
Simulation time 336846730000 ps
CPU time 805.97 seconds
Started Aug 01 04:22:41 PM PDT 24
Finished Aug 01 04:57:05 PM PDT 24
Peak memory 159296 kb
Host smart-ab85b256-b3c5-4004-8fe4-eab2440a6e0e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3730893440 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.3730893440
Directory /workspace/39.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.10845397
Short name T175
Test name
Test status
Simulation time 336395710000 ps
CPU time 798.75 seconds
Started Aug 01 04:17:45 PM PDT 24
Finished Aug 01 04:51:30 PM PDT 24
Peak memory 160764 kb
Host smart-5d53bdd9-55f9-4a36-bb32-27486faae1e9
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=10845397 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.10845397
Directory /workspace/4.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.3202068234
Short name T185
Test name
Test status
Simulation time 336681490000 ps
CPU time 616.64 seconds
Started Aug 01 04:22:27 PM PDT 24
Finished Aug 01 04:47:44 PM PDT 24
Peak memory 159796 kb
Host smart-0683b90a-4fdc-4bee-b57e-f8352c2eb561
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3202068234 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.3202068234
Directory /workspace/40.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.2761734780
Short name T195
Test name
Test status
Simulation time 336646250000 ps
CPU time 645.93 seconds
Started Aug 01 04:22:37 PM PDT 24
Finished Aug 01 04:49:00 PM PDT 24
Peak memory 159508 kb
Host smart-476aab4a-7de3-4eab-b260-4b8770a8912e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2761734780 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.2761734780
Directory /workspace/41.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.2998660533
Short name T166
Test name
Test status
Simulation time 336511210000 ps
CPU time 694.82 seconds
Started Aug 01 04:22:49 PM PDT 24
Finished Aug 01 04:51:32 PM PDT 24
Peak memory 160640 kb
Host smart-b72db423-aca5-4b7f-b05f-1749ebeaf7c7
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2998660533 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.2998660533
Directory /workspace/42.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.616177006
Short name T171
Test name
Test status
Simulation time 336799510000 ps
CPU time 660.97 seconds
Started Aug 01 04:23:04 PM PDT 24
Finished Aug 01 04:50:05 PM PDT 24
Peak memory 160600 kb
Host smart-95a54e10-040c-45f9-8c4c-4234c7f36c8c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=616177006 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.616177006
Directory /workspace/43.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.1955604953
Short name T194
Test name
Test status
Simulation time 337013810000 ps
CPU time 717.44 seconds
Started Aug 01 04:22:58 PM PDT 24
Finished Aug 01 04:52:17 PM PDT 24
Peak memory 160632 kb
Host smart-2b940ecc-84b4-4446-a7c2-82da27a1d91f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1955604953 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.1955604953
Directory /workspace/44.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.3419832167
Short name T182
Test name
Test status
Simulation time 336400570000 ps
CPU time 720.14 seconds
Started Aug 01 04:22:49 PM PDT 24
Finished Aug 01 04:52:40 PM PDT 24
Peak memory 160616 kb
Host smart-60a45cd6-5de0-44d8-9fb8-03b02dd0766a
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3419832167 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.3419832167
Directory /workspace/45.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.424566634
Short name T200
Test name
Test status
Simulation time 336447810000 ps
CPU time 906.69 seconds
Started Aug 01 04:22:55 PM PDT 24
Finished Aug 01 04:59:54 PM PDT 24
Peak memory 160448 kb
Host smart-0974b171-2393-493d-a788-9303b880879a
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=424566634 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.424566634
Directory /workspace/46.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.1389003560
Short name T25
Test name
Test status
Simulation time 336886110000 ps
CPU time 673.38 seconds
Started Aug 01 04:22:56 PM PDT 24
Finished Aug 01 04:50:34 PM PDT 24
Peak memory 160632 kb
Host smart-ebd6590e-ba51-42c7-b399-b0e0e84f26d7
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1389003560 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.1389003560
Directory /workspace/47.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1189757861
Short name T193
Test name
Test status
Simulation time 336671290000 ps
CPU time 855.65 seconds
Started Aug 01 04:22:42 PM PDT 24
Finished Aug 01 04:58:28 PM PDT 24
Peak memory 160180 kb
Host smart-fd62f563-9582-462f-96fb-34c075967189
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1189757861 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.1189757861
Directory /workspace/48.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.1619064889
Short name T177
Test name
Test status
Simulation time 336364030000 ps
CPU time 819.13 seconds
Started Aug 01 04:22:42 PM PDT 24
Finished Aug 01 04:57:18 PM PDT 24
Peak memory 160244 kb
Host smart-e987caf9-ab47-44b2-909a-8697448d0638
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1619064889 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.1619064889
Directory /workspace/49.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.2139942954
Short name T198
Test name
Test status
Simulation time 336295530000 ps
CPU time 970.02 seconds
Started Aug 01 04:17:45 PM PDT 24
Finished Aug 01 04:59:22 PM PDT 24
Peak memory 160300 kb
Host smart-1c5ae642-8ebe-48a3-ab4e-78dcc94e45a1
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2139942954 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.2139942954
Directory /workspace/5.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.2984945171
Short name T192
Test name
Test status
Simulation time 337042950000 ps
CPU time 745.12 seconds
Started Aug 01 04:17:47 PM PDT 24
Finished Aug 01 04:48:36 PM PDT 24
Peak memory 160672 kb
Host smart-ca75bc07-2e4d-46bf-856a-6fe3424468ca
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2984945171 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.2984945171
Directory /workspace/6.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.2517553624
Short name T191
Test name
Test status
Simulation time 336878970000 ps
CPU time 978.96 seconds
Started Aug 01 04:17:45 PM PDT 24
Finished Aug 01 04:59:21 PM PDT 24
Peak memory 159448 kb
Host smart-b3c8bb97-de7b-4bb8-a600-01f4169ebfa1
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2517553624 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.2517553624
Directory /workspace/7.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.3407871691
Short name T188
Test name
Test status
Simulation time 336794870000 ps
CPU time 648.96 seconds
Started Aug 01 04:17:38 PM PDT 24
Finished Aug 01 04:44:53 PM PDT 24
Peak memory 160076 kb
Host smart-234a9345-ad36-4436-ba5d-311c9589bfb6
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3407871691 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.3407871691
Directory /workspace/8.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.277327227
Short name T164
Test name
Test status
Simulation time 336925550000 ps
CPU time 765.59 seconds
Started Aug 01 04:17:47 PM PDT 24
Finished Aug 01 04:49:23 PM PDT 24
Peak memory 160660 kb
Host smart-bb381279-44e7-47f0-b347-f33e8adbc1db
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=277327227 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.277327227
Directory /workspace/9.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.3118067412
Short name T118
Test name
Test status
Simulation time 1282150000 ps
CPU time 3.92 seconds
Started Aug 01 04:18:45 PM PDT 24
Finished Aug 01 04:18:54 PM PDT 24
Peak memory 163716 kb
Host smart-fdb83966-21f4-43dd-ad75-cecbb29b9209
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3118067412 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.3118067412
Directory /workspace/0.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.3059709879
Short name T159
Test name
Test status
Simulation time 1228970000 ps
CPU time 3.95 seconds
Started Aug 01 04:17:38 PM PDT 24
Finished Aug 01 04:17:47 PM PDT 24
Peak memory 164004 kb
Host smart-858ffe46-0d72-4f38-821c-7f11fc5f5909
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3059709879 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.3059709879
Directory /workspace/1.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.3826389702
Short name T114
Test name
Test status
Simulation time 1516070000 ps
CPU time 4.99 seconds
Started Aug 01 04:17:52 PM PDT 24
Finished Aug 01 04:18:03 PM PDT 24
Peak memory 164868 kb
Host smart-0a20fe1d-b36b-4cda-959d-c2e0da346321
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3826389702 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.3826389702
Directory /workspace/10.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.3146749027
Short name T155
Test name
Test status
Simulation time 1494630000 ps
CPU time 3.46 seconds
Started Aug 01 04:17:36 PM PDT 24
Finished Aug 01 04:17:43 PM PDT 24
Peak memory 163564 kb
Host smart-e0a5637e-5dee-41e3-84cf-1d84929e8364
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3146749027 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.3146749027
Directory /workspace/11.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.1225387018
Short name T121
Test name
Test status
Simulation time 1393410000 ps
CPU time 4.25 seconds
Started Aug 01 04:17:45 PM PDT 24
Finished Aug 01 04:17:55 PM PDT 24
Peak memory 164828 kb
Host smart-96c34ec2-79c0-4f9d-95cf-6059517d3c16
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1225387018 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.1225387018
Directory /workspace/12.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.576168
Short name T134
Test name
Test status
Simulation time 1456590000 ps
CPU time 5.2 seconds
Started Aug 01 04:17:45 PM PDT 24
Finished Aug 01 04:17:57 PM PDT 24
Peak memory 162944 kb
Host smart-6fde1729-d826-4691-b9d3-791f6cbe2926
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=576168 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.576168
Directory /workspace/13.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.1446753101
Short name T123
Test name
Test status
Simulation time 1466710000 ps
CPU time 4.66 seconds
Started Aug 01 04:17:52 PM PDT 24
Finished Aug 01 04:18:02 PM PDT 24
Peak memory 164868 kb
Host smart-3bb9a083-2f76-404a-8acf-c92806954b0a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1446753101 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.1446753101
Directory /workspace/14.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.2762549216
Short name T160
Test name
Test status
Simulation time 1337650000 ps
CPU time 4.36 seconds
Started Aug 01 04:17:52 PM PDT 24
Finished Aug 01 04:18:02 PM PDT 24
Peak memory 164828 kb
Host smart-7ee43438-36c0-4686-a694-96cf09cacb26
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2762549216 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.2762549216
Directory /workspace/15.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.2728075122
Short name T143
Test name
Test status
Simulation time 1438430000 ps
CPU time 4.13 seconds
Started Aug 01 04:20:19 PM PDT 24
Finished Aug 01 04:20:28 PM PDT 24
Peak memory 164876 kb
Host smart-8b32c0bd-0bf0-4bb3-991a-8c54e8a369d2
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2728075122 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.2728075122
Directory /workspace/16.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.3096114918
Short name T148
Test name
Test status
Simulation time 1227190000 ps
CPU time 3.52 seconds
Started Aug 01 04:19:39 PM PDT 24
Finished Aug 01 04:19:46 PM PDT 24
Peak memory 164840 kb
Host smart-c8ddd971-b29e-492c-8b70-eac2213c8496
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3096114918 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.3096114918
Directory /workspace/17.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.4061972297
Short name T149
Test name
Test status
Simulation time 1397430000 ps
CPU time 4.57 seconds
Started Aug 01 04:17:52 PM PDT 24
Finished Aug 01 04:18:02 PM PDT 24
Peak memory 164868 kb
Host smart-0eec4924-a6ac-4c07-b0fd-bfbe63b1c44f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4061972297 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.4061972297
Directory /workspace/18.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.3143983688
Short name T150
Test name
Test status
Simulation time 1176710000 ps
CPU time 3.21 seconds
Started Aug 01 04:17:45 PM PDT 24
Finished Aug 01 04:17:52 PM PDT 24
Peak memory 164868 kb
Host smart-34328d0d-db5c-4a75-8790-a892879c51c0
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3143983688 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.3143983688
Directory /workspace/19.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.2696035915
Short name T133
Test name
Test status
Simulation time 1218490000 ps
CPU time 4.28 seconds
Started Aug 01 04:17:45 PM PDT 24
Finished Aug 01 04:17:55 PM PDT 24
Peak memory 164216 kb
Host smart-68a42aed-05ac-442b-8f54-2b994133c5ae
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2696035915 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.2696035915
Directory /workspace/2.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.2249720505
Short name T125
Test name
Test status
Simulation time 1336850000 ps
CPU time 3.61 seconds
Started Aug 01 04:22:57 PM PDT 24
Finished Aug 01 04:23:05 PM PDT 24
Peak memory 164596 kb
Host smart-a2a55763-f592-41dd-8ce0-2a57df39f01a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2249720505 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.2249720505
Directory /workspace/20.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3044616808
Short name T129
Test name
Test status
Simulation time 1479750000 ps
CPU time 3.51 seconds
Started Aug 01 04:23:02 PM PDT 24
Finished Aug 01 04:23:10 PM PDT 24
Peak memory 164564 kb
Host smart-4ebbe6fd-42c4-402b-854a-a8acf2a56420
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3044616808 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.3044616808
Directory /workspace/21.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.496696868
Short name T157
Test name
Test status
Simulation time 1439750000 ps
CPU time 3.35 seconds
Started Aug 01 04:22:25 PM PDT 24
Finished Aug 01 04:22:33 PM PDT 24
Peak memory 163320 kb
Host smart-d9701362-fdbc-4400-977c-71ed9e104558
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=496696868 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.496696868
Directory /workspace/22.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.576100491
Short name T146
Test name
Test status
Simulation time 1423350000 ps
CPU time 3.41 seconds
Started Aug 01 04:22:42 PM PDT 24
Finished Aug 01 04:22:50 PM PDT 24
Peak memory 163308 kb
Host smart-f37333c2-0dbc-43e8-85be-d375f6c0c569
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=576100491 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.576100491
Directory /workspace/23.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.1092293646
Short name T124
Test name
Test status
Simulation time 1496190000 ps
CPU time 3.66 seconds
Started Aug 01 04:22:39 PM PDT 24
Finished Aug 01 04:22:48 PM PDT 24
Peak memory 164656 kb
Host smart-20e5541b-2e6b-45ae-88d7-fabae76caea8
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1092293646 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.1092293646
Directory /workspace/24.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.3860709387
Short name T151
Test name
Test status
Simulation time 1337330000 ps
CPU time 4.17 seconds
Started Aug 01 04:18:19 PM PDT 24
Finished Aug 01 04:18:28 PM PDT 24
Peak memory 164012 kb
Host smart-e62e0eb2-5918-4623-9338-774ab44b7315
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3860709387 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.3860709387
Directory /workspace/25.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.3925237024
Short name T145
Test name
Test status
Simulation time 1394710000 ps
CPU time 3.75 seconds
Started Aug 01 04:22:53 PM PDT 24
Finished Aug 01 04:23:01 PM PDT 24
Peak memory 164556 kb
Host smart-aec4163f-27f9-4b46-989f-828187e59b84
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3925237024 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.3925237024
Directory /workspace/26.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.754020368
Short name T156
Test name
Test status
Simulation time 1440250000 ps
CPU time 3.51 seconds
Started Aug 01 04:22:43 PM PDT 24
Finished Aug 01 04:22:51 PM PDT 24
Peak memory 163604 kb
Host smart-df65b3be-a30e-4a8d-b433-7250f3227254
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=754020368 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.754020368
Directory /workspace/27.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.2671674241
Short name T115
Test name
Test status
Simulation time 1486570000 ps
CPU time 3.21 seconds
Started Aug 01 04:22:26 PM PDT 24
Finished Aug 01 04:22:33 PM PDT 24
Peak memory 164376 kb
Host smart-d7eebebe-8f3d-4acb-a494-b1707231f3c6
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2671674241 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.2671674241
Directory /workspace/28.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.4136217979
Short name T153
Test name
Test status
Simulation time 1292550000 ps
CPU time 2.53 seconds
Started Aug 01 04:22:47 PM PDT 24
Finished Aug 01 04:22:52 PM PDT 24
Peak memory 164320 kb
Host smart-bf6b45e3-3540-443d-8cb1-b3633913d6b6
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4136217979 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.4136217979
Directory /workspace/29.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.3441205986
Short name T139
Test name
Test status
Simulation time 1520430000 ps
CPU time 4.88 seconds
Started Aug 01 04:17:45 PM PDT 24
Finished Aug 01 04:17:57 PM PDT 24
Peak memory 164232 kb
Host smart-aa004a17-2a8d-4c5a-a902-638f85fda554
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3441205986 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.3441205986
Directory /workspace/3.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.3428156453
Short name T131
Test name
Test status
Simulation time 1561970000 ps
CPU time 3.52 seconds
Started Aug 01 04:22:50 PM PDT 24
Finished Aug 01 04:22:58 PM PDT 24
Peak memory 164704 kb
Host smart-be2d3103-4006-4620-80f3-d1948120db90
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3428156453 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.3428156453
Directory /workspace/30.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.122027989
Short name T127
Test name
Test status
Simulation time 1573510000 ps
CPU time 4.7 seconds
Started Aug 01 04:20:03 PM PDT 24
Finished Aug 01 04:20:13 PM PDT 24
Peak memory 164908 kb
Host smart-81919404-0840-4584-b8fa-4ce6a7e2dde4
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=122027989 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.122027989
Directory /workspace/31.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.2726394596
Short name T147
Test name
Test status
Simulation time 1508670000 ps
CPU time 3.31 seconds
Started Aug 01 04:22:33 PM PDT 24
Finished Aug 01 04:22:41 PM PDT 24
Peak memory 164392 kb
Host smart-9784f4f1-42c7-48dc-a562-e06d4a37f61d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2726394596 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.2726394596
Directory /workspace/32.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.378786543
Short name T111
Test name
Test status
Simulation time 1501250000 ps
CPU time 6.32 seconds
Started Aug 01 04:20:12 PM PDT 24
Finished Aug 01 04:20:25 PM PDT 24
Peak memory 164708 kb
Host smart-657716c7-f20e-4a45-803c-50782e330f77
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=378786543 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.378786543
Directory /workspace/33.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.1344162791
Short name T128
Test name
Test status
Simulation time 1462710000 ps
CPU time 3.47 seconds
Started Aug 01 04:22:43 PM PDT 24
Finished Aug 01 04:22:51 PM PDT 24
Peak memory 164280 kb
Host smart-09335a19-1192-47e2-a896-a811006d4311
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1344162791 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.1344162791
Directory /workspace/34.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.3316341358
Short name T117
Test name
Test status
Simulation time 1444450000 ps
CPU time 5.61 seconds
Started Aug 01 04:18:33 PM PDT 24
Finished Aug 01 04:18:46 PM PDT 24
Peak memory 164464 kb
Host smart-b7e7801c-9cbb-4c3a-99f1-1d71a4961a72
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3316341358 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.3316341358
Directory /workspace/35.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.1449521217
Short name T136
Test name
Test status
Simulation time 1424450000 ps
CPU time 4.04 seconds
Started Aug 01 04:22:41 PM PDT 24
Finished Aug 01 04:22:50 PM PDT 24
Peak memory 162736 kb
Host smart-19a72286-2fac-4e90-a31e-de237284dbee
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1449521217 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.1449521217
Directory /workspace/36.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.904802066
Short name T116
Test name
Test status
Simulation time 1430470000 ps
CPU time 3.81 seconds
Started Aug 01 04:22:28 PM PDT 24
Finished Aug 01 04:22:37 PM PDT 24
Peak memory 164012 kb
Host smart-24aea307-9d69-4abe-8982-e1c477c5a196
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=904802066 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.904802066
Directory /workspace/37.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.2440542949
Short name T113
Test name
Test status
Simulation time 1414370000 ps
CPU time 4.13 seconds
Started Aug 01 04:18:24 PM PDT 24
Finished Aug 01 04:18:34 PM PDT 24
Peak memory 164912 kb
Host smart-54a51e68-2c12-4535-ab36-653e3a8e411b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2440542949 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.2440542949
Directory /workspace/38.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.1420672839
Short name T141
Test name
Test status
Simulation time 1482330000 ps
CPU time 4.66 seconds
Started Aug 01 04:22:42 PM PDT 24
Finished Aug 01 04:22:52 PM PDT 24
Peak memory 164260 kb
Host smart-7864b39d-fb0a-4250-a9eb-b0e23e26b3af
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1420672839 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.1420672839
Directory /workspace/39.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.2641463488
Short name T126
Test name
Test status
Simulation time 1664090000 ps
CPU time 5.48 seconds
Started Aug 01 04:17:51 PM PDT 24
Finished Aug 01 04:18:04 PM PDT 24
Peak memory 164868 kb
Host smart-d90a164c-9ee6-44ee-8d6c-5894954ce3bd
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2641463488 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.2641463488
Directory /workspace/4.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.3969274646
Short name T130
Test name
Test status
Simulation time 1139250000 ps
CPU time 3.74 seconds
Started Aug 01 04:19:53 PM PDT 24
Finished Aug 01 04:20:01 PM PDT 24
Peak memory 164828 kb
Host smart-0e1105fb-02b7-4b5e-a54d-ff5d38a26ba5
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3969274646 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.3969274646
Directory /workspace/40.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.1119703443
Short name T120
Test name
Test status
Simulation time 1494970000 ps
CPU time 3.6 seconds
Started Aug 01 04:23:44 PM PDT 24
Finished Aug 01 04:23:52 PM PDT 24
Peak memory 165952 kb
Host smart-7f543d84-50f3-4c54-a1b5-2212e380b38c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1119703443 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.1119703443
Directory /workspace/41.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.451128744
Short name T144
Test name
Test status
Simulation time 1465410000 ps
CPU time 3.25 seconds
Started Aug 01 04:22:32 PM PDT 24
Finished Aug 01 04:22:40 PM PDT 24
Peak memory 164508 kb
Host smart-b5352e50-8c09-49a2-94df-538ff66ce3ab
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=451128744 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.451128744
Directory /workspace/42.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.3880134990
Short name T122
Test name
Test status
Simulation time 1079250000 ps
CPU time 3.29 seconds
Started Aug 01 04:22:41 PM PDT 24
Finished Aug 01 04:22:49 PM PDT 24
Peak memory 163416 kb
Host smart-fc0f20eb-0c5a-44e6-8ef8-cd529e6eaf2c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3880134990 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.3880134990
Directory /workspace/43.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.3923261631
Short name T112
Test name
Test status
Simulation time 1483550000 ps
CPU time 4.53 seconds
Started Aug 01 04:22:55 PM PDT 24
Finished Aug 01 04:23:06 PM PDT 24
Peak memory 164448 kb
Host smart-47b96da3-259e-487e-ad7b-32770a046840
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3923261631 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.3923261631
Directory /workspace/44.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.1476620148
Short name T140
Test name
Test status
Simulation time 1408490000 ps
CPU time 3.79 seconds
Started Aug 01 04:24:15 PM PDT 24
Finished Aug 01 04:24:24 PM PDT 24
Peak memory 162248 kb
Host smart-30e3aca9-5c82-4482-997b-4c0fed3d8d03
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1476620148 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.1476620148
Directory /workspace/45.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.3170386142
Short name T135
Test name
Test status
Simulation time 1552890000 ps
CPU time 3.83 seconds
Started Aug 01 04:22:19 PM PDT 24
Finished Aug 01 04:22:28 PM PDT 24
Peak memory 162688 kb
Host smart-55bd27ed-6a6d-40fe-b25d-55fc9f68101d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3170386142 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.3170386142
Directory /workspace/46.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.226037480
Short name T158
Test name
Test status
Simulation time 1564790000 ps
CPU time 4.46 seconds
Started Aug 01 04:22:24 PM PDT 24
Finished Aug 01 04:22:34 PM PDT 24
Peak memory 164532 kb
Host smart-fb2eb289-8856-418c-8ed3-09bf9e9d5c99
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=226037480 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.226037480
Directory /workspace/47.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.3665502105
Short name T138
Test name
Test status
Simulation time 1550870000 ps
CPU time 5.34 seconds
Started Aug 01 04:20:57 PM PDT 24
Finished Aug 01 04:21:10 PM PDT 24
Peak memory 165020 kb
Host smart-471a2339-2437-48a8-9589-78cb74199adb
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3665502105 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.3665502105
Directory /workspace/48.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.2690255277
Short name T137
Test name
Test status
Simulation time 1513910000 ps
CPU time 3.96 seconds
Started Aug 01 04:22:37 PM PDT 24
Finished Aug 01 04:22:46 PM PDT 24
Peak memory 164656 kb
Host smart-7ab974f2-b490-407a-a704-fb13695ab350
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2690255277 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.2690255277
Directory /workspace/49.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.2297640666
Short name T119
Test name
Test status
Simulation time 1478170000 ps
CPU time 4.18 seconds
Started Aug 01 04:17:45 PM PDT 24
Finished Aug 01 04:17:55 PM PDT 24
Peak memory 164464 kb
Host smart-431f5afe-2dc6-46ed-9ee1-58b11f70fd08
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2297640666 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.2297640666
Directory /workspace/5.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.2137691709
Short name T132
Test name
Test status
Simulation time 1425210000 ps
CPU time 4 seconds
Started Aug 01 04:17:45 PM PDT 24
Finished Aug 01 04:17:54 PM PDT 24
Peak memory 164508 kb
Host smart-6fba9ceb-dbba-4172-917e-8219d6242b75
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2137691709 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.2137691709
Directory /workspace/6.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.3347906678
Short name T152
Test name
Test status
Simulation time 1299950000 ps
CPU time 3.41 seconds
Started Aug 01 04:17:46 PM PDT 24
Finished Aug 01 04:17:54 PM PDT 24
Peak memory 164856 kb
Host smart-e51fbaa8-d9d0-4204-8be0-2f072b032c52
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3347906678 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.3347906678
Directory /workspace/7.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1003914972
Short name T154
Test name
Test status
Simulation time 1332450000 ps
CPU time 3.88 seconds
Started Aug 01 04:17:37 PM PDT 24
Finished Aug 01 04:17:45 PM PDT 24
Peak memory 164900 kb
Host smart-26897580-4341-49cb-b6a3-f5b42ef1b4b5
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1003914972 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.1003914972
Directory /workspace/8.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.332853529
Short name T142
Test name
Test status
Simulation time 1320030000 ps
CPU time 3.59 seconds
Started Aug 01 04:17:45 PM PDT 24
Finished Aug 01 04:17:53 PM PDT 24
Peak memory 164808 kb
Host smart-6e6852e9-6c56-4323-858a-ee390c4eb820
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=332853529 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.332853529
Directory /workspace/9.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.2309164443
Short name T62
Test name
Test status
Simulation time 1543750000 ps
CPU time 4.25 seconds
Started Aug 01 04:17:45 PM PDT 24
Finished Aug 01 04:17:55 PM PDT 24
Peak memory 164648 kb
Host smart-f366f8a4-4ff3-435f-8ef0-d78663f6371f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2309164443 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.2309164443
Directory /workspace/0.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.2152959783
Short name T60
Test name
Test status
Simulation time 1384730000 ps
CPU time 4.5 seconds
Started Aug 01 04:17:47 PM PDT 24
Finished Aug 01 04:17:58 PM PDT 24
Peak memory 164296 kb
Host smart-323f64d3-3d6e-4fa4-a31f-779ccb8c7e8a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2152959783 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.2152959783
Directory /workspace/1.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.3990286626
Short name T51
Test name
Test status
Simulation time 1387410000 ps
CPU time 4.49 seconds
Started Aug 01 04:18:55 PM PDT 24
Finished Aug 01 04:19:05 PM PDT 24
Peak memory 164364 kb
Host smart-56d33fab-ef22-45d2-8f3a-b0b720f5f307
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3990286626 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.3990286626
Directory /workspace/10.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.2526653847
Short name T57
Test name
Test status
Simulation time 1535950000 ps
CPU time 4.29 seconds
Started Aug 01 04:19:53 PM PDT 24
Finished Aug 01 04:20:04 PM PDT 24
Peak memory 164776 kb
Host smart-b9548409-3d65-466c-b1de-5206822f86a2
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2526653847 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.2526653847
Directory /workspace/11.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.3192393321
Short name T63
Test name
Test status
Simulation time 1571710000 ps
CPU time 5.43 seconds
Started Aug 01 04:18:17 PM PDT 24
Finished Aug 01 04:18:29 PM PDT 24
Peak memory 165020 kb
Host smart-1e7f8b94-be9f-4d67-8a89-f835c17b4229
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3192393321 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.3192393321
Directory /workspace/12.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.432133378
Short name T34
Test name
Test status
Simulation time 1656410000 ps
CPU time 5.86 seconds
Started Aug 01 04:19:56 PM PDT 24
Finished Aug 01 04:20:08 PM PDT 24
Peak memory 164908 kb
Host smart-dd35ad91-4565-42c0-8801-8fd7dba47129
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=432133378 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.432133378
Directory /workspace/13.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.517916772
Short name T67
Test name
Test status
Simulation time 1491770000 ps
CPU time 5.26 seconds
Started Aug 01 04:18:17 PM PDT 24
Finished Aug 01 04:18:29 PM PDT 24
Peak memory 165024 kb
Host smart-bb3f9a74-593d-4b05-9c9c-e29e0f10cfcd
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=517916772 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.517916772
Directory /workspace/14.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.2158287356
Short name T56
Test name
Test status
Simulation time 1571290000 ps
CPU time 4.44 seconds
Started Aug 01 04:22:37 PM PDT 24
Finished Aug 01 04:22:48 PM PDT 24
Peak memory 163724 kb
Host smart-02162fe0-8950-42e2-b0df-6478e31907a4
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2158287356 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.2158287356
Directory /workspace/15.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.967453905
Short name T54
Test name
Test status
Simulation time 1198350000 ps
CPU time 3.27 seconds
Started Aug 01 04:23:09 PM PDT 24
Finished Aug 01 04:23:16 PM PDT 24
Peak memory 164756 kb
Host smart-42d629bf-8446-42cb-8c51-175e93175f7a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=967453905 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.967453905
Directory /workspace/16.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.180873295
Short name T45
Test name
Test status
Simulation time 1415110000 ps
CPU time 4.37 seconds
Started Aug 01 04:18:54 PM PDT 24
Finished Aug 01 04:19:04 PM PDT 24
Peak memory 164200 kb
Host smart-3211ef30-3a24-42c3-b78f-073fd3d4995a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=180873295 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.180873295
Directory /workspace/17.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.2833636856
Short name T41
Test name
Test status
Simulation time 1491770000 ps
CPU time 4.44 seconds
Started Aug 01 04:18:45 PM PDT 24
Finished Aug 01 04:18:55 PM PDT 24
Peak memory 162408 kb
Host smart-7b86a237-3fbe-44d7-8c1d-5e7df7ea6b9f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2833636856 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.2833636856
Directory /workspace/18.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.3453571316
Short name T50
Test name
Test status
Simulation time 1486910000 ps
CPU time 3.29 seconds
Started Aug 01 04:22:58 PM PDT 24
Finished Aug 01 04:23:06 PM PDT 24
Peak memory 164580 kb
Host smart-1c92eaaf-177b-4d2d-9033-04032ca0c99a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3453571316 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.3453571316
Directory /workspace/19.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.3964224948
Short name T69
Test name
Test status
Simulation time 1122910000 ps
CPU time 3.21 seconds
Started Aug 01 04:22:50 PM PDT 24
Finished Aug 01 04:22:57 PM PDT 24
Peak memory 164480 kb
Host smart-c1c66e53-45e1-4672-8716-35f79354433d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3964224948 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.3964224948
Directory /workspace/20.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.690167862
Short name T44
Test name
Test status
Simulation time 1521350000 ps
CPU time 3.69 seconds
Started Aug 01 04:23:43 PM PDT 24
Finished Aug 01 04:23:52 PM PDT 24
Peak memory 163040 kb
Host smart-7c3aac64-ac72-487f-9dd3-40c5c8eb62be
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=690167862 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.690167862
Directory /workspace/21.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.1059992486
Short name T31
Test name
Test status
Simulation time 1472330000 ps
CPU time 3.41 seconds
Started Aug 01 04:22:54 PM PDT 24
Finished Aug 01 04:23:02 PM PDT 24
Peak memory 164764 kb
Host smart-70d899c0-c40b-45c7-b413-80b9f63f18ee
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1059992486 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.1059992486
Directory /workspace/22.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.2881058988
Short name T49
Test name
Test status
Simulation time 1405070000 ps
CPU time 4.12 seconds
Started Aug 01 04:22:43 PM PDT 24
Finished Aug 01 04:22:52 PM PDT 24
Peak memory 166336 kb
Host smart-0666b8e9-e8c0-4325-86ba-2eb5488c1332
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2881058988 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.2881058988
Directory /workspace/23.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.1593330228
Short name T33
Test name
Test status
Simulation time 1391530000 ps
CPU time 3.83 seconds
Started Aug 01 04:24:15 PM PDT 24
Finished Aug 01 04:24:24 PM PDT 24
Peak memory 162936 kb
Host smart-d417bd82-d78b-4f24-91b4-7b03a160dff1
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1593330228 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.1593330228
Directory /workspace/24.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.2898335819
Short name T35
Test name
Test status
Simulation time 1582130000 ps
CPU time 3.53 seconds
Started Aug 01 04:22:58 PM PDT 24
Finished Aug 01 04:23:06 PM PDT 24
Peak memory 164520 kb
Host smart-8da26df1-e782-4b0a-a7d0-395799abe8b0
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2898335819 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.2898335819
Directory /workspace/25.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.438300011
Short name T9
Test name
Test status
Simulation time 1600350000 ps
CPU time 3.74 seconds
Started Aug 01 04:22:35 PM PDT 24
Finished Aug 01 04:22:43 PM PDT 24
Peak memory 164732 kb
Host smart-7a5cb2a5-2d73-4050-bf84-ae66d05d3279
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=438300011 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.438300011
Directory /workspace/26.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.3783157693
Short name T10
Test name
Test status
Simulation time 1485950000 ps
CPU time 4.77 seconds
Started Aug 01 04:22:55 PM PDT 24
Finished Aug 01 04:23:06 PM PDT 24
Peak memory 164448 kb
Host smart-f7f69859-0bab-45f3-8224-70ddc6bea11c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3783157693 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.3783157693
Directory /workspace/27.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.238169759
Short name T12
Test name
Test status
Simulation time 1468470000 ps
CPU time 3.22 seconds
Started Aug 01 04:22:37 PM PDT 24
Finished Aug 01 04:22:44 PM PDT 24
Peak memory 164744 kb
Host smart-c2b880ed-f1c1-4622-95c4-0ef78bba1605
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=238169759 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.238169759
Directory /workspace/28.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.2837318312
Short name T39
Test name
Test status
Simulation time 1554530000 ps
CPU time 4.14 seconds
Started Aug 01 04:24:15 PM PDT 24
Finished Aug 01 04:24:25 PM PDT 24
Peak memory 162220 kb
Host smart-4686de27-ae06-4bcc-a078-3df678fded9b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2837318312 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.2837318312
Directory /workspace/29.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.4013707072
Short name T52
Test name
Test status
Simulation time 1535090000 ps
CPU time 3.79 seconds
Started Aug 01 04:17:45 PM PDT 24
Finished Aug 01 04:17:53 PM PDT 24
Peak memory 164856 kb
Host smart-89fd4652-60e9-4fb0-8e66-d594ff3076c6
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4013707072 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.4013707072
Directory /workspace/3.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.564590489
Short name T70
Test name
Test status
Simulation time 1462890000 ps
CPU time 3.68 seconds
Started Aug 01 04:22:34 PM PDT 24
Finished Aug 01 04:22:43 PM PDT 24
Peak memory 164508 kb
Host smart-191a2f25-d33d-446b-8347-f0f2c4670537
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=564590489 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.564590489
Directory /workspace/30.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.2470701730
Short name T65
Test name
Test status
Simulation time 1333070000 ps
CPU time 3.08 seconds
Started Aug 01 04:22:37 PM PDT 24
Finished Aug 01 04:22:44 PM PDT 24
Peak memory 165344 kb
Host smart-8e85b067-cd80-4b07-a651-68dd8ac3b25a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2470701730 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.2470701730
Directory /workspace/31.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.2003459098
Short name T40
Test name
Test status
Simulation time 1504470000 ps
CPU time 3.72 seconds
Started Aug 01 04:22:19 PM PDT 24
Finished Aug 01 04:22:28 PM PDT 24
Peak memory 163276 kb
Host smart-64cd1f0f-ebd7-4561-bd62-61e92a82873d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2003459098 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.2003459098
Directory /workspace/32.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.2356755471
Short name T61
Test name
Test status
Simulation time 1575610000 ps
CPU time 5.4 seconds
Started Aug 01 04:20:26 PM PDT 24
Finished Aug 01 04:20:38 PM PDT 24
Peak memory 164916 kb
Host smart-00aa8eb3-3df9-42c5-8045-4617fc98c653
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2356755471 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.2356755471
Directory /workspace/33.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.3041623673
Short name T3
Test name
Test status
Simulation time 1530870000 ps
CPU time 3.98 seconds
Started Aug 01 04:22:30 PM PDT 24
Finished Aug 01 04:22:40 PM PDT 24
Peak memory 164508 kb
Host smart-4ddfd27e-393b-4316-958a-f26eb8f372c1
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3041623673 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.3041623673
Directory /workspace/34.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.1084775998
Short name T8
Test name
Test status
Simulation time 1126750000 ps
CPU time 3.28 seconds
Started Aug 01 04:22:31 PM PDT 24
Finished Aug 01 04:22:38 PM PDT 24
Peak memory 164524 kb
Host smart-80e67f34-27ab-40f0-b70f-0a56e71981e6
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1084775998 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.1084775998
Directory /workspace/35.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.523421409
Short name T64
Test name
Test status
Simulation time 1544770000 ps
CPU time 3.4 seconds
Started Aug 01 04:22:39 PM PDT 24
Finished Aug 01 04:22:46 PM PDT 24
Peak memory 164472 kb
Host smart-fcc5d2e6-4fba-43a0-9da4-a3042aed1fa4
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=523421409 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.523421409
Directory /workspace/36.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.3310216828
Short name T48
Test name
Test status
Simulation time 1224010000 ps
CPU time 3.39 seconds
Started Aug 01 04:22:31 PM PDT 24
Finished Aug 01 04:22:39 PM PDT 24
Peak memory 164688 kb
Host smart-6b4fbcbd-5b61-47e4-9d54-cf6e8bb5c8cf
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3310216828 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.3310216828
Directory /workspace/37.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.4142911032
Short name T68
Test name
Test status
Simulation time 1591870000 ps
CPU time 5.29 seconds
Started Aug 01 04:20:18 PM PDT 24
Finished Aug 01 04:20:30 PM PDT 24
Peak memory 164676 kb
Host smart-4491674e-9984-47db-906d-17097e4eba91
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4142911032 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.4142911032
Directory /workspace/38.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.3440993110
Short name T1
Test name
Test status
Simulation time 1558830000 ps
CPU time 4.64 seconds
Started Aug 01 04:23:02 PM PDT 24
Finished Aug 01 04:23:13 PM PDT 24
Peak memory 164316 kb
Host smart-40f9ad26-14e0-4e56-84e5-d37b396e82b0
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3440993110 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.3440993110
Directory /workspace/39.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.807861253
Short name T37
Test name
Test status
Simulation time 1459050000 ps
CPU time 4.68 seconds
Started Aug 01 04:17:48 PM PDT 24
Finished Aug 01 04:17:58 PM PDT 24
Peak memory 164340 kb
Host smart-ac9149b4-bc9c-4207-afb7-14bc8217bb04
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=807861253 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.807861253
Directory /workspace/4.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.1573111617
Short name T42
Test name
Test status
Simulation time 1274870000 ps
CPU time 2.71 seconds
Started Aug 01 04:23:33 PM PDT 24
Finished Aug 01 04:23:39 PM PDT 24
Peak memory 164508 kb
Host smart-46a6c66e-4de4-4754-9342-64e54f69eb3a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1573111617 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.1573111617
Directory /workspace/40.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.3182349984
Short name T36
Test name
Test status
Simulation time 1578390000 ps
CPU time 3.59 seconds
Started Aug 01 04:22:48 PM PDT 24
Finished Aug 01 04:22:56 PM PDT 24
Peak memory 166008 kb
Host smart-b592375d-1b77-480b-9799-d22522857421
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3182349984 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.3182349984
Directory /workspace/41.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.2067986942
Short name T47
Test name
Test status
Simulation time 1576490000 ps
CPU time 4.5 seconds
Started Aug 01 04:20:58 PM PDT 24
Finished Aug 01 04:21:08 PM PDT 24
Peak memory 164912 kb
Host smart-f8c5525c-e488-4a71-b4bd-c9ccc2299a22
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2067986942 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.2067986942
Directory /workspace/42.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.326104708
Short name T46
Test name
Test status
Simulation time 1547310000 ps
CPU time 3.27 seconds
Started Aug 01 04:22:50 PM PDT 24
Finished Aug 01 04:22:58 PM PDT 24
Peak memory 164304 kb
Host smart-5bcdf234-9260-4a6d-bebd-ad0238d43dd1
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=326104708 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.326104708
Directory /workspace/43.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.106155336
Short name T11
Test name
Test status
Simulation time 1411730000 ps
CPU time 3.29 seconds
Started Aug 01 04:23:11 PM PDT 24
Finished Aug 01 04:23:18 PM PDT 24
Peak memory 164324 kb
Host smart-f7dde8fa-1bc3-4ea0-9d75-7688c5fd0e6a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=106155336 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.106155336
Directory /workspace/44.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.1425874412
Short name T55
Test name
Test status
Simulation time 1602650000 ps
CPU time 4.64 seconds
Started Aug 01 04:19:05 PM PDT 24
Finished Aug 01 04:19:16 PM PDT 24
Peak memory 164712 kb
Host smart-5956c0e6-996d-4dcb-b466-e10db769f6ac
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1425874412 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.1425874412
Directory /workspace/45.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.1007344482
Short name T7
Test name
Test status
Simulation time 1503590000 ps
CPU time 4.94 seconds
Started Aug 01 04:23:02 PM PDT 24
Finished Aug 01 04:23:12 PM PDT 24
Peak memory 164676 kb
Host smart-5bc88341-92d8-4117-bcdf-fa3dd8b28ec1
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1007344482 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.1007344482
Directory /workspace/46.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.2043389181
Short name T32
Test name
Test status
Simulation time 1496790000 ps
CPU time 2.9 seconds
Started Aug 01 04:23:37 PM PDT 24
Finished Aug 01 04:23:43 PM PDT 24
Peak memory 164688 kb
Host smart-0b7bc67d-1202-40e9-be8b-66828d053c82
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2043389181 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.2043389181
Directory /workspace/47.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.58581137
Short name T43
Test name
Test status
Simulation time 1373470000 ps
CPU time 3.88 seconds
Started Aug 01 04:21:53 PM PDT 24
Finished Aug 01 04:22:02 PM PDT 24
Peak memory 164704 kb
Host smart-e32d784f-4c9f-4760-8b3a-84e7c56d1840
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=58581137 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.58581137
Directory /workspace/48.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.44285333
Short name T58
Test name
Test status
Simulation time 1383090000 ps
CPU time 4.05 seconds
Started Aug 01 04:19:15 PM PDT 24
Finished Aug 01 04:19:23 PM PDT 24
Peak memory 164900 kb
Host smart-24a3697c-39e5-480a-8722-ab635e2596c7
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=44285333 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.44285333
Directory /workspace/49.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.4126999985
Short name T38
Test name
Test status
Simulation time 1313250000 ps
CPU time 4.63 seconds
Started Aug 01 04:17:41 PM PDT 24
Finished Aug 01 04:17:51 PM PDT 24
Peak memory 165020 kb
Host smart-4d7e2047-12a6-4a19-a84c-3d2dda2321ec
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4126999985 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.4126999985
Directory /workspace/5.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.4248418987
Short name T2
Test name
Test status
Simulation time 1384250000 ps
CPU time 4.66 seconds
Started Aug 01 04:17:47 PM PDT 24
Finished Aug 01 04:17:57 PM PDT 24
Peak memory 163556 kb
Host smart-c520d87e-30e8-4f6a-9f47-d81f12532696
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4248418987 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.4248418987
Directory /workspace/6.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.1793620152
Short name T66
Test name
Test status
Simulation time 1298730000 ps
CPU time 4.39 seconds
Started Aug 01 04:17:47 PM PDT 24
Finished Aug 01 04:17:57 PM PDT 24
Peak memory 163996 kb
Host smart-d458e5d5-a25a-458f-86f2-9a9b871bb58c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1793620152 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.1793620152
Directory /workspace/7.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.2079036375
Short name T59
Test name
Test status
Simulation time 1216930000 ps
CPU time 4.28 seconds
Started Aug 01 04:17:48 PM PDT 24
Finished Aug 01 04:17:57 PM PDT 24
Peak memory 164344 kb
Host smart-f8468f67-0439-4acf-91b1-26122dc0b8f8
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2079036375 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.2079036375
Directory /workspace/8.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.2912863616
Short name T53
Test name
Test status
Simulation time 1413250000 ps
CPU time 3.88 seconds
Started Aug 01 04:22:39 PM PDT 24
Finished Aug 01 04:22:48 PM PDT 24
Peak memory 164456 kb
Host smart-e9085f3e-e6bf-497d-bbf6-bcabb6ae6e8e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2912863616 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.2912863616
Directory /workspace/9.prim_lfsr_gal_smoke/latest
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