Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.31 100.00 96.55 100.00 100.00 95.00


Total tests in report: 200
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
87.31 87.31 100.00 100.00 96.55 96.55 100.00 100.00 100.00 100.00 40.00 40.00 /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.4024653152
96.81 9.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 87.50 47.50 /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.2612633411
98.31 1.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 95.00 7.50 /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.3832398139

Tests that do not contribute to grading

Name
/workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.3009924233
/workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.1783651721
/workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.1233011823
/workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.1906767238
/workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.3885252488
/workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.283076665
/workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.1900816720
/workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.1911613037
/workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.3782969564
/workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.3143691058
/workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.700341887
/workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.3537977993
/workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.707180318
/workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.2678420772
/workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.2379939040
/workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.1618939237
/workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.3607503307
/workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.3962992978
/workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.3749997266
/workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.3698174450
/workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.3352992800
/workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.1054795244
/workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.3103540606
/workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3089215609
/workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.1076312976
/workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.3926285444
/workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.2312694460
/workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.90194174
/workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.383345180
/workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.622936080
/workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.2021888251
/workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.656664808
/workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.3543505810
/workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.3601632739
/workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.3023749909
/workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.494879077
/workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.3144350578
/workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.2768571158
/workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.3252298397
/workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.270419329
/workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.3466311390
/workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.2114976381
/workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.1631232465
/workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.907002332
/workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.2047551495
/workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.2236915613
/workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.669785943
/workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.612001370
/workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.1333018889
/workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.1292178463
/workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.618104597
/workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.1858529422
/workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.235247103
/workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.689128339
/workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.4165759550
/workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.414091265
/workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.3009076356
/workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.1005722095
/workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.1728931813
/workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.82828742
/workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.3109980034
/workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.3331159003
/workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.707689669
/workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.2862654218
/workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.309958491
/workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.56233432
/workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.3403171143
/workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.2334246765
/workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.2105267394
/workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.4108694330
/workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.987643010
/workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.3681437881
/workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.1539067157
/workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.292729394
/workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.3902705400
/workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.687447053
/workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.235313040
/workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.2028937152
/workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.3477617749
/workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.1550827896
/workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.2318326272
/workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.2216952849
/workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.1370050244
/workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.584339752
/workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.2284412334
/workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.2606458592
/workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.2222767187
/workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.3739538877
/workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.3305163539
/workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.1753100350
/workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.2755236444
/workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.3523376739
/workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.3233411658
/workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.1310218287
/workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.2925767497
/workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.3337657112
/workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.2461221509
/workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.1476949108
/workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.665697750
/workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.2921035394
/workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.1601467114
/workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.4293079458
/workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.3360147383
/workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.1158827632
/workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.170682519
/workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.367833184
/workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.3569064094
/workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.3525661886
/workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.2066761870
/workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.1942916140
/workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.1331480631
/workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.1171361639
/workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.1200897263
/workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.909930823
/workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.3415881209
/workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.2050053969
/workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.3485359581
/workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.3881468659
/workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.2457804705
/workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.3542186650
/workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.1151858765
/workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.3107068894
/workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.690999371
/workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.3145487922
/workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.2420433253
/workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.1386047166
/workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.615079950
/workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.2768827696
/workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.1363729225
/workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1550399582
/workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.54003782
/workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.1487083550
/workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3527915165
/workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.3919559928
/workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.4142038902
/workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.3777082487
/workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.2820948397
/workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.3043071067
/workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.3558086640
/workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.2774991519
/workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.83935198
/workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.1672779421
/workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.2258171274
/workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.1232220686
/workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.3169856914
/workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.3561285601
/workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1475646448
/workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2238543311
/workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.3290817015
/workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.865621546
/workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.3523945790
/workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.581023081
/workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.3757561863
/workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.4042334490
/workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.2197290650
/workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.3923759061
/workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.2250491587
/workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.3195833202
/workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.1381784344
/workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.3698057264
/workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.2030212975
/workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.2677340509
/workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.2976982465
/workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.4128124168
/workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.1304400058
/workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.2008557878
/workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.636272225
/workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.3690935984
/workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.1739616215
/workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.1935465939
/workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.1095322787
/workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.2665077319
/workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.1681970066
/workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.3347022244
/workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.1091852824
/workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.199378771
/workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.2215194074
/workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.2501513130
/workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.3011628023
/workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.756672215
/workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.675661747
/workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.1602886945
/workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.1389794827
/workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.756671826
/workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.3147768001
/workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.3711554221
/workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.4252492595
/workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.3695280285
/workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.724963131
/workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.1320693363
/workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.177232219
/workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.2617607257
/workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.3071168174
/workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.3721973655
/workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.1957531284
/workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.1599235064
/workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.4272833290



Total test records in report: 200
tests.html | tests1.html | tests2.html | tests3.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.636272225 Aug 02 04:24:29 PM PDT 24 Aug 02 04:24:38 PM PDT 24 1619310000 ps
T2 /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.3721973655 Aug 02 04:23:13 PM PDT 24 Aug 02 04:23:24 PM PDT 24 1493350000 ps
T3 /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.1320693363 Aug 02 04:23:26 PM PDT 24 Aug 02 04:23:34 PM PDT 24 1432910000 ps
T7 /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.1304400058 Aug 02 04:24:26 PM PDT 24 Aug 02 04:24:34 PM PDT 24 1451850000 ps
T8 /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.3690935984 Aug 02 04:24:29 PM PDT 24 Aug 02 04:24:35 PM PDT 24 1248970000 ps
T9 /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.1935465939 Aug 02 04:24:05 PM PDT 24 Aug 02 04:24:12 PM PDT 24 1237270000 ps
T10 /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.4024653152 Aug 02 04:24:41 PM PDT 24 Aug 02 04:24:48 PM PDT 24 1587870000 ps
T11 /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.177232219 Aug 02 04:23:24 PM PDT 24 Aug 02 04:23:35 PM PDT 24 1607150000 ps
T12 /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.1389794827 Aug 02 04:23:24 PM PDT 24 Aug 02 04:23:33 PM PDT 24 1295070000 ps
T13 /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.1091852824 Aug 02 04:24:10 PM PDT 24 Aug 02 04:24:18 PM PDT 24 1363590000 ps
T31 /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.2030212975 Aug 02 04:23:14 PM PDT 24 Aug 02 04:23:25 PM PDT 24 1553170000 ps
T32 /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.3757561863 Aug 02 04:23:25 PM PDT 24 Aug 02 04:23:35 PM PDT 24 1438510000 ps
T33 /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.2976982465 Aug 02 04:24:30 PM PDT 24 Aug 02 04:24:37 PM PDT 24 1263050000 ps
T34 /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.3195833202 Aug 02 04:24:43 PM PDT 24 Aug 02 04:24:52 PM PDT 24 1471470000 ps
T35 /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.1381784344 Aug 02 04:24:30 PM PDT 24 Aug 02 04:24:39 PM PDT 24 1415650000 ps
T36 /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.2665077319 Aug 02 04:24:09 PM PDT 24 Aug 02 04:24:17 PM PDT 24 1290130000 ps
T37 /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.2250491587 Aug 02 04:24:40 PM PDT 24 Aug 02 04:24:47 PM PDT 24 1278890000 ps
T38 /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.756672215 Aug 02 04:24:05 PM PDT 24 Aug 02 04:24:14 PM PDT 24 1615630000 ps
T39 /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.581023081 Aug 02 04:24:44 PM PDT 24 Aug 02 04:24:53 PM PDT 24 1451870000 ps
T40 /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.1095322787 Aug 02 04:23:14 PM PDT 24 Aug 02 04:23:22 PM PDT 24 1079550000 ps
T41 /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.2008557878 Aug 02 04:24:44 PM PDT 24 Aug 02 04:24:52 PM PDT 24 1510170000 ps
T42 /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.1739616215 Aug 02 04:24:41 PM PDT 24 Aug 02 04:24:49 PM PDT 24 1503550000 ps
T43 /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.724963131 Aug 02 04:23:29 PM PDT 24 Aug 02 04:23:38 PM PDT 24 1295510000 ps
T44 /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.1957531284 Aug 02 04:23:15 PM PDT 24 Aug 02 04:23:26 PM PDT 24 1514930000 ps
T45 /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.3011628023 Aug 02 04:24:08 PM PDT 24 Aug 02 04:24:15 PM PDT 24 1397250000 ps
T46 /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.4128124168 Aug 02 04:24:29 PM PDT 24 Aug 02 04:24:36 PM PDT 24 1301730000 ps
T47 /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.675661747 Aug 02 04:25:07 PM PDT 24 Aug 02 04:25:19 PM PDT 24 1485570000 ps
T48 /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.4272833290 Aug 02 04:23:14 PM PDT 24 Aug 02 04:23:24 PM PDT 24 1518530000 ps
T49 /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.4042334490 Aug 02 04:23:24 PM PDT 24 Aug 02 04:23:33 PM PDT 24 1397530000 ps
T50 /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.2677340509 Aug 02 04:24:29 PM PDT 24 Aug 02 04:24:39 PM PDT 24 1551570000 ps
T51 /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.2197290650 Aug 02 04:24:40 PM PDT 24 Aug 02 04:24:48 PM PDT 24 1300070000 ps
T52 /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.1599235064 Aug 02 04:23:16 PM PDT 24 Aug 02 04:23:26 PM PDT 24 1555810000 ps
T53 /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.3695280285 Aug 02 04:23:25 PM PDT 24 Aug 02 04:23:35 PM PDT 24 1526690000 ps
T54 /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.199378771 Aug 02 04:24:13 PM PDT 24 Aug 02 04:24:23 PM PDT 24 1359030000 ps
T55 /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.3347022244 Aug 02 04:25:18 PM PDT 24 Aug 02 04:25:28 PM PDT 24 1426870000 ps
T56 /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.2215194074 Aug 02 04:24:13 PM PDT 24 Aug 02 04:24:24 PM PDT 24 1552210000 ps
T57 /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.3071168174 Aug 02 04:23:14 PM PDT 24 Aug 02 04:23:25 PM PDT 24 1357010000 ps
T58 /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.3290817015 Aug 02 04:23:13 PM PDT 24 Aug 02 04:23:24 PM PDT 24 1590970000 ps
T59 /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.1681970066 Aug 02 04:24:28 PM PDT 24 Aug 02 04:24:35 PM PDT 24 1419670000 ps
T60 /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.3923759061 Aug 02 04:24:28 PM PDT 24 Aug 02 04:24:35 PM PDT 24 1439230000 ps
T61 /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.2617607257 Aug 02 04:23:25 PM PDT 24 Aug 02 04:23:35 PM PDT 24 1523990000 ps
T62 /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.756671826 Aug 02 04:23:24 PM PDT 24 Aug 02 04:23:33 PM PDT 24 1476570000 ps
T63 /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.3147768001 Aug 02 04:23:24 PM PDT 24 Aug 02 04:23:34 PM PDT 24 1517330000 ps
T64 /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.865621546 Aug 02 04:23:14 PM PDT 24 Aug 02 04:23:22 PM PDT 24 1245830000 ps
T65 /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.1602886945 Aug 02 04:23:13 PM PDT 24 Aug 02 04:23:23 PM PDT 24 1318990000 ps
T66 /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.3711554221 Aug 02 04:23:23 PM PDT 24 Aug 02 04:23:33 PM PDT 24 1495450000 ps
T67 /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.3523945790 Aug 02 04:23:25 PM PDT 24 Aug 02 04:23:35 PM PDT 24 1487250000 ps
T68 /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.4252492595 Aug 02 04:23:24 PM PDT 24 Aug 02 04:23:34 PM PDT 24 1593310000 ps
T69 /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.2501513130 Aug 02 04:25:08 PM PDT 24 Aug 02 04:25:20 PM PDT 24 1640410000 ps
T70 /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.3698057264 Aug 02 04:24:29 PM PDT 24 Aug 02 04:24:39 PM PDT 24 1483430000 ps
T4 /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.1900816720 Aug 02 04:23:14 PM PDT 24 Aug 02 04:58:38 PM PDT 24 336410050000 ps
T5 /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.3144350578 Aug 02 04:24:42 PM PDT 24 Aug 02 04:56:27 PM PDT 24 337028530000 ps
T6 /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.2612633411 Aug 02 04:23:14 PM PDT 24 Aug 02 05:00:42 PM PDT 24 336498030000 ps
T14 /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.3782969564 Aug 02 04:23:14 PM PDT 24 Aug 02 04:50:12 PM PDT 24 336671390000 ps
T15 /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.3543505810 Aug 02 04:23:33 PM PDT 24 Aug 02 04:58:09 PM PDT 24 336371670000 ps
T16 /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.669785943 Aug 02 04:23:14 PM PDT 24 Aug 02 05:00:01 PM PDT 24 336966830000 ps
T17 /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.1076312976 Aug 02 04:23:30 PM PDT 24 Aug 02 04:59:54 PM PDT 24 336720370000 ps
T18 /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.3466311390 Aug 02 04:24:42 PM PDT 24 Aug 02 04:56:36 PM PDT 24 336672930000 ps
T19 /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.3607503307 Aug 02 04:25:00 PM PDT 24 Aug 02 04:56:34 PM PDT 24 336489290000 ps
T20 /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3089215609 Aug 02 04:23:24 PM PDT 24 Aug 02 04:53:19 PM PDT 24 336957430000 ps
T71 /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.2236915613 Aug 02 04:23:12 PM PDT 24 Aug 02 04:50:04 PM PDT 24 337119590000 ps
T72 /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.2379939040 Aug 02 04:25:17 PM PDT 24 Aug 02 04:59:42 PM PDT 24 336946930000 ps
T73 /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.656664808 Aug 02 04:23:25 PM PDT 24 Aug 02 04:53:16 PM PDT 24 336674110000 ps
T74 /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.383345180 Aug 02 04:23:23 PM PDT 24 Aug 02 04:55:35 PM PDT 24 336716270000 ps
T75 /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.270419329 Aug 02 04:23:35 PM PDT 24 Aug 02 04:55:27 PM PDT 24 337071770000 ps
T76 /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.700341887 Aug 02 04:23:15 PM PDT 24 Aug 02 04:52:06 PM PDT 24 336824990000 ps
T77 /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.2114976381 Aug 02 04:24:26 PM PDT 24 Aug 02 04:47:41 PM PDT 24 336953890000 ps
T78 /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.2047551495 Aug 02 04:23:12 PM PDT 24 Aug 02 04:53:08 PM PDT 24 336878470000 ps
T79 /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.1233011823 Aug 02 04:23:14 PM PDT 24 Aug 02 04:59:32 PM PDT 24 336817110000 ps
T80 /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.1333018889 Aug 02 04:23:14 PM PDT 24 Aug 02 05:01:05 PM PDT 24 336318590000 ps
T81 /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.707180318 Aug 02 04:24:20 PM PDT 24 Aug 02 04:49:24 PM PDT 24 337011410000 ps
T82 /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.3537977993 Aug 02 04:23:13 PM PDT 24 Aug 02 04:50:56 PM PDT 24 337030250000 ps
T83 /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.3143691058 Aug 02 04:23:14 PM PDT 24 Aug 02 04:48:50 PM PDT 24 336354370000 ps
T84 /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.3749997266 Aug 02 04:25:07 PM PDT 24 Aug 02 05:05:42 PM PDT 24 336784390000 ps
T85 /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.3023749909 Aug 02 04:24:42 PM PDT 24 Aug 02 04:57:09 PM PDT 24 336411930000 ps
T86 /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.1054795244 Aug 02 04:25:07 PM PDT 24 Aug 02 05:05:48 PM PDT 24 336937170000 ps
T87 /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.622936080 Aug 02 04:23:25 PM PDT 24 Aug 02 04:53:12 PM PDT 24 336750490000 ps
T88 /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.3103540606 Aug 02 04:23:15 PM PDT 24 Aug 02 04:57:52 PM PDT 24 336670030000 ps
T89 /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.2678420772 Aug 02 04:25:18 PM PDT 24 Aug 02 04:59:53 PM PDT 24 336887210000 ps
T90 /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.3698174450 Aug 02 04:25:08 PM PDT 24 Aug 02 05:05:04 PM PDT 24 337037150000 ps
T91 /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.907002332 Aug 02 04:23:38 PM PDT 24 Aug 02 04:55:53 PM PDT 24 336871730000 ps
T92 /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.2312694460 Aug 02 04:23:25 PM PDT 24 Aug 02 04:59:18 PM PDT 24 336905750000 ps
T93 /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.283076665 Aug 02 04:23:13 PM PDT 24 Aug 02 04:59:12 PM PDT 24 336782650000 ps
T94 /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.3009924233 Aug 02 04:23:12 PM PDT 24 Aug 02 04:53:38 PM PDT 24 336823410000 ps
T95 /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.2768571158 Aug 02 04:24:42 PM PDT 24 Aug 02 04:56:21 PM PDT 24 337042150000 ps
T96 /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.3962992978 Aug 02 04:25:08 PM PDT 24 Aug 02 05:03:36 PM PDT 24 336979950000 ps
T97 /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.3926285444 Aug 02 04:23:25 PM PDT 24 Aug 02 04:50:40 PM PDT 24 336881550000 ps
T98 /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.3352992800 Aug 02 04:25:07 PM PDT 24 Aug 02 05:05:51 PM PDT 24 336526290000 ps
T99 /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.3601632739 Aug 02 04:23:14 PM PDT 24 Aug 02 04:58:40 PM PDT 24 336448290000 ps
T100 /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.1783651721 Aug 02 04:23:11 PM PDT 24 Aug 02 04:50:58 PM PDT 24 336407350000 ps
T101 /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.494879077 Aug 02 04:24:41 PM PDT 24 Aug 02 04:57:24 PM PDT 24 336752590000 ps
T102 /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.1631232465 Aug 02 04:23:37 PM PDT 24 Aug 02 04:55:34 PM PDT 24 336820610000 ps
T103 /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.3252298397 Aug 02 04:23:34 PM PDT 24 Aug 02 04:54:26 PM PDT 24 336887390000 ps
T104 /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.3885252488 Aug 02 04:23:13 PM PDT 24 Aug 02 04:59:09 PM PDT 24 336572090000 ps
T105 /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.90194174 Aug 02 04:23:32 PM PDT 24 Aug 02 04:56:47 PM PDT 24 336573890000 ps
T106 /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.1618939237 Aug 02 04:25:18 PM PDT 24 Aug 02 05:00:14 PM PDT 24 336684930000 ps
T107 /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.1911613037 Aug 02 04:23:12 PM PDT 24 Aug 02 04:50:18 PM PDT 24 336710490000 ps
T108 /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.2021888251 Aug 02 04:23:24 PM PDT 24 Aug 02 04:56:12 PM PDT 24 336880830000 ps
T109 /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.1906767238 Aug 02 04:23:15 PM PDT 24 Aug 02 04:49:05 PM PDT 24 336548230000 ps
T110 /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.612001370 Aug 02 04:23:13 PM PDT 24 Aug 02 04:59:11 PM PDT 24 336404330000 ps
T111 /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.1672779421 Aug 02 04:25:01 PM PDT 24 Aug 02 04:25:12 PM PDT 24 1499170000 ps
T112 /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.3485359581 Aug 02 04:24:43 PM PDT 24 Aug 02 04:24:51 PM PDT 24 1367870000 ps
T113 /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.2420433253 Aug 02 04:24:30 PM PDT 24 Aug 02 04:24:39 PM PDT 24 1565190000 ps
T114 /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.3360147383 Aug 02 04:24:41 PM PDT 24 Aug 02 04:24:52 PM PDT 24 1579330000 ps
T115 /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.3043071067 Aug 02 04:24:10 PM PDT 24 Aug 02 04:24:18 PM PDT 24 1480870000 ps
T116 /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.3569064094 Aug 02 04:24:42 PM PDT 24 Aug 02 04:24:50 PM PDT 24 1374030000 ps
T117 /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.2774991519 Aug 02 04:25:17 PM PDT 24 Aug 02 04:25:27 PM PDT 24 1257370000 ps
T118 /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.3415881209 Aug 02 04:23:35 PM PDT 24 Aug 02 04:23:43 PM PDT 24 1525010000 ps
T119 /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.909930823 Aug 02 04:24:44 PM PDT 24 Aug 02 04:24:53 PM PDT 24 1420030000 ps
T120 /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.3919559928 Aug 02 04:24:03 PM PDT 24 Aug 02 04:24:12 PM PDT 24 1396590000 ps
T121 /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.3777082487 Aug 02 04:24:11 PM PDT 24 Aug 02 04:24:19 PM PDT 24 1455510000 ps
T122 /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.3542186650 Aug 02 04:24:25 PM PDT 24 Aug 02 04:24:31 PM PDT 24 1316150000 ps
T123 /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.1151858765 Aug 02 04:24:30 PM PDT 24 Aug 02 04:24:40 PM PDT 24 1367410000 ps
T124 /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.3881468659 Aug 02 04:24:41 PM PDT 24 Aug 02 04:24:50 PM PDT 24 1490990000 ps
T125 /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.3525661886 Aug 02 04:23:31 PM PDT 24 Aug 02 04:23:42 PM PDT 24 1606130000 ps
T126 /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.1158827632 Aug 02 04:23:27 PM PDT 24 Aug 02 04:23:33 PM PDT 24 1296870000 ps
T127 /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.2050053969 Aug 02 04:24:29 PM PDT 24 Aug 02 04:24:35 PM PDT 24 1214310000 ps
T128 /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.170682519 Aug 02 04:24:42 PM PDT 24 Aug 02 04:24:51 PM PDT 24 1529490000 ps
T129 /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.2820948397 Aug 02 04:25:18 PM PDT 24 Aug 02 04:25:29 PM PDT 24 1533370000 ps
T130 /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.1171361639 Aug 02 04:23:37 PM PDT 24 Aug 02 04:23:43 PM PDT 24 1211970000 ps
T131 /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.3561285601 Aug 02 04:23:19 PM PDT 24 Aug 02 04:23:27 PM PDT 24 1587170000 ps
T132 /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.1363729225 Aug 02 04:24:42 PM PDT 24 Aug 02 04:24:49 PM PDT 24 1399490000 ps
T133 /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.367833184 Aug 02 04:24:42 PM PDT 24 Aug 02 04:24:50 PM PDT 24 1246330000 ps
T134 /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.690999371 Aug 02 04:24:27 PM PDT 24 Aug 02 04:24:35 PM PDT 24 1520310000 ps
T135 /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.1200897263 Aug 02 04:23:24 PM PDT 24 Aug 02 04:23:35 PM PDT 24 1575290000 ps
T136 /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.1331480631 Aug 02 04:23:14 PM PDT 24 Aug 02 04:23:24 PM PDT 24 1368910000 ps
T137 /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.1601467114 Aug 02 04:24:55 PM PDT 24 Aug 02 04:25:06 PM PDT 24 1589350000 ps
T138 /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.2921035394 Aug 02 04:23:16 PM PDT 24 Aug 02 04:23:26 PM PDT 24 1519310000 ps
T139 /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.3169856914 Aug 02 04:23:15 PM PDT 24 Aug 02 04:23:24 PM PDT 24 1357530000 ps
T140 /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.4293079458 Aug 02 04:23:37 PM PDT 24 Aug 02 04:23:49 PM PDT 24 1621270000 ps
T141 /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2238543311 Aug 02 04:23:21 PM PDT 24 Aug 02 04:23:30 PM PDT 24 1532470000 ps
T142 /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.1487083550 Aug 02 04:24:41 PM PDT 24 Aug 02 04:24:50 PM PDT 24 1567350000 ps
T143 /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.1232220686 Aug 02 04:23:13 PM PDT 24 Aug 02 04:23:20 PM PDT 24 1414010000 ps
T144 /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.4142038902 Aug 02 04:24:29 PM PDT 24 Aug 02 04:24:36 PM PDT 24 1341350000 ps
T145 /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.2768827696 Aug 02 04:24:42 PM PDT 24 Aug 02 04:24:49 PM PDT 24 1372090000 ps
T146 /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.2258171274 Aug 02 04:24:09 PM PDT 24 Aug 02 04:24:19 PM PDT 24 1452510000 ps
T147 /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.3558086640 Aug 02 04:24:12 PM PDT 24 Aug 02 04:24:20 PM PDT 24 1420050000 ps
T148 /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.54003782 Aug 02 04:24:42 PM PDT 24 Aug 02 04:24:51 PM PDT 24 1414570000 ps
T149 /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1550399582 Aug 02 04:24:41 PM PDT 24 Aug 02 04:24:48 PM PDT 24 1520170000 ps
T150 /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.1386047166 Aug 02 04:24:44 PM PDT 24 Aug 02 04:24:52 PM PDT 24 1492310000 ps
T151 /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.615079950 Aug 02 04:24:29 PM PDT 24 Aug 02 04:24:39 PM PDT 24 1576470000 ps
T152 /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.3145487922 Aug 02 04:24:27 PM PDT 24 Aug 02 04:24:34 PM PDT 24 1473090000 ps
T153 /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.83935198 Aug 02 04:24:14 PM PDT 24 Aug 02 04:24:24 PM PDT 24 1519150000 ps
T154 /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.665697750 Aug 02 04:23:16 PM PDT 24 Aug 02 04:23:26 PM PDT 24 1481950000 ps
T155 /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.2066761870 Aug 02 04:23:38 PM PDT 24 Aug 02 04:23:48 PM PDT 24 1478430000 ps
T156 /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.2457804705 Aug 02 04:24:41 PM PDT 24 Aug 02 04:24:50 PM PDT 24 1506390000 ps
T157 /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.3107068894 Aug 02 04:23:14 PM PDT 24 Aug 02 04:23:22 PM PDT 24 1246410000 ps
T158 /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.1942916140 Aug 02 04:24:27 PM PDT 24 Aug 02 04:24:35 PM PDT 24 1570790000 ps
T159 /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1475646448 Aug 02 04:23:14 PM PDT 24 Aug 02 04:23:22 PM PDT 24 1147250000 ps
T160 /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3527915165 Aug 02 04:23:15 PM PDT 24 Aug 02 04:23:24 PM PDT 24 1325430000 ps
T21 /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.1476949108 Aug 02 04:23:14 PM PDT 24 Aug 02 05:00:59 PM PDT 24 336700890000 ps
T22 /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.2755236444 Aug 02 04:24:26 PM PDT 24 Aug 02 04:54:11 PM PDT 24 336872970000 ps
T23 /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.584339752 Aug 02 04:23:37 PM PDT 24 Aug 02 04:54:54 PM PDT 24 336406910000 ps
T24 /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.689128339 Aug 02 04:23:27 PM PDT 24 Aug 02 04:54:11 PM PDT 24 336538630000 ps
T25 /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.3832398139 Aug 02 04:23:15 PM PDT 24 Aug 02 04:52:32 PM PDT 24 336746790000 ps
T26 /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.4165759550 Aug 02 04:23:23 PM PDT 24 Aug 02 04:54:07 PM PDT 24 336373150000 ps
T27 /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.3331159003 Aug 02 04:23:25 PM PDT 24 Aug 02 05:01:45 PM PDT 24 337099330000 ps
T28 /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.3009076356 Aug 02 04:23:24 PM PDT 24 Aug 02 04:54:45 PM PDT 24 336769450000 ps
T29 /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.2461221509 Aug 02 04:23:14 PM PDT 24 Aug 02 05:00:53 PM PDT 24 336423970000 ps
T30 /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.707689669 Aug 02 04:24:41 PM PDT 24 Aug 02 04:53:42 PM PDT 24 337003630000 ps
T161 /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.2028937152 Aug 02 04:23:24 PM PDT 24 Aug 02 04:59:25 PM PDT 24 336706630000 ps
T162 /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.2862654218 Aug 02 04:23:27 PM PDT 24 Aug 02 04:51:07 PM PDT 24 336445310000 ps
T163 /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.3403171143 Aug 02 04:24:29 PM PDT 24 Aug 02 04:54:48 PM PDT 24 336429370000 ps
T164 /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.2105267394 Aug 02 04:23:40 PM PDT 24 Aug 02 04:55:31 PM PDT 24 336591810000 ps
T165 /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.687447053 Aug 02 04:24:26 PM PDT 24 Aug 02 04:56:00 PM PDT 24 336907870000 ps
T166 /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.56233432 Aug 02 04:24:29 PM PDT 24 Aug 02 04:54:13 PM PDT 24 336464190000 ps
T167 /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.3305163539 Aug 02 04:24:26 PM PDT 24 Aug 02 04:54:34 PM PDT 24 336734650000 ps
T168 /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.618104597 Aug 02 04:23:25 PM PDT 24 Aug 02 05:01:10 PM PDT 24 336854470000 ps
T169 /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.3681437881 Aug 02 04:23:21 PM PDT 24 Aug 02 04:54:37 PM PDT 24 336551730000 ps
T170 /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.1550827896 Aug 02 04:23:34 PM PDT 24 Aug 02 05:02:39 PM PDT 24 336453590000 ps
T171 /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.3233411658 Aug 02 04:23:25 PM PDT 24 Aug 02 04:53:37 PM PDT 24 336833230000 ps
T172 /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.292729394 Aug 02 04:23:34 PM PDT 24 Aug 02 04:57:19 PM PDT 24 337116010000 ps
T173 /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.1858529422 Aug 02 04:23:35 PM PDT 24 Aug 02 05:00:55 PM PDT 24 336640870000 ps
T174 /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.309958491 Aug 02 04:24:29 PM PDT 24 Aug 02 04:54:42 PM PDT 24 336372830000 ps
T175 /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.235247103 Aug 02 04:23:23 PM PDT 24 Aug 02 04:54:29 PM PDT 24 336446910000 ps
T176 /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.4108694330 Aug 02 04:23:32 PM PDT 24 Aug 02 04:54:29 PM PDT 24 336823210000 ps
T177 /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.1310218287 Aug 02 04:23:14 PM PDT 24 Aug 02 04:51:53 PM PDT 24 336370750000 ps
T178 /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.2925767497 Aug 02 04:23:15 PM PDT 24 Aug 02 04:52:22 PM PDT 24 336659490000 ps
T179 /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.2334246765 Aug 02 04:23:34 PM PDT 24 Aug 02 04:51:34 PM PDT 24 336953270000 ps
T180 /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.3739538877 Aug 02 04:24:42 PM PDT 24 Aug 02 04:56:33 PM PDT 24 336762970000 ps
T181 /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.3337657112 Aug 02 04:23:11 PM PDT 24 Aug 02 04:48:49 PM PDT 24 337116090000 ps
T182 /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.3109980034 Aug 02 04:23:21 PM PDT 24 Aug 02 04:55:00 PM PDT 24 336900170000 ps
T183 /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.2606458592 Aug 02 04:23:37 PM PDT 24 Aug 02 04:55:01 PM PDT 24 336700110000 ps
T184 /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.2318326272 Aug 02 04:24:39 PM PDT 24 Aug 02 04:58:18 PM PDT 24 336361870000 ps
T185 /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.1292178463 Aug 02 04:23:14 PM PDT 24 Aug 02 04:52:58 PM PDT 24 337073170000 ps
T186 /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.987643010 Aug 02 04:23:26 PM PDT 24 Aug 02 04:53:40 PM PDT 24 336520510000 ps
T187 /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.1728931813 Aug 02 04:23:23 PM PDT 24 Aug 02 04:59:11 PM PDT 24 336746210000 ps
T188 /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.3477617749 Aug 02 04:23:25 PM PDT 24 Aug 02 05:02:09 PM PDT 24 336437530000 ps
T189 /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.2284412334 Aug 02 04:24:29 PM PDT 24 Aug 02 04:55:23 PM PDT 24 337060030000 ps
T190 /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.235313040 Aug 02 04:24:25 PM PDT 24 Aug 02 04:56:50 PM PDT 24 337044690000 ps
T191 /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.3523376739 Aug 02 04:23:25 PM PDT 24 Aug 02 05:01:06 PM PDT 24 337036850000 ps
T192 /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.414091265 Aug 02 04:23:35 PM PDT 24 Aug 02 05:01:17 PM PDT 24 336946770000 ps
T193 /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.1539067157 Aug 02 04:24:25 PM PDT 24 Aug 02 04:56:50 PM PDT 24 336639590000 ps
T194 /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.2216952849 Aug 02 04:23:24 PM PDT 24 Aug 02 05:01:59 PM PDT 24 336777650000 ps
T195 /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.1370050244 Aug 02 04:23:22 PM PDT 24 Aug 02 04:53:32 PM PDT 24 336812650000 ps
T196 /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.2222767187 Aug 02 04:24:42 PM PDT 24 Aug 02 04:56:17 PM PDT 24 336427450000 ps
T197 /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.3902705400 Aug 02 04:23:23 PM PDT 24 Aug 02 04:59:53 PM PDT 24 336720870000 ps
T198 /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.82828742 Aug 02 04:23:25 PM PDT 24 Aug 02 05:01:22 PM PDT 24 337060230000 ps
T199 /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.1753100350 Aug 02 04:23:24 PM PDT 24 Aug 02 04:53:16 PM PDT 24 336618650000 ps
T200 /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.1005722095 Aug 02 04:23:25 PM PDT 24 Aug 02 04:58:44 PM PDT 24 336609790000 ps

Test location /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.4024653152
Short name T10
Test name
Test status
Simulation time 1587870000 ps
CPU time 3.06 seconds
Started Aug 02 04:24:41 PM PDT 24
Finished Aug 02 04:24:48 PM PDT 24
Peak memory 164700 kb
Host smart-1f4d105b-4d09-4d06-bc22-8f8ed9974aa4
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4024653152 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.4024653152
Directory /workspace/20.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.2612633411
Short name T6
Test name
Test status
Simulation time 336498030000 ps
CPU time 913.23 seconds
Started Aug 02 04:23:14 PM PDT 24
Finished Aug 02 05:00:42 PM PDT 24
Peak memory 160696 kb
Host smart-b03d4785-d080-42ec-9c30-00c303b8247a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2612633411 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.2612633411
Directory /workspace/11.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.3832398139
Short name T25
Test name
Test status
Simulation time 336746790000 ps
CPU time 700.78 seconds
Started Aug 02 04:23:15 PM PDT 24
Finished Aug 02 04:52:32 PM PDT 24
Peak memory 160656 kb
Host smart-655f9feb-395c-4cf9-a32b-ef2381660b20
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3832398139 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.3832398139
Directory /workspace/1.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.3009924233
Short name T94
Test name
Test status
Simulation time 336823410000 ps
CPU time 738.54 seconds
Started Aug 02 04:23:12 PM PDT 24
Finished Aug 02 04:53:38 PM PDT 24
Peak memory 160684 kb
Host smart-c9728340-e524-4deb-ace7-661bf8d1e843
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3009924233 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.3009924233
Directory /workspace/0.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.1783651721
Short name T100
Test name
Test status
Simulation time 336407350000 ps
CPU time 673.87 seconds
Started Aug 02 04:23:11 PM PDT 24
Finished Aug 02 04:50:58 PM PDT 24
Peak memory 160708 kb
Host smart-94d8db9d-2079-40ae-bf9b-3a948fd1764d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1783651721 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.1783651721
Directory /workspace/1.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.1233011823
Short name T79
Test name
Test status
Simulation time 336817110000 ps
CPU time 867.57 seconds
Started Aug 02 04:23:14 PM PDT 24
Finished Aug 02 04:59:32 PM PDT 24
Peak memory 160656 kb
Host smart-ef0237db-eed8-4bf0-97c1-1d28b20d1d91
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1233011823 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.1233011823
Directory /workspace/10.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.1906767238
Short name T109
Test name
Test status
Simulation time 336548230000 ps
CPU time 626.64 seconds
Started Aug 02 04:23:15 PM PDT 24
Finished Aug 02 04:49:05 PM PDT 24
Peak memory 160640 kb
Host smart-b3c28bde-a4c5-48a8-9050-33973c4919dd
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1906767238 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.1906767238
Directory /workspace/12.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.3885252488
Short name T104
Test name
Test status
Simulation time 336572090000 ps
CPU time 855.17 seconds
Started Aug 02 04:23:13 PM PDT 24
Finished Aug 02 04:59:09 PM PDT 24
Peak memory 160656 kb
Host smart-256250ed-950d-41c1-bab0-e20cbaeec821
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3885252488 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.3885252488
Directory /workspace/13.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.283076665
Short name T93
Test name
Test status
Simulation time 336782650000 ps
CPU time 860.15 seconds
Started Aug 02 04:23:13 PM PDT 24
Finished Aug 02 04:59:12 PM PDT 24
Peak memory 160648 kb
Host smart-3f84edd3-be0b-408b-bdaa-93135cb420b0
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=283076665 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.283076665
Directory /workspace/14.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.1900816720
Short name T4
Test name
Test status
Simulation time 336410050000 ps
CPU time 838.46 seconds
Started Aug 02 04:23:14 PM PDT 24
Finished Aug 02 04:58:38 PM PDT 24
Peak memory 160656 kb
Host smart-00bafcfa-dac2-410d-b012-6c8aba5e217e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1900816720 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.1900816720
Directory /workspace/15.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.1911613037
Short name T107
Test name
Test status
Simulation time 336710490000 ps
CPU time 665.72 seconds
Started Aug 02 04:23:12 PM PDT 24
Finished Aug 02 04:50:18 PM PDT 24
Peak memory 160688 kb
Host smart-3932f33c-cc78-4e1c-96e2-96fca5eeae42
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1911613037 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.1911613037
Directory /workspace/16.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.3782969564
Short name T14
Test name
Test status
Simulation time 336671390000 ps
CPU time 650.7 seconds
Started Aug 02 04:23:14 PM PDT 24
Finished Aug 02 04:50:12 PM PDT 24
Peak memory 160688 kb
Host smart-00c22744-3e1e-4684-a8ba-6607446d3add
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3782969564 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.3782969564
Directory /workspace/17.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.3143691058
Short name T83
Test name
Test status
Simulation time 336354370000 ps
CPU time 622.14 seconds
Started Aug 02 04:23:14 PM PDT 24
Finished Aug 02 04:48:50 PM PDT 24
Peak memory 160688 kb
Host smart-3122a2a6-080a-48cd-9ae4-d8144f04e6fc
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3143691058 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.3143691058
Directory /workspace/18.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.700341887
Short name T76
Test name
Test status
Simulation time 336824990000 ps
CPU time 702.26 seconds
Started Aug 02 04:23:15 PM PDT 24
Finished Aug 02 04:52:06 PM PDT 24
Peak memory 160680 kb
Host smart-4d29740f-7fb9-4f2a-9799-dd966ee180cd
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=700341887 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.700341887
Directory /workspace/19.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.3537977993
Short name T82
Test name
Test status
Simulation time 337030250000 ps
CPU time 672.47 seconds
Started Aug 02 04:23:13 PM PDT 24
Finished Aug 02 04:50:56 PM PDT 24
Peak memory 160712 kb
Host smart-ba36f471-6057-4199-89bd-b43b0c2e818e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3537977993 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.3537977993
Directory /workspace/2.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.707180318
Short name T81
Test name
Test status
Simulation time 337011410000 ps
CPU time 609.01 seconds
Started Aug 02 04:24:20 PM PDT 24
Finished Aug 02 04:49:24 PM PDT 24
Peak memory 160836 kb
Host smart-1e08b2bb-f7ef-4d8f-9b41-3c9665619904
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=707180318 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.707180318
Directory /workspace/20.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.2678420772
Short name T89
Test name
Test status
Simulation time 336887210000 ps
CPU time 839.12 seconds
Started Aug 02 04:25:18 PM PDT 24
Finished Aug 02 04:59:53 PM PDT 24
Peak memory 160616 kb
Host smart-4406ac28-4b59-43b0-9761-10ddf8e31916
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2678420772 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.2678420772
Directory /workspace/21.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.2379939040
Short name T72
Test name
Test status
Simulation time 336946930000 ps
CPU time 839.72 seconds
Started Aug 02 04:25:17 PM PDT 24
Finished Aug 02 04:59:42 PM PDT 24
Peak memory 160616 kb
Host smart-46a7ef26-b27a-4c3e-b623-df1f8d763c18
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2379939040 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.2379939040
Directory /workspace/22.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.1618939237
Short name T106
Test name
Test status
Simulation time 336684930000 ps
CPU time 850.42 seconds
Started Aug 02 04:25:18 PM PDT 24
Finished Aug 02 05:00:14 PM PDT 24
Peak memory 160616 kb
Host smart-e3a0431f-6d67-41b4-93bc-653efa2c48bd
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1618939237 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.1618939237
Directory /workspace/23.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.3607503307
Short name T19
Test name
Test status
Simulation time 336489290000 ps
CPU time 764.08 seconds
Started Aug 02 04:25:00 PM PDT 24
Finished Aug 02 04:56:34 PM PDT 24
Peak memory 160764 kb
Host smart-fe69cfef-5f19-4b38-aeaa-868677fa4f3c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3607503307 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.3607503307
Directory /workspace/24.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.3962992978
Short name T96
Test name
Test status
Simulation time 336979950000 ps
CPU time 920.24 seconds
Started Aug 02 04:25:08 PM PDT 24
Finished Aug 02 05:03:36 PM PDT 24
Peak memory 160240 kb
Host smart-e297da77-6dbd-47c5-8c7d-fef4987a45b2
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3962992978 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.3962992978
Directory /workspace/25.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.3749997266
Short name T84
Test name
Test status
Simulation time 336784390000 ps
CPU time 977.1 seconds
Started Aug 02 04:25:07 PM PDT 24
Finished Aug 02 05:05:42 PM PDT 24
Peak memory 158656 kb
Host smart-7e772530-2304-4ed8-a0f8-b8ea49656953
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3749997266 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.3749997266
Directory /workspace/26.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.3698174450
Short name T90
Test name
Test status
Simulation time 337037150000 ps
CPU time 971.01 seconds
Started Aug 02 04:25:08 PM PDT 24
Finished Aug 02 05:05:04 PM PDT 24
Peak memory 160228 kb
Host smart-562a4ae9-d51a-43a8-86d3-8bb7d18737ee
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3698174450 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.3698174450
Directory /workspace/27.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.3352992800
Short name T98
Test name
Test status
Simulation time 336526290000 ps
CPU time 982.76 seconds
Started Aug 02 04:25:07 PM PDT 24
Finished Aug 02 05:05:51 PM PDT 24
Peak memory 158640 kb
Host smart-f9c1d55c-e941-4922-b408-12970873f9a2
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3352992800 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.3352992800
Directory /workspace/28.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.1054795244
Short name T86
Test name
Test status
Simulation time 336937170000 ps
CPU time 983.28 seconds
Started Aug 02 04:25:07 PM PDT 24
Finished Aug 02 05:05:48 PM PDT 24
Peak memory 158400 kb
Host smart-397ad6bc-21cc-4c85-b21a-397ee2f98e7a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1054795244 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.1054795244
Directory /workspace/29.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.3103540606
Short name T88
Test name
Test status
Simulation time 336670030000 ps
CPU time 839.35 seconds
Started Aug 02 04:23:15 PM PDT 24
Finished Aug 02 04:57:52 PM PDT 24
Peak memory 160716 kb
Host smart-294949c6-8be4-413f-9e23-9d306da40bf2
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3103540606 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.3103540606
Directory /workspace/3.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3089215609
Short name T20
Test name
Test status
Simulation time 336957430000 ps
CPU time 727.02 seconds
Started Aug 02 04:23:24 PM PDT 24
Finished Aug 02 04:53:19 PM PDT 24
Peak memory 160684 kb
Host smart-cb3fb91f-1bbd-492b-81ae-4d2af7df5fb9
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3089215609 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.3089215609
Directory /workspace/30.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.1076312976
Short name T17
Test name
Test status
Simulation time 336720370000 ps
CPU time 874.82 seconds
Started Aug 02 04:23:30 PM PDT 24
Finished Aug 02 04:59:54 PM PDT 24
Peak memory 160648 kb
Host smart-41d1eb8e-096e-48d1-9c59-b8e9141fb1c9
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1076312976 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.1076312976
Directory /workspace/31.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.3926285444
Short name T97
Test name
Test status
Simulation time 336881550000 ps
CPU time 661.38 seconds
Started Aug 02 04:23:25 PM PDT 24
Finished Aug 02 04:50:40 PM PDT 24
Peak memory 160864 kb
Host smart-191c61df-b71c-4d4a-8a99-ec1ee7ed9fa7
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3926285444 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.3926285444
Directory /workspace/32.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.2312694460
Short name T92
Test name
Test status
Simulation time 336905750000 ps
CPU time 859.85 seconds
Started Aug 02 04:23:25 PM PDT 24
Finished Aug 02 04:59:18 PM PDT 24
Peak memory 160668 kb
Host smart-eb5134d3-d265-490d-907e-1f5977449ca4
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2312694460 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.2312694460
Directory /workspace/33.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.90194174
Short name T105
Test name
Test status
Simulation time 336573890000 ps
CPU time 808.52 seconds
Started Aug 02 04:23:32 PM PDT 24
Finished Aug 02 04:56:47 PM PDT 24
Peak memory 160712 kb
Host smart-4af3e25b-c0c2-4903-83c4-62f259ce4e4b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=90194174 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.90194174
Directory /workspace/34.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.383345180
Short name T74
Test name
Test status
Simulation time 336716270000 ps
CPU time 782.35 seconds
Started Aug 02 04:23:23 PM PDT 24
Finished Aug 02 04:55:35 PM PDT 24
Peak memory 160716 kb
Host smart-5095b340-0260-47e9-b5e2-2a600a51bb70
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=383345180 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.383345180
Directory /workspace/35.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.622936080
Short name T87
Test name
Test status
Simulation time 336750490000 ps
CPU time 715.51 seconds
Started Aug 02 04:23:25 PM PDT 24
Finished Aug 02 04:53:12 PM PDT 24
Peak memory 160676 kb
Host smart-127a8e4b-402a-4674-b4ca-504628ae5253
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=622936080 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.622936080
Directory /workspace/36.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.2021888251
Short name T108
Test name
Test status
Simulation time 336880830000 ps
CPU time 795.04 seconds
Started Aug 02 04:23:24 PM PDT 24
Finished Aug 02 04:56:12 PM PDT 24
Peak memory 160716 kb
Host smart-cecb4fd2-21b9-4f60-938e-0498a74cb284
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2021888251 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.2021888251
Directory /workspace/37.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.656664808
Short name T73
Test name
Test status
Simulation time 336674110000 ps
CPU time 719.92 seconds
Started Aug 02 04:23:25 PM PDT 24
Finished Aug 02 04:53:16 PM PDT 24
Peak memory 160676 kb
Host smart-58699805-3376-451d-8a11-82ec86d43413
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=656664808 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.656664808
Directory /workspace/38.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.3543505810
Short name T15
Test name
Test status
Simulation time 336371670000 ps
CPU time 847.09 seconds
Started Aug 02 04:23:33 PM PDT 24
Finished Aug 02 04:58:09 PM PDT 24
Peak memory 160716 kb
Host smart-d5d8f6fc-a886-4db3-8bf6-8e307fb7ca95
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3543505810 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.3543505810
Directory /workspace/39.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.3601632739
Short name T99
Test name
Test status
Simulation time 336448290000 ps
CPU time 842.2 seconds
Started Aug 02 04:23:14 PM PDT 24
Finished Aug 02 04:58:40 PM PDT 24
Peak memory 160652 kb
Host smart-745a3a67-d974-434e-809f-057cf881d9fd
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3601632739 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.3601632739
Directory /workspace/4.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.3023749909
Short name T85
Test name
Test status
Simulation time 336411930000 ps
CPU time 775.76 seconds
Started Aug 02 04:24:42 PM PDT 24
Finished Aug 02 04:57:09 PM PDT 24
Peak memory 160224 kb
Host smart-ea3d6af1-024d-4822-93fe-21157750fc29
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3023749909 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.3023749909
Directory /workspace/40.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.494879077
Short name T101
Test name
Test status
Simulation time 336752590000 ps
CPU time 789.38 seconds
Started Aug 02 04:24:41 PM PDT 24
Finished Aug 02 04:57:24 PM PDT 24
Peak memory 159328 kb
Host smart-35cffff2-de99-4c70-8c04-41146a4a5a10
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=494879077 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.494879077
Directory /workspace/41.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.3144350578
Short name T5
Test name
Test status
Simulation time 337028530000 ps
CPU time 762.47 seconds
Started Aug 02 04:24:42 PM PDT 24
Finished Aug 02 04:56:27 PM PDT 24
Peak memory 159628 kb
Host smart-eecb0e3c-a9e9-48e6-844f-fd8d27ce2e5c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3144350578 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.3144350578
Directory /workspace/42.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.2768571158
Short name T95
Test name
Test status
Simulation time 337042150000 ps
CPU time 753.08 seconds
Started Aug 02 04:24:42 PM PDT 24
Finished Aug 02 04:56:21 PM PDT 24
Peak memory 160364 kb
Host smart-a95c7e42-f6d3-4b33-8aee-42bdde641663
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2768571158 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.2768571158
Directory /workspace/43.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.3252298397
Short name T103
Test name
Test status
Simulation time 336887390000 ps
CPU time 750.66 seconds
Started Aug 02 04:23:34 PM PDT 24
Finished Aug 02 04:54:26 PM PDT 24
Peak memory 160724 kb
Host smart-7c96ac85-db8e-4f55-b78d-66a7bc2e8b6d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3252298397 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.3252298397
Directory /workspace/44.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.270419329
Short name T75
Test name
Test status
Simulation time 337071770000 ps
CPU time 786.46 seconds
Started Aug 02 04:23:35 PM PDT 24
Finished Aug 02 04:55:27 PM PDT 24
Peak memory 160740 kb
Host smart-189c8d9b-536e-4696-a326-3845964fa92e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=270419329 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.270419329
Directory /workspace/45.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.3466311390
Short name T18
Test name
Test status
Simulation time 336672930000 ps
CPU time 782.87 seconds
Started Aug 02 04:24:42 PM PDT 24
Finished Aug 02 04:56:36 PM PDT 24
Peak memory 160620 kb
Host smart-0f4a8e82-817d-40e1-8eed-c11d78fa70a3
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3466311390 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.3466311390
Directory /workspace/46.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.2114976381
Short name T77
Test name
Test status
Simulation time 336953890000 ps
CPU time 567.79 seconds
Started Aug 02 04:24:26 PM PDT 24
Finished Aug 02 04:47:41 PM PDT 24
Peak memory 159760 kb
Host smart-e5451ec5-bf77-4cb9-b8be-63ef3e4f005a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2114976381 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.2114976381
Directory /workspace/47.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.1631232465
Short name T102
Test name
Test status
Simulation time 336820610000 ps
CPU time 784.03 seconds
Started Aug 02 04:23:37 PM PDT 24
Finished Aug 02 04:55:34 PM PDT 24
Peak memory 160740 kb
Host smart-6212d56d-b85a-4901-a3dc-c39a3b22cf14
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1631232465 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.1631232465
Directory /workspace/48.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.907002332
Short name T91
Test name
Test status
Simulation time 336871730000 ps
CPU time 786.42 seconds
Started Aug 02 04:23:38 PM PDT 24
Finished Aug 02 04:55:53 PM PDT 24
Peak memory 160692 kb
Host smart-af26804d-e2d0-4ce3-a5ea-f46f9b3e58b4
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=907002332 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.907002332
Directory /workspace/49.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.2047551495
Short name T78
Test name
Test status
Simulation time 336878470000 ps
CPU time 736 seconds
Started Aug 02 04:23:12 PM PDT 24
Finished Aug 02 04:53:08 PM PDT 24
Peak memory 160684 kb
Host smart-fbfdeb0c-462b-492c-b3b9-dd988bd43af9
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2047551495 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.2047551495
Directory /workspace/5.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.2236915613
Short name T71
Test name
Test status
Simulation time 337119590000 ps
CPU time 654.94 seconds
Started Aug 02 04:23:12 PM PDT 24
Finished Aug 02 04:50:04 PM PDT 24
Peak memory 160708 kb
Host smart-f7133a1d-51be-401d-9d26-0e01f6defba1
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2236915613 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.2236915613
Directory /workspace/6.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.669785943
Short name T16
Test name
Test status
Simulation time 336966830000 ps
CPU time 895.84 seconds
Started Aug 02 04:23:14 PM PDT 24
Finished Aug 02 05:00:01 PM PDT 24
Peak memory 160708 kb
Host smart-310027d7-308e-4385-b88b-92b74c86a488
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=669785943 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.669785943
Directory /workspace/7.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.612001370
Short name T110
Test name
Test status
Simulation time 336404330000 ps
CPU time 859.78 seconds
Started Aug 02 04:23:13 PM PDT 24
Finished Aug 02 04:59:11 PM PDT 24
Peak memory 160644 kb
Host smart-6e46888a-8bae-4bb8-b06b-95c46f903d0c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=612001370 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.612001370
Directory /workspace/8.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.1333018889
Short name T80
Test name
Test status
Simulation time 336318590000 ps
CPU time 917.79 seconds
Started Aug 02 04:23:14 PM PDT 24
Finished Aug 02 05:01:05 PM PDT 24
Peak memory 160716 kb
Host smart-edfdea56-20b4-4ba4-a64d-f42ee3be7dde
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1333018889 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.1333018889
Directory /workspace/9.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.1292178463
Short name T185
Test name
Test status
Simulation time 337073170000 ps
CPU time 720.41 seconds
Started Aug 02 04:23:14 PM PDT 24
Finished Aug 02 04:52:58 PM PDT 24
Peak memory 160652 kb
Host smart-21cfb9c5-200d-4fe7-bb10-cb2a42320640
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1292178463 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.1292178463
Directory /workspace/0.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.618104597
Short name T168
Test name
Test status
Simulation time 336854470000 ps
CPU time 910.12 seconds
Started Aug 02 04:23:25 PM PDT 24
Finished Aug 02 05:01:10 PM PDT 24
Peak memory 160660 kb
Host smart-5bdbafb6-5f6d-4839-a74a-3d8e317fd31e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=618104597 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.618104597
Directory /workspace/10.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.1858529422
Short name T173
Test name
Test status
Simulation time 336640870000 ps
CPU time 908.32 seconds
Started Aug 02 04:23:35 PM PDT 24
Finished Aug 02 05:00:55 PM PDT 24
Peak memory 160652 kb
Host smart-81443d1b-d4c9-4ef9-ab4d-77d780836c35
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1858529422 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.1858529422
Directory /workspace/11.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.235247103
Short name T175
Test name
Test status
Simulation time 336446910000 ps
CPU time 738.98 seconds
Started Aug 02 04:23:23 PM PDT 24
Finished Aug 02 04:54:29 PM PDT 24
Peak memory 160696 kb
Host smart-767b904b-6796-432e-9637-600dac0b233d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=235247103 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.235247103
Directory /workspace/12.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.689128339
Short name T24
Test name
Test status
Simulation time 336538630000 ps
CPU time 731.59 seconds
Started Aug 02 04:23:27 PM PDT 24
Finished Aug 02 04:54:11 PM PDT 24
Peak memory 160696 kb
Host smart-4bba901a-583e-4d0e-b14a-f6f7826d967e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=689128339 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.689128339
Directory /workspace/13.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.4165759550
Short name T26
Test name
Test status
Simulation time 336373150000 ps
CPU time 731.73 seconds
Started Aug 02 04:23:23 PM PDT 24
Finished Aug 02 04:54:07 PM PDT 24
Peak memory 160708 kb
Host smart-afc3a42c-3351-4c35-8e9c-1589912e4d2d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4165759550 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.4165759550
Directory /workspace/14.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.414091265
Short name T192
Test name
Test status
Simulation time 336946770000 ps
CPU time 927.76 seconds
Started Aug 02 04:23:35 PM PDT 24
Finished Aug 02 05:01:17 PM PDT 24
Peak memory 160644 kb
Host smart-2a80c2fd-90f5-4a78-9bba-f02425728f72
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=414091265 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.414091265
Directory /workspace/15.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.3009076356
Short name T28
Test name
Test status
Simulation time 336769450000 ps
CPU time 747.8 seconds
Started Aug 02 04:23:24 PM PDT 24
Finished Aug 02 04:54:45 PM PDT 24
Peak memory 160708 kb
Host smart-ec77fc82-53e0-4920-a524-234d02f40915
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3009076356 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.3009076356
Directory /workspace/16.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.1005722095
Short name T200
Test name
Test status
Simulation time 336609790000 ps
CPU time 842.65 seconds
Started Aug 02 04:23:25 PM PDT 24
Finished Aug 02 04:58:44 PM PDT 24
Peak memory 160672 kb
Host smart-48b8f7c1-38d9-4cab-a876-54feaaf8dfd5
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1005722095 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.1005722095
Directory /workspace/17.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.1728931813
Short name T187
Test name
Test status
Simulation time 336746210000 ps
CPU time 866.77 seconds
Started Aug 02 04:23:23 PM PDT 24
Finished Aug 02 04:59:11 PM PDT 24
Peak memory 160652 kb
Host smart-b2dbe1ac-8823-484c-add2-216689f398b3
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1728931813 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.1728931813
Directory /workspace/18.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.82828742
Short name T198
Test name
Test status
Simulation time 337060230000 ps
CPU time 928.39 seconds
Started Aug 02 04:23:25 PM PDT 24
Finished Aug 02 05:01:22 PM PDT 24
Peak memory 160656 kb
Host smart-6c295405-3afd-4ec5-a8b3-e5128e40535b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=82828742 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.82828742
Directory /workspace/19.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.3109980034
Short name T182
Test name
Test status
Simulation time 336900170000 ps
CPU time 772.22 seconds
Started Aug 02 04:23:21 PM PDT 24
Finished Aug 02 04:55:00 PM PDT 24
Peak memory 160724 kb
Host smart-f0927b58-382d-4ec9-a0dd-6d919ed339cc
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3109980034 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.3109980034
Directory /workspace/2.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.3331159003
Short name T27
Test name
Test status
Simulation time 337099330000 ps
CPU time 941.7 seconds
Started Aug 02 04:23:25 PM PDT 24
Finished Aug 02 05:01:45 PM PDT 24
Peak memory 160608 kb
Host smart-f42f289d-efce-4989-8600-0e20441c7338
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3331159003 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.3331159003
Directory /workspace/20.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.707689669
Short name T30
Test name
Test status
Simulation time 337003630000 ps
CPU time 715.23 seconds
Started Aug 02 04:24:41 PM PDT 24
Finished Aug 02 04:53:42 PM PDT 24
Peak memory 160608 kb
Host smart-7c8bbb7f-e9d6-4833-9491-c876defcf03d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=707689669 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.707689669
Directory /workspace/21.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.2862654218
Short name T162
Test name
Test status
Simulation time 336445310000 ps
CPU time 671.13 seconds
Started Aug 02 04:23:27 PM PDT 24
Finished Aug 02 04:51:07 PM PDT 24
Peak memory 160744 kb
Host smart-940f6f7b-4b67-4633-9f0e-ec5bb8e3931b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2862654218 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.2862654218
Directory /workspace/22.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.309958491
Short name T174
Test name
Test status
Simulation time 336372830000 ps
CPU time 726.02 seconds
Started Aug 02 04:24:29 PM PDT 24
Finished Aug 02 04:54:42 PM PDT 24
Peak memory 160096 kb
Host smart-e7227bcf-38b8-4885-86cd-939d99db2299
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=309958491 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.309958491
Directory /workspace/23.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.56233432
Short name T166
Test name
Test status
Simulation time 336464190000 ps
CPU time 717.94 seconds
Started Aug 02 04:24:29 PM PDT 24
Finished Aug 02 04:54:13 PM PDT 24
Peak memory 159172 kb
Host smart-3c394290-c1d5-4c5f-b519-3cc9b29f225f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=56233432 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.56233432
Directory /workspace/24.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.3403171143
Short name T163
Test name
Test status
Simulation time 336429370000 ps
CPU time 733.04 seconds
Started Aug 02 04:24:29 PM PDT 24
Finished Aug 02 04:54:48 PM PDT 24
Peak memory 159172 kb
Host smart-4d0c0a77-f8e9-4fe5-b461-1b9a3812beb3
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3403171143 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.3403171143
Directory /workspace/25.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.2334246765
Short name T179
Test name
Test status
Simulation time 336953270000 ps
CPU time 678.45 seconds
Started Aug 02 04:23:34 PM PDT 24
Finished Aug 02 04:51:34 PM PDT 24
Peak memory 160744 kb
Host smart-ebbed1ef-770f-4475-9d19-4d08d0a729a0
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2334246765 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.2334246765
Directory /workspace/26.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.2105267394
Short name T164
Test name
Test status
Simulation time 336591810000 ps
CPU time 777.45 seconds
Started Aug 02 04:23:40 PM PDT 24
Finished Aug 02 04:55:31 PM PDT 24
Peak memory 160744 kb
Host smart-b80384c5-3ef7-41b8-a057-145c5efb51f0
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2105267394 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.2105267394
Directory /workspace/27.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.4108694330
Short name T176
Test name
Test status
Simulation time 336823210000 ps
CPU time 750.39 seconds
Started Aug 02 04:23:32 PM PDT 24
Finished Aug 02 04:54:29 PM PDT 24
Peak memory 160696 kb
Host smart-6953c15c-3d3d-4baf-8b2e-21d267b8925a
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4108694330 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.4108694330
Directory /workspace/28.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.987643010
Short name T186
Test name
Test status
Simulation time 336520510000 ps
CPU time 732.18 seconds
Started Aug 02 04:23:26 PM PDT 24
Finished Aug 02 04:53:40 PM PDT 24
Peak memory 160696 kb
Host smart-8fdd9959-1151-4146-bda7-d9ff048114d9
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=987643010 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.987643010
Directory /workspace/29.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.3681437881
Short name T169
Test name
Test status
Simulation time 336551730000 ps
CPU time 756.35 seconds
Started Aug 02 04:23:21 PM PDT 24
Finished Aug 02 04:54:37 PM PDT 24
Peak memory 160724 kb
Host smart-30b06e4e-595c-43de-9bed-797e5d46b3c9
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3681437881 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.3681437881
Directory /workspace/3.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.1539067157
Short name T193
Test name
Test status
Simulation time 336639590000 ps
CPU time 772.8 seconds
Started Aug 02 04:24:25 PM PDT 24
Finished Aug 02 04:56:50 PM PDT 24
Peak memory 159016 kb
Host smart-e399275d-94d0-4f0f-89c6-f0e5d5b86657
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1539067157 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.1539067157
Directory /workspace/30.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.292729394
Short name T172
Test name
Test status
Simulation time 337116010000 ps
CPU time 826.8 seconds
Started Aug 02 04:23:34 PM PDT 24
Finished Aug 02 04:57:19 PM PDT 24
Peak memory 160696 kb
Host smart-0bc5b725-e238-4343-99f7-8dcc920f80fa
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=292729394 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.292729394
Directory /workspace/31.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.3902705400
Short name T197
Test name
Test status
Simulation time 336720870000 ps
CPU time 887.25 seconds
Started Aug 02 04:23:23 PM PDT 24
Finished Aug 02 04:59:53 PM PDT 24
Peak memory 160652 kb
Host smart-ccc664c2-210b-4404-9fa0-e4478960d63d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3902705400 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.3902705400
Directory /workspace/32.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.687447053
Short name T165
Test name
Test status
Simulation time 336907870000 ps
CPU time 757.38 seconds
Started Aug 02 04:24:26 PM PDT 24
Finished Aug 02 04:56:00 PM PDT 24
Peak memory 160204 kb
Host smart-32cf5bc5-2d33-421d-a07e-90b9031c90c9
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=687447053 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.687447053
Directory /workspace/33.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.235313040
Short name T190
Test name
Test status
Simulation time 337044690000 ps
CPU time 776.33 seconds
Started Aug 02 04:24:25 PM PDT 24
Finished Aug 02 04:56:50 PM PDT 24
Peak memory 158976 kb
Host smart-54d30d7a-d5f4-4243-8da7-ae9d670894b8
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=235313040 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.235313040
Directory /workspace/34.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.2028937152
Short name T161
Test name
Test status
Simulation time 336706630000 ps
CPU time 870.79 seconds
Started Aug 02 04:23:24 PM PDT 24
Finished Aug 02 04:59:25 PM PDT 24
Peak memory 160652 kb
Host smart-37c66292-98c5-4fac-9728-4abd179fcb22
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2028937152 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.2028937152
Directory /workspace/35.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.3477617749
Short name T188
Test name
Test status
Simulation time 336437530000 ps
CPU time 957.21 seconds
Started Aug 02 04:23:25 PM PDT 24
Finished Aug 02 05:02:09 PM PDT 24
Peak memory 160672 kb
Host smart-a4c476d5-9503-4b62-a592-4aecdf969a84
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3477617749 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.3477617749
Directory /workspace/36.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.1550827896
Short name T170
Test name
Test status
Simulation time 336453590000 ps
CPU time 952.52 seconds
Started Aug 02 04:23:34 PM PDT 24
Finished Aug 02 05:02:39 PM PDT 24
Peak memory 160672 kb
Host smart-4ca93730-9fe2-43ad-afad-f7416ab7f8ac
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1550827896 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.1550827896
Directory /workspace/37.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.2318326272
Short name T184
Test name
Test status
Simulation time 336361870000 ps
CPU time 810.66 seconds
Started Aug 02 04:24:39 PM PDT 24
Finished Aug 02 04:58:18 PM PDT 24
Peak memory 160232 kb
Host smart-59c5a6a2-c779-463d-b1c3-32907f4ee716
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2318326272 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.2318326272
Directory /workspace/38.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.2216952849
Short name T194
Test name
Test status
Simulation time 336777650000 ps
CPU time 948.56 seconds
Started Aug 02 04:23:24 PM PDT 24
Finished Aug 02 05:01:59 PM PDT 24
Peak memory 160600 kb
Host smart-6cfc5592-4e0c-4949-b7f7-56876c37d2b3
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2216952849 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.2216952849
Directory /workspace/39.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.1370050244
Short name T195
Test name
Test status
Simulation time 336812650000 ps
CPU time 738.3 seconds
Started Aug 02 04:23:22 PM PDT 24
Finished Aug 02 04:53:32 PM PDT 24
Peak memory 160724 kb
Host smart-53cdd3cd-0072-4514-86c6-5266da954dc4
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1370050244 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.1370050244
Directory /workspace/4.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.584339752
Short name T23
Test name
Test status
Simulation time 336406910000 ps
CPU time 760.49 seconds
Started Aug 02 04:23:37 PM PDT 24
Finished Aug 02 04:54:54 PM PDT 24
Peak memory 160728 kb
Host smart-0aa0f45f-d03d-4baf-bc18-3f2177525b38
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=584339752 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.584339752
Directory /workspace/40.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.2284412334
Short name T189
Test name
Test status
Simulation time 337060030000 ps
CPU time 739.95 seconds
Started Aug 02 04:24:29 PM PDT 24
Finished Aug 02 04:55:23 PM PDT 24
Peak memory 158788 kb
Host smart-142355c7-bfcd-4aa7-85a4-bbcc102101d8
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2284412334 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.2284412334
Directory /workspace/41.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.2606458592
Short name T183
Test name
Test status
Simulation time 336700110000 ps
CPU time 763.03 seconds
Started Aug 02 04:23:37 PM PDT 24
Finished Aug 02 04:55:01 PM PDT 24
Peak memory 160728 kb
Host smart-fcdbdb31-914f-4f3d-994a-4899324630df
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2606458592 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.2606458592
Directory /workspace/42.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.2222767187
Short name T196
Test name
Test status
Simulation time 336427450000 ps
CPU time 768.35 seconds
Started Aug 02 04:24:42 PM PDT 24
Finished Aug 02 04:56:17 PM PDT 24
Peak memory 160624 kb
Host smart-d2a97113-6047-4b15-a4f3-ecd537538770
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2222767187 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.2222767187
Directory /workspace/43.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.3739538877
Short name T180
Test name
Test status
Simulation time 336762970000 ps
CPU time 781.29 seconds
Started Aug 02 04:24:42 PM PDT 24
Finished Aug 02 04:56:33 PM PDT 24
Peak memory 160624 kb
Host smart-c4a00d49-235e-4a0b-b030-48c900d94b59
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3739538877 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.3739538877
Directory /workspace/44.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.3305163539
Short name T167
Test name
Test status
Simulation time 336734650000 ps
CPU time 735.4 seconds
Started Aug 02 04:24:26 PM PDT 24
Finished Aug 02 04:54:34 PM PDT 24
Peak memory 159564 kb
Host smart-1d19f845-056e-4b4c-b354-1c24e4d70294
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3305163539 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.3305163539
Directory /workspace/45.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.1753100350
Short name T199
Test name
Test status
Simulation time 336618650000 ps
CPU time 728.7 seconds
Started Aug 02 04:23:24 PM PDT 24
Finished Aug 02 04:53:16 PM PDT 24
Peak memory 160664 kb
Host smart-25e74692-5268-4ac8-a2ac-39dd080d72e2
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1753100350 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.1753100350
Directory /workspace/46.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.2755236444
Short name T22
Test name
Test status
Simulation time 336872970000 ps
CPU time 722.2 seconds
Started Aug 02 04:24:26 PM PDT 24
Finished Aug 02 04:54:11 PM PDT 24
Peak memory 159676 kb
Host smart-ba70e88e-89ce-4fc1-ad3f-cd27de56e906
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2755236444 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.2755236444
Directory /workspace/47.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.3523376739
Short name T191
Test name
Test status
Simulation time 337036850000 ps
CPU time 923.17 seconds
Started Aug 02 04:23:25 PM PDT 24
Finished Aug 02 05:01:06 PM PDT 24
Peak memory 160672 kb
Host smart-1a0ade87-231c-42ab-8b40-c7abb04aebe0
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3523376739 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.3523376739
Directory /workspace/48.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.3233411658
Short name T171
Test name
Test status
Simulation time 336833230000 ps
CPU time 728.26 seconds
Started Aug 02 04:23:25 PM PDT 24
Finished Aug 02 04:53:37 PM PDT 24
Peak memory 160692 kb
Host smart-276912a9-f0d3-4381-b0b2-ab4ebdade991
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3233411658 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.3233411658
Directory /workspace/49.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.1310218287
Short name T177
Test name
Test status
Simulation time 336370750000 ps
CPU time 687.72 seconds
Started Aug 02 04:23:14 PM PDT 24
Finished Aug 02 04:51:53 PM PDT 24
Peak memory 160652 kb
Host smart-85553f34-766b-4265-9fc4-0c651b74963d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1310218287 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.1310218287
Directory /workspace/5.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.2925767497
Short name T178
Test name
Test status
Simulation time 336659490000 ps
CPU time 701.18 seconds
Started Aug 02 04:23:15 PM PDT 24
Finished Aug 02 04:52:22 PM PDT 24
Peak memory 160652 kb
Host smart-fcca3877-d2de-4daa-8be0-3195a4e1654f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2925767497 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.2925767497
Directory /workspace/6.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.3337657112
Short name T181
Test name
Test status
Simulation time 337116090000 ps
CPU time 628.76 seconds
Started Aug 02 04:23:11 PM PDT 24
Finished Aug 02 04:48:49 PM PDT 24
Peak memory 160716 kb
Host smart-4b14f9c3-8cbc-440d-9282-c37c4a983843
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3337657112 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.3337657112
Directory /workspace/7.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.2461221509
Short name T29
Test name
Test status
Simulation time 336423970000 ps
CPU time 923.44 seconds
Started Aug 02 04:23:14 PM PDT 24
Finished Aug 02 05:00:53 PM PDT 24
Peak memory 160720 kb
Host smart-14145c78-4ea1-40d4-a670-ce82a941ef1e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2461221509 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.2461221509
Directory /workspace/8.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.1476949108
Short name T21
Test name
Test status
Simulation time 336700890000 ps
CPU time 917.7 seconds
Started Aug 02 04:23:14 PM PDT 24
Finished Aug 02 05:00:59 PM PDT 24
Peak memory 160720 kb
Host smart-80c8236d-8ed5-4b56-a9fb-e24949bba1a8
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1476949108 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.1476949108
Directory /workspace/9.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.665697750
Short name T154
Test name
Test status
Simulation time 1481950000 ps
CPU time 4.46 seconds
Started Aug 02 04:23:16 PM PDT 24
Finished Aug 02 04:23:26 PM PDT 24
Peak memory 166300 kb
Host smart-e161ae77-e3ee-47c3-91af-1fc768cfb46f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=665697750 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.665697750
Directory /workspace/0.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.2921035394
Short name T138
Test name
Test status
Simulation time 1519310000 ps
CPU time 4.47 seconds
Started Aug 02 04:23:16 PM PDT 24
Finished Aug 02 04:23:26 PM PDT 24
Peak memory 164680 kb
Host smart-b21a4e66-a90b-41ac-b835-cf59c87fb325
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2921035394 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.2921035394
Directory /workspace/1.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.1601467114
Short name T137
Test name
Test status
Simulation time 1589350000 ps
CPU time 4.63 seconds
Started Aug 02 04:24:55 PM PDT 24
Finished Aug 02 04:25:06 PM PDT 24
Peak memory 164772 kb
Host smart-6d19605b-4119-4430-907a-da7170c67ae3
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1601467114 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.1601467114
Directory /workspace/10.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.4293079458
Short name T140
Test name
Test status
Simulation time 1621270000 ps
CPU time 5.34 seconds
Started Aug 02 04:23:37 PM PDT 24
Finished Aug 02 04:23:49 PM PDT 24
Peak memory 164820 kb
Host smart-1a5a17b2-0826-4410-b963-2ac21690a8b1
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4293079458 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.4293079458
Directory /workspace/11.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.3360147383
Short name T114
Test name
Test status
Simulation time 1579330000 ps
CPU time 4.61 seconds
Started Aug 02 04:24:41 PM PDT 24
Finished Aug 02 04:24:52 PM PDT 24
Peak memory 163316 kb
Host smart-78f8324e-6aca-479c-8a20-e80c96f6c642
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3360147383 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.3360147383
Directory /workspace/12.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.1158827632
Short name T126
Test name
Test status
Simulation time 1296870000 ps
CPU time 2.82 seconds
Started Aug 02 04:23:27 PM PDT 24
Finished Aug 02 04:23:33 PM PDT 24
Peak memory 164852 kb
Host smart-2d96eb6c-5c32-4266-a3b7-9d6879c4274d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1158827632 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.1158827632
Directory /workspace/13.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.170682519
Short name T128
Test name
Test status
Simulation time 1529490000 ps
CPU time 3.8 seconds
Started Aug 02 04:24:42 PM PDT 24
Finished Aug 02 04:24:51 PM PDT 24
Peak memory 164344 kb
Host smart-3c59f413-5184-4fa8-a463-002742fbed1f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=170682519 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.170682519
Directory /workspace/14.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.367833184
Short name T133
Test name
Test status
Simulation time 1246330000 ps
CPU time 3.33 seconds
Started Aug 02 04:24:42 PM PDT 24
Finished Aug 02 04:24:50 PM PDT 24
Peak memory 164580 kb
Host smart-a680e6ea-ffa5-453e-a4fe-31d4b97100b7
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=367833184 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.367833184
Directory /workspace/15.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.3569064094
Short name T116
Test name
Test status
Simulation time 1374030000 ps
CPU time 3.43 seconds
Started Aug 02 04:24:42 PM PDT 24
Finished Aug 02 04:24:50 PM PDT 24
Peak memory 164564 kb
Host smart-d4654e1a-2d93-40c9-8791-13d253d7cee9
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3569064094 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.3569064094
Directory /workspace/16.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.3525661886
Short name T125
Test name
Test status
Simulation time 1606130000 ps
CPU time 4.76 seconds
Started Aug 02 04:23:31 PM PDT 24
Finished Aug 02 04:23:42 PM PDT 24
Peak memory 164812 kb
Host smart-64ce21f3-6de1-44a5-8bd3-b8e1ae14dc34
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3525661886 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.3525661886
Directory /workspace/17.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.2066761870
Short name T155
Test name
Test status
Simulation time 1478430000 ps
CPU time 4.77 seconds
Started Aug 02 04:23:38 PM PDT 24
Finished Aug 02 04:23:48 PM PDT 24
Peak memory 164812 kb
Host smart-cffca20f-3a69-43f7-98f2-259c51acd33b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2066761870 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.2066761870
Directory /workspace/18.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.1942916140
Short name T158
Test name
Test status
Simulation time 1570790000 ps
CPU time 3.58 seconds
Started Aug 02 04:24:27 PM PDT 24
Finished Aug 02 04:24:35 PM PDT 24
Peak memory 164484 kb
Host smart-791d1d07-7451-47b0-8976-900a9bffba85
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1942916140 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.1942916140
Directory /workspace/19.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.1331480631
Short name T136
Test name
Test status
Simulation time 1368910000 ps
CPU time 4.03 seconds
Started Aug 02 04:23:14 PM PDT 24
Finished Aug 02 04:23:24 PM PDT 24
Peak memory 164700 kb
Host smart-c85d0b67-5f51-413a-9012-13137b7e9b37
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1331480631 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.1331480631
Directory /workspace/2.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.1171361639
Short name T130
Test name
Test status
Simulation time 1211970000 ps
CPU time 3.1 seconds
Started Aug 02 04:23:37 PM PDT 24
Finished Aug 02 04:23:43 PM PDT 24
Peak memory 164820 kb
Host smart-f3b2865e-f227-48fa-b7a2-3c584ce434fd
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1171361639 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.1171361639
Directory /workspace/20.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.1200897263
Short name T135
Test name
Test status
Simulation time 1575290000 ps
CPU time 4.45 seconds
Started Aug 02 04:23:24 PM PDT 24
Finished Aug 02 04:23:35 PM PDT 24
Peak memory 164820 kb
Host smart-b5ad2f63-b8af-4430-a4eb-0fdb10d37039
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1200897263 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.1200897263
Directory /workspace/21.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.909930823
Short name T119
Test name
Test status
Simulation time 1420030000 ps
CPU time 4.37 seconds
Started Aug 02 04:24:44 PM PDT 24
Finished Aug 02 04:24:53 PM PDT 24
Peak memory 164780 kb
Host smart-0ee5ab26-8cf9-4a74-b21c-2a046009a415
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=909930823 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.909930823
Directory /workspace/22.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.3415881209
Short name T118
Test name
Test status
Simulation time 1525010000 ps
CPU time 3.74 seconds
Started Aug 02 04:23:35 PM PDT 24
Finished Aug 02 04:23:43 PM PDT 24
Peak memory 164820 kb
Host smart-5cc034e3-674a-4331-9d62-38d6952bc5de
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3415881209 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.3415881209
Directory /workspace/23.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.2050053969
Short name T127
Test name
Test status
Simulation time 1214310000 ps
CPU time 2.65 seconds
Started Aug 02 04:24:29 PM PDT 24
Finished Aug 02 04:24:35 PM PDT 24
Peak memory 164508 kb
Host smart-bc765995-e671-4607-a9ac-97f47c2b0973
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2050053969 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.2050053969
Directory /workspace/24.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.3485359581
Short name T112
Test name
Test status
Simulation time 1367870000 ps
CPU time 3.79 seconds
Started Aug 02 04:24:43 PM PDT 24
Finished Aug 02 04:24:51 PM PDT 24
Peak memory 164688 kb
Host smart-3906fb31-3f9c-4773-ab0e-74ce0551cd46
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3485359581 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.3485359581
Directory /workspace/25.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.3881468659
Short name T124
Test name
Test status
Simulation time 1490990000 ps
CPU time 3.89 seconds
Started Aug 02 04:24:41 PM PDT 24
Finished Aug 02 04:24:50 PM PDT 24
Peak memory 164644 kb
Host smart-1ac2a068-5ed9-403c-8ab0-542bcf37c6ca
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3881468659 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.3881468659
Directory /workspace/26.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.2457804705
Short name T156
Test name
Test status
Simulation time 1506390000 ps
CPU time 3.96 seconds
Started Aug 02 04:24:41 PM PDT 24
Finished Aug 02 04:24:50 PM PDT 24
Peak memory 164644 kb
Host smart-d2a5524f-c8dd-435e-8cab-0310f5bc5fb1
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2457804705 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.2457804705
Directory /workspace/27.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.3542186650
Short name T122
Test name
Test status
Simulation time 1316150000 ps
CPU time 2.69 seconds
Started Aug 02 04:24:25 PM PDT 24
Finished Aug 02 04:24:31 PM PDT 24
Peak memory 163324 kb
Host smart-97cbc870-c2e2-419c-9735-e9da6fe19905
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3542186650 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.3542186650
Directory /workspace/28.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.1151858765
Short name T123
Test name
Test status
Simulation time 1367410000 ps
CPU time 4.21 seconds
Started Aug 02 04:24:30 PM PDT 24
Finished Aug 02 04:24:40 PM PDT 24
Peak memory 164504 kb
Host smart-411e6678-1f70-4eb7-9284-4b8deabcc6f7
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1151858765 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.1151858765
Directory /workspace/29.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.3107068894
Short name T157
Test name
Test status
Simulation time 1246410000 ps
CPU time 3.57 seconds
Started Aug 02 04:23:14 PM PDT 24
Finished Aug 02 04:23:22 PM PDT 24
Peak memory 164700 kb
Host smart-b80906be-d718-46c5-9ecc-be9fb4dc139c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3107068894 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.3107068894
Directory /workspace/3.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.690999371
Short name T134
Test name
Test status
Simulation time 1520310000 ps
CPU time 3.63 seconds
Started Aug 02 04:24:27 PM PDT 24
Finished Aug 02 04:24:35 PM PDT 24
Peak memory 164520 kb
Host smart-1354fe97-90d7-4fc1-9313-9ef5ebabfe67
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=690999371 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.690999371
Directory /workspace/30.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.3145487922
Short name T152
Test name
Test status
Simulation time 1473090000 ps
CPU time 3.51 seconds
Started Aug 02 04:24:27 PM PDT 24
Finished Aug 02 04:24:34 PM PDT 24
Peak memory 164516 kb
Host smart-4a7aabdc-c371-4ff5-a9ed-ebbad00a1f53
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3145487922 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.3145487922
Directory /workspace/31.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.2420433253
Short name T113
Test name
Test status
Simulation time 1565190000 ps
CPU time 3.82 seconds
Started Aug 02 04:24:30 PM PDT 24
Finished Aug 02 04:24:39 PM PDT 24
Peak memory 164408 kb
Host smart-e709f706-2279-4ac1-b42d-764568eb5ce1
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2420433253 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.2420433253
Directory /workspace/32.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.1386047166
Short name T150
Test name
Test status
Simulation time 1492310000 ps
CPU time 3.43 seconds
Started Aug 02 04:24:44 PM PDT 24
Finished Aug 02 04:24:52 PM PDT 24
Peak memory 164636 kb
Host smart-5e53e8a7-6b8d-4521-aedf-4e22f7632a4d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1386047166 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.1386047166
Directory /workspace/33.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.615079950
Short name T151
Test name
Test status
Simulation time 1576470000 ps
CPU time 4.16 seconds
Started Aug 02 04:24:29 PM PDT 24
Finished Aug 02 04:24:39 PM PDT 24
Peak memory 163444 kb
Host smart-59706909-cdac-4ada-a1e3-277bb841a109
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=615079950 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.615079950
Directory /workspace/34.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.2768827696
Short name T145
Test name
Test status
Simulation time 1372090000 ps
CPU time 3.05 seconds
Started Aug 02 04:24:42 PM PDT 24
Finished Aug 02 04:24:49 PM PDT 24
Peak memory 164684 kb
Host smart-d02bdc08-b027-47d6-b649-af2f9121d6e2
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2768827696 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.2768827696
Directory /workspace/35.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.1363729225
Short name T132
Test name
Test status
Simulation time 1399490000 ps
CPU time 3.11 seconds
Started Aug 02 04:24:42 PM PDT 24
Finished Aug 02 04:24:49 PM PDT 24
Peak memory 164684 kb
Host smart-ad9275bf-a373-491f-8a33-5a27a05f7fcc
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1363729225 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.1363729225
Directory /workspace/36.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1550399582
Short name T149
Test name
Test status
Simulation time 1520170000 ps
CPU time 3.32 seconds
Started Aug 02 04:24:41 PM PDT 24
Finished Aug 02 04:24:48 PM PDT 24
Peak memory 164684 kb
Host smart-7072a06c-886e-4aca-9570-bb41507faa6e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1550399582 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.1550399582
Directory /workspace/37.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.54003782
Short name T148
Test name
Test status
Simulation time 1414570000 ps
CPU time 3.83 seconds
Started Aug 02 04:24:42 PM PDT 24
Finished Aug 02 04:24:51 PM PDT 24
Peak memory 164648 kb
Host smart-a7072900-5e55-42aa-a6a3-d9f6a07033d0
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=54003782 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.54003782
Directory /workspace/38.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.1487083550
Short name T142
Test name
Test status
Simulation time 1567350000 ps
CPU time 4.23 seconds
Started Aug 02 04:24:41 PM PDT 24
Finished Aug 02 04:24:50 PM PDT 24
Peak memory 164460 kb
Host smart-1b21c915-3260-4b04-87a1-415ef595a4dc
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1487083550 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.1487083550
Directory /workspace/39.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3527915165
Short name T160
Test name
Test status
Simulation time 1325430000 ps
CPU time 3.92 seconds
Started Aug 02 04:23:15 PM PDT 24
Finished Aug 02 04:23:24 PM PDT 24
Peak memory 164700 kb
Host smart-8aa2bdf2-e20f-428f-b6f5-9b2a26fd9886
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3527915165 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.3527915165
Directory /workspace/4.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.3919559928
Short name T120
Test name
Test status
Simulation time 1396590000 ps
CPU time 4.44 seconds
Started Aug 02 04:24:03 PM PDT 24
Finished Aug 02 04:24:12 PM PDT 24
Peak memory 164808 kb
Host smart-6fa042df-643f-4498-aa19-55ed151eb9bf
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3919559928 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.3919559928
Directory /workspace/40.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.4142038902
Short name T144
Test name
Test status
Simulation time 1341350000 ps
CPU time 2.97 seconds
Started Aug 02 04:24:29 PM PDT 24
Finished Aug 02 04:24:36 PM PDT 24
Peak memory 164448 kb
Host smart-f1b0275c-bd16-4c45-bae9-634b467edc4e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4142038902 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.4142038902
Directory /workspace/41.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.3777082487
Short name T121
Test name
Test status
Simulation time 1455510000 ps
CPU time 3.46 seconds
Started Aug 02 04:24:11 PM PDT 24
Finished Aug 02 04:24:19 PM PDT 24
Peak memory 164840 kb
Host smart-0027c193-f8aa-4fab-83ef-0e7f34e3af28
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3777082487 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.3777082487
Directory /workspace/42.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.2820948397
Short name T129
Test name
Test status
Simulation time 1533370000 ps
CPU time 4.82 seconds
Started Aug 02 04:25:18 PM PDT 24
Finished Aug 02 04:25:29 PM PDT 24
Peak memory 164700 kb
Host smart-bfd94d64-44ab-4b55-97dd-d77d23c1850a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2820948397 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.2820948397
Directory /workspace/43.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.3043071067
Short name T115
Test name
Test status
Simulation time 1480870000 ps
CPU time 3.51 seconds
Started Aug 02 04:24:10 PM PDT 24
Finished Aug 02 04:24:18 PM PDT 24
Peak memory 164772 kb
Host smart-d7fed4ca-37c1-4b48-bbbf-94bd455bbb5a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3043071067 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.3043071067
Directory /workspace/44.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.3558086640
Short name T147
Test name
Test status
Simulation time 1420050000 ps
CPU time 3.56 seconds
Started Aug 02 04:24:12 PM PDT 24
Finished Aug 02 04:24:20 PM PDT 24
Peak memory 164744 kb
Host smart-a838427f-f2df-48c2-9bfd-65d72b72f00c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3558086640 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.3558086640
Directory /workspace/45.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.2774991519
Short name T117
Test name
Test status
Simulation time 1257370000 ps
CPU time 4.24 seconds
Started Aug 02 04:25:17 PM PDT 24
Finished Aug 02 04:25:27 PM PDT 24
Peak memory 164700 kb
Host smart-b565dc3c-eeb0-4cde-b99e-7ed711b4e9c7
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2774991519 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.2774991519
Directory /workspace/46.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.83935198
Short name T153
Test name
Test status
Simulation time 1519150000 ps
CPU time 4.75 seconds
Started Aug 02 04:24:14 PM PDT 24
Finished Aug 02 04:24:24 PM PDT 24
Peak memory 164752 kb
Host smart-9150ba33-3c6f-4dda-a8f7-e0ad91acd9e9
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=83935198 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.83935198
Directory /workspace/47.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.1672779421
Short name T111
Test name
Test status
Simulation time 1499170000 ps
CPU time 4.65 seconds
Started Aug 02 04:25:01 PM PDT 24
Finished Aug 02 04:25:12 PM PDT 24
Peak memory 164744 kb
Host smart-8a6dacfc-6cf4-413f-af95-f996a7686fe2
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1672779421 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.1672779421
Directory /workspace/48.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.2258171274
Short name T146
Test name
Test status
Simulation time 1452510000 ps
CPU time 4.36 seconds
Started Aug 02 04:24:09 PM PDT 24
Finished Aug 02 04:24:19 PM PDT 24
Peak memory 164840 kb
Host smart-998f04db-1f24-4f80-b26b-87942f441092
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2258171274 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.2258171274
Directory /workspace/49.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.1232220686
Short name T143
Test name
Test status
Simulation time 1414010000 ps
CPU time 3.37 seconds
Started Aug 02 04:23:13 PM PDT 24
Finished Aug 02 04:23:20 PM PDT 24
Peak memory 164796 kb
Host smart-ff2b0b98-03cd-4129-840b-9b868e286ff6
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1232220686 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.1232220686
Directory /workspace/5.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.3169856914
Short name T139
Test name
Test status
Simulation time 1357530000 ps
CPU time 3.85 seconds
Started Aug 02 04:23:15 PM PDT 24
Finished Aug 02 04:23:24 PM PDT 24
Peak memory 164676 kb
Host smart-1a1aff59-7709-46b1-8431-b933aedcf3bd
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3169856914 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.3169856914
Directory /workspace/6.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.3561285601
Short name T131
Test name
Test status
Simulation time 1587170000 ps
CPU time 3.77 seconds
Started Aug 02 04:23:19 PM PDT 24
Finished Aug 02 04:23:27 PM PDT 24
Peak memory 164832 kb
Host smart-6e43b4b1-4ea6-4893-bcd9-ed58d222e374
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3561285601 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.3561285601
Directory /workspace/7.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1475646448
Short name T159
Test name
Test status
Simulation time 1147250000 ps
CPU time 2.97 seconds
Started Aug 02 04:23:14 PM PDT 24
Finished Aug 02 04:23:22 PM PDT 24
Peak memory 164796 kb
Host smart-c25d083b-fd3c-4b2d-b62c-a82959ef4165
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1475646448 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.1475646448
Directory /workspace/8.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2238543311
Short name T141
Test name
Test status
Simulation time 1532470000 ps
CPU time 3.63 seconds
Started Aug 02 04:23:21 PM PDT 24
Finished Aug 02 04:23:30 PM PDT 24
Peak memory 164832 kb
Host smart-812d5c9f-fb7c-4b09-97e9-37a9c805e542
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2238543311 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.2238543311
Directory /workspace/9.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.3290817015
Short name T58
Test name
Test status
Simulation time 1590970000 ps
CPU time 5.05 seconds
Started Aug 02 04:23:13 PM PDT 24
Finished Aug 02 04:23:24 PM PDT 24
Peak memory 164720 kb
Host smart-98e6b931-160a-473f-b85a-2802b1dc5105
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3290817015 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.3290817015
Directory /workspace/0.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.865621546
Short name T64
Test name
Test status
Simulation time 1245830000 ps
CPU time 3.88 seconds
Started Aug 02 04:23:14 PM PDT 24
Finished Aug 02 04:23:22 PM PDT 24
Peak memory 164732 kb
Host smart-cc32e319-0de3-47af-941d-30ce24baa224
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=865621546 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.865621546
Directory /workspace/1.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.3523945790
Short name T67
Test name
Test status
Simulation time 1487250000 ps
CPU time 4.41 seconds
Started Aug 02 04:23:25 PM PDT 24
Finished Aug 02 04:23:35 PM PDT 24
Peak memory 164820 kb
Host smart-add1eba5-f3f7-4608-956c-bab973de812f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3523945790 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.3523945790
Directory /workspace/10.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.581023081
Short name T39
Test name
Test status
Simulation time 1451870000 ps
CPU time 4.25 seconds
Started Aug 02 04:24:44 PM PDT 24
Finished Aug 02 04:24:53 PM PDT 24
Peak memory 164780 kb
Host smart-10ee16d3-692a-4784-a522-eb8882c0e0cd
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=581023081 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.581023081
Directory /workspace/11.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.3757561863
Short name T32
Test name
Test status
Simulation time 1438510000 ps
CPU time 4.24 seconds
Started Aug 02 04:23:25 PM PDT 24
Finished Aug 02 04:23:35 PM PDT 24
Peak memory 164820 kb
Host smart-62ee3999-4ebd-4015-bb6a-73bf8d3e04a4
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3757561863 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.3757561863
Directory /workspace/12.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.4042334490
Short name T49
Test name
Test status
Simulation time 1397530000 ps
CPU time 4.06 seconds
Started Aug 02 04:23:24 PM PDT 24
Finished Aug 02 04:23:33 PM PDT 24
Peak memory 164820 kb
Host smart-5e1fbd04-e62a-444b-9090-fbfa4737c527
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4042334490 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.4042334490
Directory /workspace/13.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.2197290650
Short name T51
Test name
Test status
Simulation time 1300070000 ps
CPU time 3.4 seconds
Started Aug 02 04:24:40 PM PDT 24
Finished Aug 02 04:24:48 PM PDT 24
Peak memory 164644 kb
Host smart-b7902443-a236-4858-be89-b8ff9646f01e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2197290650 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.2197290650
Directory /workspace/14.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.3923759061
Short name T60
Test name
Test status
Simulation time 1439230000 ps
CPU time 3.03 seconds
Started Aug 02 04:24:28 PM PDT 24
Finished Aug 02 04:24:35 PM PDT 24
Peak memory 164444 kb
Host smart-c3c5d768-abd5-4918-a12b-08fe38523e34
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3923759061 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.3923759061
Directory /workspace/15.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.2250491587
Short name T37
Test name
Test status
Simulation time 1278890000 ps
CPU time 3.31 seconds
Started Aug 02 04:24:40 PM PDT 24
Finished Aug 02 04:24:47 PM PDT 24
Peak memory 164644 kb
Host smart-c9bb6500-d4ea-4d69-846f-6ca9702faa93
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2250491587 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.2250491587
Directory /workspace/16.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.3195833202
Short name T34
Test name
Test status
Simulation time 1471470000 ps
CPU time 4.07 seconds
Started Aug 02 04:24:43 PM PDT 24
Finished Aug 02 04:24:52 PM PDT 24
Peak memory 164688 kb
Host smart-19ac7aff-38a4-4907-b8e4-654fba02714a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3195833202 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.3195833202
Directory /workspace/17.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.1381784344
Short name T35
Test name
Test status
Simulation time 1415650000 ps
CPU time 3.88 seconds
Started Aug 02 04:24:30 PM PDT 24
Finished Aug 02 04:24:39 PM PDT 24
Peak memory 163896 kb
Host smart-c7fd3840-5d73-481b-9989-3735bf74ec39
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1381784344 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.1381784344
Directory /workspace/18.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.3698057264
Short name T70
Test name
Test status
Simulation time 1483430000 ps
CPU time 4.14 seconds
Started Aug 02 04:24:29 PM PDT 24
Finished Aug 02 04:24:39 PM PDT 24
Peak memory 163116 kb
Host smart-e1103b18-6530-4254-9a29-4cfc66974a86
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3698057264 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.3698057264
Directory /workspace/19.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.2030212975
Short name T31
Test name
Test status
Simulation time 1553170000 ps
CPU time 4.58 seconds
Started Aug 02 04:23:14 PM PDT 24
Finished Aug 02 04:23:25 PM PDT 24
Peak memory 164656 kb
Host smart-7f7f9b87-5a9a-4f70-b588-c7d4024e68b1
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2030212975 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.2030212975
Directory /workspace/2.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.2677340509
Short name T50
Test name
Test status
Simulation time 1551570000 ps
CPU time 4.2 seconds
Started Aug 02 04:24:29 PM PDT 24
Finished Aug 02 04:24:39 PM PDT 24
Peak memory 163192 kb
Host smart-7da303c3-28fc-4be2-84a9-e2f907031819
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2677340509 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.2677340509
Directory /workspace/21.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.2976982465
Short name T33
Test name
Test status
Simulation time 1263050000 ps
CPU time 3.25 seconds
Started Aug 02 04:24:30 PM PDT 24
Finished Aug 02 04:24:37 PM PDT 24
Peak memory 164420 kb
Host smart-ab1dc988-7910-46cf-838e-fa77a84668f6
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2976982465 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.2976982465
Directory /workspace/22.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.4128124168
Short name T46
Test name
Test status
Simulation time 1301730000 ps
CPU time 3.21 seconds
Started Aug 02 04:24:29 PM PDT 24
Finished Aug 02 04:24:36 PM PDT 24
Peak memory 163728 kb
Host smart-24d2fedd-5fa9-410b-b5bc-72b566e22f69
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4128124168 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.4128124168
Directory /workspace/23.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.1304400058
Short name T7
Test name
Test status
Simulation time 1451850000 ps
CPU time 3.39 seconds
Started Aug 02 04:24:26 PM PDT 24
Finished Aug 02 04:24:34 PM PDT 24
Peak memory 164420 kb
Host smart-9a19b015-009e-43b5-bb8b-377f97430e92
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1304400058 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.1304400058
Directory /workspace/24.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.2008557878
Short name T41
Test name
Test status
Simulation time 1510170000 ps
CPU time 3.91 seconds
Started Aug 02 04:24:44 PM PDT 24
Finished Aug 02 04:24:52 PM PDT 24
Peak memory 164716 kb
Host smart-d94faf6e-5afc-4286-9cef-2caa0c71bdfb
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2008557878 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.2008557878
Directory /workspace/25.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.636272225
Short name T1
Test name
Test status
Simulation time 1619310000 ps
CPU time 3.68 seconds
Started Aug 02 04:24:29 PM PDT 24
Finished Aug 02 04:24:38 PM PDT 24
Peak memory 163140 kb
Host smart-826263d8-6744-4dc3-a4c8-cf5e8dc12cf0
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=636272225 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.636272225
Directory /workspace/26.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.3690935984
Short name T8
Test name
Test status
Simulation time 1248970000 ps
CPU time 2.82 seconds
Started Aug 02 04:24:29 PM PDT 24
Finished Aug 02 04:24:35 PM PDT 24
Peak memory 164448 kb
Host smart-f5903022-b452-42d0-a4e5-d493b8e433d2
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3690935984 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.3690935984
Directory /workspace/27.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.1739616215
Short name T42
Test name
Test status
Simulation time 1503550000 ps
CPU time 3.67 seconds
Started Aug 02 04:24:41 PM PDT 24
Finished Aug 02 04:24:49 PM PDT 24
Peak memory 164460 kb
Host smart-d6c54426-92d9-4682-b801-9f1941a28b87
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1739616215 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.1739616215
Directory /workspace/28.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.1935465939
Short name T9
Test name
Test status
Simulation time 1237270000 ps
CPU time 3.5 seconds
Started Aug 02 04:24:05 PM PDT 24
Finished Aug 02 04:24:12 PM PDT 24
Peak memory 164772 kb
Host smart-ac27dc87-903c-4872-8e74-b38a77b44ab9
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1935465939 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.1935465939
Directory /workspace/29.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.1095322787
Short name T40
Test name
Test status
Simulation time 1079550000 ps
CPU time 3.33 seconds
Started Aug 02 04:23:14 PM PDT 24
Finished Aug 02 04:23:22 PM PDT 24
Peak memory 164784 kb
Host smart-b4e4d8c4-35ad-454a-9f78-a24ccdb83d6f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1095322787 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.1095322787
Directory /workspace/3.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.2665077319
Short name T36
Test name
Test status
Simulation time 1290130000 ps
CPU time 3.43 seconds
Started Aug 02 04:24:09 PM PDT 24
Finished Aug 02 04:24:17 PM PDT 24
Peak memory 164840 kb
Host smart-3195a327-f214-4871-93d0-3b8a6920b7ce
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2665077319 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.2665077319
Directory /workspace/30.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.1681970066
Short name T59
Test name
Test status
Simulation time 1419670000 ps
CPU time 3.07 seconds
Started Aug 02 04:24:28 PM PDT 24
Finished Aug 02 04:24:35 PM PDT 24
Peak memory 163328 kb
Host smart-3aabba4f-8d0e-4788-b292-ff05cdf4a54a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1681970066 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.1681970066
Directory /workspace/31.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.3347022244
Short name T55
Test name
Test status
Simulation time 1426870000 ps
CPU time 4.38 seconds
Started Aug 02 04:25:18 PM PDT 24
Finished Aug 02 04:25:28 PM PDT 24
Peak memory 164700 kb
Host smart-20c6a261-c7d9-484b-8082-74e596fc80f7
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3347022244 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.3347022244
Directory /workspace/32.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.1091852824
Short name T13
Test name
Test status
Simulation time 1363590000 ps
CPU time 3.77 seconds
Started Aug 02 04:24:10 PM PDT 24
Finished Aug 02 04:24:18 PM PDT 24
Peak memory 164744 kb
Host smart-0b1e2a4b-f4fc-4556-b7c2-b1faec74176c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1091852824 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.1091852824
Directory /workspace/33.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.199378771
Short name T54
Test name
Test status
Simulation time 1359030000 ps
CPU time 4.4 seconds
Started Aug 02 04:24:13 PM PDT 24
Finished Aug 02 04:24:23 PM PDT 24
Peak memory 164760 kb
Host smart-397bc66d-bd32-49a8-bd3c-702195ab1901
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=199378771 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.199378771
Directory /workspace/34.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.2215194074
Short name T56
Test name
Test status
Simulation time 1552210000 ps
CPU time 4.81 seconds
Started Aug 02 04:24:13 PM PDT 24
Finished Aug 02 04:24:24 PM PDT 24
Peak memory 164692 kb
Host smart-96d0a678-8401-4056-879f-f4a536102c10
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2215194074 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.2215194074
Directory /workspace/35.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.2501513130
Short name T69
Test name
Test status
Simulation time 1640410000 ps
CPU time 5.35 seconds
Started Aug 02 04:25:08 PM PDT 24
Finished Aug 02 04:25:20 PM PDT 24
Peak memory 164232 kb
Host smart-797fe89e-f072-4721-8d50-e93729608cc8
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2501513130 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.2501513130
Directory /workspace/36.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.3011628023
Short name T45
Test name
Test status
Simulation time 1397250000 ps
CPU time 3.57 seconds
Started Aug 02 04:24:08 PM PDT 24
Finished Aug 02 04:24:15 PM PDT 24
Peak memory 164772 kb
Host smart-512463dd-f308-4012-bd1a-ca0b614fb613
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3011628023 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.3011628023
Directory /workspace/37.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.756672215
Short name T38
Test name
Test status
Simulation time 1615630000 ps
CPU time 3.77 seconds
Started Aug 02 04:24:05 PM PDT 24
Finished Aug 02 04:24:14 PM PDT 24
Peak memory 164768 kb
Host smart-e692f42b-dd12-45fa-8020-4d857746fae1
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=756672215 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.756672215
Directory /workspace/38.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.675661747
Short name T47
Test name
Test status
Simulation time 1485570000 ps
CPU time 5.27 seconds
Started Aug 02 04:25:07 PM PDT 24
Finished Aug 02 04:25:19 PM PDT 24
Peak memory 163604 kb
Host smart-182103af-ddd1-4f26-a43f-19195cae6d2f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=675661747 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.675661747
Directory /workspace/39.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.1602886945
Short name T65
Test name
Test status
Simulation time 1318990000 ps
CPU time 4.2 seconds
Started Aug 02 04:23:13 PM PDT 24
Finished Aug 02 04:23:23 PM PDT 24
Peak memory 164720 kb
Host smart-4cfbc97e-9689-4248-a62c-08cefe5c65ce
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1602886945 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.1602886945
Directory /workspace/4.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.1389794827
Short name T12
Test name
Test status
Simulation time 1295070000 ps
CPU time 3.69 seconds
Started Aug 02 04:23:24 PM PDT 24
Finished Aug 02 04:23:33 PM PDT 24
Peak memory 164724 kb
Host smart-fb3d109e-1199-4fa4-b561-92163d0f0c4e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1389794827 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.1389794827
Directory /workspace/40.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.756671826
Short name T62
Test name
Test status
Simulation time 1476570000 ps
CPU time 3.96 seconds
Started Aug 02 04:23:24 PM PDT 24
Finished Aug 02 04:23:33 PM PDT 24
Peak memory 164840 kb
Host smart-38a5c401-cccb-4dc0-b3a5-593e715b364e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=756671826 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.756671826
Directory /workspace/41.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.3147768001
Short name T63
Test name
Test status
Simulation time 1517330000 ps
CPU time 4.57 seconds
Started Aug 02 04:23:24 PM PDT 24
Finished Aug 02 04:23:34 PM PDT 24
Peak memory 164836 kb
Host smart-59e06b93-7caf-4013-a5f5-70be5788b636
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3147768001 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.3147768001
Directory /workspace/42.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.3711554221
Short name T66
Test name
Test status
Simulation time 1495450000 ps
CPU time 4.46 seconds
Started Aug 02 04:23:23 PM PDT 24
Finished Aug 02 04:23:33 PM PDT 24
Peak memory 164700 kb
Host smart-931cbc76-1695-4d72-842f-42eddc4c2a9b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3711554221 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.3711554221
Directory /workspace/43.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.4252492595
Short name T68
Test name
Test status
Simulation time 1593310000 ps
CPU time 4.49 seconds
Started Aug 02 04:23:24 PM PDT 24
Finished Aug 02 04:23:34 PM PDT 24
Peak memory 164724 kb
Host smart-ea1ac137-e605-4884-806a-c4c77535a192
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4252492595 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.4252492595
Directory /workspace/44.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.3695280285
Short name T53
Test name
Test status
Simulation time 1526690000 ps
CPU time 4.47 seconds
Started Aug 02 04:23:25 PM PDT 24
Finished Aug 02 04:23:35 PM PDT 24
Peak memory 164728 kb
Host smart-c26a3479-397f-4b4e-bfbf-14c0c1afed8b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3695280285 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.3695280285
Directory /workspace/45.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.724963131
Short name T43
Test name
Test status
Simulation time 1295510000 ps
CPU time 4.01 seconds
Started Aug 02 04:23:29 PM PDT 24
Finished Aug 02 04:23:38 PM PDT 24
Peak memory 164696 kb
Host smart-26680a1d-b69e-4a77-876f-cad78aa8a095
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=724963131 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.724963131
Directory /workspace/46.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.1320693363
Short name T3
Test name
Test status
Simulation time 1432910000 ps
CPU time 3.85 seconds
Started Aug 02 04:23:26 PM PDT 24
Finished Aug 02 04:23:34 PM PDT 24
Peak memory 164804 kb
Host smart-20ea0cc5-fce3-4215-b079-0377199331a3
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1320693363 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.1320693363
Directory /workspace/47.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.177232219
Short name T11
Test name
Test status
Simulation time 1607150000 ps
CPU time 5.01 seconds
Started Aug 02 04:23:24 PM PDT 24
Finished Aug 02 04:23:35 PM PDT 24
Peak memory 164668 kb
Host smart-52e3b475-a783-40fc-9ed5-bdd4dee95ab5
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=177232219 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.177232219
Directory /workspace/48.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.2617607257
Short name T61
Test name
Test status
Simulation time 1523990000 ps
CPU time 4.21 seconds
Started Aug 02 04:23:25 PM PDT 24
Finished Aug 02 04:23:35 PM PDT 24
Peak memory 164728 kb
Host smart-8ed979b6-fafe-4d8e-af36-185fa05182a4
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2617607257 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.2617607257
Directory /workspace/49.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.3071168174
Short name T57
Test name
Test status
Simulation time 1357010000 ps
CPU time 4.9 seconds
Started Aug 02 04:23:14 PM PDT 24
Finished Aug 02 04:23:25 PM PDT 24
Peak memory 164720 kb
Host smart-5f0ff53f-9e60-4f7e-87e0-7e7d0ef04fdd
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3071168174 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.3071168174
Directory /workspace/5.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.3721973655
Short name T2
Test name
Test status
Simulation time 1493350000 ps
CPU time 4.98 seconds
Started Aug 02 04:23:13 PM PDT 24
Finished Aug 02 04:23:24 PM PDT 24
Peak memory 164720 kb
Host smart-8fc9fff9-063d-4384-b5ac-54adefbe7742
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3721973655 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.3721973655
Directory /workspace/6.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.1957531284
Short name T44
Test name
Test status
Simulation time 1514930000 ps
CPU time 4.54 seconds
Started Aug 02 04:23:15 PM PDT 24
Finished Aug 02 04:23:26 PM PDT 24
Peak memory 164676 kb
Host smart-3f6b5cab-765f-49a6-8b21-e6ab935b0c4a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1957531284 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.1957531284
Directory /workspace/7.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.1599235064
Short name T52
Test name
Test status
Simulation time 1555810000 ps
CPU time 4.7 seconds
Started Aug 02 04:23:16 PM PDT 24
Finished Aug 02 04:23:26 PM PDT 24
Peak memory 164676 kb
Host smart-7438f02e-92d2-4f2b-a50f-e58272a9e65e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1599235064 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.1599235064
Directory /workspace/8.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.4272833290
Short name T48
Test name
Test status
Simulation time 1518530000 ps
CPU time 4.33 seconds
Started Aug 02 04:23:14 PM PDT 24
Finished Aug 02 04:23:24 PM PDT 24
Peak memory 164668 kb
Host smart-9dff26fd-5e0d-4dc9-a6b5-80d183577476
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4272833290 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.4272833290
Directory /workspace/9.prim_lfsr_gal_smoke/latest
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