Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.31 100.00 96.55 100.00 100.00 95.00


Total tests in report: 200
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
87.31 87.31 100.00 100.00 96.55 96.55 100.00 100.00 100.00 100.00 40.00 40.00 /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.1965998434
96.81 9.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 87.50 47.50 /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.3238384396
98.31 1.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 95.00 7.50 /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.3740953524

Tests that do not contribute to grading

Name
/workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.2654594929
/workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.2799161935
/workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.794671916
/workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.4041265898
/workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.3947192531
/workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.2746914439
/workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.1845043856
/workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.2606587059
/workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.3668418413
/workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.2241391662
/workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2293360008
/workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.957947385
/workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.2208330647
/workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.2863376120
/workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.2297749963
/workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.176700777
/workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.2488303592
/workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.2831622819
/workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.4217592683
/workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.2304765261
/workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.2066243148
/workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.2056272106
/workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.1495534403
/workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.1868227317
/workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.1836490253
/workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.4179479365
/workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.3829993485
/workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.472768902
/workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.1783041102
/workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.2016038536
/workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.2534230809
/workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.9624064
/workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.1184825929
/workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.2240730631
/workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.4203349640
/workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.2175887153
/workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.4010516353
/workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.2759012653
/workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.3657793814
/workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.3334272346
/workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.1834121813
/workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.3470698296
/workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.2931082728
/workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.1399640594
/workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.539041873
/workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.752598472
/workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.3486749975
/workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.3312267241
/workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.1088668558
/workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.3118951048
/workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.2694441698
/workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.3022197961
/workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.1718634475
/workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.1743088093
/workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.399523311
/workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.2851564200
/workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.398598124
/workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.1529794466
/workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.2672310708
/workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.2907820761
/workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.1906109922
/workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.3976399691
/workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.627301721
/workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.971547548
/workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.2222377024
/workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.1188454861
/workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.660511711
/workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.3534265014
/workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.696752041
/workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.1519128695
/workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.4009705097
/workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.2425855681
/workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.4204656643
/workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.2306611755
/workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.317218447
/workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.3841892790
/workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.2161141226
/workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.753130712
/workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.3393812234
/workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.1409182972
/workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3961867211
/workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.3306271454
/workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.3139549462
/workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.3516711922
/workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.2819642182
/workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.592384370
/workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.125536138
/workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.1509413054
/workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.780505423
/workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.3232003434
/workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.3379056341
/workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.522156698
/workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.3967244501
/workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.3380068407
/workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.2539224088
/workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.2362150551
/workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.4257106891
/workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.552706855
/workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.3709856820
/workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.487782798
/workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.2256406028
/workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.485182586
/workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.4280503448
/workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.3361023735
/workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.4221586459
/workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.1111944504
/workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.3215531677
/workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.2027079915
/workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.1289015499
/workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.114791571
/workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.2373846134
/workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.301521550
/workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.1862097694
/workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.611360818
/workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.4052013966
/workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.1356929785
/workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.4016231064
/workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.1922768503
/workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.3567968064
/workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.2504243387
/workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.339737727
/workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.2894871211
/workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.1612672710
/workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.1654595030
/workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.4086348595
/workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.1961483769
/workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.3531766262
/workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.2108082507
/workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.2021079085
/workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.2821985863
/workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.3029297974
/workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.2399847409
/workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.2330440282
/workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.513964370
/workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.53626694
/workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.2698244048
/workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.298115772
/workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.3204393074
/workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.882010648
/workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.2640073048
/workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.601465830
/workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.801768648
/workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.935396718
/workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.1097972686
/workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.4116484394
/workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.2366142477
/workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.2212753275
/workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.3588882095
/workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.2386598778
/workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.1073569248
/workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.1978963692
/workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.2298102843
/workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.2008057294
/workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.2018614677
/workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.212862089
/workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.3446590615
/workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.991893948
/workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.3687620868
/workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.2283137726
/workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.2633601420
/workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.2156152202
/workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.1069382137
/workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.929505977
/workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.1109884467
/workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.2773446400
/workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.4150806386
/workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.4083230613
/workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.161484937
/workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.2621771640
/workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.3026057391
/workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.553656221
/workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.884790887
/workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.2545757740
/workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.3964999971
/workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.3933709773
/workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.180853405
/workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.860423877
/workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.798951118
/workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.2794117877
/workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.1010999268
/workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.2101032746
/workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.409448712
/workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.1057510235
/workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.373886381
/workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.3665167260
/workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.2872556104
/workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.554575938
/workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.2745736570
/workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.1443592505
/workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.2409016540
/workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.4144740577
/workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.965750161
/workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.2473271419
/workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.188818389
/workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.4146831886
/workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.2853970087
/workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.328547164



Total test records in report: 200
tests.html | tests1.html | tests2.html | tests3.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.3665167260 Aug 03 04:20:59 PM PDT 24 Aug 03 04:21:09 PM PDT 24 1458130000 ps
T2 /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.3933709773 Aug 03 04:21:41 PM PDT 24 Aug 03 04:21:51 PM PDT 24 1534970000 ps
T3 /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.3446590615 Aug 03 04:19:48 PM PDT 24 Aug 03 04:19:59 PM PDT 24 1511290000 ps
T7 /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.2545757740 Aug 03 04:21:56 PM PDT 24 Aug 03 04:22:04 PM PDT 24 1560490000 ps
T8 /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.2283137726 Aug 03 04:22:39 PM PDT 24 Aug 03 04:22:50 PM PDT 24 1551030000 ps
T9 /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.180853405 Aug 03 04:22:05 PM PDT 24 Aug 03 04:22:17 PM PDT 24 1652710000 ps
T10 /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.2409016540 Aug 03 04:19:48 PM PDT 24 Aug 03 04:19:56 PM PDT 24 1177970000 ps
T11 /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.4146831886 Aug 03 04:21:41 PM PDT 24 Aug 03 04:21:50 PM PDT 24 1401150000 ps
T12 /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.188818389 Aug 03 04:21:15 PM PDT 24 Aug 03 04:21:23 PM PDT 24 1509030000 ps
T13 /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.1965998434 Aug 03 04:21:37 PM PDT 24 Aug 03 04:21:46 PM PDT 24 1488250000 ps
T31 /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.1978963692 Aug 03 04:20:44 PM PDT 24 Aug 03 04:20:52 PM PDT 24 1340170000 ps
T32 /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.2872556104 Aug 03 04:22:42 PM PDT 24 Aug 03 04:22:49 PM PDT 24 1433430000 ps
T33 /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.4083230613 Aug 03 04:21:13 PM PDT 24 Aug 03 04:21:26 PM PDT 24 1562090000 ps
T34 /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.1010999268 Aug 03 04:21:49 PM PDT 24 Aug 03 04:22:00 PM PDT 24 1513410000 ps
T35 /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.1069382137 Aug 03 04:20:54 PM PDT 24 Aug 03 04:21:06 PM PDT 24 1590930000 ps
T36 /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.3026057391 Aug 03 04:19:48 PM PDT 24 Aug 03 04:19:57 PM PDT 24 1548590000 ps
T37 /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.553656221 Aug 03 04:21:16 PM PDT 24 Aug 03 04:21:23 PM PDT 24 1327810000 ps
T38 /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.2473271419 Aug 03 04:21:14 PM PDT 24 Aug 03 04:21:23 PM PDT 24 1471530000 ps
T39 /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.554575938 Aug 03 04:20:14 PM PDT 24 Aug 03 04:20:24 PM PDT 24 1286370000 ps
T40 /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.2773446400 Aug 03 04:22:15 PM PDT 24 Aug 03 04:22:21 PM PDT 24 1217470000 ps
T41 /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.929505977 Aug 03 04:20:35 PM PDT 24 Aug 03 04:20:47 PM PDT 24 1584210000 ps
T42 /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.1073569248 Aug 03 04:22:33 PM PDT 24 Aug 03 04:22:40 PM PDT 24 1524770000 ps
T43 /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.965750161 Aug 03 04:20:28 PM PDT 24 Aug 03 04:20:38 PM PDT 24 1130410000 ps
T44 /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.2386598778 Aug 03 04:21:54 PM PDT 24 Aug 03 04:22:04 PM PDT 24 1503290000 ps
T45 /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.798951118 Aug 03 04:21:30 PM PDT 24 Aug 03 04:21:38 PM PDT 24 1187390000 ps
T46 /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.2794117877 Aug 03 04:21:38 PM PDT 24 Aug 03 04:21:47 PM PDT 24 1485730000 ps
T47 /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.2156152202 Aug 03 04:20:41 PM PDT 24 Aug 03 04:20:50 PM PDT 24 1556350000 ps
T48 /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.328547164 Aug 03 04:19:20 PM PDT 24 Aug 03 04:19:33 PM PDT 24 1559910000 ps
T49 /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.2018614677 Aug 03 04:19:07 PM PDT 24 Aug 03 04:19:18 PM PDT 24 1530230000 ps
T50 /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.2853970087 Aug 03 04:20:41 PM PDT 24 Aug 03 04:20:53 PM PDT 24 1441470000 ps
T51 /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.161484937 Aug 03 04:21:29 PM PDT 24 Aug 03 04:21:40 PM PDT 24 1466370000 ps
T52 /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.212862089 Aug 03 04:18:49 PM PDT 24 Aug 03 04:19:01 PM PDT 24 1546630000 ps
T53 /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.2101032746 Aug 03 04:21:41 PM PDT 24 Aug 03 04:21:51 PM PDT 24 1502130000 ps
T54 /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.4144740577 Aug 03 04:21:56 PM PDT 24 Aug 03 04:22:04 PM PDT 24 1465950000 ps
T55 /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.860423877 Aug 03 04:21:36 PM PDT 24 Aug 03 04:21:45 PM PDT 24 1414490000 ps
T56 /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.2745736570 Aug 03 04:20:59 PM PDT 24 Aug 03 04:21:09 PM PDT 24 1435210000 ps
T57 /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.4150806386 Aug 03 04:19:27 PM PDT 24 Aug 03 04:19:37 PM PDT 24 1554870000 ps
T58 /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.3964999971 Aug 03 04:23:22 PM PDT 24 Aug 03 04:23:30 PM PDT 24 1460910000 ps
T59 /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.409448712 Aug 03 04:21:51 PM PDT 24 Aug 03 04:22:02 PM PDT 24 1314750000 ps
T60 /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.373886381 Aug 03 04:19:28 PM PDT 24 Aug 03 04:19:39 PM PDT 24 1439110000 ps
T61 /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.2298102843 Aug 03 04:23:01 PM PDT 24 Aug 03 04:23:10 PM PDT 24 1436230000 ps
T62 /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.2633601420 Aug 03 04:22:31 PM PDT 24 Aug 03 04:22:41 PM PDT 24 1459550000 ps
T63 /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.884790887 Aug 03 04:21:40 PM PDT 24 Aug 03 04:21:50 PM PDT 24 1550690000 ps
T64 /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.3687620868 Aug 03 04:21:39 PM PDT 24 Aug 03 04:21:50 PM PDT 24 1667650000 ps
T65 /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.1057510235 Aug 03 04:21:54 PM PDT 24 Aug 03 04:22:04 PM PDT 24 1506550000 ps
T66 /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.991893948 Aug 03 04:21:17 PM PDT 24 Aug 03 04:21:30 PM PDT 24 1465650000 ps
T67 /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.2008057294 Aug 03 04:21:15 PM PDT 24 Aug 03 04:21:24 PM PDT 24 1523990000 ps
T68 /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.1109884467 Aug 03 04:21:14 PM PDT 24 Aug 03 04:21:27 PM PDT 24 1562730000 ps
T69 /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.1443592505 Aug 03 04:22:35 PM PDT 24 Aug 03 04:22:44 PM PDT 24 1440850000 ps
T70 /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.2621771640 Aug 03 04:23:42 PM PDT 24 Aug 03 04:23:50 PM PDT 24 1402110000 ps
T4 /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.3829993485 Aug 03 04:21:19 PM PDT 24 Aug 03 04:55:43 PM PDT 24 336486190000 ps
T5 /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.2175887153 Aug 03 04:21:54 PM PDT 24 Aug 03 04:55:19 PM PDT 24 336998250000 ps
T6 /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.176700777 Aug 03 04:19:31 PM PDT 24 Aug 03 05:03:04 PM PDT 24 336853810000 ps
T14 /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.2534230809 Aug 03 04:21:36 PM PDT 24 Aug 03 04:53:33 PM PDT 24 336662910000 ps
T15 /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.472768902 Aug 03 04:22:09 PM PDT 24 Aug 03 04:52:43 PM PDT 24 336872850000 ps
T16 /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.2240730631 Aug 03 04:18:38 PM PDT 24 Aug 03 05:01:41 PM PDT 24 336452750000 ps
T17 /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.1868227317 Aug 03 04:21:40 PM PDT 24 Aug 03 04:56:11 PM PDT 24 336672470000 ps
T18 /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.2759012653 Aug 03 04:21:32 PM PDT 24 Aug 03 04:48:38 PM PDT 24 337046630000 ps
T19 /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.3238384396 Aug 03 04:21:53 PM PDT 24 Aug 03 04:49:23 PM PDT 24 336776770000 ps
T20 /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.1783041102 Aug 03 04:20:01 PM PDT 24 Aug 03 04:56:50 PM PDT 24 337099530000 ps
T71 /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.3668418413 Aug 03 04:20:20 PM PDT 24 Aug 03 04:56:49 PM PDT 24 336385750000 ps
T72 /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.2606587059 Aug 03 04:20:57 PM PDT 24 Aug 03 04:55:54 PM PDT 24 336370230000 ps
T73 /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.2931082728 Aug 03 04:18:40 PM PDT 24 Aug 03 04:54:43 PM PDT 24 336577730000 ps
T74 /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.4179479365 Aug 03 04:23:22 PM PDT 24 Aug 03 04:54:46 PM PDT 24 336522890000 ps
T75 /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.2654594929 Aug 03 04:20:55 PM PDT 24 Aug 03 04:48:34 PM PDT 24 336760810000 ps
T76 /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.9624064 Aug 03 04:21:56 PM PDT 24 Aug 03 04:57:02 PM PDT 24 336781390000 ps
T77 /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.2241391662 Aug 03 04:20:51 PM PDT 24 Aug 03 05:03:57 PM PDT 24 336690710000 ps
T78 /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.2488303592 Aug 03 04:21:39 PM PDT 24 Aug 03 04:54:26 PM PDT 24 336794210000 ps
T79 /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.539041873 Aug 03 04:21:07 PM PDT 24 Aug 03 04:53:01 PM PDT 24 336785870000 ps
T80 /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.2066243148 Aug 03 04:21:40 PM PDT 24 Aug 03 04:55:25 PM PDT 24 336786030000 ps
T81 /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.2208330647 Aug 03 04:21:39 PM PDT 24 Aug 03 04:54:21 PM PDT 24 336389390000 ps
T82 /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.794671916 Aug 03 04:21:28 PM PDT 24 Aug 03 04:53:48 PM PDT 24 336632690000 ps
T83 /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.1184825929 Aug 03 04:20:11 PM PDT 24 Aug 03 05:03:24 PM PDT 24 336490350000 ps
T84 /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.957947385 Aug 03 04:20:54 PM PDT 24 Aug 03 04:48:42 PM PDT 24 337139410000 ps
T85 /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.2799161935 Aug 03 04:20:33 PM PDT 24 Aug 03 04:57:02 PM PDT 24 336515650000 ps
T86 /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.4217592683 Aug 03 04:21:39 PM PDT 24 Aug 03 04:53:56 PM PDT 24 337156310000 ps
T87 /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.1836490253 Aug 03 04:21:40 PM PDT 24 Aug 03 04:55:40 PM PDT 24 337074150000 ps
T88 /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.2831622819 Aug 03 04:20:40 PM PDT 24 Aug 03 04:52:43 PM PDT 24 336358410000 ps
T89 /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.4010516353 Aug 03 04:21:47 PM PDT 24 Aug 03 04:55:49 PM PDT 24 336724910000 ps
T90 /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.4203349640 Aug 03 04:21:54 PM PDT 24 Aug 03 04:55:10 PM PDT 24 336424190000 ps
T91 /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.752598472 Aug 03 04:20:24 PM PDT 24 Aug 03 04:47:35 PM PDT 24 336974690000 ps
T92 /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.2863376120 Aug 03 04:19:28 PM PDT 24 Aug 03 04:59:33 PM PDT 24 336680950000 ps
T93 /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.3312267241 Aug 03 04:20:40 PM PDT 24 Aug 03 04:53:59 PM PDT 24 337004390000 ps
T94 /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.1088668558 Aug 03 04:20:11 PM PDT 24 Aug 03 05:03:32 PM PDT 24 336902130000 ps
T95 /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.3486749975 Aug 03 04:21:04 PM PDT 24 Aug 03 04:50:50 PM PDT 24 336694070000 ps
T96 /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.1834121813 Aug 03 04:20:59 PM PDT 24 Aug 03 04:55:45 PM PDT 24 336637950000 ps
T97 /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.1845043856 Aug 03 04:21:01 PM PDT 24 Aug 03 04:56:56 PM PDT 24 336516390000 ps
T98 /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.2304765261 Aug 03 04:23:08 PM PDT 24 Aug 03 04:54:45 PM PDT 24 336802230000 ps
T99 /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.2297749963 Aug 03 04:19:25 PM PDT 24 Aug 03 04:59:24 PM PDT 24 336335870000 ps
T100 /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.3947192531 Aug 03 04:19:47 PM PDT 24 Aug 03 05:02:54 PM PDT 24 337031410000 ps
T101 /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.4041265898 Aug 03 04:20:36 PM PDT 24 Aug 03 04:57:20 PM PDT 24 336779450000 ps
T102 /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.1399640594 Aug 03 04:22:19 PM PDT 24 Aug 03 04:50:44 PM PDT 24 336650370000 ps
T103 /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.3470698296 Aug 03 04:22:39 PM PDT 24 Aug 03 04:58:31 PM PDT 24 336583770000 ps
T104 /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.3334272346 Aug 03 04:22:32 PM PDT 24 Aug 03 04:58:37 PM PDT 24 336885430000 ps
T105 /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.2746914439 Aug 03 04:20:56 PM PDT 24 Aug 03 04:48:29 PM PDT 24 336741110000 ps
T106 /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.1495534403 Aug 03 04:20:40 PM PDT 24 Aug 03 04:53:48 PM PDT 24 336906370000 ps
T107 /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.2016038536 Aug 03 04:19:24 PM PDT 24 Aug 03 04:57:24 PM PDT 24 337042770000 ps
T108 /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.2056272106 Aug 03 04:21:39 PM PDT 24 Aug 03 04:56:52 PM PDT 24 336910310000 ps
T109 /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.3657793814 Aug 03 04:18:44 PM PDT 24 Aug 03 04:58:31 PM PDT 24 336612970000 ps
T110 /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2293360008 Aug 03 04:20:01 PM PDT 24 Aug 03 04:56:20 PM PDT 24 336403590000 ps
T111 /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.2366142477 Aug 03 04:19:24 PM PDT 24 Aug 03 04:19:36 PM PDT 24 1479550000 ps
T112 /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.53626694 Aug 03 04:21:01 PM PDT 24 Aug 03 04:21:14 PM PDT 24 1600890000 ps
T113 /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.4116484394 Aug 03 04:20:44 PM PDT 24 Aug 03 04:20:52 PM PDT 24 1386450000 ps
T114 /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.2330440282 Aug 03 04:19:38 PM PDT 24 Aug 03 04:19:46 PM PDT 24 1278630000 ps
T115 /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.4016231064 Aug 03 04:21:01 PM PDT 24 Aug 03 04:21:10 PM PDT 24 1331670000 ps
T116 /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.3588882095 Aug 03 04:21:37 PM PDT 24 Aug 03 04:21:46 PM PDT 24 1322890000 ps
T117 /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.1111944504 Aug 03 04:21:02 PM PDT 24 Aug 03 04:21:10 PM PDT 24 1321630000 ps
T118 /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.487782798 Aug 03 04:22:46 PM PDT 24 Aug 03 04:22:56 PM PDT 24 1339030000 ps
T119 /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.2021079085 Aug 03 04:21:32 PM PDT 24 Aug 03 04:21:43 PM PDT 24 1480110000 ps
T120 /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.298115772 Aug 03 04:21:51 PM PDT 24 Aug 03 04:21:58 PM PDT 24 1401730000 ps
T121 /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.485182586 Aug 03 04:19:14 PM PDT 24 Aug 03 04:19:25 PM PDT 24 1397050000 ps
T122 /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.2256406028 Aug 03 04:21:08 PM PDT 24 Aug 03 04:21:17 PM PDT 24 1425950000 ps
T123 /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.2212753275 Aug 03 04:20:01 PM PDT 24 Aug 03 04:20:12 PM PDT 24 1443630000 ps
T124 /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.4221586459 Aug 03 04:20:47 PM PDT 24 Aug 03 04:20:53 PM PDT 24 1186690000 ps
T125 /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.2640073048 Aug 03 04:24:19 PM PDT 24 Aug 03 04:24:26 PM PDT 24 1371750000 ps
T126 /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.1612672710 Aug 03 04:21:24 PM PDT 24 Aug 03 04:21:31 PM PDT 24 1506610000 ps
T127 /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.301521550 Aug 03 04:19:38 PM PDT 24 Aug 03 04:19:47 PM PDT 24 1539290000 ps
T128 /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.513964370 Aug 03 04:21:02 PM PDT 24 Aug 03 04:21:12 PM PDT 24 1193630000 ps
T129 /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.339737727 Aug 03 04:19:44 PM PDT 24 Aug 03 04:19:55 PM PDT 24 1565130000 ps
T130 /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.611360818 Aug 03 04:19:48 PM PDT 24 Aug 03 04:19:56 PM PDT 24 1355970000 ps
T131 /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.935396718 Aug 03 04:20:38 PM PDT 24 Aug 03 04:20:48 PM PDT 24 1464770000 ps
T132 /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.3215531677 Aug 03 04:21:03 PM PDT 24 Aug 03 04:21:13 PM PDT 24 1599930000 ps
T133 /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.2108082507 Aug 03 04:19:48 PM PDT 24 Aug 03 04:19:58 PM PDT 24 1543710000 ps
T134 /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.3709856820 Aug 03 04:18:44 PM PDT 24 Aug 03 04:18:55 PM PDT 24 1536890000 ps
T135 /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.3029297974 Aug 03 04:21:01 PM PDT 24 Aug 03 04:21:13 PM PDT 24 1481610000 ps
T136 /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.882010648 Aug 03 04:21:03 PM PDT 24 Aug 03 04:21:10 PM PDT 24 1361310000 ps
T137 /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.601465830 Aug 03 04:20:48 PM PDT 24 Aug 03 04:20:54 PM PDT 24 1234650000 ps
T138 /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.1922768503 Aug 03 04:21:03 PM PDT 24 Aug 03 04:21:11 PM PDT 24 1268670000 ps
T139 /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.2504243387 Aug 03 04:19:58 PM PDT 24 Aug 03 04:20:10 PM PDT 24 1434530000 ps
T140 /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.1289015499 Aug 03 04:19:59 PM PDT 24 Aug 03 04:20:10 PM PDT 24 1497650000 ps
T141 /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.4280503448 Aug 03 04:19:43 PM PDT 24 Aug 03 04:19:51 PM PDT 24 1085010000 ps
T142 /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.4052013966 Aug 03 04:20:58 PM PDT 24 Aug 03 04:21:05 PM PDT 24 1382630000 ps
T143 /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.1961483769 Aug 03 04:20:20 PM PDT 24 Aug 03 04:20:32 PM PDT 24 1565850000 ps
T144 /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.2027079915 Aug 03 04:20:57 PM PDT 24 Aug 03 04:21:06 PM PDT 24 1514010000 ps
T145 /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.1654595030 Aug 03 04:20:14 PM PDT 24 Aug 03 04:20:24 PM PDT 24 1470810000 ps
T146 /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.3204393074 Aug 03 04:20:26 PM PDT 24 Aug 03 04:20:35 PM PDT 24 1426750000 ps
T147 /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.2698244048 Aug 03 04:21:25 PM PDT 24 Aug 03 04:21:36 PM PDT 24 1457110000 ps
T148 /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.1097972686 Aug 03 04:20:57 PM PDT 24 Aug 03 04:21:07 PM PDT 24 1538390000 ps
T149 /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.2894871211 Aug 03 04:21:37 PM PDT 24 Aug 03 04:21:46 PM PDT 24 1440650000 ps
T150 /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.1862097694 Aug 03 04:20:47 PM PDT 24 Aug 03 04:20:55 PM PDT 24 1592370000 ps
T151 /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.3567968064 Aug 03 04:20:17 PM PDT 24 Aug 03 04:20:25 PM PDT 24 1285170000 ps
T152 /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.3531766262 Aug 03 04:19:55 PM PDT 24 Aug 03 04:20:05 PM PDT 24 1439030000 ps
T153 /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.3361023735 Aug 03 04:21:03 PM PDT 24 Aug 03 04:21:13 PM PDT 24 1544750000 ps
T154 /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.114791571 Aug 03 04:20:47 PM PDT 24 Aug 03 04:20:54 PM PDT 24 1366210000 ps
T155 /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.2399847409 Aug 03 04:21:02 PM PDT 24 Aug 03 04:21:12 PM PDT 24 1386950000 ps
T156 /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.4086348595 Aug 03 04:20:23 PM PDT 24 Aug 03 04:20:33 PM PDT 24 1565610000 ps
T157 /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.2821985863 Aug 03 04:20:53 PM PDT 24 Aug 03 04:21:02 PM PDT 24 1580550000 ps
T158 /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.801768648 Aug 03 04:20:26 PM PDT 24 Aug 03 04:20:36 PM PDT 24 1555770000 ps
T159 /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.2373846134 Aug 03 04:21:53 PM PDT 24 Aug 03 04:22:03 PM PDT 24 1382830000 ps
T160 /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.1356929785 Aug 03 04:21:04 PM PDT 24 Aug 03 04:21:12 PM PDT 24 1373450000 ps
T21 /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.2362150551 Aug 03 04:22:45 PM PDT 24 Aug 03 04:57:33 PM PDT 24 336900790000 ps
T22 /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.3740953524 Aug 03 04:20:44 PM PDT 24 Aug 03 04:53:54 PM PDT 24 337002630000 ps
T23 /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.592384370 Aug 03 04:20:59 PM PDT 24 Aug 03 04:56:03 PM PDT 24 336449190000 ps
T24 /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.3380068407 Aug 03 04:18:38 PM PDT 24 Aug 03 04:51:14 PM PDT 24 336442810000 ps
T25 /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.3022197961 Aug 03 04:20:57 PM PDT 24 Aug 03 04:51:58 PM PDT 24 336513430000 ps
T26 /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.317218447 Aug 03 04:18:44 PM PDT 24 Aug 03 04:56:31 PM PDT 24 337052150000 ps
T27 /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.552706855 Aug 03 04:21:37 PM PDT 24 Aug 03 04:54:48 PM PDT 24 336772030000 ps
T28 /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.522156698 Aug 03 04:22:15 PM PDT 24 Aug 03 04:49:49 PM PDT 24 336369810000 ps
T29 /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.3841892790 Aug 03 04:21:20 PM PDT 24 Aug 03 05:04:25 PM PDT 24 336727830000 ps
T30 /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.3516711922 Aug 03 04:21:40 PM PDT 24 Aug 03 04:58:24 PM PDT 24 336488010000 ps
T161 /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.3306271454 Aug 03 04:21:54 PM PDT 24 Aug 03 04:54:17 PM PDT 24 336564510000 ps
T162 /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.1519128695 Aug 03 04:21:06 PM PDT 24 Aug 03 05:00:27 PM PDT 24 336461330000 ps
T163 /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.1906109922 Aug 03 04:22:28 PM PDT 24 Aug 03 04:57:01 PM PDT 24 337076890000 ps
T164 /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.696752041 Aug 03 04:21:07 PM PDT 24 Aug 03 05:04:15 PM PDT 24 336701330000 ps
T165 /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.2425855681 Aug 03 04:22:57 PM PDT 24 Aug 03 04:55:55 PM PDT 24 336423630000 ps
T166 /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.3118951048 Aug 03 04:22:28 PM PDT 24 Aug 03 04:53:10 PM PDT 24 336963910000 ps
T167 /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.660511711 Aug 03 04:19:28 PM PDT 24 Aug 03 04:59:04 PM PDT 24 337076630000 ps
T168 /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.971547548 Aug 03 04:20:40 PM PDT 24 Aug 03 04:54:09 PM PDT 24 337042690000 ps
T169 /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.1409182972 Aug 03 04:21:41 PM PDT 24 Aug 03 04:56:28 PM PDT 24 336728050000 ps
T170 /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.2161141226 Aug 03 04:19:28 PM PDT 24 Aug 03 04:59:11 PM PDT 24 336689870000 ps
T171 /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.1743088093 Aug 03 04:20:57 PM PDT 24 Aug 03 04:51:27 PM PDT 24 337132550000 ps
T172 /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.3393812234 Aug 03 04:21:20 PM PDT 24 Aug 03 05:04:23 PM PDT 24 336839270000 ps
T173 /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.753130712 Aug 03 04:21:26 PM PDT 24 Aug 03 04:57:50 PM PDT 24 336375970000 ps
T174 /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.627301721 Aug 03 04:21:15 PM PDT 24 Aug 03 04:58:21 PM PDT 24 336516550000 ps
T175 /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.398598124 Aug 03 04:20:44 PM PDT 24 Aug 03 04:53:48 PM PDT 24 336731050000 ps
T176 /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.2672310708 Aug 03 04:19:35 PM PDT 24 Aug 03 05:02:12 PM PDT 24 337038090000 ps
T177 /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.3534265014 Aug 03 04:21:39 PM PDT 24 Aug 03 04:50:40 PM PDT 24 336820010000 ps
T178 /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.3139549462 Aug 03 04:21:14 PM PDT 24 Aug 03 04:47:30 PM PDT 24 336687510000 ps
T179 /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.2907820761 Aug 03 04:19:14 PM PDT 24 Aug 03 04:54:21 PM PDT 24 336687310000 ps
T180 /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.1718634475 Aug 03 04:20:45 PM PDT 24 Aug 03 04:54:02 PM PDT 24 336957950000 ps
T181 /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.3976399691 Aug 03 04:21:28 PM PDT 24 Aug 03 04:53:41 PM PDT 24 336931730000 ps
T182 /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.2306611755 Aug 03 04:23:41 PM PDT 24 Aug 03 04:56:45 PM PDT 24 336615270000 ps
T183 /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.4009705097 Aug 03 04:21:30 PM PDT 24 Aug 03 04:51:56 PM PDT 24 337040130000 ps
T184 /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.780505423 Aug 03 04:22:42 PM PDT 24 Aug 03 04:51:50 PM PDT 24 337035770000 ps
T185 /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.1188454861 Aug 03 04:21:37 PM PDT 24 Aug 03 04:52:50 PM PDT 24 336906950000 ps
T186 /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.2222377024 Aug 03 04:20:53 PM PDT 24 Aug 03 04:55:40 PM PDT 24 336720990000 ps
T187 /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.125536138 Aug 03 04:20:59 PM PDT 24 Aug 03 04:55:39 PM PDT 24 336889970000 ps
T188 /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.2694441698 Aug 03 04:19:13 PM PDT 24 Aug 03 04:53:48 PM PDT 24 336321590000 ps
T189 /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3961867211 Aug 03 04:21:46 PM PDT 24 Aug 03 05:04:34 PM PDT 24 336697470000 ps
T190 /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.4257106891 Aug 03 04:18:36 PM PDT 24 Aug 03 04:51:00 PM PDT 24 336369850000 ps
T191 /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.399523311 Aug 03 04:21:06 PM PDT 24 Aug 03 04:52:44 PM PDT 24 336725590000 ps
T192 /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.2819642182 Aug 03 04:22:25 PM PDT 24 Aug 03 04:56:26 PM PDT 24 336368910000 ps
T193 /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.1529794466 Aug 03 04:23:35 PM PDT 24 Aug 03 04:52:04 PM PDT 24 336810230000 ps
T194 /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.3967244501 Aug 03 04:20:39 PM PDT 24 Aug 03 04:48:51 PM PDT 24 336484850000 ps
T195 /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.1509413054 Aug 03 04:19:28 PM PDT 24 Aug 03 04:59:26 PM PDT 24 336479430000 ps
T196 /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.2851564200 Aug 03 04:21:56 PM PDT 24 Aug 03 04:56:30 PM PDT 24 337079690000 ps
T197 /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.3379056341 Aug 03 04:20:42 PM PDT 24 Aug 03 04:52:19 PM PDT 24 336723690000 ps
T198 /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.2539224088 Aug 03 04:18:40 PM PDT 24 Aug 03 04:55:49 PM PDT 24 336507410000 ps
T199 /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.3232003434 Aug 03 04:20:59 PM PDT 24 Aug 03 04:56:08 PM PDT 24 337115690000 ps
T200 /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.4204656643 Aug 03 04:21:40 PM PDT 24 Aug 03 04:56:15 PM PDT 24 337059570000 ps

Test location /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.1965998434
Short name T13
Test name
Test status
Simulation time 1488250000 ps
CPU time 3.7 seconds
Started Aug 03 04:21:37 PM PDT 24
Finished Aug 03 04:21:46 PM PDT 24
Peak memory 164528 kb
Host smart-70bb20bf-377e-43af-af71-57e215012c97
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1965998434 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.1965998434
Directory /workspace/11.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.3238384396
Short name T19
Test name
Test status
Simulation time 336776770000 ps
CPU time 656.36 seconds
Started Aug 03 04:21:53 PM PDT 24
Finished Aug 03 04:49:23 PM PDT 24
Peak memory 160652 kb
Host smart-58167cce-42b0-4c8f-8806-c7e39335524a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3238384396 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.3238384396
Directory /workspace/11.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.3740953524
Short name T22
Test name
Test status
Simulation time 337002630000 ps
CPU time 798.7 seconds
Started Aug 03 04:20:44 PM PDT 24
Finished Aug 03 04:53:54 PM PDT 24
Peak memory 160252 kb
Host smart-a868d20e-2921-4b6c-ba37-13e2365245ac
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3740953524 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.3740953524
Directory /workspace/10.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.2654594929
Short name T75
Test name
Test status
Simulation time 336760810000 ps
CPU time 673.15 seconds
Started Aug 03 04:20:55 PM PDT 24
Finished Aug 03 04:48:34 PM PDT 24
Peak memory 160344 kb
Host smart-b6e8073a-8494-41f7-878f-c65bb3839b35
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2654594929 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.2654594929
Directory /workspace/0.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.2799161935
Short name T85
Test name
Test status
Simulation time 336515650000 ps
CPU time 888.71 seconds
Started Aug 03 04:20:33 PM PDT 24
Finished Aug 03 04:57:02 PM PDT 24
Peak memory 160656 kb
Host smart-62ce27a4-be7d-410a-9f4e-3d693dd99b09
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2799161935 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.2799161935
Directory /workspace/1.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.794671916
Short name T82
Test name
Test status
Simulation time 336632690000 ps
CPU time 778.4 seconds
Started Aug 03 04:21:28 PM PDT 24
Finished Aug 03 04:53:48 PM PDT 24
Peak memory 159272 kb
Host smart-31ea3890-83eb-4319-9040-ba86c91915ae
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=794671916 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.794671916
Directory /workspace/10.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.4041265898
Short name T101
Test name
Test status
Simulation time 336779450000 ps
CPU time 866.79 seconds
Started Aug 03 04:20:36 PM PDT 24
Finished Aug 03 04:57:20 PM PDT 24
Peak memory 160656 kb
Host smart-fed71991-a824-4374-8908-c9663e25aa4e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4041265898 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.4041265898
Directory /workspace/12.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.3947192531
Short name T100
Test name
Test status
Simulation time 337031410000 ps
CPU time 1067.04 seconds
Started Aug 03 04:19:47 PM PDT 24
Finished Aug 03 05:02:54 PM PDT 24
Peak memory 160660 kb
Host smart-e7c2384a-d49e-4b56-9322-49381de2aabb
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3947192531 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.3947192531
Directory /workspace/13.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.2746914439
Short name T105
Test name
Test status
Simulation time 336741110000 ps
CPU time 670.62 seconds
Started Aug 03 04:20:56 PM PDT 24
Finished Aug 03 04:48:29 PM PDT 24
Peak memory 160368 kb
Host smart-4a5da58a-7d2a-412d-90c6-dc0e4935c24b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2746914439 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.2746914439
Directory /workspace/14.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.1845043856
Short name T97
Test name
Test status
Simulation time 336516390000 ps
CPU time 882.54 seconds
Started Aug 03 04:21:01 PM PDT 24
Finished Aug 03 04:56:56 PM PDT 24
Peak memory 160676 kb
Host smart-e4c8db11-b311-495b-8924-edff1be4813f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1845043856 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.1845043856
Directory /workspace/15.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.2606587059
Short name T72
Test name
Test status
Simulation time 336370230000 ps
CPU time 856.88 seconds
Started Aug 03 04:20:57 PM PDT 24
Finished Aug 03 04:55:54 PM PDT 24
Peak memory 160608 kb
Host smart-aa82ac1e-3124-4214-8b11-374e2f4beee0
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2606587059 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.2606587059
Directory /workspace/16.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.3668418413
Short name T71
Test name
Test status
Simulation time 336385750000 ps
CPU time 888.65 seconds
Started Aug 03 04:20:20 PM PDT 24
Finished Aug 03 04:56:49 PM PDT 24
Peak memory 160632 kb
Host smart-d8d4c830-7ce1-42af-bd40-333e3cc59704
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3668418413 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.3668418413
Directory /workspace/17.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.2241391662
Short name T77
Test name
Test status
Simulation time 336690710000 ps
CPU time 1066.16 seconds
Started Aug 03 04:20:51 PM PDT 24
Finished Aug 03 05:03:57 PM PDT 24
Peak memory 160660 kb
Host smart-068aa859-ffc6-442a-8de8-4a514beb7e9a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2241391662 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.2241391662
Directory /workspace/18.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2293360008
Short name T110
Test name
Test status
Simulation time 336403590000 ps
CPU time 883.24 seconds
Started Aug 03 04:20:01 PM PDT 24
Finished Aug 03 04:56:20 PM PDT 24
Peak memory 160632 kb
Host smart-aefb8d23-5f32-4a13-b460-acaf29fc925c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2293360008 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.2293360008
Directory /workspace/19.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.957947385
Short name T84
Test name
Test status
Simulation time 337139410000 ps
CPU time 683.29 seconds
Started Aug 03 04:20:54 PM PDT 24
Finished Aug 03 04:48:42 PM PDT 24
Peak memory 160244 kb
Host smart-6aead6c8-31b7-4976-850e-d0d8e9370f85
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=957947385 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.957947385
Directory /workspace/2.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.2208330647
Short name T81
Test name
Test status
Simulation time 336389390000 ps
CPU time 791 seconds
Started Aug 03 04:21:39 PM PDT 24
Finished Aug 03 04:54:21 PM PDT 24
Peak memory 160376 kb
Host smart-1dc39ded-a4d1-4ee0-9433-eaa4559a50bb
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2208330647 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.2208330647
Directory /workspace/20.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.2863376120
Short name T92
Test name
Test status
Simulation time 336680950000 ps
CPU time 977.97 seconds
Started Aug 03 04:19:28 PM PDT 24
Finished Aug 03 04:59:33 PM PDT 24
Peak memory 160604 kb
Host smart-ee3b59be-44a8-407c-8e5d-839d1b47f6ba
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2863376120 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.2863376120
Directory /workspace/21.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.2297749963
Short name T99
Test name
Test status
Simulation time 336335870000 ps
CPU time 975.5 seconds
Started Aug 03 04:19:25 PM PDT 24
Finished Aug 03 04:59:24 PM PDT 24
Peak memory 160604 kb
Host smart-0f62c3d3-545d-45b3-bc4b-667c1de16533
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2297749963 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.2297749963
Directory /workspace/22.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.176700777
Short name T6
Test name
Test status
Simulation time 336853810000 ps
CPU time 1034.69 seconds
Started Aug 03 04:19:31 PM PDT 24
Finished Aug 03 05:03:04 PM PDT 24
Peak memory 160620 kb
Host smart-48ae31f6-453d-4513-9271-8f22fb120f67
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=176700777 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.176700777
Directory /workspace/23.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.2488303592
Short name T78
Test name
Test status
Simulation time 336794210000 ps
CPU time 792.21 seconds
Started Aug 03 04:21:39 PM PDT 24
Finished Aug 03 04:54:26 PM PDT 24
Peak memory 160404 kb
Host smart-340afaf0-fb08-4f90-b23c-d365cfde049c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2488303592 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.2488303592
Directory /workspace/24.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.2831622819
Short name T88
Test name
Test status
Simulation time 336358410000 ps
CPU time 782.9 seconds
Started Aug 03 04:20:40 PM PDT 24
Finished Aug 03 04:52:43 PM PDT 24
Peak memory 160920 kb
Host smart-5f422d90-86a3-4ff6-8ed9-0f60f1602107
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2831622819 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.2831622819
Directory /workspace/25.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.4217592683
Short name T86
Test name
Test status
Simulation time 337156310000 ps
CPU time 796.52 seconds
Started Aug 03 04:21:39 PM PDT 24
Finished Aug 03 04:53:56 PM PDT 24
Peak memory 160556 kb
Host smart-44adba1d-ee21-4758-bf19-66490a36330a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4217592683 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.4217592683
Directory /workspace/26.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.2304765261
Short name T98
Test name
Test status
Simulation time 336802230000 ps
CPU time 780.06 seconds
Started Aug 03 04:23:08 PM PDT 24
Finished Aug 03 04:54:45 PM PDT 24
Peak memory 160668 kb
Host smart-4a05c68c-4e6a-45bb-88e5-8b6a0eb8d490
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2304765261 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.2304765261
Directory /workspace/27.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.2066243148
Short name T80
Test name
Test status
Simulation time 336786030000 ps
CPU time 821.14 seconds
Started Aug 03 04:21:40 PM PDT 24
Finished Aug 03 04:55:25 PM PDT 24
Peak memory 160588 kb
Host smart-37d1070f-fa08-49c8-b4d2-a9d9725afb53
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2066243148 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.2066243148
Directory /workspace/28.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.2056272106
Short name T108
Test name
Test status
Simulation time 336910310000 ps
CPU time 865.15 seconds
Started Aug 03 04:21:39 PM PDT 24
Finished Aug 03 04:56:52 PM PDT 24
Peak memory 160556 kb
Host smart-256d5f74-f35a-49ac-90ef-8bdc2dcd39d7
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2056272106 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.2056272106
Directory /workspace/29.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.1495534403
Short name T106
Test name
Test status
Simulation time 336906370000 ps
CPU time 782.29 seconds
Started Aug 03 04:20:40 PM PDT 24
Finished Aug 03 04:53:48 PM PDT 24
Peak memory 158516 kb
Host smart-858ff030-7a89-4c6d-8ca4-11c7a6e644d3
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1495534403 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.1495534403
Directory /workspace/3.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.1868227317
Short name T17
Test name
Test status
Simulation time 336672470000 ps
CPU time 840.62 seconds
Started Aug 03 04:21:40 PM PDT 24
Finished Aug 03 04:56:11 PM PDT 24
Peak memory 160584 kb
Host smart-7a0a9033-48e6-4cfe-8865-f847085adf06
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1868227317 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.1868227317
Directory /workspace/30.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.1836490253
Short name T87
Test name
Test status
Simulation time 337074150000 ps
CPU time 823.8 seconds
Started Aug 03 04:21:40 PM PDT 24
Finished Aug 03 04:55:40 PM PDT 24
Peak memory 160588 kb
Host smart-426651b9-4f8c-4b3b-8c3f-610d3b25eb6b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1836490253 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.1836490253
Directory /workspace/31.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.4179479365
Short name T74
Test name
Test status
Simulation time 336522890000 ps
CPU time 771.32 seconds
Started Aug 03 04:23:22 PM PDT 24
Finished Aug 03 04:54:46 PM PDT 24
Peak memory 159872 kb
Host smart-3678cac6-17e4-4ea2-b9a8-cb43fd556469
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4179479365 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.4179479365
Directory /workspace/32.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.3829993485
Short name T4
Test name
Test status
Simulation time 336486190000 ps
CPU time 864.59 seconds
Started Aug 03 04:21:19 PM PDT 24
Finished Aug 03 04:55:43 PM PDT 24
Peak memory 160692 kb
Host smart-44974070-8bb4-4987-bf24-2f6e713fdb40
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3829993485 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.3829993485
Directory /workspace/33.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.472768902
Short name T15
Test name
Test status
Simulation time 336872850000 ps
CPU time 748.81 seconds
Started Aug 03 04:22:09 PM PDT 24
Finished Aug 03 04:52:43 PM PDT 24
Peak memory 160616 kb
Host smart-6c46261b-fe91-4b2c-a89f-6574a5f0e89e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=472768902 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.472768902
Directory /workspace/34.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.1783041102
Short name T20
Test name
Test status
Simulation time 337099530000 ps
CPU time 892.35 seconds
Started Aug 03 04:20:01 PM PDT 24
Finished Aug 03 04:56:50 PM PDT 24
Peak memory 160632 kb
Host smart-d9d909e0-2828-4f03-bc79-c4b1ccaa2dec
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1783041102 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.1783041102
Directory /workspace/35.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.2016038536
Short name T107
Test name
Test status
Simulation time 337042770000 ps
CPU time 913.12 seconds
Started Aug 03 04:19:24 PM PDT 24
Finished Aug 03 04:57:24 PM PDT 24
Peak memory 160640 kb
Host smart-c84fe075-a3ee-4bfd-aa6b-90e246922e93
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2016038536 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.2016038536
Directory /workspace/36.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.2534230809
Short name T14
Test name
Test status
Simulation time 336662910000 ps
CPU time 783.61 seconds
Started Aug 03 04:21:36 PM PDT 24
Finished Aug 03 04:53:33 PM PDT 24
Peak memory 160640 kb
Host smart-96bf1605-989f-4147-ae6d-255f1719fd4b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2534230809 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.2534230809
Directory /workspace/37.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.9624064
Short name T76
Test name
Test status
Simulation time 336781390000 ps
CPU time 844.79 seconds
Started Aug 03 04:21:56 PM PDT 24
Finished Aug 03 04:57:02 PM PDT 24
Peak memory 160624 kb
Host smart-4d59c396-a4b3-467c-a442-a2560053eed8
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=9624064 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.9624064
Directory /workspace/38.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.1184825929
Short name T83
Test name
Test status
Simulation time 336490350000 ps
CPU time 1069.16 seconds
Started Aug 03 04:20:11 PM PDT 24
Finished Aug 03 05:03:24 PM PDT 24
Peak memory 160660 kb
Host smart-85b4ccef-f0b6-4d20-85ea-c25289b8c10c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1184825929 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.1184825929
Directory /workspace/39.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.2240730631
Short name T16
Test name
Test status
Simulation time 336452750000 ps
CPU time 1046.27 seconds
Started Aug 03 04:18:38 PM PDT 24
Finished Aug 03 05:01:41 PM PDT 24
Peak memory 160616 kb
Host smart-b17d410f-e9bc-45c5-af32-209576c0267e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2240730631 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.2240730631
Directory /workspace/4.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.4203349640
Short name T90
Test name
Test status
Simulation time 336424190000 ps
CPU time 786.1 seconds
Started Aug 03 04:21:54 PM PDT 24
Finished Aug 03 04:55:10 PM PDT 24
Peak memory 160600 kb
Host smart-673e7ff6-8f20-4c21-bc8c-7923c72c29d6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4203349640 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.4203349640
Directory /workspace/40.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.2175887153
Short name T5
Test name
Test status
Simulation time 336998250000 ps
CPU time 790.16 seconds
Started Aug 03 04:21:54 PM PDT 24
Finished Aug 03 04:55:19 PM PDT 24
Peak memory 160600 kb
Host smart-294b9a62-cbac-4aa0-9f16-6a7428a2b367
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2175887153 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.2175887153
Directory /workspace/41.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.4010516353
Short name T89
Test name
Test status
Simulation time 336724910000 ps
CPU time 846.91 seconds
Started Aug 03 04:21:47 PM PDT 24
Finished Aug 03 04:55:49 PM PDT 24
Peak memory 160692 kb
Host smart-6ded1f4e-8d6b-483a-9f75-67c5034c5f12
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4010516353 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.4010516353
Directory /workspace/42.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.2759012653
Short name T18
Test name
Test status
Simulation time 337046630000 ps
CPU time 662.08 seconds
Started Aug 03 04:21:32 PM PDT 24
Finished Aug 03 04:48:38 PM PDT 24
Peak memory 160616 kb
Host smart-c511af5a-0b5d-4d89-a732-64485766d6e6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2759012653 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.2759012653
Directory /workspace/43.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.3657793814
Short name T109
Test name
Test status
Simulation time 336612970000 ps
CPU time 981.12 seconds
Started Aug 03 04:18:44 PM PDT 24
Finished Aug 03 04:58:31 PM PDT 24
Peak memory 160656 kb
Host smart-2c5c9422-f734-408b-9ed9-13b60156fc3d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3657793814 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.3657793814
Directory /workspace/44.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.3334272346
Short name T104
Test name
Test status
Simulation time 336885430000 ps
CPU time 893.64 seconds
Started Aug 03 04:22:32 PM PDT 24
Finished Aug 03 04:58:37 PM PDT 24
Peak memory 160592 kb
Host smart-bdf97d78-32b9-4331-b694-f2aeef352d7d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3334272346 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.3334272346
Directory /workspace/45.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.1834121813
Short name T96
Test name
Test status
Simulation time 336637950000 ps
CPU time 863.33 seconds
Started Aug 03 04:20:59 PM PDT 24
Finished Aug 03 04:55:45 PM PDT 24
Peak memory 160556 kb
Host smart-af60e9ef-f059-4baf-b630-49e5b5a31884
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1834121813 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.1834121813
Directory /workspace/46.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.3470698296
Short name T103
Test name
Test status
Simulation time 336583770000 ps
CPU time 883.78 seconds
Started Aug 03 04:22:39 PM PDT 24
Finished Aug 03 04:58:31 PM PDT 24
Peak memory 160592 kb
Host smart-7a7593c8-8f4a-4ac6-a510-3f64e4f50f8c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3470698296 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.3470698296
Directory /workspace/47.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.2931082728
Short name T73
Test name
Test status
Simulation time 336577730000 ps
CPU time 877.85 seconds
Started Aug 03 04:18:40 PM PDT 24
Finished Aug 03 04:54:43 PM PDT 24
Peak memory 160632 kb
Host smart-cb82917e-0564-4ff8-a040-70c0e9e731d6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2931082728 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.2931082728
Directory /workspace/48.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.1399640594
Short name T102
Test name
Test status
Simulation time 336650370000 ps
CPU time 696.39 seconds
Started Aug 03 04:22:19 PM PDT 24
Finished Aug 03 04:50:44 PM PDT 24
Peak memory 160676 kb
Host smart-5d0b6e1d-c75a-4edc-b566-065eee840769
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1399640594 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.1399640594
Directory /workspace/49.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.539041873
Short name T79
Test name
Test status
Simulation time 336785870000 ps
CPU time 770.22 seconds
Started Aug 03 04:21:07 PM PDT 24
Finished Aug 03 04:53:01 PM PDT 24
Peak memory 160568 kb
Host smart-8f06e2f6-42f7-498f-a02b-23cd6605d5d4
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=539041873 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.539041873
Directory /workspace/5.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.752598472
Short name T91
Test name
Test status
Simulation time 336974690000 ps
CPU time 666.64 seconds
Started Aug 03 04:20:24 PM PDT 24
Finished Aug 03 04:47:35 PM PDT 24
Peak memory 160600 kb
Host smart-1db232c7-cfbd-48f4-8d68-e6f86296f0e1
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=752598472 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.752598472
Directory /workspace/6.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.3486749975
Short name T95
Test name
Test status
Simulation time 336694070000 ps
CPU time 733.94 seconds
Started Aug 03 04:21:04 PM PDT 24
Finished Aug 03 04:50:50 PM PDT 24
Peak memory 160172 kb
Host smart-65c4593e-5954-40fb-a27b-57f12c8d08a5
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3486749975 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.3486749975
Directory /workspace/7.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.3312267241
Short name T93
Test name
Test status
Simulation time 337004390000 ps
CPU time 784.54 seconds
Started Aug 03 04:20:40 PM PDT 24
Finished Aug 03 04:53:59 PM PDT 24
Peak memory 158588 kb
Host smart-b6b2f38f-e399-41f6-a9ef-66a3224806b2
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3312267241 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.3312267241
Directory /workspace/8.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.1088668558
Short name T94
Test name
Test status
Simulation time 336902130000 ps
CPU time 1042.24 seconds
Started Aug 03 04:20:11 PM PDT 24
Finished Aug 03 05:03:32 PM PDT 24
Peak memory 160624 kb
Host smart-146455a4-3a16-4664-be55-269c53b6379a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1088668558 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.1088668558
Directory /workspace/9.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.3118951048
Short name T166
Test name
Test status
Simulation time 336963910000 ps
CPU time 746.77 seconds
Started Aug 03 04:22:28 PM PDT 24
Finished Aug 03 04:53:10 PM PDT 24
Peak memory 160636 kb
Host smart-1d74646c-13d4-4da0-bf57-fa63ac1637a0
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3118951048 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.3118951048
Directory /workspace/0.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.2694441698
Short name T188
Test name
Test status
Simulation time 336321590000 ps
CPU time 845.48 seconds
Started Aug 03 04:19:13 PM PDT 24
Finished Aug 03 04:53:48 PM PDT 24
Peak memory 160628 kb
Host smart-135c7383-7278-46e5-be05-40ae4dd3837f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2694441698 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.2694441698
Directory /workspace/1.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.3022197961
Short name T25
Test name
Test status
Simulation time 336513430000 ps
CPU time 747.66 seconds
Started Aug 03 04:20:57 PM PDT 24
Finished Aug 03 04:51:58 PM PDT 24
Peak memory 159244 kb
Host smart-6cb64f73-4db2-4ab9-8202-69487168fc6a
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3022197961 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.3022197961
Directory /workspace/11.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.1718634475
Short name T180
Test name
Test status
Simulation time 336957950000 ps
CPU time 800.71 seconds
Started Aug 03 04:20:45 PM PDT 24
Finished Aug 03 04:54:02 PM PDT 24
Peak memory 160612 kb
Host smart-1b27b8b8-165e-446c-8730-e43f7a18fbd4
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1718634475 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.1718634475
Directory /workspace/12.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.1743088093
Short name T171
Test name
Test status
Simulation time 337132550000 ps
CPU time 731.76 seconds
Started Aug 03 04:20:57 PM PDT 24
Finished Aug 03 04:51:27 PM PDT 24
Peak memory 159140 kb
Host smart-8355c10a-2d7c-440f-8dcf-6fe3c4c853c9
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1743088093 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.1743088093
Directory /workspace/13.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.399523311
Short name T191
Test name
Test status
Simulation time 336725590000 ps
CPU time 762.55 seconds
Started Aug 03 04:21:06 PM PDT 24
Finished Aug 03 04:52:44 PM PDT 24
Peak memory 160344 kb
Host smart-aff06c8e-59aa-4eb8-9d0e-1dfeaac42817
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=399523311 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.399523311
Directory /workspace/14.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.2851564200
Short name T196
Test name
Test status
Simulation time 337079690000 ps
CPU time 835.89 seconds
Started Aug 03 04:21:56 PM PDT 24
Finished Aug 03 04:56:30 PM PDT 24
Peak memory 160648 kb
Host smart-641dab6e-1de7-4d66-bd75-399f9443061c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2851564200 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.2851564200
Directory /workspace/15.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.398598124
Short name T175
Test name
Test status
Simulation time 336731050000 ps
CPU time 797.45 seconds
Started Aug 03 04:20:44 PM PDT 24
Finished Aug 03 04:53:48 PM PDT 24
Peak memory 160132 kb
Host smart-1403895d-6f78-4f4c-902e-c69b989b1011
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=398598124 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.398598124
Directory /workspace/16.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.1529794466
Short name T193
Test name
Test status
Simulation time 336810230000 ps
CPU time 703.79 seconds
Started Aug 03 04:23:35 PM PDT 24
Finished Aug 03 04:52:04 PM PDT 24
Peak memory 160628 kb
Host smart-b0855593-da49-4f35-8c7b-57fde2b28fe9
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1529794466 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.1529794466
Directory /workspace/17.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.2672310708
Short name T176
Test name
Test status
Simulation time 337038090000 ps
CPU time 1053.88 seconds
Started Aug 03 04:19:35 PM PDT 24
Finished Aug 03 05:02:12 PM PDT 24
Peak memory 160664 kb
Host smart-8251b812-3246-4521-b305-67e679739273
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2672310708 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.2672310708
Directory /workspace/18.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.2907820761
Short name T179
Test name
Test status
Simulation time 336687310000 ps
CPU time 846.2 seconds
Started Aug 03 04:19:14 PM PDT 24
Finished Aug 03 04:54:21 PM PDT 24
Peak memory 160652 kb
Host smart-bd5eb6d7-3737-4782-92fc-0ab348a48541
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2907820761 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.2907820761
Directory /workspace/19.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.1906109922
Short name T163
Test name
Test status
Simulation time 337076890000 ps
CPU time 825.97 seconds
Started Aug 03 04:22:28 PM PDT 24
Finished Aug 03 04:57:01 PM PDT 24
Peak memory 160636 kb
Host smart-7b61212f-b90f-487a-b017-dd859d0ed8cd
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1906109922 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.1906109922
Directory /workspace/2.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.3976399691
Short name T181
Test name
Test status
Simulation time 336931730000 ps
CPU time 770.86 seconds
Started Aug 03 04:21:28 PM PDT 24
Finished Aug 03 04:53:41 PM PDT 24
Peak memory 159404 kb
Host smart-9dcf90a9-306b-4fdd-a2a3-d37ba471ffee
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3976399691 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.3976399691
Directory /workspace/20.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.627301721
Short name T174
Test name
Test status
Simulation time 336516550000 ps
CPU time 876.6 seconds
Started Aug 03 04:21:15 PM PDT 24
Finished Aug 03 04:58:21 PM PDT 24
Peak memory 160644 kb
Host smart-71cb6fa3-6c62-4826-b40e-880883fe0de5
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=627301721 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.627301721
Directory /workspace/21.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.971547548
Short name T168
Test name
Test status
Simulation time 337042690000 ps
CPU time 785.46 seconds
Started Aug 03 04:20:40 PM PDT 24
Finished Aug 03 04:54:09 PM PDT 24
Peak memory 158588 kb
Host smart-e6d4372b-358a-4d81-8469-0d674bc48053
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=971547548 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.971547548
Directory /workspace/22.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.2222377024
Short name T186
Test name
Test status
Simulation time 336720990000 ps
CPU time 839.8 seconds
Started Aug 03 04:20:53 PM PDT 24
Finished Aug 03 04:55:40 PM PDT 24
Peak memory 160160 kb
Host smart-f1f0ffca-604d-4258-af45-50fa1aab6182
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2222377024 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.2222377024
Directory /workspace/23.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.1188454861
Short name T185
Test name
Test status
Simulation time 336906950000 ps
CPU time 752.26 seconds
Started Aug 03 04:21:37 PM PDT 24
Finished Aug 03 04:52:50 PM PDT 24
Peak memory 160328 kb
Host smart-ec09cdb5-7b0f-4ce2-bb5e-4ac05704e65e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1188454861 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.1188454861
Directory /workspace/24.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.660511711
Short name T167
Test name
Test status
Simulation time 337076630000 ps
CPU time 962.13 seconds
Started Aug 03 04:19:28 PM PDT 24
Finished Aug 03 04:59:04 PM PDT 24
Peak memory 160596 kb
Host smart-20d8665b-f5a3-409b-8796-701f9c164dc0
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=660511711 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.660511711
Directory /workspace/25.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.3534265014
Short name T177
Test name
Test status
Simulation time 336820010000 ps
CPU time 709.57 seconds
Started Aug 03 04:21:39 PM PDT 24
Finished Aug 03 04:50:40 PM PDT 24
Peak memory 160556 kb
Host smart-8dd68c32-047f-4c5d-9e19-1bcd6befdd4f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3534265014 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.3534265014
Directory /workspace/26.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.696752041
Short name T164
Test name
Test status
Simulation time 336701330000 ps
CPU time 1026.51 seconds
Started Aug 03 04:21:07 PM PDT 24
Finished Aug 03 05:04:15 PM PDT 24
Peak memory 160624 kb
Host smart-7f025123-ca70-4558-b17e-540845d79970
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=696752041 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.696752041
Directory /workspace/27.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.1519128695
Short name T162
Test name
Test status
Simulation time 336461330000 ps
CPU time 954.22 seconds
Started Aug 03 04:21:06 PM PDT 24
Finished Aug 03 05:00:27 PM PDT 24
Peak memory 160612 kb
Host smart-99a0be9a-0162-47dd-9560-3af9f785aad2
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1519128695 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.1519128695
Directory /workspace/28.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.4009705097
Short name T183
Test name
Test status
Simulation time 337040130000 ps
CPU time 738.34 seconds
Started Aug 03 04:21:30 PM PDT 24
Finished Aug 03 04:51:56 PM PDT 24
Peak memory 160560 kb
Host smart-e9cb481c-03de-46e9-aa23-4b8c3dd79a90
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4009705097 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.4009705097
Directory /workspace/29.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.2425855681
Short name T165
Test name
Test status
Simulation time 336423630000 ps
CPU time 783.92 seconds
Started Aug 03 04:22:57 PM PDT 24
Finished Aug 03 04:55:55 PM PDT 24
Peak memory 160628 kb
Host smart-09175c5c-ab23-4738-94f3-8afcbf25d53e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2425855681 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.2425855681
Directory /workspace/3.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.4204656643
Short name T200
Test name
Test status
Simulation time 337059570000 ps
CPU time 839.36 seconds
Started Aug 03 04:21:40 PM PDT 24
Finished Aug 03 04:56:15 PM PDT 24
Peak memory 160592 kb
Host smart-18c545f2-ff90-4a54-bfdb-e274b94f798b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4204656643 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.4204656643
Directory /workspace/30.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.2306611755
Short name T182
Test name
Test status
Simulation time 336615270000 ps
CPU time 803.07 seconds
Started Aug 03 04:23:41 PM PDT 24
Finished Aug 03 04:56:45 PM PDT 24
Peak memory 160644 kb
Host smart-b58d2ac3-caa7-4626-b095-19a1c967295c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2306611755 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.2306611755
Directory /workspace/31.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.317218447
Short name T26
Test name
Test status
Simulation time 337052150000 ps
CPU time 926.72 seconds
Started Aug 03 04:18:44 PM PDT 24
Finished Aug 03 04:56:31 PM PDT 24
Peak memory 160652 kb
Host smart-b43b1e00-121b-4b8f-9667-7859e17e3efd
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=317218447 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.317218447
Directory /workspace/32.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.3841892790
Short name T29
Test name
Test status
Simulation time 336727830000 ps
CPU time 1034.59 seconds
Started Aug 03 04:21:20 PM PDT 24
Finished Aug 03 05:04:25 PM PDT 24
Peak memory 160636 kb
Host smart-5e3abb57-8f55-4595-8fae-0a4d8c0e18ad
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3841892790 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.3841892790
Directory /workspace/33.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.2161141226
Short name T170
Test name
Test status
Simulation time 336689870000 ps
CPU time 962.18 seconds
Started Aug 03 04:19:28 PM PDT 24
Finished Aug 03 04:59:11 PM PDT 24
Peak memory 160608 kb
Host smart-ac22514b-1a1e-4f9b-a245-027b61e51cfc
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2161141226 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.2161141226
Directory /workspace/34.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.753130712
Short name T173
Test name
Test status
Simulation time 336375970000 ps
CPU time 887.59 seconds
Started Aug 03 04:21:26 PM PDT 24
Finished Aug 03 04:57:50 PM PDT 24
Peak memory 160660 kb
Host smart-60864db3-486d-47d8-b7e0-4b6e579d4d61
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=753130712 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.753130712
Directory /workspace/35.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.3393812234
Short name T172
Test name
Test status
Simulation time 336839270000 ps
CPU time 1038.24 seconds
Started Aug 03 04:21:20 PM PDT 24
Finished Aug 03 05:04:23 PM PDT 24
Peak memory 160636 kb
Host smart-39d7a8d0-7f96-4287-9b00-a20d6b6286e3
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3393812234 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.3393812234
Directory /workspace/36.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.1409182972
Short name T169
Test name
Test status
Simulation time 336728050000 ps
CPU time 827.53 seconds
Started Aug 03 04:21:41 PM PDT 24
Finished Aug 03 04:56:28 PM PDT 24
Peak memory 160648 kb
Host smart-ffbea16c-3abc-4fc5-850c-5aebe8a37077
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1409182972 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.1409182972
Directory /workspace/37.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3961867211
Short name T189
Test name
Test status
Simulation time 336697470000 ps
CPU time 1063.26 seconds
Started Aug 03 04:21:46 PM PDT 24
Finished Aug 03 05:04:34 PM PDT 24
Peak memory 160664 kb
Host smart-6f442492-613f-4328-918a-b7fcfc5cd397
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3961867211 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.3961867211
Directory /workspace/38.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.3306271454
Short name T161
Test name
Test status
Simulation time 336564510000 ps
CPU time 759.98 seconds
Started Aug 03 04:21:54 PM PDT 24
Finished Aug 03 04:54:17 PM PDT 24
Peak memory 160604 kb
Host smart-ab300eb9-7a4c-48e0-8ca2-9c5ddbca2198
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3306271454 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.3306271454
Directory /workspace/39.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.3139549462
Short name T178
Test name
Test status
Simulation time 336687510000 ps
CPU time 644.88 seconds
Started Aug 03 04:21:14 PM PDT 24
Finished Aug 03 04:47:30 PM PDT 24
Peak memory 160620 kb
Host smart-8844dcb5-22b6-41b7-94bb-b25716580603
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3139549462 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.3139549462
Directory /workspace/4.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.3516711922
Short name T30
Test name
Test status
Simulation time 336488010000 ps
CPU time 890.59 seconds
Started Aug 03 04:21:40 PM PDT 24
Finished Aug 03 04:58:24 PM PDT 24
Peak memory 160612 kb
Host smart-9dbd1518-0d9f-4092-be75-4214a5e70700
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3516711922 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.3516711922
Directory /workspace/40.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.2819642182
Short name T192
Test name
Test status
Simulation time 336368910000 ps
CPU time 820.74 seconds
Started Aug 03 04:22:25 PM PDT 24
Finished Aug 03 04:56:26 PM PDT 24
Peak memory 160596 kb
Host smart-737a58c1-ef6d-4088-8dfb-e58111ba7be4
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2819642182 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.2819642182
Directory /workspace/41.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.592384370
Short name T23
Test name
Test status
Simulation time 336449190000 ps
CPU time 867.36 seconds
Started Aug 03 04:20:59 PM PDT 24
Finished Aug 03 04:56:03 PM PDT 24
Peak memory 160552 kb
Host smart-b5248e8d-44c7-481c-b72c-87344a062774
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=592384370 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.592384370
Directory /workspace/42.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.125536138
Short name T187
Test name
Test status
Simulation time 336889970000 ps
CPU time 851.58 seconds
Started Aug 03 04:20:59 PM PDT 24
Finished Aug 03 04:55:39 PM PDT 24
Peak memory 160552 kb
Host smart-26a0bf44-97f0-4c72-b259-120c23c85062
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=125536138 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.125536138
Directory /workspace/43.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.1509413054
Short name T195
Test name
Test status
Simulation time 336479430000 ps
CPU time 973.26 seconds
Started Aug 03 04:19:28 PM PDT 24
Finished Aug 03 04:59:26 PM PDT 24
Peak memory 160608 kb
Host smart-e42470e3-e03d-41f4-9dcf-6401451836e0
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1509413054 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.1509413054
Directory /workspace/44.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.780505423
Short name T184
Test name
Test status
Simulation time 337035770000 ps
CPU time 713.36 seconds
Started Aug 03 04:22:42 PM PDT 24
Finished Aug 03 04:51:50 PM PDT 24
Peak memory 160540 kb
Host smart-ff9bf2fd-67eb-4354-8973-1895961f21b9
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=780505423 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.780505423
Directory /workspace/45.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.3232003434
Short name T199
Test name
Test status
Simulation time 337115690000 ps
CPU time 868.52 seconds
Started Aug 03 04:20:59 PM PDT 24
Finished Aug 03 04:56:08 PM PDT 24
Peak memory 160560 kb
Host smart-83ffd2c2-8886-4673-8086-9591b07beed3
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3232003434 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.3232003434
Directory /workspace/46.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.3379056341
Short name T197
Test name
Test status
Simulation time 336723690000 ps
CPU time 775.07 seconds
Started Aug 03 04:20:42 PM PDT 24
Finished Aug 03 04:52:19 PM PDT 24
Peak memory 159496 kb
Host smart-a82ec9d4-a4d0-4041-9fb1-4db702589c5f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3379056341 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.3379056341
Directory /workspace/47.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.522156698
Short name T28
Test name
Test status
Simulation time 336369810000 ps
CPU time 678.76 seconds
Started Aug 03 04:22:15 PM PDT 24
Finished Aug 03 04:49:49 PM PDT 24
Peak memory 160632 kb
Host smart-fcf4805f-f57f-4e3d-ac31-719254ce35e5
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=522156698 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.522156698
Directory /workspace/48.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.3967244501
Short name T194
Test name
Test status
Simulation time 336484850000 ps
CPU time 692.42 seconds
Started Aug 03 04:20:39 PM PDT 24
Finished Aug 03 04:48:51 PM PDT 24
Peak memory 160676 kb
Host smart-860f11a0-6367-404b-a480-ada34ae87b65
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3967244501 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.3967244501
Directory /workspace/49.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.3380068407
Short name T24
Test name
Test status
Simulation time 336442810000 ps
CPU time 799.05 seconds
Started Aug 03 04:18:38 PM PDT 24
Finished Aug 03 04:51:14 PM PDT 24
Peak memory 160912 kb
Host smart-64d12197-48f8-4073-89ba-c24ed2be860c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3380068407 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.3380068407
Directory /workspace/5.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.2539224088
Short name T198
Test name
Test status
Simulation time 336507410000 ps
CPU time 912.64 seconds
Started Aug 03 04:18:40 PM PDT 24
Finished Aug 03 04:55:49 PM PDT 24
Peak memory 160624 kb
Host smart-80f0a69b-709c-4e81-b71e-8a1b333b1fb2
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2539224088 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.2539224088
Directory /workspace/6.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.2362150551
Short name T21
Test name
Test status
Simulation time 336900790000 ps
CPU time 835.49 seconds
Started Aug 03 04:22:45 PM PDT 24
Finished Aug 03 04:57:33 PM PDT 24
Peak memory 160640 kb
Host smart-452a92d7-d93d-4e51-a5e1-fae04341f3ba
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2362150551 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.2362150551
Directory /workspace/7.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.4257106891
Short name T190
Test name
Test status
Simulation time 336369850000 ps
CPU time 796.53 seconds
Started Aug 03 04:18:36 PM PDT 24
Finished Aug 03 04:51:00 PM PDT 24
Peak memory 160912 kb
Host smart-0a0b7620-0d66-411e-a920-6c803bfd9d3c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4257106891 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.4257106891
Directory /workspace/8.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.552706855
Short name T27
Test name
Test status
Simulation time 336772030000 ps
CPU time 807.2 seconds
Started Aug 03 04:21:37 PM PDT 24
Finished Aug 03 04:54:48 PM PDT 24
Peak memory 160320 kb
Host smart-31d8d263-eae6-4add-93a2-91fed07daae7
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=552706855 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.552706855
Directory /workspace/9.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.3709856820
Short name T134
Test name
Test status
Simulation time 1536890000 ps
CPU time 4.99 seconds
Started Aug 03 04:18:44 PM PDT 24
Finished Aug 03 04:18:55 PM PDT 24
Peak memory 164692 kb
Host smart-56defdfa-1030-40b1-89e4-fd903c5811a1
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3709856820 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.3709856820
Directory /workspace/0.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.487782798
Short name T118
Test name
Test status
Simulation time 1339030000 ps
CPU time 4.62 seconds
Started Aug 03 04:22:46 PM PDT 24
Finished Aug 03 04:22:56 PM PDT 24
Peak memory 164712 kb
Host smart-00ab751d-3bc7-4a41-9e20-5268c9d6424f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=487782798 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.487782798
Directory /workspace/1.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.2256406028
Short name T122
Test name
Test status
Simulation time 1425950000 ps
CPU time 3.76 seconds
Started Aug 03 04:21:08 PM PDT 24
Finished Aug 03 04:21:17 PM PDT 24
Peak memory 163408 kb
Host smart-6199b475-ffc3-47ef-8565-6fcbeadd56e3
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2256406028 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.2256406028
Directory /workspace/10.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.485182586
Short name T121
Test name
Test status
Simulation time 1397050000 ps
CPU time 4.69 seconds
Started Aug 03 04:19:14 PM PDT 24
Finished Aug 03 04:19:25 PM PDT 24
Peak memory 164744 kb
Host smart-7b68ddfc-7822-4555-8ee9-e91d98465b81
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=485182586 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.485182586
Directory /workspace/11.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.4280503448
Short name T141
Test name
Test status
Simulation time 1085010000 ps
CPU time 3.56 seconds
Started Aug 03 04:19:43 PM PDT 24
Finished Aug 03 04:19:51 PM PDT 24
Peak memory 164664 kb
Host smart-604b53b6-2978-4eac-9acf-45e7a19e5e06
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4280503448 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.4280503448
Directory /workspace/12.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.3361023735
Short name T153
Test name
Test status
Simulation time 1544750000 ps
CPU time 4.43 seconds
Started Aug 03 04:21:03 PM PDT 24
Finished Aug 03 04:21:13 PM PDT 24
Peak memory 164576 kb
Host smart-484782be-8d0a-452c-9a02-47000eaec276
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3361023735 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.3361023735
Directory /workspace/13.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.4221586459
Short name T124
Test name
Test status
Simulation time 1186690000 ps
CPU time 2.99 seconds
Started Aug 03 04:20:47 PM PDT 24
Finished Aug 03 04:20:53 PM PDT 24
Peak memory 163664 kb
Host smart-a4399f8c-02f9-4269-8064-fd3132329909
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4221586459 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.4221586459
Directory /workspace/14.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.1111944504
Short name T117
Test name
Test status
Simulation time 1321630000 ps
CPU time 3.96 seconds
Started Aug 03 04:21:02 PM PDT 24
Finished Aug 03 04:21:10 PM PDT 24
Peak memory 164720 kb
Host smart-5fb8ac48-33a0-479e-a69a-ec68ea16a0fc
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1111944504 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.1111944504
Directory /workspace/15.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.3215531677
Short name T132
Test name
Test status
Simulation time 1599930000 ps
CPU time 4.54 seconds
Started Aug 03 04:21:03 PM PDT 24
Finished Aug 03 04:21:13 PM PDT 24
Peak memory 164504 kb
Host smart-7c916b18-da0a-4566-8e8e-4962dd86462f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3215531677 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.3215531677
Directory /workspace/16.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.2027079915
Short name T144
Test name
Test status
Simulation time 1514010000 ps
CPU time 3.88 seconds
Started Aug 03 04:20:57 PM PDT 24
Finished Aug 03 04:21:06 PM PDT 24
Peak memory 163416 kb
Host smart-93ae2e8b-abd2-4aaa-978b-2ada00f55b78
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2027079915 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.2027079915
Directory /workspace/17.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.1289015499
Short name T140
Test name
Test status
Simulation time 1497650000 ps
CPU time 5 seconds
Started Aug 03 04:19:59 PM PDT 24
Finished Aug 03 04:20:10 PM PDT 24
Peak memory 164756 kb
Host smart-e710aad4-29fc-4de4-b692-dd9d7437f914
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1289015499 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.1289015499
Directory /workspace/18.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.114791571
Short name T154
Test name
Test status
Simulation time 1366210000 ps
CPU time 3.05 seconds
Started Aug 03 04:20:47 PM PDT 24
Finished Aug 03 04:20:54 PM PDT 24
Peak memory 164192 kb
Host smart-215d89cb-8ca7-4b40-9256-7680c28ebbff
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=114791571 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.114791571
Directory /workspace/19.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.2373846134
Short name T159
Test name
Test status
Simulation time 1382830000 ps
CPU time 4.38 seconds
Started Aug 03 04:21:53 PM PDT 24
Finished Aug 03 04:22:03 PM PDT 24
Peak memory 164728 kb
Host smart-5d2c5914-2ec8-470a-81e4-cf077e202185
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2373846134 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.2373846134
Directory /workspace/2.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.301521550
Short name T127
Test name
Test status
Simulation time 1539290000 ps
CPU time 4.21 seconds
Started Aug 03 04:19:38 PM PDT 24
Finished Aug 03 04:19:47 PM PDT 24
Peak memory 164732 kb
Host smart-b97b72b3-f25a-48ff-a812-1b8ee216051d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=301521550 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.301521550
Directory /workspace/20.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.1862097694
Short name T150
Test name
Test status
Simulation time 1592370000 ps
CPU time 3.17 seconds
Started Aug 03 04:20:47 PM PDT 24
Finished Aug 03 04:20:55 PM PDT 24
Peak memory 164532 kb
Host smart-2e4b5406-581d-4b9a-a8aa-13c86e206a6d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1862097694 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.1862097694
Directory /workspace/21.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.611360818
Short name T130
Test name
Test status
Simulation time 1355970000 ps
CPU time 3.8 seconds
Started Aug 03 04:19:48 PM PDT 24
Finished Aug 03 04:19:56 PM PDT 24
Peak memory 164692 kb
Host smart-78908082-a745-424a-b555-f155af235808
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=611360818 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.611360818
Directory /workspace/22.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.4052013966
Short name T142
Test name
Test status
Simulation time 1382630000 ps
CPU time 3.56 seconds
Started Aug 03 04:20:58 PM PDT 24
Finished Aug 03 04:21:05 PM PDT 24
Peak memory 163436 kb
Host smart-fd226947-8020-4d81-b3a1-1a947e4ec41f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4052013966 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.4052013966
Directory /workspace/23.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.1356929785
Short name T160
Test name
Test status
Simulation time 1373450000 ps
CPU time 3.66 seconds
Started Aug 03 04:21:04 PM PDT 24
Finished Aug 03 04:21:12 PM PDT 24
Peak memory 164536 kb
Host smart-b6532f93-75f7-4d60-a36c-189f682fe02b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1356929785 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.1356929785
Directory /workspace/24.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.4016231064
Short name T115
Test name
Test status
Simulation time 1331670000 ps
CPU time 3.92 seconds
Started Aug 03 04:21:01 PM PDT 24
Finished Aug 03 04:21:10 PM PDT 24
Peak memory 164320 kb
Host smart-0520f11a-0c86-40e4-b893-5ddfa019322c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4016231064 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.4016231064
Directory /workspace/25.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.1922768503
Short name T138
Test name
Test status
Simulation time 1268670000 ps
CPU time 3.88 seconds
Started Aug 03 04:21:03 PM PDT 24
Finished Aug 03 04:21:11 PM PDT 24
Peak memory 164280 kb
Host smart-45b67597-e698-4e6a-b44c-a79302f4c199
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1922768503 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.1922768503
Directory /workspace/26.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.3567968064
Short name T151
Test name
Test status
Simulation time 1285170000 ps
CPU time 3.91 seconds
Started Aug 03 04:20:17 PM PDT 24
Finished Aug 03 04:20:25 PM PDT 24
Peak memory 164756 kb
Host smart-966fc98b-cf9a-4701-b45c-4a227731aabe
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3567968064 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.3567968064
Directory /workspace/27.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.2504243387
Short name T139
Test name
Test status
Simulation time 1434530000 ps
CPU time 5.12 seconds
Started Aug 03 04:19:58 PM PDT 24
Finished Aug 03 04:20:10 PM PDT 24
Peak memory 164696 kb
Host smart-4cf2e829-00ca-4ff7-9e0e-5bca865e1048
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2504243387 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.2504243387
Directory /workspace/28.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.339737727
Short name T129
Test name
Test status
Simulation time 1565130000 ps
CPU time 5.01 seconds
Started Aug 03 04:19:44 PM PDT 24
Finished Aug 03 04:19:55 PM PDT 24
Peak memory 164668 kb
Host smart-c2468573-fbc5-41da-ace7-9fe6f90c3082
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=339737727 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.339737727
Directory /workspace/29.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.2894871211
Short name T149
Test name
Test status
Simulation time 1440650000 ps
CPU time 4.26 seconds
Started Aug 03 04:21:37 PM PDT 24
Finished Aug 03 04:21:46 PM PDT 24
Peak memory 164236 kb
Host smart-d1359ea2-105b-4cd1-a498-05fd0e108765
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2894871211 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.2894871211
Directory /workspace/3.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.1612672710
Short name T126
Test name
Test status
Simulation time 1506610000 ps
CPU time 3.45 seconds
Started Aug 03 04:21:24 PM PDT 24
Finished Aug 03 04:21:31 PM PDT 24
Peak memory 164696 kb
Host smart-3d5fc52a-1223-40fa-8b70-760804bcbfa3
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1612672710 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.1612672710
Directory /workspace/30.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.1654595030
Short name T145
Test name
Test status
Simulation time 1470810000 ps
CPU time 4.79 seconds
Started Aug 03 04:20:14 PM PDT 24
Finished Aug 03 04:20:24 PM PDT 24
Peak memory 165012 kb
Host smart-6cd15a02-cad2-4a34-a2e9-aea1ce1947a6
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1654595030 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.1654595030
Directory /workspace/31.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.4086348595
Short name T156
Test name
Test status
Simulation time 1565610000 ps
CPU time 4.16 seconds
Started Aug 03 04:20:23 PM PDT 24
Finished Aug 03 04:20:33 PM PDT 24
Peak memory 164776 kb
Host smart-321908a7-7a7e-4de2-b664-d52497f741fe
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4086348595 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.4086348595
Directory /workspace/32.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.1961483769
Short name T143
Test name
Test status
Simulation time 1565850000 ps
CPU time 5.32 seconds
Started Aug 03 04:20:20 PM PDT 24
Finished Aug 03 04:20:32 PM PDT 24
Peak memory 164756 kb
Host smart-f9603d61-3bb4-4ec2-b741-ad17a01005ed
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1961483769 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.1961483769
Directory /workspace/33.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.3531766262
Short name T152
Test name
Test status
Simulation time 1439030000 ps
CPU time 4.51 seconds
Started Aug 03 04:19:55 PM PDT 24
Finished Aug 03 04:20:05 PM PDT 24
Peak memory 165012 kb
Host smart-fc134c78-b05b-4a75-a003-539c38cecec8
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3531766262 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.3531766262
Directory /workspace/34.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.2108082507
Short name T133
Test name
Test status
Simulation time 1543710000 ps
CPU time 4.28 seconds
Started Aug 03 04:19:48 PM PDT 24
Finished Aug 03 04:19:58 PM PDT 24
Peak memory 164800 kb
Host smart-da320566-0870-4be8-8949-a40d98040cba
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2108082507 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.2108082507
Directory /workspace/35.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.2021079085
Short name T119
Test name
Test status
Simulation time 1480110000 ps
CPU time 4.75 seconds
Started Aug 03 04:21:32 PM PDT 24
Finished Aug 03 04:21:43 PM PDT 24
Peak memory 164656 kb
Host smart-f243f3e4-a7c4-4d8e-b807-cb489f9fd709
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2021079085 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.2021079085
Directory /workspace/36.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.2821985863
Short name T157
Test name
Test status
Simulation time 1580550000 ps
CPU time 3.82 seconds
Started Aug 03 04:20:53 PM PDT 24
Finished Aug 03 04:21:02 PM PDT 24
Peak memory 164732 kb
Host smart-106d711f-b987-4581-990e-0b6ebd223c03
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2821985863 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.2821985863
Directory /workspace/37.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.3029297974
Short name T135
Test name
Test status
Simulation time 1481610000 ps
CPU time 5.05 seconds
Started Aug 03 04:21:01 PM PDT 24
Finished Aug 03 04:21:13 PM PDT 24
Peak memory 163456 kb
Host smart-aefd4d35-1483-4272-83c0-2eeea14ae6a0
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3029297974 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.3029297974
Directory /workspace/38.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.2399847409
Short name T155
Test name
Test status
Simulation time 1386950000 ps
CPU time 4.73 seconds
Started Aug 03 04:21:02 PM PDT 24
Finished Aug 03 04:21:12 PM PDT 24
Peak memory 164248 kb
Host smart-40dc0ea9-7dbf-4f02-8fa9-ca2d7e5eec2c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2399847409 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.2399847409
Directory /workspace/39.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.2330440282
Short name T114
Test name
Test status
Simulation time 1278630000 ps
CPU time 3.66 seconds
Started Aug 03 04:19:38 PM PDT 24
Finished Aug 03 04:19:46 PM PDT 24
Peak memory 164676 kb
Host smart-7e34cf1e-cdf9-4313-83d8-8f6c7d65ef40
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2330440282 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.2330440282
Directory /workspace/4.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.513964370
Short name T128
Test name
Test status
Simulation time 1193630000 ps
CPU time 4.49 seconds
Started Aug 03 04:21:02 PM PDT 24
Finished Aug 03 04:21:12 PM PDT 24
Peak memory 164840 kb
Host smart-371fa031-cda3-4043-b835-7ea167f56b99
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=513964370 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.513964370
Directory /workspace/40.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.53626694
Short name T112
Test name
Test status
Simulation time 1600890000 ps
CPU time 5.48 seconds
Started Aug 03 04:21:01 PM PDT 24
Finished Aug 03 04:21:14 PM PDT 24
Peak memory 163472 kb
Host smart-010fa31e-4c02-4e02-b05b-3961d97b5577
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=53626694 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.53626694
Directory /workspace/41.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.2698244048
Short name T147
Test name
Test status
Simulation time 1457110000 ps
CPU time 4.41 seconds
Started Aug 03 04:21:25 PM PDT 24
Finished Aug 03 04:21:36 PM PDT 24
Peak memory 164688 kb
Host smart-3a61ae02-843c-46b1-8c65-da49e577cd60
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2698244048 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.2698244048
Directory /workspace/42.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.298115772
Short name T120
Test name
Test status
Simulation time 1401730000 ps
CPU time 3.03 seconds
Started Aug 03 04:21:51 PM PDT 24
Finished Aug 03 04:21:58 PM PDT 24
Peak memory 164700 kb
Host smart-a6bde613-9023-4eba-b1c1-c040e9c3128e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=298115772 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.298115772
Directory /workspace/43.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.3204393074
Short name T146
Test name
Test status
Simulation time 1426750000 ps
CPU time 3.93 seconds
Started Aug 03 04:20:26 PM PDT 24
Finished Aug 03 04:20:35 PM PDT 24
Peak memory 164776 kb
Host smart-8c98a719-b1e4-4192-80ce-dadb170829c7
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3204393074 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.3204393074
Directory /workspace/44.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.882010648
Short name T136
Test name
Test status
Simulation time 1361310000 ps
CPU time 3.48 seconds
Started Aug 03 04:21:03 PM PDT 24
Finished Aug 03 04:21:10 PM PDT 24
Peak memory 164668 kb
Host smart-83da8db7-c467-4737-b2e7-dcbe89416ae1
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=882010648 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.882010648
Directory /workspace/45.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.2640073048
Short name T125
Test name
Test status
Simulation time 1371750000 ps
CPU time 2.71 seconds
Started Aug 03 04:24:19 PM PDT 24
Finished Aug 03 04:24:26 PM PDT 24
Peak memory 164676 kb
Host smart-c8ff6d56-eff1-41c7-928e-69b1ce5f26c9
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2640073048 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.2640073048
Directory /workspace/46.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.601465830
Short name T137
Test name
Test status
Simulation time 1234650000 ps
CPU time 2.81 seconds
Started Aug 03 04:20:48 PM PDT 24
Finished Aug 03 04:20:54 PM PDT 24
Peak memory 164388 kb
Host smart-3324b991-8085-40f1-8086-f4d8a47b7f4b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=601465830 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.601465830
Directory /workspace/47.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.801768648
Short name T158
Test name
Test status
Simulation time 1555770000 ps
CPU time 4.18 seconds
Started Aug 03 04:20:26 PM PDT 24
Finished Aug 03 04:20:36 PM PDT 24
Peak memory 164768 kb
Host smart-9c4ef9f3-04cd-4769-985f-8d6673cf828d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=801768648 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.801768648
Directory /workspace/48.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.935396718
Short name T131
Test name
Test status
Simulation time 1464770000 ps
CPU time 4.4 seconds
Started Aug 03 04:20:38 PM PDT 24
Finished Aug 03 04:20:48 PM PDT 24
Peak memory 164780 kb
Host smart-6dd468fc-e26f-4dce-9686-6b182d06d3c1
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=935396718 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.935396718
Directory /workspace/49.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.1097972686
Short name T148
Test name
Test status
Simulation time 1538390000 ps
CPU time 3.91 seconds
Started Aug 03 04:20:57 PM PDT 24
Finished Aug 03 04:21:07 PM PDT 24
Peak memory 163564 kb
Host smart-6afc4c57-f8f4-4ece-831c-f5dcfce4be82
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1097972686 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.1097972686
Directory /workspace/5.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.4116484394
Short name T113
Test name
Test status
Simulation time 1386450000 ps
CPU time 3.85 seconds
Started Aug 03 04:20:44 PM PDT 24
Finished Aug 03 04:20:52 PM PDT 24
Peak memory 162704 kb
Host smart-37e6ab4c-aa59-4db6-9338-36f33db04967
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4116484394 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.4116484394
Directory /workspace/6.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.2366142477
Short name T111
Test name
Test status
Simulation time 1479550000 ps
CPU time 5.33 seconds
Started Aug 03 04:19:24 PM PDT 24
Finished Aug 03 04:19:36 PM PDT 24
Peak memory 164748 kb
Host smart-e2e765f6-6d07-47da-bb24-e8b83b79a057
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2366142477 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.2366142477
Directory /workspace/7.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.2212753275
Short name T123
Test name
Test status
Simulation time 1443630000 ps
CPU time 5.04 seconds
Started Aug 03 04:20:01 PM PDT 24
Finished Aug 03 04:20:12 PM PDT 24
Peak memory 164736 kb
Host smart-8ab750fc-a972-4615-920b-ba5cc38c0c77
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2212753275 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.2212753275
Directory /workspace/8.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.3588882095
Short name T116
Test name
Test status
Simulation time 1322890000 ps
CPU time 4.28 seconds
Started Aug 03 04:21:37 PM PDT 24
Finished Aug 03 04:21:46 PM PDT 24
Peak memory 164696 kb
Host smart-ac7d60d7-d122-4676-939c-6fd41c2f8e75
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3588882095 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.3588882095
Directory /workspace/9.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.2386598778
Short name T44
Test name
Test status
Simulation time 1503290000 ps
CPU time 4.53 seconds
Started Aug 03 04:21:54 PM PDT 24
Finished Aug 03 04:22:04 PM PDT 24
Peak memory 164724 kb
Host smart-cfb68e87-385c-4049-9d95-8b283be73e4f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2386598778 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.2386598778
Directory /workspace/0.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.1073569248
Short name T42
Test name
Test status
Simulation time 1524770000 ps
CPU time 3 seconds
Started Aug 03 04:22:33 PM PDT 24
Finished Aug 03 04:22:40 PM PDT 24
Peak memory 164704 kb
Host smart-345e9947-a695-4374-bef3-82edc8c0ac2f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1073569248 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.1073569248
Directory /workspace/1.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.1978963692
Short name T31
Test name
Test status
Simulation time 1340170000 ps
CPU time 3.8 seconds
Started Aug 03 04:20:44 PM PDT 24
Finished Aug 03 04:20:52 PM PDT 24
Peak memory 162716 kb
Host smart-3ff2ddd4-755d-4e5d-bc3c-c3b596105081
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1978963692 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.1978963692
Directory /workspace/10.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.2298102843
Short name T61
Test name
Test status
Simulation time 1436230000 ps
CPU time 3.82 seconds
Started Aug 03 04:23:01 PM PDT 24
Finished Aug 03 04:23:10 PM PDT 24
Peak memory 164732 kb
Host smart-052fb5b7-d2ee-46b0-844a-92b0b5b0842a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2298102843 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.2298102843
Directory /workspace/12.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.2008057294
Short name T67
Test name
Test status
Simulation time 1523990000 ps
CPU time 3.9 seconds
Started Aug 03 04:21:15 PM PDT 24
Finished Aug 03 04:21:24 PM PDT 24
Peak memory 164768 kb
Host smart-7983822d-02c1-4b71-9e27-f4188fc537b2
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2008057294 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.2008057294
Directory /workspace/13.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.2018614677
Short name T49
Test name
Test status
Simulation time 1530230000 ps
CPU time 5.4 seconds
Started Aug 03 04:19:07 PM PDT 24
Finished Aug 03 04:19:18 PM PDT 24
Peak memory 164692 kb
Host smart-e93fa98d-ab89-403c-866f-2a8cdd0a35e7
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2018614677 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.2018614677
Directory /workspace/14.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.212862089
Short name T52
Test name
Test status
Simulation time 1546630000 ps
CPU time 5.57 seconds
Started Aug 03 04:18:49 PM PDT 24
Finished Aug 03 04:19:01 PM PDT 24
Peak memory 164752 kb
Host smart-765139cf-9cda-4123-bb59-7a22417d000c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=212862089 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.212862089
Directory /workspace/15.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.3446590615
Short name T3
Test name
Test status
Simulation time 1511290000 ps
CPU time 5.05 seconds
Started Aug 03 04:19:48 PM PDT 24
Finished Aug 03 04:19:59 PM PDT 24
Peak memory 164656 kb
Host smart-5b1b7d86-7227-447f-a2f2-cded545da439
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3446590615 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.3446590615
Directory /workspace/16.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.991893948
Short name T66
Test name
Test status
Simulation time 1465650000 ps
CPU time 5.49 seconds
Started Aug 03 04:21:17 PM PDT 24
Finished Aug 03 04:21:30 PM PDT 24
Peak memory 164660 kb
Host smart-ce3b7fc7-8abf-4604-b7a7-29395a17567d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=991893948 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.991893948
Directory /workspace/17.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.3687620868
Short name T64
Test name
Test status
Simulation time 1667650000 ps
CPU time 4.58 seconds
Started Aug 03 04:21:39 PM PDT 24
Finished Aug 03 04:21:50 PM PDT 24
Peak memory 164692 kb
Host smart-9e12e1b2-e39e-4e83-baf4-f59f81ff58f3
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3687620868 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.3687620868
Directory /workspace/18.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.2283137726
Short name T8
Test name
Test status
Simulation time 1551030000 ps
CPU time 4.79 seconds
Started Aug 03 04:22:39 PM PDT 24
Finished Aug 03 04:22:50 PM PDT 24
Peak memory 164660 kb
Host smart-b417d136-3945-40a5-afff-01bc796aa12c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2283137726 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.2283137726
Directory /workspace/19.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.2633601420
Short name T62
Test name
Test status
Simulation time 1459550000 ps
CPU time 4.43 seconds
Started Aug 03 04:22:31 PM PDT 24
Finished Aug 03 04:22:41 PM PDT 24
Peak memory 164656 kb
Host smart-a44dbf68-7f5e-4e65-9103-be003cd47f3c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2633601420 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.2633601420
Directory /workspace/2.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.2156152202
Short name T47
Test name
Test status
Simulation time 1556350000 ps
CPU time 4.24 seconds
Started Aug 03 04:20:41 PM PDT 24
Finished Aug 03 04:20:50 PM PDT 24
Peak memory 162560 kb
Host smart-e23ed88d-c68d-4290-a70b-078b61252450
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2156152202 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.2156152202
Directory /workspace/20.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.1069382137
Short name T35
Test name
Test status
Simulation time 1590930000 ps
CPU time 5.48 seconds
Started Aug 03 04:20:54 PM PDT 24
Finished Aug 03 04:21:06 PM PDT 24
Peak memory 164652 kb
Host smart-8fa386ca-5a32-441b-8a48-1f7eef3fa37f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1069382137 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.1069382137
Directory /workspace/21.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.929505977
Short name T41
Test name
Test status
Simulation time 1584210000 ps
CPU time 5.88 seconds
Started Aug 03 04:20:35 PM PDT 24
Finished Aug 03 04:20:47 PM PDT 24
Peak memory 164672 kb
Host smart-70559f42-7826-40c2-977e-0a53f5e3f6c1
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=929505977 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.929505977
Directory /workspace/22.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.1109884467
Short name T68
Test name
Test status
Simulation time 1562730000 ps
CPU time 5.41 seconds
Started Aug 03 04:21:14 PM PDT 24
Finished Aug 03 04:21:27 PM PDT 24
Peak memory 164668 kb
Host smart-351e4c7e-b539-41c3-a287-40415f0c66b2
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1109884467 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.1109884467
Directory /workspace/23.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.2773446400
Short name T40
Test name
Test status
Simulation time 1217470000 ps
CPU time 2.72 seconds
Started Aug 03 04:22:15 PM PDT 24
Finished Aug 03 04:22:21 PM PDT 24
Peak memory 164696 kb
Host smart-b5222435-98ff-4ddb-b3d2-287db4a92d28
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2773446400 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.2773446400
Directory /workspace/24.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.4150806386
Short name T57
Test name
Test status
Simulation time 1554870000 ps
CPU time 4.61 seconds
Started Aug 03 04:19:27 PM PDT 24
Finished Aug 03 04:19:37 PM PDT 24
Peak memory 164664 kb
Host smart-35e0a407-61bf-4904-9190-978d0fa10947
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4150806386 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.4150806386
Directory /workspace/25.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.4083230613
Short name T33
Test name
Test status
Simulation time 1562090000 ps
CPU time 5.99 seconds
Started Aug 03 04:21:13 PM PDT 24
Finished Aug 03 04:21:26 PM PDT 24
Peak memory 164764 kb
Host smart-0e9a892e-5ca3-4554-bb4d-4a5686b25c7a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4083230613 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.4083230613
Directory /workspace/26.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.161484937
Short name T51
Test name
Test status
Simulation time 1466370000 ps
CPU time 4.81 seconds
Started Aug 03 04:21:29 PM PDT 24
Finished Aug 03 04:21:40 PM PDT 24
Peak memory 164660 kb
Host smart-6a7e1c1a-1b0d-48bd-9244-0dbdbe65633e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=161484937 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.161484937
Directory /workspace/27.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.2621771640
Short name T70
Test name
Test status
Simulation time 1402110000 ps
CPU time 3.55 seconds
Started Aug 03 04:23:42 PM PDT 24
Finished Aug 03 04:23:50 PM PDT 24
Peak memory 164704 kb
Host smart-e5cd977e-f8f3-41ae-99ec-77c4094cd398
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2621771640 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.2621771640
Directory /workspace/28.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.3026057391
Short name T36
Test name
Test status
Simulation time 1548590000 ps
CPU time 4.19 seconds
Started Aug 03 04:19:48 PM PDT 24
Finished Aug 03 04:19:57 PM PDT 24
Peak memory 164800 kb
Host smart-6a805127-4bde-4404-9977-8f7d86a03b8c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3026057391 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.3026057391
Directory /workspace/29.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.553656221
Short name T37
Test name
Test status
Simulation time 1327810000 ps
CPU time 3.23 seconds
Started Aug 03 04:21:16 PM PDT 24
Finished Aug 03 04:21:23 PM PDT 24
Peak memory 164752 kb
Host smart-fcd040da-6ba4-43cc-85c4-7a3d2d528b2b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=553656221 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.553656221
Directory /workspace/3.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.884790887
Short name T63
Test name
Test status
Simulation time 1550690000 ps
CPU time 4.39 seconds
Started Aug 03 04:21:40 PM PDT 24
Finished Aug 03 04:21:50 PM PDT 24
Peak memory 164652 kb
Host smart-587382f7-b18d-49d0-b25f-0310a18394db
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=884790887 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.884790887
Directory /workspace/30.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.2545757740
Short name T7
Test name
Test status
Simulation time 1560490000 ps
CPU time 3.92 seconds
Started Aug 03 04:21:56 PM PDT 24
Finished Aug 03 04:22:04 PM PDT 24
Peak memory 164756 kb
Host smart-31c29fbd-62c8-4a58-9c9d-bf65c96adc18
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2545757740 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.2545757740
Directory /workspace/31.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.3964999971
Short name T58
Test name
Test status
Simulation time 1460910000 ps
CPU time 3.33 seconds
Started Aug 03 04:23:22 PM PDT 24
Finished Aug 03 04:23:30 PM PDT 24
Peak memory 163044 kb
Host smart-bf0e1919-28a4-4635-bad4-4b9656b0a2fe
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3964999971 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.3964999971
Directory /workspace/32.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.3933709773
Short name T2
Test name
Test status
Simulation time 1534970000 ps
CPU time 4.47 seconds
Started Aug 03 04:21:41 PM PDT 24
Finished Aug 03 04:21:51 PM PDT 24
Peak memory 164720 kb
Host smart-fa3db74e-69ad-47fe-954c-fef468273519
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3933709773 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.3933709773
Directory /workspace/33.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.180853405
Short name T9
Test name
Test status
Simulation time 1652710000 ps
CPU time 5.23 seconds
Started Aug 03 04:22:05 PM PDT 24
Finished Aug 03 04:22:17 PM PDT 24
Peak memory 164748 kb
Host smart-81b9ac8a-e558-4053-9d48-b027b8d898e0
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=180853405 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.180853405
Directory /workspace/34.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.860423877
Short name T55
Test name
Test status
Simulation time 1414490000 ps
CPU time 3.85 seconds
Started Aug 03 04:21:36 PM PDT 24
Finished Aug 03 04:21:45 PM PDT 24
Peak memory 164768 kb
Host smart-204c5867-fd1f-4c2c-86dd-3c9d90e0f609
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=860423877 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.860423877
Directory /workspace/35.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.798951118
Short name T45
Test name
Test status
Simulation time 1187390000 ps
CPU time 3.48 seconds
Started Aug 03 04:21:30 PM PDT 24
Finished Aug 03 04:21:38 PM PDT 24
Peak memory 164692 kb
Host smart-74f17986-d221-4da6-a262-137eb059754b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=798951118 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.798951118
Directory /workspace/36.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.2794117877
Short name T46
Test name
Test status
Simulation time 1485730000 ps
CPU time 4.29 seconds
Started Aug 03 04:21:38 PM PDT 24
Finished Aug 03 04:21:47 PM PDT 24
Peak memory 164664 kb
Host smart-aa526e92-a27e-4f16-b974-a1f1d5f26c59
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2794117877 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.2794117877
Directory /workspace/37.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.1010999268
Short name T34
Test name
Test status
Simulation time 1513410000 ps
CPU time 5.06 seconds
Started Aug 03 04:21:49 PM PDT 24
Finished Aug 03 04:22:00 PM PDT 24
Peak memory 164756 kb
Host smart-99f3256c-5ab6-4643-800b-43da561cfe0e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1010999268 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.1010999268
Directory /workspace/38.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.2101032746
Short name T53
Test name
Test status
Simulation time 1502130000 ps
CPU time 4.29 seconds
Started Aug 03 04:21:41 PM PDT 24
Finished Aug 03 04:21:51 PM PDT 24
Peak memory 164720 kb
Host smart-8080991e-dced-4243-81c4-cb310b46963e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2101032746 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.2101032746
Directory /workspace/39.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.409448712
Short name T59
Test name
Test status
Simulation time 1314750000 ps
CPU time 5.16 seconds
Started Aug 03 04:21:51 PM PDT 24
Finished Aug 03 04:22:02 PM PDT 24
Peak memory 164744 kb
Host smart-4cbb3260-f1a2-4680-9034-93626f143ed3
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=409448712 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.409448712
Directory /workspace/4.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.1057510235
Short name T65
Test name
Test status
Simulation time 1506550000 ps
CPU time 4.29 seconds
Started Aug 03 04:21:54 PM PDT 24
Finished Aug 03 04:22:04 PM PDT 24
Peak memory 164688 kb
Host smart-03546d1a-6294-4b75-b400-e58d9eab3045
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1057510235 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.1057510235
Directory /workspace/40.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.373886381
Short name T60
Test name
Test status
Simulation time 1439110000 ps
CPU time 5.11 seconds
Started Aug 03 04:19:28 PM PDT 24
Finished Aug 03 04:19:39 PM PDT 24
Peak memory 164748 kb
Host smart-23ff2413-2df1-44e7-b599-dd576f42b41e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=373886381 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.373886381
Directory /workspace/41.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.3665167260
Short name T1
Test name
Test status
Simulation time 1458130000 ps
CPU time 4.47 seconds
Started Aug 03 04:20:59 PM PDT 24
Finished Aug 03 04:21:09 PM PDT 24
Peak memory 164636 kb
Host smart-e51b8ff3-4fea-48e4-8e07-2052c25130ba
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3665167260 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.3665167260
Directory /workspace/42.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.2872556104
Short name T32
Test name
Test status
Simulation time 1433430000 ps
CPU time 3.31 seconds
Started Aug 03 04:22:42 PM PDT 24
Finished Aug 03 04:22:49 PM PDT 24
Peak memory 164740 kb
Host smart-a077b033-cee5-44b1-9f5c-d8b3b3472232
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2872556104 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.2872556104
Directory /workspace/43.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.554575938
Short name T39
Test name
Test status
Simulation time 1286370000 ps
CPU time 4.64 seconds
Started Aug 03 04:20:14 PM PDT 24
Finished Aug 03 04:20:24 PM PDT 24
Peak memory 164720 kb
Host smart-e51d84db-f7de-4a37-8eea-ce0d9ce72991
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=554575938 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.554575938
Directory /workspace/44.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.2745736570
Short name T56
Test name
Test status
Simulation time 1435210000 ps
CPU time 4.57 seconds
Started Aug 03 04:20:59 PM PDT 24
Finished Aug 03 04:21:09 PM PDT 24
Peak memory 164636 kb
Host smart-f0d7ae62-5cb9-4bc5-a0d1-cd87e2b48b09
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2745736570 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.2745736570
Directory /workspace/45.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.1443592505
Short name T69
Test name
Test status
Simulation time 1440850000 ps
CPU time 3.89 seconds
Started Aug 03 04:22:35 PM PDT 24
Finished Aug 03 04:22:44 PM PDT 24
Peak memory 164800 kb
Host smart-8eb17652-027d-45ac-b0ce-2e95da7dcb6b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1443592505 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.1443592505
Directory /workspace/46.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.2409016540
Short name T10
Test name
Test status
Simulation time 1177970000 ps
CPU time 3.47 seconds
Started Aug 03 04:19:48 PM PDT 24
Finished Aug 03 04:19:56 PM PDT 24
Peak memory 164800 kb
Host smart-ef2181ca-eab3-45eb-8334-6332a54e07df
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2409016540 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.2409016540
Directory /workspace/47.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.4144740577
Short name T54
Test name
Test status
Simulation time 1465950000 ps
CPU time 3.78 seconds
Started Aug 03 04:21:56 PM PDT 24
Finished Aug 03 04:22:04 PM PDT 24
Peak memory 164696 kb
Host smart-1324820e-dd7c-4769-b529-a3d0ce8a4a52
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4144740577 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.4144740577
Directory /workspace/48.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.965750161
Short name T43
Test name
Test status
Simulation time 1130410000 ps
CPU time 4.09 seconds
Started Aug 03 04:20:28 PM PDT 24
Finished Aug 03 04:20:38 PM PDT 24
Peak memory 164668 kb
Host smart-7080b4e8-42fc-4c44-8ad0-946ec5486d66
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=965750161 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.965750161
Directory /workspace/49.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.2473271419
Short name T38
Test name
Test status
Simulation time 1471530000 ps
CPU time 3.75 seconds
Started Aug 03 04:21:14 PM PDT 24
Finished Aug 03 04:21:23 PM PDT 24
Peak memory 164660 kb
Host smart-3764f004-af76-489f-9ed5-35e631ee15a4
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2473271419 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.2473271419
Directory /workspace/5.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.188818389
Short name T12
Test name
Test status
Simulation time 1509030000 ps
CPU time 3.91 seconds
Started Aug 03 04:21:15 PM PDT 24
Finished Aug 03 04:21:23 PM PDT 24
Peak memory 164752 kb
Host smart-a40e9b84-78cd-498d-ae5e-2616376e7673
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=188818389 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.188818389
Directory /workspace/6.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.4146831886
Short name T11
Test name
Test status
Simulation time 1401150000 ps
CPU time 4.24 seconds
Started Aug 03 04:21:41 PM PDT 24
Finished Aug 03 04:21:50 PM PDT 24
Peak memory 164492 kb
Host smart-b1d36c7d-261d-4b5e-adf5-8b519648cb0a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4146831886 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.4146831886
Directory /workspace/7.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.2853970087
Short name T50
Test name
Test status
Simulation time 1441470000 ps
CPU time 5.41 seconds
Started Aug 03 04:20:41 PM PDT 24
Finished Aug 03 04:20:53 PM PDT 24
Peak memory 164688 kb
Host smart-9146287e-e285-4304-8cee-1b06b2e3f585
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2853970087 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.2853970087
Directory /workspace/8.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.328547164
Short name T48
Test name
Test status
Simulation time 1559910000 ps
CPU time 6.2 seconds
Started Aug 03 04:19:20 PM PDT 24
Finished Aug 03 04:19:33 PM PDT 24
Peak memory 164704 kb
Host smart-dfa82c52-ac11-4280-baca-dce687c70d4e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=328547164 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.328547164
Directory /workspace/9.prim_lfsr_gal_smoke/latest
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