Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.31 100.00 96.55 100.00 100.00 95.00


Total tests in report: 200
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
87.31 87.31 100.00 100.00 96.55 96.55 100.00 100.00 100.00 100.00 40.00 40.00 /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.882493999
96.81 9.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 87.50 47.50 /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.2328852826
98.31 1.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 95.00 7.50 /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.2965198089

Tests that do not contribute to grading

Name
/workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.337354679
/workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.2573778452
/workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.3202709060
/workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.2462007957
/workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.2677604830
/workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.657794646
/workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.2373337632
/workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.1232074257
/workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.3725091617
/workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.3348707403
/workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.3605485687
/workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.575523199
/workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.702545463
/workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.2494560682
/workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.362404406
/workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.569190641
/workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.4187878887
/workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.960144069
/workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.820675258
/workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.2125776778
/workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.1022604236
/workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.4231421819
/workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.4150155352
/workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3820792996
/workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.2715372518
/workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.3677328240
/workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.219348621
/workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.1300203323
/workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.802554967
/workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.1599509009
/workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.3506151929
/workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.2978027615
/workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.1180188945
/workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.2311104800
/workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.2641812004
/workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.4249083106
/workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.3576247436
/workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.2823147916
/workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.67872954
/workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.682407030
/workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.1137187873
/workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.3289289750
/workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.582358618
/workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.2755682370
/workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.3553584019
/workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.1758431731
/workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.3796950817
/workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.3496549202
/workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.1683214306
/workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.4069240212
/workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.3766090546
/workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.906043142
/workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.2729549735
/workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.2180316419
/workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.2501621438
/workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.1572040075
/workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.3414965480
/workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.3771671894
/workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.337802819
/workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.1092080833
/workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.2856689769
/workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.4251462070
/workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.1680198265
/workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.3587941573
/workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.1302480505
/workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.3486437268
/workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.1578744011
/workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.3853295323
/workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.1257568601
/workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.2932446010
/workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.2478491529
/workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.1576651380
/workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.395591487
/workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.3624435218
/workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.12513641
/workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.1434475273
/workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.2778594834
/workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.2975997716
/workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.3983050037
/workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.581306729
/workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.1826763327
/workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.868619143
/workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.3525412089
/workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.1213883562
/workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.393456348
/workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.2487178114
/workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.2170463611
/workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.3574915877
/workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.2917910441
/workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.1776227745
/workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.2032084337
/workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.2500062362
/workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.2298395658
/workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.4159552056
/workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.2712812550
/workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.3479258739
/workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.1149883910
/workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.1801656594
/workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.4228247701
/workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.76109566
/workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.3202174611
/workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.1200932025
/workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.489216162
/workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.3702406047
/workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.937536032
/workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.537696011
/workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.3763471033
/workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.4228176889
/workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.4156791958
/workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.3094948575
/workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.1966262073
/workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.3604362085
/workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3009603180
/workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.3876511942
/workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.2703323222
/workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.3705452381
/workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.2331739646
/workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.4100615697
/workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.3209756790
/workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.1551785032
/workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.1686513477
/workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.3696935403
/workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.3373753746
/workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.391996332
/workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.2236358998
/workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.3351367213
/workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.2886983504
/workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.3914348778
/workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.4142770667
/workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.2894218731
/workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.2400204063
/workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.1248953354
/workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.1091263938
/workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.3488610911
/workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.704081145
/workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.2909922752
/workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.3994030412
/workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.2126389200
/workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.248056236
/workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.719688544
/workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.121738204
/workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.4131906910
/workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.3005379029
/workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.651106745
/workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.2061417016
/workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.4038587161
/workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1517052431
/workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.3705887622
/workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.596396892
/workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.3763184096
/workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.1501939757
/workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.1950881541
/workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.94087229
/workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.3489250885
/workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.178456203
/workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.130926205
/workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.899641826
/workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.2274835002
/workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.4174785348
/workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.1525641562
/workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.2803721868
/workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.2169366310
/workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.4258469627
/workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.117500850
/workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.78070213
/workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.1619186919
/workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.1857787345
/workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.2853347916
/workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.4186151445
/workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.1124856961
/workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.2189036056
/workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.791065256
/workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.2327216281
/workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.1777409658
/workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.1886797653
/workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.1420409377
/workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.100733270
/workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.2673666422
/workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.2253783977
/workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.3898318751
/workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.3126888729
/workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.961259538
/workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.1772952778
/workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.1175633075
/workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.3604363198
/workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.479186987
/workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.3683243832
/workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.208506756
/workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.655816841
/workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.4084475510
/workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.4128461139
/workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.3214631141
/workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.1204622667
/workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.3060998619
/workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.1401030756
/workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.2044663250
/workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.276568860



Total test records in report: 200
tests.html | tests1.html | tests2.html | tests3.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.3214631141 Aug 05 04:22:12 PM PDT 24 Aug 05 04:22:22 PM PDT 24 1342050000 ps
T2 /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.2673666422 Aug 05 04:23:44 PM PDT 24 Aug 05 04:23:57 PM PDT 24 1466270000 ps
T3 /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.100733270 Aug 05 04:22:14 PM PDT 24 Aug 05 04:22:23 PM PDT 24 1499510000 ps
T7 /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.882493999 Aug 05 04:23:47 PM PDT 24 Aug 05 04:24:00 PM PDT 24 1458170000 ps
T8 /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.1204622667 Aug 05 04:23:16 PM PDT 24 Aug 05 04:23:23 PM PDT 24 1088630000 ps
T9 /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.1772952778 Aug 05 04:22:14 PM PDT 24 Aug 05 04:22:24 PM PDT 24 1486130000 ps
T10 /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.208506756 Aug 05 04:22:19 PM PDT 24 Aug 05 04:22:29 PM PDT 24 1520890000 ps
T11 /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.3489250885 Aug 05 04:22:16 PM PDT 24 Aug 05 04:22:27 PM PDT 24 1608270000 ps
T12 /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.1175633075 Aug 05 04:22:13 PM PDT 24 Aug 05 04:22:25 PM PDT 24 1371030000 ps
T13 /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.3060998619 Aug 05 04:22:04 PM PDT 24 Aug 05 04:22:12 PM PDT 24 1566750000 ps
T31 /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.4128461139 Aug 05 04:23:14 PM PDT 24 Aug 05 04:23:24 PM PDT 24 1540670000 ps
T32 /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.1857787345 Aug 05 04:23:20 PM PDT 24 Aug 05 04:23:28 PM PDT 24 1327190000 ps
T33 /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.2803721868 Aug 05 04:23:14 PM PDT 24 Aug 05 04:23:23 PM PDT 24 1608190000 ps
T34 /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.3683243832 Aug 05 04:22:14 PM PDT 24 Aug 05 04:22:24 PM PDT 24 1453510000 ps
T35 /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.4258469627 Aug 05 04:23:43 PM PDT 24 Aug 05 04:24:00 PM PDT 24 1456870000 ps
T36 /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.3126888729 Aug 05 04:22:13 PM PDT 24 Aug 05 04:22:21 PM PDT 24 1219290000 ps
T37 /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.961259538 Aug 05 04:23:17 PM PDT 24 Aug 05 04:23:25 PM PDT 24 1356190000 ps
T38 /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.1777409658 Aug 05 04:23:47 PM PDT 24 Aug 05 04:24:01 PM PDT 24 1543970000 ps
T39 /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.1886797653 Aug 05 04:22:03 PM PDT 24 Aug 05 04:22:14 PM PDT 24 1497130000 ps
T40 /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.3763184096 Aug 05 04:22:13 PM PDT 24 Aug 05 04:22:23 PM PDT 24 1518850000 ps
T41 /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.655816841 Aug 05 04:22:13 PM PDT 24 Aug 05 04:22:22 PM PDT 24 1340190000 ps
T42 /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.596396892 Aug 05 04:22:13 PM PDT 24 Aug 05 04:22:23 PM PDT 24 1456250000 ps
T43 /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.4084475510 Aug 05 04:23:14 PM PDT 24 Aug 05 04:23:24 PM PDT 24 1444570000 ps
T44 /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.1420409377 Aug 05 04:22:16 PM PDT 24 Aug 05 04:22:24 PM PDT 24 1234630000 ps
T45 /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.1501939757 Aug 05 04:22:01 PM PDT 24 Aug 05 04:22:08 PM PDT 24 1563890000 ps
T46 /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.94087229 Aug 05 04:22:08 PM PDT 24 Aug 05 04:22:20 PM PDT 24 1529730000 ps
T47 /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.178456203 Aug 05 04:23:16 PM PDT 24 Aug 05 04:23:24 PM PDT 24 1317550000 ps
T48 /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.130926205 Aug 05 04:23:47 PM PDT 24 Aug 05 04:23:53 PM PDT 24 1440150000 ps
T49 /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.2327216281 Aug 05 04:23:20 PM PDT 24 Aug 05 04:23:29 PM PDT 24 1388170000 ps
T50 /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.4174785348 Aug 05 04:23:17 PM PDT 24 Aug 05 04:23:24 PM PDT 24 1339610000 ps
T51 /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.1401030756 Aug 05 04:22:16 PM PDT 24 Aug 05 04:22:26 PM PDT 24 1483210000 ps
T52 /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.2853347916 Aug 05 04:23:16 PM PDT 24 Aug 05 04:23:26 PM PDT 24 1490450000 ps
T53 /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.2044663250 Aug 05 04:22:13 PM PDT 24 Aug 05 04:22:24 PM PDT 24 1568870000 ps
T54 /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.1124856961 Aug 05 04:22:04 PM PDT 24 Aug 05 04:22:12 PM PDT 24 1541490000 ps
T55 /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.1950881541 Aug 05 04:22:06 PM PDT 24 Aug 05 04:22:15 PM PDT 24 1526830000 ps
T56 /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.3604363198 Aug 05 04:22:12 PM PDT 24 Aug 05 04:22:22 PM PDT 24 1619170000 ps
T57 /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.276568860 Aug 05 04:23:31 PM PDT 24 Aug 05 04:23:36 PM PDT 24 1144050000 ps
T58 /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.1525641562 Aug 05 04:22:16 PM PDT 24 Aug 05 04:22:26 PM PDT 24 1514150000 ps
T59 /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.4186151445 Aug 05 04:22:04 PM PDT 24 Aug 05 04:22:12 PM PDT 24 1394890000 ps
T60 /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.1619186919 Aug 05 04:23:38 PM PDT 24 Aug 05 04:23:47 PM PDT 24 1545970000 ps
T61 /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.117500850 Aug 05 04:23:42 PM PDT 24 Aug 05 04:23:53 PM PDT 24 1123170000 ps
T62 /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.2253783977 Aug 05 04:22:09 PM PDT 24 Aug 05 04:22:15 PM PDT 24 1541510000 ps
T63 /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.3898318751 Aug 05 04:22:15 PM PDT 24 Aug 05 04:22:23 PM PDT 24 1432950000 ps
T64 /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.2274835002 Aug 05 04:22:02 PM PDT 24 Aug 05 04:22:10 PM PDT 24 1597230000 ps
T65 /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.78070213 Aug 05 04:23:36 PM PDT 24 Aug 05 04:23:45 PM PDT 24 1563490000 ps
T66 /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.2169366310 Aug 05 04:22:13 PM PDT 24 Aug 05 04:22:23 PM PDT 24 1433810000 ps
T67 /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.2189036056 Aug 05 04:22:13 PM PDT 24 Aug 05 04:22:22 PM PDT 24 1369350000 ps
T68 /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.791065256 Aug 05 04:22:03 PM PDT 24 Aug 05 04:22:10 PM PDT 24 1489690000 ps
T69 /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.479186987 Aug 05 04:22:15 PM PDT 24 Aug 05 04:22:24 PM PDT 24 1475210000 ps
T70 /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.899641826 Aug 05 04:23:43 PM PDT 24 Aug 05 04:23:57 PM PDT 24 1519150000 ps
T4 /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.960144069 Aug 05 04:21:55 PM PDT 24 Aug 05 05:00:14 PM PDT 24 336941410000 ps
T5 /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.2328852826 Aug 05 04:22:42 PM PDT 24 Aug 05 04:48:16 PM PDT 24 336647670000 ps
T6 /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.702545463 Aug 05 04:22:03 PM PDT 24 Aug 05 04:56:25 PM PDT 24 336487290000 ps
T14 /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.2373337632 Aug 05 04:21:54 PM PDT 24 Aug 05 04:59:12 PM PDT 24 336886290000 ps
T15 /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.657794646 Aug 05 04:22:14 PM PDT 24 Aug 05 04:56:28 PM PDT 24 336460550000 ps
T16 /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.582358618 Aug 05 04:23:15 PM PDT 24 Aug 05 04:50:57 PM PDT 24 337010010000 ps
T17 /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.219348621 Aug 05 04:22:01 PM PDT 24 Aug 05 04:48:43 PM PDT 24 336515790000 ps
T18 /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.569190641 Aug 05 04:21:54 PM PDT 24 Aug 05 05:00:03 PM PDT 24 336628370000 ps
T19 /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.1758431731 Aug 05 04:22:16 PM PDT 24 Aug 05 04:45:52 PM PDT 24 336796730000 ps
T20 /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.682407030 Aug 05 04:21:58 PM PDT 24 Aug 05 04:59:33 PM PDT 24 336546410000 ps
T71 /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.2125776778 Aug 05 04:21:57 PM PDT 24 Aug 05 04:58:24 PM PDT 24 336645270000 ps
T72 /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3820792996 Aug 05 04:21:58 PM PDT 24 Aug 05 04:56:39 PM PDT 24 336526470000 ps
T73 /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.2677604830 Aug 05 04:21:54 PM PDT 24 Aug 05 04:50:37 PM PDT 24 336727730000 ps
T74 /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.802554967 Aug 05 04:22:14 PM PDT 24 Aug 05 04:56:42 PM PDT 24 336961270000 ps
T75 /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.2823147916 Aug 05 04:22:08 PM PDT 24 Aug 05 04:54:08 PM PDT 24 336945970000 ps
T76 /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.1232074257 Aug 05 04:22:13 PM PDT 24 Aug 05 04:51:59 PM PDT 24 336803650000 ps
T77 /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.337354679 Aug 05 04:22:54 PM PDT 24 Aug 05 04:51:40 PM PDT 24 336374770000 ps
T78 /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.1300203323 Aug 05 04:21:58 PM PDT 24 Aug 05 04:59:47 PM PDT 24 336434530000 ps
T79 /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.3348707403 Aug 05 04:21:54 PM PDT 24 Aug 05 05:00:07 PM PDT 24 336983850000 ps
T80 /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.2978027615 Aug 05 04:23:19 PM PDT 24 Aug 05 04:50:41 PM PDT 24 337065590000 ps
T81 /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.820675258 Aug 05 04:21:57 PM PDT 24 Aug 05 04:52:04 PM PDT 24 337047490000 ps
T82 /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.67872954 Aug 05 04:22:03 PM PDT 24 Aug 05 04:56:00 PM PDT 24 336817610000 ps
T83 /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.3506151929 Aug 05 04:22:13 PM PDT 24 Aug 05 04:52:20 PM PDT 24 336414910000 ps
T84 /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.2573778452 Aug 05 04:21:49 PM PDT 24 Aug 05 04:59:05 PM PDT 24 337073490000 ps
T85 /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.2494560682 Aug 05 04:21:55 PM PDT 24 Aug 05 05:00:17 PM PDT 24 337032350000 ps
T86 /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.4187878887 Aug 05 04:21:56 PM PDT 24 Aug 05 04:59:42 PM PDT 24 336529010000 ps
T87 /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.3605485687 Aug 05 04:21:56 PM PDT 24 Aug 05 04:59:46 PM PDT 24 336699330000 ps
T88 /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.3202709060 Aug 05 04:22:14 PM PDT 24 Aug 05 04:56:31 PM PDT 24 336470690000 ps
T89 /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.3496549202 Aug 05 04:21:48 PM PDT 24 Aug 05 04:59:16 PM PDT 24 336766790000 ps
T90 /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.3725091617 Aug 05 04:22:14 PM PDT 24 Aug 05 04:57:12 PM PDT 24 337104670000 ps
T91 /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.3796950817 Aug 05 04:21:45 PM PDT 24 Aug 05 04:51:52 PM PDT 24 336467970000 ps
T92 /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.4249083106 Aug 05 04:22:08 PM PDT 24 Aug 05 04:53:48 PM PDT 24 336473910000 ps
T93 /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.2462007957 Aug 05 04:21:54 PM PDT 24 Aug 05 04:59:14 PM PDT 24 337009070000 ps
T94 /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.2755682370 Aug 05 04:22:03 PM PDT 24 Aug 05 04:56:18 PM PDT 24 336382730000 ps
T95 /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.3576247436 Aug 05 04:21:58 PM PDT 24 Aug 05 04:59:55 PM PDT 24 336674370000 ps
T96 /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.1599509009 Aug 05 04:21:55 PM PDT 24 Aug 05 04:49:34 PM PDT 24 336295830000 ps
T97 /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.4231421819 Aug 05 04:22:09 PM PDT 24 Aug 05 04:59:49 PM PDT 24 336921530000 ps
T98 /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.2311104800 Aug 05 04:21:48 PM PDT 24 Aug 05 04:58:02 PM PDT 24 336919030000 ps
T99 /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.1022604236 Aug 05 04:23:15 PM PDT 24 Aug 05 04:51:12 PM PDT 24 336738590000 ps
T100 /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.2641812004 Aug 05 04:23:21 PM PDT 24 Aug 05 04:51:16 PM PDT 24 336660270000 ps
T101 /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.575523199 Aug 05 04:21:49 PM PDT 24 Aug 05 04:50:30 PM PDT 24 336678790000 ps
T102 /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.1180188945 Aug 05 04:22:03 PM PDT 24 Aug 05 04:47:48 PM PDT 24 336547430000 ps
T103 /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.1683214306 Aug 05 04:21:49 PM PDT 24 Aug 05 04:59:10 PM PDT 24 336357710000 ps
T104 /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.362404406 Aug 05 04:22:14 PM PDT 24 Aug 05 04:56:36 PM PDT 24 336783910000 ps
T105 /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.4150155352 Aug 05 04:21:44 PM PDT 24 Aug 05 04:58:04 PM PDT 24 336874530000 ps
T106 /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.3289289750 Aug 05 04:22:07 PM PDT 24 Aug 05 04:54:43 PM PDT 24 336698070000 ps
T107 /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.3677328240 Aug 05 04:23:26 PM PDT 24 Aug 05 04:50:53 PM PDT 24 336900950000 ps
T108 /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.1137187873 Aug 05 04:21:58 PM PDT 24 Aug 05 04:59:55 PM PDT 24 336815770000 ps
T109 /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.2715372518 Aug 05 04:22:06 PM PDT 24 Aug 05 04:52:25 PM PDT 24 336740690000 ps
T110 /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.3553584019 Aug 05 04:21:55 PM PDT 24 Aug 05 04:59:11 PM PDT 24 336440610000 ps
T111 /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.704081145 Aug 05 04:22:24 PM PDT 24 Aug 05 04:22:33 PM PDT 24 1445030000 ps
T112 /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.3005379029 Aug 05 04:22:47 PM PDT 24 Aug 05 04:22:56 PM PDT 24 1596490000 ps
T113 /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.2126389200 Aug 05 04:22:43 PM PDT 24 Aug 05 04:22:52 PM PDT 24 1524230000 ps
T114 /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.1966262073 Aug 05 04:22:19 PM PDT 24 Aug 05 04:22:27 PM PDT 24 1392170000 ps
T115 /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.4228176889 Aug 05 04:22:25 PM PDT 24 Aug 05 04:22:34 PM PDT 24 1575510000 ps
T116 /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.3209756790 Aug 05 04:22:28 PM PDT 24 Aug 05 04:22:37 PM PDT 24 1522870000 ps
T117 /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.3705452381 Aug 05 04:22:27 PM PDT 24 Aug 05 04:22:39 PM PDT 24 1614950000 ps
T118 /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.2331739646 Aug 05 04:22:25 PM PDT 24 Aug 05 04:22:34 PM PDT 24 1387690000 ps
T119 /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.3763471033 Aug 05 04:22:20 PM PDT 24 Aug 05 04:22:30 PM PDT 24 1564810000 ps
T120 /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.3604362085 Aug 05 04:22:30 PM PDT 24 Aug 05 04:22:40 PM PDT 24 1355510000 ps
T121 /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.121738204 Aug 05 04:22:31 PM PDT 24 Aug 05 04:22:40 PM PDT 24 1519410000 ps
T122 /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.1091263938 Aug 05 04:22:11 PM PDT 24 Aug 05 04:22:23 PM PDT 24 1581610000 ps
T123 /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.1686513477 Aug 05 04:22:27 PM PDT 24 Aug 05 04:22:39 PM PDT 24 1567990000 ps
T124 /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.1248953354 Aug 05 04:22:28 PM PDT 24 Aug 05 04:22:37 PM PDT 24 1602570000 ps
T125 /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.3373753746 Aug 05 04:22:30 PM PDT 24 Aug 05 04:22:39 PM PDT 24 1532710000 ps
T126 /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.2400204063 Aug 05 04:22:35 PM PDT 24 Aug 05 04:22:47 PM PDT 24 1511210000 ps
T127 /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.391996332 Aug 05 04:22:29 PM PDT 24 Aug 05 04:22:40 PM PDT 24 1420530000 ps
T128 /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.719688544 Aug 05 04:22:41 PM PDT 24 Aug 05 04:22:51 PM PDT 24 1553630000 ps
T129 /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.3876511942 Aug 05 04:22:31 PM PDT 24 Aug 05 04:22:40 PM PDT 24 1436250000 ps
T130 /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.651106745 Aug 05 04:22:19 PM PDT 24 Aug 05 04:22:26 PM PDT 24 1343030000 ps
T131 /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.1200932025 Aug 05 04:22:10 PM PDT 24 Aug 05 04:22:20 PM PDT 24 1507610000 ps
T132 /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.3488610911 Aug 05 04:22:36 PM PDT 24 Aug 05 04:22:49 PM PDT 24 1590150000 ps
T133 /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.3696935403 Aug 05 04:22:23 PM PDT 24 Aug 05 04:22:31 PM PDT 24 1413770000 ps
T134 /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.3351367213 Aug 05 04:22:40 PM PDT 24 Aug 05 04:22:50 PM PDT 24 1543890000 ps
T135 /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.2061417016 Aug 05 04:22:14 PM PDT 24 Aug 05 04:22:26 PM PDT 24 1530430000 ps
T136 /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.2909922752 Aug 05 04:22:29 PM PDT 24 Aug 05 04:22:38 PM PDT 24 1454830000 ps
T137 /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.4038587161 Aug 05 04:22:15 PM PDT 24 Aug 05 04:22:25 PM PDT 24 1491870000 ps
T138 /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.4142770667 Aug 05 04:22:30 PM PDT 24 Aug 05 04:22:37 PM PDT 24 1478950000 ps
T139 /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.3094948575 Aug 05 04:22:34 PM PDT 24 Aug 05 04:22:47 PM PDT 24 1568610000 ps
T140 /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.3202174611 Aug 05 04:22:15 PM PDT 24 Aug 05 04:22:26 PM PDT 24 1429770000 ps
T141 /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.248056236 Aug 05 04:22:33 PM PDT 24 Aug 05 04:22:43 PM PDT 24 1358910000 ps
T142 /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.2894218731 Aug 05 04:22:34 PM PDT 24 Aug 05 04:22:44 PM PDT 24 1294650000 ps
T143 /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.4228247701 Aug 05 04:22:23 PM PDT 24 Aug 05 04:22:32 PM PDT 24 1546890000 ps
T144 /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.489216162 Aug 05 04:22:11 PM PDT 24 Aug 05 04:22:20 PM PDT 24 1313490000 ps
T145 /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.537696011 Aug 05 04:22:15 PM PDT 24 Aug 05 04:22:25 PM PDT 24 1399910000 ps
T146 /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1517052431 Aug 05 04:23:14 PM PDT 24 Aug 05 04:23:24 PM PDT 24 1502670000 ps
T147 /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.76109566 Aug 05 04:22:13 PM PDT 24 Aug 05 04:22:21 PM PDT 24 1253970000 ps
T148 /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.2886983504 Aug 05 04:22:40 PM PDT 24 Aug 05 04:22:48 PM PDT 24 1409190000 ps
T149 /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.2703323222 Aug 05 04:22:24 PM PDT 24 Aug 05 04:22:34 PM PDT 24 1564570000 ps
T150 /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.4100615697 Aug 05 04:22:42 PM PDT 24 Aug 05 04:22:51 PM PDT 24 1509730000 ps
T151 /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.2236358998 Aug 05 04:22:21 PM PDT 24 Aug 05 04:22:31 PM PDT 24 1417090000 ps
T152 /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.1551785032 Aug 05 04:23:34 PM PDT 24 Aug 05 04:23:41 PM PDT 24 1296910000 ps
T153 /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.4131906910 Aug 05 04:22:25 PM PDT 24 Aug 05 04:22:35 PM PDT 24 1527090000 ps
T154 /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.937536032 Aug 05 04:22:14 PM PDT 24 Aug 05 04:22:23 PM PDT 24 1354250000 ps
T155 /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.4156791958 Aug 05 04:22:32 PM PDT 24 Aug 05 04:22:44 PM PDT 24 1589630000 ps
T156 /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.3994030412 Aug 05 04:22:25 PM PDT 24 Aug 05 04:22:36 PM PDT 24 1374450000 ps
T157 /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3009603180 Aug 05 04:22:24 PM PDT 24 Aug 05 04:22:32 PM PDT 24 1178510000 ps
T158 /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.3914348778 Aug 05 04:22:24 PM PDT 24 Aug 05 04:22:34 PM PDT 24 1493330000 ps
T159 /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.3702406047 Aug 05 04:23:14 PM PDT 24 Aug 05 04:23:22 PM PDT 24 1153450000 ps
T160 /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.3705887622 Aug 05 04:22:13 PM PDT 24 Aug 05 04:22:22 PM PDT 24 1448470000 ps
T21 /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.337802819 Aug 05 04:16:54 PM PDT 24 Aug 05 04:54:27 PM PDT 24 336960950000 ps
T22 /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.1257568601 Aug 05 04:18:03 PM PDT 24 Aug 05 04:55:19 PM PDT 24 336873650000 ps
T23 /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.2917910441 Aug 05 04:21:37 PM PDT 24 Aug 05 04:50:47 PM PDT 24 336690230000 ps
T24 /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.3983050037 Aug 05 04:17:46 PM PDT 24 Aug 05 04:49:39 PM PDT 24 336683910000 ps
T25 /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.2478491529 Aug 05 04:18:09 PM PDT 24 Aug 05 04:54:24 PM PDT 24 336580490000 ps
T26 /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.2729549735 Aug 05 04:22:20 PM PDT 24 Aug 05 04:51:18 PM PDT 24 336643570000 ps
T27 /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.2975997716 Aug 05 04:18:28 PM PDT 24 Aug 05 04:55:41 PM PDT 24 336820350000 ps
T28 /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.1302480505 Aug 05 04:16:55 PM PDT 24 Aug 05 04:52:18 PM PDT 24 336836970000 ps
T29 /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.2965198089 Aug 05 04:21:41 PM PDT 24 Aug 05 04:54:05 PM PDT 24 336395210000 ps
T30 /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.2856689769 Aug 05 04:19:33 PM PDT 24 Aug 05 04:48:34 PM PDT 24 336869670000 ps
T161 /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.3486437268 Aug 05 04:16:54 PM PDT 24 Aug 05 04:54:35 PM PDT 24 336333270000 ps
T162 /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.1213883562 Aug 05 04:22:34 PM PDT 24 Aug 05 04:57:41 PM PDT 24 336821650000 ps
T163 /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.2712812550 Aug 05 04:22:55 PM PDT 24 Aug 05 04:53:29 PM PDT 24 336351190000 ps
T164 /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.2500062362 Aug 05 04:23:02 PM PDT 24 Aug 05 04:58:00 PM PDT 24 336798790000 ps
T165 /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.581306729 Aug 05 04:21:58 PM PDT 24 Aug 05 04:52:15 PM PDT 24 336461030000 ps
T166 /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.4251462070 Aug 05 04:18:23 PM PDT 24 Aug 05 04:52:51 PM PDT 24 336775390000 ps
T167 /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.3766090546 Aug 05 04:22:07 PM PDT 24 Aug 05 04:48:28 PM PDT 24 336593930000 ps
T168 /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.1578744011 Aug 05 04:21:40 PM PDT 24 Aug 05 04:54:02 PM PDT 24 336699310000 ps
T169 /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.3525412089 Aug 05 04:18:45 PM PDT 24 Aug 05 04:47:16 PM PDT 24 337033710000 ps
T170 /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.3574915877 Aug 05 04:21:37 PM PDT 24 Aug 05 04:50:37 PM PDT 24 336991510000 ps
T171 /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.2032084337 Aug 05 04:23:05 PM PDT 24 Aug 05 04:59:16 PM PDT 24 336696550000 ps
T172 /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.2180316419 Aug 05 04:22:20 PM PDT 24 Aug 05 04:51:09 PM PDT 24 336490710000 ps
T173 /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.395591487 Aug 05 04:18:01 PM PDT 24 Aug 05 04:46:03 PM PDT 24 336630390000 ps
T174 /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.2932446010 Aug 05 04:18:08 PM PDT 24 Aug 05 04:53:35 PM PDT 24 336790050000 ps
T175 /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.1092080833 Aug 05 04:21:53 PM PDT 24 Aug 05 04:55:48 PM PDT 24 336864390000 ps
T176 /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.12513641 Aug 05 04:18:21 PM PDT 24 Aug 05 04:56:16 PM PDT 24 336517830000 ps
T177 /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.1434475273 Aug 05 04:19:07 PM PDT 24 Aug 05 04:57:12 PM PDT 24 336862130000 ps
T178 /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.1680198265 Aug 05 04:18:24 PM PDT 24 Aug 05 04:54:39 PM PDT 24 337141950000 ps
T179 /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.3771671894 Aug 05 04:16:54 PM PDT 24 Aug 05 04:54:30 PM PDT 24 336973850000 ps
T180 /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.1576651380 Aug 05 04:21:40 PM PDT 24 Aug 05 04:53:56 PM PDT 24 336807990000 ps
T181 /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.1826763327 Aug 05 04:21:42 PM PDT 24 Aug 05 04:49:38 PM PDT 24 336814930000 ps
T182 /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.906043142 Aug 05 04:22:24 PM PDT 24 Aug 05 04:44:41 PM PDT 24 336876490000 ps
T183 /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.2487178114 Aug 05 04:17:24 PM PDT 24 Aug 05 04:46:42 PM PDT 24 336940230000 ps
T184 /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.2501621438 Aug 05 04:17:45 PM PDT 24 Aug 05 04:54:35 PM PDT 24 336790350000 ps
T185 /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.3414965480 Aug 05 04:16:55 PM PDT 24 Aug 05 04:52:09 PM PDT 24 336542330000 ps
T186 /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.868619143 Aug 05 04:21:56 PM PDT 24 Aug 05 04:51:04 PM PDT 24 336716230000 ps
T187 /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.3587941573 Aug 05 04:16:56 PM PDT 24 Aug 05 04:53:20 PM PDT 24 336810210000 ps
T188 /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.3624435218 Aug 05 04:20:25 PM PDT 24 Aug 05 04:54:45 PM PDT 24 336517970000 ps
T189 /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.1572040075 Aug 05 04:20:04 PM PDT 24 Aug 05 04:58:20 PM PDT 24 336648970000 ps
T190 /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.2170463611 Aug 05 04:21:22 PM PDT 24 Aug 05 04:47:25 PM PDT 24 336896450000 ps
T191 /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.3853295323 Aug 05 04:21:56 PM PDT 24 Aug 05 04:47:39 PM PDT 24 336602770000 ps
T192 /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.2778594834 Aug 05 04:18:30 PM PDT 24 Aug 05 04:50:38 PM PDT 24 337103210000 ps
T193 /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.4069240212 Aug 05 04:18:27 PM PDT 24 Aug 05 04:56:34 PM PDT 24 337136610000 ps
T194 /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.1801656594 Aug 05 04:19:20 PM PDT 24 Aug 05 04:56:42 PM PDT 24 336577770000 ps
T195 /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.3479258739 Aug 05 04:22:54 PM PDT 24 Aug 05 04:52:39 PM PDT 24 336404750000 ps
T196 /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.4159552056 Aug 05 04:22:55 PM PDT 24 Aug 05 04:53:17 PM PDT 24 336937410000 ps
T197 /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.1149883910 Aug 05 04:20:32 PM PDT 24 Aug 05 04:58:49 PM PDT 24 336280810000 ps
T198 /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.1776227745 Aug 05 04:17:46 PM PDT 24 Aug 05 04:49:39 PM PDT 24 336458830000 ps
T199 /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.2298395658 Aug 05 04:22:51 PM PDT 24 Aug 05 04:49:32 PM PDT 24 337123150000 ps
T200 /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.393456348 Aug 05 04:23:00 PM PDT 24 Aug 05 04:59:19 PM PDT 24 336862350000 ps

Test location /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.882493999
Short name T7
Test name
Test status
Simulation time 1458170000 ps
CPU time 7.02 seconds
Started Aug 05 04:23:47 PM PDT 24
Finished Aug 05 04:24:00 PM PDT 24
Peak memory 164440 kb
Host smart-4b03d2f8-7356-4f72-b181-2a3bf6375d3a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=882493999 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.882493999
Directory /workspace/21.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.2328852826
Short name T5
Test name
Test status
Simulation time 336647670000 ps
CPU time 627.47 seconds
Started Aug 05 04:22:42 PM PDT 24
Finished Aug 05 04:48:16 PM PDT 24
Peak memory 159748 kb
Host smart-b6112a84-0aeb-4df5-8269-17e313cdc352
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2328852826 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.2328852826
Directory /workspace/1.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.2965198089
Short name T29
Test name
Test status
Simulation time 336395210000 ps
CPU time 776.56 seconds
Started Aug 05 04:21:41 PM PDT 24
Finished Aug 05 04:54:05 PM PDT 24
Peak memory 160352 kb
Host smart-d569624b-8296-4aaf-b20a-25570469cdd8
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2965198089 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.2965198089
Directory /workspace/1.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.337354679
Short name T77
Test name
Test status
Simulation time 336374770000 ps
CPU time 705.52 seconds
Started Aug 05 04:22:54 PM PDT 24
Finished Aug 05 04:51:40 PM PDT 24
Peak memory 160396 kb
Host smart-7c0b7dd3-d8fe-4956-ab26-583db771d964
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=337354679 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.337354679
Directory /workspace/0.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.2573778452
Short name T84
Test name
Test status
Simulation time 337073490000 ps
CPU time 921.03 seconds
Started Aug 05 04:21:49 PM PDT 24
Finished Aug 05 04:59:05 PM PDT 24
Peak memory 160652 kb
Host smart-7e3a75ad-5efc-461e-a72c-e8d8c2c529a6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2573778452 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.2573778452
Directory /workspace/10.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.3202709060
Short name T88
Test name
Test status
Simulation time 336470690000 ps
CPU time 822.65 seconds
Started Aug 05 04:22:14 PM PDT 24
Finished Aug 05 04:56:31 PM PDT 24
Peak memory 160620 kb
Host smart-df9d0557-f7ff-446e-90da-9de5ee6e83cf
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3202709060 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.3202709060
Directory /workspace/11.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.2462007957
Short name T93
Test name
Test status
Simulation time 337009070000 ps
CPU time 923.65 seconds
Started Aug 05 04:21:54 PM PDT 24
Finished Aug 05 04:59:14 PM PDT 24
Peak memory 160632 kb
Host smart-f47bc1a9-12ec-415b-9158-dd0bbecb11e3
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2462007957 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.2462007957
Directory /workspace/12.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.2677604830
Short name T73
Test name
Test status
Simulation time 336727730000 ps
CPU time 701.28 seconds
Started Aug 05 04:21:54 PM PDT 24
Finished Aug 05 04:50:37 PM PDT 24
Peak memory 160880 kb
Host smart-601572ae-16a8-41d5-a5f2-4cb95ca1457e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2677604830 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.2677604830
Directory /workspace/13.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.657794646
Short name T15
Test name
Test status
Simulation time 336460550000 ps
CPU time 827.25 seconds
Started Aug 05 04:22:14 PM PDT 24
Finished Aug 05 04:56:28 PM PDT 24
Peak memory 160596 kb
Host smart-335a4422-6a51-42c2-a63e-2ff7d8351eab
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=657794646 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.657794646
Directory /workspace/14.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.2373337632
Short name T14
Test name
Test status
Simulation time 336886290000 ps
CPU time 912.72 seconds
Started Aug 05 04:21:54 PM PDT 24
Finished Aug 05 04:59:12 PM PDT 24
Peak memory 160628 kb
Host smart-1c70853e-4c77-459f-88e7-10f3875fa87a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2373337632 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.2373337632
Directory /workspace/15.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.1232074257
Short name T76
Test name
Test status
Simulation time 336803650000 ps
CPU time 729.01 seconds
Started Aug 05 04:22:13 PM PDT 24
Finished Aug 05 04:51:59 PM PDT 24
Peak memory 160588 kb
Host smart-3e7f54cd-44ab-4876-b194-0d7c5abacee6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1232074257 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.1232074257
Directory /workspace/16.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.3725091617
Short name T90
Test name
Test status
Simulation time 337104670000 ps
CPU time 844.08 seconds
Started Aug 05 04:22:14 PM PDT 24
Finished Aug 05 04:57:12 PM PDT 24
Peak memory 160620 kb
Host smart-659780e3-fd8e-4ce5-94f2-701be1de07bf
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3725091617 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.3725091617
Directory /workspace/17.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.3348707403
Short name T79
Test name
Test status
Simulation time 336983850000 ps
CPU time 938.27 seconds
Started Aug 05 04:21:54 PM PDT 24
Finished Aug 05 05:00:07 PM PDT 24
Peak memory 160656 kb
Host smart-90b99420-cde1-4182-927b-657010391fcc
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3348707403 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.3348707403
Directory /workspace/18.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.3605485687
Short name T87
Test name
Test status
Simulation time 336699330000 ps
CPU time 928.11 seconds
Started Aug 05 04:21:56 PM PDT 24
Finished Aug 05 04:59:46 PM PDT 24
Peak memory 160628 kb
Host smart-b282a3d9-fdab-4b3e-8ded-9a074fccda16
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3605485687 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.3605485687
Directory /workspace/19.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.575523199
Short name T101
Test name
Test status
Simulation time 336678790000 ps
CPU time 703 seconds
Started Aug 05 04:21:49 PM PDT 24
Finished Aug 05 04:50:30 PM PDT 24
Peak memory 160856 kb
Host smart-e75e668f-67de-4993-b6ee-f7b144268f21
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=575523199 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.575523199
Directory /workspace/2.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.702545463
Short name T6
Test name
Test status
Simulation time 336487290000 ps
CPU time 844.97 seconds
Started Aug 05 04:22:03 PM PDT 24
Finished Aug 05 04:56:25 PM PDT 24
Peak memory 159052 kb
Host smart-97cd7fc2-aabf-4dee-9531-17d2ac098339
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=702545463 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.702545463
Directory /workspace/20.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.2494560682
Short name T85
Test name
Test status
Simulation time 337032350000 ps
CPU time 938.26 seconds
Started Aug 05 04:21:55 PM PDT 24
Finished Aug 05 05:00:17 PM PDT 24
Peak memory 160652 kb
Host smart-60a44f68-b6b0-4a9e-bea0-e5b0a3df34b3
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2494560682 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.2494560682
Directory /workspace/21.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.362404406
Short name T104
Test name
Test status
Simulation time 336783910000 ps
CPU time 823.88 seconds
Started Aug 05 04:22:14 PM PDT 24
Finished Aug 05 04:56:36 PM PDT 24
Peak memory 160288 kb
Host smart-02435218-9fe9-4218-bbb7-286232a10530
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=362404406 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.362404406
Directory /workspace/22.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.569190641
Short name T18
Test name
Test status
Simulation time 336628370000 ps
CPU time 935 seconds
Started Aug 05 04:21:54 PM PDT 24
Finished Aug 05 05:00:03 PM PDT 24
Peak memory 160636 kb
Host smart-a8290b63-6866-41c8-8341-3d5102f72511
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=569190641 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.569190641
Directory /workspace/23.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.4187878887
Short name T86
Test name
Test status
Simulation time 336529010000 ps
CPU time 924.72 seconds
Started Aug 05 04:21:56 PM PDT 24
Finished Aug 05 04:59:42 PM PDT 24
Peak memory 160628 kb
Host smart-6d0d2838-1290-4625-8594-9a06b885927a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4187878887 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.4187878887
Directory /workspace/24.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.960144069
Short name T4
Test name
Test status
Simulation time 336941410000 ps
CPU time 931.43 seconds
Started Aug 05 04:21:55 PM PDT 24
Finished Aug 05 05:00:14 PM PDT 24
Peak memory 160640 kb
Host smart-c5d4ad50-818e-4163-8d88-719e9c712718
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=960144069 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.960144069
Directory /workspace/25.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.820675258
Short name T81
Test name
Test status
Simulation time 337047490000 ps
CPU time 732.89 seconds
Started Aug 05 04:21:57 PM PDT 24
Finished Aug 05 04:52:04 PM PDT 24
Peak memory 160624 kb
Host smart-e2a15b50-d607-462b-8394-40d8b18cbb34
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=820675258 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.820675258
Directory /workspace/26.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.2125776778
Short name T71
Test name
Test status
Simulation time 336645270000 ps
CPU time 890.71 seconds
Started Aug 05 04:21:57 PM PDT 24
Finished Aug 05 04:58:24 PM PDT 24
Peak memory 160632 kb
Host smart-aca88e26-7a9d-4420-9da5-9289de1d6748
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2125776778 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.2125776778
Directory /workspace/27.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.1022604236
Short name T99
Test name
Test status
Simulation time 336738590000 ps
CPU time 668.34 seconds
Started Aug 05 04:23:15 PM PDT 24
Finished Aug 05 04:51:12 PM PDT 24
Peak memory 160256 kb
Host smart-f1279852-2173-4fab-af62-919a2c96872f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1022604236 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.1022604236
Directory /workspace/28.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.4231421819
Short name T97
Test name
Test status
Simulation time 336921530000 ps
CPU time 914.39 seconds
Started Aug 05 04:22:09 PM PDT 24
Finished Aug 05 04:59:49 PM PDT 24
Peak memory 160628 kb
Host smart-53a5d66b-d4ca-4b63-bd7e-d3cb6620c59d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4231421819 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.4231421819
Directory /workspace/29.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.4150155352
Short name T105
Test name
Test status
Simulation time 336874530000 ps
CPU time 879.46 seconds
Started Aug 05 04:21:44 PM PDT 24
Finished Aug 05 04:58:04 PM PDT 24
Peak memory 160632 kb
Host smart-17fe3a29-a9bc-4ccf-9f06-da72d8e088a0
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4150155352 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.4150155352
Directory /workspace/3.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3820792996
Short name T72
Test name
Test status
Simulation time 336526470000 ps
CPU time 849.24 seconds
Started Aug 05 04:21:58 PM PDT 24
Finished Aug 05 04:56:39 PM PDT 24
Peak memory 160628 kb
Host smart-d4dcc688-7ccd-4eb2-9756-972f30e4986c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3820792996 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.3820792996
Directory /workspace/30.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.2715372518
Short name T109
Test name
Test status
Simulation time 336740690000 ps
CPU time 739.8 seconds
Started Aug 05 04:22:06 PM PDT 24
Finished Aug 05 04:52:25 PM PDT 24
Peak memory 160624 kb
Host smart-76f87409-b0e8-401d-b853-ba9d54e230ff
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2715372518 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.2715372518
Directory /workspace/31.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.3677328240
Short name T107
Test name
Test status
Simulation time 336900950000 ps
CPU time 653.73 seconds
Started Aug 05 04:23:26 PM PDT 24
Finished Aug 05 04:50:53 PM PDT 24
Peak memory 160468 kb
Host smart-4edc5a12-7634-4b4c-a205-683825cfd086
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3677328240 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.3677328240
Directory /workspace/32.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.219348621
Short name T17
Test name
Test status
Simulation time 336515790000 ps
CPU time 651.92 seconds
Started Aug 05 04:22:01 PM PDT 24
Finished Aug 05 04:48:43 PM PDT 24
Peak memory 160612 kb
Host smart-654dfd5d-2ccd-46c3-839f-94ab7010e624
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=219348621 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.219348621
Directory /workspace/33.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.1300203323
Short name T78
Test name
Test status
Simulation time 336434530000 ps
CPU time 921.4 seconds
Started Aug 05 04:21:58 PM PDT 24
Finished Aug 05 04:59:47 PM PDT 24
Peak memory 160652 kb
Host smart-934fb780-694f-4ab2-ad86-54a47e57fa56
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1300203323 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.1300203323
Directory /workspace/34.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.802554967
Short name T74
Test name
Test status
Simulation time 336961270000 ps
CPU time 833.18 seconds
Started Aug 05 04:22:14 PM PDT 24
Finished Aug 05 04:56:42 PM PDT 24
Peak memory 160276 kb
Host smart-bb49459f-8590-4433-8f59-5a4fab66b96a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=802554967 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.802554967
Directory /workspace/35.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.1599509009
Short name T96
Test name
Test status
Simulation time 336295830000 ps
CPU time 659.63 seconds
Started Aug 05 04:21:55 PM PDT 24
Finished Aug 05 04:49:34 PM PDT 24
Peak memory 160252 kb
Host smart-beb6c1c3-cd93-4abf-b33d-3878ea741751
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1599509009 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.1599509009
Directory /workspace/36.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.3506151929
Short name T83
Test name
Test status
Simulation time 336414910000 ps
CPU time 738.22 seconds
Started Aug 05 04:22:13 PM PDT 24
Finished Aug 05 04:52:20 PM PDT 24
Peak memory 160588 kb
Host smart-aaec315a-03fb-40d5-9b0f-992ed81ccd3c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3506151929 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.3506151929
Directory /workspace/37.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.2978027615
Short name T80
Test name
Test status
Simulation time 337065590000 ps
CPU time 654.14 seconds
Started Aug 05 04:23:19 PM PDT 24
Finished Aug 05 04:50:41 PM PDT 24
Peak memory 160256 kb
Host smart-f8ede9c1-4031-4a76-8b71-50cb2970a711
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2978027615 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.2978027615
Directory /workspace/38.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.1180188945
Short name T102
Test name
Test status
Simulation time 336547430000 ps
CPU time 628.15 seconds
Started Aug 05 04:22:03 PM PDT 24
Finished Aug 05 04:47:48 PM PDT 24
Peak memory 160636 kb
Host smart-86bd2c92-fa5a-4a2d-8c56-4755acb70b53
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1180188945 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.1180188945
Directory /workspace/39.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.2311104800
Short name T98
Test name
Test status
Simulation time 336919030000 ps
CPU time 887.94 seconds
Started Aug 05 04:21:48 PM PDT 24
Finished Aug 05 04:58:02 PM PDT 24
Peak memory 160608 kb
Host smart-8e4ec0f6-1bf9-4d77-890d-83c41d055551
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2311104800 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.2311104800
Directory /workspace/4.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.2641812004
Short name T100
Test name
Test status
Simulation time 336660270000 ps
CPU time 671.13 seconds
Started Aug 05 04:23:21 PM PDT 24
Finished Aug 05 04:51:16 PM PDT 24
Peak memory 160256 kb
Host smart-cfb734bb-2f70-4f0d-99f7-c813792f7357
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2641812004 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.2641812004
Directory /workspace/40.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.4249083106
Short name T92
Test name
Test status
Simulation time 336473910000 ps
CPU time 770.16 seconds
Started Aug 05 04:22:08 PM PDT 24
Finished Aug 05 04:53:48 PM PDT 24
Peak memory 160624 kb
Host smart-1c2bd039-5bda-4a87-be39-6f1507cbc753
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4249083106 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.4249083106
Directory /workspace/41.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.3576247436
Short name T95
Test name
Test status
Simulation time 336674370000 ps
CPU time 937.55 seconds
Started Aug 05 04:21:58 PM PDT 24
Finished Aug 05 04:59:55 PM PDT 24
Peak memory 160564 kb
Host smart-823a6fdf-cb90-41f6-b94a-c8109a05715e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3576247436 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.3576247436
Directory /workspace/42.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.2823147916
Short name T75
Test name
Test status
Simulation time 336945970000 ps
CPU time 779.08 seconds
Started Aug 05 04:22:08 PM PDT 24
Finished Aug 05 04:54:08 PM PDT 24
Peak memory 160624 kb
Host smart-b557c4a5-8827-46cd-a4a2-1fcb24082d5d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2823147916 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.2823147916
Directory /workspace/43.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.67872954
Short name T82
Test name
Test status
Simulation time 336817610000 ps
CPU time 826.39 seconds
Started Aug 05 04:22:03 PM PDT 24
Finished Aug 05 04:56:00 PM PDT 24
Peak memory 159580 kb
Host smart-1e8c6e0b-a028-4a34-8610-5a667109d11e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=67872954 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.67872954
Directory /workspace/44.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.682407030
Short name T20
Test name
Test status
Simulation time 336546410000 ps
CPU time 918.04 seconds
Started Aug 05 04:21:58 PM PDT 24
Finished Aug 05 04:59:33 PM PDT 24
Peak memory 160640 kb
Host smart-651394ea-29e5-4c81-acd0-c91719e87809
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=682407030 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.682407030
Directory /workspace/45.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.1137187873
Short name T108
Test name
Test status
Simulation time 336815770000 ps
CPU time 929.92 seconds
Started Aug 05 04:21:58 PM PDT 24
Finished Aug 05 04:59:55 PM PDT 24
Peak memory 160564 kb
Host smart-28dc7937-e4d5-4848-96ad-6f0f57d882e4
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1137187873 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.1137187873
Directory /workspace/46.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.3289289750
Short name T106
Test name
Test status
Simulation time 336698070000 ps
CPU time 794.73 seconds
Started Aug 05 04:22:07 PM PDT 24
Finished Aug 05 04:54:43 PM PDT 24
Peak memory 160624 kb
Host smart-61845ebf-d840-421a-8c5e-f66c38444da0
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3289289750 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.3289289750
Directory /workspace/47.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.582358618
Short name T16
Test name
Test status
Simulation time 337010010000 ps
CPU time 666.8 seconds
Started Aug 05 04:23:15 PM PDT 24
Finished Aug 05 04:50:57 PM PDT 24
Peak memory 160244 kb
Host smart-87656bd6-5eb6-4af0-8d22-af5a0107e30e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=582358618 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.582358618
Directory /workspace/48.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.2755682370
Short name T94
Test name
Test status
Simulation time 336382730000 ps
CPU time 842.73 seconds
Started Aug 05 04:22:03 PM PDT 24
Finished Aug 05 04:56:18 PM PDT 24
Peak memory 159128 kb
Host smart-d7237024-5138-45b8-a062-109493c8a98a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2755682370 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.2755682370
Directory /workspace/49.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.3553584019
Short name T110
Test name
Test status
Simulation time 336440610000 ps
CPU time 921.44 seconds
Started Aug 05 04:21:55 PM PDT 24
Finished Aug 05 04:59:11 PM PDT 24
Peak memory 160608 kb
Host smart-8ad86a80-1da1-409f-87de-4b7cf67ba6ef
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3553584019 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.3553584019
Directory /workspace/5.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.1758431731
Short name T19
Test name
Test status
Simulation time 336796730000 ps
CPU time 547.34 seconds
Started Aug 05 04:22:16 PM PDT 24
Finished Aug 05 04:45:52 PM PDT 24
Peak memory 159736 kb
Host smart-677fbb22-36e9-4269-a8a0-f3cc1db15bc4
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1758431731 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.1758431731
Directory /workspace/6.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.3796950817
Short name T91
Test name
Test status
Simulation time 336467970000 ps
CPU time 730.14 seconds
Started Aug 05 04:21:45 PM PDT 24
Finished Aug 05 04:51:52 PM PDT 24
Peak memory 160636 kb
Host smart-0e248bd8-ab00-4caa-8366-ebe3f6e871d5
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3796950817 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.3796950817
Directory /workspace/7.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.3496549202
Short name T89
Test name
Test status
Simulation time 336766790000 ps
CPU time 915.28 seconds
Started Aug 05 04:21:48 PM PDT 24
Finished Aug 05 04:59:16 PM PDT 24
Peak memory 160608 kb
Host smart-d560b4ad-b6bf-4593-afe0-9fd7fe0e139c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3496549202 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.3496549202
Directory /workspace/8.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.1683214306
Short name T103
Test name
Test status
Simulation time 336357710000 ps
CPU time 910.01 seconds
Started Aug 05 04:21:49 PM PDT 24
Finished Aug 05 04:59:10 PM PDT 24
Peak memory 160632 kb
Host smart-274011d5-1bae-4fbe-8d6e-afe512dac0b1
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1683214306 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.1683214306
Directory /workspace/9.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.4069240212
Short name T193
Test name
Test status
Simulation time 337136610000 ps
CPU time 933.86 seconds
Started Aug 05 04:18:27 PM PDT 24
Finished Aug 05 04:56:34 PM PDT 24
Peak memory 160416 kb
Host smart-ccc8118b-3f54-4f42-831e-eb0c2d069f91
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4069240212 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.4069240212
Directory /workspace/0.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.3766090546
Short name T167
Test name
Test status
Simulation time 336593930000 ps
CPU time 621.21 seconds
Started Aug 05 04:22:07 PM PDT 24
Finished Aug 05 04:48:28 PM PDT 24
Peak memory 159468 kb
Host smart-735c6737-7771-46c9-9498-504691b5ba26
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3766090546 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.3766090546
Directory /workspace/10.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.906043142
Short name T182
Test name
Test status
Simulation time 336876490000 ps
CPU time 517.99 seconds
Started Aug 05 04:22:24 PM PDT 24
Finished Aug 05 04:44:41 PM PDT 24
Peak memory 160636 kb
Host smart-d710a1a5-b706-4c42-9dea-304c99f1e6b3
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=906043142 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.906043142
Directory /workspace/11.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.2729549735
Short name T26
Test name
Test status
Simulation time 336643570000 ps
CPU time 702.64 seconds
Started Aug 05 04:22:20 PM PDT 24
Finished Aug 05 04:51:18 PM PDT 24
Peak memory 160636 kb
Host smart-df0bb5d7-d074-4ce7-9a35-3af375306e17
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2729549735 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.2729549735
Directory /workspace/12.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.2180316419
Short name T172
Test name
Test status
Simulation time 336490710000 ps
CPU time 700.85 seconds
Started Aug 05 04:22:20 PM PDT 24
Finished Aug 05 04:51:09 PM PDT 24
Peak memory 160636 kb
Host smart-b121e2f9-4a6b-4227-9fa1-6f8c4883dfe4
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2180316419 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.2180316419
Directory /workspace/13.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.2501621438
Short name T184
Test name
Test status
Simulation time 336790350000 ps
CPU time 868.47 seconds
Started Aug 05 04:17:45 PM PDT 24
Finished Aug 05 04:54:35 PM PDT 24
Peak memory 160536 kb
Host smart-9417975e-9ef8-44e5-8f39-d6a2b6da5d65
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2501621438 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.2501621438
Directory /workspace/14.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.1572040075
Short name T189
Test name
Test status
Simulation time 336648970000 ps
CPU time 933.19 seconds
Started Aug 05 04:20:04 PM PDT 24
Finished Aug 05 04:58:20 PM PDT 24
Peak memory 160656 kb
Host smart-a3666350-9aff-48ee-a766-77b74be29979
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1572040075 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.1572040075
Directory /workspace/15.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.3414965480
Short name T185
Test name
Test status
Simulation time 336542330000 ps
CPU time 880.69 seconds
Started Aug 05 04:16:55 PM PDT 24
Finished Aug 05 04:52:09 PM PDT 24
Peak memory 159600 kb
Host smart-f127c0dd-b210-4699-99da-84f1942a1290
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3414965480 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.3414965480
Directory /workspace/16.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.3771671894
Short name T179
Test name
Test status
Simulation time 336973850000 ps
CPU time 889.71 seconds
Started Aug 05 04:16:54 PM PDT 24
Finished Aug 05 04:54:30 PM PDT 24
Peak memory 159176 kb
Host smart-bf65c0c8-9726-4ed8-8bec-39a47393404f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3771671894 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.3771671894
Directory /workspace/17.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.337802819
Short name T21
Test name
Test status
Simulation time 336960950000 ps
CPU time 882.44 seconds
Started Aug 05 04:16:54 PM PDT 24
Finished Aug 05 04:54:27 PM PDT 24
Peak memory 159136 kb
Host smart-202748c0-bc88-49fe-9531-6fd701ab9333
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=337802819 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.337802819
Directory /workspace/18.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.1092080833
Short name T175
Test name
Test status
Simulation time 336864390000 ps
CPU time 827.3 seconds
Started Aug 05 04:21:53 PM PDT 24
Finished Aug 05 04:55:48 PM PDT 24
Peak memory 160364 kb
Host smart-6da9e622-c855-4aaf-81e9-1e344e654ab5
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1092080833 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.1092080833
Directory /workspace/19.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.2856689769
Short name T30
Test name
Test status
Simulation time 336869670000 ps
CPU time 712.73 seconds
Started Aug 05 04:19:33 PM PDT 24
Finished Aug 05 04:48:34 PM PDT 24
Peak memory 160868 kb
Host smart-0a38559b-a0ff-4cd2-8ed3-ccaac6d56dc5
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2856689769 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.2856689769
Directory /workspace/2.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.4251462070
Short name T166
Test name
Test status
Simulation time 336775390000 ps
CPU time 846.31 seconds
Started Aug 05 04:18:23 PM PDT 24
Finished Aug 05 04:52:51 PM PDT 24
Peak memory 160228 kb
Host smart-e069b07b-e008-4f81-a20c-998f930020f0
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4251462070 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.4251462070
Directory /workspace/20.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.1680198265
Short name T178
Test name
Test status
Simulation time 337141950000 ps
CPU time 899.32 seconds
Started Aug 05 04:18:24 PM PDT 24
Finished Aug 05 04:54:39 PM PDT 24
Peak memory 160536 kb
Host smart-132a44ec-c578-445b-8699-03a11e1bcdeb
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1680198265 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.1680198265
Directory /workspace/21.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.3587941573
Short name T187
Test name
Test status
Simulation time 336810210000 ps
CPU time 857.46 seconds
Started Aug 05 04:16:56 PM PDT 24
Finished Aug 05 04:53:20 PM PDT 24
Peak memory 160376 kb
Host smart-eec5dc2a-b7e5-4518-b3e7-277476162dbd
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3587941573 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.3587941573
Directory /workspace/22.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.1302480505
Short name T28
Test name
Test status
Simulation time 336836970000 ps
CPU time 865.67 seconds
Started Aug 05 04:16:55 PM PDT 24
Finished Aug 05 04:52:18 PM PDT 24
Peak memory 159728 kb
Host smart-5a7c877f-4d13-4c09-aeb9-5080beca3b0a
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1302480505 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.1302480505
Directory /workspace/23.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.3486437268
Short name T161
Test name
Test status
Simulation time 336333270000 ps
CPU time 898.27 seconds
Started Aug 05 04:16:54 PM PDT 24
Finished Aug 05 04:54:35 PM PDT 24
Peak memory 159224 kb
Host smart-bb45e66d-51be-401b-95e0-6b3c8a1d325c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3486437268 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.3486437268
Directory /workspace/24.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.1578744011
Short name T168
Test name
Test status
Simulation time 336699310000 ps
CPU time 777.87 seconds
Started Aug 05 04:21:40 PM PDT 24
Finished Aug 05 04:54:02 PM PDT 24
Peak memory 159576 kb
Host smart-975a9864-71e0-49dd-b8d5-a1d1fc755ba5
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1578744011 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.1578744011
Directory /workspace/25.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.3853295323
Short name T191
Test name
Test status
Simulation time 336602770000 ps
CPU time 625.19 seconds
Started Aug 05 04:21:56 PM PDT 24
Finished Aug 05 04:47:39 PM PDT 24
Peak memory 160640 kb
Host smart-5945225a-a76c-4e65-9a86-0dfd7d1b9e26
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3853295323 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.3853295323
Directory /workspace/26.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.1257568601
Short name T22
Test name
Test status
Simulation time 336873650000 ps
CPU time 890.59 seconds
Started Aug 05 04:18:03 PM PDT 24
Finished Aug 05 04:55:19 PM PDT 24
Peak memory 160536 kb
Host smart-ce5e2453-d8ec-4e50-b565-572e88a80536
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1257568601 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.1257568601
Directory /workspace/27.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.2932446010
Short name T174
Test name
Test status
Simulation time 336790050000 ps
CPU time 861.08 seconds
Started Aug 05 04:18:08 PM PDT 24
Finished Aug 05 04:53:35 PM PDT 24
Peak memory 160204 kb
Host smart-87f14fa0-76ca-49b6-b8c4-a9ddb99b438f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2932446010 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.2932446010
Directory /workspace/28.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.2478491529
Short name T25
Test name
Test status
Simulation time 336580490000 ps
CPU time 887.53 seconds
Started Aug 05 04:18:09 PM PDT 24
Finished Aug 05 04:54:24 PM PDT 24
Peak memory 160204 kb
Host smart-eae0db01-1ef4-432b-b697-11edeb42160a
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2478491529 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.2478491529
Directory /workspace/29.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.1576651380
Short name T180
Test name
Test status
Simulation time 336807990000 ps
CPU time 772.57 seconds
Started Aug 05 04:21:40 PM PDT 24
Finished Aug 05 04:53:56 PM PDT 24
Peak memory 159596 kb
Host smart-c06bbe59-932e-4bdf-a105-e581fd0221ba
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1576651380 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.1576651380
Directory /workspace/3.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.395591487
Short name T173
Test name
Test status
Simulation time 336630390000 ps
CPU time 674.36 seconds
Started Aug 05 04:18:01 PM PDT 24
Finished Aug 05 04:46:03 PM PDT 24
Peak memory 160248 kb
Host smart-7a8f7b0d-185a-4d45-adde-7d7e245f1e71
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=395591487 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.395591487
Directory /workspace/30.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.3624435218
Short name T188
Test name
Test status
Simulation time 336517970000 ps
CPU time 838.37 seconds
Started Aug 05 04:20:25 PM PDT 24
Finished Aug 05 04:54:45 PM PDT 24
Peak memory 160628 kb
Host smart-34c93128-a8e1-4d97-95f9-66a0a05c90b8
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3624435218 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.3624435218
Directory /workspace/31.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.12513641
Short name T176
Test name
Test status
Simulation time 336517830000 ps
CPU time 940.55 seconds
Started Aug 05 04:18:21 PM PDT 24
Finished Aug 05 04:56:16 PM PDT 24
Peak memory 160176 kb
Host smart-e50e06d7-c47c-493c-861f-2b2cf507da05
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=12513641 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.12513641
Directory /workspace/32.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.1434475273
Short name T177
Test name
Test status
Simulation time 336862130000 ps
CPU time 935.56 seconds
Started Aug 05 04:19:07 PM PDT 24
Finished Aug 05 04:57:12 PM PDT 24
Peak memory 160632 kb
Host smart-64084782-5f78-422d-8d62-a4bd000f6b44
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1434475273 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.1434475273
Directory /workspace/33.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.2778594834
Short name T192
Test name
Test status
Simulation time 337103210000 ps
CPU time 792.98 seconds
Started Aug 05 04:18:30 PM PDT 24
Finished Aug 05 04:50:38 PM PDT 24
Peak memory 160920 kb
Host smart-99716334-3b77-4d65-937f-95f64835b6cc
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2778594834 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.2778594834
Directory /workspace/34.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.2975997716
Short name T27
Test name
Test status
Simulation time 336820350000 ps
CPU time 907.22 seconds
Started Aug 05 04:18:28 PM PDT 24
Finished Aug 05 04:55:41 PM PDT 24
Peak memory 160428 kb
Host smart-71ce33e1-44c2-4ea9-8b7d-88a80d83f44c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2975997716 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.2975997716
Directory /workspace/35.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.3983050037
Short name T24
Test name
Test status
Simulation time 336683910000 ps
CPU time 788.12 seconds
Started Aug 05 04:17:46 PM PDT 24
Finished Aug 05 04:49:39 PM PDT 24
Peak memory 160924 kb
Host smart-9a358a1d-b92c-42df-95a1-50565eb339df
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3983050037 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.3983050037
Directory /workspace/36.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.581306729
Short name T165
Test name
Test status
Simulation time 336461030000 ps
CPU time 734.08 seconds
Started Aug 05 04:21:58 PM PDT 24
Finished Aug 05 04:52:15 PM PDT 24
Peak memory 160328 kb
Host smart-fc69c838-4ace-405e-b44f-f4a2291f4280
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=581306729 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.581306729
Directory /workspace/37.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.1826763327
Short name T181
Test name
Test status
Simulation time 336814930000 ps
CPU time 677.74 seconds
Started Aug 05 04:21:42 PM PDT 24
Finished Aug 05 04:49:38 PM PDT 24
Peak memory 159636 kb
Host smart-fc6f17b2-0649-41ae-b881-b35d8f41fb85
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1826763327 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.1826763327
Directory /workspace/38.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.868619143
Short name T186
Test name
Test status
Simulation time 336716230000 ps
CPU time 705.56 seconds
Started Aug 05 04:21:56 PM PDT 24
Finished Aug 05 04:51:04 PM PDT 24
Peak memory 160328 kb
Host smart-795687a3-1f0d-452f-8776-7616c49d78da
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=868619143 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.868619143
Directory /workspace/39.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.3525412089
Short name T169
Test name
Test status
Simulation time 337033710000 ps
CPU time 686.15 seconds
Started Aug 05 04:18:45 PM PDT 24
Finished Aug 05 04:47:16 PM PDT 24
Peak memory 160224 kb
Host smart-a257ab9d-2f13-40a4-963f-af555cafebc5
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3525412089 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.3525412089
Directory /workspace/4.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.1213883562
Short name T162
Test name
Test status
Simulation time 336821650000 ps
CPU time 833.8 seconds
Started Aug 05 04:22:34 PM PDT 24
Finished Aug 05 04:57:41 PM PDT 24
Peak memory 159764 kb
Host smart-4d1b2697-15a7-4073-b5c1-89f3e8e522ae
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1213883562 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.1213883562
Directory /workspace/40.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.393456348
Short name T200
Test name
Test status
Simulation time 336862350000 ps
CPU time 865.87 seconds
Started Aug 05 04:23:00 PM PDT 24
Finished Aug 05 04:59:19 PM PDT 24
Peak memory 160248 kb
Host smart-b93cf6ff-d8b4-43ed-9e88-0e41ae87d7fd
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=393456348 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.393456348
Directory /workspace/41.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.2487178114
Short name T183
Test name
Test status
Simulation time 336940230000 ps
CPU time 710.36 seconds
Started Aug 05 04:17:24 PM PDT 24
Finished Aug 05 04:46:42 PM PDT 24
Peak memory 159748 kb
Host smart-adfdbaa2-f922-4ddc-b3d9-c55737ce1f2b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2487178114 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.2487178114
Directory /workspace/42.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.2170463611
Short name T190
Test name
Test status
Simulation time 336896450000 ps
CPU time 633.2 seconds
Started Aug 05 04:21:22 PM PDT 24
Finished Aug 05 04:47:25 PM PDT 24
Peak memory 159764 kb
Host smart-b63ca981-70eb-467b-afef-ba8331798548
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2170463611 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.2170463611
Directory /workspace/43.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.3574915877
Short name T170
Test name
Test status
Simulation time 336991510000 ps
CPU time 702.17 seconds
Started Aug 05 04:21:37 PM PDT 24
Finished Aug 05 04:50:37 PM PDT 24
Peak memory 160260 kb
Host smart-15284a8e-e80b-43df-beff-97fd7d66faf1
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3574915877 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.3574915877
Directory /workspace/44.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.2917910441
Short name T23
Test name
Test status
Simulation time 336690230000 ps
CPU time 710.25 seconds
Started Aug 05 04:21:37 PM PDT 24
Finished Aug 05 04:50:47 PM PDT 24
Peak memory 160260 kb
Host smart-7b657be6-40d9-472c-92b5-630f0beaf5fb
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2917910441 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.2917910441
Directory /workspace/45.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.1776227745
Short name T198
Test name
Test status
Simulation time 336458830000 ps
CPU time 785.61 seconds
Started Aug 05 04:17:46 PM PDT 24
Finished Aug 05 04:49:39 PM PDT 24
Peak memory 160920 kb
Host smart-e02a64e7-e9fe-4666-b952-e7bcdbee87bc
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1776227745 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.1776227745
Directory /workspace/46.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.2032084337
Short name T171
Test name
Test status
Simulation time 336696550000 ps
CPU time 868.45 seconds
Started Aug 05 04:23:05 PM PDT 24
Finished Aug 05 04:59:16 PM PDT 24
Peak memory 160260 kb
Host smart-bb34b58e-76c8-42fc-8309-058dacc8e041
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2032084337 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.2032084337
Directory /workspace/47.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.2500062362
Short name T164
Test name
Test status
Simulation time 336798790000 ps
CPU time 840.04 seconds
Started Aug 05 04:23:02 PM PDT 24
Finished Aug 05 04:58:00 PM PDT 24
Peak memory 160260 kb
Host smart-4edfdb19-f08b-4b1a-b236-ab0218857b07
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2500062362 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.2500062362
Directory /workspace/48.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.2298395658
Short name T199
Test name
Test status
Simulation time 337123150000 ps
CPU time 641.47 seconds
Started Aug 05 04:22:51 PM PDT 24
Finished Aug 05 04:49:32 PM PDT 24
Peak memory 159592 kb
Host smart-59226385-9d34-4231-b6b9-4bd543fc0149
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2298395658 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.2298395658
Directory /workspace/49.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.4159552056
Short name T196
Test name
Test status
Simulation time 336937410000 ps
CPU time 740.05 seconds
Started Aug 05 04:22:55 PM PDT 24
Finished Aug 05 04:53:17 PM PDT 24
Peak memory 160340 kb
Host smart-74b4f1b3-215f-4fec-bc60-7e85ec3bc63b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4159552056 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.4159552056
Directory /workspace/5.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.2712812550
Short name T163
Test name
Test status
Simulation time 336351190000 ps
CPU time 747.23 seconds
Started Aug 05 04:22:55 PM PDT 24
Finished Aug 05 04:53:29 PM PDT 24
Peak memory 160340 kb
Host smart-7bed2ed8-7ec2-4761-a09c-71cded798e82
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2712812550 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.2712812550
Directory /workspace/6.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.3479258739
Short name T195
Test name
Test status
Simulation time 336404750000 ps
CPU time 725.05 seconds
Started Aug 05 04:22:54 PM PDT 24
Finished Aug 05 04:52:39 PM PDT 24
Peak memory 160244 kb
Host smart-da03082f-fce6-490a-9aef-794ec7fccba1
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3479258739 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.3479258739
Directory /workspace/7.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.1149883910
Short name T197
Test name
Test status
Simulation time 336280810000 ps
CPU time 930.66 seconds
Started Aug 05 04:20:32 PM PDT 24
Finished Aug 05 04:58:49 PM PDT 24
Peak memory 160656 kb
Host smart-f8da5fb5-5bdb-4e97-9945-0ca9ec5a7f56
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1149883910 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.1149883910
Directory /workspace/8.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.1801656594
Short name T194
Test name
Test status
Simulation time 336577770000 ps
CPU time 908.39 seconds
Started Aug 05 04:19:20 PM PDT 24
Finished Aug 05 04:56:42 PM PDT 24
Peak memory 160636 kb
Host smart-1b2d1561-c225-45b5-9dae-c790d2209f46
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1801656594 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.1801656594
Directory /workspace/9.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.4228247701
Short name T143
Test name
Test status
Simulation time 1546890000 ps
CPU time 3.92 seconds
Started Aug 05 04:22:23 PM PDT 24
Finished Aug 05 04:22:32 PM PDT 24
Peak memory 164700 kb
Host smart-10960cc9-6a66-446a-ac7f-bc5036fed25f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4228247701 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.4228247701
Directory /workspace/0.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.76109566
Short name T147
Test name
Test status
Simulation time 1253970000 ps
CPU time 3.38 seconds
Started Aug 05 04:22:13 PM PDT 24
Finished Aug 05 04:22:21 PM PDT 24
Peak memory 164772 kb
Host smart-a8cbc843-a524-4603-9e25-9f511799bddf
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=76109566 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.76109566
Directory /workspace/1.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.3202174611
Short name T140
Test name
Test status
Simulation time 1429770000 ps
CPU time 4.62 seconds
Started Aug 05 04:22:15 PM PDT 24
Finished Aug 05 04:22:26 PM PDT 24
Peak memory 164348 kb
Host smart-ec9d74fc-09c0-44e0-b5a6-d06e21a58a28
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3202174611 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.3202174611
Directory /workspace/10.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.1200932025
Short name T131
Test name
Test status
Simulation time 1507610000 ps
CPU time 4.24 seconds
Started Aug 05 04:22:10 PM PDT 24
Finished Aug 05 04:22:20 PM PDT 24
Peak memory 164764 kb
Host smart-b73188f2-056b-4ca6-a264-58151ef50e22
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1200932025 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.1200932025
Directory /workspace/11.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.489216162
Short name T144
Test name
Test status
Simulation time 1313490000 ps
CPU time 3.96 seconds
Started Aug 05 04:22:11 PM PDT 24
Finished Aug 05 04:22:20 PM PDT 24
Peak memory 165020 kb
Host smart-5b4554ee-1fbd-40a0-ae37-a6df07c6ba25
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=489216162 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.489216162
Directory /workspace/12.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.3702406047
Short name T159
Test name
Test status
Simulation time 1153450000 ps
CPU time 3.23 seconds
Started Aug 05 04:23:14 PM PDT 24
Finished Aug 05 04:23:22 PM PDT 24
Peak memory 163368 kb
Host smart-85ea0292-1d2e-4bed-9621-8977f44d7747
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3702406047 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.3702406047
Directory /workspace/13.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.937536032
Short name T154
Test name
Test status
Simulation time 1354250000 ps
CPU time 3.71 seconds
Started Aug 05 04:22:14 PM PDT 24
Finished Aug 05 04:22:23 PM PDT 24
Peak memory 164772 kb
Host smart-00f2113e-c809-439a-929a-3a5a8e91b92f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=937536032 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.937536032
Directory /workspace/14.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.537696011
Short name T145
Test name
Test status
Simulation time 1399910000 ps
CPU time 4.24 seconds
Started Aug 05 04:22:15 PM PDT 24
Finished Aug 05 04:22:25 PM PDT 24
Peak memory 164940 kb
Host smart-07d3c262-17ef-45d5-aebb-0d9a11ca06d4
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=537696011 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.537696011
Directory /workspace/15.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.3763471033
Short name T119
Test name
Test status
Simulation time 1564810000 ps
CPU time 4.93 seconds
Started Aug 05 04:22:20 PM PDT 24
Finished Aug 05 04:22:30 PM PDT 24
Peak memory 164348 kb
Host smart-6f09a5b5-ae70-474a-a2c9-76b2749a85f5
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3763471033 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.3763471033
Directory /workspace/16.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.4228176889
Short name T115
Test name
Test status
Simulation time 1575510000 ps
CPU time 3.98 seconds
Started Aug 05 04:22:25 PM PDT 24
Finished Aug 05 04:22:34 PM PDT 24
Peak memory 164716 kb
Host smart-7532c3d3-549c-4ae1-bee7-22878aecc03d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4228176889 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.4228176889
Directory /workspace/17.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.4156791958
Short name T155
Test name
Test status
Simulation time 1589630000 ps
CPU time 5.15 seconds
Started Aug 05 04:22:32 PM PDT 24
Finished Aug 05 04:22:44 PM PDT 24
Peak memory 165020 kb
Host smart-cb75418e-441f-42c2-8eea-ed68f668921e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4156791958 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.4156791958
Directory /workspace/18.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.3094948575
Short name T139
Test name
Test status
Simulation time 1568610000 ps
CPU time 5.28 seconds
Started Aug 05 04:22:34 PM PDT 24
Finished Aug 05 04:22:47 PM PDT 24
Peak memory 164696 kb
Host smart-e266a3f5-8796-40ce-8c21-f39114eff7a2
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3094948575 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.3094948575
Directory /workspace/19.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.1966262073
Short name T114
Test name
Test status
Simulation time 1392170000 ps
CPU time 3.29 seconds
Started Aug 05 04:22:19 PM PDT 24
Finished Aug 05 04:22:27 PM PDT 24
Peak memory 164700 kb
Host smart-101a56b9-d85a-4272-b1ca-a5395af9137f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1966262073 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.1966262073
Directory /workspace/2.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.3604362085
Short name T120
Test name
Test status
Simulation time 1355510000 ps
CPU time 4.59 seconds
Started Aug 05 04:22:30 PM PDT 24
Finished Aug 05 04:22:40 PM PDT 24
Peak memory 164748 kb
Host smart-74e7a3cf-af23-4f4e-aede-95539f8d696a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3604362085 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.3604362085
Directory /workspace/20.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3009603180
Short name T157
Test name
Test status
Simulation time 1178510000 ps
CPU time 3.17 seconds
Started Aug 05 04:22:24 PM PDT 24
Finished Aug 05 04:22:32 PM PDT 24
Peak memory 164320 kb
Host smart-eea2cd04-f575-4403-af42-eeda522bd568
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3009603180 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.3009603180
Directory /workspace/21.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.3876511942
Short name T129
Test name
Test status
Simulation time 1436250000 ps
CPU time 4.42 seconds
Started Aug 05 04:22:31 PM PDT 24
Finished Aug 05 04:22:40 PM PDT 24
Peak memory 164668 kb
Host smart-394dc8fd-0edb-4c5e-825c-13a4a6691968
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3876511942 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.3876511942
Directory /workspace/22.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.2703323222
Short name T149
Test name
Test status
Simulation time 1564570000 ps
CPU time 4.36 seconds
Started Aug 05 04:22:24 PM PDT 24
Finished Aug 05 04:22:34 PM PDT 24
Peak memory 164764 kb
Host smart-aed71445-5434-4813-aaf8-dfb3d4f38ac0
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2703323222 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.2703323222
Directory /workspace/23.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.3705452381
Short name T117
Test name
Test status
Simulation time 1614950000 ps
CPU time 5.47 seconds
Started Aug 05 04:22:27 PM PDT 24
Finished Aug 05 04:22:39 PM PDT 24
Peak memory 164708 kb
Host smart-b3d10b4a-54b0-47d8-b1d6-8b3dc3d4e9e0
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3705452381 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.3705452381
Directory /workspace/24.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.2331739646
Short name T118
Test name
Test status
Simulation time 1387690000 ps
CPU time 4.31 seconds
Started Aug 05 04:22:25 PM PDT 24
Finished Aug 05 04:22:34 PM PDT 24
Peak memory 164748 kb
Host smart-b82d7b49-b7da-4195-86b1-a51717ed8a47
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2331739646 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.2331739646
Directory /workspace/25.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.4100615697
Short name T150
Test name
Test status
Simulation time 1509730000 ps
CPU time 4.34 seconds
Started Aug 05 04:22:42 PM PDT 24
Finished Aug 05 04:22:51 PM PDT 24
Peak memory 164680 kb
Host smart-6f5bf9d9-7470-4a76-8cb7-9382b20df86b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4100615697 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.4100615697
Directory /workspace/26.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.3209756790
Short name T116
Test name
Test status
Simulation time 1522870000 ps
CPU time 3.98 seconds
Started Aug 05 04:22:28 PM PDT 24
Finished Aug 05 04:22:37 PM PDT 24
Peak memory 164700 kb
Host smart-bc69cb6d-7c18-4087-bcf9-33f0d22f18cf
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3209756790 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.3209756790
Directory /workspace/27.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.1551785032
Short name T152
Test name
Test status
Simulation time 1296910000 ps
CPU time 2.78 seconds
Started Aug 05 04:23:34 PM PDT 24
Finished Aug 05 04:23:41 PM PDT 24
Peak memory 164452 kb
Host smart-2e2fc35d-d27a-4e71-92bf-8caf2946bede
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1551785032 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.1551785032
Directory /workspace/28.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.1686513477
Short name T123
Test name
Test status
Simulation time 1567990000 ps
CPU time 5.29 seconds
Started Aug 05 04:22:27 PM PDT 24
Finished Aug 05 04:22:39 PM PDT 24
Peak memory 164708 kb
Host smart-4a4ff002-ffd6-457e-b2a9-918337af8b77
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1686513477 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.1686513477
Directory /workspace/29.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.3696935403
Short name T133
Test name
Test status
Simulation time 1413770000 ps
CPU time 3.73 seconds
Started Aug 05 04:22:23 PM PDT 24
Finished Aug 05 04:22:31 PM PDT 24
Peak memory 164700 kb
Host smart-2a3b744c-725b-4713-96f5-2962d44611a1
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3696935403 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.3696935403
Directory /workspace/3.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.3373753746
Short name T125
Test name
Test status
Simulation time 1532710000 ps
CPU time 4.06 seconds
Started Aug 05 04:22:30 PM PDT 24
Finished Aug 05 04:22:39 PM PDT 24
Peak memory 164536 kb
Host smart-5dddb3cd-a3e8-4abc-8b1a-05b8b329a8ee
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3373753746 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.3373753746
Directory /workspace/30.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.391996332
Short name T127
Test name
Test status
Simulation time 1420530000 ps
CPU time 5.12 seconds
Started Aug 05 04:22:29 PM PDT 24
Finished Aug 05 04:22:40 PM PDT 24
Peak memory 164320 kb
Host smart-58988c0b-f0fd-45e3-8696-cab9f5bca6a6
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=391996332 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.391996332
Directory /workspace/31.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.2236358998
Short name T151
Test name
Test status
Simulation time 1417090000 ps
CPU time 4.34 seconds
Started Aug 05 04:22:21 PM PDT 24
Finished Aug 05 04:22:31 PM PDT 24
Peak memory 164796 kb
Host smart-639211ed-4ca8-4d00-883d-ff46c4d409a4
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2236358998 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.2236358998
Directory /workspace/32.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.3351367213
Short name T134
Test name
Test status
Simulation time 1543890000 ps
CPU time 4.45 seconds
Started Aug 05 04:22:40 PM PDT 24
Finished Aug 05 04:22:50 PM PDT 24
Peak memory 164732 kb
Host smart-153e87da-021a-4d67-8001-3b3e3eae58b8
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3351367213 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.3351367213
Directory /workspace/33.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.2886983504
Short name T148
Test name
Test status
Simulation time 1409190000 ps
CPU time 3.54 seconds
Started Aug 05 04:22:40 PM PDT 24
Finished Aug 05 04:22:48 PM PDT 24
Peak memory 164680 kb
Host smart-7d43a263-6301-4cf5-a9ea-4991b44e3df5
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2886983504 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.2886983504
Directory /workspace/34.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.3914348778
Short name T158
Test name
Test status
Simulation time 1493330000 ps
CPU time 4.3 seconds
Started Aug 05 04:22:24 PM PDT 24
Finished Aug 05 04:22:34 PM PDT 24
Peak memory 164700 kb
Host smart-4c945904-49a2-49b0-8e32-03a53e4f6da4
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3914348778 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.3914348778
Directory /workspace/35.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.4142770667
Short name T138
Test name
Test status
Simulation time 1478950000 ps
CPU time 3.01 seconds
Started Aug 05 04:22:30 PM PDT 24
Finished Aug 05 04:22:37 PM PDT 24
Peak memory 164768 kb
Host smart-4a5f8099-4434-49e7-ab82-d56424187d17
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4142770667 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.4142770667
Directory /workspace/36.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.2894218731
Short name T142
Test name
Test status
Simulation time 1294650000 ps
CPU time 4.04 seconds
Started Aug 05 04:22:34 PM PDT 24
Finished Aug 05 04:22:44 PM PDT 24
Peak memory 164748 kb
Host smart-3d47417b-5c1e-41b2-9a2d-1a5ab0747131
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2894218731 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.2894218731
Directory /workspace/37.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.2400204063
Short name T126
Test name
Test status
Simulation time 1511210000 ps
CPU time 5.23 seconds
Started Aug 05 04:22:35 PM PDT 24
Finished Aug 05 04:22:47 PM PDT 24
Peak memory 164696 kb
Host smart-9f08bbe1-92c6-4fca-9c2a-9906ceede31e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2400204063 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.2400204063
Directory /workspace/38.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.1248953354
Short name T124
Test name
Test status
Simulation time 1602570000 ps
CPU time 3.98 seconds
Started Aug 05 04:22:28 PM PDT 24
Finished Aug 05 04:22:37 PM PDT 24
Peak memory 164664 kb
Host smart-76aa2d16-9f49-4aef-8f5e-49587120ab18
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1248953354 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.1248953354
Directory /workspace/39.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.1091263938
Short name T122
Test name
Test status
Simulation time 1581610000 ps
CPU time 5.62 seconds
Started Aug 05 04:22:11 PM PDT 24
Finished Aug 05 04:22:23 PM PDT 24
Peak memory 164716 kb
Host smart-b378cbe3-d202-4c29-b17a-9fdad8a8d824
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1091263938 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.1091263938
Directory /workspace/4.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.3488610911
Short name T132
Test name
Test status
Simulation time 1590150000 ps
CPU time 5.5 seconds
Started Aug 05 04:22:36 PM PDT 24
Finished Aug 05 04:22:49 PM PDT 24
Peak memory 164696 kb
Host smart-99b52561-0c1e-4234-b79c-ed4a94d8aedb
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3488610911 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.3488610911
Directory /workspace/40.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.704081145
Short name T111
Test name
Test status
Simulation time 1445030000 ps
CPU time 4.13 seconds
Started Aug 05 04:22:24 PM PDT 24
Finished Aug 05 04:22:33 PM PDT 24
Peak memory 164708 kb
Host smart-85c73cc8-17aa-436b-9781-0d7bc990b707
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=704081145 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.704081145
Directory /workspace/41.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.2909922752
Short name T136
Test name
Test status
Simulation time 1454830000 ps
CPU time 4.15 seconds
Started Aug 05 04:22:29 PM PDT 24
Finished Aug 05 04:22:38 PM PDT 24
Peak memory 164692 kb
Host smart-1eb5a34d-cef8-4ff7-9138-e060df07b376
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2909922752 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.2909922752
Directory /workspace/42.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.3994030412
Short name T156
Test name
Test status
Simulation time 1374450000 ps
CPU time 5.29 seconds
Started Aug 05 04:22:25 PM PDT 24
Finished Aug 05 04:22:36 PM PDT 24
Peak memory 164988 kb
Host smart-167ba4f7-122b-462e-a0fd-e01f27c96291
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3994030412 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.3994030412
Directory /workspace/43.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.2126389200
Short name T113
Test name
Test status
Simulation time 1524230000 ps
CPU time 3.99 seconds
Started Aug 05 04:22:43 PM PDT 24
Finished Aug 05 04:22:52 PM PDT 24
Peak memory 164696 kb
Host smart-5f10fe94-0fb9-46a9-9626-a86febafa1e8
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2126389200 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.2126389200
Directory /workspace/44.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.248056236
Short name T141
Test name
Test status
Simulation time 1358910000 ps
CPU time 4.17 seconds
Started Aug 05 04:22:33 PM PDT 24
Finished Aug 05 04:22:43 PM PDT 24
Peak memory 164724 kb
Host smart-4c17687c-c023-47df-b2f0-3078f9d07cad
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=248056236 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.248056236
Directory /workspace/45.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.719688544
Short name T128
Test name
Test status
Simulation time 1553630000 ps
CPU time 4.74 seconds
Started Aug 05 04:22:41 PM PDT 24
Finished Aug 05 04:22:51 PM PDT 24
Peak memory 164700 kb
Host smart-1418aa70-a400-4912-8fa4-48f93226db82
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=719688544 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.719688544
Directory /workspace/46.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.121738204
Short name T121
Test name
Test status
Simulation time 1519410000 ps
CPU time 3.85 seconds
Started Aug 05 04:22:31 PM PDT 24
Finished Aug 05 04:22:40 PM PDT 24
Peak memory 164668 kb
Host smart-899ae670-0a96-4698-8d41-4d4732d2d4bb
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=121738204 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.121738204
Directory /workspace/47.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.4131906910
Short name T153
Test name
Test status
Simulation time 1527090000 ps
CPU time 4.31 seconds
Started Aug 05 04:22:25 PM PDT 24
Finished Aug 05 04:22:35 PM PDT 24
Peak memory 164684 kb
Host smart-fa7c3ec7-55c6-4f1f-a495-d947f76cef76
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4131906910 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.4131906910
Directory /workspace/48.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.3005379029
Short name T112
Test name
Test status
Simulation time 1596490000 ps
CPU time 3.98 seconds
Started Aug 05 04:22:47 PM PDT 24
Finished Aug 05 04:22:56 PM PDT 24
Peak memory 164664 kb
Host smart-b621250b-8b60-4183-9522-6a63913fee87
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3005379029 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.3005379029
Directory /workspace/49.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.651106745
Short name T130
Test name
Test status
Simulation time 1343030000 ps
CPU time 3.19 seconds
Started Aug 05 04:22:19 PM PDT 24
Finished Aug 05 04:22:26 PM PDT 24
Peak memory 164748 kb
Host smart-cdf6b639-229e-4a26-a5e4-17d7f10fea39
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=651106745 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.651106745
Directory /workspace/5.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.2061417016
Short name T135
Test name
Test status
Simulation time 1530430000 ps
CPU time 5.59 seconds
Started Aug 05 04:22:14 PM PDT 24
Finished Aug 05 04:22:26 PM PDT 24
Peak memory 164712 kb
Host smart-08cfdffa-9dc2-47ec-81ac-95a54eed5d7a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2061417016 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.2061417016
Directory /workspace/6.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.4038587161
Short name T137
Test name
Test status
Simulation time 1491870000 ps
CPU time 4.75 seconds
Started Aug 05 04:22:15 PM PDT 24
Finished Aug 05 04:22:25 PM PDT 24
Peak memory 164280 kb
Host smart-f05b93d2-7d4f-4e03-ac91-2f8c1be5e4ed
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4038587161 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.4038587161
Directory /workspace/7.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1517052431
Short name T146
Test name
Test status
Simulation time 1502670000 ps
CPU time 4.17 seconds
Started Aug 05 04:23:14 PM PDT 24
Finished Aug 05 04:23:24 PM PDT 24
Peak memory 162532 kb
Host smart-1f74f9b0-fbb5-4ddc-b008-30d8cf3b9d41
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1517052431 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.1517052431
Directory /workspace/8.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.3705887622
Short name T160
Test name
Test status
Simulation time 1448470000 ps
CPU time 4.09 seconds
Started Aug 05 04:22:13 PM PDT 24
Finished Aug 05 04:22:22 PM PDT 24
Peak memory 164780 kb
Host smart-b302e1d7-e954-4df2-9911-44e79132c8f5
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3705887622 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.3705887622
Directory /workspace/9.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.596396892
Short name T42
Test name
Test status
Simulation time 1456250000 ps
CPU time 4.52 seconds
Started Aug 05 04:22:13 PM PDT 24
Finished Aug 05 04:22:23 PM PDT 24
Peak memory 164668 kb
Host smart-c015cbcf-ada3-4d09-b847-3fa2b3194362
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=596396892 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.596396892
Directory /workspace/0.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.3763184096
Short name T40
Test name
Test status
Simulation time 1518850000 ps
CPU time 4.58 seconds
Started Aug 05 04:22:13 PM PDT 24
Finished Aug 05 04:22:23 PM PDT 24
Peak memory 164476 kb
Host smart-0f443a26-082d-42d4-bb15-c33c4fd6b18a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3763184096 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.3763184096
Directory /workspace/1.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.1501939757
Short name T45
Test name
Test status
Simulation time 1563890000 ps
CPU time 2.99 seconds
Started Aug 05 04:22:01 PM PDT 24
Finished Aug 05 04:22:08 PM PDT 24
Peak memory 164392 kb
Host smart-57498dc9-f836-4c1d-90ad-fca6fc428072
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1501939757 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.1501939757
Directory /workspace/10.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.1950881541
Short name T55
Test name
Test status
Simulation time 1526830000 ps
CPU time 4.15 seconds
Started Aug 05 04:22:06 PM PDT 24
Finished Aug 05 04:22:15 PM PDT 24
Peak memory 164776 kb
Host smart-52112c54-0859-4750-b2c7-e29e4f25487c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1950881541 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.1950881541
Directory /workspace/11.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.94087229
Short name T46
Test name
Test status
Simulation time 1529730000 ps
CPU time 5.62 seconds
Started Aug 05 04:22:08 PM PDT 24
Finished Aug 05 04:22:20 PM PDT 24
Peak memory 164760 kb
Host smart-a6619703-7534-42b0-8cff-f8a080a726b4
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=94087229 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.94087229
Directory /workspace/12.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.3489250885
Short name T11
Test name
Test status
Simulation time 1608270000 ps
CPU time 4.84 seconds
Started Aug 05 04:22:16 PM PDT 24
Finished Aug 05 04:22:27 PM PDT 24
Peak memory 164308 kb
Host smart-89edced8-4c7f-4024-bdb2-51eb50028663
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3489250885 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.3489250885
Directory /workspace/13.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.178456203
Short name T47
Test name
Test status
Simulation time 1317550000 ps
CPU time 3.07 seconds
Started Aug 05 04:23:16 PM PDT 24
Finished Aug 05 04:23:24 PM PDT 24
Peak memory 162512 kb
Host smart-babfc34f-8e36-4d57-9696-a95cf72b9005
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=178456203 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.178456203
Directory /workspace/14.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.130926205
Short name T48
Test name
Test status
Simulation time 1440150000 ps
CPU time 2.95 seconds
Started Aug 05 04:23:47 PM PDT 24
Finished Aug 05 04:23:53 PM PDT 24
Peak memory 164456 kb
Host smart-93cf6b99-2007-4c9f-8314-385f9b5552e3
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=130926205 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.130926205
Directory /workspace/15.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.899641826
Short name T70
Test name
Test status
Simulation time 1519150000 ps
CPU time 4.33 seconds
Started Aug 05 04:23:43 PM PDT 24
Finished Aug 05 04:23:57 PM PDT 24
Peak memory 164440 kb
Host smart-81de031d-6d06-401a-aa7d-c5d363e70f46
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=899641826 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.899641826
Directory /workspace/16.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.2274835002
Short name T64
Test name
Test status
Simulation time 1597230000 ps
CPU time 3.56 seconds
Started Aug 05 04:22:02 PM PDT 24
Finished Aug 05 04:22:10 PM PDT 24
Peak memory 164160 kb
Host smart-fa332b6d-9e36-4db4-bdb5-6d44d536d121
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2274835002 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.2274835002
Directory /workspace/17.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.4174785348
Short name T50
Test name
Test status
Simulation time 1339610000 ps
CPU time 3 seconds
Started Aug 05 04:23:17 PM PDT 24
Finished Aug 05 04:23:24 PM PDT 24
Peak memory 162744 kb
Host smart-e7f5a660-b138-439d-a7de-747201345605
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4174785348 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.4174785348
Directory /workspace/18.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.1525641562
Short name T58
Test name
Test status
Simulation time 1514150000 ps
CPU time 4.49 seconds
Started Aug 05 04:22:16 PM PDT 24
Finished Aug 05 04:22:26 PM PDT 24
Peak memory 164348 kb
Host smart-3d8346a8-e7c4-453f-9470-7686d49dc28b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1525641562 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.1525641562
Directory /workspace/19.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.2803721868
Short name T33
Test name
Test status
Simulation time 1608190000 ps
CPU time 4.01 seconds
Started Aug 05 04:23:14 PM PDT 24
Finished Aug 05 04:23:23 PM PDT 24
Peak memory 164324 kb
Host smart-be0cbccd-15d6-4f27-969a-2e56d57fe267
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2803721868 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.2803721868
Directory /workspace/2.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.2169366310
Short name T66
Test name
Test status
Simulation time 1433810000 ps
CPU time 4.42 seconds
Started Aug 05 04:22:13 PM PDT 24
Finished Aug 05 04:22:23 PM PDT 24
Peak memory 164732 kb
Host smart-d34cf665-79dd-4e42-8659-a149c66f4301
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2169366310 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.2169366310
Directory /workspace/20.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.4258469627
Short name T35
Test name
Test status
Simulation time 1456870000 ps
CPU time 4.25 seconds
Started Aug 05 04:23:43 PM PDT 24
Finished Aug 05 04:24:00 PM PDT 24
Peak memory 164440 kb
Host smart-ca73a8d8-7209-41e1-9f1c-341a16b34096
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4258469627 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.4258469627
Directory /workspace/22.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.117500850
Short name T61
Test name
Test status
Simulation time 1123170000 ps
CPU time 3.39 seconds
Started Aug 05 04:23:42 PM PDT 24
Finished Aug 05 04:23:53 PM PDT 24
Peak memory 164440 kb
Host smart-c7f8cdd1-729a-419e-a7ef-9d51e273a04b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=117500850 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.117500850
Directory /workspace/23.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.78070213
Short name T65
Test name
Test status
Simulation time 1563490000 ps
CPU time 3.87 seconds
Started Aug 05 04:23:36 PM PDT 24
Finished Aug 05 04:23:45 PM PDT 24
Peak memory 164440 kb
Host smart-923a2fa7-1b8d-4b05-8c85-337c912cfbb4
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=78070213 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.78070213
Directory /workspace/24.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.1619186919
Short name T60
Test name
Test status
Simulation time 1545970000 ps
CPU time 4.32 seconds
Started Aug 05 04:23:38 PM PDT 24
Finished Aug 05 04:23:47 PM PDT 24
Peak memory 164436 kb
Host smart-7ca117e7-6d83-4323-a81a-c2149dded4b6
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1619186919 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.1619186919
Directory /workspace/25.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.1857787345
Short name T32
Test name
Test status
Simulation time 1327190000 ps
CPU time 3.67 seconds
Started Aug 05 04:23:20 PM PDT 24
Finished Aug 05 04:23:28 PM PDT 24
Peak memory 164280 kb
Host smart-b3f4a846-9e36-42ce-b5cb-b9791c0e5256
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1857787345 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.1857787345
Directory /workspace/26.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.2853347916
Short name T52
Test name
Test status
Simulation time 1490450000 ps
CPU time 4 seconds
Started Aug 05 04:23:16 PM PDT 24
Finished Aug 05 04:23:26 PM PDT 24
Peak memory 164280 kb
Host smart-9cf7c782-ea65-42c1-8430-46c6b250e32a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2853347916 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.2853347916
Directory /workspace/27.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.4186151445
Short name T59
Test name
Test status
Simulation time 1394890000 ps
CPU time 3.51 seconds
Started Aug 05 04:22:04 PM PDT 24
Finished Aug 05 04:22:12 PM PDT 24
Peak memory 164700 kb
Host smart-ed9153e6-cdf0-44fa-b49e-4938b535a699
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4186151445 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.4186151445
Directory /workspace/28.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.1124856961
Short name T54
Test name
Test status
Simulation time 1541490000 ps
CPU time 3.31 seconds
Started Aug 05 04:22:04 PM PDT 24
Finished Aug 05 04:22:12 PM PDT 24
Peak memory 164764 kb
Host smart-d9f72376-fc3f-4826-86fb-1fcd6e26e2fb
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1124856961 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.1124856961
Directory /workspace/29.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.2189036056
Short name T67
Test name
Test status
Simulation time 1369350000 ps
CPU time 4.04 seconds
Started Aug 05 04:22:13 PM PDT 24
Finished Aug 05 04:22:22 PM PDT 24
Peak memory 164664 kb
Host smart-716770a8-0efd-4d76-9477-68cfe52d7184
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2189036056 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.2189036056
Directory /workspace/3.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.791065256
Short name T68
Test name
Test status
Simulation time 1489690000 ps
CPU time 2.83 seconds
Started Aug 05 04:22:03 PM PDT 24
Finished Aug 05 04:22:10 PM PDT 24
Peak memory 164324 kb
Host smart-4ca2002a-14b3-4572-b2a2-5c5f9515deb1
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=791065256 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.791065256
Directory /workspace/30.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.2327216281
Short name T49
Test name
Test status
Simulation time 1388170000 ps
CPU time 3.98 seconds
Started Aug 05 04:23:20 PM PDT 24
Finished Aug 05 04:23:29 PM PDT 24
Peak memory 164280 kb
Host smart-9d306cca-559e-4eac-91d1-3d8b6ffe0c1b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2327216281 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.2327216281
Directory /workspace/31.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.1777409658
Short name T38
Test name
Test status
Simulation time 1543970000 ps
CPU time 4.47 seconds
Started Aug 05 04:23:47 PM PDT 24
Finished Aug 05 04:24:01 PM PDT 24
Peak memory 164436 kb
Host smart-58f6a54b-f222-408c-8e92-05c151e718cc
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1777409658 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.1777409658
Directory /workspace/32.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.1886797653
Short name T39
Test name
Test status
Simulation time 1497130000 ps
CPU time 5.26 seconds
Started Aug 05 04:22:03 PM PDT 24
Finished Aug 05 04:22:14 PM PDT 24
Peak memory 164972 kb
Host smart-417b885b-70fe-49d2-86c1-ea2e80d10c5b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1886797653 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.1886797653
Directory /workspace/33.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.1420409377
Short name T44
Test name
Test status
Simulation time 1234630000 ps
CPU time 3.55 seconds
Started Aug 05 04:22:16 PM PDT 24
Finished Aug 05 04:22:24 PM PDT 24
Peak memory 164348 kb
Host smart-fd61c9e5-b9cf-46dc-9ae0-90b050bc143c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1420409377 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.1420409377
Directory /workspace/34.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.100733270
Short name T3
Test name
Test status
Simulation time 1499510000 ps
CPU time 4.07 seconds
Started Aug 05 04:22:14 PM PDT 24
Finished Aug 05 04:22:23 PM PDT 24
Peak memory 164324 kb
Host smart-13aaa12c-80c4-4fc2-81cb-b727ce5d86b4
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=100733270 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.100733270
Directory /workspace/35.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.2673666422
Short name T2
Test name
Test status
Simulation time 1466270000 ps
CPU time 4.38 seconds
Started Aug 05 04:23:44 PM PDT 24
Finished Aug 05 04:23:57 PM PDT 24
Peak memory 164436 kb
Host smart-9596f414-27df-4666-9b0a-49e6b18a3513
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2673666422 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.2673666422
Directory /workspace/36.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.2253783977
Short name T62
Test name
Test status
Simulation time 1541510000 ps
CPU time 2.94 seconds
Started Aug 05 04:22:09 PM PDT 24
Finished Aug 05 04:22:15 PM PDT 24
Peak memory 164764 kb
Host smart-cbc114a3-5ad8-4815-8a63-b0976cc3b7c3
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2253783977 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.2253783977
Directory /workspace/37.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.3898318751
Short name T63
Test name
Test status
Simulation time 1432950000 ps
CPU time 3.87 seconds
Started Aug 05 04:22:15 PM PDT 24
Finished Aug 05 04:22:23 PM PDT 24
Peak memory 164780 kb
Host smart-95f742eb-fd1a-49de-bca2-763a25cd86a4
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3898318751 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.3898318751
Directory /workspace/38.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.3126888729
Short name T36
Test name
Test status
Simulation time 1219290000 ps
CPU time 3.89 seconds
Started Aug 05 04:22:13 PM PDT 24
Finished Aug 05 04:22:21 PM PDT 24
Peak memory 164800 kb
Host smart-372364ad-87dc-4c0c-869b-c2258cda4070
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3126888729 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.3126888729
Directory /workspace/39.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.961259538
Short name T37
Test name
Test status
Simulation time 1356190000 ps
CPU time 3.58 seconds
Started Aug 05 04:23:17 PM PDT 24
Finished Aug 05 04:23:25 PM PDT 24
Peak memory 164332 kb
Host smart-e4f9e44a-81fb-4155-bbed-fd2aa24828ce
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=961259538 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.961259538
Directory /workspace/4.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.1772952778
Short name T9
Test name
Test status
Simulation time 1486130000 ps
CPU time 4.45 seconds
Started Aug 05 04:22:14 PM PDT 24
Finished Aug 05 04:22:24 PM PDT 24
Peak memory 164696 kb
Host smart-60abb9b1-f37c-4652-8b74-958032f50fcc
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1772952778 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.1772952778
Directory /workspace/40.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.1175633075
Short name T12
Test name
Test status
Simulation time 1371030000 ps
CPU time 5.38 seconds
Started Aug 05 04:22:13 PM PDT 24
Finished Aug 05 04:22:25 PM PDT 24
Peak memory 164708 kb
Host smart-f22510be-e0db-4b82-8307-aaf83efa66f1
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1175633075 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.1175633075
Directory /workspace/41.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.3604363198
Short name T56
Test name
Test status
Simulation time 1619170000 ps
CPU time 4.44 seconds
Started Aug 05 04:22:12 PM PDT 24
Finished Aug 05 04:22:22 PM PDT 24
Peak memory 164704 kb
Host smart-84aad53b-6e05-4367-9923-b59445e3fc21
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3604363198 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.3604363198
Directory /workspace/42.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.479186987
Short name T69
Test name
Test status
Simulation time 1475210000 ps
CPU time 4.08 seconds
Started Aug 05 04:22:15 PM PDT 24
Finished Aug 05 04:22:24 PM PDT 24
Peak memory 164772 kb
Host smart-7d9ab1aa-8659-4fe8-93d0-1db281a210b4
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=479186987 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.479186987
Directory /workspace/43.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.3683243832
Short name T34
Test name
Test status
Simulation time 1453510000 ps
CPU time 4.27 seconds
Started Aug 05 04:22:14 PM PDT 24
Finished Aug 05 04:22:24 PM PDT 24
Peak memory 164708 kb
Host smart-0493cc5a-5ee3-4f4a-8351-13cd67acefb0
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3683243832 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.3683243832
Directory /workspace/44.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.208506756
Short name T10
Test name
Test status
Simulation time 1520890000 ps
CPU time 4.35 seconds
Started Aug 05 04:22:19 PM PDT 24
Finished Aug 05 04:22:29 PM PDT 24
Peak memory 164340 kb
Host smart-639a19e6-97c9-4e75-9476-0d4a87112801
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=208506756 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.208506756
Directory /workspace/45.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.655816841
Short name T41
Test name
Test status
Simulation time 1340190000 ps
CPU time 4.36 seconds
Started Aug 05 04:22:13 PM PDT 24
Finished Aug 05 04:22:22 PM PDT 24
Peak memory 164804 kb
Host smart-32e81862-f287-41f0-a7f6-10f279c947fd
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=655816841 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.655816841
Directory /workspace/46.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.4084475510
Short name T43
Test name
Test status
Simulation time 1444570000 ps
CPU time 4.23 seconds
Started Aug 05 04:23:14 PM PDT 24
Finished Aug 05 04:23:24 PM PDT 24
Peak memory 162368 kb
Host smart-bd4ff836-1b39-4f63-af84-9b610e1712af
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4084475510 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.4084475510
Directory /workspace/47.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.4128461139
Short name T31
Test name
Test status
Simulation time 1540670000 ps
CPU time 4.39 seconds
Started Aug 05 04:23:14 PM PDT 24
Finished Aug 05 04:23:24 PM PDT 24
Peak memory 162652 kb
Host smart-c068f0cc-6707-4b2e-b3cd-620d63f158f3
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4128461139 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.4128461139
Directory /workspace/48.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.3214631141
Short name T1
Test name
Test status
Simulation time 1342050000 ps
CPU time 4.53 seconds
Started Aug 05 04:22:12 PM PDT 24
Finished Aug 05 04:22:22 PM PDT 24
Peak memory 165028 kb
Host smart-e9f02e12-3f3a-4579-9811-35ddd15ca2d0
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3214631141 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.3214631141
Directory /workspace/49.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.1204622667
Short name T8
Test name
Test status
Simulation time 1088630000 ps
CPU time 2.75 seconds
Started Aug 05 04:23:16 PM PDT 24
Finished Aug 05 04:23:23 PM PDT 24
Peak memory 163136 kb
Host smart-88d9ef13-1919-4a7f-9eb5-b598bf9e1ad0
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1204622667 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.1204622667
Directory /workspace/5.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.3060998619
Short name T13
Test name
Test status
Simulation time 1566750000 ps
CPU time 3.36 seconds
Started Aug 05 04:22:04 PM PDT 24
Finished Aug 05 04:22:12 PM PDT 24
Peak memory 164696 kb
Host smart-6c33dee1-f772-47c5-82e1-99de75ca6c64
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3060998619 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.3060998619
Directory /workspace/6.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.1401030756
Short name T51
Test name
Test status
Simulation time 1483210000 ps
CPU time 4.4 seconds
Started Aug 05 04:22:16 PM PDT 24
Finished Aug 05 04:22:26 PM PDT 24
Peak memory 164244 kb
Host smart-999172a6-7dd3-4994-a4a9-7b4a3bc7503c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1401030756 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.1401030756
Directory /workspace/7.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.2044663250
Short name T53
Test name
Test status
Simulation time 1568870000 ps
CPU time 4.72 seconds
Started Aug 05 04:22:13 PM PDT 24
Finished Aug 05 04:22:24 PM PDT 24
Peak memory 164472 kb
Host smart-4cd87edc-7a03-4e9e-a7fe-db0a03188002
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2044663250 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.2044663250
Directory /workspace/8.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.276568860
Short name T57
Test name
Test status
Simulation time 1144050000 ps
CPU time 2.53 seconds
Started Aug 05 04:23:31 PM PDT 24
Finished Aug 05 04:23:36 PM PDT 24
Peak memory 164504 kb
Host smart-6363ab18-e779-4968-80cf-5c6b69ae3bdf
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=276568860 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.276568860
Directory /workspace/9.prim_lfsr_gal_smoke/latest
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