Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.31 100.00 96.55 100.00 100.00 95.00


Total tests in report: 200
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
87.31 87.31 100.00 100.00 96.55 96.55 100.00 100.00 100.00 100.00 40.00 40.00 /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.897359578
95.31 8.00 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 80.00 40.00 /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.3505547
98.31 3.00 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 95.00 15.00 /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.2804101475

Tests that do not contribute to grading

Name
/workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.1443503722
/workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.506026843
/workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.2380315060
/workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.1808813697
/workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.884950351
/workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.3862166919
/workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.1348672639
/workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.2599054777
/workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.1772500661
/workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.2777008082
/workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2222394819
/workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.2724761837
/workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.2515275720
/workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.1887505068
/workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.62449872
/workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.611441249
/workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.568070814
/workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.3801940996
/workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1970732929
/workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.3753497441
/workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.562243193
/workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.2160226544
/workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.3412018042
/workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3837633953
/workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.3136983130
/workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.3938072054
/workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.1461212045
/workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.1643497114
/workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.766364428
/workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.1015414218
/workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.3637053580
/workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.353785767
/workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.3630251688
/workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.3866451889
/workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.2593163256
/workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.1966601419
/workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.2311838288
/workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.1111139935
/workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.1924657937
/workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.3863751519
/workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.1428527492
/workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.176054924
/workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.592651338
/workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.2023183627
/workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.2128412853
/workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.1015614133
/workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.4276566509
/workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1800980051
/workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.4173344375
/workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.4109034413
/workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.2194958904
/workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.2433186952
/workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.996267445
/workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.3783344980
/workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.1598828126
/workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.4048468733
/workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.2445756774
/workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.3305339914
/workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.3709886036
/workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.3197496192
/workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.2121990193
/workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.445956584
/workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3938098495
/workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.699568815
/workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.2118176859
/workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.1478779152
/workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.1775386167
/workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.1034040144
/workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.836422743
/workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.1445352073
/workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.4204263683
/workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.1318465138
/workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.1966647473
/workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.2650684795
/workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.1010524688
/workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.2363640000
/workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.3877906589
/workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.255931027
/workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.3551010900
/workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.243479376
/workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.1118648720
/workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.184423968
/workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.390674853
/workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.265532969
/workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.2386639544
/workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.3512248676
/workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.1068602913
/workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.851346125
/workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.2037348978
/workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.2892516305
/workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.3760817116
/workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.3811567032
/workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.3202008946
/workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.720597280
/workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.4214788255
/workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.3694099385
/workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.764965389
/workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.451648208
/workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.4038512466
/workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.1622542780
/workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.4284852719
/workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.2787667135
/workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.2557800925
/workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.669936367
/workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.3804201534
/workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.889918292
/workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.1993150292
/workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.898517147
/workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.1230304300
/workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.3019375382
/workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.627690087
/workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.1840428011
/workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3487242995
/workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.4009822803
/workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.1574537859
/workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.2774379351
/workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.1994512289
/workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.518235464
/workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.453062250
/workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.1716770085
/workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.2052032247
/workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.3960049431
/workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.3833443982
/workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.1290251432
/workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.2740870639
/workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.3596510608
/workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.518966340
/workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.2598866817
/workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.2813071939
/workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.363100847
/workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.3376663104
/workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.3798657271
/workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3990704994
/workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.2371773968
/workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.1937832181
/workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.4022128619
/workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1694166619
/workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.980730607
/workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.3328443094
/workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.2660214107
/workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.4261785502
/workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.4037516713
/workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.1738048453
/workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.2093060270
/workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.754265190
/workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.48176216
/workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.33294083
/workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.3347754396
/workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.2664643450
/workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.3766711046
/workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.2941110350
/workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.2712156296
/workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.3814023814
/workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.2760702684
/workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.2384071252
/workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.1299805896
/workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.410382138
/workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.2531167960
/workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.536368962
/workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.1798229904
/workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.1404045602
/workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.3440252855
/workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.3584296345
/workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.848870722
/workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.621562916
/workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.997684708
/workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.3434179276
/workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.3769559006
/workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.3395385390
/workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.3382853323
/workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.3563728835
/workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.3783654284
/workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.2719257848
/workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.3394297491
/workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.2380726253
/workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.1998009915
/workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.1404408828
/workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.3066727259
/workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.3431092809
/workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.1164556196
/workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.752723556
/workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.3816093219
/workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.2590089363
/workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.330181342
/workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.1490932886
/workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.2566398999
/workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.2680542112
/workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.900622226
/workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.955325324
/workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.3853813740
/workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.3259201177
/workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.1142297665
/workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.3881363198
/workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.2936987279
/workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.2871452728
/workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.651370318
/workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.4175516105



Total test records in report: 200
tests.html | tests1.html | tests2.html | tests3.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.3382853323 Aug 07 04:22:23 PM PDT 24 Aug 07 04:22:34 PM PDT 24 1635050000 ps
T2 /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.3814023814 Aug 07 04:20:29 PM PDT 24 Aug 07 04:20:39 PM PDT 24 1491850000 ps
T3 /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.651370318 Aug 07 04:25:03 PM PDT 24 Aug 07 04:25:12 PM PDT 24 1495150000 ps
T4 /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.3431092809 Aug 07 04:24:19 PM PDT 24 Aug 07 04:24:28 PM PDT 24 1525790000 ps
T8 /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.1404408828 Aug 07 04:19:36 PM PDT 24 Aug 07 04:19:46 PM PDT 24 1620110000 ps
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T10 /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.1299805896 Aug 07 04:25:01 PM PDT 24 Aug 07 04:25:10 PM PDT 24 1533950000 ps
T11 /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.752723556 Aug 07 04:20:32 PM PDT 24 Aug 07 04:20:43 PM PDT 24 1543950000 ps
T12 /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.2664643450 Aug 07 04:24:05 PM PDT 24 Aug 07 04:24:13 PM PDT 24 1490990000 ps
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T32 /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.3816093219 Aug 07 04:24:05 PM PDT 24 Aug 07 04:24:14 PM PDT 24 1590010000 ps
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T34 /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.621562916 Aug 07 04:24:27 PM PDT 24 Aug 07 04:24:36 PM PDT 24 1428330000 ps
T35 /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.2680542112 Aug 07 04:20:54 PM PDT 24 Aug 07 04:21:02 PM PDT 24 1009150000 ps
T36 /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.2941110350 Aug 07 04:24:19 PM PDT 24 Aug 07 04:24:27 PM PDT 24 1578510000 ps
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T38 /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.3853813740 Aug 07 04:19:43 PM PDT 24 Aug 07 04:19:51 PM PDT 24 1530830000 ps
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T40 /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.900622226 Aug 07 04:24:50 PM PDT 24 Aug 07 04:25:00 PM PDT 24 1393830000 ps
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T44 /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.3395385390 Aug 07 04:20:44 PM PDT 24 Aug 07 04:20:51 PM PDT 24 1524650000 ps
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T49 /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.3783654284 Aug 07 04:24:47 PM PDT 24 Aug 07 04:24:56 PM PDT 24 1415930000 ps
T50 /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.2719257848 Aug 07 04:20:44 PM PDT 24 Aug 07 04:20:52 PM PDT 24 1081290000 ps
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T52 /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.1998009915 Aug 07 04:24:56 PM PDT 24 Aug 07 04:25:05 PM PDT 24 1453490000 ps
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T55 /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.3881363198 Aug 07 04:25:00 PM PDT 24 Aug 07 04:25:06 PM PDT 24 1366650000 ps
T56 /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.4175516105 Aug 07 04:25:00 PM PDT 24 Aug 07 04:25:09 PM PDT 24 1396010000 ps
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T58 /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.330181342 Aug 07 04:20:41 PM PDT 24 Aug 07 04:20:52 PM PDT 24 1556330000 ps
T59 /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.536368962 Aug 07 04:24:24 PM PDT 24 Aug 07 04:24:32 PM PDT 24 1439310000 ps
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T64 /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.2380726253 Aug 07 04:25:00 PM PDT 24 Aug 07 04:25:09 PM PDT 24 1511810000 ps
T65 /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.1798229904 Aug 07 04:24:24 PM PDT 24 Aug 07 04:24:32 PM PDT 24 1399750000 ps
T66 /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.3584296345 Aug 07 04:19:38 PM PDT 24 Aug 07 04:19:45 PM PDT 24 1509150000 ps
T67 /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.2760702684 Aug 07 04:19:52 PM PDT 24 Aug 07 04:20:03 PM PDT 24 1592570000 ps
T68 /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.3440252855 Aug 07 04:24:23 PM PDT 24 Aug 07 04:24:31 PM PDT 24 1451930000 ps
T69 /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.2590089363 Aug 07 04:24:55 PM PDT 24 Aug 07 04:25:05 PM PDT 24 1409970000 ps
T70 /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.3259201177 Aug 07 04:20:29 PM PDT 24 Aug 07 04:20:38 PM PDT 24 1471010000 ps
T14 /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.4204263683 Aug 07 04:20:39 PM PDT 24 Aug 07 04:54:07 PM PDT 24 336321830000 ps
T15 /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.4048468733 Aug 07 04:21:54 PM PDT 24 Aug 07 04:56:16 PM PDT 24 336807170000 ps
T16 /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.2386639544 Aug 07 04:19:19 PM PDT 24 Aug 07 04:46:10 PM PDT 24 337116710000 ps
T17 /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.2363640000 Aug 07 04:24:50 PM PDT 24 Aug 07 04:56:48 PM PDT 24 336376530000 ps
T18 /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.2650684795 Aug 07 04:20:44 PM PDT 24 Aug 07 04:52:04 PM PDT 24 336607890000 ps
T19 /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.3305339914 Aug 07 04:22:47 PM PDT 24 Aug 07 04:54:46 PM PDT 24 336743550000 ps
T20 /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.445956584 Aug 07 04:24:25 PM PDT 24 Aug 07 04:57:48 PM PDT 24 337004890000 ps
T21 /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.3811567032 Aug 07 04:24:15 PM PDT 24 Aug 07 04:54:18 PM PDT 24 336723110000 ps
T22 /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.3505547 Aug 07 04:21:06 PM PDT 24 Aug 07 04:54:49 PM PDT 24 336982130000 ps
T23 /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.1068602913 Aug 07 04:23:33 PM PDT 24 Aug 07 05:03:19 PM PDT 24 336720790000 ps
T71 /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.255931027 Aug 07 04:20:32 PM PDT 24 Aug 07 04:55:21 PM PDT 24 336820250000 ps
T72 /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.4214788255 Aug 07 04:24:26 PM PDT 24 Aug 07 04:53:23 PM PDT 24 336505410000 ps
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T74 /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.3512248676 Aug 07 04:23:34 PM PDT 24 Aug 07 05:03:13 PM PDT 24 336405890000 ps
T75 /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.265532969 Aug 07 04:25:26 PM PDT 24 Aug 07 04:56:34 PM PDT 24 336834850000 ps
T76 /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.1010524688 Aug 07 04:24:43 PM PDT 24 Aug 07 04:49:46 PM PDT 24 336469830000 ps
T77 /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.720597280 Aug 07 04:22:46 PM PDT 24 Aug 07 04:55:48 PM PDT 24 336771290000 ps
T78 /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.1478779152 Aug 07 04:24:06 PM PDT 24 Aug 07 04:53:06 PM PDT 24 336871090000 ps
T79 /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.1775386167 Aug 07 04:21:28 PM PDT 24 Aug 07 05:00:52 PM PDT 24 336695790000 ps
T80 /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.1598828126 Aug 07 04:24:01 PM PDT 24 Aug 07 04:49:08 PM PDT 24 336914090000 ps
T81 /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.2445756774 Aug 07 04:24:21 PM PDT 24 Aug 07 04:49:01 PM PDT 24 336462650000 ps
T82 /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.1118648720 Aug 07 04:25:26 PM PDT 24 Aug 07 04:56:20 PM PDT 24 336727670000 ps
T83 /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.3783344980 Aug 07 04:24:20 PM PDT 24 Aug 07 04:50:32 PM PDT 24 336799350000 ps
T84 /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.764965389 Aug 07 04:24:09 PM PDT 24 Aug 07 05:02:46 PM PDT 24 337092170000 ps
T85 /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.2121990193 Aug 07 04:20:55 PM PDT 24 Aug 07 04:56:56 PM PDT 24 336601770000 ps
T86 /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.390674853 Aug 07 04:24:11 PM PDT 24 Aug 07 05:02:31 PM PDT 24 336649390000 ps
T87 /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.2194958904 Aug 07 04:20:30 PM PDT 24 Aug 07 04:52:10 PM PDT 24 336363530000 ps
T88 /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.3709886036 Aug 07 04:24:08 PM PDT 24 Aug 07 04:54:40 PM PDT 24 336573450000 ps
T89 /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.2118176859 Aug 07 04:24:09 PM PDT 24 Aug 07 04:50:32 PM PDT 24 336701610000 ps
T90 /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.996267445 Aug 07 04:20:58 PM PDT 24 Aug 07 04:52:34 PM PDT 24 336346230000 ps
T91 /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.3551010900 Aug 07 04:20:30 PM PDT 24 Aug 07 04:54:11 PM PDT 24 336428630000 ps
T92 /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.1318465138 Aug 07 04:19:19 PM PDT 24 Aug 07 04:46:06 PM PDT 24 337125270000 ps
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T94 /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.1966647473 Aug 07 04:20:01 PM PDT 24 Aug 07 04:49:18 PM PDT 24 336779430000 ps
T95 /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.851346125 Aug 07 04:20:30 PM PDT 24 Aug 07 04:52:41 PM PDT 24 336626330000 ps
T96 /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.451648208 Aug 07 04:24:09 PM PDT 24 Aug 07 05:02:26 PM PDT 24 337003210000 ps
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T98 /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.243479376 Aug 07 04:20:26 PM PDT 24 Aug 07 04:54:26 PM PDT 24 337119450000 ps
T99 /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.3202008946 Aug 07 04:23:34 PM PDT 24 Aug 07 04:56:57 PM PDT 24 336599730000 ps
T100 /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.3694099385 Aug 07 04:24:10 PM PDT 24 Aug 07 05:02:17 PM PDT 24 336919830000 ps
T101 /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.1034040144 Aug 07 04:20:41 PM PDT 24 Aug 07 04:51:28 PM PDT 24 336669110000 ps
T102 /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.2433186952 Aug 07 04:24:50 PM PDT 24 Aug 07 04:54:50 PM PDT 24 336945150000 ps
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T104 /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.2892516305 Aug 07 04:25:00 PM PDT 24 Aug 07 04:53:58 PM PDT 24 336584450000 ps
T105 /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.699568815 Aug 07 04:19:41 PM PDT 24 Aug 07 04:51:28 PM PDT 24 336617530000 ps
T106 /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.2037348978 Aug 07 04:23:26 PM PDT 24 Aug 07 04:57:54 PM PDT 24 336946090000 ps
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T108 /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.3197496192 Aug 07 04:24:17 PM PDT 24 Aug 07 04:50:03 PM PDT 24 337058210000 ps
T109 /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.3877906589 Aug 07 04:19:43 PM PDT 24 Aug 07 04:53:02 PM PDT 24 337009870000 ps
T110 /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3938098495 Aug 07 04:24:25 PM PDT 24 Aug 07 04:57:40 PM PDT 24 336927730000 ps
T5 /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.3630251688 Aug 07 04:20:56 PM PDT 24 Aug 07 04:56:50 PM PDT 24 336815010000 ps
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T7 /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1970732929 Aug 07 04:20:32 PM PDT 24 Aug 07 04:54:22 PM PDT 24 337007650000 ps
T24 /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.2380315060 Aug 07 04:23:10 PM PDT 24 Aug 07 04:54:10 PM PDT 24 337036470000 ps
T25 /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.592651338 Aug 07 04:24:14 PM PDT 24 Aug 07 04:55:03 PM PDT 24 336399890000 ps
T26 /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.3801940996 Aug 07 04:20:25 PM PDT 24 Aug 07 04:52:56 PM PDT 24 336612730000 ps
T27 /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.884950351 Aug 07 04:23:10 PM PDT 24 Aug 07 04:57:54 PM PDT 24 336393590000 ps
T28 /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.2804101475 Aug 07 04:24:41 PM PDT 24 Aug 07 04:54:36 PM PDT 24 336314190000 ps
T29 /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.353785767 Aug 07 04:20:36 PM PDT 24 Aug 07 04:59:54 PM PDT 24 336414850000 ps
T30 /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.766364428 Aug 07 04:19:41 PM PDT 24 Aug 07 04:51:22 PM PDT 24 337128610000 ps
T111 /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.3637053580 Aug 07 04:24:33 PM PDT 24 Aug 07 04:56:21 PM PDT 24 336626070000 ps
T112 /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.3412018042 Aug 07 04:25:00 PM PDT 24 Aug 07 04:50:18 PM PDT 24 336378190000 ps
T113 /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.1111139935 Aug 07 04:19:59 PM PDT 24 Aug 07 04:44:48 PM PDT 24 336705170000 ps
T114 /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.1643497114 Aug 07 04:19:43 PM PDT 24 Aug 07 04:54:33 PM PDT 24 337086870000 ps
T115 /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.2311838288 Aug 07 04:20:44 PM PDT 24 Aug 07 04:51:26 PM PDT 24 336911870000 ps
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T117 /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.3136983130 Aug 07 04:21:50 PM PDT 24 Aug 07 04:56:55 PM PDT 24 336781730000 ps
T118 /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.611441249 Aug 07 04:19:36 PM PDT 24 Aug 07 04:51:21 PM PDT 24 336698230000 ps
T119 /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.2724761837 Aug 07 04:19:30 PM PDT 24 Aug 07 04:52:43 PM PDT 24 336978290000 ps
T120 /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.176054924 Aug 07 04:22:36 PM PDT 24 Aug 07 04:56:00 PM PDT 24 336287770000 ps
T121 /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.506026843 Aug 07 04:20:36 PM PDT 24 Aug 07 04:56:01 PM PDT 24 336356310000 ps
T122 /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.2777008082 Aug 07 04:22:25 PM PDT 24 Aug 07 04:56:08 PM PDT 24 336980450000 ps
T123 /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.1887505068 Aug 07 04:24:24 PM PDT 24 Aug 07 04:57:12 PM PDT 24 336995890000 ps
T124 /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.2515275720 Aug 07 04:22:52 PM PDT 24 Aug 07 04:51:23 PM PDT 24 336430350000 ps
T125 /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.3753497441 Aug 07 04:22:39 PM PDT 24 Aug 07 04:56:15 PM PDT 24 337005550000 ps
T126 /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.3938072054 Aug 07 04:24:34 PM PDT 24 Aug 07 04:56:47 PM PDT 24 337136810000 ps
T127 /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.4276566509 Aug 07 04:24:24 PM PDT 24 Aug 07 04:51:46 PM PDT 24 336646750000 ps
T128 /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.2593163256 Aug 07 04:21:42 PM PDT 24 Aug 07 04:56:37 PM PDT 24 336751190000 ps
T129 /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.1428527492 Aug 07 04:22:35 PM PDT 24 Aug 07 04:54:11 PM PDT 24 336554490000 ps
T130 /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.1443503722 Aug 07 04:24:20 PM PDT 24 Aug 07 04:53:49 PM PDT 24 336414990000 ps
T131 /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.562243193 Aug 07 04:24:55 PM PDT 24 Aug 07 04:56:27 PM PDT 24 336311850000 ps
T132 /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.568070814 Aug 07 04:19:37 PM PDT 24 Aug 07 04:49:46 PM PDT 24 337071810000 ps
T133 /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2222394819 Aug 07 04:20:55 PM PDT 24 Aug 07 04:52:08 PM PDT 24 336625670000 ps
T134 /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.2599054777 Aug 07 04:24:07 PM PDT 24 Aug 07 04:49:37 PM PDT 24 336395330000 ps
T135 /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.1808813697 Aug 07 04:24:50 PM PDT 24 Aug 07 04:54:51 PM PDT 24 336854050000 ps
T136 /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.1966601419 Aug 07 04:19:44 PM PDT 24 Aug 07 04:51:10 PM PDT 24 336654850000 ps
T137 /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.4173344375 Aug 07 04:24:39 PM PDT 24 Aug 07 04:54:54 PM PDT 24 336759970000 ps
T138 /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.2128412853 Aug 07 04:24:23 PM PDT 24 Aug 07 05:03:11 PM PDT 24 336755550000 ps
T139 /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.2160226544 Aug 07 04:19:35 PM PDT 24 Aug 07 04:49:35 PM PDT 24 336994930000 ps
T140 /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.1348672639 Aug 07 04:20:20 PM PDT 24 Aug 07 04:49:11 PM PDT 24 336766290000 ps
T141 /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.3862166919 Aug 07 04:20:36 PM PDT 24 Aug 07 04:58:48 PM PDT 24 336401410000 ps
T142 /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3837633953 Aug 07 04:24:55 PM PDT 24 Aug 07 04:56:18 PM PDT 24 336697970000 ps
T143 /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.1461212045 Aug 07 04:20:55 PM PDT 24 Aug 07 04:57:05 PM PDT 24 336956330000 ps
T144 /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1800980051 Aug 07 04:25:00 PM PDT 24 Aug 07 04:52:35 PM PDT 24 336416950000 ps
T145 /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.1772500661 Aug 07 04:24:31 PM PDT 24 Aug 07 04:48:17 PM PDT 24 336487370000 ps
T146 /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.1015414218 Aug 07 04:22:27 PM PDT 24 Aug 07 04:56:10 PM PDT 24 336987730000 ps
T147 /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.1015614133 Aug 07 04:21:08 PM PDT 24 Aug 07 04:55:11 PM PDT 24 336411410000 ps
T148 /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.1924657937 Aug 07 04:24:15 PM PDT 24 Aug 07 04:54:45 PM PDT 24 336799950000 ps
T149 /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.3866451889 Aug 07 04:24:24 PM PDT 24 Aug 07 04:54:12 PM PDT 24 336422930000 ps
T150 /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.62449872 Aug 07 04:19:36 PM PDT 24 Aug 07 04:54:47 PM PDT 24 336573550000 ps
T151 /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.518235464 Aug 07 04:24:55 PM PDT 24 Aug 07 04:25:04 PM PDT 24 1487310000 ps
T152 /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.669936367 Aug 07 04:24:26 PM PDT 24 Aug 07 04:24:34 PM PDT 24 1361270000 ps
T153 /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.2813071939 Aug 07 04:24:06 PM PDT 24 Aug 07 04:24:18 PM PDT 24 1554970000 ps
T154 /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.1716770085 Aug 07 04:24:47 PM PDT 24 Aug 07 04:24:55 PM PDT 24 1398710000 ps
T155 /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.1994512289 Aug 07 04:19:44 PM PDT 24 Aug 07 04:19:51 PM PDT 24 1249070000 ps
T156 /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.2774379351 Aug 07 04:25:36 PM PDT 24 Aug 07 04:25:47 PM PDT 24 1529210000 ps
T157 /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.363100847 Aug 07 04:20:41 PM PDT 24 Aug 07 04:20:49 PM PDT 24 1397790000 ps
T158 /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.1993150292 Aug 07 04:24:55 PM PDT 24 Aug 07 04:25:08 PM PDT 24 1588130000 ps
T159 /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1694166619 Aug 07 04:24:55 PM PDT 24 Aug 07 04:25:04 PM PDT 24 1495250000 ps
T160 /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.3328443094 Aug 07 04:24:23 PM PDT 24 Aug 07 04:24:32 PM PDT 24 1587070000 ps
T161 /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.3804201534 Aug 07 04:24:26 PM PDT 24 Aug 07 04:24:36 PM PDT 24 1553710000 ps
T162 /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.2093060270 Aug 07 04:24:27 PM PDT 24 Aug 07 04:24:36 PM PDT 24 1443770000 ps
T163 /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.3798657271 Aug 07 04:24:06 PM PDT 24 Aug 07 04:24:16 PM PDT 24 1231450000 ps
T164 /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.754265190 Aug 07 04:24:09 PM PDT 24 Aug 07 04:24:17 PM PDT 24 1405630000 ps
T165 /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.980730607 Aug 07 04:23:15 PM PDT 24 Aug 07 04:23:26 PM PDT 24 1349030000 ps
T166 /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.2052032247 Aug 07 04:22:06 PM PDT 24 Aug 07 04:22:16 PM PDT 24 1572530000 ps
T167 /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.2787667135 Aug 07 04:24:31 PM PDT 24 Aug 07 04:24:39 PM PDT 24 1570350000 ps
T168 /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.3833443982 Aug 07 04:19:35 PM PDT 24 Aug 07 04:19:42 PM PDT 24 1126530000 ps
T169 /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.48176216 Aug 07 04:21:05 PM PDT 24 Aug 07 04:21:14 PM PDT 24 1481610000 ps
T170 /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.4038512466 Aug 07 04:22:47 PM PDT 24 Aug 07 04:22:58 PM PDT 24 1527710000 ps
T171 /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.3376663104 Aug 07 04:19:42 PM PDT 24 Aug 07 04:19:51 PM PDT 24 1477390000 ps
T172 /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.1290251432 Aug 07 04:23:23 PM PDT 24 Aug 07 04:23:33 PM PDT 24 1517730000 ps
T173 /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.33294083 Aug 07 04:22:53 PM PDT 24 Aug 07 04:23:01 PM PDT 24 1319350000 ps
T174 /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.453062250 Aug 07 04:21:55 PM PDT 24 Aug 07 04:22:05 PM PDT 24 1619390000 ps
T175 /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.4037516713 Aug 07 04:24:23 PM PDT 24 Aug 07 04:24:31 PM PDT 24 1485090000 ps
T176 /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.1937832181 Aug 07 04:24:49 PM PDT 24 Aug 07 04:24:55 PM PDT 24 1329430000 ps
T177 /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.1840428011 Aug 07 04:20:42 PM PDT 24 Aug 07 04:20:50 PM PDT 24 1450210000 ps
T178 /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.1622542780 Aug 07 04:20:18 PM PDT 24 Aug 07 04:20:27 PM PDT 24 1418530000 ps
T179 /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.2598866817 Aug 07 04:21:38 PM PDT 24 Aug 07 04:21:50 PM PDT 24 1507910000 ps
T180 /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.4022128619 Aug 07 04:24:48 PM PDT 24 Aug 07 04:24:56 PM PDT 24 1534550000 ps
T181 /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.3960049431 Aug 07 04:25:03 PM PDT 24 Aug 07 04:25:11 PM PDT 24 1392390000 ps
T182 /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.3347754396 Aug 07 04:24:06 PM PDT 24 Aug 07 04:24:18 PM PDT 24 1516170000 ps
T183 /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.627690087 Aug 07 04:24:55 PM PDT 24 Aug 07 04:25:05 PM PDT 24 1341370000 ps
T184 /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.898517147 Aug 07 04:24:55 PM PDT 24 Aug 07 04:25:07 PM PDT 24 1532390000 ps
T185 /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.3019375382 Aug 07 04:22:11 PM PDT 24 Aug 07 04:22:19 PM PDT 24 1130790000 ps
T186 /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3990704994 Aug 07 04:21:44 PM PDT 24 Aug 07 04:21:54 PM PDT 24 1494750000 ps
T187 /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.1230304300 Aug 07 04:22:17 PM PDT 24 Aug 07 04:22:26 PM PDT 24 1385890000 ps
T188 /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.3596510608 Aug 07 04:23:30 PM PDT 24 Aug 07 04:23:41 PM PDT 24 1547350000 ps
T189 /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.1738048453 Aug 07 04:24:36 PM PDT 24 Aug 07 04:24:44 PM PDT 24 1575490000 ps
T190 /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.4009822803 Aug 07 04:23:21 PM PDT 24 Aug 07 04:23:32 PM PDT 24 1630410000 ps
T191 /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.2371773968 Aug 07 04:24:49 PM PDT 24 Aug 07 04:24:55 PM PDT 24 1420710000 ps
T192 /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.2660214107 Aug 07 04:24:55 PM PDT 24 Aug 07 04:25:05 PM PDT 24 1607350000 ps
T193 /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.889918292 Aug 07 04:22:15 PM PDT 24 Aug 07 04:22:23 PM PDT 24 936770000 ps
T194 /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.518966340 Aug 07 04:21:38 PM PDT 24 Aug 07 04:21:50 PM PDT 24 1485190000 ps
T195 /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.4261785502 Aug 07 04:24:55 PM PDT 24 Aug 07 04:25:07 PM PDT 24 1437110000 ps
T196 /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.2740870639 Aug 07 04:24:55 PM PDT 24 Aug 07 04:25:07 PM PDT 24 1455050000 ps
T197 /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.4284852719 Aug 07 04:24:46 PM PDT 24 Aug 07 04:24:54 PM PDT 24 1347670000 ps
T198 /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3487242995 Aug 07 04:25:00 PM PDT 24 Aug 07 04:25:10 PM PDT 24 1542590000 ps
T199 /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.1574537859 Aug 07 04:22:40 PM PDT 24 Aug 07 04:22:49 PM PDT 24 1460590000 ps
T200 /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.2557800925 Aug 07 04:24:56 PM PDT 24 Aug 07 04:25:05 PM PDT 24 1500390000 ps

Test location /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.897359578
Short name T13
Test name
Test status
Simulation time 1591650000 ps
CPU time 5.42 seconds
Started Aug 07 04:24:37 PM PDT 24
Finished Aug 07 04:24:49 PM PDT 24
Peak memory 164724 kb
Host smart-bc295078-cb67-4331-bdb2-7e56bc9da95f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=897359578 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.897359578
Directory /workspace/0.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.3505547
Short name T22
Test name
Test status
Simulation time 336982130000 ps
CPU time 815.21 seconds
Started Aug 07 04:21:06 PM PDT 24
Finished Aug 07 04:54:49 PM PDT 24
Peak memory 160596 kb
Host smart-94220a73-099e-4cbe-8263-0a64e602fe72
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3505547 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.3505547
Directory /workspace/10.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.2804101475
Short name T28
Test name
Test status
Simulation time 336314190000 ps
CPU time 726.04 seconds
Started Aug 07 04:24:41 PM PDT 24
Finished Aug 07 04:54:36 PM PDT 24
Peak memory 160624 kb
Host smart-ab42ab9d-e412-4090-aa9b-543474670a39
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2804101475 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.2804101475
Directory /workspace/10.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.1443503722
Short name T130
Test name
Test status
Simulation time 336414990000 ps
CPU time 719.38 seconds
Started Aug 07 04:24:20 PM PDT 24
Finished Aug 07 04:53:49 PM PDT 24
Peak memory 160616 kb
Host smart-922faff6-10a0-4e91-b624-e063989dddb6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1443503722 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.1443503722
Directory /workspace/0.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.506026843
Short name T121
Test name
Test status
Simulation time 336356310000 ps
CPU time 877.63 seconds
Started Aug 07 04:20:36 PM PDT 24
Finished Aug 07 04:56:01 PM PDT 24
Peak memory 160660 kb
Host smart-7c832547-0a31-4eb6-ab90-92b15fec6c33
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=506026843 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.506026843
Directory /workspace/1.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.2380315060
Short name T24
Test name
Test status
Simulation time 337036470000 ps
CPU time 755.83 seconds
Started Aug 07 04:23:10 PM PDT 24
Finished Aug 07 04:54:10 PM PDT 24
Peak memory 160628 kb
Host smart-7aef9c83-d280-4f1c-b567-c554a58b522d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2380315060 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.2380315060
Directory /workspace/11.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.1808813697
Short name T135
Test name
Test status
Simulation time 336854050000 ps
CPU time 731.13 seconds
Started Aug 07 04:24:50 PM PDT 24
Finished Aug 07 04:54:51 PM PDT 24
Peak memory 160620 kb
Host smart-2a287108-bb14-49e8-86fe-6894cf6e858d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1808813697 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.1808813697
Directory /workspace/12.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.884950351
Short name T27
Test name
Test status
Simulation time 336393590000 ps
CPU time 843.14 seconds
Started Aug 07 04:23:10 PM PDT 24
Finished Aug 07 04:57:54 PM PDT 24
Peak memory 160628 kb
Host smart-4ee72622-9c80-45d7-9719-64a2e395fa28
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=884950351 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.884950351
Directory /workspace/13.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.3862166919
Short name T141
Test name
Test status
Simulation time 336401410000 ps
CPU time 913.85 seconds
Started Aug 07 04:20:36 PM PDT 24
Finished Aug 07 04:58:48 PM PDT 24
Peak memory 160688 kb
Host smart-a0d2c0a3-ddf2-4da4-83f5-9005748d2986
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3862166919 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.3862166919
Directory /workspace/14.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.1348672639
Short name T140
Test name
Test status
Simulation time 336766290000 ps
CPU time 697.77 seconds
Started Aug 07 04:20:20 PM PDT 24
Finished Aug 07 04:49:11 PM PDT 24
Peak memory 160668 kb
Host smart-ab7c4dc8-dec2-4e94-bc6d-0a76a997a98d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1348672639 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.1348672639
Directory /workspace/15.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.2599054777
Short name T134
Test name
Test status
Simulation time 336395330000 ps
CPU time 614.72 seconds
Started Aug 07 04:24:07 PM PDT 24
Finished Aug 07 04:49:37 PM PDT 24
Peak memory 159764 kb
Host smart-1ab98354-341b-4e50-a751-02161211ea00
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2599054777 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.2599054777
Directory /workspace/16.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.1772500661
Short name T145
Test name
Test status
Simulation time 336487370000 ps
CPU time 578.47 seconds
Started Aug 07 04:24:31 PM PDT 24
Finished Aug 07 04:48:17 PM PDT 24
Peak memory 159748 kb
Host smart-2d3e855c-4e9e-4a55-b630-967a52a2b96f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1772500661 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.1772500661
Directory /workspace/17.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.2777008082
Short name T122
Test name
Test status
Simulation time 336980450000 ps
CPU time 833.18 seconds
Started Aug 07 04:22:25 PM PDT 24
Finished Aug 07 04:56:08 PM PDT 24
Peak memory 160672 kb
Host smart-c3f71ff0-8b5f-4c0f-acca-bc0fc3a21c84
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2777008082 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.2777008082
Directory /workspace/18.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2222394819
Short name T133
Test name
Test status
Simulation time 336625670000 ps
CPU time 760.38 seconds
Started Aug 07 04:20:55 PM PDT 24
Finished Aug 07 04:52:08 PM PDT 24
Peak memory 160632 kb
Host smart-8119e8f7-43dc-40d8-85d0-150641042bdb
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2222394819 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.2222394819
Directory /workspace/19.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.2724761837
Short name T119
Test name
Test status
Simulation time 336978290000 ps
CPU time 818.55 seconds
Started Aug 07 04:19:30 PM PDT 24
Finished Aug 07 04:52:43 PM PDT 24
Peak memory 160660 kb
Host smart-a047ad16-0f6a-43bd-956a-6a60db3ba2eb
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2724761837 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.2724761837
Directory /workspace/2.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.2515275720
Short name T124
Test name
Test status
Simulation time 336430350000 ps
CPU time 692.22 seconds
Started Aug 07 04:22:52 PM PDT 24
Finished Aug 07 04:51:23 PM PDT 24
Peak memory 160632 kb
Host smart-d80e81d9-784b-453f-85ea-e6fac41e4d20
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2515275720 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.2515275720
Directory /workspace/20.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.1887505068
Short name T123
Test name
Test status
Simulation time 336995890000 ps
CPU time 804.85 seconds
Started Aug 07 04:24:24 PM PDT 24
Finished Aug 07 04:57:12 PM PDT 24
Peak memory 160260 kb
Host smart-553bbb80-f878-4caa-9bfc-01c81699f266
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1887505068 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.1887505068
Directory /workspace/21.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.62449872
Short name T150
Test name
Test status
Simulation time 336573550000 ps
CPU time 857.3 seconds
Started Aug 07 04:19:36 PM PDT 24
Finished Aug 07 04:54:47 PM PDT 24
Peak memory 160640 kb
Host smart-930484d3-3fde-4e90-b9fb-af79d32afdb4
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=62449872 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.62449872
Directory /workspace/22.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.611441249
Short name T118
Test name
Test status
Simulation time 336698230000 ps
CPU time 777.05 seconds
Started Aug 07 04:19:36 PM PDT 24
Finished Aug 07 04:51:21 PM PDT 24
Peak memory 160668 kb
Host smart-2959d9a6-6bc7-4be3-a6d6-9ceb1b6a4b92
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=611441249 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.611441249
Directory /workspace/23.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.568070814
Short name T132
Test name
Test status
Simulation time 337071810000 ps
CPU time 737.44 seconds
Started Aug 07 04:19:37 PM PDT 24
Finished Aug 07 04:49:46 PM PDT 24
Peak memory 160636 kb
Host smart-4ed33775-2d2e-4065-8053-118c8876c245
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=568070814 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.568070814
Directory /workspace/24.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.3801940996
Short name T26
Test name
Test status
Simulation time 336612730000 ps
CPU time 802.98 seconds
Started Aug 07 04:20:25 PM PDT 24
Finished Aug 07 04:52:56 PM PDT 24
Peak memory 160680 kb
Host smart-7f3c498b-3b6b-4771-a3af-4c0afcab374f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3801940996 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.3801940996
Directory /workspace/25.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1970732929
Short name T7
Test name
Test status
Simulation time 337007650000 ps
CPU time 828.49 seconds
Started Aug 07 04:20:32 PM PDT 24
Finished Aug 07 04:54:22 PM PDT 24
Peak memory 160896 kb
Host smart-4cccdf01-a24e-49f9-856e-bfd06d4db68b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1970732929 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.1970732929
Directory /workspace/26.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.3753497441
Short name T125
Test name
Test status
Simulation time 337005550000 ps
CPU time 821.39 seconds
Started Aug 07 04:22:39 PM PDT 24
Finished Aug 07 04:56:15 PM PDT 24
Peak memory 160680 kb
Host smart-96215ad4-650c-4931-b852-8fbdb4a04b10
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3753497441 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.3753497441
Directory /workspace/27.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.562243193
Short name T131
Test name
Test status
Simulation time 336311850000 ps
CPU time 764.04 seconds
Started Aug 07 04:24:55 PM PDT 24
Finished Aug 07 04:56:27 PM PDT 24
Peak memory 160128 kb
Host smart-b3e55bfb-e279-4786-9569-9e7811b4c10d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=562243193 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.562243193
Directory /workspace/28.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.2160226544
Short name T139
Test name
Test status
Simulation time 336994930000 ps
CPU time 735.78 seconds
Started Aug 07 04:19:35 PM PDT 24
Finished Aug 07 04:49:35 PM PDT 24
Peak memory 160644 kb
Host smart-3c66444a-97e3-48e9-93d4-5478ec57df66
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2160226544 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.2160226544
Directory /workspace/29.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.3412018042
Short name T112
Test name
Test status
Simulation time 336378190000 ps
CPU time 607.08 seconds
Started Aug 07 04:25:00 PM PDT 24
Finished Aug 07 04:50:18 PM PDT 24
Peak memory 160132 kb
Host smart-8cea2794-a3d2-4705-8698-9a1b7bc10dde
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3412018042 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.3412018042
Directory /workspace/3.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3837633953
Short name T142
Test name
Test status
Simulation time 336697970000 ps
CPU time 764.65 seconds
Started Aug 07 04:24:55 PM PDT 24
Finished Aug 07 04:56:18 PM PDT 24
Peak memory 159600 kb
Host smart-c566d059-35c3-4ca9-9f7c-0c5d40ba3ca9
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3837633953 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.3837633953
Directory /workspace/30.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.3136983130
Short name T117
Test name
Test status
Simulation time 336781730000 ps
CPU time 852.83 seconds
Started Aug 07 04:21:50 PM PDT 24
Finished Aug 07 04:56:55 PM PDT 24
Peak memory 160636 kb
Host smart-75c5a9fb-2c15-4e65-b9d0-0ff4572df064
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3136983130 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.3136983130
Directory /workspace/31.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.3938072054
Short name T126
Test name
Test status
Simulation time 337136810000 ps
CPU time 778.65 seconds
Started Aug 07 04:24:34 PM PDT 24
Finished Aug 07 04:56:47 PM PDT 24
Peak memory 160492 kb
Host smart-d8b30039-342c-4199-9a51-49950e8c6812
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3938072054 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.3938072054
Directory /workspace/32.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.1461212045
Short name T143
Test name
Test status
Simulation time 336956330000 ps
CPU time 877.89 seconds
Started Aug 07 04:20:55 PM PDT 24
Finished Aug 07 04:57:05 PM PDT 24
Peak memory 160648 kb
Host smart-3b4f86b1-4c95-4b3e-ad3b-4bf78a0c4a1e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1461212045 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.1461212045
Directory /workspace/33.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.1643497114
Short name T114
Test name
Test status
Simulation time 337086870000 ps
CPU time 861.01 seconds
Started Aug 07 04:19:43 PM PDT 24
Finished Aug 07 04:54:33 PM PDT 24
Peak memory 160664 kb
Host smart-b807f0b6-cd6f-4ada-8280-055c7741b7e7
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1643497114 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.1643497114
Directory /workspace/34.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.766364428
Short name T30
Test name
Test status
Simulation time 337128610000 ps
CPU time 753.83 seconds
Started Aug 07 04:19:41 PM PDT 24
Finished Aug 07 04:51:22 PM PDT 24
Peak memory 160536 kb
Host smart-bd0a07d8-6411-4b13-8f42-1ebd922eabba
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=766364428 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.766364428
Directory /workspace/35.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.1015414218
Short name T146
Test name
Test status
Simulation time 336987730000 ps
CPU time 818.17 seconds
Started Aug 07 04:22:27 PM PDT 24
Finished Aug 07 04:56:10 PM PDT 24
Peak memory 160904 kb
Host smart-6d6bbde8-3bd0-4165-b1e1-8250ddaac907
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1015414218 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.1015414218
Directory /workspace/36.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.3637053580
Short name T111
Test name
Test status
Simulation time 336626070000 ps
CPU time 773.33 seconds
Started Aug 07 04:24:33 PM PDT 24
Finished Aug 07 04:56:21 PM PDT 24
Peak memory 160492 kb
Host smart-a5ffa2df-ffc3-4b14-b864-68c1f2e5861a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3637053580 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.3637053580
Directory /workspace/37.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.353785767
Short name T29
Test name
Test status
Simulation time 336414850000 ps
CPU time 955.01 seconds
Started Aug 07 04:20:36 PM PDT 24
Finished Aug 07 04:59:54 PM PDT 24
Peak memory 160672 kb
Host smart-0b8dec4d-16be-4552-81b5-5b34fddbecc5
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=353785767 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.353785767
Directory /workspace/38.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.3630251688
Short name T5
Test name
Test status
Simulation time 336815010000 ps
CPU time 872.36 seconds
Started Aug 07 04:20:56 PM PDT 24
Finished Aug 07 04:56:50 PM PDT 24
Peak memory 160648 kb
Host smart-559765cb-3e41-4998-93c3-1d4f78b120d6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3630251688 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.3630251688
Directory /workspace/39.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.3866451889
Short name T149
Test name
Test status
Simulation time 336422930000 ps
CPU time 727.43 seconds
Started Aug 07 04:24:24 PM PDT 24
Finished Aug 07 04:54:12 PM PDT 24
Peak memory 159736 kb
Host smart-e9e7ec62-0d01-40ff-835f-3bcececfc4fd
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3866451889 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.3866451889
Directory /workspace/4.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.2593163256
Short name T128
Test name
Test status
Simulation time 336751190000 ps
CPU time 850.25 seconds
Started Aug 07 04:21:42 PM PDT 24
Finished Aug 07 04:56:37 PM PDT 24
Peak memory 160648 kb
Host smart-816075b4-6a43-4313-8178-73d88122b8f3
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2593163256 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.2593163256
Directory /workspace/40.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.1966601419
Short name T136
Test name
Test status
Simulation time 336654850000 ps
CPU time 772.86 seconds
Started Aug 07 04:19:44 PM PDT 24
Finished Aug 07 04:51:10 PM PDT 24
Peak memory 160644 kb
Host smart-f9356d5a-cd8c-4d01-acea-6871d17de228
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1966601419 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.1966601419
Directory /workspace/41.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.2311838288
Short name T115
Test name
Test status
Simulation time 336911870000 ps
CPU time 753.37 seconds
Started Aug 07 04:20:44 PM PDT 24
Finished Aug 07 04:51:26 PM PDT 24
Peak memory 160684 kb
Host smart-0ca7c4e7-252d-424b-8a3e-64d842c85533
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2311838288 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.2311838288
Directory /workspace/42.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.1111139935
Short name T113
Test name
Test status
Simulation time 336705170000 ps
CPU time 575.78 seconds
Started Aug 07 04:19:59 PM PDT 24
Finished Aug 07 04:44:48 PM PDT 24
Peak memory 160080 kb
Host smart-304b25cd-1301-42b4-b02d-a8e4867cf3b3
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1111139935 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.1111139935
Directory /workspace/43.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.1924657937
Short name T148
Test name
Test status
Simulation time 336799950000 ps
CPU time 738.51 seconds
Started Aug 07 04:24:15 PM PDT 24
Finished Aug 07 04:54:45 PM PDT 24
Peak memory 159640 kb
Host smart-04a7aaa2-64ac-4e2c-8882-492af901d2dd
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1924657937 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.1924657937
Directory /workspace/44.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.3863751519
Short name T116
Test name
Test status
Simulation time 336395250000 ps
CPU time 738.25 seconds
Started Aug 07 04:20:44 PM PDT 24
Finished Aug 07 04:50:52 PM PDT 24
Peak memory 160684 kb
Host smart-72b31e8c-5ea4-4d3a-aa3f-7b95bcc29961
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3863751519 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.3863751519
Directory /workspace/45.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.1428527492
Short name T129
Test name
Test status
Simulation time 336554490000 ps
CPU time 771.75 seconds
Started Aug 07 04:22:35 PM PDT 24
Finished Aug 07 04:54:11 PM PDT 24
Peak memory 160680 kb
Host smart-d25551ab-31f5-411f-82a5-354baf3b3d20
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1428527492 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.1428527492
Directory /workspace/46.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.176054924
Short name T120
Test name
Test status
Simulation time 336287770000 ps
CPU time 821.46 seconds
Started Aug 07 04:22:36 PM PDT 24
Finished Aug 07 04:56:00 PM PDT 24
Peak memory 160704 kb
Host smart-71009d7a-1fb8-455a-8ad8-8a571fb451bc
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=176054924 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.176054924
Directory /workspace/47.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.592651338
Short name T25
Test name
Test status
Simulation time 336399890000 ps
CPU time 748.22 seconds
Started Aug 07 04:24:14 PM PDT 24
Finished Aug 07 04:55:03 PM PDT 24
Peak memory 159524 kb
Host smart-a711e6f8-b454-42ad-a66a-f42d6db117a6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=592651338 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.592651338
Directory /workspace/48.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.2023183627
Short name T6
Test name
Test status
Simulation time 336460050000 ps
CPU time 910.5 seconds
Started Aug 07 04:24:09 PM PDT 24
Finished Aug 07 05:02:49 PM PDT 24
Peak memory 158816 kb
Host smart-36cd7046-6310-432b-8438-e6c721a335c6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2023183627 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.2023183627
Directory /workspace/49.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.2128412853
Short name T138
Test name
Test status
Simulation time 336755550000 ps
CPU time 937.37 seconds
Started Aug 07 04:24:23 PM PDT 24
Finished Aug 07 05:03:11 PM PDT 24
Peak memory 160556 kb
Host smart-29473bda-3072-454f-9f8f-f978cbe2e859
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2128412853 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.2128412853
Directory /workspace/5.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.1015614133
Short name T147
Test name
Test status
Simulation time 336411410000 ps
CPU time 840.22 seconds
Started Aug 07 04:21:08 PM PDT 24
Finished Aug 07 04:55:11 PM PDT 24
Peak memory 160660 kb
Host smart-ef172432-1b48-4842-84a6-9755616e014d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1015614133 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.1015614133
Directory /workspace/6.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.4276566509
Short name T127
Test name
Test status
Simulation time 336646750000 ps
CPU time 662.91 seconds
Started Aug 07 04:24:24 PM PDT 24
Finished Aug 07 04:51:46 PM PDT 24
Peak memory 159620 kb
Host smart-2cd86fc3-94bc-4e29-a1f6-d11ba08018c5
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4276566509 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.4276566509
Directory /workspace/7.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1800980051
Short name T144
Test name
Test status
Simulation time 336416950000 ps
CPU time 675.28 seconds
Started Aug 07 04:25:00 PM PDT 24
Finished Aug 07 04:52:35 PM PDT 24
Peak memory 160504 kb
Host smart-46c82532-786a-42c2-8f2c-3522feacd3a7
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1800980051 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.1800980051
Directory /workspace/8.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.4173344375
Short name T137
Test name
Test status
Simulation time 336759970000 ps
CPU time 733.34 seconds
Started Aug 07 04:24:39 PM PDT 24
Finished Aug 07 04:54:54 PM PDT 24
Peak memory 159336 kb
Host smart-1a953d70-7eea-4724-9688-75d29c257326
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4173344375 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.4173344375
Directory /workspace/9.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.4109034413
Short name T107
Test name
Test status
Simulation time 336562170000 ps
CPU time 878.12 seconds
Started Aug 07 04:20:36 PM PDT 24
Finished Aug 07 04:56:01 PM PDT 24
Peak memory 160660 kb
Host smart-c96e496d-042b-45cd-a998-0674ef2874a3
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4109034413 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.4109034413
Directory /workspace/0.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.2194958904
Short name T87
Test name
Test status
Simulation time 336363530000 ps
CPU time 752.28 seconds
Started Aug 07 04:20:30 PM PDT 24
Finished Aug 07 04:52:10 PM PDT 24
Peak memory 160536 kb
Host smart-e51f51bd-7b2e-4558-be25-8bacfb90504e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2194958904 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.2194958904
Directory /workspace/1.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.2433186952
Short name T102
Test name
Test status
Simulation time 336945150000 ps
CPU time 726.72 seconds
Started Aug 07 04:24:50 PM PDT 24
Finished Aug 07 04:54:50 PM PDT 24
Peak memory 160624 kb
Host smart-797cd434-9c32-48d2-9ef8-86692430f6dc
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2433186952 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.2433186952
Directory /workspace/11.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.996267445
Short name T90
Test name
Test status
Simulation time 336346230000 ps
CPU time 772.12 seconds
Started Aug 07 04:20:58 PM PDT 24
Finished Aug 07 04:52:34 PM PDT 24
Peak memory 160600 kb
Host smart-2149f37d-9ca4-44be-a542-916967cc3c94
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=996267445 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.996267445
Directory /workspace/12.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.3783344980
Short name T83
Test name
Test status
Simulation time 336799350000 ps
CPU time 638.22 seconds
Started Aug 07 04:24:20 PM PDT 24
Finished Aug 07 04:50:32 PM PDT 24
Peak memory 159544 kb
Host smart-e537a7c8-aaf0-43b4-b1a5-816d16784afa
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3783344980 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.3783344980
Directory /workspace/13.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.1598828126
Short name T80
Test name
Test status
Simulation time 336914090000 ps
CPU time 611.26 seconds
Started Aug 07 04:24:01 PM PDT 24
Finished Aug 07 04:49:08 PM PDT 24
Peak memory 159004 kb
Host smart-9a8b29ce-78e1-43d0-ac74-a6c4392cf8cf
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1598828126 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.1598828126
Directory /workspace/14.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.4048468733
Short name T15
Test name
Test status
Simulation time 336807170000 ps
CPU time 832.2 seconds
Started Aug 07 04:21:54 PM PDT 24
Finished Aug 07 04:56:16 PM PDT 24
Peak memory 160908 kb
Host smart-cb6dcbe3-e26b-48fb-af17-f0d4323e70e7
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4048468733 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.4048468733
Directory /workspace/15.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.2445756774
Short name T81
Test name
Test status
Simulation time 336462650000 ps
CPU time 599.09 seconds
Started Aug 07 04:24:21 PM PDT 24
Finished Aug 07 04:49:01 PM PDT 24
Peak memory 159768 kb
Host smart-1bb29c45-a345-4b1b-9339-a995a564fcb3
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2445756774 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.2445756774
Directory /workspace/16.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.3305339914
Short name T19
Test name
Test status
Simulation time 336743550000 ps
CPU time 783.04 seconds
Started Aug 07 04:22:47 PM PDT 24
Finished Aug 07 04:54:46 PM PDT 24
Peak memory 160668 kb
Host smart-00ce598f-9cac-4ca9-9241-d557b2985ea5
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3305339914 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.3305339914
Directory /workspace/17.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.3709886036
Short name T88
Test name
Test status
Simulation time 336573450000 ps
CPU time 748.4 seconds
Started Aug 07 04:24:08 PM PDT 24
Finished Aug 07 04:54:40 PM PDT 24
Peak memory 159768 kb
Host smart-99612041-3784-4651-bd22-026621eb50d4
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3709886036 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.3709886036
Directory /workspace/18.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.3197496192
Short name T108
Test name
Test status
Simulation time 337058210000 ps
CPU time 617.28 seconds
Started Aug 07 04:24:17 PM PDT 24
Finished Aug 07 04:50:03 PM PDT 24
Peak memory 160624 kb
Host smart-e4490a26-3954-4aa7-b554-7dabb0660e6d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3197496192 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.3197496192
Directory /workspace/19.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.2121990193
Short name T85
Test name
Test status
Simulation time 336601770000 ps
CPU time 876.77 seconds
Started Aug 07 04:20:55 PM PDT 24
Finished Aug 07 04:56:56 PM PDT 24
Peak memory 160644 kb
Host smart-66da11d2-30d5-4791-803e-37d48e56c3a3
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2121990193 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.2121990193
Directory /workspace/2.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.445956584
Short name T20
Test name
Test status
Simulation time 337004890000 ps
CPU time 814.26 seconds
Started Aug 07 04:24:25 PM PDT 24
Finished Aug 07 04:57:48 PM PDT 24
Peak memory 160628 kb
Host smart-a00f8dc8-c5bd-4a94-a6ff-e042dceb9a60
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=445956584 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.445956584
Directory /workspace/20.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3938098495
Short name T110
Test name
Test status
Simulation time 336927730000 ps
CPU time 812.95 seconds
Started Aug 07 04:24:25 PM PDT 24
Finished Aug 07 04:57:40 PM PDT 24
Peak memory 160640 kb
Host smart-c262359a-e954-42a5-b1ae-81cc31c4f37d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3938098495 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.3938098495
Directory /workspace/21.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.699568815
Short name T105
Test name
Test status
Simulation time 336617530000 ps
CPU time 763.95 seconds
Started Aug 07 04:19:41 PM PDT 24
Finished Aug 07 04:51:28 PM PDT 24
Peak memory 160540 kb
Host smart-8d0c3295-210f-4c8b-9828-194f922525a2
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=699568815 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.699568815
Directory /workspace/22.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.2118176859
Short name T89
Test name
Test status
Simulation time 336701610000 ps
CPU time 639.76 seconds
Started Aug 07 04:24:09 PM PDT 24
Finished Aug 07 04:50:32 PM PDT 24
Peak memory 160364 kb
Host smart-cfbc208c-2926-4ea5-bda1-4e9aac2d4a68
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2118176859 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.2118176859
Directory /workspace/23.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.1478779152
Short name T78
Test name
Test status
Simulation time 336871090000 ps
CPU time 708.76 seconds
Started Aug 07 04:24:06 PM PDT 24
Finished Aug 07 04:53:06 PM PDT 24
Peak memory 159300 kb
Host smart-ed82e5f8-08e7-4cdc-8cd8-35df94be9bb4
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1478779152 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.1478779152
Directory /workspace/24.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.1775386167
Short name T79
Test name
Test status
Simulation time 336695790000 ps
CPU time 949.07 seconds
Started Aug 07 04:21:28 PM PDT 24
Finished Aug 07 05:00:52 PM PDT 24
Peak memory 160680 kb
Host smart-cd998290-2775-41bd-b59e-42a4fe6c04df
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1775386167 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.1775386167
Directory /workspace/25.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.1034040144
Short name T101
Test name
Test status
Simulation time 336669110000 ps
CPU time 754.21 seconds
Started Aug 07 04:20:41 PM PDT 24
Finished Aug 07 04:51:28 PM PDT 24
Peak memory 160636 kb
Host smart-b7744566-b09d-4ad8-9327-16f894fbd581
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1034040144 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.1034040144
Directory /workspace/26.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.836422743
Short name T97
Test name
Test status
Simulation time 336541670000 ps
CPU time 729.98 seconds
Started Aug 07 04:24:26 PM PDT 24
Finished Aug 07 04:54:30 PM PDT 24
Peak memory 160228 kb
Host smart-ece57d55-b527-4445-ae0c-c8e78f0cf4cc
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=836422743 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.836422743
Directory /workspace/27.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.1445352073
Short name T103
Test name
Test status
Simulation time 336942230000 ps
CPU time 700.13 seconds
Started Aug 07 04:24:26 PM PDT 24
Finished Aug 07 04:53:12 PM PDT 24
Peak memory 159520 kb
Host smart-6e29d899-e246-441e-a419-234087756427
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1445352073 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.1445352073
Directory /workspace/28.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.4204263683
Short name T14
Test name
Test status
Simulation time 336321830000 ps
CPU time 830.2 seconds
Started Aug 07 04:20:39 PM PDT 24
Finished Aug 07 04:54:07 PM PDT 24
Peak memory 160684 kb
Host smart-dae23b8a-7448-430a-9bca-82983083e59f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4204263683 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.4204263683
Directory /workspace/29.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.1318465138
Short name T92
Test name
Test status
Simulation time 337125270000 ps
CPU time 650.62 seconds
Started Aug 07 04:19:19 PM PDT 24
Finished Aug 07 04:46:06 PM PDT 24
Peak memory 160648 kb
Host smart-b79575a5-4449-432e-a595-7752c1058e0b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1318465138 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.1318465138
Directory /workspace/3.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.1966647473
Short name T94
Test name
Test status
Simulation time 336779430000 ps
CPU time 717.73 seconds
Started Aug 07 04:20:01 PM PDT 24
Finished Aug 07 04:49:18 PM PDT 24
Peak memory 160692 kb
Host smart-dfdf014c-d5dd-4d49-957c-08d89d3958b0
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1966647473 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.1966647473
Directory /workspace/30.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.2650684795
Short name T18
Test name
Test status
Simulation time 336607890000 ps
CPU time 764.18 seconds
Started Aug 07 04:20:44 PM PDT 24
Finished Aug 07 04:52:04 PM PDT 24
Peak memory 160596 kb
Host smart-f6c3a372-5af5-4000-a3e5-7e83db1a7c78
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2650684795 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.2650684795
Directory /workspace/31.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.1010524688
Short name T76
Test name
Test status
Simulation time 336469830000 ps
CPU time 608.43 seconds
Started Aug 07 04:24:43 PM PDT 24
Finished Aug 07 04:49:46 PM PDT 24
Peak memory 159748 kb
Host smart-4952c42c-4c1a-42ac-ac00-fa7bac2d8bdc
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1010524688 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.1010524688
Directory /workspace/32.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.2363640000
Short name T17
Test name
Test status
Simulation time 336376530000 ps
CPU time 779.03 seconds
Started Aug 07 04:24:50 PM PDT 24
Finished Aug 07 04:56:48 PM PDT 24
Peak memory 159836 kb
Host smart-884e5bf0-f8d4-4ce2-9dca-b78d97f82e80
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2363640000 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.2363640000
Directory /workspace/33.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.3877906589
Short name T109
Test name
Test status
Simulation time 337009870000 ps
CPU time 820.61 seconds
Started Aug 07 04:19:43 PM PDT 24
Finished Aug 07 04:53:02 PM PDT 24
Peak memory 160668 kb
Host smart-ba0c55cc-296e-4efc-8bab-af81f6dc688e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3877906589 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.3877906589
Directory /workspace/34.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.255931027
Short name T71
Test name
Test status
Simulation time 336820250000 ps
CPU time 842.86 seconds
Started Aug 07 04:20:32 PM PDT 24
Finished Aug 07 04:55:21 PM PDT 24
Peak memory 160904 kb
Host smart-b8a61a66-aabc-4c6a-a025-975d31cec59b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=255931027 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.255931027
Directory /workspace/35.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.3551010900
Short name T91
Test name
Test status
Simulation time 336428630000 ps
CPU time 830.48 seconds
Started Aug 07 04:20:30 PM PDT 24
Finished Aug 07 04:54:11 PM PDT 24
Peak memory 160544 kb
Host smart-43f3ab2b-3eab-49e3-a0c3-92c0c84b57fb
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3551010900 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.3551010900
Directory /workspace/36.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.243479376
Short name T98
Test name
Test status
Simulation time 337119450000 ps
CPU time 843.41 seconds
Started Aug 07 04:20:26 PM PDT 24
Finished Aug 07 04:54:26 PM PDT 24
Peak memory 160668 kb
Host smart-33007d02-9931-4b34-a2af-d2d427d4a1e2
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=243479376 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.243479376
Directory /workspace/37.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.1118648720
Short name T82
Test name
Test status
Simulation time 336727670000 ps
CPU time 760.24 seconds
Started Aug 07 04:25:26 PM PDT 24
Finished Aug 07 04:56:20 PM PDT 24
Peak memory 159444 kb
Host smart-467935f2-eec1-4f2d-afe9-7150086dc26e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1118648720 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.1118648720
Directory /workspace/38.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.184423968
Short name T93
Test name
Test status
Simulation time 337078410000 ps
CPU time 782.19 seconds
Started Aug 07 04:24:34 PM PDT 24
Finished Aug 07 04:56:53 PM PDT 24
Peak memory 160496 kb
Host smart-604a5811-aa60-4e97-a72d-fe637110b88f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=184423968 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.184423968
Directory /workspace/39.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.390674853
Short name T86
Test name
Test status
Simulation time 336649390000 ps
CPU time 907.09 seconds
Started Aug 07 04:24:11 PM PDT 24
Finished Aug 07 05:02:31 PM PDT 24
Peak memory 160560 kb
Host smart-c7ae556c-6ada-4d67-8980-0dc4e96d5223
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=390674853 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.390674853
Directory /workspace/4.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.265532969
Short name T75
Test name
Test status
Simulation time 336834850000 ps
CPU time 766.69 seconds
Started Aug 07 04:25:26 PM PDT 24
Finished Aug 07 04:56:34 PM PDT 24
Peak memory 160364 kb
Host smart-ee97fb81-2345-4fec-a165-af0e5c9ac5de
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=265532969 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.265532969
Directory /workspace/40.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.2386639544
Short name T16
Test name
Test status
Simulation time 337116710000 ps
CPU time 651.11 seconds
Started Aug 07 04:19:19 PM PDT 24
Finished Aug 07 04:46:10 PM PDT 24
Peak memory 160660 kb
Host smart-e44eb9b2-d6c7-4618-acd3-dbf72e3a09d4
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2386639544 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.2386639544
Directory /workspace/41.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.3512248676
Short name T74
Test name
Test status
Simulation time 336405890000 ps
CPU time 959.14 seconds
Started Aug 07 04:23:34 PM PDT 24
Finished Aug 07 05:03:13 PM PDT 24
Peak memory 160684 kb
Host smart-1520b969-4b10-41ce-9bd7-5aa04361a1b6
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3512248676 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.3512248676
Directory /workspace/42.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.1068602913
Short name T23
Test name
Test status
Simulation time 336720790000 ps
CPU time 965.56 seconds
Started Aug 07 04:23:33 PM PDT 24
Finished Aug 07 05:03:19 PM PDT 24
Peak memory 160680 kb
Host smart-bcf1f635-edb2-41c5-8944-807f89d76475
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1068602913 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.1068602913
Directory /workspace/43.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.851346125
Short name T95
Test name
Test status
Simulation time 336626330000 ps
CPU time 772.64 seconds
Started Aug 07 04:20:30 PM PDT 24
Finished Aug 07 04:52:41 PM PDT 24
Peak memory 160540 kb
Host smart-dab02aeb-172b-4662-9799-6769b85ff8ef
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=851346125 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.851346125
Directory /workspace/44.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.2037348978
Short name T106
Test name
Test status
Simulation time 336946090000 ps
CPU time 851.55 seconds
Started Aug 07 04:23:26 PM PDT 24
Finished Aug 07 04:57:54 PM PDT 24
Peak memory 160668 kb
Host smart-93abc7b7-8a30-4138-9735-283ebad0d24b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2037348978 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.2037348978
Directory /workspace/45.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.2892516305
Short name T104
Test name
Test status
Simulation time 336584450000 ps
CPU time 703.85 seconds
Started Aug 07 04:25:00 PM PDT 24
Finished Aug 07 04:53:58 PM PDT 24
Peak memory 160632 kb
Host smart-e023e35f-6d46-419f-84a9-bd9b6aef9683
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2892516305 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.2892516305
Directory /workspace/46.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.3760817116
Short name T73
Test name
Test status
Simulation time 337047090000 ps
CPU time 736.33 seconds
Started Aug 07 04:20:15 PM PDT 24
Finished Aug 07 04:50:19 PM PDT 24
Peak memory 160692 kb
Host smart-342ddd3d-a677-42e8-aa8d-e620bad297aa
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3760817116 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.3760817116
Directory /workspace/47.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.3811567032
Short name T21
Test name
Test status
Simulation time 336723110000 ps
CPU time 726.01 seconds
Started Aug 07 04:24:15 PM PDT 24
Finished Aug 07 04:54:18 PM PDT 24
Peak memory 160132 kb
Host smart-b546f773-c2af-4bd6-8d43-14312c05dba9
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3811567032 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.3811567032
Directory /workspace/48.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.3202008946
Short name T99
Test name
Test status
Simulation time 336599730000 ps
CPU time 826.72 seconds
Started Aug 07 04:23:34 PM PDT 24
Finished Aug 07 04:56:57 PM PDT 24
Peak memory 160720 kb
Host smart-4c7f2b54-fb8f-4a99-8cd7-15157af23a6c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3202008946 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.3202008946
Directory /workspace/49.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.720597280
Short name T77
Test name
Test status
Simulation time 336771290000 ps
CPU time 810.49 seconds
Started Aug 07 04:22:46 PM PDT 24
Finished Aug 07 04:55:48 PM PDT 24
Peak memory 160680 kb
Host smart-4d9130a2-1463-48d5-9458-0d894d5f9747
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=720597280 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.720597280
Directory /workspace/5.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.4214788255
Short name T72
Test name
Test status
Simulation time 336505410000 ps
CPU time 702.19 seconds
Started Aug 07 04:24:26 PM PDT 24
Finished Aug 07 04:53:23 PM PDT 24
Peak memory 160620 kb
Host smart-50f4b1c9-9f2f-4fe3-bdda-fe126f874688
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4214788255 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.4214788255
Directory /workspace/6.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.3694099385
Short name T100
Test name
Test status
Simulation time 336919830000 ps
CPU time 899.81 seconds
Started Aug 07 04:24:10 PM PDT 24
Finished Aug 07 05:02:17 PM PDT 24
Peak memory 160076 kb
Host smart-0c6ead1c-fac2-47e7-a538-f37c9969746f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3694099385 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.3694099385
Directory /workspace/7.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.764965389
Short name T84
Test name
Test status
Simulation time 337092170000 ps
CPU time 914.7 seconds
Started Aug 07 04:24:09 PM PDT 24
Finished Aug 07 05:02:46 PM PDT 24
Peak memory 158816 kb
Host smart-658aa086-dc54-4969-889b-f2289974ba37
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=764965389 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.764965389
Directory /workspace/8.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.451648208
Short name T96
Test name
Test status
Simulation time 337003210000 ps
CPU time 908.07 seconds
Started Aug 07 04:24:09 PM PDT 24
Finished Aug 07 05:02:26 PM PDT 24
Peak memory 159124 kb
Host smart-f1f4c9f6-a409-4164-88a3-79d977c86b25
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=451648208 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.451648208
Directory /workspace/9.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.4038512466
Short name T170
Test name
Test status
Simulation time 1527710000 ps
CPU time 4.83 seconds
Started Aug 07 04:22:47 PM PDT 24
Finished Aug 07 04:22:58 PM PDT 24
Peak memory 164968 kb
Host smart-9537c94a-665a-44a9-8e37-ffb19cdb7fbe
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4038512466 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.4038512466
Directory /workspace/0.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.1622542780
Short name T178
Test name
Test status
Simulation time 1418530000 ps
CPU time 4.24 seconds
Started Aug 07 04:20:18 PM PDT 24
Finished Aug 07 04:20:27 PM PDT 24
Peak memory 164728 kb
Host smart-1f24cf16-219c-4e1e-ab59-7e46b49e2e46
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1622542780 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.1622542780
Directory /workspace/1.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.4284852719
Short name T197
Test name
Test status
Simulation time 1347670000 ps
CPU time 3.2 seconds
Started Aug 07 04:24:46 PM PDT 24
Finished Aug 07 04:24:54 PM PDT 24
Peak memory 164316 kb
Host smart-06a0c617-2670-498a-9483-2176f95c1e3d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4284852719 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.4284852719
Directory /workspace/10.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.2787667135
Short name T167
Test name
Test status
Simulation time 1570350000 ps
CPU time 3.82 seconds
Started Aug 07 04:24:31 PM PDT 24
Finished Aug 07 04:24:39 PM PDT 24
Peak memory 164320 kb
Host smart-60c37b91-ddc9-497a-a758-3026750fe36a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2787667135 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.2787667135
Directory /workspace/11.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.2557800925
Short name T200
Test name
Test status
Simulation time 1500390000 ps
CPU time 4.07 seconds
Started Aug 07 04:24:56 PM PDT 24
Finished Aug 07 04:25:05 PM PDT 24
Peak memory 164316 kb
Host smart-a30f1c21-c5f3-4527-b975-7a2bca87489e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2557800925 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.2557800925
Directory /workspace/12.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.669936367
Short name T152
Test name
Test status
Simulation time 1361270000 ps
CPU time 3.74 seconds
Started Aug 07 04:24:26 PM PDT 24
Finished Aug 07 04:24:34 PM PDT 24
Peak memory 164804 kb
Host smart-e4023d78-1c68-483e-a2d9-049b5b07b3fa
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=669936367 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.669936367
Directory /workspace/13.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.3804201534
Short name T161
Test name
Test status
Simulation time 1553710000 ps
CPU time 4.44 seconds
Started Aug 07 04:24:26 PM PDT 24
Finished Aug 07 04:24:36 PM PDT 24
Peak memory 163204 kb
Host smart-b99b3602-6a49-4703-8121-5d58249deab4
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3804201534 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.3804201534
Directory /workspace/14.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.889918292
Short name T193
Test name
Test status
Simulation time 936770000 ps
CPU time 3.46 seconds
Started Aug 07 04:22:15 PM PDT 24
Finished Aug 07 04:22:23 PM PDT 24
Peak memory 164804 kb
Host smart-9cb828d5-4c3d-49f5-ac24-ddc767853de6
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=889918292 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.889918292
Directory /workspace/15.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.1993150292
Short name T158
Test name
Test status
Simulation time 1588130000 ps
CPU time 5.6 seconds
Started Aug 07 04:24:55 PM PDT 24
Finished Aug 07 04:25:08 PM PDT 24
Peak memory 164176 kb
Host smart-bc6f3df8-7a3d-47ac-9393-907198a144aa
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1993150292 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.1993150292
Directory /workspace/16.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.898517147
Short name T184
Test name
Test status
Simulation time 1532390000 ps
CPU time 5.49 seconds
Started Aug 07 04:24:55 PM PDT 24
Finished Aug 07 04:25:07 PM PDT 24
Peak memory 163504 kb
Host smart-30999888-26fc-4e54-ae42-e482083bc549
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=898517147 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.898517147
Directory /workspace/17.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.1230304300
Short name T187
Test name
Test status
Simulation time 1385890000 ps
CPU time 4.15 seconds
Started Aug 07 04:22:17 PM PDT 24
Finished Aug 07 04:22:26 PM PDT 24
Peak memory 164804 kb
Host smart-dede7cc6-eb09-44da-b965-42066f9384fb
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1230304300 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.1230304300
Directory /workspace/18.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.3019375382
Short name T185
Test name
Test status
Simulation time 1130790000 ps
CPU time 3.68 seconds
Started Aug 07 04:22:11 PM PDT 24
Finished Aug 07 04:22:19 PM PDT 24
Peak memory 164736 kb
Host smart-b4a5ae39-753e-474b-997e-67ad2e63744d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3019375382 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.3019375382
Directory /workspace/19.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.627690087
Short name T183
Test name
Test status
Simulation time 1341370000 ps
CPU time 4.12 seconds
Started Aug 07 04:24:55 PM PDT 24
Finished Aug 07 04:25:05 PM PDT 24
Peak memory 164184 kb
Host smart-a11973bb-0467-45aa-bbbc-f0c4613f9cce
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=627690087 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.627690087
Directory /workspace/2.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.1840428011
Short name T177
Test name
Test status
Simulation time 1450210000 ps
CPU time 3.53 seconds
Started Aug 07 04:20:42 PM PDT 24
Finished Aug 07 04:20:50 PM PDT 24
Peak memory 164708 kb
Host smart-83cd0ee2-126b-4d7f-bade-8e24f5f12d97
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1840428011 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.1840428011
Directory /workspace/20.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3487242995
Short name T198
Test name
Test status
Simulation time 1542590000 ps
CPU time 4.55 seconds
Started Aug 07 04:25:00 PM PDT 24
Finished Aug 07 04:25:10 PM PDT 24
Peak memory 164496 kb
Host smart-2ebb6895-8552-421e-ba13-756155928574
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3487242995 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.3487242995
Directory /workspace/21.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.4009822803
Short name T190
Test name
Test status
Simulation time 1630410000 ps
CPU time 4.89 seconds
Started Aug 07 04:23:21 PM PDT 24
Finished Aug 07 04:23:32 PM PDT 24
Peak memory 164764 kb
Host smart-fef15a4a-fbc3-4f88-9f78-9fd69a5ead9e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4009822803 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.4009822803
Directory /workspace/22.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.1574537859
Short name T199
Test name
Test status
Simulation time 1460590000 ps
CPU time 3.9 seconds
Started Aug 07 04:22:40 PM PDT 24
Finished Aug 07 04:22:49 PM PDT 24
Peak memory 164720 kb
Host smart-92b89e1a-d094-4e2f-878e-bc21505dc66a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1574537859 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.1574537859
Directory /workspace/23.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.2774379351
Short name T156
Test name
Test status
Simulation time 1529210000 ps
CPU time 4.79 seconds
Started Aug 07 04:25:36 PM PDT 24
Finished Aug 07 04:25:47 PM PDT 24
Peak memory 164560 kb
Host smart-6ee5d351-45ea-4e15-92a5-8575aa8f929b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2774379351 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.2774379351
Directory /workspace/24.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.1994512289
Short name T155
Test name
Test status
Simulation time 1249070000 ps
CPU time 3.57 seconds
Started Aug 07 04:19:44 PM PDT 24
Finished Aug 07 04:19:51 PM PDT 24
Peak memory 164788 kb
Host smart-429965db-ba8b-4299-a7bf-4f501d1d2a76
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1994512289 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.1994512289
Directory /workspace/25.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.518235464
Short name T151
Test name
Test status
Simulation time 1487310000 ps
CPU time 3.61 seconds
Started Aug 07 04:24:55 PM PDT 24
Finished Aug 07 04:25:04 PM PDT 24
Peak memory 164956 kb
Host smart-43ba213a-94c9-41a4-b147-d34d8928e5d4
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=518235464 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.518235464
Directory /workspace/26.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.453062250
Short name T174
Test name
Test status
Simulation time 1619390000 ps
CPU time 4.58 seconds
Started Aug 07 04:21:55 PM PDT 24
Finished Aug 07 04:22:05 PM PDT 24
Peak memory 164788 kb
Host smart-85dd7a45-91a7-47ff-bb2d-65ed3fecad47
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=453062250 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.453062250
Directory /workspace/27.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.1716770085
Short name T154
Test name
Test status
Simulation time 1398710000 ps
CPU time 3.62 seconds
Started Aug 07 04:24:47 PM PDT 24
Finished Aug 07 04:24:55 PM PDT 24
Peak memory 164532 kb
Host smart-8021e293-cdb3-4b39-a78b-724d0db52b42
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1716770085 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.1716770085
Directory /workspace/28.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.2052032247
Short name T166
Test name
Test status
Simulation time 1572530000 ps
CPU time 4.32 seconds
Started Aug 07 04:22:06 PM PDT 24
Finished Aug 07 04:22:16 PM PDT 24
Peak memory 164728 kb
Host smart-2a8e666c-03ba-4fce-81df-e440af2b6291
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2052032247 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.2052032247
Directory /workspace/29.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.3960049431
Short name T181
Test name
Test status
Simulation time 1392390000 ps
CPU time 3.58 seconds
Started Aug 07 04:25:03 PM PDT 24
Finished Aug 07 04:25:11 PM PDT 24
Peak memory 163688 kb
Host smart-cb98a745-a387-463f-a292-640a83dee1eb
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3960049431 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.3960049431
Directory /workspace/3.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.3833443982
Short name T168
Test name
Test status
Simulation time 1126530000 ps
CPU time 3.38 seconds
Started Aug 07 04:19:35 PM PDT 24
Finished Aug 07 04:19:42 PM PDT 24
Peak memory 164788 kb
Host smart-2c502360-1452-4bc8-bed2-89b9418d265c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3833443982 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.3833443982
Directory /workspace/30.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.1290251432
Short name T172
Test name
Test status
Simulation time 1517730000 ps
CPU time 4.24 seconds
Started Aug 07 04:23:23 PM PDT 24
Finished Aug 07 04:23:33 PM PDT 24
Peak memory 164820 kb
Host smart-067e9cde-a99a-495e-9f6e-02a7ee26611a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1290251432 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.1290251432
Directory /workspace/31.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.2740870639
Short name T196
Test name
Test status
Simulation time 1455050000 ps
CPU time 5.2 seconds
Started Aug 07 04:24:55 PM PDT 24
Finished Aug 07 04:25:07 PM PDT 24
Peak memory 164192 kb
Host smart-e27bc2d7-83aa-408c-9fa6-9c08c9a311f0
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2740870639 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.2740870639
Directory /workspace/32.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.3596510608
Short name T188
Test name
Test status
Simulation time 1547350000 ps
CPU time 4.69 seconds
Started Aug 07 04:23:30 PM PDT 24
Finished Aug 07 04:23:41 PM PDT 24
Peak memory 164776 kb
Host smart-f9d7cb0e-2a42-4b11-a3c0-0af4fd9c2cb5
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3596510608 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.3596510608
Directory /workspace/33.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.518966340
Short name T194
Test name
Test status
Simulation time 1485190000 ps
CPU time 5 seconds
Started Aug 07 04:21:38 PM PDT 24
Finished Aug 07 04:21:50 PM PDT 24
Peak memory 164708 kb
Host smart-07a8f9be-2c48-4363-877f-ed3d496599a2
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=518966340 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.518966340
Directory /workspace/34.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.2598866817
Short name T179
Test name
Test status
Simulation time 1507910000 ps
CPU time 5.11 seconds
Started Aug 07 04:21:38 PM PDT 24
Finished Aug 07 04:21:50 PM PDT 24
Peak memory 164708 kb
Host smart-5ebd9bd3-aaa6-423d-bee0-c599ad2fa602
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2598866817 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.2598866817
Directory /workspace/35.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.2813071939
Short name T153
Test name
Test status
Simulation time 1554970000 ps
CPU time 5.3 seconds
Started Aug 07 04:24:06 PM PDT 24
Finished Aug 07 04:24:18 PM PDT 24
Peak memory 162876 kb
Host smart-30b469d1-f352-4292-ae03-173a6b796dbe
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2813071939 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.2813071939
Directory /workspace/36.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.363100847
Short name T157
Test name
Test status
Simulation time 1397790000 ps
CPU time 3.8 seconds
Started Aug 07 04:20:41 PM PDT 24
Finished Aug 07 04:20:49 PM PDT 24
Peak memory 164720 kb
Host smart-96fbaa49-1d36-4187-889d-5d02effff39a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=363100847 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.363100847
Directory /workspace/37.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.3376663104
Short name T171
Test name
Test status
Simulation time 1477390000 ps
CPU time 3.74 seconds
Started Aug 07 04:19:42 PM PDT 24
Finished Aug 07 04:19:51 PM PDT 24
Peak memory 164728 kb
Host smart-c31a4a44-c234-4620-a3e6-2d302ec5ba86
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3376663104 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.3376663104
Directory /workspace/38.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.3798657271
Short name T163
Test name
Test status
Simulation time 1231450000 ps
CPU time 4.33 seconds
Started Aug 07 04:24:06 PM PDT 24
Finished Aug 07 04:24:16 PM PDT 24
Peak memory 164272 kb
Host smart-217a1ca7-5d6b-4d96-94b8-798b2219229a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3798657271 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.3798657271
Directory /workspace/39.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3990704994
Short name T186
Test name
Test status
Simulation time 1494750000 ps
CPU time 4.42 seconds
Started Aug 07 04:21:44 PM PDT 24
Finished Aug 07 04:21:54 PM PDT 24
Peak memory 164820 kb
Host smart-4aee88be-df83-4f38-86d7-99474ee368bb
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3990704994 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.3990704994
Directory /workspace/4.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.2371773968
Short name T191
Test name
Test status
Simulation time 1420710000 ps
CPU time 2.95 seconds
Started Aug 07 04:24:49 PM PDT 24
Finished Aug 07 04:24:55 PM PDT 24
Peak memory 164464 kb
Host smart-33028947-f7de-4fa3-b766-23afb9d0ebef
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2371773968 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.2371773968
Directory /workspace/40.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.1937832181
Short name T176
Test name
Test status
Simulation time 1329430000 ps
CPU time 2.86 seconds
Started Aug 07 04:24:49 PM PDT 24
Finished Aug 07 04:24:55 PM PDT 24
Peak memory 164464 kb
Host smart-0f4cb621-069d-4c9b-b586-b8ebe279f2bb
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1937832181 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.1937832181
Directory /workspace/41.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.4022128619
Short name T180
Test name
Test status
Simulation time 1534550000 ps
CPU time 3.28 seconds
Started Aug 07 04:24:48 PM PDT 24
Finished Aug 07 04:24:56 PM PDT 24
Peak memory 164464 kb
Host smart-163821f2-ebd1-4275-bd90-32c5e35719f4
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4022128619 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.4022128619
Directory /workspace/42.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1694166619
Short name T159
Test name
Test status
Simulation time 1495250000 ps
CPU time 4.01 seconds
Started Aug 07 04:24:55 PM PDT 24
Finished Aug 07 04:25:04 PM PDT 24
Peak memory 164316 kb
Host smart-a719c798-8a5a-423f-84c0-d93be63015d3
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1694166619 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.1694166619
Directory /workspace/43.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.980730607
Short name T165
Test name
Test status
Simulation time 1349030000 ps
CPU time 4.81 seconds
Started Aug 07 04:23:15 PM PDT 24
Finished Aug 07 04:23:26 PM PDT 24
Peak memory 164720 kb
Host smart-b47ec914-714a-4c57-9f79-a699279627bd
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=980730607 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.980730607
Directory /workspace/44.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.3328443094
Short name T160
Test name
Test status
Simulation time 1587070000 ps
CPU time 4.07 seconds
Started Aug 07 04:24:23 PM PDT 24
Finished Aug 07 04:24:32 PM PDT 24
Peak memory 164324 kb
Host smart-84ccc019-9c46-45bc-a013-428d951486d9
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3328443094 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.3328443094
Directory /workspace/45.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.2660214107
Short name T192
Test name
Test status
Simulation time 1607350000 ps
CPU time 4.19 seconds
Started Aug 07 04:24:55 PM PDT 24
Finished Aug 07 04:25:05 PM PDT 24
Peak memory 164316 kb
Host smart-af26c169-085d-433d-a9e3-2a9516b5b514
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2660214107 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.2660214107
Directory /workspace/46.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.4261785502
Short name T195
Test name
Test status
Simulation time 1437110000 ps
CPU time 4.88 seconds
Started Aug 07 04:24:55 PM PDT 24
Finished Aug 07 04:25:07 PM PDT 24
Peak memory 164848 kb
Host smart-d11df7b1-0637-4c19-9acb-bc0454f7eb00
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4261785502 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.4261785502
Directory /workspace/47.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.4037516713
Short name T175
Test name
Test status
Simulation time 1485090000 ps
CPU time 3.72 seconds
Started Aug 07 04:24:23 PM PDT 24
Finished Aug 07 04:24:31 PM PDT 24
Peak memory 164328 kb
Host smart-1167c475-afc3-4c9f-9320-7b733b55121b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4037516713 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.4037516713
Directory /workspace/48.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.1738048453
Short name T189
Test name
Test status
Simulation time 1575490000 ps
CPU time 3.47 seconds
Started Aug 07 04:24:36 PM PDT 24
Finished Aug 07 04:24:44 PM PDT 24
Peak memory 164316 kb
Host smart-5a126041-85b3-4a15-ad6a-9dd106d423f2
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1738048453 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.1738048453
Directory /workspace/49.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.2093060270
Short name T162
Test name
Test status
Simulation time 1443770000 ps
CPU time 4.33 seconds
Started Aug 07 04:24:27 PM PDT 24
Finished Aug 07 04:24:36 PM PDT 24
Peak memory 164244 kb
Host smart-c331f6d1-d7ea-4b07-a91b-9f3b1b2e6a96
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2093060270 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.2093060270
Directory /workspace/5.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.754265190
Short name T164
Test name
Test status
Simulation time 1405630000 ps
CPU time 3.67 seconds
Started Aug 07 04:24:09 PM PDT 24
Finished Aug 07 04:24:17 PM PDT 24
Peak memory 164328 kb
Host smart-372ee2ad-06db-4d68-ba9f-f08443bc581a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=754265190 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.754265190
Directory /workspace/6.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.48176216
Short name T169
Test name
Test status
Simulation time 1481610000 ps
CPU time 4.34 seconds
Started Aug 07 04:21:05 PM PDT 24
Finished Aug 07 04:21:14 PM PDT 24
Peak memory 164744 kb
Host smart-99f343f5-e860-4bfa-852c-65a839dafedf
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=48176216 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.48176216
Directory /workspace/7.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.33294083
Short name T173
Test name
Test status
Simulation time 1319350000 ps
CPU time 3.71 seconds
Started Aug 07 04:22:53 PM PDT 24
Finished Aug 07 04:23:01 PM PDT 24
Peak memory 164724 kb
Host smart-109c2b65-7bdc-42cf-9eb3-644d7da63145
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=33294083 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.33294083
Directory /workspace/8.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.3347754396
Short name T182
Test name
Test status
Simulation time 1516170000 ps
CPU time 5.21 seconds
Started Aug 07 04:24:06 PM PDT 24
Finished Aug 07 04:24:18 PM PDT 24
Peak memory 164304 kb
Host smart-96de7b1d-a1ec-4a3c-aa3b-6150de778cf7
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3347754396 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.3347754396
Directory /workspace/9.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.2664643450
Short name T12
Test name
Test status
Simulation time 1490990000 ps
CPU time 3.71 seconds
Started Aug 07 04:24:05 PM PDT 24
Finished Aug 07 04:24:13 PM PDT 24
Peak memory 162804 kb
Host smart-fd783afa-6ae7-4235-8c2b-6787e5311bd5
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2664643450 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.2664643450
Directory /workspace/1.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.3766711046
Short name T54
Test name
Test status
Simulation time 1440930000 ps
CPU time 5.15 seconds
Started Aug 07 04:23:07 PM PDT 24
Finished Aug 07 04:23:19 PM PDT 24
Peak memory 164708 kb
Host smart-02008ac8-925a-4c4d-aefc-8ad90645f152
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3766711046 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.3766711046
Directory /workspace/10.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.2941110350
Short name T36
Test name
Test status
Simulation time 1578510000 ps
CPU time 4.03 seconds
Started Aug 07 04:24:19 PM PDT 24
Finished Aug 07 04:24:27 PM PDT 24
Peak memory 164276 kb
Host smart-327a1c95-5205-453e-b3fe-9cc6ab8b252e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2941110350 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.2941110350
Directory /workspace/11.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.2712156296
Short name T43
Test name
Test status
Simulation time 1501990000 ps
CPU time 4.63 seconds
Started Aug 07 04:21:27 PM PDT 24
Finished Aug 07 04:21:37 PM PDT 24
Peak memory 164708 kb
Host smart-92537232-ca30-40b8-a8ce-c43b9db8d218
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2712156296 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.2712156296
Directory /workspace/12.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.3814023814
Short name T2
Test name
Test status
Simulation time 1491850000 ps
CPU time 4.78 seconds
Started Aug 07 04:20:29 PM PDT 24
Finished Aug 07 04:20:39 PM PDT 24
Peak memory 164788 kb
Host smart-d0d74bd5-8338-4369-a854-686cd0994edf
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3814023814 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.3814023814
Directory /workspace/13.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.2760702684
Short name T67
Test name
Test status
Simulation time 1592570000 ps
CPU time 4.72 seconds
Started Aug 07 04:19:52 PM PDT 24
Finished Aug 07 04:20:03 PM PDT 24
Peak memory 164780 kb
Host smart-97a13981-a8b9-4688-bfd4-76ea525beaf1
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2760702684 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.2760702684
Directory /workspace/14.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.2384071252
Short name T42
Test name
Test status
Simulation time 1415730000 ps
CPU time 3.9 seconds
Started Aug 07 04:20:09 PM PDT 24
Finished Aug 07 04:20:18 PM PDT 24
Peak memory 164736 kb
Host smart-801fe763-5ebb-4f4f-bae3-00b67a82d8ac
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2384071252 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.2384071252
Directory /workspace/15.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.1299805896
Short name T10
Test name
Test status
Simulation time 1533950000 ps
CPU time 3.99 seconds
Started Aug 07 04:25:01 PM PDT 24
Finished Aug 07 04:25:10 PM PDT 24
Peak memory 164500 kb
Host smart-2218535b-decf-40d8-9a64-230e7848a77b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1299805896 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.1299805896
Directory /workspace/16.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.410382138
Short name T39
Test name
Test status
Simulation time 1437930000 ps
CPU time 4.79 seconds
Started Aug 07 04:24:07 PM PDT 24
Finished Aug 07 04:24:18 PM PDT 24
Peak memory 164404 kb
Host smart-b7db7572-5bee-4798-8901-d89a6ef2f2a2
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=410382138 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.410382138
Directory /workspace/17.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.2531167960
Short name T51
Test name
Test status
Simulation time 1501910000 ps
CPU time 3.73 seconds
Started Aug 07 04:24:57 PM PDT 24
Finished Aug 07 04:25:05 PM PDT 24
Peak memory 164464 kb
Host smart-a3c1ba39-b453-42f5-b6dd-cc333638e6bd
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2531167960 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.2531167960
Directory /workspace/18.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.536368962
Short name T59
Test name
Test status
Simulation time 1439310000 ps
CPU time 3.65 seconds
Started Aug 07 04:24:24 PM PDT 24
Finished Aug 07 04:24:32 PM PDT 24
Peak memory 164276 kb
Host smart-5b7b69c5-1bf5-45c9-9ab1-094e5d1108d3
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=536368962 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.536368962
Directory /workspace/19.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.1798229904
Short name T65
Test name
Test status
Simulation time 1399750000 ps
CPU time 3.76 seconds
Started Aug 07 04:24:24 PM PDT 24
Finished Aug 07 04:24:32 PM PDT 24
Peak memory 163976 kb
Host smart-40923dd1-ac97-4249-9e82-471acf51977d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1798229904 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.1798229904
Directory /workspace/2.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.1404045602
Short name T33
Test name
Test status
Simulation time 1276690000 ps
CPU time 3.07 seconds
Started Aug 07 04:24:03 PM PDT 24
Finished Aug 07 04:24:10 PM PDT 24
Peak memory 164320 kb
Host smart-ecff8250-cdb6-4ebf-8661-3f2fd7caf4ea
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1404045602 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.1404045602
Directory /workspace/20.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.3440252855
Short name T68
Test name
Test status
Simulation time 1451930000 ps
CPU time 3.55 seconds
Started Aug 07 04:24:23 PM PDT 24
Finished Aug 07 04:24:31 PM PDT 24
Peak memory 164276 kb
Host smart-31971c51-f05a-4380-ab58-29852335568c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3440252855 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.3440252855
Directory /workspace/21.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.3584296345
Short name T66
Test name
Test status
Simulation time 1509150000 ps
CPU time 3.51 seconds
Started Aug 07 04:19:38 PM PDT 24
Finished Aug 07 04:19:45 PM PDT 24
Peak memory 164788 kb
Host smart-b952d4bc-cd1b-4cee-b181-b29ecc56a139
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3584296345 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.3584296345
Directory /workspace/22.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.848870722
Short name T46
Test name
Test status
Simulation time 1448570000 ps
CPU time 4.88 seconds
Started Aug 07 04:24:06 PM PDT 24
Finished Aug 07 04:24:17 PM PDT 24
Peak memory 163196 kb
Host smart-24d860a1-5990-4274-8ed7-a1eb3ba30c0d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=848870722 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.848870722
Directory /workspace/23.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.621562916
Short name T34
Test name
Test status
Simulation time 1428330000 ps
CPU time 4.27 seconds
Started Aug 07 04:24:27 PM PDT 24
Finished Aug 07 04:24:36 PM PDT 24
Peak memory 164240 kb
Host smart-05aa6e9f-e7cd-4174-b7ed-41d300146a3e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=621562916 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.621562916
Directory /workspace/24.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.997684708
Short name T63
Test name
Test status
Simulation time 1524030000 ps
CPU time 5.07 seconds
Started Aug 07 04:21:55 PM PDT 24
Finished Aug 07 04:22:06 PM PDT 24
Peak memory 164708 kb
Host smart-11e80b54-4aa0-4207-a76c-c94d402e0037
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=997684708 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.997684708
Directory /workspace/25.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.3434179276
Short name T9
Test name
Test status
Simulation time 1429670000 ps
CPU time 4.16 seconds
Started Aug 07 04:20:37 PM PDT 24
Finished Aug 07 04:20:47 PM PDT 24
Peak memory 164728 kb
Host smart-c7c0d6bd-a244-4f48-9c0a-39022d410a73
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3434179276 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.3434179276
Directory /workspace/26.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.3769559006
Short name T45
Test name
Test status
Simulation time 1546090000 ps
CPU time 3.72 seconds
Started Aug 07 04:25:03 PM PDT 24
Finished Aug 07 04:25:12 PM PDT 24
Peak memory 162956 kb
Host smart-2c4245a8-8954-4519-ab46-e452190ac9cc
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3769559006 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.3769559006
Directory /workspace/27.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.3395385390
Short name T44
Test name
Test status
Simulation time 1524650000 ps
CPU time 3.34 seconds
Started Aug 07 04:20:44 PM PDT 24
Finished Aug 07 04:20:51 PM PDT 24
Peak memory 164684 kb
Host smart-bb479c27-9376-45fb-a26b-6ceee761695a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3395385390 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.3395385390
Directory /workspace/28.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.3382853323
Short name T1
Test name
Test status
Simulation time 1635050000 ps
CPU time 4.99 seconds
Started Aug 07 04:22:23 PM PDT 24
Finished Aug 07 04:22:34 PM PDT 24
Peak memory 164708 kb
Host smart-65e5b22e-d6bb-4a95-9cbe-de394be67f62
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3382853323 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.3382853323
Directory /workspace/29.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.3563728835
Short name T53
Test name
Test status
Simulation time 1561870000 ps
CPU time 4.12 seconds
Started Aug 07 04:24:24 PM PDT 24
Finished Aug 07 04:24:33 PM PDT 24
Peak memory 164036 kb
Host smart-a3ab4834-16dc-4aa3-b0d2-18c87d9b7874
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3563728835 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.3563728835
Directory /workspace/3.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.3783654284
Short name T49
Test name
Test status
Simulation time 1415930000 ps
CPU time 4 seconds
Started Aug 07 04:24:47 PM PDT 24
Finished Aug 07 04:24:56 PM PDT 24
Peak memory 164576 kb
Host smart-6bac26a7-228a-4f5f-8111-8dbe38da125b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3783654284 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.3783654284
Directory /workspace/30.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.2719257848
Short name T50
Test name
Test status
Simulation time 1081290000 ps
CPU time 3.8 seconds
Started Aug 07 04:20:44 PM PDT 24
Finished Aug 07 04:20:52 PM PDT 24
Peak memory 164816 kb
Host smart-2245abe6-8e04-4bf4-be27-78b6a5620299
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2719257848 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.2719257848
Directory /workspace/31.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.3394297491
Short name T37
Test name
Test status
Simulation time 1438010000 ps
CPU time 3.55 seconds
Started Aug 07 04:19:35 PM PDT 24
Finished Aug 07 04:19:43 PM PDT 24
Peak memory 164784 kb
Host smart-d49b51cb-9e74-4f43-b1f7-819b6ece3603
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3394297491 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.3394297491
Directory /workspace/32.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.2380726253
Short name T64
Test name
Test status
Simulation time 1511810000 ps
CPU time 3.75 seconds
Started Aug 07 04:25:00 PM PDT 24
Finished Aug 07 04:25:09 PM PDT 24
Peak memory 164500 kb
Host smart-9db7f5c0-b672-47c8-836b-264614ad0a28
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2380726253 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.2380726253
Directory /workspace/33.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.1998009915
Short name T52
Test name
Test status
Simulation time 1453490000 ps
CPU time 3.87 seconds
Started Aug 07 04:24:56 PM PDT 24
Finished Aug 07 04:25:05 PM PDT 24
Peak memory 164316 kb
Host smart-fb4942cd-3d44-47a8-a271-fb51a7e92952
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1998009915 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.1998009915
Directory /workspace/34.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.1404408828
Short name T8
Test name
Test status
Simulation time 1620110000 ps
CPU time 4.19 seconds
Started Aug 07 04:19:36 PM PDT 24
Finished Aug 07 04:19:46 PM PDT 24
Peak memory 164780 kb
Host smart-630c3c65-dd4b-453f-89e7-081d00baff90
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1404408828 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.1404408828
Directory /workspace/35.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.3066727259
Short name T41
Test name
Test status
Simulation time 1575210000 ps
CPU time 3.82 seconds
Started Aug 07 04:24:18 PM PDT 24
Finished Aug 07 04:24:26 PM PDT 24
Peak memory 164316 kb
Host smart-cd228f43-9195-4d2a-b696-3ab04f690e0f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3066727259 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.3066727259
Directory /workspace/36.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.3431092809
Short name T4
Test name
Test status
Simulation time 1525790000 ps
CPU time 4.03 seconds
Started Aug 07 04:24:19 PM PDT 24
Finished Aug 07 04:24:28 PM PDT 24
Peak memory 164556 kb
Host smart-02e66571-2382-487f-8b6c-4f9cdfd08e42
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3431092809 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.3431092809
Directory /workspace/37.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.1164556196
Short name T62
Test name
Test status
Simulation time 1554050000 ps
CPU time 4.56 seconds
Started Aug 07 04:24:26 PM PDT 24
Finished Aug 07 04:24:36 PM PDT 24
Peak memory 163064 kb
Host smart-9f079fd2-4be6-4d92-a956-390329c4a482
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1164556196 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.1164556196
Directory /workspace/38.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.752723556
Short name T11
Test name
Test status
Simulation time 1543950000 ps
CPU time 4.74 seconds
Started Aug 07 04:20:32 PM PDT 24
Finished Aug 07 04:20:43 PM PDT 24
Peak memory 164980 kb
Host smart-ad0c568a-d692-414d-9bd3-7d1875b02c13
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=752723556 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.752723556
Directory /workspace/39.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.3816093219
Short name T32
Test name
Test status
Simulation time 1590010000 ps
CPU time 3.8 seconds
Started Aug 07 04:24:05 PM PDT 24
Finished Aug 07 04:24:14 PM PDT 24
Peak memory 162812 kb
Host smart-45111d58-d4ea-4f96-9ba5-d06641fbf707
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3816093219 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.3816093219
Directory /workspace/4.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.2590089363
Short name T69
Test name
Test status
Simulation time 1409970000 ps
CPU time 4.68 seconds
Started Aug 07 04:24:55 PM PDT 24
Finished Aug 07 04:25:05 PM PDT 24
Peak memory 163664 kb
Host smart-f1d45d32-71a7-47dc-89f9-b9c7e7abf452
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2590089363 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.2590089363
Directory /workspace/40.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.330181342
Short name T58
Test name
Test status
Simulation time 1556330000 ps
CPU time 4.87 seconds
Started Aug 07 04:20:41 PM PDT 24
Finished Aug 07 04:20:52 PM PDT 24
Peak memory 164740 kb
Host smart-6c1cbb6d-9be8-4d4d-ad78-77ff862f3546
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=330181342 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.330181342
Directory /workspace/41.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.1490932886
Short name T31
Test name
Test status
Simulation time 1482650000 ps
CPU time 4.7 seconds
Started Aug 07 04:22:24 PM PDT 24
Finished Aug 07 04:22:34 PM PDT 24
Peak memory 164708 kb
Host smart-1108430d-f29b-472a-bc9b-02e4c2887dad
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1490932886 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.1490932886
Directory /workspace/42.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.2566398999
Short name T57
Test name
Test status
Simulation time 1448350000 ps
CPU time 4.02 seconds
Started Aug 07 04:24:19 PM PDT 24
Finished Aug 07 04:24:28 PM PDT 24
Peak memory 164324 kb
Host smart-53fcb9df-193b-4fb3-a265-e0cb896abddc
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2566398999 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.2566398999
Directory /workspace/43.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.2680542112
Short name T35
Test name
Test status
Simulation time 1009150000 ps
CPU time 3.69 seconds
Started Aug 07 04:20:54 PM PDT 24
Finished Aug 07 04:21:02 PM PDT 24
Peak memory 164708 kb
Host smart-2ef2af26-4984-4ea4-9bd2-1552f2edccd6
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2680542112 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.2680542112
Directory /workspace/44.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.900622226
Short name T40
Test name
Test status
Simulation time 1393830000 ps
CPU time 4.28 seconds
Started Aug 07 04:24:50 PM PDT 24
Finished Aug 07 04:25:00 PM PDT 24
Peak memory 164244 kb
Host smart-860a48c5-f212-4203-a68c-45efd6f54a50
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=900622226 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.900622226
Directory /workspace/45.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.955325324
Short name T48
Test name
Test status
Simulation time 1454010000 ps
CPU time 3.8 seconds
Started Aug 07 04:20:21 PM PDT 24
Finished Aug 07 04:20:29 PM PDT 24
Peak memory 164740 kb
Host smart-ae02cfc9-de9f-42d3-b637-5c3cc7045752
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=955325324 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.955325324
Directory /workspace/46.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.3853813740
Short name T38
Test name
Test status
Simulation time 1530830000 ps
CPU time 3.96 seconds
Started Aug 07 04:19:43 PM PDT 24
Finished Aug 07 04:19:51 PM PDT 24
Peak memory 164728 kb
Host smart-73049ac6-1637-4f82-b3ac-05a5c9e6be0a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3853813740 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.3853813740
Directory /workspace/47.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.3259201177
Short name T70
Test name
Test status
Simulation time 1471010000 ps
CPU time 3.95 seconds
Started Aug 07 04:20:29 PM PDT 24
Finished Aug 07 04:20:38 PM PDT 24
Peak memory 164788 kb
Host smart-82c89285-7ba7-49a3-a896-7718cd873310
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3259201177 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.3259201177
Directory /workspace/48.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.1142297665
Short name T60
Test name
Test status
Simulation time 1441070000 ps
CPU time 4.53 seconds
Started Aug 07 04:25:26 PM PDT 24
Finished Aug 07 04:25:36 PM PDT 24
Peak memory 163488 kb
Host smart-a1a5456d-2be7-4168-a497-41ca9fae25b4
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1142297665 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.1142297665
Directory /workspace/49.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.3881363198
Short name T55
Test name
Test status
Simulation time 1366650000 ps
CPU time 3.09 seconds
Started Aug 07 04:25:00 PM PDT 24
Finished Aug 07 04:25:06 PM PDT 24
Peak memory 164696 kb
Host smart-e3955311-43d6-430a-9faf-784f2c644838
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3881363198 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.3881363198
Directory /workspace/5.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.2936987279
Short name T47
Test name
Test status
Simulation time 1357870000 ps
CPU time 4.2 seconds
Started Aug 07 04:24:39 PM PDT 24
Finished Aug 07 04:24:49 PM PDT 24
Peak memory 163648 kb
Host smart-025b86c4-5ff5-4149-a5a9-7ab7137e433b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2936987279 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.2936987279
Directory /workspace/6.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.2871452728
Short name T61
Test name
Test status
Simulation time 1391890000 ps
CPU time 4.41 seconds
Started Aug 07 04:24:39 PM PDT 24
Finished Aug 07 04:24:49 PM PDT 24
Peak memory 162992 kb
Host smart-580956b4-7668-4e23-adaa-4ce0470568e6
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2871452728 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.2871452728
Directory /workspace/7.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.651370318
Short name T3
Test name
Test status
Simulation time 1495150000 ps
CPU time 3.69 seconds
Started Aug 07 04:25:03 PM PDT 24
Finished Aug 07 04:25:12 PM PDT 24
Peak memory 162800 kb
Host smart-26b1e9bb-bf05-45f2-99da-4c8129d5e193
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=651370318 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.651370318
Directory /workspace/8.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.4175516105
Short name T56
Test name
Test status
Simulation time 1396010000 ps
CPU time 3.98 seconds
Started Aug 07 04:25:00 PM PDT 24
Finished Aug 07 04:25:09 PM PDT 24
Peak memory 164504 kb
Host smart-560994f8-552a-4d2a-856d-b7650dae1c17
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4175516105 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.4175516105
Directory /workspace/9.prim_lfsr_gal_smoke/latest
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