Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.31 100.00 96.55 100.00 100.00 95.00


Total tests in report: 200
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
87.31 87.31 100.00 100.00 96.55 96.55 100.00 100.00 100.00 100.00 40.00 40.00 /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.3837606339
95.31 8.00 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 80.00 40.00 /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.2546584551
98.31 3.00 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 95.00 15.00 /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.4259126149

Tests that do not contribute to grading

Name
/workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.146870368
/workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.3983214260
/workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.1182780284
/workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.31853923
/workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.3454913228
/workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.4099273583
/workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.1443297085
/workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.2371701940
/workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.14298107
/workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.3795646055
/workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.3286627278
/workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.1256870679
/workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.631314670
/workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.1227283709
/workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.1117417051
/workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.764182326
/workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.84878504
/workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.2307087074
/workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1558930845
/workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.3706300231
/workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.2456605172
/workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.3696211592
/workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.3868084437
/workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.2958761372
/workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.2549897237
/workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.3192166790
/workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.135347913
/workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.2964566846
/workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.165146155
/workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.3981323956
/workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.326524145
/workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.3813114723
/workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.2619842012
/workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.1139316365
/workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.2469035621
/workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.2812804612
/workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.735853177
/workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.918274411
/workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.2223649515
/workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.1322168458
/workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.577305951
/workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.976634602
/workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.2992073847
/workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.3487874123
/workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.1457616843
/workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.497083175
/workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.4176747232
/workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.3497799734
/workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.1368409132
/workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.780267353
/workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.3319207355
/workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.2313810962
/workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.4059307227
/workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.688556085
/workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.979284595
/workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.3263653570
/workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.968537118
/workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.4082155018
/workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.1177446246
/workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.1431610724
/workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.882007353
/workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.2867929679
/workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.2437238447
/workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.1897520866
/workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.3595850969
/workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.1061397223
/workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.2105173952
/workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.4018268791
/workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.126633784
/workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.1377255906
/workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.3645142361
/workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.3323856371
/workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.3589063221
/workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.2825644167
/workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.2369064454
/workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.3114702210
/workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.1755545004
/workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.1879850301
/workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.3218587502
/workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.2535644497
/workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.94930498
/workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.2824875368
/workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.342586453
/workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.3746544222
/workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.3730785422
/workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.3675123200
/workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.2786810867
/workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.1830642636
/workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.2728246490
/workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.3599608335
/workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.746277666
/workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1570185093
/workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.2987497183
/workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.73592732
/workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.2616906978
/workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.333227948
/workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.1262528018
/workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.392028177
/workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.3047335247
/workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.703057848
/workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.79269198
/workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.3093129768
/workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.3395636583
/workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.2074583681
/workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.3950838781
/workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.2252171005
/workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.98163345
/workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.1315176795
/workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.98684850
/workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.547449937
/workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.2841753740
/workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.1962007244
/workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.76045662
/workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.4278863723
/workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.1266367457
/workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.3967997880
/workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.3885547871
/workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2868945716
/workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.118629717
/workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.2841906171
/workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.2368954666
/workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.3531143380
/workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.703927770
/workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.450943834
/workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.3992290068
/workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.1951723523
/workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.3541721712
/workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.1608754291
/workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.1432496405
/workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1129723782
/workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.3049116642
/workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.1871043287
/workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3856943708
/workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.1237177231
/workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.3320760627
/workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.3933713471
/workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.779722460
/workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.3752175221
/workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.1621345930
/workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.1330421732
/workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.2337828633
/workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.347345501
/workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.3925154970
/workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.3573509542
/workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.3902072310
/workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.3668322979
/workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1603006454
/workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.3543866264
/workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.3313222936
/workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.2078656028
/workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.3308015113
/workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.256053012
/workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.3054318421
/workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.3001175652
/workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.2829671568
/workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.3600857578
/workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.552302597
/workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.2846675091
/workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.318658430
/workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.4002781896
/workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.2943623120
/workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.100635690
/workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.3551682451
/workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.1541452820
/workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.2810171064
/workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.1961566708
/workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.647995681
/workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.1228695968
/workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.2965364066
/workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.1183296940
/workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.2566762874
/workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.497965697
/workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.2288998861
/workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.1155822565
/workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.1033967748
/workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.3293991994
/workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.2791493767
/workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.2424350684
/workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.1552132150
/workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.2141753810
/workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.2212938905
/workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.3981815534
/workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.302309814
/workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.1955214497
/workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.3543343214
/workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.2465667743
/workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.2512493701
/workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.3492602383
/workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.2870788455
/workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.4281045923
/workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.3653709658
/workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.1863734734
/workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.1587203991
/workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.3340414974
/workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.950030700
/workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.3221209573
/workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.579867658



Total test records in report: 200
tests.html | tests1.html | tests2.html | tests3.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.3221209573 Aug 08 05:04:26 PM PDT 24 Aug 08 05:04:33 PM PDT 24 1140170000 ps
T2 /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.3293991994 Aug 08 05:04:33 PM PDT 24 Aug 08 05:04:47 PM PDT 24 1589450000 ps
T3 /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.950030700 Aug 08 05:04:27 PM PDT 24 Aug 08 05:04:37 PM PDT 24 1552890000 ps
T4 /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.3837606339 Aug 08 05:04:20 PM PDT 24 Aug 08 05:04:31 PM PDT 24 1406450000 ps
T8 /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.2141753810 Aug 08 05:04:33 PM PDT 24 Aug 08 05:04:41 PM PDT 24 1582150000 ps
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T68 /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.2829671568 Aug 08 05:04:25 PM PDT 24 Aug 08 05:04:34 PM PDT 24 1338530000 ps
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T70 /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.3600857578 Aug 08 05:04:26 PM PDT 24 Aug 08 05:04:35 PM PDT 24 1489850000 ps
T14 /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.2825644167 Aug 08 05:04:29 PM PDT 24 Aug 08 05:39:10 PM PDT 24 336533150000 ps
T15 /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.2546584551 Aug 08 05:04:10 PM PDT 24 Aug 08 05:39:32 PM PDT 24 336424950000 ps
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T17 /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.3730785422 Aug 08 05:04:30 PM PDT 24 Aug 08 05:35:55 PM PDT 24 336334050000 ps
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T19 /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.3114702210 Aug 08 05:04:22 PM PDT 24 Aug 08 05:38:11 PM PDT 24 336918610000 ps
T20 /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.3645142361 Aug 08 05:04:10 PM PDT 24 Aug 08 05:36:19 PM PDT 24 336630330000 ps
T21 /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.1830642636 Aug 08 05:04:22 PM PDT 24 Aug 08 05:43:04 PM PDT 24 336992550000 ps
T22 /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.2728246490 Aug 08 05:04:20 PM PDT 24 Aug 08 05:36:46 PM PDT 24 336665270000 ps
T23 /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.1061397223 Aug 08 05:04:14 PM PDT 24 Aug 08 05:34:22 PM PDT 24 336361330000 ps
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T73 /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.2313810962 Aug 08 05:04:23 PM PDT 24 Aug 08 05:41:40 PM PDT 24 336978450000 ps
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T81 /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.3675123200 Aug 08 05:04:25 PM PDT 24 Aug 08 05:32:53 PM PDT 24 336919070000 ps
T82 /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.2105173952 Aug 08 05:04:11 PM PDT 24 Aug 08 05:39:13 PM PDT 24 336565890000 ps
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T95 /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.2616906978 Aug 08 05:04:12 PM PDT 24 Aug 08 05:37:29 PM PDT 24 336636290000 ps
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T128 /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.3706300231 Aug 08 05:04:25 PM PDT 24 Aug 08 05:36:20 PM PDT 24 336510810000 ps
T129 /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.631314670 Aug 08 05:04:25 PM PDT 24 Aug 08 05:32:39 PM PDT 24 336439370000 ps
T130 /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.14298107 Aug 08 05:04:29 PM PDT 24 Aug 08 05:33:55 PM PDT 24 337090270000 ps
T131 /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.1457616843 Aug 08 05:04:33 PM PDT 24 Aug 08 05:39:22 PM PDT 24 336666670000 ps
T132 /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.2812804612 Aug 08 05:04:26 PM PDT 24 Aug 08 05:35:46 PM PDT 24 336979830000 ps
T133 /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.135347913 Aug 08 05:04:34 PM PDT 24 Aug 08 05:35:20 PM PDT 24 336701870000 ps
T134 /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.2223649515 Aug 08 05:04:34 PM PDT 24 Aug 08 05:38:57 PM PDT 24 337037610000 ps
T135 /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.3454913228 Aug 08 05:04:23 PM PDT 24 Aug 08 05:37:14 PM PDT 24 336971950000 ps
T136 /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.976634602 Aug 08 05:04:25 PM PDT 24 Aug 08 05:31:48 PM PDT 24 336896790000 ps
T137 /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.764182326 Aug 08 05:04:32 PM PDT 24 Aug 08 05:36:18 PM PDT 24 336784310000 ps
T138 /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.4176747232 Aug 08 05:04:21 PM PDT 24 Aug 08 05:38:07 PM PDT 24 337019250000 ps
T139 /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.84878504 Aug 08 05:04:30 PM PDT 24 Aug 08 05:42:13 PM PDT 24 336392170000 ps
T140 /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.165146155 Aug 08 05:04:31 PM PDT 24 Aug 08 05:41:56 PM PDT 24 337126610000 ps
T141 /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.2549897237 Aug 08 05:04:31 PM PDT 24 Aug 08 05:40:10 PM PDT 24 336465250000 ps
T142 /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.326524145 Aug 08 05:04:31 PM PDT 24 Aug 08 05:38:15 PM PDT 24 336980190000 ps
T143 /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.146870368 Aug 08 05:04:31 PM PDT 24 Aug 08 05:33:46 PM PDT 24 336557730000 ps
T144 /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.2371701940 Aug 08 05:04:23 PM PDT 24 Aug 08 05:31:06 PM PDT 24 337076090000 ps
T145 /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.3813114723 Aug 08 05:04:33 PM PDT 24 Aug 08 05:31:53 PM PDT 24 336670010000 ps
T146 /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.2619842012 Aug 08 05:04:34 PM PDT 24 Aug 08 05:38:50 PM PDT 24 336664630000 ps
T147 /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.1117417051 Aug 08 05:04:32 PM PDT 24 Aug 08 05:32:00 PM PDT 24 336930230000 ps
T148 /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1558930845 Aug 08 05:04:31 PM PDT 24 Aug 08 05:39:51 PM PDT 24 336727030000 ps
T149 /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.3497799734 Aug 08 05:04:25 PM PDT 24 Aug 08 05:37:39 PM PDT 24 336860830000 ps
T150 /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.577305951 Aug 08 05:04:26 PM PDT 24 Aug 08 05:31:36 PM PDT 24 336539330000 ps
T151 /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2868945716 Aug 08 05:04:35 PM PDT 24 Aug 08 05:04:44 PM PDT 24 1275070000 ps
T152 /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.3541721712 Aug 08 05:04:35 PM PDT 24 Aug 08 05:04:47 PM PDT 24 1477450000 ps
T153 /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.3950838781 Aug 08 05:04:45 PM PDT 24 Aug 08 05:04:58 PM PDT 24 1538650000 ps
T154 /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.3885547871 Aug 08 05:04:33 PM PDT 24 Aug 08 05:04:44 PM PDT 24 1477150000 ps
T155 /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.79269198 Aug 08 05:04:35 PM PDT 24 Aug 08 05:04:42 PM PDT 24 1302350000 ps
T156 /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.76045662 Aug 08 05:04:31 PM PDT 24 Aug 08 05:04:39 PM PDT 24 1250650000 ps
T157 /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.98163345 Aug 08 05:04:41 PM PDT 24 Aug 08 05:04:54 PM PDT 24 1525670000 ps
T158 /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.1951723523 Aug 08 05:04:37 PM PDT 24 Aug 08 05:04:47 PM PDT 24 1524910000 ps
T159 /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1129723782 Aug 08 05:04:33 PM PDT 24 Aug 08 05:04:44 PM PDT 24 1532370000 ps
T160 /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.703927770 Aug 08 05:04:32 PM PDT 24 Aug 08 05:04:41 PM PDT 24 1325170000 ps
T161 /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.3093129768 Aug 08 05:04:30 PM PDT 24 Aug 08 05:04:41 PM PDT 24 1505410000 ps
T162 /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.4278863723 Aug 08 05:04:34 PM PDT 24 Aug 08 05:04:44 PM PDT 24 1466510000 ps
T163 /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.347345501 Aug 08 05:04:38 PM PDT 24 Aug 08 05:04:48 PM PDT 24 1549670000 ps
T164 /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.3992290068 Aug 08 05:04:36 PM PDT 24 Aug 08 05:04:48 PM PDT 24 1467130000 ps
T165 /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.3752175221 Aug 08 05:04:38 PM PDT 24 Aug 08 05:04:49 PM PDT 24 1529590000 ps
T166 /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.1432496405 Aug 08 05:04:47 PM PDT 24 Aug 08 05:04:55 PM PDT 24 1393730000 ps
T167 /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.3531143380 Aug 08 05:04:33 PM PDT 24 Aug 08 05:04:47 PM PDT 24 1586250000 ps
T168 /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.1621345930 Aug 08 05:04:39 PM PDT 24 Aug 08 05:04:51 PM PDT 24 1312690000 ps
T169 /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.3933713471 Aug 08 05:04:35 PM PDT 24 Aug 08 05:04:47 PM PDT 24 1509590000 ps
T170 /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.1962007244 Aug 08 05:04:34 PM PDT 24 Aug 08 05:04:45 PM PDT 24 1439230000 ps
T171 /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.1237177231 Aug 08 05:04:37 PM PDT 24 Aug 08 05:04:47 PM PDT 24 1583310000 ps
T172 /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.547449937 Aug 08 05:04:37 PM PDT 24 Aug 08 05:04:45 PM PDT 24 1379790000 ps
T173 /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.3320760627 Aug 08 05:04:35 PM PDT 24 Aug 08 05:04:46 PM PDT 24 1439630000 ps
T174 /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.2841906171 Aug 08 05:04:36 PM PDT 24 Aug 08 05:04:45 PM PDT 24 1446990000 ps
T175 /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.3925154970 Aug 08 05:04:37 PM PDT 24 Aug 08 05:04:51 PM PDT 24 1514270000 ps
T176 /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.3668322979 Aug 08 05:04:35 PM PDT 24 Aug 08 05:04:46 PM PDT 24 1527630000 ps
T177 /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1603006454 Aug 08 05:04:31 PM PDT 24 Aug 08 05:04:42 PM PDT 24 1424490000 ps
T178 /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.118629717 Aug 08 05:04:33 PM PDT 24 Aug 08 05:04:43 PM PDT 24 1501730000 ps
T179 /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.2841753740 Aug 08 05:04:46 PM PDT 24 Aug 08 05:04:54 PM PDT 24 1504450000 ps
T180 /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.3543866264 Aug 08 05:04:38 PM PDT 24 Aug 08 05:04:49 PM PDT 24 1506410000 ps
T181 /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.2252171005 Aug 08 05:04:40 PM PDT 24 Aug 08 05:04:51 PM PDT 24 1599170000 ps
T182 /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.3049116642 Aug 08 05:04:45 PM PDT 24 Aug 08 05:04:57 PM PDT 24 1440250000 ps
T183 /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.1266367457 Aug 08 05:04:35 PM PDT 24 Aug 08 05:04:43 PM PDT 24 1314030000 ps
T184 /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.3047335247 Aug 08 05:04:36 PM PDT 24 Aug 08 05:04:46 PM PDT 24 1409590000 ps
T185 /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.1315176795 Aug 08 05:04:38 PM PDT 24 Aug 08 05:04:48 PM PDT 24 1297210000 ps
T186 /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.3902072310 Aug 08 05:04:35 PM PDT 24 Aug 08 05:04:46 PM PDT 24 1526490000 ps
T187 /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.3967997880 Aug 08 05:04:34 PM PDT 24 Aug 08 05:04:45 PM PDT 24 1538770000 ps
T188 /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.1608754291 Aug 08 05:04:33 PM PDT 24 Aug 08 05:04:42 PM PDT 24 1486210000 ps
T189 /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3856943708 Aug 08 05:04:36 PM PDT 24 Aug 08 05:04:46 PM PDT 24 1558010000 ps
T190 /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.1330421732 Aug 08 05:04:34 PM PDT 24 Aug 08 05:04:46 PM PDT 24 1341230000 ps
T191 /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.1871043287 Aug 08 05:04:40 PM PDT 24 Aug 08 05:04:51 PM PDT 24 1545470000 ps
T192 /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.2337828633 Aug 08 05:04:36 PM PDT 24 Aug 08 05:04:46 PM PDT 24 1274110000 ps
T193 /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.3395636583 Aug 08 05:04:34 PM PDT 24 Aug 08 05:04:48 PM PDT 24 1567690000 ps
T194 /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.450943834 Aug 08 05:04:33 PM PDT 24 Aug 08 05:04:45 PM PDT 24 1507790000 ps
T195 /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.2074583681 Aug 08 05:04:39 PM PDT 24 Aug 08 05:04:46 PM PDT 24 1156690000 ps
T196 /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.3573509542 Aug 08 05:04:36 PM PDT 24 Aug 08 05:04:45 PM PDT 24 1506350000 ps
T197 /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.779722460 Aug 08 05:04:32 PM PDT 24 Aug 08 05:04:44 PM PDT 24 1488850000 ps
T198 /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.703057848 Aug 08 05:04:38 PM PDT 24 Aug 08 05:04:47 PM PDT 24 1347790000 ps
T199 /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.98684850 Aug 08 05:04:38 PM PDT 24 Aug 08 05:04:48 PM PDT 24 1415170000 ps
T200 /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.2368954666 Aug 08 05:04:34 PM PDT 24 Aug 08 05:04:44 PM PDT 24 1459150000 ps

Test location /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.3837606339
Short name T4
Test name
Test status
Simulation time 1406450000 ps
CPU time 5.12 seconds
Started Aug 08 05:04:20 PM PDT 24
Finished Aug 08 05:04:31 PM PDT 24
Peak memory 164796 kb
Host smart-3371aa11-7ec3-4134-b307-b2193194d6b7
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3837606339 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.3837606339
Directory /workspace/15.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.2546584551
Short name T15
Test name
Test status
Simulation time 336424950000 ps
CPU time 847.34 seconds
Started Aug 08 05:04:10 PM PDT 24
Finished Aug 08 05:39:32 PM PDT 24
Peak memory 160648 kb
Host smart-806a5d82-9b57-4828-86a9-5cf93c8fb2a0
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2546584551 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.2546584551
Directory /workspace/10.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.4259126149
Short name T7
Test name
Test status
Simulation time 336381250000 ps
CPU time 778.59 seconds
Started Aug 08 05:04:23 PM PDT 24
Finished Aug 08 05:36:26 PM PDT 24
Peak memory 160704 kb
Host smart-90fc85da-db3c-4bf0-8105-3e802716391e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4259126149 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.4259126149
Directory /workspace/13.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.146870368
Short name T143
Test name
Test status
Simulation time 336557730000 ps
CPU time 718.23 seconds
Started Aug 08 05:04:31 PM PDT 24
Finished Aug 08 05:33:46 PM PDT 24
Peak memory 160668 kb
Host smart-454e0c65-c658-4d22-ba27-a4eb13984e52
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=146870368 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.146870368
Directory /workspace/0.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.3983214260
Short name T122
Test name
Test status
Simulation time 336574710000 ps
CPU time 813.05 seconds
Started Aug 08 05:04:33 PM PDT 24
Finished Aug 08 05:38:08 PM PDT 24
Peak memory 160764 kb
Host smart-37bfb88d-49a8-4d60-b1a3-1ccb27da790c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3983214260 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.3983214260
Directory /workspace/1.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.1182780284
Short name T114
Test name
Test status
Simulation time 337065810000 ps
CPU time 824.69 seconds
Started Aug 08 05:04:26 PM PDT 24
Finished Aug 08 05:38:27 PM PDT 24
Peak memory 160740 kb
Host smart-243c7d4b-9077-41c8-bbbe-5eddd8d5778e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1182780284 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.1182780284
Directory /workspace/10.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.31853923
Short name T111
Test name
Test status
Simulation time 336916270000 ps
CPU time 767.53 seconds
Started Aug 08 05:04:28 PM PDT 24
Finished Aug 08 05:36:03 PM PDT 24
Peak memory 160720 kb
Host smart-e563f5b5-ce82-449a-b095-5d0212f3a358
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=31853923 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.31853923
Directory /workspace/11.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.3454913228
Short name T135
Test name
Test status
Simulation time 336971950000 ps
CPU time 803.01 seconds
Started Aug 08 05:04:23 PM PDT 24
Finished Aug 08 05:37:14 PM PDT 24
Peak memory 160768 kb
Host smart-34279fd2-32d6-4413-8ca0-dca7f09c4256
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3454913228 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.3454913228
Directory /workspace/12.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.4099273583
Short name T29
Test name
Test status
Simulation time 337117590000 ps
CPU time 785.17 seconds
Started Aug 08 05:04:27 PM PDT 24
Finished Aug 08 05:36:21 PM PDT 24
Peak memory 160688 kb
Host smart-25f44d1a-fcd9-4efc-8ac4-7ce92b62dffb
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4099273583 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.4099273583
Directory /workspace/14.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.1443297085
Short name T116
Test name
Test status
Simulation time 336713570000 ps
CPU time 770.73 seconds
Started Aug 08 05:04:34 PM PDT 24
Finished Aug 08 05:36:09 PM PDT 24
Peak memory 160780 kb
Host smart-6cf0f2fc-9210-4361-a8c5-660518c2baa3
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1443297085 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.1443297085
Directory /workspace/15.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.2371701940
Short name T144
Test name
Test status
Simulation time 337076090000 ps
CPU time 651.18 seconds
Started Aug 08 05:04:23 PM PDT 24
Finished Aug 08 05:31:06 PM PDT 24
Peak memory 160684 kb
Host smart-e11b8af3-3714-4c19-a3d8-407e83e59b6f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2371701940 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.2371701940
Directory /workspace/16.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.14298107
Short name T130
Test name
Test status
Simulation time 337090270000 ps
CPU time 718.48 seconds
Started Aug 08 05:04:29 PM PDT 24
Finished Aug 08 05:33:55 PM PDT 24
Peak memory 160708 kb
Host smart-46c24b46-090a-44c1-804c-027db2deca0f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=14298107 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.14298107
Directory /workspace/17.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.3795646055
Short name T118
Test name
Test status
Simulation time 336916130000 ps
CPU time 842.01 seconds
Started Aug 08 05:04:26 PM PDT 24
Finished Aug 08 05:38:30 PM PDT 24
Peak memory 160704 kb
Host smart-b18dc607-2f8c-402a-8f89-47a309d7c092
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3795646055 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.3795646055
Directory /workspace/18.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.3286627278
Short name T5
Test name
Test status
Simulation time 336846730000 ps
CPU time 771.03 seconds
Started Aug 08 05:04:25 PM PDT 24
Finished Aug 08 05:36:03 PM PDT 24
Peak memory 160784 kb
Host smart-4ca353d3-2a99-4435-b44c-9f015fdabee6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3286627278 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.3286627278
Directory /workspace/19.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.1256870679
Short name T28
Test name
Test status
Simulation time 336913270000 ps
CPU time 943.03 seconds
Started Aug 08 05:04:28 PM PDT 24
Finished Aug 08 05:43:18 PM PDT 24
Peak memory 160764 kb
Host smart-f95561ff-bee4-4190-bbcb-ee02c9a883a2
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1256870679 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.1256870679
Directory /workspace/2.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.631314670
Short name T129
Test name
Test status
Simulation time 336439370000 ps
CPU time 687.75 seconds
Started Aug 08 05:04:25 PM PDT 24
Finished Aug 08 05:32:39 PM PDT 24
Peak memory 160724 kb
Host smart-3c8338cb-751c-4b8d-bc0f-563f7718d298
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=631314670 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.631314670
Directory /workspace/20.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.1227283709
Short name T27
Test name
Test status
Simulation time 336752690000 ps
CPU time 791.75 seconds
Started Aug 08 05:04:29 PM PDT 24
Finished Aug 08 05:37:16 PM PDT 24
Peak memory 160704 kb
Host smart-287a08b2-c448-45d7-b397-2dabfd9bbfc9
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1227283709 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.1227283709
Directory /workspace/21.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.1117417051
Short name T147
Test name
Test status
Simulation time 336930230000 ps
CPU time 668.88 seconds
Started Aug 08 05:04:32 PM PDT 24
Finished Aug 08 05:32:00 PM PDT 24
Peak memory 160716 kb
Host smart-eacfc312-a065-423a-bbdd-04cc2c72681a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1117417051 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.1117417051
Directory /workspace/22.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.764182326
Short name T137
Test name
Test status
Simulation time 336784310000 ps
CPU time 777.61 seconds
Started Aug 08 05:04:32 PM PDT 24
Finished Aug 08 05:36:18 PM PDT 24
Peak memory 160696 kb
Host smart-956b205a-c13f-40ae-b308-2328166afb09
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=764182326 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.764182326
Directory /workspace/23.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.84878504
Short name T139
Test name
Test status
Simulation time 336392170000 ps
CPU time 916.4 seconds
Started Aug 08 05:04:30 PM PDT 24
Finished Aug 08 05:42:13 PM PDT 24
Peak memory 160792 kb
Host smart-a5b7b556-4f7f-41a1-ae11-17617b6592e8
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=84878504 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.84878504
Directory /workspace/24.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.2307087074
Short name T123
Test name
Test status
Simulation time 337029150000 ps
CPU time 835.24 seconds
Started Aug 08 05:04:32 PM PDT 24
Finished Aug 08 05:38:54 PM PDT 24
Peak memory 160768 kb
Host smart-953ea895-c159-4e9e-8e35-14bdf6f801c7
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2307087074 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.2307087074
Directory /workspace/25.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1558930845
Short name T148
Test name
Test status
Simulation time 336727030000 ps
CPU time 844.6 seconds
Started Aug 08 05:04:31 PM PDT 24
Finished Aug 08 05:39:51 PM PDT 24
Peak memory 160652 kb
Host smart-7d353d92-6cdc-4981-8a30-305b92547cae
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1558930845 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.1558930845
Directory /workspace/26.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.3706300231
Short name T128
Test name
Test status
Simulation time 336510810000 ps
CPU time 788.53 seconds
Started Aug 08 05:04:25 PM PDT 24
Finished Aug 08 05:36:20 PM PDT 24
Peak memory 160816 kb
Host smart-e3cec59a-e64a-4cfe-868f-b7920a8f175b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3706300231 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.3706300231
Directory /workspace/27.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.2456605172
Short name T25
Test name
Test status
Simulation time 336533270000 ps
CPU time 788.13 seconds
Started Aug 08 05:04:22 PM PDT 24
Finished Aug 08 05:36:13 PM PDT 24
Peak memory 160688 kb
Host smart-38199ecd-cc0f-47e4-9957-0c5950220857
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2456605172 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.2456605172
Directory /workspace/28.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.3696211592
Short name T117
Test name
Test status
Simulation time 336716990000 ps
CPU time 915.45 seconds
Started Aug 08 05:04:31 PM PDT 24
Finished Aug 08 05:42:13 PM PDT 24
Peak memory 160784 kb
Host smart-770d06a6-64c2-4b7a-a4d8-f98203b6adc4
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3696211592 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.3696211592
Directory /workspace/29.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.3868084437
Short name T30
Test name
Test status
Simulation time 336902370000 ps
CPU time 715.59 seconds
Started Aug 08 05:04:23 PM PDT 24
Finished Aug 08 05:33:39 PM PDT 24
Peak memory 160748 kb
Host smart-ffa3ac17-3ae1-4e41-9f99-c227e8537191
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3868084437 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.3868084437
Directory /workspace/3.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.2958761372
Short name T127
Test name
Test status
Simulation time 337105110000 ps
CPU time 931.45 seconds
Started Aug 08 05:04:25 PM PDT 24
Finished Aug 08 05:42:50 PM PDT 24
Peak memory 160740 kb
Host smart-548b729c-9399-4aaa-9603-217a4ec13262
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2958761372 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.2958761372
Directory /workspace/30.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.2549897237
Short name T141
Test name
Test status
Simulation time 336465250000 ps
CPU time 847.98 seconds
Started Aug 08 05:04:31 PM PDT 24
Finished Aug 08 05:40:10 PM PDT 24
Peak memory 160648 kb
Host smart-6fb92399-32df-4031-a1e9-5c79bc440077
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2549897237 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.2549897237
Directory /workspace/31.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.3192166790
Short name T125
Test name
Test status
Simulation time 336416230000 ps
CPU time 909.17 seconds
Started Aug 08 05:04:37 PM PDT 24
Finished Aug 08 05:41:56 PM PDT 24
Peak memory 160784 kb
Host smart-34288b11-e9b1-4bcd-94e0-a9097c8831b3
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3192166790 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.3192166790
Directory /workspace/32.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.135347913
Short name T133
Test name
Test status
Simulation time 336701870000 ps
CPU time 755.04 seconds
Started Aug 08 05:04:34 PM PDT 24
Finished Aug 08 05:35:20 PM PDT 24
Peak memory 160688 kb
Host smart-ca252855-71ed-4184-8f61-452d09106c55
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=135347913 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.135347913
Directory /workspace/33.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.2964566846
Short name T124
Test name
Test status
Simulation time 336708910000 ps
CPU time 764.53 seconds
Started Aug 08 05:04:29 PM PDT 24
Finished Aug 08 05:35:46 PM PDT 24
Peak memory 160768 kb
Host smart-2ff9088e-39bb-4618-9880-447823bbe85b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2964566846 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.2964566846
Directory /workspace/34.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.165146155
Short name T140
Test name
Test status
Simulation time 337126610000 ps
CPU time 908.28 seconds
Started Aug 08 05:04:31 PM PDT 24
Finished Aug 08 05:41:56 PM PDT 24
Peak memory 160776 kb
Host smart-e32ee74b-e875-419b-b46c-0805d8e67dc0
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=165146155 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.165146155
Directory /workspace/35.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.3981323956
Short name T113
Test name
Test status
Simulation time 336750570000 ps
CPU time 851.89 seconds
Started Aug 08 05:04:32 PM PDT 24
Finished Aug 08 05:39:20 PM PDT 24
Peak memory 160068 kb
Host smart-ab726f33-6d0e-4ac4-ac40-b835da98efe4
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3981323956 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.3981323956
Directory /workspace/36.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.326524145
Short name T142
Test name
Test status
Simulation time 336980190000 ps
CPU time 820.12 seconds
Started Aug 08 05:04:31 PM PDT 24
Finished Aug 08 05:38:15 PM PDT 24
Peak memory 160764 kb
Host smart-00ac2c2c-f092-444d-9a23-1c57d56756e9
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=326524145 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.326524145
Directory /workspace/37.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.3813114723
Short name T145
Test name
Test status
Simulation time 336670010000 ps
CPU time 663.17 seconds
Started Aug 08 05:04:33 PM PDT 24
Finished Aug 08 05:31:53 PM PDT 24
Peak memory 160740 kb
Host smart-f88b3230-1579-4959-a3c9-58bd2cea86f2
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3813114723 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.3813114723
Directory /workspace/38.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.2619842012
Short name T146
Test name
Test status
Simulation time 336664630000 ps
CPU time 834.62 seconds
Started Aug 08 05:04:34 PM PDT 24
Finished Aug 08 05:38:50 PM PDT 24
Peak memory 160652 kb
Host smart-94210f24-8e3c-463c-88f2-bc53c1a5869a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2619842012 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.2619842012
Directory /workspace/39.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.1139316365
Short name T24
Test name
Test status
Simulation time 336352170000 ps
CPU time 817.27 seconds
Started Aug 08 05:04:25 PM PDT 24
Finished Aug 08 05:38:15 PM PDT 24
Peak memory 160812 kb
Host smart-3cd71562-5d9b-46c4-97d2-02d9044cdb24
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1139316365 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.1139316365
Directory /workspace/4.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.2469035621
Short name T119
Test name
Test status
Simulation time 336714070000 ps
CPU time 735.78 seconds
Started Aug 08 05:04:22 PM PDT 24
Finished Aug 08 05:34:03 PM PDT 24
Peak memory 160704 kb
Host smart-03a5d314-a9c2-474e-a9aa-2e919d64f06c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2469035621 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.2469035621
Directory /workspace/40.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.2812804612
Short name T132
Test name
Test status
Simulation time 336979830000 ps
CPU time 752.1 seconds
Started Aug 08 05:04:26 PM PDT 24
Finished Aug 08 05:35:46 PM PDT 24
Peak memory 160680 kb
Host smart-b0cc6a96-bdf2-45fe-b0fb-1463add9ce9a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2812804612 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.2812804612
Directory /workspace/41.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.735853177
Short name T112
Test name
Test status
Simulation time 336906150000 ps
CPU time 855.25 seconds
Started Aug 08 05:04:32 PM PDT 24
Finished Aug 08 05:39:22 PM PDT 24
Peak memory 159964 kb
Host smart-f07f22fb-f72a-412a-94ee-87d12ca9c7e5
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=735853177 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.735853177
Directory /workspace/42.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.918274411
Short name T115
Test name
Test status
Simulation time 336548350000 ps
CPU time 923.07 seconds
Started Aug 08 05:04:20 PM PDT 24
Finished Aug 08 05:42:05 PM PDT 24
Peak memory 160728 kb
Host smart-024d3bf1-aa4b-43ab-9848-22eff2836ae7
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=918274411 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.918274411
Directory /workspace/43.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.2223649515
Short name T134
Test name
Test status
Simulation time 337037610000 ps
CPU time 838.03 seconds
Started Aug 08 05:04:34 PM PDT 24
Finished Aug 08 05:38:57 PM PDT 24
Peak memory 160644 kb
Host smart-f1089cd1-491e-4df5-a14e-66c8835d43e5
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2223649515 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.2223649515
Directory /workspace/44.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.1322168458
Short name T126
Test name
Test status
Simulation time 337113410000 ps
CPU time 909.49 seconds
Started Aug 08 05:04:30 PM PDT 24
Finished Aug 08 05:41:52 PM PDT 24
Peak memory 160784 kb
Host smart-1f70d7ce-3eb5-4672-adbf-1a4dc9ba1b0b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1322168458 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.1322168458
Directory /workspace/45.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.577305951
Short name T150
Test name
Test status
Simulation time 336539330000 ps
CPU time 644.57 seconds
Started Aug 08 05:04:26 PM PDT 24
Finished Aug 08 05:31:36 PM PDT 24
Peak memory 160892 kb
Host smart-4b68f78e-7b22-4102-aa14-f2ef7219aa42
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=577305951 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.577305951
Directory /workspace/46.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.976634602
Short name T136
Test name
Test status
Simulation time 336896790000 ps
CPU time 673.66 seconds
Started Aug 08 05:04:25 PM PDT 24
Finished Aug 08 05:31:48 PM PDT 24
Peak memory 160732 kb
Host smart-30d5613f-597f-4237-91d7-fe31adb93e13
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=976634602 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.976634602
Directory /workspace/47.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.2992073847
Short name T6
Test name
Test status
Simulation time 337068230000 ps
CPU time 817.4 seconds
Started Aug 08 05:04:19 PM PDT 24
Finished Aug 08 05:38:03 PM PDT 24
Peak memory 160772 kb
Host smart-51da1b35-233a-49e4-886e-02c05e56d391
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2992073847 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.2992073847
Directory /workspace/48.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.3487874123
Short name T26
Test name
Test status
Simulation time 336892770000 ps
CPU time 853.16 seconds
Started Aug 08 05:04:29 PM PDT 24
Finished Aug 08 05:39:17 PM PDT 24
Peak memory 160740 kb
Host smart-742d2556-a916-431e-b7e6-28b786380e7a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3487874123 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.3487874123
Directory /workspace/49.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.1457616843
Short name T131
Test name
Test status
Simulation time 336666670000 ps
CPU time 823.88 seconds
Started Aug 08 05:04:33 PM PDT 24
Finished Aug 08 05:39:22 PM PDT 24
Peak memory 160672 kb
Host smart-bca60ee4-f295-4629-9fee-ca42f004b287
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1457616843 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.1457616843
Directory /workspace/5.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.497083175
Short name T121
Test name
Test status
Simulation time 336566110000 ps
CPU time 894.04 seconds
Started Aug 08 05:04:22 PM PDT 24
Finished Aug 08 05:40:46 PM PDT 24
Peak memory 160680 kb
Host smart-91998cf0-482a-473c-b56b-7348a777f99e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=497083175 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.497083175
Directory /workspace/6.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.4176747232
Short name T138
Test name
Test status
Simulation time 337019250000 ps
CPU time 818.52 seconds
Started Aug 08 05:04:21 PM PDT 24
Finished Aug 08 05:38:07 PM PDT 24
Peak memory 160740 kb
Host smart-75d56148-0a8c-41f8-a711-62074a5adab7
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4176747232 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.4176747232
Directory /workspace/7.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.3497799734
Short name T149
Test name
Test status
Simulation time 336860830000 ps
CPU time 801.18 seconds
Started Aug 08 05:04:25 PM PDT 24
Finished Aug 08 05:37:39 PM PDT 24
Peak memory 160696 kb
Host smart-fa4e96e2-34d9-4f30-a23c-4728c44f295e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3497799734 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.3497799734
Directory /workspace/8.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.1368409132
Short name T120
Test name
Test status
Simulation time 336503370000 ps
CPU time 916.46 seconds
Started Aug 08 05:04:30 PM PDT 24
Finished Aug 08 05:42:11 PM PDT 24
Peak memory 160772 kb
Host smart-7d0fb5bb-c7f0-4865-a0d5-64eaae077753
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1368409132 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.1368409132
Directory /workspace/9.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.780267353
Short name T106
Test name
Test status
Simulation time 336353950000 ps
CPU time 957.46 seconds
Started Aug 08 05:04:06 PM PDT 24
Finished Aug 08 05:43:36 PM PDT 24
Peak memory 160744 kb
Host smart-3636abb8-75db-46d7-9757-d09bf6afb9e6
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=780267353 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.780267353
Directory /workspace/0.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.3319207355
Short name T87
Test name
Test status
Simulation time 336406190000 ps
CPU time 846.05 seconds
Started Aug 08 05:04:13 PM PDT 24
Finished Aug 08 05:38:48 PM PDT 24
Peak memory 160764 kb
Host smart-077b8ad1-007c-4c83-8d17-c78aa967800e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3319207355 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.3319207355
Directory /workspace/1.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.2313810962
Short name T73
Test name
Test status
Simulation time 336978450000 ps
CPU time 908.53 seconds
Started Aug 08 05:04:23 PM PDT 24
Finished Aug 08 05:41:40 PM PDT 24
Peak memory 160712 kb
Host smart-8ca822fd-6f96-4c76-9dec-b7c49a38d616
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2313810962 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.2313810962
Directory /workspace/11.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.4059307227
Short name T71
Test name
Test status
Simulation time 336896590000 ps
CPU time 851.64 seconds
Started Aug 08 05:04:26 PM PDT 24
Finished Aug 08 05:39:36 PM PDT 24
Peak memory 160652 kb
Host smart-7682223b-06b1-4e2c-a625-65a706463cc7
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4059307227 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.4059307227
Directory /workspace/12.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.688556085
Short name T72
Test name
Test status
Simulation time 336416350000 ps
CPU time 848.54 seconds
Started Aug 08 05:04:07 PM PDT 24
Finished Aug 08 05:38:49 PM PDT 24
Peak memory 160648 kb
Host smart-6d152840-c847-4c33-aea1-0ca5100ab1c0
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=688556085 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.688556085
Directory /workspace/13.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.979284595
Short name T104
Test name
Test status
Simulation time 336954970000 ps
CPU time 791.63 seconds
Started Aug 08 05:04:13 PM PDT 24
Finished Aug 08 05:36:04 PM PDT 24
Peak memory 160788 kb
Host smart-beccda60-3e2e-47e2-a59f-1dbb5830f4c5
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=979284595 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.979284595
Directory /workspace/14.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.3263653570
Short name T92
Test name
Test status
Simulation time 336997190000 ps
CPU time 867.05 seconds
Started Aug 08 05:04:14 PM PDT 24
Finished Aug 08 05:39:37 PM PDT 24
Peak memory 160696 kb
Host smart-b0784c28-954c-4e97-8406-103ef829be1f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3263653570 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.3263653570
Directory /workspace/15.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.968537118
Short name T100
Test name
Test status
Simulation time 336542190000 ps
CPU time 756.77 seconds
Started Aug 08 05:04:08 PM PDT 24
Finished Aug 08 05:35:02 PM PDT 24
Peak memory 160688 kb
Host smart-d7b91a82-50b5-4381-ab5a-6150aee3fab4
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=968537118 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.968537118
Directory /workspace/16.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.4082155018
Short name T84
Test name
Test status
Simulation time 336376610000 ps
CPU time 831.29 seconds
Started Aug 08 05:04:20 PM PDT 24
Finished Aug 08 05:38:45 PM PDT 24
Peak memory 160776 kb
Host smart-b878e8a5-e3d0-42a3-90c3-59b464498a8e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4082155018 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.4082155018
Directory /workspace/17.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.1177446246
Short name T89
Test name
Test status
Simulation time 336727310000 ps
CPU time 827.38 seconds
Started Aug 08 05:04:15 PM PDT 24
Finished Aug 08 05:38:29 PM PDT 24
Peak memory 160824 kb
Host smart-e4311e1c-b58f-4737-bd30-fd0f5afcfafe
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1177446246 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.1177446246
Directory /workspace/18.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.1431610724
Short name T91
Test name
Test status
Simulation time 336971630000 ps
CPU time 842.91 seconds
Started Aug 08 05:04:17 PM PDT 24
Finished Aug 08 05:38:53 PM PDT 24
Peak memory 160772 kb
Host smart-668f3475-85a3-440a-adbb-22ba2f2f765f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1431610724 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.1431610724
Directory /workspace/19.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.882007353
Short name T78
Test name
Test status
Simulation time 336436290000 ps
CPU time 932.07 seconds
Started Aug 08 05:04:22 PM PDT 24
Finished Aug 08 05:43:07 PM PDT 24
Peak memory 160740 kb
Host smart-88093bfc-b0fd-4da3-bcfd-875ac6854589
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=882007353 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.882007353
Directory /workspace/2.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.2867929679
Short name T83
Test name
Test status
Simulation time 336862010000 ps
CPU time 785.32 seconds
Started Aug 08 05:04:09 PM PDT 24
Finished Aug 08 05:35:46 PM PDT 24
Peak memory 160720 kb
Host smart-480a65ae-3e8b-4386-99f5-b96688a49502
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2867929679 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.2867929679
Directory /workspace/20.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.2437238447
Short name T98
Test name
Test status
Simulation time 336681390000 ps
CPU time 802.34 seconds
Started Aug 08 05:04:23 PM PDT 24
Finished Aug 08 05:37:18 PM PDT 24
Peak memory 160772 kb
Host smart-bc303f8f-0780-4d4b-8399-a2b8a36ddd24
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2437238447 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.2437238447
Directory /workspace/21.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.1897520866
Short name T86
Test name
Test status
Simulation time 336807310000 ps
CPU time 860.22 seconds
Started Aug 08 05:04:10 PM PDT 24
Finished Aug 08 05:40:01 PM PDT 24
Peak memory 160648 kb
Host smart-8cf5a3c0-cd35-49ca-85e6-22063c102f1e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1897520866 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.1897520866
Directory /workspace/22.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.3595850969
Short name T18
Test name
Test status
Simulation time 336597090000 ps
CPU time 834.42 seconds
Started Aug 08 05:04:15 PM PDT 24
Finished Aug 08 05:39:19 PM PDT 24
Peak memory 160684 kb
Host smart-b5ada9dc-cee7-44df-b56f-53b0aeae0f07
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3595850969 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.3595850969
Directory /workspace/23.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.1061397223
Short name T23
Test name
Test status
Simulation time 336361330000 ps
CPU time 731.99 seconds
Started Aug 08 05:04:14 PM PDT 24
Finished Aug 08 05:34:22 PM PDT 24
Peak memory 160700 kb
Host smart-1a54ac34-a9b6-4d41-89c1-7dca0b4f58d4
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1061397223 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.1061397223
Directory /workspace/24.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.2105173952
Short name T82
Test name
Test status
Simulation time 336565890000 ps
CPU time 830.29 seconds
Started Aug 08 05:04:11 PM PDT 24
Finished Aug 08 05:39:13 PM PDT 24
Peak memory 160684 kb
Host smart-2832a0d3-2655-41f7-ac29-dd3e03989914
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2105173952 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.2105173952
Directory /workspace/25.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.4018268791
Short name T102
Test name
Test status
Simulation time 336445270000 ps
CPU time 715.06 seconds
Started Aug 08 05:04:24 PM PDT 24
Finished Aug 08 05:34:00 PM PDT 24
Peak memory 160700 kb
Host smart-8acb86a8-700c-411f-8b81-07820f05f98f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4018268791 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.4018268791
Directory /workspace/26.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.126633784
Short name T16
Test name
Test status
Simulation time 336449550000 ps
CPU time 887.25 seconds
Started Aug 08 05:04:20 PM PDT 24
Finished Aug 08 05:40:45 PM PDT 24
Peak memory 160776 kb
Host smart-443367a5-d5ab-428f-ba55-7513cba6a821
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=126633784 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.126633784
Directory /workspace/27.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.1377255906
Short name T80
Test name
Test status
Simulation time 336436650000 ps
CPU time 802.42 seconds
Started Aug 08 05:04:17 PM PDT 24
Finished Aug 08 05:37:44 PM PDT 24
Peak memory 160708 kb
Host smart-e519ee8c-3e3d-42a9-b459-f7c0a3b40c8e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1377255906 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.1377255906
Directory /workspace/28.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.3645142361
Short name T20
Test name
Test status
Simulation time 336630330000 ps
CPU time 788.09 seconds
Started Aug 08 05:04:10 PM PDT 24
Finished Aug 08 05:36:19 PM PDT 24
Peak memory 160788 kb
Host smart-f028dfe0-a33b-479a-a039-92699ed8d724
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3645142361 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.3645142361
Directory /workspace/29.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.3323856371
Short name T94
Test name
Test status
Simulation time 336918210000 ps
CPU time 923.88 seconds
Started Aug 08 05:04:18 PM PDT 24
Finished Aug 08 05:41:59 PM PDT 24
Peak memory 160752 kb
Host smart-a290c5b4-290b-4c22-87d4-767c5c67860b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3323856371 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.3323856371
Directory /workspace/3.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.3589063221
Short name T109
Test name
Test status
Simulation time 336729130000 ps
CPU time 767.14 seconds
Started Aug 08 05:04:14 PM PDT 24
Finished Aug 08 05:35:58 PM PDT 24
Peak memory 160684 kb
Host smart-7f42e606-d926-42f6-84df-8545811f2a29
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3589063221 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.3589063221
Directory /workspace/30.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.2825644167
Short name T14
Test name
Test status
Simulation time 336533150000 ps
CPU time 846.04 seconds
Started Aug 08 05:04:29 PM PDT 24
Finished Aug 08 05:39:10 PM PDT 24
Peak memory 160744 kb
Host smart-b7e0e99d-d9e9-49ad-baf2-3b3cb7bd40c0
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2825644167 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.2825644167
Directory /workspace/31.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.2369064454
Short name T85
Test name
Test status
Simulation time 336481830000 ps
CPU time 876.74 seconds
Started Aug 08 05:04:14 PM PDT 24
Finished Aug 08 05:40:41 PM PDT 24
Peak memory 160656 kb
Host smart-c0d21bbf-6242-4144-9624-6c5eabe7227a
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2369064454 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.2369064454
Directory /workspace/32.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.3114702210
Short name T19
Test name
Test status
Simulation time 336918610000 ps
CPU time 823.94 seconds
Started Aug 08 05:04:22 PM PDT 24
Finished Aug 08 05:38:11 PM PDT 24
Peak memory 160724 kb
Host smart-21b81643-9e56-44ba-9f03-659a79b79e37
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3114702210 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.3114702210
Directory /workspace/33.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.1755545004
Short name T96
Test name
Test status
Simulation time 337046250000 ps
CPU time 820.72 seconds
Started Aug 08 05:04:15 PM PDT 24
Finished Aug 08 05:37:53 PM PDT 24
Peak memory 160724 kb
Host smart-c429c694-6943-46b8-b44d-8bc599313ab6
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1755545004 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.1755545004
Directory /workspace/34.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.1879850301
Short name T105
Test name
Test status
Simulation time 336751950000 ps
CPU time 880.16 seconds
Started Aug 08 05:04:20 PM PDT 24
Finished Aug 08 05:40:25 PM PDT 24
Peak memory 160708 kb
Host smart-0876dcfb-f5c1-41e0-a372-dc74274c7ba5
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1879850301 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.1879850301
Directory /workspace/35.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.3218587502
Short name T101
Test name
Test status
Simulation time 336472410000 ps
CPU time 929.76 seconds
Started Aug 08 05:04:16 PM PDT 24
Finished Aug 08 05:42:14 PM PDT 24
Peak memory 160712 kb
Host smart-5376464d-430e-48a3-a5cb-52233ed3814f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3218587502 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.3218587502
Directory /workspace/36.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.2535644497
Short name T110
Test name
Test status
Simulation time 336460630000 ps
CPU time 807.74 seconds
Started Aug 08 05:04:22 PM PDT 24
Finished Aug 08 05:37:30 PM PDT 24
Peak memory 160716 kb
Host smart-86e3c78b-e170-4984-8b88-d059256b60d1
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2535644497 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.2535644497
Directory /workspace/37.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.94930498
Short name T76
Test name
Test status
Simulation time 336687630000 ps
CPU time 832.36 seconds
Started Aug 08 05:04:14 PM PDT 24
Finished Aug 08 05:38:14 PM PDT 24
Peak memory 160708 kb
Host smart-e525f009-9a16-4c01-94c7-575a9bc518da
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=94930498 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.94930498
Directory /workspace/38.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.2824875368
Short name T97
Test name
Test status
Simulation time 336694670000 ps
CPU time 879.4 seconds
Started Aug 08 05:04:20 PM PDT 24
Finished Aug 08 05:40:17 PM PDT 24
Peak memory 160708 kb
Host smart-e6806c9e-5973-4586-926a-c4dfb30e044b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2824875368 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.2824875368
Directory /workspace/39.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.342586453
Short name T90
Test name
Test status
Simulation time 337013970000 ps
CPU time 864.09 seconds
Started Aug 08 05:04:22 PM PDT 24
Finished Aug 08 05:39:46 PM PDT 24
Peak memory 160704 kb
Host smart-ff359e4f-3f8f-4447-9570-4bbee8fd7a4b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=342586453 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.342586453
Directory /workspace/4.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.3746544222
Short name T79
Test name
Test status
Simulation time 336623690000 ps
CPU time 832.68 seconds
Started Aug 08 05:04:30 PM PDT 24
Finished Aug 08 05:38:39 PM PDT 24
Peak memory 160764 kb
Host smart-71b25f8c-8737-4001-aa8a-b7bb57a6bc20
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3746544222 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.3746544222
Directory /workspace/40.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.3730785422
Short name T17
Test name
Test status
Simulation time 336334050000 ps
CPU time 770.36 seconds
Started Aug 08 05:04:30 PM PDT 24
Finished Aug 08 05:35:55 PM PDT 24
Peak memory 160728 kb
Host smart-e5ba5314-f88b-44cd-b680-7047be6581b9
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3730785422 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.3730785422
Directory /workspace/41.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.3675123200
Short name T81
Test name
Test status
Simulation time 336919070000 ps
CPU time 696.2 seconds
Started Aug 08 05:04:25 PM PDT 24
Finished Aug 08 05:32:53 PM PDT 24
Peak memory 160700 kb
Host smart-829d1cb7-e757-4770-aad5-e99ed0f481be
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3675123200 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.3675123200
Directory /workspace/42.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.2786810867
Short name T74
Test name
Test status
Simulation time 337105330000 ps
CPU time 801.76 seconds
Started Aug 08 05:04:24 PM PDT 24
Finished Aug 08 05:36:56 PM PDT 24
Peak memory 160720 kb
Host smart-8a298054-ce40-45db-940d-755c67f42c0f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2786810867 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.2786810867
Directory /workspace/43.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.1830642636
Short name T21
Test name
Test status
Simulation time 336992550000 ps
CPU time 943.49 seconds
Started Aug 08 05:04:22 PM PDT 24
Finished Aug 08 05:43:04 PM PDT 24
Peak memory 160744 kb
Host smart-e10a5d2e-31f0-49cd-80a2-ab92c41912c3
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1830642636 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.1830642636
Directory /workspace/44.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.2728246490
Short name T22
Test name
Test status
Simulation time 336665270000 ps
CPU time 803.9 seconds
Started Aug 08 05:04:20 PM PDT 24
Finished Aug 08 05:36:46 PM PDT 24
Peak memory 160732 kb
Host smart-661ea63a-7969-4e08-a405-61f658e76669
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2728246490 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.2728246490
Directory /workspace/45.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.3599608335
Short name T103
Test name
Test status
Simulation time 336981570000 ps
CPU time 803.67 seconds
Started Aug 08 05:04:24 PM PDT 24
Finished Aug 08 05:37:31 PM PDT 24
Peak memory 160752 kb
Host smart-0aea9d94-1f22-4364-9931-be032a7322dd
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3599608335 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.3599608335
Directory /workspace/46.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.746277666
Short name T93
Test name
Test status
Simulation time 336773370000 ps
CPU time 824.05 seconds
Started Aug 08 05:04:21 PM PDT 24
Finished Aug 08 05:37:38 PM PDT 24
Peak memory 160788 kb
Host smart-57db603e-6206-4fbb-9066-00fa5d024f46
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=746277666 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.746277666
Directory /workspace/47.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1570185093
Short name T99
Test name
Test status
Simulation time 336413790000 ps
CPU time 847.07 seconds
Started Aug 08 05:04:25 PM PDT 24
Finished Aug 08 05:39:26 PM PDT 24
Peak memory 160664 kb
Host smart-2437460a-4b8c-4315-b87a-df0d4979e134
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1570185093 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.1570185093
Directory /workspace/48.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.2987497183
Short name T88
Test name
Test status
Simulation time 336867890000 ps
CPU time 721.97 seconds
Started Aug 08 05:04:20 PM PDT 24
Finished Aug 08 05:33:47 PM PDT 24
Peak memory 160800 kb
Host smart-b0358a08-ea94-45d5-8808-30a564e7d0e5
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2987497183 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.2987497183
Directory /workspace/49.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.73592732
Short name T75
Test name
Test status
Simulation time 336769990000 ps
CPU time 759.23 seconds
Started Aug 08 05:04:24 PM PDT 24
Finished Aug 08 05:36:08 PM PDT 24
Peak memory 160680 kb
Host smart-7e84ba2f-7d64-4c5f-b6a3-5085eb408597
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=73592732 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.73592732
Directory /workspace/5.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.2616906978
Short name T95
Test name
Test status
Simulation time 336636290000 ps
CPU time 811.41 seconds
Started Aug 08 05:04:12 PM PDT 24
Finished Aug 08 05:37:29 PM PDT 24
Peak memory 160744 kb
Host smart-3bb3a564-9c64-45f9-9b10-6628f8dfbd21
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2616906978 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.2616906978
Directory /workspace/6.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.333227948
Short name T108
Test name
Test status
Simulation time 336864150000 ps
CPU time 803.21 seconds
Started Aug 08 05:04:24 PM PDT 24
Finished Aug 08 05:37:36 PM PDT 24
Peak memory 160704 kb
Host smart-7c22417d-33f6-4b63-897b-0201ccc16c9d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=333227948 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.333227948
Directory /workspace/7.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.1262528018
Short name T77
Test name
Test status
Simulation time 336995610000 ps
CPU time 734.67 seconds
Started Aug 08 05:04:21 PM PDT 24
Finished Aug 08 05:34:29 PM PDT 24
Peak memory 160720 kb
Host smart-2c84cabf-f87c-45d5-bae1-75a68b612724
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1262528018 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.1262528018
Directory /workspace/8.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.392028177
Short name T107
Test name
Test status
Simulation time 336654150000 ps
CPU time 757.94 seconds
Started Aug 08 05:04:06 PM PDT 24
Finished Aug 08 05:34:57 PM PDT 24
Peak memory 160708 kb
Host smart-97b65534-3520-48f6-861e-04da80af1d33
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=392028177 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.392028177
Directory /workspace/9.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.3047335247
Short name T184
Test name
Test status
Simulation time 1409590000 ps
CPU time 4.26 seconds
Started Aug 08 05:04:36 PM PDT 24
Finished Aug 08 05:04:46 PM PDT 24
Peak memory 164856 kb
Host smart-24d476ac-304b-4da6-baee-6ac6841b4cdc
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3047335247 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.3047335247
Directory /workspace/0.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.703057848
Short name T198
Test name
Test status
Simulation time 1347790000 ps
CPU time 4.1 seconds
Started Aug 08 05:04:38 PM PDT 24
Finished Aug 08 05:04:47 PM PDT 24
Peak memory 164808 kb
Host smart-125080af-6b31-454a-949c-81bd99a210a8
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=703057848 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.703057848
Directory /workspace/1.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.79269198
Short name T155
Test name
Test status
Simulation time 1302350000 ps
CPU time 3.23 seconds
Started Aug 08 05:04:35 PM PDT 24
Finished Aug 08 05:04:42 PM PDT 24
Peak memory 164816 kb
Host smart-11b142d1-1853-4f0d-bb03-f51cea5b2f80
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=79269198 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.79269198
Directory /workspace/10.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.3093129768
Short name T161
Test name
Test status
Simulation time 1505410000 ps
CPU time 4.88 seconds
Started Aug 08 05:04:30 PM PDT 24
Finished Aug 08 05:04:41 PM PDT 24
Peak memory 164864 kb
Host smart-37127a92-c3c7-46ad-9b64-8d40279ce5df
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3093129768 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.3093129768
Directory /workspace/11.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.3395636583
Short name T193
Test name
Test status
Simulation time 1567690000 ps
CPU time 6.2 seconds
Started Aug 08 05:04:34 PM PDT 24
Finished Aug 08 05:04:48 PM PDT 24
Peak memory 164892 kb
Host smart-f83c7e85-be09-4b22-beda-f2274c766252
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3395636583 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.3395636583
Directory /workspace/12.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.2074583681
Short name T195
Test name
Test status
Simulation time 1156690000 ps
CPU time 3.38 seconds
Started Aug 08 05:04:39 PM PDT 24
Finished Aug 08 05:04:46 PM PDT 24
Peak memory 164864 kb
Host smart-9cc5b55a-d883-4083-aedf-fdadfd81ac08
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2074583681 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.2074583681
Directory /workspace/13.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.3950838781
Short name T153
Test name
Test status
Simulation time 1538650000 ps
CPU time 5.89 seconds
Started Aug 08 05:04:45 PM PDT 24
Finished Aug 08 05:04:58 PM PDT 24
Peak memory 164900 kb
Host smart-52eb78bc-5d21-4e7e-9b55-c717481ecfe9
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3950838781 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.3950838781
Directory /workspace/14.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.2252171005
Short name T181
Test name
Test status
Simulation time 1599170000 ps
CPU time 4.95 seconds
Started Aug 08 05:04:40 PM PDT 24
Finished Aug 08 05:04:51 PM PDT 24
Peak memory 165036 kb
Host smart-b3830b2f-59f9-4ebc-9a14-56fdffb8a50f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2252171005 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.2252171005
Directory /workspace/15.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.98163345
Short name T157
Test name
Test status
Simulation time 1525670000 ps
CPU time 5.76 seconds
Started Aug 08 05:04:41 PM PDT 24
Finished Aug 08 05:04:54 PM PDT 24
Peak memory 164900 kb
Host smart-5030a14d-561d-4ded-93be-56d4c8288b61
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=98163345 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.98163345
Directory /workspace/16.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.1315176795
Short name T185
Test name
Test status
Simulation time 1297210000 ps
CPU time 4.33 seconds
Started Aug 08 05:04:38 PM PDT 24
Finished Aug 08 05:04:48 PM PDT 24
Peak memory 164764 kb
Host smart-3d556410-65ab-4bba-887d-2540fb541499
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1315176795 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.1315176795
Directory /workspace/17.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.98684850
Short name T199
Test name
Test status
Simulation time 1415170000 ps
CPU time 4.56 seconds
Started Aug 08 05:04:38 PM PDT 24
Finished Aug 08 05:04:48 PM PDT 24
Peak memory 164772 kb
Host smart-5f91e85b-6919-4fe9-96bb-bfc553877831
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=98684850 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.98684850
Directory /workspace/18.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.547449937
Short name T172
Test name
Test status
Simulation time 1379790000 ps
CPU time 3.35 seconds
Started Aug 08 05:04:37 PM PDT 24
Finished Aug 08 05:04:45 PM PDT 24
Peak memory 164760 kb
Host smart-316f5f70-6303-4df2-8f1c-4cfb5303aeaa
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=547449937 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.547449937
Directory /workspace/19.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.2841753740
Short name T179
Test name
Test status
Simulation time 1504450000 ps
CPU time 3.74 seconds
Started Aug 08 05:04:46 PM PDT 24
Finished Aug 08 05:04:54 PM PDT 24
Peak memory 164848 kb
Host smart-61ab4166-50ec-4eff-a9aa-4f5cc146e878
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2841753740 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.2841753740
Directory /workspace/2.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.1962007244
Short name T170
Test name
Test status
Simulation time 1439230000 ps
CPU time 4.78 seconds
Started Aug 08 05:04:34 PM PDT 24
Finished Aug 08 05:04:45 PM PDT 24
Peak memory 164824 kb
Host smart-f0f19083-f9f3-4b67-9d5d-437c80e9630e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1962007244 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.1962007244
Directory /workspace/20.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.76045662
Short name T156
Test name
Test status
Simulation time 1250650000 ps
CPU time 3.49 seconds
Started Aug 08 05:04:31 PM PDT 24
Finished Aug 08 05:04:39 PM PDT 24
Peak memory 164816 kb
Host smart-5f5e7100-548d-4867-a6df-297a2be92e38
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=76045662 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.76045662
Directory /workspace/21.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.4278863723
Short name T162
Test name
Test status
Simulation time 1466510000 ps
CPU time 4.29 seconds
Started Aug 08 05:04:34 PM PDT 24
Finished Aug 08 05:04:44 PM PDT 24
Peak memory 164824 kb
Host smart-c40dfce3-1cfb-4d2e-a357-a7b80ed29a21
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4278863723 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.4278863723
Directory /workspace/22.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.1266367457
Short name T183
Test name
Test status
Simulation time 1314030000 ps
CPU time 3.88 seconds
Started Aug 08 05:04:35 PM PDT 24
Finished Aug 08 05:04:43 PM PDT 24
Peak memory 164888 kb
Host smart-dd1a2c30-689b-4918-887d-a9e3117b3fd6
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1266367457 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.1266367457
Directory /workspace/23.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.3967997880
Short name T187
Test name
Test status
Simulation time 1538770000 ps
CPU time 4.77 seconds
Started Aug 08 05:04:34 PM PDT 24
Finished Aug 08 05:04:45 PM PDT 24
Peak memory 164892 kb
Host smart-fcad5bfa-7697-4c8e-a260-ab9e570c8829
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3967997880 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.3967997880
Directory /workspace/24.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.3885547871
Short name T154
Test name
Test status
Simulation time 1477150000 ps
CPU time 4.71 seconds
Started Aug 08 05:04:33 PM PDT 24
Finished Aug 08 05:04:44 PM PDT 24
Peak memory 164896 kb
Host smart-3f6f4b59-02b5-4bd2-ae8d-ba99c514cbb8
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3885547871 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.3885547871
Directory /workspace/25.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2868945716
Short name T151
Test name
Test status
Simulation time 1275070000 ps
CPU time 3.88 seconds
Started Aug 08 05:04:35 PM PDT 24
Finished Aug 08 05:04:44 PM PDT 24
Peak memory 164864 kb
Host smart-c0d9bee8-dbf3-444f-8b5a-4181646221bf
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2868945716 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.2868945716
Directory /workspace/26.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.118629717
Short name T178
Test name
Test status
Simulation time 1501730000 ps
CPU time 4.37 seconds
Started Aug 08 05:04:33 PM PDT 24
Finished Aug 08 05:04:43 PM PDT 24
Peak memory 164788 kb
Host smart-556f40c8-9b78-4d06-a19d-39926803ffaa
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=118629717 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.118629717
Directory /workspace/27.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.2841906171
Short name T174
Test name
Test status
Simulation time 1446990000 ps
CPU time 4.14 seconds
Started Aug 08 05:04:36 PM PDT 24
Finished Aug 08 05:04:45 PM PDT 24
Peak memory 164820 kb
Host smart-b41e84d8-fcac-474d-a63a-aa80db8f3f06
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2841906171 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.2841906171
Directory /workspace/28.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.2368954666
Short name T200
Test name
Test status
Simulation time 1459150000 ps
CPU time 4.27 seconds
Started Aug 08 05:04:34 PM PDT 24
Finished Aug 08 05:04:44 PM PDT 24
Peak memory 164820 kb
Host smart-568f6df9-7709-40e1-abd9-613460622674
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2368954666 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.2368954666
Directory /workspace/29.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.3531143380
Short name T167
Test name
Test status
Simulation time 1586250000 ps
CPU time 6.13 seconds
Started Aug 08 05:04:33 PM PDT 24
Finished Aug 08 05:04:47 PM PDT 24
Peak memory 164820 kb
Host smart-a4e98c68-a906-4de6-bbd3-f2d97ab60654
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3531143380 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.3531143380
Directory /workspace/3.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.703927770
Short name T160
Test name
Test status
Simulation time 1325170000 ps
CPU time 3.92 seconds
Started Aug 08 05:04:32 PM PDT 24
Finished Aug 08 05:04:41 PM PDT 24
Peak memory 164880 kb
Host smart-6a7301ba-9a8f-4760-a423-3ac76eb2bbf7
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=703927770 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.703927770
Directory /workspace/30.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.450943834
Short name T194
Test name
Test status
Simulation time 1507790000 ps
CPU time 5.27 seconds
Started Aug 08 05:04:33 PM PDT 24
Finished Aug 08 05:04:45 PM PDT 24
Peak memory 164812 kb
Host smart-adb4b9fe-9e1e-4bcd-a436-9f9695272f1d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=450943834 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.450943834
Directory /workspace/31.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.3992290068
Short name T164
Test name
Test status
Simulation time 1467130000 ps
CPU time 5.64 seconds
Started Aug 08 05:04:36 PM PDT 24
Finished Aug 08 05:04:48 PM PDT 24
Peak memory 164816 kb
Host smart-f0b80944-007c-49fe-b45f-8d895b3f0ff5
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3992290068 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.3992290068
Directory /workspace/32.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.1951723523
Short name T158
Test name
Test status
Simulation time 1524910000 ps
CPU time 4.33 seconds
Started Aug 08 05:04:37 PM PDT 24
Finished Aug 08 05:04:47 PM PDT 24
Peak memory 164800 kb
Host smart-6f7b5436-6074-4f87-aea7-273fa5440404
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1951723523 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.1951723523
Directory /workspace/33.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.3541721712
Short name T152
Test name
Test status
Simulation time 1477450000 ps
CPU time 4.87 seconds
Started Aug 08 05:04:35 PM PDT 24
Finished Aug 08 05:04:47 PM PDT 24
Peak memory 164672 kb
Host smart-4cba5377-cae9-4e9c-a4a5-7f6ecf05bc02
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3541721712 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.3541721712
Directory /workspace/34.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.1608754291
Short name T188
Test name
Test status
Simulation time 1486210000 ps
CPU time 3.88 seconds
Started Aug 08 05:04:33 PM PDT 24
Finished Aug 08 05:04:42 PM PDT 24
Peak memory 164868 kb
Host smart-d63a7789-76f3-4647-a47d-4704fd1553f4
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1608754291 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.1608754291
Directory /workspace/35.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.1432496405
Short name T166
Test name
Test status
Simulation time 1393730000 ps
CPU time 3.89 seconds
Started Aug 08 05:04:47 PM PDT 24
Finished Aug 08 05:04:55 PM PDT 24
Peak memory 164880 kb
Host smart-62978e7d-9ecf-4141-864f-e76664df7812
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1432496405 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.1432496405
Directory /workspace/36.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1129723782
Short name T159
Test name
Test status
Simulation time 1532370000 ps
CPU time 4.53 seconds
Started Aug 08 05:04:33 PM PDT 24
Finished Aug 08 05:04:44 PM PDT 24
Peak memory 164732 kb
Host smart-be4a8e4f-75fd-4b4f-bc53-a8b8dbd6cc18
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1129723782 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.1129723782
Directory /workspace/37.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.3049116642
Short name T182
Test name
Test status
Simulation time 1440250000 ps
CPU time 5.52 seconds
Started Aug 08 05:04:45 PM PDT 24
Finished Aug 08 05:04:57 PM PDT 24
Peak memory 164900 kb
Host smart-c16ffbcc-0816-4749-98d2-187b28583114
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3049116642 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.3049116642
Directory /workspace/38.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.1871043287
Short name T191
Test name
Test status
Simulation time 1545470000 ps
CPU time 4.96 seconds
Started Aug 08 05:04:40 PM PDT 24
Finished Aug 08 05:04:51 PM PDT 24
Peak memory 165036 kb
Host smart-a623364b-7222-4f26-b306-5c900113659f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1871043287 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.1871043287
Directory /workspace/39.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3856943708
Short name T189
Test name
Test status
Simulation time 1558010000 ps
CPU time 4.71 seconds
Started Aug 08 05:04:36 PM PDT 24
Finished Aug 08 05:04:46 PM PDT 24
Peak memory 164760 kb
Host smart-a7b56507-8bf7-48ec-b0c6-a6577f2dbd86
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3856943708 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.3856943708
Directory /workspace/4.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.1237177231
Short name T171
Test name
Test status
Simulation time 1583310000 ps
CPU time 4.05 seconds
Started Aug 08 05:04:37 PM PDT 24
Finished Aug 08 05:04:47 PM PDT 24
Peak memory 164852 kb
Host smart-5e16c132-3cea-408a-9191-d47341685805
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1237177231 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.1237177231
Directory /workspace/40.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.3320760627
Short name T173
Test name
Test status
Simulation time 1439630000 ps
CPU time 4.78 seconds
Started Aug 08 05:04:35 PM PDT 24
Finished Aug 08 05:04:46 PM PDT 24
Peak memory 164824 kb
Host smart-49345356-b6c9-41e3-af1d-da7d1aef792c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3320760627 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.3320760627
Directory /workspace/41.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.3933713471
Short name T169
Test name
Test status
Simulation time 1509590000 ps
CPU time 4.97 seconds
Started Aug 08 05:04:35 PM PDT 24
Finished Aug 08 05:04:47 PM PDT 24
Peak memory 164640 kb
Host smart-610a0c4e-7e0b-400e-bdf5-224abbb3c564
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3933713471 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.3933713471
Directory /workspace/42.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.779722460
Short name T197
Test name
Test status
Simulation time 1488850000 ps
CPU time 5.38 seconds
Started Aug 08 05:04:32 PM PDT 24
Finished Aug 08 05:04:44 PM PDT 24
Peak memory 164768 kb
Host smart-763f60b3-c29e-4f79-aa3f-f8397c8e3bf4
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=779722460 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.779722460
Directory /workspace/43.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.3752175221
Short name T165
Test name
Test status
Simulation time 1529590000 ps
CPU time 4.72 seconds
Started Aug 08 05:04:38 PM PDT 24
Finished Aug 08 05:04:49 PM PDT 24
Peak memory 164764 kb
Host smart-10238d94-67ae-4ef3-8121-a2a8ef0afcf5
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3752175221 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.3752175221
Directory /workspace/44.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.1621345930
Short name T168
Test name
Test status
Simulation time 1312690000 ps
CPU time 5.11 seconds
Started Aug 08 05:04:39 PM PDT 24
Finished Aug 08 05:04:51 PM PDT 24
Peak memory 164892 kb
Host smart-d18f1f1e-788d-41c6-a3ac-1f82860aecb8
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1621345930 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.1621345930
Directory /workspace/45.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.1330421732
Short name T190
Test name
Test status
Simulation time 1341230000 ps
CPU time 5.32 seconds
Started Aug 08 05:04:34 PM PDT 24
Finished Aug 08 05:04:46 PM PDT 24
Peak memory 164816 kb
Host smart-7752500d-5d88-47d6-a9b3-721dd7cc77aa
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1330421732 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.1330421732
Directory /workspace/46.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.2337828633
Short name T192
Test name
Test status
Simulation time 1274110000 ps
CPU time 4.29 seconds
Started Aug 08 05:04:36 PM PDT 24
Finished Aug 08 05:04:46 PM PDT 24
Peak memory 164780 kb
Host smart-fef27247-e464-43a0-85c2-ade87e8cf48b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2337828633 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.2337828633
Directory /workspace/47.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.347345501
Short name T163
Test name
Test status
Simulation time 1549670000 ps
CPU time 4.35 seconds
Started Aug 08 05:04:38 PM PDT 24
Finished Aug 08 05:04:48 PM PDT 24
Peak memory 164756 kb
Host smart-6a21a91a-9789-4018-bf9c-cf661b7e49af
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=347345501 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.347345501
Directory /workspace/48.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.3925154970
Short name T175
Test name
Test status
Simulation time 1514270000 ps
CPU time 5.93 seconds
Started Aug 08 05:04:37 PM PDT 24
Finished Aug 08 05:04:51 PM PDT 24
Peak memory 164892 kb
Host smart-a781936b-6cc4-495f-8c9d-4e100a4a018e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3925154970 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.3925154970
Directory /workspace/49.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.3573509542
Short name T196
Test name
Test status
Simulation time 1506350000 ps
CPU time 4.04 seconds
Started Aug 08 05:04:36 PM PDT 24
Finished Aug 08 05:04:45 PM PDT 24
Peak memory 164868 kb
Host smart-eb6c2b26-5255-4d68-b1dc-e0cfc9aca263
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3573509542 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.3573509542
Directory /workspace/5.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.3902072310
Short name T186
Test name
Test status
Simulation time 1526490000 ps
CPU time 4.89 seconds
Started Aug 08 05:04:35 PM PDT 24
Finished Aug 08 05:04:46 PM PDT 24
Peak memory 164840 kb
Host smart-e35d6825-b1f2-47a2-a544-b3e70b91f07b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3902072310 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.3902072310
Directory /workspace/6.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.3668322979
Short name T176
Test name
Test status
Simulation time 1527630000 ps
CPU time 4.91 seconds
Started Aug 08 05:04:35 PM PDT 24
Finished Aug 08 05:04:46 PM PDT 24
Peak memory 164860 kb
Host smart-78aa386c-45a4-4d9a-9aec-a991a36e3796
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3668322979 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.3668322979
Directory /workspace/7.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1603006454
Short name T177
Test name
Test status
Simulation time 1424490000 ps
CPU time 4.84 seconds
Started Aug 08 05:04:31 PM PDT 24
Finished Aug 08 05:04:42 PM PDT 24
Peak memory 164760 kb
Host smart-c1d4af9e-7598-4142-ad4f-85b4b174cab4
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1603006454 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.1603006454
Directory /workspace/8.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.3543866264
Short name T180
Test name
Test status
Simulation time 1506410000 ps
CPU time 5.24 seconds
Started Aug 08 05:04:38 PM PDT 24
Finished Aug 08 05:04:49 PM PDT 24
Peak memory 164904 kb
Host smart-724263df-a128-4f4f-8716-6e9acce746e7
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3543866264 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.3543866264
Directory /workspace/9.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.3313222936
Short name T50
Test name
Test status
Simulation time 1563490000 ps
CPU time 5.47 seconds
Started Aug 08 05:04:26 PM PDT 24
Finished Aug 08 05:04:38 PM PDT 24
Peak memory 164796 kb
Host smart-38df2ce2-4e07-4c8b-a25d-c24162066c27
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3313222936 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.3313222936
Directory /workspace/0.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.2078656028
Short name T48
Test name
Test status
Simulation time 1461030000 ps
CPU time 4.66 seconds
Started Aug 08 05:04:23 PM PDT 24
Finished Aug 08 05:04:33 PM PDT 24
Peak memory 164920 kb
Host smart-964c2c60-73cc-496d-a37a-3edd24f3435f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2078656028 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.2078656028
Directory /workspace/1.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.3308015113
Short name T54
Test name
Test status
Simulation time 1494270000 ps
CPU time 4.09 seconds
Started Aug 08 05:04:23 PM PDT 24
Finished Aug 08 05:04:32 PM PDT 24
Peak memory 164892 kb
Host smart-a17a4054-4da3-4124-9351-c22bac88109d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3308015113 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.3308015113
Directory /workspace/10.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.256053012
Short name T36
Test name
Test status
Simulation time 1519290000 ps
CPU time 3.93 seconds
Started Aug 08 05:04:22 PM PDT 24
Finished Aug 08 05:04:30 PM PDT 24
Peak memory 164760 kb
Host smart-a64d09c0-a0bb-421d-8583-b679daf26102
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=256053012 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.256053012
Directory /workspace/11.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.3054318421
Short name T57
Test name
Test status
Simulation time 1489010000 ps
CPU time 4.3 seconds
Started Aug 08 05:04:23 PM PDT 24
Finished Aug 08 05:04:32 PM PDT 24
Peak memory 164760 kb
Host smart-a8a6482d-6309-4070-9a5e-993eeacc71ac
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3054318421 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.3054318421
Directory /workspace/12.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.3001175652
Short name T53
Test name
Test status
Simulation time 1570390000 ps
CPU time 4.95 seconds
Started Aug 08 05:04:33 PM PDT 24
Finished Aug 08 05:04:44 PM PDT 24
Peak memory 164804 kb
Host smart-af5fdb56-947e-4828-9b8a-fb7153d80ecf
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3001175652 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.3001175652
Directory /workspace/13.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.2829671568
Short name T68
Test name
Test status
Simulation time 1338530000 ps
CPU time 3.91 seconds
Started Aug 08 05:04:25 PM PDT 24
Finished Aug 08 05:04:34 PM PDT 24
Peak memory 164832 kb
Host smart-0c79ac8e-c1ed-4f73-aa90-a9253e95c74f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2829671568 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.2829671568
Directory /workspace/14.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.3600857578
Short name T70
Test name
Test status
Simulation time 1489850000 ps
CPU time 4.27 seconds
Started Aug 08 05:04:26 PM PDT 24
Finished Aug 08 05:04:35 PM PDT 24
Peak memory 164892 kb
Host smart-955a2ecd-3dc1-4f0e-aae3-6d6d5d7bfbc7
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3600857578 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.3600857578
Directory /workspace/16.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.552302597
Short name T32
Test name
Test status
Simulation time 1455830000 ps
CPU time 4.84 seconds
Started Aug 08 05:04:25 PM PDT 24
Finished Aug 08 05:04:36 PM PDT 24
Peak memory 164956 kb
Host smart-6a8a80e8-85bb-4f9c-b336-801cd4748493
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=552302597 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.552302597
Directory /workspace/17.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.2846675091
Short name T39
Test name
Test status
Simulation time 1599490000 ps
CPU time 5.78 seconds
Started Aug 08 05:04:27 PM PDT 24
Finished Aug 08 05:04:39 PM PDT 24
Peak memory 164812 kb
Host smart-0bfc7af4-1f3c-4f4d-adbf-e40418791b6f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2846675091 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.2846675091
Directory /workspace/18.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.318658430
Short name T44
Test name
Test status
Simulation time 1483530000 ps
CPU time 4.59 seconds
Started Aug 08 05:04:31 PM PDT 24
Finished Aug 08 05:04:41 PM PDT 24
Peak memory 164816 kb
Host smart-d3a2d8de-4aa7-457c-aee8-27036934cd6c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=318658430 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.318658430
Directory /workspace/19.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.4002781896
Short name T35
Test name
Test status
Simulation time 1320750000 ps
CPU time 3.84 seconds
Started Aug 08 05:04:19 PM PDT 24
Finished Aug 08 05:04:28 PM PDT 24
Peak memory 164860 kb
Host smart-2a29fca9-0841-4bb3-a62a-cadf43965705
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4002781896 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.4002781896
Directory /workspace/2.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.2943623120
Short name T43
Test name
Test status
Simulation time 1383610000 ps
CPU time 4.88 seconds
Started Aug 08 05:04:31 PM PDT 24
Finished Aug 08 05:04:41 PM PDT 24
Peak memory 164760 kb
Host smart-adab3a0a-28c4-482c-8503-091f7e9e9d55
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2943623120 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.2943623120
Directory /workspace/20.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.100635690
Short name T46
Test name
Test status
Simulation time 1256770000 ps
CPU time 3.59 seconds
Started Aug 08 05:04:24 PM PDT 24
Finished Aug 08 05:04:32 PM PDT 24
Peak memory 164788 kb
Host smart-f2aa0ddf-9146-4d56-ac96-ded2b163a6c1
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=100635690 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.100635690
Directory /workspace/21.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.3551682451
Short name T37
Test name
Test status
Simulation time 1467510000 ps
CPU time 4.75 seconds
Started Aug 08 05:04:31 PM PDT 24
Finished Aug 08 05:04:42 PM PDT 24
Peak memory 164732 kb
Host smart-38aafb47-a62e-4de3-ab5c-4a0c89c638d7
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3551682451 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.3551682451
Directory /workspace/22.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.1541452820
Short name T61
Test name
Test status
Simulation time 1179350000 ps
CPU time 2.99 seconds
Started Aug 08 05:04:25 PM PDT 24
Finished Aug 08 05:04:32 PM PDT 24
Peak memory 164832 kb
Host smart-a83f3e98-3aab-4f26-a583-820fe3887bb4
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1541452820 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.1541452820
Directory /workspace/23.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.2810171064
Short name T11
Test name
Test status
Simulation time 1521570000 ps
CPU time 4.5 seconds
Started Aug 08 05:04:39 PM PDT 24
Finished Aug 08 05:04:49 PM PDT 24
Peak memory 164860 kb
Host smart-06eca7ec-8600-46cd-99ef-8d6483592a94
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2810171064 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.2810171064
Directory /workspace/24.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.1961566708
Short name T41
Test name
Test status
Simulation time 1557530000 ps
CPU time 4.15 seconds
Started Aug 08 05:04:30 PM PDT 24
Finished Aug 08 05:04:40 PM PDT 24
Peak memory 164852 kb
Host smart-075b1961-4b18-49dd-9605-447d5796ec04
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1961566708 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.1961566708
Directory /workspace/25.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.647995681
Short name T34
Test name
Test status
Simulation time 1352390000 ps
CPU time 4.62 seconds
Started Aug 08 05:04:33 PM PDT 24
Finished Aug 08 05:04:43 PM PDT 24
Peak memory 164836 kb
Host smart-67504f72-7190-4ef2-b415-46040708626b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=647995681 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.647995681
Directory /workspace/26.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.1228695968
Short name T49
Test name
Test status
Simulation time 1442030000 ps
CPU time 3.22 seconds
Started Aug 08 05:04:33 PM PDT 24
Finished Aug 08 05:04:40 PM PDT 24
Peak memory 164804 kb
Host smart-39509b34-42b9-4a56-9772-6ca5a61230a9
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1228695968 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.1228695968
Directory /workspace/27.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.2965364066
Short name T55
Test name
Test status
Simulation time 1593890000 ps
CPU time 5.34 seconds
Started Aug 08 05:04:27 PM PDT 24
Finished Aug 08 05:04:39 PM PDT 24
Peak memory 164776 kb
Host smart-98fe7051-f140-42e9-b4a1-f17b21bf793d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2965364066 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.2965364066
Directory /workspace/28.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.1183296940
Short name T60
Test name
Test status
Simulation time 1085610000 ps
CPU time 3.17 seconds
Started Aug 08 05:04:28 PM PDT 24
Finished Aug 08 05:04:35 PM PDT 24
Peak memory 164800 kb
Host smart-704b74d1-afa7-45d7-b7e5-63dcc814b042
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1183296940 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.1183296940
Directory /workspace/29.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.2566762874
Short name T31
Test name
Test status
Simulation time 1215610000 ps
CPU time 3.6 seconds
Started Aug 08 05:04:29 PM PDT 24
Finished Aug 08 05:04:37 PM PDT 24
Peak memory 164816 kb
Host smart-fe19a645-bf5b-401d-8656-0d8dfde4463a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2566762874 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.2566762874
Directory /workspace/3.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.497965697
Short name T69
Test name
Test status
Simulation time 1529770000 ps
CPU time 5.07 seconds
Started Aug 08 05:04:25 PM PDT 24
Finished Aug 08 05:04:37 PM PDT 24
Peak memory 164804 kb
Host smart-a3b71ecf-b135-4414-9e3e-adab427bd614
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=497965697 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.497965697
Directory /workspace/30.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.2288998861
Short name T47
Test name
Test status
Simulation time 1351270000 ps
CPU time 4.43 seconds
Started Aug 08 05:04:33 PM PDT 24
Finished Aug 08 05:04:42 PM PDT 24
Peak memory 164820 kb
Host smart-63cd6b48-b9ee-43c2-aefa-a43700762ae0
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2288998861 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.2288998861
Directory /workspace/31.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.1155822565
Short name T65
Test name
Test status
Simulation time 1502370000 ps
CPU time 5.24 seconds
Started Aug 08 05:04:34 PM PDT 24
Finished Aug 08 05:04:46 PM PDT 24
Peak memory 164816 kb
Host smart-6922074c-453b-47f9-bac3-36395f38997c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1155822565 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.1155822565
Directory /workspace/32.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.1033967748
Short name T51
Test name
Test status
Simulation time 1508250000 ps
CPU time 4.49 seconds
Started Aug 08 05:04:33 PM PDT 24
Finished Aug 08 05:04:43 PM PDT 24
Peak memory 164756 kb
Host smart-9e1e0fb1-de88-49a6-b618-643b769132e8
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1033967748 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.1033967748
Directory /workspace/33.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.3293991994
Short name T2
Test name
Test status
Simulation time 1589450000 ps
CPU time 6.06 seconds
Started Aug 08 05:04:33 PM PDT 24
Finished Aug 08 05:04:47 PM PDT 24
Peak memory 164908 kb
Host smart-db789f2f-9ca2-4621-9b1c-fb3c0583756f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3293991994 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.3293991994
Directory /workspace/34.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.2791493767
Short name T62
Test name
Test status
Simulation time 1449350000 ps
CPU time 3.91 seconds
Started Aug 08 05:04:35 PM PDT 24
Finished Aug 08 05:04:44 PM PDT 24
Peak memory 164792 kb
Host smart-1449024f-6a36-40d9-850d-2e3551183ebb
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2791493767 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.2791493767
Directory /workspace/35.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.2424350684
Short name T12
Test name
Test status
Simulation time 1488770000 ps
CPU time 4.45 seconds
Started Aug 08 05:04:36 PM PDT 24
Finished Aug 08 05:04:47 PM PDT 24
Peak memory 164852 kb
Host smart-5058b784-e0cf-4d53-81e6-94a9f50fe1d9
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2424350684 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.2424350684
Directory /workspace/36.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.1552132150
Short name T10
Test name
Test status
Simulation time 1525270000 ps
CPU time 3.88 seconds
Started Aug 08 05:04:37 PM PDT 24
Finished Aug 08 05:04:46 PM PDT 24
Peak memory 164832 kb
Host smart-73d85c77-ea5d-47e2-a4d9-0cff7b30e7a9
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1552132150 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.1552132150
Directory /workspace/37.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.2141753810
Short name T8
Test name
Test status
Simulation time 1582150000 ps
CPU time 3.4 seconds
Started Aug 08 05:04:33 PM PDT 24
Finished Aug 08 05:04:41 PM PDT 24
Peak memory 164920 kb
Host smart-d49b4285-7fbb-404b-a9ac-b522bbd02650
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2141753810 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.2141753810
Directory /workspace/38.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.2212938905
Short name T67
Test name
Test status
Simulation time 1464550000 ps
CPU time 5.25 seconds
Started Aug 08 05:04:33 PM PDT 24
Finished Aug 08 05:04:45 PM PDT 24
Peak memory 164844 kb
Host smart-0026fdb8-f14e-4810-9fd4-fb8680a8ce24
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2212938905 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.2212938905
Directory /workspace/39.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.3981815534
Short name T33
Test name
Test status
Simulation time 1586210000 ps
CPU time 4.63 seconds
Started Aug 08 05:04:28 PM PDT 24
Finished Aug 08 05:04:38 PM PDT 24
Peak memory 164920 kb
Host smart-874c75f3-608a-46d8-92b6-7b05495a3c55
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3981815534 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.3981815534
Directory /workspace/4.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.302309814
Short name T38
Test name
Test status
Simulation time 1461430000 ps
CPU time 4.16 seconds
Started Aug 08 05:04:32 PM PDT 24
Finished Aug 08 05:04:42 PM PDT 24
Peak memory 164788 kb
Host smart-af6e45e4-c074-4cc2-b862-39e2acfe0f3e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=302309814 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.302309814
Directory /workspace/40.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.1955214497
Short name T58
Test name
Test status
Simulation time 1498830000 ps
CPU time 4.45 seconds
Started Aug 08 05:04:35 PM PDT 24
Finished Aug 08 05:04:44 PM PDT 24
Peak memory 164880 kb
Host smart-a723f396-f28f-4553-a3c6-743e9997de4a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1955214497 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.1955214497
Directory /workspace/41.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.3543343214
Short name T40
Test name
Test status
Simulation time 1531950000 ps
CPU time 3.16 seconds
Started Aug 08 05:04:35 PM PDT 24
Finished Aug 08 05:04:42 PM PDT 24
Peak memory 164760 kb
Host smart-4aea3d54-fe52-41b8-8f8e-ab407b3ebefc
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3543343214 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.3543343214
Directory /workspace/42.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.2465667743
Short name T56
Test name
Test status
Simulation time 1417950000 ps
CPU time 4.26 seconds
Started Aug 08 05:04:30 PM PDT 24
Finished Aug 08 05:04:39 PM PDT 24
Peak memory 164852 kb
Host smart-bb8a73f1-9d46-4068-903d-910354fbb6a7
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2465667743 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.2465667743
Directory /workspace/43.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.2512493701
Short name T52
Test name
Test status
Simulation time 1065050000 ps
CPU time 4.44 seconds
Started Aug 08 05:04:33 PM PDT 24
Finished Aug 08 05:04:43 PM PDT 24
Peak memory 164816 kb
Host smart-5e0bbd2c-7f80-432f-8f33-d7a8ad1a1bc5
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2512493701 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.2512493701
Directory /workspace/44.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.3492602383
Short name T42
Test name
Test status
Simulation time 1598850000 ps
CPU time 4.23 seconds
Started Aug 08 05:04:35 PM PDT 24
Finished Aug 08 05:04:44 PM PDT 24
Peak memory 164864 kb
Host smart-ff1cefb0-6bef-420c-bd68-94f533666dbd
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3492602383 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.3492602383
Directory /workspace/45.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.2870788455
Short name T9
Test name
Test status
Simulation time 1364910000 ps
CPU time 3.32 seconds
Started Aug 08 05:04:33 PM PDT 24
Finished Aug 08 05:04:41 PM PDT 24
Peak memory 164920 kb
Host smart-5c12396d-0cb8-461d-995a-1880a3ce040f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2870788455 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.2870788455
Directory /workspace/46.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.4281045923
Short name T59
Test name
Test status
Simulation time 1561030000 ps
CPU time 5.12 seconds
Started Aug 08 05:04:33 PM PDT 24
Finished Aug 08 05:04:44 PM PDT 24
Peak memory 164820 kb
Host smart-7c653888-444c-462a-bf88-4aa1f0ffc7d2
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4281045923 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.4281045923
Directory /workspace/47.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.3653709658
Short name T45
Test name
Test status
Simulation time 1486070000 ps
CPU time 3.98 seconds
Started Aug 08 05:04:34 PM PDT 24
Finished Aug 08 05:04:43 PM PDT 24
Peak memory 164808 kb
Host smart-f8ed073c-09d8-45cd-aad5-42d8ea1fd2c1
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3653709658 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.3653709658
Directory /workspace/48.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.1863734734
Short name T63
Test name
Test status
Simulation time 1584690000 ps
CPU time 5.98 seconds
Started Aug 08 05:04:32 PM PDT 24
Finished Aug 08 05:04:46 PM PDT 24
Peak memory 164908 kb
Host smart-f56656c5-57bf-474a-88a0-c3767db4838d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1863734734 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.1863734734
Directory /workspace/49.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.1587203991
Short name T64
Test name
Test status
Simulation time 1529450000 ps
CPU time 5.86 seconds
Started Aug 08 05:04:24 PM PDT 24
Finished Aug 08 05:04:37 PM PDT 24
Peak memory 164764 kb
Host smart-da04191d-312b-4443-b487-2af17dccf708
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1587203991 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.1587203991
Directory /workspace/5.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.3340414974
Short name T66
Test name
Test status
Simulation time 1161330000 ps
CPU time 3.01 seconds
Started Aug 08 05:04:30 PM PDT 24
Finished Aug 08 05:04:36 PM PDT 24
Peak memory 164820 kb
Host smart-5f9ab812-afbf-4518-aae5-f13c44b31e2d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3340414974 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.3340414974
Directory /workspace/6.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.950030700
Short name T3
Test name
Test status
Simulation time 1552890000 ps
CPU time 4.7 seconds
Started Aug 08 05:04:27 PM PDT 24
Finished Aug 08 05:04:37 PM PDT 24
Peak memory 164916 kb
Host smart-ee649cd6-d180-4af0-8679-506fc21ad1bf
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=950030700 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.950030700
Directory /workspace/7.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.3221209573
Short name T1
Test name
Test status
Simulation time 1140170000 ps
CPU time 3.09 seconds
Started Aug 08 05:04:26 PM PDT 24
Finished Aug 08 05:04:33 PM PDT 24
Peak memory 164756 kb
Host smart-a43bba08-506b-403f-9ce7-da695acac320
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3221209573 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.3221209573
Directory /workspace/8.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.579867658
Short name T13
Test name
Test status
Simulation time 1368450000 ps
CPU time 3.89 seconds
Started Aug 08 05:04:27 PM PDT 24
Finished Aug 08 05:04:35 PM PDT 24
Peak memory 164876 kb
Host smart-3dba480b-87f3-44d3-b2a1-3d1110a6cbd5
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=579867658 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.579867658
Directory /workspace/9.prim_lfsr_gal_smoke/latest
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