Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.31 100.00 96.55 100.00 100.00 95.00


Total tests in report: 200
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
87.31 87.31 100.00 100.00 96.55 96.55 100.00 100.00 100.00 100.00 40.00 40.00 /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.2976415243
95.31 8.00 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 80.00 40.00 /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.2798357649
98.31 3.00 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 95.00 15.00 /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.106580382

Tests that do not contribute to grading

Name
/workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.2702611217
/workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.3365461561
/workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.3347884078
/workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.250142086
/workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.1430461344
/workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.1527914908
/workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.3763019950
/workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.648579042
/workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.4089445180
/workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.284096935
/workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.1848615670
/workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.3728377128
/workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.2021233539
/workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.3898827321
/workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.1113109431
/workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.1259478199
/workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.3650458029
/workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.3199002590
/workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.2401941410
/workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.357787386
/workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.2877002761
/workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.3702391744
/workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.3731116804
/workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3084577878
/workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.1804077424
/workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.979912677
/workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.838893523
/workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.2416210022
/workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.1749990271
/workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.3663905854
/workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.3408847065
/workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.1323429444
/workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.792140328
/workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.1800633429
/workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.3279624536
/workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.3478089250
/workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.854158918
/workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.2574084372
/workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.900473257
/workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.785195850
/workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.3235126767
/workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.2099539004
/workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.2820939562
/workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.2073116899
/workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.2282631164
/workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.1923300950
/workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.4244090749
/workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1245357879
/workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.3027680381
/workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.860109515
/workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.2255914706
/workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.3123533462
/workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.1672464183
/workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.2175813865
/workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.3064024845
/workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.2277479452
/workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.932981811
/workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.1493658087
/workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.3166450457
/workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.3227882558
/workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.885075697
/workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.1783305924
/workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.4270469029
/workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.85279520
/workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.2433578714
/workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.1160779092
/workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.4039846819
/workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.4214449099
/workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.1994705477
/workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.1584547178
/workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.2455260296
/workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.878855081
/workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.2116874767
/workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.4202235115
/workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.2247895807
/workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.2773858028
/workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.767668133
/workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.3736672055
/workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.244585820
/workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.3864005612
/workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.993039848
/workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.1663432650
/workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.2759884003
/workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.2797499128
/workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.1643352862
/workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.410609178
/workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.846460728
/workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.3844309336
/workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.2782946994
/workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.2601182611
/workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.869153326
/workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.2012258726
/workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.2156185283
/workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.1709802277
/workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.2014313871
/workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.3825679928
/workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.600921549
/workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.2172900939
/workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.3600195077
/workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.2789175989
/workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.3625020537
/workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.1777404753
/workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.2636081622
/workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.3093906296
/workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.220303534
/workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.3916154271
/workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.1842433139
/workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.2402995414
/workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.2594257622
/workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.2959469722
/workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.1923483115
/workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.1599419061
/workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3335786698
/workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.1994552921
/workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.1930011807
/workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.1205418530
/workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.3186523634
/workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.3058203642
/workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.3593500429
/workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.1000491587
/workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.1747098841
/workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.1766637214
/workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.357412210
/workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.2703916823
/workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.3024680292
/workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.579845804
/workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.94436618
/workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.4191042986
/workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.1793602715
/workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.2882740480
/workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.2332130425
/workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.2079434201
/workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.1367720152
/workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.2674340613
/workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.2190284761
/workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.921415671
/workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.3054448441
/workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.282487212
/workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.1577185732
/workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.58099894
/workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.3192963417
/workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.4292248734
/workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.4169873358
/workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.3483869091
/workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.3050974352
/workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.1916906280
/workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.718410063
/workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.3851650229
/workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.383371463
/workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.4146629603
/workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.1193607161
/workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.1007516938
/workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.4271130941
/workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.3943422641
/workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.3199594819
/workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.1354139154
/workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.3230116241
/workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.3120980428
/workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.153337691
/workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.3435457810
/workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.3301462524
/workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.4066203260
/workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.2945941301
/workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.494623565
/workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.1361534853
/workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.3334392856
/workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.4107992509
/workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.3378175692
/workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.3582396126
/workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.1086347113
/workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.342210203
/workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.1542026294
/workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.2260175908
/workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.1449870770
/workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.3915380539
/workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.1952702292
/workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.2358851199
/workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.3261058364
/workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.3717051743
/workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.613413799
/workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.3059235446
/workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.1613005002
/workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.3709507880
/workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.76746956
/workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.2971801149
/workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.4145626515
/workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.1091998209
/workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.3758413042
/workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.1807869195
/workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.297859320
/workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.109427580
/workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.2855174296
/workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.1676313037
/workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.4179058603
/workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.2102580386
/workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.4055066657
/workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.2876660592



Total test records in report: 200
tests.html | tests1.html | tests2.html | tests3.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.76746956 Aug 09 04:19:55 PM PDT 24 Aug 09 04:20:06 PM PDT 24 1501510000 ps
T2 /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.3199594819 Aug 09 04:19:55 PM PDT 24 Aug 09 04:20:05 PM PDT 24 1397130000 ps
T3 /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.3758413042 Aug 09 04:19:52 PM PDT 24 Aug 09 04:20:03 PM PDT 24 1483090000 ps
T7 /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.3717051743 Aug 09 04:19:59 PM PDT 24 Aug 09 04:20:09 PM PDT 24 1409510000 ps
T8 /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.4107992509 Aug 09 04:19:55 PM PDT 24 Aug 09 04:20:06 PM PDT 24 1565630000 ps
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T128 /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.3702391744 Aug 09 04:32:01 PM PDT 24 Aug 09 05:09:32 PM PDT 24 336514310000 ps
T129 /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.1848615670 Aug 09 04:32:02 PM PDT 24 Aug 09 05:14:06 PM PDT 24 336696930000 ps
T130 /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.2282631164 Aug 09 04:20:51 PM PDT 24 Aug 09 04:53:16 PM PDT 24 336464870000 ps
T131 /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.979912677 Aug 09 04:32:13 PM PDT 24 Aug 09 05:07:31 PM PDT 24 336716670000 ps
T132 /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.3728377128 Aug 09 04:20:43 PM PDT 24 Aug 09 04:54:02 PM PDT 24 336450470000 ps
T133 /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3084577878 Aug 09 04:32:01 PM PDT 24 Aug 09 05:09:39 PM PDT 24 337028210000 ps
T134 /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.2401941410 Aug 09 04:32:02 PM PDT 24 Aug 09 05:08:50 PM PDT 24 336378110000 ps
T135 /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.648579042 Aug 09 04:32:01 PM PDT 24 Aug 09 05:14:02 PM PDT 24 336452930000 ps
T136 /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.3365461561 Aug 09 04:32:07 PM PDT 24 Aug 09 04:57:12 PM PDT 24 337005170000 ps
T137 /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.4089445180 Aug 09 04:31:57 PM PDT 24 Aug 09 05:06:25 PM PDT 24 336823130000 ps
T138 /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.785195850 Aug 09 04:31:56 PM PDT 24 Aug 09 05:07:06 PM PDT 24 336689530000 ps
T139 /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.1527914908 Aug 09 04:32:30 PM PDT 24 Aug 09 05:06:20 PM PDT 24 336824530000 ps
T140 /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.3199002590 Aug 09 04:32:10 PM PDT 24 Aug 09 05:09:13 PM PDT 24 337015930000 ps
T141 /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.1804077424 Aug 09 04:32:02 PM PDT 24 Aug 09 05:06:46 PM PDT 24 336337070000 ps
T142 /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.3650458029 Aug 09 04:32:31 PM PDT 24 Aug 09 04:55:15 PM PDT 24 336586030000 ps
T143 /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.900473257 Aug 09 04:32:12 PM PDT 24 Aug 09 05:08:30 PM PDT 24 336835250000 ps
T144 /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.3898827321 Aug 09 04:32:13 PM PDT 24 Aug 09 05:08:15 PM PDT 24 336939390000 ps
T145 /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.1259478199 Aug 09 04:32:31 PM PDT 24 Aug 09 05:08:09 PM PDT 24 336456890000 ps
T146 /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.2820939562 Aug 09 04:32:45 PM PDT 24 Aug 09 05:01:59 PM PDT 24 336385290000 ps
T147 /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.3663905854 Aug 09 04:31:57 PM PDT 24 Aug 09 05:07:52 PM PDT 24 336832850000 ps
T148 /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.1923300950 Aug 09 04:32:08 PM PDT 24 Aug 09 05:03:50 PM PDT 24 336511490000 ps
T149 /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.2099539004 Aug 09 04:32:06 PM PDT 24 Aug 09 05:05:16 PM PDT 24 336427970000 ps
T150 /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.792140328 Aug 09 04:32:08 PM PDT 24 Aug 09 05:09:49 PM PDT 24 336829450000 ps
T151 /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.282487212 Aug 09 04:32:29 PM PDT 24 Aug 09 04:32:46 PM PDT 24 1401270000 ps
T152 /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.3593500429 Aug 09 04:32:01 PM PDT 24 Aug 09 04:32:07 PM PDT 24 1323490000 ps
T153 /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.1923483115 Aug 09 04:32:50 PM PDT 24 Aug 09 04:32:59 PM PDT 24 1417510000 ps
T154 /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.1994552921 Aug 09 04:32:04 PM PDT 24 Aug 09 04:32:12 PM PDT 24 1451430000 ps
T155 /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.3024680292 Aug 09 04:32:25 PM PDT 24 Aug 09 04:32:33 PM PDT 24 1549230000 ps
T156 /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.4292248734 Aug 09 04:32:04 PM PDT 24 Aug 09 04:32:12 PM PDT 24 1436470000 ps
T157 /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.3058203642 Aug 09 04:32:23 PM PDT 24 Aug 09 04:32:31 PM PDT 24 1486790000 ps
T158 /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.3054448441 Aug 09 04:32:08 PM PDT 24 Aug 09 04:32:15 PM PDT 24 1445970000 ps
T159 /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.1747098841 Aug 09 04:32:09 PM PDT 24 Aug 09 04:32:18 PM PDT 24 1453150000 ps
T160 /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.2789175989 Aug 09 04:32:02 PM PDT 24 Aug 09 04:32:11 PM PDT 24 1370790000 ps
T161 /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.2402995414 Aug 09 04:32:35 PM PDT 24 Aug 09 04:32:44 PM PDT 24 1492270000 ps
T162 /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.1000491587 Aug 09 04:32:18 PM PDT 24 Aug 09 04:32:25 PM PDT 24 1462590000 ps
T163 /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.3916154271 Aug 09 04:32:04 PM PDT 24 Aug 09 04:32:12 PM PDT 24 1407370000 ps
T164 /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.3851650229 Aug 09 04:31:58 PM PDT 24 Aug 09 04:32:06 PM PDT 24 1456190000 ps
T165 /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.3625020537 Aug 09 04:32:31 PM PDT 24 Aug 09 04:32:40 PM PDT 24 1474190000 ps
T166 /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.2703916823 Aug 09 04:32:12 PM PDT 24 Aug 09 04:32:21 PM PDT 24 1638390000 ps
T167 /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.2636081622 Aug 09 04:33:14 PM PDT 24 Aug 09 04:33:24 PM PDT 24 1573090000 ps
T168 /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.4169873358 Aug 09 04:32:06 PM PDT 24 Aug 09 04:32:14 PM PDT 24 1456250000 ps
T169 /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.3050974352 Aug 09 04:32:41 PM PDT 24 Aug 09 04:32:50 PM PDT 24 1515790000 ps
T170 /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.921415671 Aug 09 04:32:01 PM PDT 24 Aug 09 04:32:09 PM PDT 24 1557610000 ps
T171 /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.1367720152 Aug 09 04:32:05 PM PDT 24 Aug 09 04:32:15 PM PDT 24 1426170000 ps
T172 /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.2079434201 Aug 09 04:32:13 PM PDT 24 Aug 09 04:32:21 PM PDT 24 1549170000 ps
T173 /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.3093906296 Aug 09 04:31:54 PM PDT 24 Aug 09 04:32:06 PM PDT 24 1427530000 ps
T174 /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.3192963417 Aug 09 04:32:10 PM PDT 24 Aug 09 04:32:17 PM PDT 24 1286030000 ps
T175 /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3335786698 Aug 09 04:32:14 PM PDT 24 Aug 09 04:32:20 PM PDT 24 1373070000 ps
T176 /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.579845804 Aug 09 04:32:04 PM PDT 24 Aug 09 04:32:12 PM PDT 24 1457770000 ps
T177 /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.3483869091 Aug 09 04:31:45 PM PDT 24 Aug 09 04:31:55 PM PDT 24 1518650000 ps
T178 /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.1916906280 Aug 09 04:32:50 PM PDT 24 Aug 09 04:32:59 PM PDT 24 1365730000 ps
T179 /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.58099894 Aug 09 04:32:19 PM PDT 24 Aug 09 04:32:26 PM PDT 24 1392970000 ps
T180 /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.4191042986 Aug 09 04:32:02 PM PDT 24 Aug 09 04:32:09 PM PDT 24 1539670000 ps
T181 /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.220303534 Aug 09 04:32:20 PM PDT 24 Aug 09 04:32:29 PM PDT 24 1513290000 ps
T182 /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.3600195077 Aug 09 04:32:49 PM PDT 24 Aug 09 04:32:57 PM PDT 24 1509790000 ps
T183 /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.2959469722 Aug 09 04:32:17 PM PDT 24 Aug 09 04:32:25 PM PDT 24 1238610000 ps
T184 /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.2190284761 Aug 09 04:32:08 PM PDT 24 Aug 09 04:32:16 PM PDT 24 1620530000 ps
T185 /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.1842433139 Aug 09 04:32:10 PM PDT 24 Aug 09 04:32:20 PM PDT 24 1530110000 ps
T186 /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.1930011807 Aug 09 04:32:10 PM PDT 24 Aug 09 04:32:20 PM PDT 24 1498290000 ps
T187 /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.94436618 Aug 09 04:32:03 PM PDT 24 Aug 09 04:32:11 PM PDT 24 1437690000 ps
T188 /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.1577185732 Aug 09 04:32:11 PM PDT 24 Aug 09 04:32:19 PM PDT 24 1365930000 ps
T189 /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.1766637214 Aug 09 04:32:34 PM PDT 24 Aug 09 04:32:41 PM PDT 24 1426030000 ps
T190 /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.2674340613 Aug 09 04:32:04 PM PDT 24 Aug 09 04:32:13 PM PDT 24 1282890000 ps
T191 /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.1793602715 Aug 09 04:32:24 PM PDT 24 Aug 09 04:32:34 PM PDT 24 1503090000 ps
T192 /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.718410063 Aug 09 04:32:26 PM PDT 24 Aug 09 04:32:37 PM PDT 24 1595050000 ps
T193 /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.2332130425 Aug 09 04:32:26 PM PDT 24 Aug 09 04:32:33 PM PDT 24 1458530000 ps
T194 /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.2594257622 Aug 09 04:32:10 PM PDT 24 Aug 09 04:32:18 PM PDT 24 1472090000 ps
T195 /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.1205418530 Aug 09 04:32:01 PM PDT 24 Aug 09 04:32:11 PM PDT 24 1414570000 ps
T196 /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.1777404753 Aug 09 04:32:03 PM PDT 24 Aug 09 04:32:12 PM PDT 24 1496830000 ps
T197 /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.3186523634 Aug 09 04:32:05 PM PDT 24 Aug 09 04:32:13 PM PDT 24 1114190000 ps
T198 /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.357412210 Aug 09 04:32:18 PM PDT 24 Aug 09 04:32:26 PM PDT 24 1405610000 ps
T199 /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.1599419061 Aug 09 04:32:05 PM PDT 24 Aug 09 04:32:15 PM PDT 24 1413570000 ps
T200 /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.2882740480 Aug 09 04:32:00 PM PDT 24 Aug 09 04:32:09 PM PDT 24 1446050000 ps

Test location /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.2976415243
Short name T11
Test name
Test status
Simulation time 1608870000 ps
CPU time 6.06 seconds
Started Aug 09 04:19:42 PM PDT 24
Finished Aug 09 04:19:56 PM PDT 24
Peak memory 165044 kb
Host smart-a52b8cfe-360e-4fbf-8068-4a5e56f95d15
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2976415243 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.2976415243
Directory /workspace/0.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.2798357649
Short name T22
Test name
Test status
Simulation time 336583950000 ps
CPU time 723.72 seconds
Started Aug 09 04:25:32 PM PDT 24
Finished Aug 09 04:56:05 PM PDT 24
Peak memory 159628 kb
Host smart-45a23a64-f8e0-4a49-b26e-fc73ad7f4537
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2798357649 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.2798357649
Directory /workspace/0.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.106580382
Short name T26
Test name
Test status
Simulation time 337073430000 ps
CPU time 795.97 seconds
Started Aug 09 04:32:12 PM PDT 24
Finished Aug 09 05:04:41 PM PDT 24
Peak memory 160632 kb
Host smart-70410903-b62b-4477-a11d-4d72b8686c8a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=106580382 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.106580382
Directory /workspace/1.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.2702611217
Short name T126
Test name
Test status
Simulation time 336976690000 ps
CPU time 849.08 seconds
Started Aug 09 04:32:36 PM PDT 24
Finished Aug 09 05:07:09 PM PDT 24
Peak memory 160648 kb
Host smart-cf8de9ad-6dbc-4551-a58a-495583b5fd58
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2702611217 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.2702611217
Directory /workspace/0.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.3365461561
Short name T136
Test name
Test status
Simulation time 337005170000 ps
CPU time 598.75 seconds
Started Aug 09 04:32:07 PM PDT 24
Finished Aug 09 04:57:12 PM PDT 24
Peak memory 160660 kb
Host smart-23537b8a-e705-4f53-93a9-0e602640e4cc
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3365461561 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.3365461561
Directory /workspace/10.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.3347884078
Short name T29
Test name
Test status
Simulation time 336547750000 ps
CPU time 996.25 seconds
Started Aug 09 04:32:03 PM PDT 24
Finished Aug 09 05:14:25 PM PDT 24
Peak memory 160924 kb
Host smart-63d2e954-47bd-4643-976a-e0270dff007d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3347884078 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.3347884078
Directory /workspace/11.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.250142086
Short name T30
Test name
Test status
Simulation time 336635230000 ps
CPU time 862.92 seconds
Started Aug 09 04:31:50 PM PDT 24
Finished Aug 09 05:07:37 PM PDT 24
Peak memory 160696 kb
Host smart-edbca8df-bb03-49cb-92b3-4003496a4c03
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=250142086 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.250142086
Directory /workspace/12.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.1430461344
Short name T121
Test name
Test status
Simulation time 336893870000 ps
CPU time 850.99 seconds
Started Aug 09 04:32:04 PM PDT 24
Finished Aug 09 05:07:19 PM PDT 24
Peak memory 160656 kb
Host smart-0a55466a-a82e-458b-bc9b-15135d5ec72d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1430461344 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.1430461344
Directory /workspace/13.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.1527914908
Short name T139
Test name
Test status
Simulation time 336824530000 ps
CPU time 803.92 seconds
Started Aug 09 04:32:30 PM PDT 24
Finished Aug 09 05:06:20 PM PDT 24
Peak memory 160584 kb
Host smart-b0790da6-4a9c-47fc-99ba-bd2e96d3c645
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1527914908 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.1527914908
Directory /workspace/14.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.3763019950
Short name T24
Test name
Test status
Simulation time 336567670000 ps
CPU time 858.79 seconds
Started Aug 09 04:32:00 PM PDT 24
Finished Aug 09 05:06:37 PM PDT 24
Peak memory 160600 kb
Host smart-6f6b071b-6206-4f4e-88b4-f859efbc03a9
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3763019950 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.3763019950
Directory /workspace/15.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.648579042
Short name T135
Test name
Test status
Simulation time 336452930000 ps
CPU time 986.81 seconds
Started Aug 09 04:32:01 PM PDT 24
Finished Aug 09 05:14:02 PM PDT 24
Peak memory 160920 kb
Host smart-2c5a5017-ee8f-483e-92c7-3f8249a303be
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=648579042 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.648579042
Directory /workspace/16.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.4089445180
Short name T137
Test name
Test status
Simulation time 336823130000 ps
CPU time 857.19 seconds
Started Aug 09 04:31:57 PM PDT 24
Finished Aug 09 05:06:25 PM PDT 24
Peak memory 160684 kb
Host smart-4f8c8513-1dcc-487c-97d1-c7df72d681e2
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4089445180 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.4089445180
Directory /workspace/17.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.284096935
Short name T5
Test name
Test status
Simulation time 336341090000 ps
CPU time 847.83 seconds
Started Aug 09 04:32:25 PM PDT 24
Finished Aug 09 05:07:28 PM PDT 24
Peak memory 160568 kb
Host smart-17b77bed-7738-41a9-9b25-4220637a7013
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=284096935 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.284096935
Directory /workspace/18.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.1848615670
Short name T129
Test name
Test status
Simulation time 336696930000 ps
CPU time 982.3 seconds
Started Aug 09 04:32:02 PM PDT 24
Finished Aug 09 05:14:06 PM PDT 24
Peak memory 160924 kb
Host smart-25c5e7bd-3237-43c8-8560-d87d5ddb2973
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1848615670 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.1848615670
Directory /workspace/19.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.3728377128
Short name T132
Test name
Test status
Simulation time 336450470000 ps
CPU time 812.91 seconds
Started Aug 09 04:20:43 PM PDT 24
Finished Aug 09 04:54:02 PM PDT 24
Peak memory 160580 kb
Host smart-5a2193e9-4a65-4117-b969-1007225be391
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3728377128 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.3728377128
Directory /workspace/2.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.2021233539
Short name T112
Test name
Test status
Simulation time 337055690000 ps
CPU time 606.39 seconds
Started Aug 09 04:31:55 PM PDT 24
Finished Aug 09 04:57:08 PM PDT 24
Peak memory 160660 kb
Host smart-1f55b659-bf96-4288-968d-ca8949b778f4
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2021233539 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.2021233539
Directory /workspace/20.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.3898827321
Short name T144
Test name
Test status
Simulation time 336939390000 ps
CPU time 846.33 seconds
Started Aug 09 04:32:13 PM PDT 24
Finished Aug 09 05:08:15 PM PDT 24
Peak memory 160644 kb
Host smart-db8f8ba4-75ea-4a87-a14b-4c8e8a10e9cf
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3898827321 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.3898827321
Directory /workspace/21.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.1113109431
Short name T28
Test name
Test status
Simulation time 336582010000 ps
CPU time 850.72 seconds
Started Aug 09 04:31:45 PM PDT 24
Finished Aug 09 05:07:05 PM PDT 24
Peak memory 160640 kb
Host smart-ca63ac0b-ab60-4d99-a090-fa3efff6ee9d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1113109431 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.1113109431
Directory /workspace/22.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.1259478199
Short name T145
Test name
Test status
Simulation time 336456890000 ps
CPU time 863.46 seconds
Started Aug 09 04:32:31 PM PDT 24
Finished Aug 09 05:08:09 PM PDT 24
Peak memory 160696 kb
Host smart-f6ca43e2-a074-483f-8884-d2b0bf4e041a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1259478199 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.1259478199
Directory /workspace/23.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.3650458029
Short name T142
Test name
Test status
Simulation time 336586030000 ps
CPU time 522.55 seconds
Started Aug 09 04:32:31 PM PDT 24
Finished Aug 09 04:55:15 PM PDT 24
Peak memory 160652 kb
Host smart-fdb4d0bd-c678-4e33-ac4b-3a5748325af8
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3650458029 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.3650458029
Directory /workspace/24.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.3199002590
Short name T140
Test name
Test status
Simulation time 337015930000 ps
CPU time 910.17 seconds
Started Aug 09 04:32:10 PM PDT 24
Finished Aug 09 05:09:13 PM PDT 24
Peak memory 160656 kb
Host smart-a09c57d3-aacb-49b1-a160-fd4f67b07781
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3199002590 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.3199002590
Directory /workspace/25.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.2401941410
Short name T134
Test name
Test status
Simulation time 336378110000 ps
CPU time 881.03 seconds
Started Aug 09 04:32:02 PM PDT 24
Finished Aug 09 05:08:50 PM PDT 24
Peak memory 160696 kb
Host smart-da70587e-cc55-49c6-82eb-103c4321960c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2401941410 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.2401941410
Directory /workspace/26.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.357787386
Short name T27
Test name
Test status
Simulation time 336646310000 ps
CPU time 695.41 seconds
Started Aug 09 04:32:10 PM PDT 24
Finished Aug 09 05:00:28 PM PDT 24
Peak memory 160684 kb
Host smart-bd1317cd-47ae-4544-aa19-8e079c96e5ad
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=357787386 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.357787386
Directory /workspace/27.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.2877002761
Short name T120
Test name
Test status
Simulation time 336524810000 ps
CPU time 798.39 seconds
Started Aug 09 04:32:11 PM PDT 24
Finished Aug 09 05:05:43 PM PDT 24
Peak memory 160628 kb
Host smart-cd38dd88-d015-41a6-ba07-6798868efc7b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2877002761 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.2877002761
Directory /workspace/28.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.3702391744
Short name T128
Test name
Test status
Simulation time 336514310000 ps
CPU time 867.62 seconds
Started Aug 09 04:32:01 PM PDT 24
Finished Aug 09 05:09:32 PM PDT 24
Peak memory 160648 kb
Host smart-b0d4e73d-2d00-4c8f-8252-c31db48cabe7
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3702391744 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.3702391744
Directory /workspace/29.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.3731116804
Short name T117
Test name
Test status
Simulation time 336930650000 ps
CPU time 748.58 seconds
Started Aug 09 04:25:48 PM PDT 24
Finished Aug 09 04:55:55 PM PDT 24
Peak memory 159252 kb
Host smart-acccf601-0c7c-4a56-8a49-9eab60aee993
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3731116804 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.3731116804
Directory /workspace/3.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3084577878
Short name T133
Test name
Test status
Simulation time 337028210000 ps
CPU time 926.08 seconds
Started Aug 09 04:32:01 PM PDT 24
Finished Aug 09 05:09:39 PM PDT 24
Peak memory 160848 kb
Host smart-f3bc2001-1ea6-4602-8c9d-9478927a6b95
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3084577878 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.3084577878
Directory /workspace/30.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.1804077424
Short name T141
Test name
Test status
Simulation time 336337070000 ps
CPU time 836.59 seconds
Started Aug 09 04:32:02 PM PDT 24
Finished Aug 09 05:06:46 PM PDT 24
Peak memory 160656 kb
Host smart-b8b0c438-4b30-4765-9db1-445932b5bdde
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1804077424 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.1804077424
Directory /workspace/31.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.979912677
Short name T131
Test name
Test status
Simulation time 336716670000 ps
CPU time 851.11 seconds
Started Aug 09 04:32:13 PM PDT 24
Finished Aug 09 05:07:31 PM PDT 24
Peak memory 160688 kb
Host smart-7320022a-c34f-4a0c-a257-ac91d5a140f9
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=979912677 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.979912677
Directory /workspace/32.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.838893523
Short name T111
Test name
Test status
Simulation time 336608090000 ps
CPU time 943.43 seconds
Started Aug 09 04:32:18 PM PDT 24
Finished Aug 09 05:11:21 PM PDT 24
Peak memory 160628 kb
Host smart-f8d6baf2-7c84-4db9-b263-50159b5447e0
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=838893523 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.838893523
Directory /workspace/33.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.2416210022
Short name T118
Test name
Test status
Simulation time 336519830000 ps
CPU time 889.74 seconds
Started Aug 09 04:32:14 PM PDT 24
Finished Aug 09 05:07:42 PM PDT 24
Peak memory 160780 kb
Host smart-6468101f-1f67-4c99-a468-07c806b23409
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2416210022 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.2416210022
Directory /workspace/34.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.1749990271
Short name T127
Test name
Test status
Simulation time 337123010000 ps
CPU time 803.9 seconds
Started Aug 09 04:32:24 PM PDT 24
Finished Aug 09 05:05:24 PM PDT 24
Peak memory 160632 kb
Host smart-2ed19874-fb9a-4d63-8db8-cd22a654a2bd
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1749990271 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.1749990271
Directory /workspace/35.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.3663905854
Short name T147
Test name
Test status
Simulation time 336832850000 ps
CPU time 843.04 seconds
Started Aug 09 04:31:57 PM PDT 24
Finished Aug 09 05:07:52 PM PDT 24
Peak memory 160700 kb
Host smart-69660f26-95e4-4b02-b60c-38629c78c7a3
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3663905854 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.3663905854
Directory /workspace/36.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.3408847065
Short name T113
Test name
Test status
Simulation time 337171410000 ps
CPU time 915.04 seconds
Started Aug 09 04:32:06 PM PDT 24
Finished Aug 09 05:09:55 PM PDT 24
Peak memory 160848 kb
Host smart-9fa91d6d-2c2f-4b81-88fc-f15e6aada9a4
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3408847065 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.3408847065
Directory /workspace/37.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.1323429444
Short name T4
Test name
Test status
Simulation time 336434510000 ps
CPU time 850.12 seconds
Started Aug 09 04:32:33 PM PDT 24
Finished Aug 09 05:08:14 PM PDT 24
Peak memory 160656 kb
Host smart-759ed906-6292-4de2-b623-66a09f2a102a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1323429444 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.1323429444
Directory /workspace/38.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.792140328
Short name T150
Test name
Test status
Simulation time 336829450000 ps
CPU time 912.1 seconds
Started Aug 09 04:32:08 PM PDT 24
Finished Aug 09 05:09:49 PM PDT 24
Peak memory 160868 kb
Host smart-ce6ba67c-1d26-47e8-9807-7d4fab2e6bf5
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=792140328 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.792140328
Directory /workspace/39.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.1800633429
Short name T116
Test name
Test status
Simulation time 336781150000 ps
CPU time 809.91 seconds
Started Aug 09 04:32:02 PM PDT 24
Finished Aug 09 05:05:55 PM PDT 24
Peak memory 160636 kb
Host smart-7d34460f-40f7-4d23-b8ed-69e306fdde21
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1800633429 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.1800633429
Directory /workspace/4.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.3279624536
Short name T6
Test name
Test status
Simulation time 336335810000 ps
CPU time 905.4 seconds
Started Aug 09 04:32:17 PM PDT 24
Finished Aug 09 05:09:39 PM PDT 24
Peak memory 160848 kb
Host smart-90e5cdd4-80fd-4110-a073-646d32c73de4
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3279624536 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.3279624536
Directory /workspace/40.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.3478089250
Short name T122
Test name
Test status
Simulation time 336997310000 ps
CPU time 807.32 seconds
Started Aug 09 04:32:00 PM PDT 24
Finished Aug 09 05:04:52 PM PDT 24
Peak memory 160632 kb
Host smart-e178cda1-5d06-4af8-893a-04f4499acb29
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3478089250 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.3478089250
Directory /workspace/41.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.854158918
Short name T114
Test name
Test status
Simulation time 336465050000 ps
CPU time 979.21 seconds
Started Aug 09 04:32:03 PM PDT 24
Finished Aug 09 05:13:55 PM PDT 24
Peak memory 160916 kb
Host smart-a3e025f8-8362-404c-a413-7269742003c8
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=854158918 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.854158918
Directory /workspace/42.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.2574084372
Short name T125
Test name
Test status
Simulation time 336673590000 ps
CPU time 864.18 seconds
Started Aug 09 04:32:11 PM PDT 24
Finished Aug 09 05:08:15 PM PDT 24
Peak memory 160656 kb
Host smart-f0283927-0a4f-4881-95f6-6225310f502b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2574084372 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.2574084372
Directory /workspace/43.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.900473257
Short name T143
Test name
Test status
Simulation time 336835250000 ps
CPU time 877.67 seconds
Started Aug 09 04:32:12 PM PDT 24
Finished Aug 09 05:08:30 PM PDT 24
Peak memory 160688 kb
Host smart-c9daff66-1c96-44a8-9d6f-7f52820e6cec
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=900473257 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.900473257
Directory /workspace/44.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.785195850
Short name T138
Test name
Test status
Simulation time 336689530000 ps
CPU time 862.23 seconds
Started Aug 09 04:31:56 PM PDT 24
Finished Aug 09 05:07:06 PM PDT 24
Peak memory 160620 kb
Host smart-5abbe06f-4dac-4a2b-adbf-a2ce39a527c9
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=785195850 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.785195850
Directory /workspace/45.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.3235126767
Short name T124
Test name
Test status
Simulation time 336547130000 ps
CPU time 810.49 seconds
Started Aug 09 04:32:04 PM PDT 24
Finished Aug 09 05:06:07 PM PDT 24
Peak memory 160584 kb
Host smart-c8fcd570-8cdb-4c4a-9faf-bd8466ad17d2
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3235126767 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.3235126767
Directory /workspace/46.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.2099539004
Short name T149
Test name
Test status
Simulation time 336427970000 ps
CPU time 832.64 seconds
Started Aug 09 04:32:06 PM PDT 24
Finished Aug 09 05:05:16 PM PDT 24
Peak memory 160664 kb
Host smart-98d4e005-908b-4274-8909-ac1c43ae5da2
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2099539004 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.2099539004
Directory /workspace/47.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.2820939562
Short name T146
Test name
Test status
Simulation time 336385290000 ps
CPU time 727.25 seconds
Started Aug 09 04:32:45 PM PDT 24
Finished Aug 09 05:01:59 PM PDT 24
Peak memory 160772 kb
Host smart-c954494c-3802-491a-bf18-360af0ba552d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2820939562 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.2820939562
Directory /workspace/48.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.2073116899
Short name T123
Test name
Test status
Simulation time 336388970000 ps
CPU time 740.34 seconds
Started Aug 09 04:32:36 PM PDT 24
Finished Aug 09 05:02:26 PM PDT 24
Peak memory 160660 kb
Host smart-dcbd092a-76b4-43e3-b679-1387772f5058
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2073116899 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.2073116899
Directory /workspace/49.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.2282631164
Short name T130
Test name
Test status
Simulation time 336464870000 ps
CPU time 798.53 seconds
Started Aug 09 04:20:51 PM PDT 24
Finished Aug 09 04:53:16 PM PDT 24
Peak memory 160628 kb
Host smart-f52ad779-abd2-4620-a12f-0577f953c85b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2282631164 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.2282631164
Directory /workspace/5.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.1923300950
Short name T148
Test name
Test status
Simulation time 336511490000 ps
CPU time 788.99 seconds
Started Aug 09 04:32:08 PM PDT 24
Finished Aug 09 05:03:50 PM PDT 24
Peak memory 160624 kb
Host smart-eccacfc4-be7f-4a8c-b9bf-64ab0cc646d6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1923300950 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.1923300950
Directory /workspace/6.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.4244090749
Short name T115
Test name
Test status
Simulation time 336802970000 ps
CPU time 736.78 seconds
Started Aug 09 04:25:48 PM PDT 24
Finished Aug 09 04:55:34 PM PDT 24
Peak memory 159172 kb
Host smart-8cc25dc7-d2de-42ed-899c-7ed2027c4c8f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4244090749 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.4244090749
Directory /workspace/7.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1245357879
Short name T119
Test name
Test status
Simulation time 336552610000 ps
CPU time 711.32 seconds
Started Aug 09 04:20:41 PM PDT 24
Finished Aug 09 04:49:35 PM PDT 24
Peak memory 160436 kb
Host smart-e2b55c6a-5f24-4777-bc28-f7e9aa236198
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1245357879 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.1245357879
Directory /workspace/8.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.3027680381
Short name T25
Test name
Test status
Simulation time 336572210000 ps
CPU time 793.55 seconds
Started Aug 09 04:20:49 PM PDT 24
Finished Aug 09 04:53:00 PM PDT 24
Peak memory 160552 kb
Host smart-02c87ebe-4243-4328-a664-8eaaeb485045
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3027680381 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.3027680381
Directory /workspace/9.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.860109515
Short name T15
Test name
Test status
Simulation time 336311790000 ps
CPU time 756.15 seconds
Started Aug 09 04:25:30 PM PDT 24
Finished Aug 09 04:57:21 PM PDT 24
Peak memory 159276 kb
Host smart-a52d62ba-5dcd-47d9-98bb-14b180ccb6c3
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=860109515 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.860109515
Directory /workspace/1.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.2255914706
Short name T110
Test name
Test status
Simulation time 336333370000 ps
CPU time 815.69 seconds
Started Aug 09 04:31:48 PM PDT 24
Finished Aug 09 05:05:41 PM PDT 24
Peak memory 160716 kb
Host smart-92e439d4-23bf-4729-ac24-70d2fc422d34
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2255914706 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.2255914706
Directory /workspace/10.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.3123533462
Short name T99
Test name
Test status
Simulation time 337088490000 ps
CPU time 825.29 seconds
Started Aug 09 04:31:58 PM PDT 24
Finished Aug 09 05:05:43 PM PDT 24
Peak memory 160660 kb
Host smart-611bb42f-4156-4ba8-b034-0a5bc374a33e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3123533462 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.3123533462
Directory /workspace/11.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.1672464183
Short name T85
Test name
Test status
Simulation time 336879890000 ps
CPU time 801.67 seconds
Started Aug 09 04:32:11 PM PDT 24
Finished Aug 09 05:05:10 PM PDT 24
Peak memory 160636 kb
Host smart-51a3f030-9a74-4f14-80e4-e0e210df18a1
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1672464183 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.1672464183
Directory /workspace/12.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.2175813865
Short name T76
Test name
Test status
Simulation time 336887710000 ps
CPU time 862.58 seconds
Started Aug 09 04:31:56 PM PDT 24
Finished Aug 09 05:08:21 PM PDT 24
Peak memory 160704 kb
Host smart-e204bb14-d9c5-4d26-94b7-c50798ddfa2d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2175813865 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.2175813865
Directory /workspace/13.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.3064024845
Short name T81
Test name
Test status
Simulation time 337092030000 ps
CPU time 908.7 seconds
Started Aug 09 04:31:58 PM PDT 24
Finished Aug 09 05:08:07 PM PDT 24
Peak memory 160592 kb
Host smart-ae0966e4-893d-43c6-a1d9-61bc87d8c4e5
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3064024845 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.3064024845
Directory /workspace/14.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.2277479452
Short name T16
Test name
Test status
Simulation time 336539070000 ps
CPU time 662.76 seconds
Started Aug 09 04:32:05 PM PDT 24
Finished Aug 09 04:59:10 PM PDT 24
Peak memory 160660 kb
Host smart-cc656fc7-75e6-47b7-95ca-4d12b8b6fb1c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2277479452 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.2277479452
Directory /workspace/15.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.932981811
Short name T75
Test name
Test status
Simulation time 337013930000 ps
CPU time 852.34 seconds
Started Aug 09 04:31:55 PM PDT 24
Finished Aug 09 05:07:23 PM PDT 24
Peak memory 160700 kb
Host smart-ea2492d8-a483-4eb7-9639-267c1eca07e6
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=932981811 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.932981811
Directory /workspace/16.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.1493658087
Short name T23
Test name
Test status
Simulation time 336635490000 ps
CPU time 500.5 seconds
Started Aug 09 04:32:21 PM PDT 24
Finished Aug 09 04:54:08 PM PDT 24
Peak memory 160676 kb
Host smart-79d9c5b7-08bc-4b8c-b86b-961c0e8c353c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1493658087 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.1493658087
Directory /workspace/17.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.3166450457
Short name T82
Test name
Test status
Simulation time 336596550000 ps
CPU time 796.81 seconds
Started Aug 09 04:32:09 PM PDT 24
Finished Aug 09 05:04:03 PM PDT 24
Peak memory 160716 kb
Host smart-a182529e-1e6d-4e2e-885d-6f462958e60f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3166450457 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.3166450457
Directory /workspace/18.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.3227882558
Short name T103
Test name
Test status
Simulation time 336703530000 ps
CPU time 709.59 seconds
Started Aug 09 04:32:01 PM PDT 24
Finished Aug 09 05:00:49 PM PDT 24
Peak memory 160776 kb
Host smart-813180ab-c5e3-405e-bf48-4d61ce5a7615
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3227882558 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.3227882558
Directory /workspace/19.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.885075697
Short name T101
Test name
Test status
Simulation time 336518110000 ps
CPU time 812.76 seconds
Started Aug 09 04:22:12 PM PDT 24
Finished Aug 09 04:55:17 PM PDT 24
Peak memory 160688 kb
Host smart-625c0cd0-b80a-429d-8c85-c70b23641019
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=885075697 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.885075697
Directory /workspace/2.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.1783305924
Short name T18
Test name
Test status
Simulation time 336487430000 ps
CPU time 835.44 seconds
Started Aug 09 04:31:56 PM PDT 24
Finished Aug 09 05:06:56 PM PDT 24
Peak memory 160656 kb
Host smart-cdab347e-59ea-466f-95d3-39db8dc6a96b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1783305924 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.1783305924
Directory /workspace/20.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.4270469029
Short name T88
Test name
Test status
Simulation time 336557370000 ps
CPU time 654.56 seconds
Started Aug 09 04:31:52 PM PDT 24
Finished Aug 09 04:58:40 PM PDT 24
Peak memory 160660 kb
Host smart-1de1b42c-3349-4284-9572-3e6ed439dbda
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4270469029 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.4270469029
Directory /workspace/21.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.85279520
Short name T109
Test name
Test status
Simulation time 337095550000 ps
CPU time 820.91 seconds
Started Aug 09 04:32:04 PM PDT 24
Finished Aug 09 05:04:54 PM PDT 24
Peak memory 160644 kb
Host smart-5632e6a7-b979-4a06-b2cd-8e236cbfd7f0
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=85279520 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.85279520
Directory /workspace/22.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.2433578714
Short name T90
Test name
Test status
Simulation time 336460430000 ps
CPU time 845.6 seconds
Started Aug 09 04:32:00 PM PDT 24
Finished Aug 09 05:06:58 PM PDT 24
Peak memory 160640 kb
Host smart-a93fdea3-e519-4352-a5e9-ebb464328341
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2433578714 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.2433578714
Directory /workspace/23.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.1160779092
Short name T95
Test name
Test status
Simulation time 337091150000 ps
CPU time 870.71 seconds
Started Aug 09 04:31:51 PM PDT 24
Finished Aug 09 05:08:36 PM PDT 24
Peak memory 160648 kb
Host smart-4e9cae1c-b7e0-4791-bc17-1d7927cf4106
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1160779092 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.1160779092
Directory /workspace/24.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.4039846819
Short name T83
Test name
Test status
Simulation time 336593590000 ps
CPU time 800.16 seconds
Started Aug 09 04:32:04 PM PDT 24
Finished Aug 09 05:04:36 PM PDT 24
Peak memory 160720 kb
Host smart-6dd244fa-a847-4393-a252-6b5a74cd1f2b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4039846819 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.4039846819
Directory /workspace/25.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.4214449099
Short name T17
Test name
Test status
Simulation time 336437470000 ps
CPU time 850.78 seconds
Started Aug 09 04:31:55 PM PDT 24
Finished Aug 09 05:06:55 PM PDT 24
Peak memory 160696 kb
Host smart-01ec9de9-9a07-4d75-9e9e-6f6f7ef0329d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4214449099 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.4214449099
Directory /workspace/26.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.1994705477
Short name T72
Test name
Test status
Simulation time 336526170000 ps
CPU time 808.76 seconds
Started Aug 09 04:32:08 PM PDT 24
Finished Aug 09 05:05:25 PM PDT 24
Peak memory 160632 kb
Host smart-0879e333-f612-407b-9303-3c87d47c8b11
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1994705477 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.1994705477
Directory /workspace/27.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.1584547178
Short name T14
Test name
Test status
Simulation time 336762170000 ps
CPU time 890.81 seconds
Started Aug 09 04:32:01 PM PDT 24
Finished Aug 09 05:07:22 PM PDT 24
Peak memory 160688 kb
Host smart-a6c04c0c-838d-4f8f-b53a-9ce9357592cb
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1584547178 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.1584547178
Directory /workspace/28.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.2455260296
Short name T96
Test name
Test status
Simulation time 336370270000 ps
CPU time 655.31 seconds
Started Aug 09 04:31:56 PM PDT 24
Finished Aug 09 04:59:21 PM PDT 24
Peak memory 160708 kb
Host smart-91432b9d-37bf-4471-b617-02f32f71b438
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2455260296 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.2455260296
Directory /workspace/29.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.878855081
Short name T91
Test name
Test status
Simulation time 336733310000 ps
CPU time 846.82 seconds
Started Aug 09 04:25:45 PM PDT 24
Finished Aug 09 05:00:31 PM PDT 24
Peak memory 160604 kb
Host smart-2e0feabd-5a5b-4120-b380-93004a2e6267
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=878855081 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.878855081
Directory /workspace/3.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.2116874767
Short name T73
Test name
Test status
Simulation time 336872050000 ps
CPU time 788.56 seconds
Started Aug 09 04:31:57 PM PDT 24
Finished Aug 09 05:03:53 PM PDT 24
Peak memory 160720 kb
Host smart-56cb2562-00a7-4558-9191-8c00020cb053
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2116874767 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.2116874767
Directory /workspace/30.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.4202235115
Short name T100
Test name
Test status
Simulation time 336610410000 ps
CPU time 878.04 seconds
Started Aug 09 04:31:50 PM PDT 24
Finished Aug 09 05:09:37 PM PDT 24
Peak memory 160652 kb
Host smart-7ede77bc-8804-4d3a-9cee-926ca17a44dc
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4202235115 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.4202235115
Directory /workspace/31.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.2247895807
Short name T102
Test name
Test status
Simulation time 336623070000 ps
CPU time 839.35 seconds
Started Aug 09 04:32:18 PM PDT 24
Finished Aug 09 05:07:08 PM PDT 24
Peak memory 160660 kb
Host smart-adca03b9-5e63-4dd1-816c-568d743c075a
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2247895807 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.2247895807
Directory /workspace/32.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.2773858028
Short name T107
Test name
Test status
Simulation time 336324570000 ps
CPU time 872.05 seconds
Started Aug 09 04:31:59 PM PDT 24
Finished Aug 09 05:08:51 PM PDT 24
Peak memory 160648 kb
Host smart-03ff5acb-4315-49e3-b401-72ac8c035851
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2773858028 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.2773858028
Directory /workspace/33.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.767668133
Short name T108
Test name
Test status
Simulation time 336417270000 ps
CPU time 935.73 seconds
Started Aug 09 04:32:25 PM PDT 24
Finished Aug 09 05:10:29 PM PDT 24
Peak memory 160676 kb
Host smart-e7748391-ed54-4452-b238-6960f0aedb18
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=767668133 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.767668133
Directory /workspace/34.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.3736672055
Short name T80
Test name
Test status
Simulation time 336929510000 ps
CPU time 633.41 seconds
Started Aug 09 04:32:06 PM PDT 24
Finished Aug 09 04:58:35 PM PDT 24
Peak memory 160640 kb
Host smart-d3b805f2-bb6e-41c4-966c-27e052a6c343
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3736672055 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.3736672055
Directory /workspace/35.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.244585820
Short name T106
Test name
Test status
Simulation time 336658530000 ps
CPU time 861.35 seconds
Started Aug 09 04:31:56 PM PDT 24
Finished Aug 09 05:07:06 PM PDT 24
Peak memory 160680 kb
Host smart-cffeb170-29f3-4951-bff6-808fe8659e11
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=244585820 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.244585820
Directory /workspace/36.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.3864005612
Short name T97
Test name
Test status
Simulation time 336937770000 ps
CPU time 940.77 seconds
Started Aug 09 04:32:08 PM PDT 24
Finished Aug 09 05:10:26 PM PDT 24
Peak memory 160684 kb
Host smart-8caa79d7-2c20-4389-9988-68db54d535f7
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3864005612 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.3864005612
Directory /workspace/37.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.993039848
Short name T79
Test name
Test status
Simulation time 337150310000 ps
CPU time 800.68 seconds
Started Aug 09 04:32:19 PM PDT 24
Finished Aug 09 05:05:18 PM PDT 24
Peak memory 160648 kb
Host smart-846d0ae1-16c1-4caa-8964-f93c8c81aa87
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=993039848 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.993039848
Directory /workspace/38.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.1663432650
Short name T21
Test name
Test status
Simulation time 336811410000 ps
CPU time 915.39 seconds
Started Aug 09 04:32:13 PM PDT 24
Finished Aug 09 05:11:10 PM PDT 24
Peak memory 160652 kb
Host smart-d249c2e1-febd-4273-b724-493ecfbcd668
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1663432650 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.1663432650
Directory /workspace/39.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.2759884003
Short name T94
Test name
Test status
Simulation time 336389790000 ps
CPU time 853.12 seconds
Started Aug 09 04:25:45 PM PDT 24
Finished Aug 09 05:01:03 PM PDT 24
Peak memory 160652 kb
Host smart-84f36475-4c5a-4df3-9cc8-153733f37aa9
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2759884003 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.2759884003
Directory /workspace/4.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.2797499128
Short name T104
Test name
Test status
Simulation time 336736230000 ps
CPU time 979.67 seconds
Started Aug 09 04:32:06 PM PDT 24
Finished Aug 09 05:11:59 PM PDT 24
Peak memory 160640 kb
Host smart-98967dad-5235-4bce-a137-e7a2b96e96e2
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2797499128 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.2797499128
Directory /workspace/40.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.1643352862
Short name T77
Test name
Test status
Simulation time 336542270000 ps
CPU time 796.26 seconds
Started Aug 09 04:32:02 PM PDT 24
Finished Aug 09 05:03:48 PM PDT 24
Peak memory 160632 kb
Host smart-b3b7bbbb-b393-49ad-9547-0e32714e68b4
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1643352862 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.1643352862
Directory /workspace/41.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.410609178
Short name T19
Test name
Test status
Simulation time 336656650000 ps
CPU time 790.49 seconds
Started Aug 09 04:32:11 PM PDT 24
Finished Aug 09 05:05:00 PM PDT 24
Peak memory 160708 kb
Host smart-3de497f1-7334-4fc1-a301-e39f346ca037
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=410609178 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.410609178
Directory /workspace/42.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.846460728
Short name T20
Test name
Test status
Simulation time 336727610000 ps
CPU time 802.15 seconds
Started Aug 09 04:32:15 PM PDT 24
Finished Aug 09 05:05:10 PM PDT 24
Peak memory 160628 kb
Host smart-9574fe4f-a38e-4d71-bdca-07922b8d0873
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=846460728 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.846460728
Directory /workspace/43.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.3844309336
Short name T84
Test name
Test status
Simulation time 336986950000 ps
CPU time 965.99 seconds
Started Aug 09 04:31:52 PM PDT 24
Finished Aug 09 05:10:56 PM PDT 24
Peak memory 160652 kb
Host smart-192ad854-e821-4208-af66-b36b338b321d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3844309336 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.3844309336
Directory /workspace/44.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.2782946994
Short name T86
Test name
Test status
Simulation time 336648670000 ps
CPU time 866.55 seconds
Started Aug 09 04:32:03 PM PDT 24
Finished Aug 09 05:06:16 PM PDT 24
Peak memory 160688 kb
Host smart-bd6a4ff9-1f40-4626-a466-7e17c7d4e947
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2782946994 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.2782946994
Directory /workspace/45.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.2601182611
Short name T87
Test name
Test status
Simulation time 336743790000 ps
CPU time 858.29 seconds
Started Aug 09 04:32:20 PM PDT 24
Finished Aug 09 05:08:32 PM PDT 24
Peak memory 160704 kb
Host smart-40fd0ec6-4d73-4715-a8ac-875af690852e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2601182611 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.2601182611
Directory /workspace/46.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.869153326
Short name T78
Test name
Test status
Simulation time 336858910000 ps
CPU time 808.91 seconds
Started Aug 09 04:32:26 PM PDT 24
Finished Aug 09 05:05:56 PM PDT 24
Peak memory 160708 kb
Host smart-683bad68-7e74-4b04-9c21-ea5fe19060b0
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=869153326 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.869153326
Directory /workspace/47.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.2012258726
Short name T89
Test name
Test status
Simulation time 336895250000 ps
CPU time 813.12 seconds
Started Aug 09 04:32:00 PM PDT 24
Finished Aug 09 05:04:27 PM PDT 24
Peak memory 160652 kb
Host smart-c1429a6c-f048-4290-8570-741cae876c86
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2012258726 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.2012258726
Directory /workspace/48.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.2156185283
Short name T98
Test name
Test status
Simulation time 336436510000 ps
CPU time 829.62 seconds
Started Aug 09 04:32:05 PM PDT 24
Finished Aug 09 05:06:55 PM PDT 24
Peak memory 160656 kb
Host smart-77387c57-ed06-4e4b-a150-a24bfbe0c75a
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2156185283 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.2156185283
Directory /workspace/49.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.1709802277
Short name T93
Test name
Test status
Simulation time 337034950000 ps
CPU time 833.64 seconds
Started Aug 09 04:23:04 PM PDT 24
Finished Aug 09 04:56:45 PM PDT 24
Peak memory 160688 kb
Host smart-6f63fe74-8db2-4b37-8646-b1411d43b72a
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1709802277 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.1709802277
Directory /workspace/5.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.2014313871
Short name T71
Test name
Test status
Simulation time 336461750000 ps
CPU time 561.72 seconds
Started Aug 09 04:21:12 PM PDT 24
Finished Aug 09 04:45:32 PM PDT 24
Peak memory 159752 kb
Host smart-6bd68375-5a79-4ccd-acdd-8345e55a7577
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2014313871 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.2014313871
Directory /workspace/6.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.3825679928
Short name T74
Test name
Test status
Simulation time 336353150000 ps
CPU time 827.54 seconds
Started Aug 09 04:25:34 PM PDT 24
Finished Aug 09 05:00:04 PM PDT 24
Peak memory 160696 kb
Host smart-c36c3165-9f7e-4a1e-8a34-91bfee821a70
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3825679928 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.3825679928
Directory /workspace/7.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.600921549
Short name T92
Test name
Test status
Simulation time 336906370000 ps
CPU time 741.82 seconds
Started Aug 09 04:25:33 PM PDT 24
Finished Aug 09 04:56:51 PM PDT 24
Peak memory 160488 kb
Host smart-c0602e31-106f-4cc7-af34-ee8b562bd364
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=600921549 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.600921549
Directory /workspace/8.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.2172900939
Short name T105
Test name
Test status
Simulation time 336368370000 ps
CPU time 744.73 seconds
Started Aug 09 04:25:30 PM PDT 24
Finished Aug 09 04:57:07 PM PDT 24
Peak memory 159300 kb
Host smart-86684038-6a41-43de-8ed4-313b302ade6e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2172900939 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.2172900939
Directory /workspace/9.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.3600195077
Short name T182
Test name
Test status
Simulation time 1509790000 ps
CPU time 3.41 seconds
Started Aug 09 04:32:49 PM PDT 24
Finished Aug 09 04:32:57 PM PDT 24
Peak memory 164752 kb
Host smart-b2c8c0ed-ce5b-401e-920b-e8f8e6b0eb4f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3600195077 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.3600195077
Directory /workspace/0.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.2789175989
Short name T160
Test name
Test status
Simulation time 1370790000 ps
CPU time 4.38 seconds
Started Aug 09 04:32:02 PM PDT 24
Finished Aug 09 04:32:11 PM PDT 24
Peak memory 164732 kb
Host smart-ac1a6f66-f8f7-4aba-9c98-a9f6e2e80d53
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2789175989 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.2789175989
Directory /workspace/1.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.3625020537
Short name T165
Test name
Test status
Simulation time 1474190000 ps
CPU time 4.12 seconds
Started Aug 09 04:32:31 PM PDT 24
Finished Aug 09 04:32:40 PM PDT 24
Peak memory 164760 kb
Host smart-6e99352b-0556-4e17-8fcc-d6b09ee55686
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3625020537 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.3625020537
Directory /workspace/10.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.1777404753
Short name T196
Test name
Test status
Simulation time 1496830000 ps
CPU time 4.02 seconds
Started Aug 09 04:32:03 PM PDT 24
Finished Aug 09 04:32:12 PM PDT 24
Peak memory 164752 kb
Host smart-0c285b87-39ea-4c9b-92b4-d22197ce9705
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1777404753 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.1777404753
Directory /workspace/11.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.2636081622
Short name T167
Test name
Test status
Simulation time 1573090000 ps
CPU time 4.63 seconds
Started Aug 09 04:33:14 PM PDT 24
Finished Aug 09 04:33:24 PM PDT 24
Peak memory 164688 kb
Host smart-f9c893a1-7dc8-4e48-af71-7e74bcf4217e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2636081622 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.2636081622
Directory /workspace/12.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.3093906296
Short name T173
Test name
Test status
Simulation time 1427530000 ps
CPU time 2.99 seconds
Started Aug 09 04:31:54 PM PDT 24
Finished Aug 09 04:32:06 PM PDT 24
Peak memory 164700 kb
Host smart-f5fc6ed0-fb04-41bd-83d1-3f2b524fe8ee
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3093906296 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.3093906296
Directory /workspace/13.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.220303534
Short name T181
Test name
Test status
Simulation time 1513290000 ps
CPU time 3.61 seconds
Started Aug 09 04:32:20 PM PDT 24
Finished Aug 09 04:32:29 PM PDT 24
Peak memory 164748 kb
Host smart-fa9c5b70-2881-401d-a282-f4d85f9c28b8
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=220303534 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.220303534
Directory /workspace/14.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.3916154271
Short name T163
Test name
Test status
Simulation time 1407370000 ps
CPU time 3.24 seconds
Started Aug 09 04:32:04 PM PDT 24
Finished Aug 09 04:32:12 PM PDT 24
Peak memory 164692 kb
Host smart-1d867537-7af0-4924-97d4-8837e56fe867
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3916154271 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.3916154271
Directory /workspace/15.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.1842433139
Short name T185
Test name
Test status
Simulation time 1530110000 ps
CPU time 4.28 seconds
Started Aug 09 04:32:10 PM PDT 24
Finished Aug 09 04:32:20 PM PDT 24
Peak memory 164684 kb
Host smart-eacd113a-59aa-4f19-86bf-cacfcc4b839e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1842433139 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.1842433139
Directory /workspace/16.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.2402995414
Short name T161
Test name
Test status
Simulation time 1492270000 ps
CPU time 3.89 seconds
Started Aug 09 04:32:35 PM PDT 24
Finished Aug 09 04:32:44 PM PDT 24
Peak memory 164716 kb
Host smart-30af48d1-b087-4f48-a717-c605381bb21a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2402995414 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.2402995414
Directory /workspace/17.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.2594257622
Short name T194
Test name
Test status
Simulation time 1472090000 ps
CPU time 3.76 seconds
Started Aug 09 04:32:10 PM PDT 24
Finished Aug 09 04:32:18 PM PDT 24
Peak memory 164728 kb
Host smart-5d0825ac-514e-45d5-8fc8-1f5dec2a6393
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2594257622 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.2594257622
Directory /workspace/18.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.2959469722
Short name T183
Test name
Test status
Simulation time 1238610000 ps
CPU time 3.53 seconds
Started Aug 09 04:32:17 PM PDT 24
Finished Aug 09 04:32:25 PM PDT 24
Peak memory 164792 kb
Host smart-c904b7a2-11fe-48d6-8646-52bef2c2b03a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2959469722 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.2959469722
Directory /workspace/19.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.1923483115
Short name T153
Test name
Test status
Simulation time 1417510000 ps
CPU time 3.87 seconds
Started Aug 09 04:32:50 PM PDT 24
Finished Aug 09 04:32:59 PM PDT 24
Peak memory 164708 kb
Host smart-15032b6e-c67a-487f-bcf3-12903a964cbf
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1923483115 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.1923483115
Directory /workspace/2.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.1599419061
Short name T199
Test name
Test status
Simulation time 1413570000 ps
CPU time 4.32 seconds
Started Aug 09 04:32:05 PM PDT 24
Finished Aug 09 04:32:15 PM PDT 24
Peak memory 164736 kb
Host smart-5abe113e-7678-4076-a068-9cda0a412b27
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1599419061 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.1599419061
Directory /workspace/20.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3335786698
Short name T175
Test name
Test status
Simulation time 1373070000 ps
CPU time 2.89 seconds
Started Aug 09 04:32:14 PM PDT 24
Finished Aug 09 04:32:20 PM PDT 24
Peak memory 164716 kb
Host smart-98f126d0-df58-4bc5-af59-340884b12933
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3335786698 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.3335786698
Directory /workspace/21.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.1994552921
Short name T154
Test name
Test status
Simulation time 1451430000 ps
CPU time 3.39 seconds
Started Aug 09 04:32:04 PM PDT 24
Finished Aug 09 04:32:12 PM PDT 24
Peak memory 164740 kb
Host smart-d6fc535f-a788-4664-9a0e-dd02b28990a3
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1994552921 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.1994552921
Directory /workspace/22.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.1930011807
Short name T186
Test name
Test status
Simulation time 1498290000 ps
CPU time 4.47 seconds
Started Aug 09 04:32:10 PM PDT 24
Finished Aug 09 04:32:20 PM PDT 24
Peak memory 164736 kb
Host smart-5a3b2dfd-89c7-446b-b458-f9fe3af5313a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1930011807 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.1930011807
Directory /workspace/23.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.1205418530
Short name T195
Test name
Test status
Simulation time 1414570000 ps
CPU time 4.06 seconds
Started Aug 09 04:32:01 PM PDT 24
Finished Aug 09 04:32:11 PM PDT 24
Peak memory 164736 kb
Host smart-81bcd03a-89d9-4152-a792-713c525c3348
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1205418530 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.1205418530
Directory /workspace/24.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.3186523634
Short name T197
Test name
Test status
Simulation time 1114190000 ps
CPU time 3.43 seconds
Started Aug 09 04:32:05 PM PDT 24
Finished Aug 09 04:32:13 PM PDT 24
Peak memory 164740 kb
Host smart-147c30a1-04ea-4a8e-9835-756afd5b47ee
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3186523634 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.3186523634
Directory /workspace/25.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.3058203642
Short name T157
Test name
Test status
Simulation time 1486790000 ps
CPU time 3.82 seconds
Started Aug 09 04:32:23 PM PDT 24
Finished Aug 09 04:32:31 PM PDT 24
Peak memory 164752 kb
Host smart-f01bcc70-e4f1-4d51-ad46-3b65c2ca5065
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3058203642 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.3058203642
Directory /workspace/26.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.3593500429
Short name T152
Test name
Test status
Simulation time 1323490000 ps
CPU time 2.81 seconds
Started Aug 09 04:32:01 PM PDT 24
Finished Aug 09 04:32:07 PM PDT 24
Peak memory 164796 kb
Host smart-8b0b2772-54d9-4bd9-84c2-42ad0ccf9c0c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3593500429 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.3593500429
Directory /workspace/27.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.1000491587
Short name T162
Test name
Test status
Simulation time 1462590000 ps
CPU time 3.06 seconds
Started Aug 09 04:32:18 PM PDT 24
Finished Aug 09 04:32:25 PM PDT 24
Peak memory 164728 kb
Host smart-b600a651-20b5-40f5-b8af-195a5eb65f39
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1000491587 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.1000491587
Directory /workspace/28.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.1747098841
Short name T159
Test name
Test status
Simulation time 1453150000 ps
CPU time 3.98 seconds
Started Aug 09 04:32:09 PM PDT 24
Finished Aug 09 04:32:18 PM PDT 24
Peak memory 164728 kb
Host smart-59cc2b96-20bc-4e60-b087-9c0c6c448a00
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1747098841 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.1747098841
Directory /workspace/29.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.1766637214
Short name T189
Test name
Test status
Simulation time 1426030000 ps
CPU time 3.07 seconds
Started Aug 09 04:32:34 PM PDT 24
Finished Aug 09 04:32:41 PM PDT 24
Peak memory 164728 kb
Host smart-cca76429-1770-4699-9be0-b38eadbb0ebe
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1766637214 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.1766637214
Directory /workspace/3.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.357412210
Short name T198
Test name
Test status
Simulation time 1405610000 ps
CPU time 3.47 seconds
Started Aug 09 04:32:18 PM PDT 24
Finished Aug 09 04:32:26 PM PDT 24
Peak memory 164712 kb
Host smart-317d1715-7b8e-4334-b773-fef2d82d4b37
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=357412210 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.357412210
Directory /workspace/30.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.2703916823
Short name T166
Test name
Test status
Simulation time 1638390000 ps
CPU time 3.76 seconds
Started Aug 09 04:32:12 PM PDT 24
Finished Aug 09 04:32:21 PM PDT 24
Peak memory 164676 kb
Host smart-b7dbf9b5-57b2-4431-b392-84e0f579a8c6
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2703916823 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.2703916823
Directory /workspace/31.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.3024680292
Short name T155
Test name
Test status
Simulation time 1549230000 ps
CPU time 3.44 seconds
Started Aug 09 04:32:25 PM PDT 24
Finished Aug 09 04:32:33 PM PDT 24
Peak memory 164716 kb
Host smart-c089b0a4-0735-42d5-920b-998bde28a993
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3024680292 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.3024680292
Directory /workspace/32.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.579845804
Short name T176
Test name
Test status
Simulation time 1457770000 ps
CPU time 3.37 seconds
Started Aug 09 04:32:04 PM PDT 24
Finished Aug 09 04:32:12 PM PDT 24
Peak memory 164696 kb
Host smart-f43029a7-97af-4350-aa73-11f152ac7250
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=579845804 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.579845804
Directory /workspace/33.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.94436618
Short name T187
Test name
Test status
Simulation time 1437690000 ps
CPU time 3.56 seconds
Started Aug 09 04:32:03 PM PDT 24
Finished Aug 09 04:32:11 PM PDT 24
Peak memory 164720 kb
Host smart-c938cc36-eb26-44ad-84e9-aaf2a35fdaba
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=94436618 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.94436618
Directory /workspace/34.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.4191042986
Short name T180
Test name
Test status
Simulation time 1539670000 ps
CPU time 3.19 seconds
Started Aug 09 04:32:02 PM PDT 24
Finished Aug 09 04:32:09 PM PDT 24
Peak memory 164696 kb
Host smart-a5f7b06e-5af2-437b-a650-5eb3241afa1f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4191042986 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.4191042986
Directory /workspace/35.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.1793602715
Short name T191
Test name
Test status
Simulation time 1503090000 ps
CPU time 4.33 seconds
Started Aug 09 04:32:24 PM PDT 24
Finished Aug 09 04:32:34 PM PDT 24
Peak memory 164712 kb
Host smart-f459df56-2616-4469-b8d8-ca9c6228e3cd
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1793602715 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.1793602715
Directory /workspace/36.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.2882740480
Short name T200
Test name
Test status
Simulation time 1446050000 ps
CPU time 4.31 seconds
Started Aug 09 04:32:00 PM PDT 24
Finished Aug 09 04:32:09 PM PDT 24
Peak memory 164756 kb
Host smart-4bcc1ec2-b16d-4809-a79a-ec21f6bac928
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2882740480 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.2882740480
Directory /workspace/37.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.2332130425
Short name T193
Test name
Test status
Simulation time 1458530000 ps
CPU time 3.62 seconds
Started Aug 09 04:32:26 PM PDT 24
Finished Aug 09 04:32:33 PM PDT 24
Peak memory 164752 kb
Host smart-ae7f8591-cbdd-44b6-bc40-cf108483bc30
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2332130425 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.2332130425
Directory /workspace/38.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.2079434201
Short name T172
Test name
Test status
Simulation time 1549170000 ps
CPU time 3.4 seconds
Started Aug 09 04:32:13 PM PDT 24
Finished Aug 09 04:32:21 PM PDT 24
Peak memory 164716 kb
Host smart-c80e1144-1bf5-4de5-95d4-165c236f4e06
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2079434201 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.2079434201
Directory /workspace/39.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.1367720152
Short name T171
Test name
Test status
Simulation time 1426170000 ps
CPU time 4.57 seconds
Started Aug 09 04:32:05 PM PDT 24
Finished Aug 09 04:32:15 PM PDT 24
Peak memory 164732 kb
Host smart-53802835-bbd5-4e13-94ce-36cb02bfbeca
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1367720152 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.1367720152
Directory /workspace/4.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.2674340613
Short name T190
Test name
Test status
Simulation time 1282890000 ps
CPU time 3.93 seconds
Started Aug 09 04:32:04 PM PDT 24
Finished Aug 09 04:32:13 PM PDT 24
Peak memory 164736 kb
Host smart-c3bf422d-8b5a-4865-b441-320d5398fe54
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2674340613 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.2674340613
Directory /workspace/40.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.2190284761
Short name T184
Test name
Test status
Simulation time 1620530000 ps
CPU time 3.74 seconds
Started Aug 09 04:32:08 PM PDT 24
Finished Aug 09 04:32:16 PM PDT 24
Peak memory 164728 kb
Host smart-f5c34d0f-f855-4f8d-848e-474fbae0a8d6
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2190284761 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.2190284761
Directory /workspace/41.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.921415671
Short name T170
Test name
Test status
Simulation time 1557610000 ps
CPU time 3.68 seconds
Started Aug 09 04:32:01 PM PDT 24
Finished Aug 09 04:32:09 PM PDT 24
Peak memory 164712 kb
Host smart-aa06281e-032d-49be-ab4c-0773c092aadc
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=921415671 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.921415671
Directory /workspace/42.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.3054448441
Short name T158
Test name
Test status
Simulation time 1445970000 ps
CPU time 3.01 seconds
Started Aug 09 04:32:08 PM PDT 24
Finished Aug 09 04:32:15 PM PDT 24
Peak memory 164724 kb
Host smart-7bab307d-7639-4622-969c-1b139a618b71
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3054448441 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.3054448441
Directory /workspace/43.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.282487212
Short name T151
Test name
Test status
Simulation time 1401270000 ps
CPU time 3.03 seconds
Started Aug 09 04:32:29 PM PDT 24
Finished Aug 09 04:32:46 PM PDT 24
Peak memory 164744 kb
Host smart-effe2921-ec2f-4ffa-bc71-4c0500e38504
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=282487212 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.282487212
Directory /workspace/44.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.1577185732
Short name T188
Test name
Test status
Simulation time 1365930000 ps
CPU time 3.86 seconds
Started Aug 09 04:32:11 PM PDT 24
Finished Aug 09 04:32:19 PM PDT 24
Peak memory 164736 kb
Host smart-76d4d9a4-da06-41b1-8b6f-75d3e3097b42
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1577185732 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.1577185732
Directory /workspace/45.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.58099894
Short name T179
Test name
Test status
Simulation time 1392970000 ps
CPU time 3.35 seconds
Started Aug 09 04:32:19 PM PDT 24
Finished Aug 09 04:32:26 PM PDT 24
Peak memory 164724 kb
Host smart-9a9b337a-6e50-405a-b512-83b6e40c9f68
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=58099894 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.58099894
Directory /workspace/46.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.3192963417
Short name T174
Test name
Test status
Simulation time 1286030000 ps
CPU time 3.36 seconds
Started Aug 09 04:32:10 PM PDT 24
Finished Aug 09 04:32:17 PM PDT 24
Peak memory 164792 kb
Host smart-bbcb5bcc-5d2a-49de-b95e-a975069b3c22
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3192963417 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.3192963417
Directory /workspace/47.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.4292248734
Short name T156
Test name
Test status
Simulation time 1436470000 ps
CPU time 3.89 seconds
Started Aug 09 04:32:04 PM PDT 24
Finished Aug 09 04:32:12 PM PDT 24
Peak memory 164688 kb
Host smart-8e5a84b4-3eaf-4375-9ac3-4b6de1326e92
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4292248734 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.4292248734
Directory /workspace/48.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.4169873358
Short name T168
Test name
Test status
Simulation time 1456250000 ps
CPU time 3.66 seconds
Started Aug 09 04:32:06 PM PDT 24
Finished Aug 09 04:32:14 PM PDT 24
Peak memory 164780 kb
Host smart-2b3873cd-689b-4f7b-850c-f22d61d4e6cd
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4169873358 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.4169873358
Directory /workspace/49.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.3483869091
Short name T177
Test name
Test status
Simulation time 1518650000 ps
CPU time 4.61 seconds
Started Aug 09 04:31:45 PM PDT 24
Finished Aug 09 04:31:55 PM PDT 24
Peak memory 164732 kb
Host smart-6fc5cb20-9a81-40bf-b162-1f29910b3ce1
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3483869091 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.3483869091
Directory /workspace/5.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.3050974352
Short name T169
Test name
Test status
Simulation time 1515790000 ps
CPU time 3.64 seconds
Started Aug 09 04:32:41 PM PDT 24
Finished Aug 09 04:32:50 PM PDT 24
Peak memory 164728 kb
Host smart-7b7057c7-245c-42e2-b0a2-d66d3c3247bd
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3050974352 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.3050974352
Directory /workspace/6.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.1916906280
Short name T178
Test name
Test status
Simulation time 1365730000 ps
CPU time 4.11 seconds
Started Aug 09 04:32:50 PM PDT 24
Finished Aug 09 04:32:59 PM PDT 24
Peak memory 164820 kb
Host smart-6fd558d0-e565-42db-92c1-84720789daad
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1916906280 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.1916906280
Directory /workspace/7.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.718410063
Short name T192
Test name
Test status
Simulation time 1595050000 ps
CPU time 4.73 seconds
Started Aug 09 04:32:26 PM PDT 24
Finished Aug 09 04:32:37 PM PDT 24
Peak memory 164680 kb
Host smart-836acbb0-3649-4c36-a504-3012c38d9d69
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=718410063 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.718410063
Directory /workspace/8.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.3851650229
Short name T164
Test name
Test status
Simulation time 1456190000 ps
CPU time 3.57 seconds
Started Aug 09 04:31:58 PM PDT 24
Finished Aug 09 04:32:06 PM PDT 24
Peak memory 164920 kb
Host smart-158df54b-0a5a-4445-b3ba-9837838fae4c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3851650229 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.3851650229
Directory /workspace/9.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.383371463
Short name T66
Test name
Test status
Simulation time 1388090000 ps
CPU time 4.9 seconds
Started Aug 09 04:19:50 PM PDT 24
Finished Aug 09 04:20:00 PM PDT 24
Peak memory 164928 kb
Host smart-99732200-dad6-41fc-9255-9d028bab294b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=383371463 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.383371463
Directory /workspace/1.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.4146629603
Short name T33
Test name
Test status
Simulation time 1537030000 ps
CPU time 4.99 seconds
Started Aug 09 04:19:56 PM PDT 24
Finished Aug 09 04:20:07 PM PDT 24
Peak memory 164980 kb
Host smart-4513c902-90d4-46b1-bbe5-6fe2cf6872da
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4146629603 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.4146629603
Directory /workspace/10.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.1193607161
Short name T60
Test name
Test status
Simulation time 992490000 ps
CPU time 3.38 seconds
Started Aug 09 04:19:49 PM PDT 24
Finished Aug 09 04:19:57 PM PDT 24
Peak memory 164868 kb
Host smart-340c020d-18db-4b77-a8dc-5d82a847dfcf
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1193607161 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.1193607161
Directory /workspace/11.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.1007516938
Short name T54
Test name
Test status
Simulation time 1640490000 ps
CPU time 6.11 seconds
Started Aug 09 04:19:59 PM PDT 24
Finished Aug 09 04:20:12 PM PDT 24
Peak memory 163104 kb
Host smart-2b55a96b-d2c1-40da-9886-bb17518fd9a9
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1007516938 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.1007516938
Directory /workspace/12.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.4271130941
Short name T56
Test name
Test status
Simulation time 1590490000 ps
CPU time 5.16 seconds
Started Aug 09 04:19:55 PM PDT 24
Finished Aug 09 04:20:07 PM PDT 24
Peak memory 164984 kb
Host smart-6c4a90e6-ae3d-4fa8-92a9-29417133cc13
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4271130941 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.4271130941
Directory /workspace/13.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.3943422641
Short name T34
Test name
Test status
Simulation time 1446690000 ps
CPU time 4.57 seconds
Started Aug 09 04:19:50 PM PDT 24
Finished Aug 09 04:20:00 PM PDT 24
Peak memory 164280 kb
Host smart-fac5121c-5625-4ecf-ab6e-18ca628bff9f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3943422641 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.3943422641
Directory /workspace/14.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.3199594819
Short name T2
Test name
Test status
Simulation time 1397130000 ps
CPU time 4.54 seconds
Started Aug 09 04:19:55 PM PDT 24
Finished Aug 09 04:20:05 PM PDT 24
Peak memory 164280 kb
Host smart-f917dba7-2f1f-41f6-b039-29963bff302d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3199594819 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.3199594819
Directory /workspace/15.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.1354139154
Short name T49
Test name
Test status
Simulation time 1569730000 ps
CPU time 5.43 seconds
Started Aug 09 04:19:55 PM PDT 24
Finished Aug 09 04:20:07 PM PDT 24
Peak memory 164980 kb
Host smart-05062fa1-54e8-4059-8503-f9ebafec2595
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1354139154 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.1354139154
Directory /workspace/16.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.3230116241
Short name T65
Test name
Test status
Simulation time 1419910000 ps
CPU time 4.45 seconds
Started Aug 09 04:19:50 PM PDT 24
Finished Aug 09 04:20:00 PM PDT 24
Peak memory 164280 kb
Host smart-5484c45d-fd0a-4a39-afe3-991aa2f77e4a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3230116241 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.3230116241
Directory /workspace/17.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.3120980428
Short name T12
Test name
Test status
Simulation time 1484270000 ps
CPU time 4.82 seconds
Started Aug 09 04:19:52 PM PDT 24
Finished Aug 09 04:20:03 PM PDT 24
Peak memory 164244 kb
Host smart-ef33a409-f03b-4bb7-85d1-5fc93346fa84
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3120980428 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.3120980428
Directory /workspace/18.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.153337691
Short name T53
Test name
Test status
Simulation time 1463830000 ps
CPU time 4.88 seconds
Started Aug 09 04:19:59 PM PDT 24
Finished Aug 09 04:20:10 PM PDT 24
Peak memory 163292 kb
Host smart-1c7105c2-7313-4ed1-9fb1-b06b18d46a06
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=153337691 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.153337691
Directory /workspace/19.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.3435457810
Short name T39
Test name
Test status
Simulation time 1517210000 ps
CPU time 5.59 seconds
Started Aug 09 04:19:41 PM PDT 24
Finished Aug 09 04:19:55 PM PDT 24
Peak memory 165044 kb
Host smart-5325ea06-1f7b-4885-9a8b-65abd46256f3
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3435457810 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.3435457810
Directory /workspace/2.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.3301462524
Short name T55
Test name
Test status
Simulation time 1581590000 ps
CPU time 5.61 seconds
Started Aug 09 04:19:59 PM PDT 24
Finished Aug 09 04:20:12 PM PDT 24
Peak memory 164200 kb
Host smart-9a1c7188-75e4-4119-a703-e336dbbac36b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3301462524 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.3301462524
Directory /workspace/20.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.4066203260
Short name T48
Test name
Test status
Simulation time 1597710000 ps
CPU time 4.83 seconds
Started Aug 09 04:19:52 PM PDT 24
Finished Aug 09 04:20:03 PM PDT 24
Peak memory 164244 kb
Host smart-6f7cdfec-1961-4289-b7d1-7fa395e3a42a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4066203260 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.4066203260
Directory /workspace/21.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.2945941301
Short name T38
Test name
Test status
Simulation time 1614870000 ps
CPU time 5.76 seconds
Started Aug 09 04:19:59 PM PDT 24
Finished Aug 09 04:20:12 PM PDT 24
Peak memory 164200 kb
Host smart-cbc26804-58ac-4db6-9607-e2e8ba69fe75
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2945941301 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.2945941301
Directory /workspace/22.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.494623565
Short name T43
Test name
Test status
Simulation time 1338990000 ps
CPU time 4.51 seconds
Started Aug 09 04:19:55 PM PDT 24
Finished Aug 09 04:20:05 PM PDT 24
Peak memory 165036 kb
Host smart-f44ac5e2-e382-4d31-8e24-2473ecf6a5a2
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=494623565 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.494623565
Directory /workspace/23.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.1361534853
Short name T31
Test name
Test status
Simulation time 1395830000 ps
CPU time 4.58 seconds
Started Aug 09 04:19:52 PM PDT 24
Finished Aug 09 04:20:02 PM PDT 24
Peak memory 165492 kb
Host smart-4cb894c3-408e-4c1b-be49-18d7fee4657a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1361534853 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.1361534853
Directory /workspace/24.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.3334392856
Short name T32
Test name
Test status
Simulation time 1539510000 ps
CPU time 5.27 seconds
Started Aug 09 04:19:55 PM PDT 24
Finished Aug 09 04:20:06 PM PDT 24
Peak memory 164980 kb
Host smart-578066fd-8c77-45e9-a491-835533b51b7a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3334392856 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.3334392856
Directory /workspace/25.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.4107992509
Short name T8
Test name
Test status
Simulation time 1565630000 ps
CPU time 5.2 seconds
Started Aug 09 04:19:55 PM PDT 24
Finished Aug 09 04:20:06 PM PDT 24
Peak memory 164980 kb
Host smart-24a22836-3d95-44d4-95df-c7e60ff3a8d0
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4107992509 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.4107992509
Directory /workspace/26.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.3378175692
Short name T51
Test name
Test status
Simulation time 1521090000 ps
CPU time 5.76 seconds
Started Aug 09 04:19:59 PM PDT 24
Finished Aug 09 04:20:11 PM PDT 24
Peak memory 162992 kb
Host smart-d08c4c12-5763-49d7-9e4b-1ab5a1c0536b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3378175692 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.3378175692
Directory /workspace/27.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.3582396126
Short name T44
Test name
Test status
Simulation time 1523790000 ps
CPU time 5.25 seconds
Started Aug 09 04:19:56 PM PDT 24
Finished Aug 09 04:20:07 PM PDT 24
Peak memory 164332 kb
Host smart-aed39788-4e43-4be8-b97f-20630323b437
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3582396126 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.3582396126
Directory /workspace/28.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.1086347113
Short name T68
Test name
Test status
Simulation time 1497110000 ps
CPU time 4.78 seconds
Started Aug 09 04:19:54 PM PDT 24
Finished Aug 09 04:20:05 PM PDT 24
Peak memory 162772 kb
Host smart-31fdbea1-5078-4446-b406-b4ffce85d8af
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1086347113 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.1086347113
Directory /workspace/29.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.342210203
Short name T59
Test name
Test status
Simulation time 1163530000 ps
CPU time 3.99 seconds
Started Aug 09 04:19:49 PM PDT 24
Finished Aug 09 04:19:58 PM PDT 24
Peak memory 164236 kb
Host smart-d5471fd5-ee47-4e85-8982-0dfd25d14daf
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=342210203 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.342210203
Directory /workspace/3.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.1542026294
Short name T61
Test name
Test status
Simulation time 1363870000 ps
CPU time 4.68 seconds
Started Aug 09 04:19:50 PM PDT 24
Finished Aug 09 04:20:00 PM PDT 24
Peak memory 164280 kb
Host smart-7ff8bc3e-88c1-47f1-89e7-d3bb17767030
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1542026294 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.1542026294
Directory /workspace/30.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.2260175908
Short name T58
Test name
Test status
Simulation time 1410350000 ps
CPU time 4.95 seconds
Started Aug 09 04:19:56 PM PDT 24
Finished Aug 09 04:20:07 PM PDT 24
Peak memory 164328 kb
Host smart-61ec80b8-9fc0-43cd-a746-66345f07fb65
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2260175908 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.2260175908
Directory /workspace/31.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.1449870770
Short name T67
Test name
Test status
Simulation time 1463590000 ps
CPU time 4.72 seconds
Started Aug 09 04:19:56 PM PDT 24
Finished Aug 09 04:20:07 PM PDT 24
Peak memory 164980 kb
Host smart-9050c314-4e61-42c0-a3c6-f62daeb4ae31
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1449870770 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.1449870770
Directory /workspace/32.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.3915380539
Short name T13
Test name
Test status
Simulation time 1539570000 ps
CPU time 5.58 seconds
Started Aug 09 04:19:59 PM PDT 24
Finished Aug 09 04:20:11 PM PDT 24
Peak memory 164104 kb
Host smart-70029423-aa8d-4925-ac31-4b476cce0a99
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3915380539 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.3915380539
Directory /workspace/33.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.1952702292
Short name T63
Test name
Test status
Simulation time 1427610000 ps
CPU time 4.21 seconds
Started Aug 09 04:19:53 PM PDT 24
Finished Aug 09 04:20:03 PM PDT 24
Peak memory 164300 kb
Host smart-d383ac41-86dc-4ddc-8931-70f433492f15
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1952702292 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.1952702292
Directory /workspace/34.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.2358851199
Short name T36
Test name
Test status
Simulation time 1387370000 ps
CPU time 2.81 seconds
Started Aug 09 04:19:48 PM PDT 24
Finished Aug 09 04:19:55 PM PDT 24
Peak memory 164292 kb
Host smart-39db0d69-0be8-4d66-ae58-cfddaca13dbf
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2358851199 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.2358851199
Directory /workspace/35.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.3261058364
Short name T64
Test name
Test status
Simulation time 1443870000 ps
CPU time 4.55 seconds
Started Aug 09 04:19:52 PM PDT 24
Finished Aug 09 04:20:02 PM PDT 24
Peak memory 165492 kb
Host smart-c8955367-c8bc-4a75-b054-ba4b1bca1ce9
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3261058364 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.3261058364
Directory /workspace/36.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.3717051743
Short name T7
Test name
Test status
Simulation time 1409510000 ps
CPU time 4.46 seconds
Started Aug 09 04:19:59 PM PDT 24
Finished Aug 09 04:20:09 PM PDT 24
Peak memory 164800 kb
Host smart-e0ea7d43-ff23-4cf6-836b-6addc80a480a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3717051743 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.3717051743
Directory /workspace/37.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.613413799
Short name T50
Test name
Test status
Simulation time 1285070000 ps
CPU time 4.3 seconds
Started Aug 09 04:19:55 PM PDT 24
Finished Aug 09 04:20:04 PM PDT 24
Peak memory 164920 kb
Host smart-67149546-e7b4-4651-8210-c4573089650d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=613413799 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.613413799
Directory /workspace/38.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.3059235446
Short name T62
Test name
Test status
Simulation time 1543010000 ps
CPU time 5.77 seconds
Started Aug 09 04:19:59 PM PDT 24
Finished Aug 09 04:20:11 PM PDT 24
Peak memory 164104 kb
Host smart-630268c7-6ec4-4681-bc50-ff689a1a138f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3059235446 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.3059235446
Directory /workspace/39.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.1613005002
Short name T37
Test name
Test status
Simulation time 1355010000 ps
CPU time 4.62 seconds
Started Aug 09 04:19:50 PM PDT 24
Finished Aug 09 04:20:00 PM PDT 24
Peak memory 164284 kb
Host smart-98f4e8bc-49bb-43f5-95ba-dddf11e9d782
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1613005002 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.1613005002
Directory /workspace/4.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.3709507880
Short name T70
Test name
Test status
Simulation time 1391870000 ps
CPU time 4.51 seconds
Started Aug 09 04:19:55 PM PDT 24
Finished Aug 09 04:20:05 PM PDT 24
Peak memory 164328 kb
Host smart-e65396c2-219f-415d-af45-c98c03656baa
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3709507880 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.3709507880
Directory /workspace/40.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.76746956
Short name T1
Test name
Test status
Simulation time 1501510000 ps
CPU time 4.81 seconds
Started Aug 09 04:19:55 PM PDT 24
Finished Aug 09 04:20:06 PM PDT 24
Peak memory 164988 kb
Host smart-37b820d3-b12a-4867-b0e5-250001c25556
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=76746956 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.76746956
Directory /workspace/41.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.2971801149
Short name T41
Test name
Test status
Simulation time 1529290000 ps
CPU time 4.78 seconds
Started Aug 09 04:19:51 PM PDT 24
Finished Aug 09 04:20:02 PM PDT 24
Peak memory 163024 kb
Host smart-e0b7d97a-68af-441c-a52e-fec5a0952030
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2971801149 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.2971801149
Directory /workspace/42.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.4145626515
Short name T57
Test name
Test status
Simulation time 1331890000 ps
CPU time 4.63 seconds
Started Aug 09 04:19:54 PM PDT 24
Finished Aug 09 04:20:05 PM PDT 24
Peak memory 162800 kb
Host smart-a6c739e9-6403-4e9e-a6be-96ca6336779c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4145626515 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.4145626515
Directory /workspace/43.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.1091998209
Short name T40
Test name
Test status
Simulation time 1439490000 ps
CPU time 5.04 seconds
Started Aug 09 04:19:54 PM PDT 24
Finished Aug 09 04:20:06 PM PDT 24
Peak memory 163324 kb
Host smart-097363bf-cc8b-421f-89cd-e79d02305034
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1091998209 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.1091998209
Directory /workspace/44.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.3758413042
Short name T3
Test name
Test status
Simulation time 1483090000 ps
CPU time 4.76 seconds
Started Aug 09 04:19:52 PM PDT 24
Finished Aug 09 04:20:03 PM PDT 24
Peak memory 164244 kb
Host smart-1fd20445-d5ca-4a9a-9040-abe2a6d76865
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3758413042 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.3758413042
Directory /workspace/45.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.1807869195
Short name T47
Test name
Test status
Simulation time 1529310000 ps
CPU time 5.35 seconds
Started Aug 09 04:19:55 PM PDT 24
Finished Aug 09 04:20:06 PM PDT 24
Peak memory 164256 kb
Host smart-5c1fca1f-093b-4f2e-921c-0efcea707725
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1807869195 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.1807869195
Directory /workspace/46.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.297859320
Short name T52
Test name
Test status
Simulation time 1508630000 ps
CPU time 5.32 seconds
Started Aug 09 04:19:59 PM PDT 24
Finished Aug 09 04:20:11 PM PDT 24
Peak memory 164200 kb
Host smart-485567fd-17d1-43e3-a00f-c671469e61bb
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=297859320 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.297859320
Directory /workspace/47.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.109427580
Short name T42
Test name
Test status
Simulation time 1530070000 ps
CPU time 4.89 seconds
Started Aug 09 04:19:49 PM PDT 24
Finished Aug 09 04:20:00 PM PDT 24
Peak memory 161892 kb
Host smart-2feb1ccf-55cb-45d9-b960-e4dfccb7ce1a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=109427580 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.109427580
Directory /workspace/48.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.2855174296
Short name T69
Test name
Test status
Simulation time 1490710000 ps
CPU time 4.73 seconds
Started Aug 09 04:19:51 PM PDT 24
Finished Aug 09 04:20:02 PM PDT 24
Peak memory 163052 kb
Host smart-aade40a7-12fd-415e-a5a4-29c08cc1d7b5
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2855174296 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.2855174296
Directory /workspace/49.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.1676313037
Short name T9
Test name
Test status
Simulation time 1551270000 ps
CPU time 5.08 seconds
Started Aug 09 04:19:49 PM PDT 24
Finished Aug 09 04:20:00 PM PDT 24
Peak memory 162064 kb
Host smart-53f1faf8-a26c-4858-a354-9554b384ec77
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1676313037 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.1676313037
Directory /workspace/5.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.4179058603
Short name T45
Test name
Test status
Simulation time 1544370000 ps
CPU time 5.14 seconds
Started Aug 09 04:19:49 PM PDT 24
Finished Aug 09 04:20:00 PM PDT 24
Peak memory 163236 kb
Host smart-a6617d32-4472-4ee7-ba07-e25969b7d6f2
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4179058603 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.4179058603
Directory /workspace/6.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.2102580386
Short name T35
Test name
Test status
Simulation time 1483790000 ps
CPU time 5.78 seconds
Started Aug 09 04:19:41 PM PDT 24
Finished Aug 09 04:19:55 PM PDT 24
Peak memory 165044 kb
Host smart-87d8bd09-ece3-4965-8b42-31936ef27be2
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2102580386 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.2102580386
Directory /workspace/7.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.4055066657
Short name T10
Test name
Test status
Simulation time 1274170000 ps
CPU time 4.3 seconds
Started Aug 09 04:19:49 PM PDT 24
Finished Aug 09 04:19:59 PM PDT 24
Peak memory 164984 kb
Host smart-f627b74f-ec2d-4b96-bbf7-cc8a018579bf
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4055066657 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.4055066657
Directory /workspace/8.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.2876660592
Short name T46
Test name
Test status
Simulation time 1453410000 ps
CPU time 5.05 seconds
Started Aug 09 04:19:49 PM PDT 24
Finished Aug 09 04:20:00 PM PDT 24
Peak memory 164984 kb
Host smart-159b330b-8b86-45c5-b6d1-624721be7662
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2876660592 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.2876660592
Directory /workspace/9.prim_lfsr_gal_smoke/latest
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