Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.31 100.00 96.55 100.00 100.00 95.00


Total tests in report: 200
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
87.31 87.31 100.00 100.00 96.55 96.55 100.00 100.00 100.00 100.00 40.00 40.00 /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.3470544264
95.31 8.00 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 80.00 40.00 /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.4183301287
98.31 3.00 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 95.00 15.00 /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.191320139

Tests that do not contribute to grading

Name
/workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.2364093031
/workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.2340804142
/workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.3354373715
/workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.2881066319
/workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.2463108423
/workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.3893898583
/workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.1620487069
/workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.2356696023
/workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.1699967888
/workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.3824678215
/workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.489861083
/workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.245552493
/workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.3915986681
/workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.166952753
/workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.4014187901
/workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.4140014690
/workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.1773703215
/workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.2979632809
/workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1036471233
/workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.1783105440
/workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.743547391
/workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.4144641996
/workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.371685589
/workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.4154014810
/workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.1428862156
/workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.2758816811
/workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.2963902328
/workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.891912550
/workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.3507766450
/workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.3319033873
/workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.2705716845
/workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.485975928
/workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.1414961421
/workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.2822987547
/workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.3844017988
/workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.4037327275
/workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.3504456623
/workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.260541996
/workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.172267651
/workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.1679756273
/workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.1950195419
/workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.143072819
/workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.2256805679
/workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.2544608123
/workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.1665828697
/workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.2379967859
/workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.2544950037
/workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.3131870
/workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.4077927489
/workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.3577702785
/workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.4272561957
/workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.1254878782
/workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.3246202293
/workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.223488940
/workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.303149912
/workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.3329845181
/workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.1878305112
/workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.1939579750
/workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.4144300856
/workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.3092080339
/workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.3852407493
/workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.2055245260
/workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3563427517
/workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.1273470336
/workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.619477517
/workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.4043982296
/workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.1895506905
/workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.629054894
/workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.2586243510
/workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.2799089527
/workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.1495727355
/workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.3041901244
/workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.2921704300
/workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.2064844785
/workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.1370221961
/workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.1931071158
/workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.3290835821
/workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.3166447063
/workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.2120691469
/workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.4211341936
/workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.819175211
/workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.140481259
/workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.2485432391
/workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.4040914607
/workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.3558554076
/workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.4073352240
/workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.3549533657
/workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.3537988557
/workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.1768668988
/workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.3099388013
/workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.1747724151
/workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.780740500
/workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.2476830096
/workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.1670717244
/workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.1997529469
/workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.2758303230
/workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.2609632244
/workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.2400404731
/workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.1552324015
/workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.3992632502
/workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.1045907242
/workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.4255009841
/workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.869351399
/workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.3050592448
/workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.1936256532
/workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.1264977783
/workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.1407594569
/workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.1765433848
/workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.2331731317
/workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.2843067072
/workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.3596665864
/workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.2045078278
/workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.4087366590
/workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.2173470193
/workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.1621334277
/workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.879599944
/workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.3305851277
/workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.3619602799
/workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.3627722093
/workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.365178863
/workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.3322738693
/workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.1116716849
/workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.2234016197
/workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.1755535375
/workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.1399443525
/workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.3655405613
/workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.3478896625
/workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.15261797
/workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.1828998578
/workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.3116803361
/workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.931400991
/workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.2060026596
/workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3415455140
/workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.19643223
/workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.1298640851
/workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.503705529
/workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1817266600
/workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.2421775657
/workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.3064609298
/workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.2859688977
/workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.1725695757
/workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.454853094
/workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.132389506
/workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.3383836117
/workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.188383068
/workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.2517298105
/workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.3432744871
/workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.1136118252
/workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.2326036856
/workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.581916784
/workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.2497285471
/workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.1110178051
/workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.3547016567
/workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.917106703
/workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.1857695257
/workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.2799659803
/workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.2640523676
/workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.2476925805
/workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.3051189580
/workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.387564048
/workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.1327233508
/workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.2276578083
/workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.4245278489
/workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.2980135016
/workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.4220954984
/workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.1883044393
/workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.2014812564
/workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.242932664
/workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.4269059305
/workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.1425994065
/workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.2665766212
/workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.425672502
/workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.4122117678
/workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.1108890395
/workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.4186711735
/workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.3982126115
/workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.4110931904
/workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.3589453502
/workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.1338710462
/workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.2111366660
/workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.1979978198
/workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.727620663
/workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.660366385
/workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.2368742493
/workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.4207706362
/workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.1074006592
/workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.637219357
/workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.1880857928
/workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.3459241321
/workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.115336623
/workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.2718872483
/workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.621169658
/workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.747249893
/workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.2225143278
/workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.4276939770
/workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.95901361
/workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.3554440036



Total test records in report: 200
tests.html | tests1.html | tests2.html | tests3.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.727620663 Aug 10 04:28:56 PM PDT 24 Aug 10 04:29:06 PM PDT 24 1543770000 ps
T2 /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.3470544264 Aug 10 04:28:55 PM PDT 24 Aug 10 04:29:04 PM PDT 24 1561150000 ps
T3 /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.1857695257 Aug 10 04:29:00 PM PDT 24 Aug 10 04:29:06 PM PDT 24 1419030000 ps
T7 /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.3554440036 Aug 10 04:29:04 PM PDT 24 Aug 10 04:29:10 PM PDT 24 1114530000 ps
T8 /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.4276939770 Aug 10 04:29:17 PM PDT 24 Aug 10 04:29:27 PM PDT 24 1361250000 ps
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T23 /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.2799089527 Aug 10 04:26:56 PM PDT 24 Aug 10 05:00:29 PM PDT 24 337077630000 ps
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T125 /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.3507766450 Aug 10 04:27:17 PM PDT 24 Aug 10 05:06:39 PM PDT 24 336590670000 ps
T126 /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.1414961421 Aug 10 04:27:21 PM PDT 24 Aug 10 05:04:56 PM PDT 24 336596170000 ps
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T128 /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1036471233 Aug 10 04:27:02 PM PDT 24 Aug 10 05:05:48 PM PDT 24 336630110000 ps
T129 /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.2463108423 Aug 10 04:27:04 PM PDT 24 Aug 10 04:59:19 PM PDT 24 336470850000 ps
T130 /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.4077927489 Aug 10 04:26:59 PM PDT 24 Aug 10 04:56:56 PM PDT 24 336763350000 ps
T131 /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.2356696023 Aug 10 04:27:21 PM PDT 24 Aug 10 04:58:24 PM PDT 24 336496230000 ps
T132 /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.3319033873 Aug 10 04:27:06 PM PDT 24 Aug 10 05:08:07 PM PDT 24 336377770000 ps
T133 /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.4140014690 Aug 10 04:26:59 PM PDT 24 Aug 10 05:03:45 PM PDT 24 336493710000 ps
T134 /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.4144641996 Aug 10 04:27:07 PM PDT 24 Aug 10 04:55:00 PM PDT 24 336611310000 ps
T135 /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.3893898583 Aug 10 04:26:56 PM PDT 24 Aug 10 05:00:19 PM PDT 24 336659930000 ps
T136 /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.166952753 Aug 10 04:27:16 PM PDT 24 Aug 10 04:54:40 PM PDT 24 336862510000 ps
T137 /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.2544950037 Aug 10 04:27:17 PM PDT 24 Aug 10 05:05:55 PM PDT 24 336970530000 ps
T138 /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.3824678215 Aug 10 04:27:06 PM PDT 24 Aug 10 04:57:53 PM PDT 24 336373210000 ps
T139 /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.743547391 Aug 10 04:27:22 PM PDT 24 Aug 10 04:56:03 PM PDT 24 336575790000 ps
T140 /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.2881066319 Aug 10 04:26:59 PM PDT 24 Aug 10 05:04:08 PM PDT 24 336549290000 ps
T141 /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.245552493 Aug 10 04:26:59 PM PDT 24 Aug 10 04:57:54 PM PDT 24 336341990000 ps
T142 /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.1783105440 Aug 10 04:27:02 PM PDT 24 Aug 10 05:06:43 PM PDT 24 336516970000 ps
T143 /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.2364093031 Aug 10 04:27:01 PM PDT 24 Aug 10 04:57:23 PM PDT 24 337064890000 ps
T144 /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.2340804142 Aug 10 04:26:59 PM PDT 24 Aug 10 04:53:07 PM PDT 24 336315690000 ps
T145 /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.4154014810 Aug 10 04:27:23 PM PDT 24 Aug 10 05:00:27 PM PDT 24 336703410000 ps
T146 /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.2822987547 Aug 10 04:26:57 PM PDT 24 Aug 10 04:54:59 PM PDT 24 336924770000 ps
T147 /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.1699967888 Aug 10 04:27:07 PM PDT 24 Aug 10 04:57:18 PM PDT 24 336656090000 ps
T148 /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.3354373715 Aug 10 04:27:04 PM PDT 24 Aug 10 04:57:31 PM PDT 24 337037830000 ps
T149 /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.3504456623 Aug 10 04:27:14 PM PDT 24 Aug 10 04:53:44 PM PDT 24 336862950000 ps
T150 /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.2979632809 Aug 10 04:27:08 PM PDT 24 Aug 10 05:04:19 PM PDT 24 336659930000 ps
T151 /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.1399443525 Aug 10 05:05:19 PM PDT 24 Aug 10 05:05:28 PM PDT 24 1370270000 ps
T152 /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.1298640851 Aug 10 05:05:17 PM PDT 24 Aug 10 05:05:26 PM PDT 24 1386630000 ps
T153 /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.3655405613 Aug 10 05:05:16 PM PDT 24 Aug 10 05:05:29 PM PDT 24 1462310000 ps
T154 /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.3478896625 Aug 10 05:05:14 PM PDT 24 Aug 10 05:05:24 PM PDT 24 1327790000 ps
T155 /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.2234016197 Aug 10 05:05:04 PM PDT 24 Aug 10 05:05:15 PM PDT 24 1490790000 ps
T156 /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.3619602799 Aug 10 05:05:01 PM PDT 24 Aug 10 05:05:07 PM PDT 24 985810000 ps
T157 /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.2173470193 Aug 10 05:05:04 PM PDT 24 Aug 10 05:05:13 PM PDT 24 1240950000 ps
T158 /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.3305851277 Aug 10 05:05:03 PM PDT 24 Aug 10 05:05:13 PM PDT 24 1520730000 ps
T159 /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.15261797 Aug 10 05:05:13 PM PDT 24 Aug 10 05:05:25 PM PDT 24 1455910000 ps
T160 /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.1116716849 Aug 10 05:05:02 PM PDT 24 Aug 10 05:05:09 PM PDT 24 1415710000 ps
T161 /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.2331731317 Aug 10 05:05:06 PM PDT 24 Aug 10 05:05:18 PM PDT 24 1382250000 ps
T162 /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.454853094 Aug 10 05:05:14 PM PDT 24 Aug 10 05:05:25 PM PDT 24 1522130000 ps
T163 /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.2859688977 Aug 10 05:05:15 PM PDT 24 Aug 10 05:05:25 PM PDT 24 1481810000 ps
T164 /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.365178863 Aug 10 05:05:03 PM PDT 24 Aug 10 05:05:16 PM PDT 24 1454810000 ps
T165 /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.3596665864 Aug 10 05:05:03 PM PDT 24 Aug 10 05:05:12 PM PDT 24 1480310000 ps
T166 /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.3322738693 Aug 10 05:05:02 PM PDT 24 Aug 10 05:05:13 PM PDT 24 1528030000 ps
T167 /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.2421775657 Aug 10 05:05:12 PM PDT 24 Aug 10 05:05:23 PM PDT 24 1545730000 ps
T168 /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.1407594569 Aug 10 05:05:03 PM PDT 24 Aug 10 05:05:14 PM PDT 24 1555370000 ps
T169 /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.879599944 Aug 10 05:05:01 PM PDT 24 Aug 10 05:05:13 PM PDT 24 1536850000 ps
T170 /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.1621334277 Aug 10 05:05:01 PM PDT 24 Aug 10 05:05:09 PM PDT 24 1111190000 ps
T171 /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.3050592448 Aug 10 05:05:03 PM PDT 24 Aug 10 05:05:16 PM PDT 24 1495010000 ps
T172 /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.931400991 Aug 10 05:05:12 PM PDT 24 Aug 10 05:05:21 PM PDT 24 1470370000 ps
T173 /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.3064609298 Aug 10 05:05:16 PM PDT 24 Aug 10 05:05:26 PM PDT 24 1450890000 ps
T174 /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.1552324015 Aug 10 05:05:03 PM PDT 24 Aug 10 05:05:12 PM PDT 24 1491890000 ps
T175 /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.2060026596 Aug 10 05:05:13 PM PDT 24 Aug 10 05:05:24 PM PDT 24 1321790000 ps
T176 /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.3627722093 Aug 10 05:05:03 PM PDT 24 Aug 10 05:05:13 PM PDT 24 1484030000 ps
T177 /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.2517298105 Aug 10 05:05:03 PM PDT 24 Aug 10 05:05:12 PM PDT 24 1531690000 ps
T178 /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.132389506 Aug 10 05:05:15 PM PDT 24 Aug 10 05:05:26 PM PDT 24 1536470000 ps
T179 /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3415455140 Aug 10 05:05:00 PM PDT 24 Aug 10 05:05:07 PM PDT 24 1461490000 ps
T180 /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.2843067072 Aug 10 05:05:06 PM PDT 24 Aug 10 05:05:20 PM PDT 24 1621150000 ps
T181 /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.188383068 Aug 10 05:05:03 PM PDT 24 Aug 10 05:05:16 PM PDT 24 1530010000 ps
T182 /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.19643223 Aug 10 05:05:21 PM PDT 24 Aug 10 05:05:30 PM PDT 24 1499870000 ps
T183 /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.4255009841 Aug 10 05:05:02 PM PDT 24 Aug 10 05:05:16 PM PDT 24 1538990000 ps
T184 /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.1045907242 Aug 10 05:05:01 PM PDT 24 Aug 10 05:05:11 PM PDT 24 1578690000 ps
T185 /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.3383836117 Aug 10 05:05:03 PM PDT 24 Aug 10 05:05:13 PM PDT 24 1333570000 ps
T186 /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.1264977783 Aug 10 05:05:03 PM PDT 24 Aug 10 05:05:14 PM PDT 24 1441970000 ps
T187 /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.1136118252 Aug 10 05:05:03 PM PDT 24 Aug 10 05:05:13 PM PDT 24 1309870000 ps
T188 /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1817266600 Aug 10 05:05:12 PM PDT 24 Aug 10 05:05:20 PM PDT 24 1379070000 ps
T189 /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.1755535375 Aug 10 05:05:15 PM PDT 24 Aug 10 05:05:25 PM PDT 24 1548490000 ps
T190 /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.3992632502 Aug 10 05:05:06 PM PDT 24 Aug 10 05:05:18 PM PDT 24 1411070000 ps
T191 /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.1936256532 Aug 10 05:05:02 PM PDT 24 Aug 10 05:05:15 PM PDT 24 1547350000 ps
T192 /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.2045078278 Aug 10 05:05:03 PM PDT 24 Aug 10 05:05:14 PM PDT 24 1541310000 ps
T193 /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.1828998578 Aug 10 05:05:10 PM PDT 24 Aug 10 05:05:18 PM PDT 24 1555170000 ps
T194 /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.3432744871 Aug 10 05:05:02 PM PDT 24 Aug 10 05:05:14 PM PDT 24 1453550000 ps
T195 /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.3116803361 Aug 10 05:05:16 PM PDT 24 Aug 10 05:05:30 PM PDT 24 1605330000 ps
T196 /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.1725695757 Aug 10 05:05:13 PM PDT 24 Aug 10 05:05:23 PM PDT 24 1485630000 ps
T197 /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.1765433848 Aug 10 05:05:02 PM PDT 24 Aug 10 05:05:09 PM PDT 24 1207510000 ps
T198 /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.4087366590 Aug 10 05:05:03 PM PDT 24 Aug 10 05:05:14 PM PDT 24 1476850000 ps
T199 /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.869351399 Aug 10 05:05:03 PM PDT 24 Aug 10 05:05:12 PM PDT 24 1358630000 ps
T200 /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.503705529 Aug 10 05:05:12 PM PDT 24 Aug 10 05:05:24 PM PDT 24 1563770000 ps

Test location /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.3470544264
Short name T2
Test name
Test status
Simulation time 1561150000 ps
CPU time 4.25 seconds
Started Aug 10 04:28:55 PM PDT 24
Finished Aug 10 04:29:04 PM PDT 24
Peak memory 164764 kb
Host smart-a1dbcc48-4065-4b47-8cc6-c4d3f1db41a1
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3470544264 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.3470544264
Directory /workspace/11.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.4183301287
Short name T15
Test name
Test status
Simulation time 336729870000 ps
CPU time 792.59 seconds
Started Aug 10 04:27:03 PM PDT 24
Finished Aug 10 04:59:22 PM PDT 24
Peak memory 160692 kb
Host smart-a228c95e-f5a9-4967-b80f-0e3c67e88667
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4183301287 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.4183301287
Directory /workspace/13.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.191320139
Short name T29
Test name
Test status
Simulation time 336737070000 ps
CPU time 736.87 seconds
Started Aug 10 04:27:18 PM PDT 24
Finished Aug 10 04:57:21 PM PDT 24
Peak memory 160672 kb
Host smart-435ad64a-9abe-430b-97e5-b722ee8eb2ee
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=191320139 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.191320139
Directory /workspace/17.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.2364093031
Short name T143
Test name
Test status
Simulation time 337064890000 ps
CPU time 749.32 seconds
Started Aug 10 04:27:01 PM PDT 24
Finished Aug 10 04:57:23 PM PDT 24
Peak memory 160636 kb
Host smart-977a6df7-4d5f-4545-8614-3882248d0b09
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2364093031 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.2364093031
Directory /workspace/0.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.2340804142
Short name T144
Test name
Test status
Simulation time 336315690000 ps
CPU time 628.52 seconds
Started Aug 10 04:26:59 PM PDT 24
Finished Aug 10 04:53:07 PM PDT 24
Peak memory 160688 kb
Host smart-0cab1730-e695-4f87-8ff5-114cdbbd998c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2340804142 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.2340804142
Directory /workspace/1.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.3354373715
Short name T148
Test name
Test status
Simulation time 337037830000 ps
CPU time 752.8 seconds
Started Aug 10 04:27:04 PM PDT 24
Finished Aug 10 04:57:31 PM PDT 24
Peak memory 160664 kb
Host smart-d1eff28e-71de-48df-a135-64d23ff18ae8
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3354373715 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.3354373715
Directory /workspace/10.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.2881066319
Short name T140
Test name
Test status
Simulation time 336549290000 ps
CPU time 923.5 seconds
Started Aug 10 04:26:59 PM PDT 24
Finished Aug 10 05:04:08 PM PDT 24
Peak memory 160668 kb
Host smart-ed1f8845-03ef-40e5-9d05-dc531c351537
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2881066319 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.2881066319
Directory /workspace/11.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.2463108423
Short name T129
Test name
Test status
Simulation time 336470850000 ps
CPU time 791.67 seconds
Started Aug 10 04:27:04 PM PDT 24
Finished Aug 10 04:59:19 PM PDT 24
Peak memory 160688 kb
Host smart-991607a3-b694-4d3e-b2ac-0b9df68e1f3a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2463108423 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.2463108423
Directory /workspace/12.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.3893898583
Short name T135
Test name
Test status
Simulation time 336659930000 ps
CPU time 816.1 seconds
Started Aug 10 04:26:56 PM PDT 24
Finished Aug 10 05:00:19 PM PDT 24
Peak memory 160788 kb
Host smart-b0ccd8b2-5b6d-4119-a888-a5bfe252fd19
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3893898583 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.3893898583
Directory /workspace/13.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.1620487069
Short name T111
Test name
Test status
Simulation time 336418510000 ps
CPU time 580.46 seconds
Started Aug 10 04:26:59 PM PDT 24
Finished Aug 10 04:51:22 PM PDT 24
Peak memory 160708 kb
Host smart-31ec3cff-f8ab-4623-8357-d90cb60fd139
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1620487069 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.1620487069
Directory /workspace/14.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.2356696023
Short name T131
Test name
Test status
Simulation time 336496230000 ps
CPU time 758.36 seconds
Started Aug 10 04:27:21 PM PDT 24
Finished Aug 10 04:58:24 PM PDT 24
Peak memory 160608 kb
Host smart-b83b1166-918b-48ee-ba7a-d6f3d6b1b61e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2356696023 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.2356696023
Directory /workspace/15.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.1699967888
Short name T147
Test name
Test status
Simulation time 336656090000 ps
CPU time 743.51 seconds
Started Aug 10 04:27:07 PM PDT 24
Finished Aug 10 04:57:18 PM PDT 24
Peak memory 160664 kb
Host smart-b8c25568-7399-46e8-8e44-82e0f3837e24
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1699967888 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.1699967888
Directory /workspace/16.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.3824678215
Short name T138
Test name
Test status
Simulation time 336373210000 ps
CPU time 750.8 seconds
Started Aug 10 04:27:06 PM PDT 24
Finished Aug 10 04:57:53 PM PDT 24
Peak memory 160688 kb
Host smart-c75d1905-f203-4d9b-a140-198ef60cebbe
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3824678215 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.3824678215
Directory /workspace/18.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.489861083
Short name T26
Test name
Test status
Simulation time 336660670000 ps
CPU time 722.32 seconds
Started Aug 10 04:27:24 PM PDT 24
Finished Aug 10 04:56:50 PM PDT 24
Peak memory 160660 kb
Host smart-212b9844-b662-42df-aca7-9e6434a68983
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=489861083 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.489861083
Directory /workspace/19.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.245552493
Short name T141
Test name
Test status
Simulation time 336341990000 ps
CPU time 764.57 seconds
Started Aug 10 04:26:59 PM PDT 24
Finished Aug 10 04:57:54 PM PDT 24
Peak memory 160656 kb
Host smart-484a13e5-ac3b-4234-bb43-77f0f4a22766
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=245552493 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.245552493
Directory /workspace/2.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.3915986681
Short name T116
Test name
Test status
Simulation time 336589890000 ps
CPU time 835.84 seconds
Started Aug 10 04:27:19 PM PDT 24
Finished Aug 10 05:00:46 PM PDT 24
Peak memory 160672 kb
Host smart-475e16e9-5312-49a3-88c9-9034e6150aba
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3915986681 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.3915986681
Directory /workspace/20.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.166952753
Short name T136
Test name
Test status
Simulation time 336862510000 ps
CPU time 670.84 seconds
Started Aug 10 04:27:16 PM PDT 24
Finished Aug 10 04:54:40 PM PDT 24
Peak memory 160672 kb
Host smart-b85f8c5e-ef78-40ac-b439-10033e13f65e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=166952753 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.166952753
Directory /workspace/21.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.4014187901
Short name T30
Test name
Test status
Simulation time 337026070000 ps
CPU time 786.43 seconds
Started Aug 10 04:27:04 PM PDT 24
Finished Aug 10 04:59:12 PM PDT 24
Peak memory 160688 kb
Host smart-d3efe6ba-0231-4df6-87c9-62d2ba5a8306
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4014187901 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.4014187901
Directory /workspace/22.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.4140014690
Short name T133
Test name
Test status
Simulation time 336493710000 ps
CPU time 914.06 seconds
Started Aug 10 04:26:59 PM PDT 24
Finished Aug 10 05:03:45 PM PDT 24
Peak memory 160668 kb
Host smart-01c87adf-e24a-4346-a551-9c5480033e52
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4140014690 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.4140014690
Directory /workspace/23.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.1773703215
Short name T5
Test name
Test status
Simulation time 336990230000 ps
CPU time 740.98 seconds
Started Aug 10 04:27:02 PM PDT 24
Finished Aug 10 04:57:07 PM PDT 24
Peak memory 160652 kb
Host smart-511637bf-7423-4671-bc96-ad08ef94428c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1773703215 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.1773703215
Directory /workspace/24.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.2979632809
Short name T150
Test name
Test status
Simulation time 336659930000 ps
CPU time 879.4 seconds
Started Aug 10 04:27:08 PM PDT 24
Finished Aug 10 05:04:19 PM PDT 24
Peak memory 160600 kb
Host smart-a8d791dd-9445-4543-aa79-55998bb79029
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2979632809 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.2979632809
Directory /workspace/25.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1036471233
Short name T128
Test name
Test status
Simulation time 336630110000 ps
CPU time 934.89 seconds
Started Aug 10 04:27:02 PM PDT 24
Finished Aug 10 05:05:48 PM PDT 24
Peak memory 160640 kb
Host smart-cb1b13ec-a567-4d15-9a54-4a40eda5917b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1036471233 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.1036471233
Directory /workspace/26.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.1783105440
Short name T142
Test name
Test status
Simulation time 336516970000 ps
CPU time 943.09 seconds
Started Aug 10 04:27:02 PM PDT 24
Finished Aug 10 05:06:43 PM PDT 24
Peak memory 160676 kb
Host smart-e2306b1a-7ea6-4d87-80b5-e4e2d9ca6be9
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1783105440 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.1783105440
Directory /workspace/27.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.743547391
Short name T139
Test name
Test status
Simulation time 336575790000 ps
CPU time 703.31 seconds
Started Aug 10 04:27:22 PM PDT 24
Finished Aug 10 04:56:03 PM PDT 24
Peak memory 160688 kb
Host smart-5c17a7e9-bffc-4fa9-87a4-1d75263d69ea
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=743547391 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.743547391
Directory /workspace/28.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.4144641996
Short name T134
Test name
Test status
Simulation time 336611310000 ps
CPU time 677.73 seconds
Started Aug 10 04:27:07 PM PDT 24
Finished Aug 10 04:55:00 PM PDT 24
Peak memory 160688 kb
Host smart-924d2216-f3f8-4b52-9253-263ef53ae174
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4144641996 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.4144641996
Directory /workspace/29.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.371685589
Short name T123
Test name
Test status
Simulation time 336762170000 ps
CPU time 952.49 seconds
Started Aug 10 04:27:17 PM PDT 24
Finished Aug 10 05:06:46 PM PDT 24
Peak memory 160672 kb
Host smart-a2224d4a-7de4-45d6-8083-f41b51c95aa9
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=371685589 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.371685589
Directory /workspace/3.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.4154014810
Short name T145
Test name
Test status
Simulation time 336703410000 ps
CPU time 808.24 seconds
Started Aug 10 04:27:23 PM PDT 24
Finished Aug 10 05:00:27 PM PDT 24
Peak memory 160860 kb
Host smart-c5854ed5-4089-439f-a2eb-44ed197eb79f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4154014810 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.4154014810
Directory /workspace/30.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.1428862156
Short name T4
Test name
Test status
Simulation time 337008250000 ps
CPU time 766.66 seconds
Started Aug 10 04:27:07 PM PDT 24
Finished Aug 10 04:58:43 PM PDT 24
Peak memory 160688 kb
Host smart-484d970d-2b8d-4b0d-a614-3d6c78fcaa25
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1428862156 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.1428862156
Directory /workspace/31.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.2758816811
Short name T117
Test name
Test status
Simulation time 336926430000 ps
CPU time 811.76 seconds
Started Aug 10 04:27:05 PM PDT 24
Finished Aug 10 04:59:52 PM PDT 24
Peak memory 160684 kb
Host smart-a0721f42-5111-4823-a483-3f4853610e60
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2758816811 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.2758816811
Directory /workspace/32.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.2963902328
Short name T27
Test name
Test status
Simulation time 336887330000 ps
CPU time 554.8 seconds
Started Aug 10 04:27:18 PM PDT 24
Finished Aug 10 04:50:52 PM PDT 24
Peak memory 160672 kb
Host smart-d3abff46-9105-4e3e-a5d4-c52a7b964dce
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2963902328 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.2963902328
Directory /workspace/33.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.891912550
Short name T120
Test name
Test status
Simulation time 337002690000 ps
CPU time 646.33 seconds
Started Aug 10 04:27:04 PM PDT 24
Finished Aug 10 04:53:24 PM PDT 24
Peak memory 160652 kb
Host smart-e4d59bd5-b654-4128-ab6e-40bcdd4f9df1
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=891912550 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.891912550
Directory /workspace/34.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.3507766450
Short name T125
Test name
Test status
Simulation time 336590670000 ps
CPU time 940.8 seconds
Started Aug 10 04:27:17 PM PDT 24
Finished Aug 10 05:06:39 PM PDT 24
Peak memory 160680 kb
Host smart-a90881fb-b3d2-447b-931a-2ae76d01a547
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3507766450 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.3507766450
Directory /workspace/35.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.3319033873
Short name T132
Test name
Test status
Simulation time 336377770000 ps
CPU time 976.16 seconds
Started Aug 10 04:27:06 PM PDT 24
Finished Aug 10 05:08:07 PM PDT 24
Peak memory 160660 kb
Host smart-3504e9c4-2ee7-4b16-b5c9-1a95671cd62e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3319033873 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.3319033873
Directory /workspace/36.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.2705716845
Short name T114
Test name
Test status
Simulation time 336984810000 ps
CPU time 585 seconds
Started Aug 10 04:26:59 PM PDT 24
Finished Aug 10 04:51:17 PM PDT 24
Peak memory 160708 kb
Host smart-675df662-7a40-4b7d-a8e1-4103d7102bf6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2705716845 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.2705716845
Directory /workspace/37.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.485975928
Short name T24
Test name
Test status
Simulation time 337075710000 ps
CPU time 979.2 seconds
Started Aug 10 04:27:12 PM PDT 24
Finished Aug 10 05:08:17 PM PDT 24
Peak memory 160664 kb
Host smart-59e13dda-20df-4a26-a2dd-8eea46b3682e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=485975928 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.485975928
Directory /workspace/38.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.1414961421
Short name T126
Test name
Test status
Simulation time 336596170000 ps
CPU time 901.6 seconds
Started Aug 10 04:27:21 PM PDT 24
Finished Aug 10 05:04:56 PM PDT 24
Peak memory 160684 kb
Host smart-53d1b335-bb25-41c9-b14d-a003531f00f3
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1414961421 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.1414961421
Directory /workspace/39.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.2822987547
Short name T146
Test name
Test status
Simulation time 336924770000 ps
CPU time 687.6 seconds
Started Aug 10 04:26:57 PM PDT 24
Finished Aug 10 04:54:59 PM PDT 24
Peak memory 160684 kb
Host smart-114ddb70-3955-4a9d-8e0a-010da3811174
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2822987547 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.2822987547
Directory /workspace/4.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.3844017988
Short name T28
Test name
Test status
Simulation time 336675350000 ps
CPU time 612.26 seconds
Started Aug 10 04:27:12 PM PDT 24
Finished Aug 10 04:52:57 PM PDT 24
Peak memory 160788 kb
Host smart-27730624-7887-4d00-a690-e73902de6d34
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3844017988 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.3844017988
Directory /workspace/40.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.4037327275
Short name T119
Test name
Test status
Simulation time 337086150000 ps
CPU time 790.95 seconds
Started Aug 10 04:27:04 PM PDT 24
Finished Aug 10 04:59:41 PM PDT 24
Peak memory 160672 kb
Host smart-eb5149c4-3b57-4667-8028-12c867e44991
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4037327275 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.4037327275
Directory /workspace/41.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.3504456623
Short name T149
Test name
Test status
Simulation time 336862950000 ps
CPU time 645.64 seconds
Started Aug 10 04:27:14 PM PDT 24
Finished Aug 10 04:53:44 PM PDT 24
Peak memory 160676 kb
Host smart-999599e9-4dc2-42b5-abc2-8630c072df1f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3504456623 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.3504456623
Directory /workspace/42.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.260541996
Short name T124
Test name
Test status
Simulation time 336838810000 ps
CPU time 988.83 seconds
Started Aug 10 04:27:08 PM PDT 24
Finished Aug 10 05:08:21 PM PDT 24
Peak memory 160664 kb
Host smart-e5ad8850-e962-4e0b-bb28-ac85c528dc8f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=260541996 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.260541996
Directory /workspace/43.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.172267651
Short name T115
Test name
Test status
Simulation time 337126730000 ps
CPU time 680.65 seconds
Started Aug 10 04:27:11 PM PDT 24
Finished Aug 10 04:55:10 PM PDT 24
Peak memory 160616 kb
Host smart-fa91e796-5fe9-4403-9e21-9f89e90d035b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=172267651 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.172267651
Directory /workspace/44.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.1679756273
Short name T25
Test name
Test status
Simulation time 336699030000 ps
CPU time 942.04 seconds
Started Aug 10 04:27:27 PM PDT 24
Finished Aug 10 05:06:53 PM PDT 24
Peak memory 160680 kb
Host smart-f63f9b7d-e50e-4714-8951-03c2a4a70a46
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1679756273 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.1679756273
Directory /workspace/45.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.1950195419
Short name T121
Test name
Test status
Simulation time 336304790000 ps
CPU time 831.56 seconds
Started Aug 10 04:27:16 PM PDT 24
Finished Aug 10 05:00:41 PM PDT 24
Peak memory 160860 kb
Host smart-dcdfad43-b0bd-4ca8-b0c1-3796d45e89e2
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1950195419 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.1950195419
Directory /workspace/46.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.143072819
Short name T6
Test name
Test status
Simulation time 336429370000 ps
CPU time 930.74 seconds
Started Aug 10 04:27:03 PM PDT 24
Finished Aug 10 05:05:38 PM PDT 24
Peak memory 160628 kb
Host smart-62e5fb32-d442-419b-a023-53aa6549dc99
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=143072819 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.143072819
Directory /workspace/47.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.2256805679
Short name T112
Test name
Test status
Simulation time 336936190000 ps
CPU time 766.01 seconds
Started Aug 10 04:27:24 PM PDT 24
Finished Aug 10 04:58:45 PM PDT 24
Peak memory 160676 kb
Host smart-484da045-f8f3-4eef-886e-2404d8ad6659
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2256805679 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.2256805679
Directory /workspace/48.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.2544608123
Short name T127
Test name
Test status
Simulation time 336566970000 ps
CPU time 803.3 seconds
Started Aug 10 04:26:59 PM PDT 24
Finished Aug 10 04:59:57 PM PDT 24
Peak memory 160672 kb
Host smart-955a3e67-7f29-473a-97d3-99f11f5df288
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2544608123 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.2544608123
Directory /workspace/49.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.1665828697
Short name T118
Test name
Test status
Simulation time 336568450000 ps
CPU time 913.85 seconds
Started Aug 10 04:27:07 PM PDT 24
Finished Aug 10 05:06:14 PM PDT 24
Peak memory 160656 kb
Host smart-4adf96c5-2074-4061-9e53-bf0f9c3bc645
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1665828697 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.1665828697
Directory /workspace/5.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.2379967859
Short name T113
Test name
Test status
Simulation time 336862490000 ps
CPU time 752.96 seconds
Started Aug 10 04:27:22 PM PDT 24
Finished Aug 10 04:58:11 PM PDT 24
Peak memory 160668 kb
Host smart-ed3ac1ba-4a7a-48e1-86c9-be8d9db574a6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2379967859 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.2379967859
Directory /workspace/6.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.2544950037
Short name T137
Test name
Test status
Simulation time 336970530000 ps
CPU time 931.66 seconds
Started Aug 10 04:27:17 PM PDT 24
Finished Aug 10 05:05:55 PM PDT 24
Peak memory 160732 kb
Host smart-1aca98f4-0300-478b-bd80-257ef57dfff2
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2544950037 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.2544950037
Directory /workspace/7.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.3131870
Short name T122
Test name
Test status
Simulation time 336729390000 ps
CPU time 794.1 seconds
Started Aug 10 04:26:58 PM PDT 24
Finished Aug 10 04:58:53 PM PDT 24
Peak memory 160664 kb
Host smart-6b6ce976-9c82-49d0-81d0-7fd8d794f1c7
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3131870 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.3131870
Directory /workspace/8.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.4077927489
Short name T130
Test name
Test status
Simulation time 336763350000 ps
CPU time 749.08 seconds
Started Aug 10 04:26:59 PM PDT 24
Finished Aug 10 04:56:56 PM PDT 24
Peak memory 160764 kb
Host smart-bfe42280-7217-4c94-bc4d-0956e07a5c3e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4077927489 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.4077927489
Directory /workspace/9.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.3577702785
Short name T73
Test name
Test status
Simulation time 336748790000 ps
CPU time 785.95 seconds
Started Aug 10 04:27:02 PM PDT 24
Finished Aug 10 05:00:31 PM PDT 24
Peak memory 160636 kb
Host smart-0fe436a6-8786-4e37-898c-7b9fa1acc7f7
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3577702785 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.3577702785
Directory /workspace/0.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.4272561957
Short name T72
Test name
Test status
Simulation time 336860710000 ps
CPU time 780.79 seconds
Started Aug 10 04:27:06 PM PDT 24
Finished Aug 10 04:59:07 PM PDT 24
Peak memory 160672 kb
Host smart-f05f87ae-ad79-47e8-a28a-40eae377c9c3
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4272561957 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.4272561957
Directory /workspace/1.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.1254878782
Short name T77
Test name
Test status
Simulation time 337020590000 ps
CPU time 692.27 seconds
Started Aug 10 04:26:57 PM PDT 24
Finished Aug 10 04:55:41 PM PDT 24
Peak memory 160696 kb
Host smart-c656b76a-1588-490f-a7cb-68620b41ed29
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1254878782 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.1254878782
Directory /workspace/10.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.3246202293
Short name T87
Test name
Test status
Simulation time 336694810000 ps
CPU time 759.22 seconds
Started Aug 10 04:27:21 PM PDT 24
Finished Aug 10 04:58:48 PM PDT 24
Peak memory 160668 kb
Host smart-665f8de3-d555-4835-85c7-5dfd86327a27
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3246202293 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.3246202293
Directory /workspace/11.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.223488940
Short name T81
Test name
Test status
Simulation time 336311270000 ps
CPU time 711.12 seconds
Started Aug 10 04:26:52 PM PDT 24
Finished Aug 10 04:56:03 PM PDT 24
Peak memory 160684 kb
Host smart-b9c11f1e-ba41-468b-a0d0-540e1691ca15
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=223488940 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.223488940
Directory /workspace/12.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.303149912
Short name T110
Test name
Test status
Simulation time 336793270000 ps
CPU time 967.16 seconds
Started Aug 10 04:26:59 PM PDT 24
Finished Aug 10 05:06:39 PM PDT 24
Peak memory 160676 kb
Host smart-211cdeda-71e4-446f-9b64-dc282aada721
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=303149912 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.303149912
Directory /workspace/14.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.3329845181
Short name T76
Test name
Test status
Simulation time 336584970000 ps
CPU time 899.17 seconds
Started Aug 10 04:27:01 PM PDT 24
Finished Aug 10 05:04:06 PM PDT 24
Peak memory 160744 kb
Host smart-542e92e8-a6d4-4af4-a838-cede27d0c47e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3329845181 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.3329845181
Directory /workspace/15.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.1878305112
Short name T74
Test name
Test status
Simulation time 337101670000 ps
CPU time 789.48 seconds
Started Aug 10 04:26:45 PM PDT 24
Finished Aug 10 04:58:59 PM PDT 24
Peak memory 160668 kb
Host smart-ac9c6fc3-82ac-46c5-bda1-2e8479085ba7
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1878305112 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.1878305112
Directory /workspace/16.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.1939579750
Short name T108
Test name
Test status
Simulation time 336727910000 ps
CPU time 950.69 seconds
Started Aug 10 04:27:00 PM PDT 24
Finished Aug 10 05:06:17 PM PDT 24
Peak memory 160688 kb
Host smart-412e74f7-140f-435a-b0f2-95c0713cf3df
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1939579750 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.1939579750
Directory /workspace/17.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.4144300856
Short name T105
Test name
Test status
Simulation time 336693910000 ps
CPU time 743.51 seconds
Started Aug 10 04:27:06 PM PDT 24
Finished Aug 10 04:57:15 PM PDT 24
Peak memory 160676 kb
Host smart-05851861-7ea0-4c30-9890-1b6121e8bec0
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4144300856 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.4144300856
Directory /workspace/18.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.3092080339
Short name T93
Test name
Test status
Simulation time 337127550000 ps
CPU time 686.29 seconds
Started Aug 10 04:26:58 PM PDT 24
Finished Aug 10 04:55:26 PM PDT 24
Peak memory 160696 kb
Host smart-3fbf6b85-1b24-40d5-9e23-8e5998917b90
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3092080339 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.3092080339
Directory /workspace/19.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.3852407493
Short name T104
Test name
Test status
Simulation time 336922350000 ps
CPU time 679.67 seconds
Started Aug 10 04:27:02 PM PDT 24
Finished Aug 10 04:55:12 PM PDT 24
Peak memory 160680 kb
Host smart-26b810a2-196c-40cc-9e5e-f8779e989f0b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3852407493 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.3852407493
Directory /workspace/2.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.2055245260
Short name T20
Test name
Test status
Simulation time 337147510000 ps
CPU time 757.81 seconds
Started Aug 10 04:26:50 PM PDT 24
Finished Aug 10 04:57:48 PM PDT 24
Peak memory 160612 kb
Host smart-7ddd7ef1-1415-493a-be13-38edc6a69b44
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2055245260 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.2055245260
Directory /workspace/20.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3563427517
Short name T16
Test name
Test status
Simulation time 336858290000 ps
CPU time 941.32 seconds
Started Aug 10 04:26:49 PM PDT 24
Finished Aug 10 05:05:36 PM PDT 24
Peak memory 160744 kb
Host smart-38a26f5b-d5e3-4c21-be94-dc9858404604
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3563427517 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.3563427517
Directory /workspace/21.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.1273470336
Short name T14
Test name
Test status
Simulation time 337028390000 ps
CPU time 729.61 seconds
Started Aug 10 04:27:00 PM PDT 24
Finished Aug 10 04:56:46 PM PDT 24
Peak memory 160776 kb
Host smart-6a26b490-f269-4699-9707-722ca99463af
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1273470336 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.1273470336
Directory /workspace/22.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.619477517
Short name T95
Test name
Test status
Simulation time 336970490000 ps
CPU time 957.85 seconds
Started Aug 10 04:27:00 PM PDT 24
Finished Aug 10 05:06:42 PM PDT 24
Peak memory 160676 kb
Host smart-d8b06f59-e2e2-4506-a305-70beca4fa2d7
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=619477517 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.619477517
Directory /workspace/23.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.4043982296
Short name T101
Test name
Test status
Simulation time 336662670000 ps
CPU time 864.55 seconds
Started Aug 10 04:26:50 PM PDT 24
Finished Aug 10 05:01:51 PM PDT 24
Peak memory 160644 kb
Host smart-ac3a1488-7e40-4d48-9337-01d354715610
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4043982296 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.4043982296
Directory /workspace/24.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.1895506905
Short name T85
Test name
Test status
Simulation time 336358530000 ps
CPU time 717.28 seconds
Started Aug 10 04:26:56 PM PDT 24
Finished Aug 10 04:56:46 PM PDT 24
Peak memory 160704 kb
Host smart-c9627071-5065-4bd6-bf12-4d047650cedc
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1895506905 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.1895506905
Directory /workspace/25.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.629054894
Short name T78
Test name
Test status
Simulation time 336587730000 ps
CPU time 1009.08 seconds
Started Aug 10 04:26:59 PM PDT 24
Finished Aug 10 05:08:50 PM PDT 24
Peak memory 160684 kb
Host smart-9c63a732-68f6-45cd-a850-0d92ba8c5782
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=629054894 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.629054894
Directory /workspace/26.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.2586243510
Short name T75
Test name
Test status
Simulation time 336959750000 ps
CPU time 1002.94 seconds
Started Aug 10 04:26:58 PM PDT 24
Finished Aug 10 05:08:44 PM PDT 24
Peak memory 160696 kb
Host smart-cf3f61de-fe33-4c57-97b0-372e154314a9
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2586243510 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.2586243510
Directory /workspace/27.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.2799089527
Short name T23
Test name
Test status
Simulation time 337077630000 ps
CPU time 815.63 seconds
Started Aug 10 04:26:56 PM PDT 24
Finished Aug 10 05:00:29 PM PDT 24
Peak memory 160792 kb
Host smart-f868a340-3abd-46b0-9def-01f70a081f30
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2799089527 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.2799089527
Directory /workspace/28.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.1495727355
Short name T92
Test name
Test status
Simulation time 336519050000 ps
CPU time 993.54 seconds
Started Aug 10 04:26:58 PM PDT 24
Finished Aug 10 05:08:09 PM PDT 24
Peak memory 160696 kb
Host smart-e08fa367-e0ca-47e5-a2bb-c690b81b6a83
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1495727355 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.1495727355
Directory /workspace/29.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.3041901244
Short name T103
Test name
Test status
Simulation time 337009190000 ps
CPU time 687.43 seconds
Started Aug 10 04:27:07 PM PDT 24
Finished Aug 10 04:55:22 PM PDT 24
Peak memory 160684 kb
Host smart-9cb6f92f-a6ff-406f-9c7d-37c15df0317d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3041901244 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.3041901244
Directory /workspace/3.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.2921704300
Short name T88
Test name
Test status
Simulation time 336836990000 ps
CPU time 981.54 seconds
Started Aug 10 04:27:00 PM PDT 24
Finished Aug 10 05:07:56 PM PDT 24
Peak memory 160696 kb
Host smart-8914c7bb-1c55-438e-a505-c24ce120aaf1
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2921704300 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.2921704300
Directory /workspace/30.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.2064844785
Short name T22
Test name
Test status
Simulation time 336984130000 ps
CPU time 749.23 seconds
Started Aug 10 04:26:52 PM PDT 24
Finished Aug 10 04:57:40 PM PDT 24
Peak memory 160656 kb
Host smart-91f9ad54-cb49-4509-ad37-757eb3063ff8
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2064844785 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.2064844785
Directory /workspace/31.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.1370221961
Short name T102
Test name
Test status
Simulation time 336601650000 ps
CPU time 789.08 seconds
Started Aug 10 04:27:05 PM PDT 24
Finished Aug 10 04:59:18 PM PDT 24
Peak memory 160692 kb
Host smart-e25cf646-884b-4821-8bda-be0cff180f58
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1370221961 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.1370221961
Directory /workspace/32.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.1931071158
Short name T91
Test name
Test status
Simulation time 336617710000 ps
CPU time 740.97 seconds
Started Aug 10 04:27:00 PM PDT 24
Finished Aug 10 04:57:25 PM PDT 24
Peak memory 160688 kb
Host smart-5071089b-ba83-4e1f-90e0-c3cb8ded3cf0
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1931071158 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.1931071158
Directory /workspace/33.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.3290835821
Short name T71
Test name
Test status
Simulation time 336824970000 ps
CPU time 889.09 seconds
Started Aug 10 04:27:02 PM PDT 24
Finished Aug 10 05:04:18 PM PDT 24
Peak memory 160604 kb
Host smart-0c0095cf-69ae-4718-b033-6f2788b0cddd
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3290835821 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.3290835821
Directory /workspace/34.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.3166447063
Short name T21
Test name
Test status
Simulation time 336885730000 ps
CPU time 800.75 seconds
Started Aug 10 04:26:47 PM PDT 24
Finished Aug 10 04:59:20 PM PDT 24
Peak memory 160668 kb
Host smart-87931f84-2938-42b2-87da-64b49145140f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3166447063 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.3166447063
Directory /workspace/35.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.2120691469
Short name T97
Test name
Test status
Simulation time 336393030000 ps
CPU time 850.07 seconds
Started Aug 10 04:26:58 PM PDT 24
Finished Aug 10 05:01:51 PM PDT 24
Peak memory 160668 kb
Host smart-8db60127-2267-46d9-bd23-cc554fe45169
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2120691469 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.2120691469
Directory /workspace/36.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.4211341936
Short name T83
Test name
Test status
Simulation time 336392190000 ps
CPU time 794.35 seconds
Started Aug 10 04:26:53 PM PDT 24
Finished Aug 10 05:00:03 PM PDT 24
Peak memory 160668 kb
Host smart-ad9f00de-34fe-4fee-9041-ca930a2f53fb
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4211341936 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.4211341936
Directory /workspace/37.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.819175211
Short name T84
Test name
Test status
Simulation time 336631110000 ps
CPU time 828.72 seconds
Started Aug 10 04:26:55 PM PDT 24
Finished Aug 10 05:01:19 PM PDT 24
Peak memory 160656 kb
Host smart-9622a701-b4e5-4583-a687-807434c0c0c4
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=819175211 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.819175211
Directory /workspace/38.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.140481259
Short name T80
Test name
Test status
Simulation time 336539990000 ps
CPU time 650.82 seconds
Started Aug 10 04:26:51 PM PDT 24
Finished Aug 10 04:53:54 PM PDT 24
Peak memory 160708 kb
Host smart-f8265c2f-ca2e-4969-917b-0227e72cefb7
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=140481259 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.140481259
Directory /workspace/39.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.2485432391
Short name T90
Test name
Test status
Simulation time 336612210000 ps
CPU time 995.77 seconds
Started Aug 10 04:26:55 PM PDT 24
Finished Aug 10 05:08:12 PM PDT 24
Peak memory 160660 kb
Host smart-fb401385-b104-4ae3-b9c9-9507b2f0a857
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2485432391 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.2485432391
Directory /workspace/4.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.4040914607
Short name T94
Test name
Test status
Simulation time 337089230000 ps
CPU time 886.14 seconds
Started Aug 10 04:27:03 PM PDT 24
Finished Aug 10 05:04:16 PM PDT 24
Peak memory 160600 kb
Host smart-df824bdd-1ec4-4b24-803b-8691821af79a
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4040914607 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.4040914607
Directory /workspace/40.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.3558554076
Short name T100
Test name
Test status
Simulation time 336363830000 ps
CPU time 854.75 seconds
Started Aug 10 04:26:59 PM PDT 24
Finished Aug 10 05:01:59 PM PDT 24
Peak memory 160668 kb
Host smart-003d87d9-6cbc-480e-85de-75e60bdff903
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3558554076 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.3558554076
Directory /workspace/41.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.4073352240
Short name T82
Test name
Test status
Simulation time 336322070000 ps
CPU time 807.7 seconds
Started Aug 10 04:26:58 PM PDT 24
Finished Aug 10 05:00:26 PM PDT 24
Peak memory 160668 kb
Host smart-3b3f0178-ecd9-4988-b0af-d504c22cba90
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4073352240 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.4073352240
Directory /workspace/42.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.3549533657
Short name T99
Test name
Test status
Simulation time 336793330000 ps
CPU time 880.81 seconds
Started Aug 10 04:27:05 PM PDT 24
Finished Aug 10 05:04:10 PM PDT 24
Peak memory 160604 kb
Host smart-c5b872f7-1a99-412e-a663-503b147a8d8d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3549533657 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.3549533657
Directory /workspace/43.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.3537988557
Short name T109
Test name
Test status
Simulation time 336380830000 ps
CPU time 808.93 seconds
Started Aug 10 04:26:58 PM PDT 24
Finished Aug 10 05:00:02 PM PDT 24
Peak memory 160704 kb
Host smart-7364f1a2-9ddd-4eb0-811e-860229a926f5
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3537988557 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.3537988557
Directory /workspace/44.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.1768668988
Short name T17
Test name
Test status
Simulation time 336582470000 ps
CPU time 857.57 seconds
Started Aug 10 04:26:57 PM PDT 24
Finished Aug 10 05:01:36 PM PDT 24
Peak memory 160704 kb
Host smart-072fb616-db3a-4071-bc7d-8d36438db3f0
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1768668988 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.1768668988
Directory /workspace/45.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.3099388013
Short name T98
Test name
Test status
Simulation time 336534970000 ps
CPU time 731.03 seconds
Started Aug 10 04:27:06 PM PDT 24
Finished Aug 10 04:57:12 PM PDT 24
Peak memory 160648 kb
Host smart-8dbc7dc0-ebc8-42ae-8822-29270d4867ac
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3099388013 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.3099388013
Directory /workspace/46.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.1747724151
Short name T89
Test name
Test status
Simulation time 336623250000 ps
CPU time 674.19 seconds
Started Aug 10 04:27:01 PM PDT 24
Finished Aug 10 04:54:35 PM PDT 24
Peak memory 160676 kb
Host smart-ea11a686-bbf6-4847-bba5-628528d780c1
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1747724151 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.1747724151
Directory /workspace/47.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.780740500
Short name T79
Test name
Test status
Simulation time 336392370000 ps
CPU time 951.3 seconds
Started Aug 10 04:26:59 PM PDT 24
Finished Aug 10 05:06:39 PM PDT 24
Peak memory 160680 kb
Host smart-2de90b90-2b90-43d9-b367-7cc68ddb27bb
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=780740500 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.780740500
Directory /workspace/48.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.2476830096
Short name T19
Test name
Test status
Simulation time 336697890000 ps
CPU time 875.57 seconds
Started Aug 10 04:27:16 PM PDT 24
Finished Aug 10 05:04:16 PM PDT 24
Peak memory 160604 kb
Host smart-f37c6950-2c7f-415e-af4c-a5be9a6ad2ee
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2476830096 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.2476830096
Directory /workspace/49.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.1670717244
Short name T107
Test name
Test status
Simulation time 336727470000 ps
CPU time 732.25 seconds
Started Aug 10 04:26:54 PM PDT 24
Finished Aug 10 04:56:47 PM PDT 24
Peak memory 160652 kb
Host smart-3d4c5318-a592-4567-b0b0-587bb5a7ff63
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1670717244 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.1670717244
Directory /workspace/5.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.1997529469
Short name T86
Test name
Test status
Simulation time 336350450000 ps
CPU time 916.78 seconds
Started Aug 10 04:27:00 PM PDT 24
Finished Aug 10 05:05:07 PM PDT 24
Peak memory 160636 kb
Host smart-47d2484c-5079-444a-879d-eab3eb125c5f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1997529469 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.1997529469
Directory /workspace/6.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.2758303230
Short name T96
Test name
Test status
Simulation time 337093070000 ps
CPU time 800.48 seconds
Started Aug 10 04:26:54 PM PDT 24
Finished Aug 10 04:59:38 PM PDT 24
Peak memory 160664 kb
Host smart-58b68e92-e0aa-49d8-8e7b-0d3ccb027a0f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2758303230 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.2758303230
Directory /workspace/7.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.2609632244
Short name T106
Test name
Test status
Simulation time 336812010000 ps
CPU time 756.48 seconds
Started Aug 10 04:26:58 PM PDT 24
Finished Aug 10 04:57:26 PM PDT 24
Peak memory 160680 kb
Host smart-1267f063-e107-444c-a94f-e494832c62ff
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2609632244 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.2609632244
Directory /workspace/8.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.2400404731
Short name T18
Test name
Test status
Simulation time 336653950000 ps
CPU time 804.79 seconds
Started Aug 10 04:26:59 PM PDT 24
Finished Aug 10 04:59:56 PM PDT 24
Peak memory 160668 kb
Host smart-a2d7d0ea-ea8f-4bd1-a73f-aff2b8427614
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2400404731 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.2400404731
Directory /workspace/9.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.1552324015
Short name T174
Test name
Test status
Simulation time 1491890000 ps
CPU time 4 seconds
Started Aug 10 05:05:03 PM PDT 24
Finished Aug 10 05:05:12 PM PDT 24
Peak memory 164856 kb
Host smart-8968a356-b5b5-44ed-83cd-062dbd766f0b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1552324015 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.1552324015
Directory /workspace/0.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.3992632502
Short name T190
Test name
Test status
Simulation time 1411070000 ps
CPU time 5.39 seconds
Started Aug 10 05:05:06 PM PDT 24
Finished Aug 10 05:05:18 PM PDT 24
Peak memory 164796 kb
Host smart-9c3e4bff-8eef-436d-9366-f4340a540437
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3992632502 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.3992632502
Directory /workspace/1.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.1045907242
Short name T184
Test name
Test status
Simulation time 1578690000 ps
CPU time 4.74 seconds
Started Aug 10 05:05:01 PM PDT 24
Finished Aug 10 05:05:11 PM PDT 24
Peak memory 164844 kb
Host smart-a753a19d-4e54-4674-8362-67f7ae5813f8
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1045907242 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.1045907242
Directory /workspace/10.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.4255009841
Short name T183
Test name
Test status
Simulation time 1538990000 ps
CPU time 6.79 seconds
Started Aug 10 05:05:02 PM PDT 24
Finished Aug 10 05:05:16 PM PDT 24
Peak memory 164796 kb
Host smart-ff7e1453-1e44-406d-b118-303e6344820a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4255009841 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.4255009841
Directory /workspace/11.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.869351399
Short name T199
Test name
Test status
Simulation time 1358630000 ps
CPU time 3.68 seconds
Started Aug 10 05:05:03 PM PDT 24
Finished Aug 10 05:05:12 PM PDT 24
Peak memory 164872 kb
Host smart-caf60f5d-af35-4736-937e-45b46bbebe47
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=869351399 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.869351399
Directory /workspace/12.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.3050592448
Short name T171
Test name
Test status
Simulation time 1495010000 ps
CPU time 6.33 seconds
Started Aug 10 05:05:03 PM PDT 24
Finished Aug 10 05:05:16 PM PDT 24
Peak memory 164792 kb
Host smart-8fe3ee05-eafd-4efd-8e47-a3ff4fbd0d92
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3050592448 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.3050592448
Directory /workspace/13.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.1936256532
Short name T191
Test name
Test status
Simulation time 1547350000 ps
CPU time 6.07 seconds
Started Aug 10 05:05:02 PM PDT 24
Finished Aug 10 05:05:15 PM PDT 24
Peak memory 164908 kb
Host smart-74bb3d68-08dd-4265-9497-c3d8298d87f9
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1936256532 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.1936256532
Directory /workspace/14.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.1264977783
Short name T186
Test name
Test status
Simulation time 1441970000 ps
CPU time 4.56 seconds
Started Aug 10 05:05:03 PM PDT 24
Finished Aug 10 05:05:14 PM PDT 24
Peak memory 164752 kb
Host smart-3d7462c5-e40c-4ccf-aa76-3a256c486335
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1264977783 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.1264977783
Directory /workspace/15.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.1407594569
Short name T168
Test name
Test status
Simulation time 1555370000 ps
CPU time 5.07 seconds
Started Aug 10 05:05:03 PM PDT 24
Finished Aug 10 05:05:14 PM PDT 24
Peak memory 164836 kb
Host smart-74f4c267-3993-4bac-a34a-8f2dae8554b8
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1407594569 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.1407594569
Directory /workspace/16.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.1765433848
Short name T197
Test name
Test status
Simulation time 1207510000 ps
CPU time 3.43 seconds
Started Aug 10 05:05:02 PM PDT 24
Finished Aug 10 05:05:09 PM PDT 24
Peak memory 164820 kb
Host smart-2814c549-66e1-4c44-a62d-960f256639e5
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1765433848 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.1765433848
Directory /workspace/17.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.2331731317
Short name T161
Test name
Test status
Simulation time 1382250000 ps
CPU time 4.88 seconds
Started Aug 10 05:05:06 PM PDT 24
Finished Aug 10 05:05:18 PM PDT 24
Peak memory 164792 kb
Host smart-c089c8ad-342c-47bc-ae9d-217973d5dca0
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2331731317 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.2331731317
Directory /workspace/18.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.2843067072
Short name T180
Test name
Test status
Simulation time 1621150000 ps
CPU time 5.82 seconds
Started Aug 10 05:05:06 PM PDT 24
Finished Aug 10 05:05:20 PM PDT 24
Peak memory 164792 kb
Host smart-bd404f46-34ec-4167-9c68-9250e53d9307
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2843067072 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.2843067072
Directory /workspace/19.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.3596665864
Short name T165
Test name
Test status
Simulation time 1480310000 ps
CPU time 3.81 seconds
Started Aug 10 05:05:03 PM PDT 24
Finished Aug 10 05:05:12 PM PDT 24
Peak memory 164812 kb
Host smart-aedab8d2-fae5-48c9-88ad-87172e8796e4
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3596665864 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.3596665864
Directory /workspace/2.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.2045078278
Short name T192
Test name
Test status
Simulation time 1541310000 ps
CPU time 5.03 seconds
Started Aug 10 05:05:03 PM PDT 24
Finished Aug 10 05:05:14 PM PDT 24
Peak memory 164864 kb
Host smart-50baf5fc-5068-4c05-a3e5-22cd68d09a6a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2045078278 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.2045078278
Directory /workspace/20.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.4087366590
Short name T198
Test name
Test status
Simulation time 1476850000 ps
CPU time 4.95 seconds
Started Aug 10 05:05:03 PM PDT 24
Finished Aug 10 05:05:14 PM PDT 24
Peak memory 164780 kb
Host smart-2da1c8b5-9537-4273-b9ab-eb428eae33b8
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4087366590 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.4087366590
Directory /workspace/21.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.2173470193
Short name T157
Test name
Test status
Simulation time 1240950000 ps
CPU time 3.83 seconds
Started Aug 10 05:05:04 PM PDT 24
Finished Aug 10 05:05:13 PM PDT 24
Peak memory 164752 kb
Host smart-70602a33-f89e-4358-bf57-44e991907f8b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2173470193 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.2173470193
Directory /workspace/22.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.1621334277
Short name T170
Test name
Test status
Simulation time 1111190000 ps
CPU time 3.35 seconds
Started Aug 10 05:05:01 PM PDT 24
Finished Aug 10 05:05:09 PM PDT 24
Peak memory 164836 kb
Host smart-0658c6a2-c7a2-43fe-8d40-0607abe4795d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1621334277 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.1621334277
Directory /workspace/23.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.879599944
Short name T169
Test name
Test status
Simulation time 1536850000 ps
CPU time 5.42 seconds
Started Aug 10 05:05:01 PM PDT 24
Finished Aug 10 05:05:13 PM PDT 24
Peak memory 164736 kb
Host smart-0e039161-1e35-46c3-9c0e-b800c10c551e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=879599944 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.879599944
Directory /workspace/24.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.3305851277
Short name T158
Test name
Test status
Simulation time 1520730000 ps
CPU time 4.49 seconds
Started Aug 10 05:05:03 PM PDT 24
Finished Aug 10 05:05:13 PM PDT 24
Peak memory 164828 kb
Host smart-3256255e-1a83-410a-8075-3a4f76e02c7e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3305851277 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.3305851277
Directory /workspace/25.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.3619602799
Short name T156
Test name
Test status
Simulation time 985810000 ps
CPU time 2.74 seconds
Started Aug 10 05:05:01 PM PDT 24
Finished Aug 10 05:05:07 PM PDT 24
Peak memory 164812 kb
Host smart-8a9b11db-05a3-4e05-b76c-bc34947b765c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3619602799 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.3619602799
Directory /workspace/26.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.3627722093
Short name T176
Test name
Test status
Simulation time 1484030000 ps
CPU time 4.48 seconds
Started Aug 10 05:05:03 PM PDT 24
Finished Aug 10 05:05:13 PM PDT 24
Peak memory 164808 kb
Host smart-1a50408a-56e4-492d-a0af-e5cabc9450c8
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3627722093 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.3627722093
Directory /workspace/27.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.365178863
Short name T164
Test name
Test status
Simulation time 1454810000 ps
CPU time 5.96 seconds
Started Aug 10 05:05:03 PM PDT 24
Finished Aug 10 05:05:16 PM PDT 24
Peak memory 164812 kb
Host smart-22198344-6dde-4203-9086-600fb3238d86
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=365178863 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.365178863
Directory /workspace/28.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.3322738693
Short name T166
Test name
Test status
Simulation time 1528030000 ps
CPU time 5.22 seconds
Started Aug 10 05:05:02 PM PDT 24
Finished Aug 10 05:05:13 PM PDT 24
Peak memory 164840 kb
Host smart-9b2d3b49-859f-4cdb-8a5e-1e8828d56565
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3322738693 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.3322738693
Directory /workspace/29.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.1116716849
Short name T160
Test name
Test status
Simulation time 1415710000 ps
CPU time 3.38 seconds
Started Aug 10 05:05:02 PM PDT 24
Finished Aug 10 05:05:09 PM PDT 24
Peak memory 164792 kb
Host smart-f4e13f26-5e64-4fbe-b86e-5d03af35497b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1116716849 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.1116716849
Directory /workspace/3.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.2234016197
Short name T155
Test name
Test status
Simulation time 1490790000 ps
CPU time 4.49 seconds
Started Aug 10 05:05:04 PM PDT 24
Finished Aug 10 05:05:15 PM PDT 24
Peak memory 164752 kb
Host smart-07ccd47a-2f40-4e11-afb0-ea12efa37c8a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2234016197 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.2234016197
Directory /workspace/30.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.1755535375
Short name T189
Test name
Test status
Simulation time 1548490000 ps
CPU time 4.64 seconds
Started Aug 10 05:05:15 PM PDT 24
Finished Aug 10 05:05:25 PM PDT 24
Peak memory 164816 kb
Host smart-8f1c8533-8c91-46ca-8fb5-209649ad17d9
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1755535375 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.1755535375
Directory /workspace/31.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.1399443525
Short name T151
Test name
Test status
Simulation time 1370270000 ps
CPU time 4.08 seconds
Started Aug 10 05:05:19 PM PDT 24
Finished Aug 10 05:05:28 PM PDT 24
Peak memory 164844 kb
Host smart-25a313e0-dfba-4319-aa36-f680db472282
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1399443525 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.1399443525
Directory /workspace/32.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.3655405613
Short name T153
Test name
Test status
Simulation time 1462310000 ps
CPU time 5.9 seconds
Started Aug 10 05:05:16 PM PDT 24
Finished Aug 10 05:05:29 PM PDT 24
Peak memory 165028 kb
Host smart-d905a0cc-d281-43e0-9145-1a3fe22c5ee2
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3655405613 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.3655405613
Directory /workspace/33.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.3478896625
Short name T154
Test name
Test status
Simulation time 1327790000 ps
CPU time 4.37 seconds
Started Aug 10 05:05:14 PM PDT 24
Finished Aug 10 05:05:24 PM PDT 24
Peak memory 164812 kb
Host smart-95e63b84-6899-4e11-a914-254433b7a153
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3478896625 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.3478896625
Directory /workspace/34.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.15261797
Short name T159
Test name
Test status
Simulation time 1455910000 ps
CPU time 5.21 seconds
Started Aug 10 05:05:13 PM PDT 24
Finished Aug 10 05:05:25 PM PDT 24
Peak memory 164792 kb
Host smart-83b31753-48e0-4f76-820f-6a04dfefbd7a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=15261797 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.15261797
Directory /workspace/35.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.1828998578
Short name T193
Test name
Test status
Simulation time 1555170000 ps
CPU time 3.32 seconds
Started Aug 10 05:05:10 PM PDT 24
Finished Aug 10 05:05:18 PM PDT 24
Peak memory 164808 kb
Host smart-af2b9397-1ac3-4398-9fa8-06db848f427f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1828998578 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.1828998578
Directory /workspace/36.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.3116803361
Short name T195
Test name
Test status
Simulation time 1605330000 ps
CPU time 6.48 seconds
Started Aug 10 05:05:16 PM PDT 24
Finished Aug 10 05:05:30 PM PDT 24
Peak memory 164976 kb
Host smart-4b7d2d8a-f844-4d2a-b3bf-3e71992e8792
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3116803361 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.3116803361
Directory /workspace/37.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.931400991
Short name T172
Test name
Test status
Simulation time 1470370000 ps
CPU time 3.96 seconds
Started Aug 10 05:05:12 PM PDT 24
Finished Aug 10 05:05:21 PM PDT 24
Peak memory 164860 kb
Host smart-ef71b406-64bf-4658-9983-c310ca9100cb
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=931400991 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.931400991
Directory /workspace/38.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.2060026596
Short name T175
Test name
Test status
Simulation time 1321790000 ps
CPU time 5.12 seconds
Started Aug 10 05:05:13 PM PDT 24
Finished Aug 10 05:05:24 PM PDT 24
Peak memory 164796 kb
Host smart-1c5c1f6b-35c7-44ce-a55e-07b3f48589fb
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2060026596 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.2060026596
Directory /workspace/39.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3415455140
Short name T179
Test name
Test status
Simulation time 1461490000 ps
CPU time 3.23 seconds
Started Aug 10 05:05:00 PM PDT 24
Finished Aug 10 05:05:07 PM PDT 24
Peak memory 164872 kb
Host smart-eefeaaad-b2a3-4557-ba99-de8d6db41d7c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3415455140 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.3415455140
Directory /workspace/4.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.19643223
Short name T182
Test name
Test status
Simulation time 1499870000 ps
CPU time 3.92 seconds
Started Aug 10 05:05:21 PM PDT 24
Finished Aug 10 05:05:30 PM PDT 24
Peak memory 164824 kb
Host smart-11102a90-a776-4303-9f83-531405418913
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=19643223 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.19643223
Directory /workspace/40.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.1298640851
Short name T152
Test name
Test status
Simulation time 1386630000 ps
CPU time 4.1 seconds
Started Aug 10 05:05:17 PM PDT 24
Finished Aug 10 05:05:26 PM PDT 24
Peak memory 164884 kb
Host smart-b12f0187-e1c7-4e3e-8f5a-e49ebd6c78e6
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1298640851 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.1298640851
Directory /workspace/41.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.503705529
Short name T200
Test name
Test status
Simulation time 1563770000 ps
CPU time 5.16 seconds
Started Aug 10 05:05:12 PM PDT 24
Finished Aug 10 05:05:24 PM PDT 24
Peak memory 164908 kb
Host smart-d5ae0808-7eec-4cd2-9d35-0dcdf6e26f21
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=503705529 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.503705529
Directory /workspace/42.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1817266600
Short name T188
Test name
Test status
Simulation time 1379070000 ps
CPU time 3.34 seconds
Started Aug 10 05:05:12 PM PDT 24
Finished Aug 10 05:05:20 PM PDT 24
Peak memory 164888 kb
Host smart-59a0f3fe-7e28-4c1e-86c2-ab324ce9381a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1817266600 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.1817266600
Directory /workspace/43.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.2421775657
Short name T167
Test name
Test status
Simulation time 1545730000 ps
CPU time 5.09 seconds
Started Aug 10 05:05:12 PM PDT 24
Finished Aug 10 05:05:23 PM PDT 24
Peak memory 164904 kb
Host smart-7310a9f3-9a73-4c67-b904-924aa4ee0b66
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2421775657 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.2421775657
Directory /workspace/44.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.3064609298
Short name T173
Test name
Test status
Simulation time 1450890000 ps
CPU time 4.93 seconds
Started Aug 10 05:05:16 PM PDT 24
Finished Aug 10 05:05:26 PM PDT 24
Peak memory 164896 kb
Host smart-d95ad799-18ed-4df5-af52-a877eb11a2f2
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3064609298 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.3064609298
Directory /workspace/45.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.2859688977
Short name T163
Test name
Test status
Simulation time 1481810000 ps
CPU time 4.77 seconds
Started Aug 10 05:05:15 PM PDT 24
Finished Aug 10 05:05:25 PM PDT 24
Peak memory 164836 kb
Host smart-d2abe459-ac46-4627-9bb4-6f347fc77032
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2859688977 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.2859688977
Directory /workspace/46.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.1725695757
Short name T196
Test name
Test status
Simulation time 1485630000 ps
CPU time 4.83 seconds
Started Aug 10 05:05:13 PM PDT 24
Finished Aug 10 05:05:23 PM PDT 24
Peak memory 164768 kb
Host smart-9b6d43cc-6a3b-42ea-8171-a6ed8635f89c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1725695757 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.1725695757
Directory /workspace/47.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.454853094
Short name T162
Test name
Test status
Simulation time 1522130000 ps
CPU time 5.08 seconds
Started Aug 10 05:05:14 PM PDT 24
Finished Aug 10 05:05:25 PM PDT 24
Peak memory 164876 kb
Host smart-4931cd24-a81b-4074-90f5-61a4a99beeab
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=454853094 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.454853094
Directory /workspace/48.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.132389506
Short name T178
Test name
Test status
Simulation time 1536470000 ps
CPU time 4.98 seconds
Started Aug 10 05:05:15 PM PDT 24
Finished Aug 10 05:05:26 PM PDT 24
Peak memory 164864 kb
Host smart-4fbbfeef-68a2-4cde-b34d-8d54bae9793e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=132389506 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.132389506
Directory /workspace/49.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.3383836117
Short name T185
Test name
Test status
Simulation time 1333570000 ps
CPU time 4.53 seconds
Started Aug 10 05:05:03 PM PDT 24
Finished Aug 10 05:05:13 PM PDT 24
Peak memory 164832 kb
Host smart-9b0a60b0-ab88-46d7-9791-84f5d7d672a5
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3383836117 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.3383836117
Directory /workspace/5.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.188383068
Short name T181
Test name
Test status
Simulation time 1530010000 ps
CPU time 6.17 seconds
Started Aug 10 05:05:03 PM PDT 24
Finished Aug 10 05:05:16 PM PDT 24
Peak memory 164948 kb
Host smart-977179b0-0d5b-4021-a6be-dd8f0833c813
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=188383068 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.188383068
Directory /workspace/6.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.2517298105
Short name T177
Test name
Test status
Simulation time 1531690000 ps
CPU time 4.36 seconds
Started Aug 10 05:05:03 PM PDT 24
Finished Aug 10 05:05:12 PM PDT 24
Peak memory 164900 kb
Host smart-0eef893e-bc6c-40a5-885a-6ed7bbfdaf33
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2517298105 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.2517298105
Directory /workspace/7.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.3432744871
Short name T194
Test name
Test status
Simulation time 1453550000 ps
CPU time 5.27 seconds
Started Aug 10 05:05:02 PM PDT 24
Finished Aug 10 05:05:14 PM PDT 24
Peak memory 164856 kb
Host smart-c25ce095-b57a-4c22-a97f-e19a93e6de94
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3432744871 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.3432744871
Directory /workspace/8.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.1136118252
Short name T187
Test name
Test status
Simulation time 1309870000 ps
CPU time 4.31 seconds
Started Aug 10 05:05:03 PM PDT 24
Finished Aug 10 05:05:13 PM PDT 24
Peak memory 164840 kb
Host smart-d6403225-70d0-4c51-bff6-3093106771ca
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1136118252 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.1136118252
Directory /workspace/9.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.2326036856
Short name T58
Test name
Test status
Simulation time 1619750000 ps
CPU time 4.5 seconds
Started Aug 10 04:28:55 PM PDT 24
Finished Aug 10 04:29:05 PM PDT 24
Peak memory 164748 kb
Host smart-8475578d-b89e-4e30-b89a-a894bb0a3702
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2326036856 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.2326036856
Directory /workspace/0.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.581916784
Short name T66
Test name
Test status
Simulation time 1505370000 ps
CPU time 3.98 seconds
Started Aug 10 04:28:55 PM PDT 24
Finished Aug 10 04:29:03 PM PDT 24
Peak memory 164832 kb
Host smart-fc7f418b-356c-4e8b-932f-689e217d841b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=581916784 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.581916784
Directory /workspace/1.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.2497285471
Short name T70
Test name
Test status
Simulation time 1384070000 ps
CPU time 4.81 seconds
Started Aug 10 04:28:57 PM PDT 24
Finished Aug 10 04:29:09 PM PDT 24
Peak memory 164752 kb
Host smart-052c818c-d3fd-4e41-beb8-b4efa719b570
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2497285471 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.2497285471
Directory /workspace/10.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.1110178051
Short name T67
Test name
Test status
Simulation time 1634930000 ps
CPU time 4.25 seconds
Started Aug 10 04:28:57 PM PDT 24
Finished Aug 10 04:29:08 PM PDT 24
Peak memory 164700 kb
Host smart-2414d99e-c369-4a31-8ff4-4190dddb2e8a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1110178051 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.1110178051
Directory /workspace/12.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.3547016567
Short name T54
Test name
Test status
Simulation time 1519630000 ps
CPU time 4.46 seconds
Started Aug 10 04:29:14 PM PDT 24
Finished Aug 10 04:29:23 PM PDT 24
Peak memory 164764 kb
Host smart-e0eda35e-e612-4212-adfb-c4c82082fa20
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3547016567 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.3547016567
Directory /workspace/13.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.917106703
Short name T68
Test name
Test status
Simulation time 1463830000 ps
CPU time 3.05 seconds
Started Aug 10 04:29:09 PM PDT 24
Finished Aug 10 04:29:16 PM PDT 24
Peak memory 164780 kb
Host smart-26a46a10-8163-41f8-9689-9eca864f2ab0
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=917106703 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.917106703
Directory /workspace/14.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.1857695257
Short name T3
Test name
Test status
Simulation time 1419030000 ps
CPU time 2.88 seconds
Started Aug 10 04:29:00 PM PDT 24
Finished Aug 10 04:29:06 PM PDT 24
Peak memory 164732 kb
Host smart-971d0dad-a59c-4c29-b717-656b56c622bb
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1857695257 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.1857695257
Directory /workspace/15.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.2799659803
Short name T45
Test name
Test status
Simulation time 1452630000 ps
CPU time 4.05 seconds
Started Aug 10 04:29:01 PM PDT 24
Finished Aug 10 04:29:10 PM PDT 24
Peak memory 164748 kb
Host smart-d7e70e4d-a0f3-4d42-92ca-7a700bdd9699
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2799659803 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.2799659803
Directory /workspace/16.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.2640523676
Short name T37
Test name
Test status
Simulation time 1564870000 ps
CPU time 5.05 seconds
Started Aug 10 04:28:58 PM PDT 24
Finished Aug 10 04:29:09 PM PDT 24
Peak memory 164828 kb
Host smart-c463f585-0e02-4a5c-b8cf-d0ba5424a8a1
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2640523676 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.2640523676
Directory /workspace/17.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.2476925805
Short name T11
Test name
Test status
Simulation time 1335310000 ps
CPU time 4.35 seconds
Started Aug 10 04:29:03 PM PDT 24
Finished Aug 10 04:29:12 PM PDT 24
Peak memory 164684 kb
Host smart-14f37228-8361-442f-911a-9bd3e69f6d70
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2476925805 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.2476925805
Directory /workspace/18.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.3051189580
Short name T50
Test name
Test status
Simulation time 1423450000 ps
CPU time 3.43 seconds
Started Aug 10 04:29:07 PM PDT 24
Finished Aug 10 04:29:15 PM PDT 24
Peak memory 164796 kb
Host smart-144e8924-d46e-451c-9465-af7e02497bd3
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3051189580 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.3051189580
Directory /workspace/19.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.387564048
Short name T63
Test name
Test status
Simulation time 1503330000 ps
CPU time 5.11 seconds
Started Aug 10 04:28:57 PM PDT 24
Finished Aug 10 04:29:10 PM PDT 24
Peak memory 164748 kb
Host smart-676aed0c-1e1f-4425-82ff-e6b43afa3665
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=387564048 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.387564048
Directory /workspace/2.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.1327233508
Short name T57
Test name
Test status
Simulation time 1585210000 ps
CPU time 4.37 seconds
Started Aug 10 04:28:59 PM PDT 24
Finished Aug 10 04:29:09 PM PDT 24
Peak memory 164744 kb
Host smart-21368268-28c4-452f-9ebf-d9f54998a779
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1327233508 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.1327233508
Directory /workspace/20.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.2276578083
Short name T40
Test name
Test status
Simulation time 1366070000 ps
CPU time 3.75 seconds
Started Aug 10 04:29:12 PM PDT 24
Finished Aug 10 04:29:21 PM PDT 24
Peak memory 164764 kb
Host smart-3affefc4-2c4a-42c7-bad7-788828335480
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2276578083 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.2276578083
Directory /workspace/21.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.4245278489
Short name T12
Test name
Test status
Simulation time 1494690000 ps
CPU time 4.23 seconds
Started Aug 10 04:28:57 PM PDT 24
Finished Aug 10 04:29:07 PM PDT 24
Peak memory 164724 kb
Host smart-b0731f7b-be12-4cda-ae7d-db3da5d2155d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4245278489 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.4245278489
Directory /workspace/22.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.2980135016
Short name T53
Test name
Test status
Simulation time 1550570000 ps
CPU time 3.09 seconds
Started Aug 10 04:28:59 PM PDT 24
Finished Aug 10 04:29:07 PM PDT 24
Peak memory 164728 kb
Host smart-f3eb2811-f9e4-4af0-bb43-0538a3e265ae
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2980135016 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.2980135016
Directory /workspace/23.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.4220954984
Short name T69
Test name
Test status
Simulation time 1303070000 ps
CPU time 4.24 seconds
Started Aug 10 04:29:10 PM PDT 24
Finished Aug 10 04:29:20 PM PDT 24
Peak memory 164688 kb
Host smart-dcba9b95-9def-49c9-bb81-9aa2b27bce93
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4220954984 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.4220954984
Directory /workspace/24.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.1883044393
Short name T52
Test name
Test status
Simulation time 1541970000 ps
CPU time 3.6 seconds
Started Aug 10 04:29:20 PM PDT 24
Finished Aug 10 04:29:28 PM PDT 24
Peak memory 164956 kb
Host smart-eabf7c52-3de6-49f0-b524-f36e03903a51
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1883044393 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.1883044393
Directory /workspace/25.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.2014812564
Short name T41
Test name
Test status
Simulation time 1531510000 ps
CPU time 4.06 seconds
Started Aug 10 04:28:55 PM PDT 24
Finished Aug 10 04:29:05 PM PDT 24
Peak memory 164780 kb
Host smart-a9e04f6f-3de2-40fb-839c-41f300ecf3f2
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2014812564 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.2014812564
Directory /workspace/26.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.242932664
Short name T42
Test name
Test status
Simulation time 1255310000 ps
CPU time 3.26 seconds
Started Aug 10 04:29:20 PM PDT 24
Finished Aug 10 04:29:28 PM PDT 24
Peak memory 164776 kb
Host smart-09f41a27-7a0c-4cdb-b0e7-b9298048cf4b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=242932664 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.242932664
Directory /workspace/27.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.4269059305
Short name T44
Test name
Test status
Simulation time 1521610000 ps
CPU time 4.3 seconds
Started Aug 10 04:28:55 PM PDT 24
Finished Aug 10 04:29:04 PM PDT 24
Peak memory 164720 kb
Host smart-092bfaeb-2346-4686-ae2b-fcbad9e6c576
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4269059305 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.4269059305
Directory /workspace/28.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.1425994065
Short name T65
Test name
Test status
Simulation time 1446010000 ps
CPU time 4.08 seconds
Started Aug 10 04:29:03 PM PDT 24
Finished Aug 10 04:29:12 PM PDT 24
Peak memory 164732 kb
Host smart-8691d5f7-6cb3-41af-bcf9-adbd03f62055
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1425994065 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.1425994065
Directory /workspace/29.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.2665766212
Short name T36
Test name
Test status
Simulation time 1239650000 ps
CPU time 3.13 seconds
Started Aug 10 04:28:57 PM PDT 24
Finished Aug 10 04:29:04 PM PDT 24
Peak memory 164720 kb
Host smart-d9e3f16d-dd48-468b-a1ee-5f4fe5ddc01d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2665766212 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.2665766212
Directory /workspace/3.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.425672502
Short name T55
Test name
Test status
Simulation time 1619870000 ps
CPU time 5.01 seconds
Started Aug 10 04:28:57 PM PDT 24
Finished Aug 10 04:29:09 PM PDT 24
Peak memory 164824 kb
Host smart-40f2fb5c-bdb7-43fa-b53d-54010bf80aea
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=425672502 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.425672502
Directory /workspace/30.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.4122117678
Short name T9
Test name
Test status
Simulation time 1510610000 ps
CPU time 3.8 seconds
Started Aug 10 04:29:22 PM PDT 24
Finished Aug 10 04:29:31 PM PDT 24
Peak memory 164768 kb
Host smart-47af8b17-b7d3-4ffa-85f3-917ba587e3f2
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4122117678 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.4122117678
Directory /workspace/31.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.1108890395
Short name T38
Test name
Test status
Simulation time 1319290000 ps
CPU time 2.96 seconds
Started Aug 10 04:28:59 PM PDT 24
Finished Aug 10 04:29:06 PM PDT 24
Peak memory 164956 kb
Host smart-84bce0c9-1e2b-4658-a8d8-7e160a059a37
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1108890395 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.1108890395
Directory /workspace/32.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.4186711735
Short name T47
Test name
Test status
Simulation time 1426010000 ps
CPU time 4.13 seconds
Started Aug 10 04:29:03 PM PDT 24
Finished Aug 10 04:29:13 PM PDT 24
Peak memory 164768 kb
Host smart-e455d7b1-4341-44d5-bec3-50045c67ead6
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4186711735 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.4186711735
Directory /workspace/33.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.3982126115
Short name T48
Test name
Test status
Simulation time 1558830000 ps
CPU time 5.37 seconds
Started Aug 10 04:28:58 PM PDT 24
Finished Aug 10 04:29:10 PM PDT 24
Peak memory 164724 kb
Host smart-423971cb-d2a1-4f77-ad6a-8063320ee99d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3982126115 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.3982126115
Directory /workspace/34.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.4110931904
Short name T59
Test name
Test status
Simulation time 1425750000 ps
CPU time 3.65 seconds
Started Aug 10 04:29:09 PM PDT 24
Finished Aug 10 04:29:17 PM PDT 24
Peak memory 164772 kb
Host smart-d14bb385-9882-4ee4-a4df-b85ddc5821e7
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4110931904 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.4110931904
Directory /workspace/35.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.3589453502
Short name T32
Test name
Test status
Simulation time 1547470000 ps
CPU time 4.01 seconds
Started Aug 10 04:28:58 PM PDT 24
Finished Aug 10 04:29:07 PM PDT 24
Peak memory 164700 kb
Host smart-af33bc49-f9cf-4523-bc18-8732b3b94af1
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3589453502 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.3589453502
Directory /workspace/36.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.1338710462
Short name T61
Test name
Test status
Simulation time 1509050000 ps
CPU time 3.6 seconds
Started Aug 10 04:29:19 PM PDT 24
Finished Aug 10 04:29:27 PM PDT 24
Peak memory 164796 kb
Host smart-e9871e22-4aa2-4d6b-8f14-867dea5f1ec8
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1338710462 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.1338710462
Directory /workspace/37.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.2111366660
Short name T60
Test name
Test status
Simulation time 1530490000 ps
CPU time 4.27 seconds
Started Aug 10 04:29:25 PM PDT 24
Finished Aug 10 04:29:35 PM PDT 24
Peak memory 164772 kb
Host smart-36323bcc-1924-477a-a38c-5c4074e8aa43
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2111366660 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.2111366660
Directory /workspace/38.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.1979978198
Short name T39
Test name
Test status
Simulation time 1422310000 ps
CPU time 4.06 seconds
Started Aug 10 04:29:22 PM PDT 24
Finished Aug 10 04:29:31 PM PDT 24
Peak memory 164692 kb
Host smart-6bbed447-8440-4102-9cc7-df529017d99b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1979978198 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.1979978198
Directory /workspace/39.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.727620663
Short name T1
Test name
Test status
Simulation time 1543770000 ps
CPU time 4.39 seconds
Started Aug 10 04:28:56 PM PDT 24
Finished Aug 10 04:29:06 PM PDT 24
Peak memory 164840 kb
Host smart-9fe9389d-310b-4b71-a6b8-ce64090d210f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=727620663 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.727620663
Directory /workspace/4.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.660366385
Short name T31
Test name
Test status
Simulation time 1534890000 ps
CPU time 4.17 seconds
Started Aug 10 04:29:13 PM PDT 24
Finished Aug 10 04:29:22 PM PDT 24
Peak memory 164772 kb
Host smart-1d88d679-f81e-40c8-8df3-0e9eee916bd8
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=660366385 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.660366385
Directory /workspace/40.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.2368742493
Short name T62
Test name
Test status
Simulation time 1477590000 ps
CPU time 3.49 seconds
Started Aug 10 04:29:17 PM PDT 24
Finished Aug 10 04:29:25 PM PDT 24
Peak memory 164840 kb
Host smart-a6f21b6a-e6eb-4866-89a7-872016fa73b4
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2368742493 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.2368742493
Directory /workspace/41.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.4207706362
Short name T35
Test name
Test status
Simulation time 1410010000 ps
CPU time 4.42 seconds
Started Aug 10 04:29:00 PM PDT 24
Finished Aug 10 04:29:09 PM PDT 24
Peak memory 164704 kb
Host smart-1b59ed98-727b-4161-997e-c510c2103b0e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4207706362 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.4207706362
Directory /workspace/42.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.1074006592
Short name T33
Test name
Test status
Simulation time 1546250000 ps
CPU time 3.74 seconds
Started Aug 10 04:29:11 PM PDT 24
Finished Aug 10 04:29:19 PM PDT 24
Peak memory 164840 kb
Host smart-bdd36a94-7c13-4d55-a72a-4c6d33af11b3
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1074006592 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.1074006592
Directory /workspace/43.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.637219357
Short name T64
Test name
Test status
Simulation time 1434290000 ps
CPU time 3.82 seconds
Started Aug 10 04:29:13 PM PDT 24
Finished Aug 10 04:29:21 PM PDT 24
Peak memory 164852 kb
Host smart-5018b90b-9b6e-44b8-b0d6-da48133f17af
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=637219357 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.637219357
Directory /workspace/44.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.1880857928
Short name T51
Test name
Test status
Simulation time 1657530000 ps
CPU time 3.89 seconds
Started Aug 10 04:29:09 PM PDT 24
Finished Aug 10 04:29:18 PM PDT 24
Peak memory 164764 kb
Host smart-e7db930f-ccdb-4256-a201-65000524a283
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1880857928 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.1880857928
Directory /workspace/45.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.3459241321
Short name T43
Test name
Test status
Simulation time 1518990000 ps
CPU time 3.75 seconds
Started Aug 10 04:29:14 PM PDT 24
Finished Aug 10 04:29:22 PM PDT 24
Peak memory 164840 kb
Host smart-c4a84f83-ca49-4bfd-af2e-44a71c1d5060
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3459241321 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.3459241321
Directory /workspace/46.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.115336623
Short name T49
Test name
Test status
Simulation time 1567950000 ps
CPU time 3.65 seconds
Started Aug 10 04:29:29 PM PDT 24
Finished Aug 10 04:29:37 PM PDT 24
Peak memory 164780 kb
Host smart-d9267533-c590-46dd-af9d-d140df9cd114
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=115336623 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.115336623
Directory /workspace/47.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.2718872483
Short name T46
Test name
Test status
Simulation time 1269790000 ps
CPU time 3.67 seconds
Started Aug 10 04:29:10 PM PDT 24
Finished Aug 10 04:29:19 PM PDT 24
Peak memory 164760 kb
Host smart-8fd71e0b-bcaa-478a-a8b4-7b555b7aa8f4
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2718872483 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.2718872483
Directory /workspace/48.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.621169658
Short name T56
Test name
Test status
Simulation time 1418550000 ps
CPU time 2.84 seconds
Started Aug 10 04:29:21 PM PDT 24
Finished Aug 10 04:29:27 PM PDT 24
Peak memory 164852 kb
Host smart-45ad5e40-67c3-49cd-a7c6-96b457c82dbf
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=621169658 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.621169658
Directory /workspace/49.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.747249893
Short name T10
Test name
Test status
Simulation time 1532570000 ps
CPU time 5.56 seconds
Started Aug 10 04:28:57 PM PDT 24
Finished Aug 10 04:29:10 PM PDT 24
Peak memory 164804 kb
Host smart-4cb3d122-ad7e-4879-9cd4-0121e7df9bec
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=747249893 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.747249893
Directory /workspace/5.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.2225143278
Short name T13
Test name
Test status
Simulation time 1448990000 ps
CPU time 4.08 seconds
Started Aug 10 04:29:09 PM PDT 24
Finished Aug 10 04:29:19 PM PDT 24
Peak memory 164764 kb
Host smart-13c321c4-0498-4e55-aa6c-23a8a5a295ef
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2225143278 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.2225143278
Directory /workspace/6.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.4276939770
Short name T8
Test name
Test status
Simulation time 1361250000 ps
CPU time 4.33 seconds
Started Aug 10 04:29:17 PM PDT 24
Finished Aug 10 04:29:27 PM PDT 24
Peak memory 164692 kb
Host smart-e0a96fc9-c1c9-4e07-9996-8ab10ced3b4b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4276939770 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.4276939770
Directory /workspace/7.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.95901361
Short name T34
Test name
Test status
Simulation time 1484990000 ps
CPU time 4.82 seconds
Started Aug 10 04:28:56 PM PDT 24
Finished Aug 10 04:29:07 PM PDT 24
Peak memory 164736 kb
Host smart-95e5028b-e582-43e4-bdaa-409c38e874ac
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=95901361 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.95901361
Directory /workspace/8.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.3554440036
Short name T7
Test name
Test status
Simulation time 1114530000 ps
CPU time 2.76 seconds
Started Aug 10 04:29:04 PM PDT 24
Finished Aug 10 04:29:10 PM PDT 24
Peak memory 164772 kb
Host smart-0fc2f52f-177a-42fc-8194-ae1ab4448d13
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3554440036 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.3554440036
Directory /workspace/9.prim_lfsr_gal_smoke/latest
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