| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 98.31 | 100.00 | 96.55 | 100.00 | 100.00 | 95.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 87.31 | 87.31 | 100.00 | 100.00 | 96.55 | 96.55 | 100.00 | 100.00 | 100.00 | 100.00 | 40.00 | 40.00 | /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.1895119420 | ||
| 95.31 | 8.00 | 100.00 | 0.00 | 96.55 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 80.00 | 40.00 | /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.3226090656 | ||
| 98.31 | 3.00 | 100.00 | 0.00 | 96.55 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 95.00 | 15.00 | /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.1789081582 | ||
| Name |
|---|
| /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.4123590888 |
| /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.3568680110 |
| /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.162660852 |
| /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.3498293047 |
| /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.4130839805 |
| /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.1379703629 |
| /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.2757896208 |
| /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.4062640181 |
| /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.1707536754 |
| /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.512046129 |
| /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.1322484313 |
| /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.729360438 |
| /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.2785844097 |
| /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.430663861 |
| /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.950989115 |
| /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.2356520888 |
| /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.3088514281 |
| /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.1594675803 |
| /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1899009485 |
| /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.3321952429 |
| /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.3440612749 |
| /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.1154040112 |
| /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.4184955821 |
| /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.461844941 |
| /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.3385744822 |
| /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.2546287363 |
| /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.3262298849 |
| /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.1880846761 |
| /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.4210116104 |
| /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.1983653460 |
| /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.460536541 |
| /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.3836830826 |
| /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.3013025847 |
| /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.1380426382 |
| /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.2362244969 |
| /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.3524800232 |
| /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.2774488596 |
| /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.958242611 |
| /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.2785007121 |
| /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.2154408057 |
| /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.3037590485 |
| /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.3857172432 |
| /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.396946459 |
| /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.2036381870 |
| /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.2569003146 |
| /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.3375086119 |
| /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.3891676562 |
| /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1462380254 |
| /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.2378113047 |
| /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.1231555462 |
| /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.1713435806 |
| /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.945880183 |
| /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.3373374572 |
| /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.2228314785 |
| /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.2490791138 |
| /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.1438082012 |
| /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.1298240873 |
| /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.3163578465 |
| /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.48201850 |
| /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.65423999 |
| /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.1332433802 |
| /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.903658410 |
| /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3957949986 |
| /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.4246455778 |
| /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.3744050357 |
| /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.1005568871 |
| /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.194469691 |
| /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.1587176225 |
| /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.2725054683 |
| /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.2455424931 |
| /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.2589953028 |
| /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.3364787094 |
| /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.3983386216 |
| /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.499932746 |
| /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.2196596188 |
| /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.1556550631 |
| /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.3881569018 |
| /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.3142117374 |
| /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.3203000896 |
| /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.2755214981 |
| /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.594283971 |
| /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.1115459163 |
| /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.1698532393 |
| /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.2888773715 |
| /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.2271334772 |
| /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.3851114446 |
| /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.3131438762 |
| /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.2980916963 |
| /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.767483288 |
| /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.450867745 |
| /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.3173338370 |
| /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.4244112247 |
| /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.1984994458 |
| /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.984596270 |
| /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.378115117 |
| /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.95195641 |
| /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.2239560865 |
| /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.1854141777 |
| /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.1642318611 |
| /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.3533276716 |
| /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.769104548 |
| /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.2069461319 |
| /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.678067835 |
| /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.798895769 |
| /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.3225840823 |
| /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.3040224804 |
| /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.289179793 |
| /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.3571430296 |
| /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.2065947793 |
| /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.2914777635 |
| /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.1411161637 |
| /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.3083688060 |
| /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.364110029 |
| /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.3076642022 |
| /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.3981455511 |
| /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.1140705953 |
| /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.2190096922 |
| /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2171490827 |
| /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.2517695081 |
| /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.2206745242 |
| /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.805763181 |
| /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.4003845370 |
| /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.420065535 |
| /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.2263860700 |
| /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.195760248 |
| /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.3446472512 |
| /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.2356618961 |
| /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.2482885486 |
| /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.1655776278 |
| /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1265012774 |
| /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.396709965 |
| /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.2013783844 |
| /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3447449961 |
| /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.3639380483 |
| /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.3037843402 |
| /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.2136266006 |
| /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.3624629292 |
| /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.396154987 |
| /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.4087445990 |
| /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.122746873 |
| /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.3067047193 |
| /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.3266026648 |
| /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.2860164181 |
| /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.1531299545 |
| /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.3128424139 |
| /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.2826644324 |
| /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.547548388 |
| /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2479651307 |
| /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.1938036404 |
| /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.4160103544 |
| /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.3007921149 |
| /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.856440441 |
| /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.1998891464 |
| /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.4292208724 |
| /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.43696594 |
| /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.3130511545 |
| /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.923717632 |
| /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.4178159803 |
| /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.3218191922 |
| /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.3081705912 |
| /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.2763594921 |
| /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.2161168367 |
| /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.2285211378 |
| /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.969404516 |
| /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.3288797968 |
| /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.2374329601 |
| /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.4065232222 |
| /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.1979330321 |
| /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.2017742067 |
| /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.859883406 |
| /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.3012591560 |
| /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.955855519 |
| /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.121540512 |
| /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.2040146306 |
| /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.84419991 |
| /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.894382432 |
| /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.1304356403 |
| /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.3189614815 |
| /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.389457619 |
| /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.1075863734 |
| /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.1521653075 |
| /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.232102185 |
| /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.838066415 |
| /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.1437255112 |
| /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.670265276 |
| /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.3470446257 |
| /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.1088280849 |
| /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.709398818 |
| /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.3580292318 |
| /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.1928076268 |
| /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.3540782395 |
| /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.553313825 |
| /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.3290869568 |
| /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.1384098770 |
| /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.228457454 |
| /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.2641980914 |
| /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.741221 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.84419991 | Aug 11 04:32:35 PM PDT 24 | Aug 11 04:32:46 PM PDT 24 | 1399890000 ps | ||
| T2 | /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.1979330321 | Aug 11 04:32:17 PM PDT 24 | Aug 11 04:32:25 PM PDT 24 | 1472350000 ps | ||
| T3 | /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.1895119420 | Aug 11 04:32:31 PM PDT 24 | Aug 11 04:32:39 PM PDT 24 | 1354710000 ps | ||
| T7 | /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.1384098770 | Aug 11 04:32:46 PM PDT 24 | Aug 11 04:32:55 PM PDT 24 | 1532510000 ps | ||
| T8 | /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.2763594921 | Aug 11 04:32:17 PM PDT 24 | Aug 11 04:32:26 PM PDT 24 | 1331610000 ps | ||
| T9 | /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.3130511545 | Aug 11 04:32:27 PM PDT 24 | Aug 11 04:32:37 PM PDT 24 | 1422070000 ps | ||
| T10 | /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.2641980914 | Aug 11 04:32:25 PM PDT 24 | Aug 11 04:32:36 PM PDT 24 | 1507350000 ps | ||
| T11 | /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.1521653075 | Aug 11 04:32:36 PM PDT 24 | Aug 11 04:32:43 PM PDT 24 | 1490110000 ps | ||
| T12 | /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.969404516 | Aug 11 04:32:13 PM PDT 24 | Aug 11 04:32:21 PM PDT 24 | 1219010000 ps | ||
| T13 | /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.3540782395 | Aug 11 04:32:23 PM PDT 24 | Aug 11 04:32:31 PM PDT 24 | 1382290000 ps | ||
| T31 | /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.232102185 | Aug 11 04:32:27 PM PDT 24 | Aug 11 04:32:36 PM PDT 24 | 1566030000 ps | ||
| T32 | /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.4160103544 | Aug 11 04:32:34 PM PDT 24 | Aug 11 04:32:42 PM PDT 24 | 1275790000 ps | ||
| T33 | /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.3007921149 | Aug 11 04:32:45 PM PDT 24 | Aug 11 04:32:53 PM PDT 24 | 1482890000 ps | ||
| T34 | /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.1088280849 | Aug 11 04:32:43 PM PDT 24 | Aug 11 04:32:50 PM PDT 24 | 1484870000 ps | ||
| T35 | /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.2374329601 | Aug 11 04:32:25 PM PDT 24 | Aug 11 04:32:32 PM PDT 24 | 1599810000 ps | ||
| T36 | /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.4292208724 | Aug 11 04:32:39 PM PDT 24 | Aug 11 04:32:47 PM PDT 24 | 1264190000 ps | ||
| T37 | /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.4178159803 | Aug 11 04:32:40 PM PDT 24 | Aug 11 04:32:47 PM PDT 24 | 1137630000 ps | ||
| T38 | /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.3012591560 | Aug 11 04:32:34 PM PDT 24 | Aug 11 04:32:43 PM PDT 24 | 1460810000 ps | ||
| T39 | /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.838066415 | Aug 11 04:32:25 PM PDT 24 | Aug 11 04:32:33 PM PDT 24 | 1364870000 ps | ||
| T40 | /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.1304356403 | Aug 11 04:32:20 PM PDT 24 | Aug 11 04:32:30 PM PDT 24 | 1318530000 ps | ||
| T41 | /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.894382432 | Aug 11 04:32:28 PM PDT 24 | Aug 11 04:32:35 PM PDT 24 | 1316310000 ps | ||
| T42 | /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.3081705912 | Aug 11 04:32:27 PM PDT 24 | Aug 11 04:32:37 PM PDT 24 | 1500330000 ps | ||
| T43 | /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.741221 | Aug 11 04:32:34 PM PDT 24 | Aug 11 04:32:41 PM PDT 24 | 1489130000 ps | ||
| T44 | /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.3189614815 | Aug 11 04:32:17 PM PDT 24 | Aug 11 04:32:26 PM PDT 24 | 1560130000 ps | ||
| T45 | /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.3218191922 | Aug 11 04:32:17 PM PDT 24 | Aug 11 04:32:25 PM PDT 24 | 1537970000 ps | ||
| T46 | /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.3290869568 | Aug 11 04:32:31 PM PDT 24 | Aug 11 04:32:40 PM PDT 24 | 1472150000 ps | ||
| T47 | /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.553313825 | Aug 11 04:32:35 PM PDT 24 | Aug 11 04:32:42 PM PDT 24 | 1192790000 ps | ||
| T48 | /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.228457454 | Aug 11 04:32:29 PM PDT 24 | Aug 11 04:32:37 PM PDT 24 | 1522650000 ps | ||
| T49 | /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.3470446257 | Aug 11 04:32:25 PM PDT 24 | Aug 11 04:32:36 PM PDT 24 | 1444610000 ps | ||
| T50 | /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.3580292318 | Aug 11 04:32:43 PM PDT 24 | Aug 11 04:32:51 PM PDT 24 | 1486810000 ps | ||
| T51 | /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.2161168367 | Aug 11 04:32:38 PM PDT 24 | Aug 11 04:32:45 PM PDT 24 | 1474990000 ps | ||
| T52 | /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.923717632 | Aug 11 04:32:31 PM PDT 24 | Aug 11 04:32:38 PM PDT 24 | 1551070000 ps | ||
| T53 | /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.2285211378 | Aug 11 04:32:20 PM PDT 24 | Aug 11 04:32:28 PM PDT 24 | 1526410000 ps | ||
| T54 | /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.1437255112 | Aug 11 04:32:27 PM PDT 24 | Aug 11 04:32:35 PM PDT 24 | 1441410000 ps | ||
| T55 | /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.670265276 | Aug 11 04:32:14 PM PDT 24 | Aug 11 04:32:24 PM PDT 24 | 1457970000 ps | ||
| T56 | /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.4065232222 | Aug 11 04:32:43 PM PDT 24 | Aug 11 04:32:51 PM PDT 24 | 1405730000 ps | ||
| T57 | /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.121540512 | Aug 11 04:32:21 PM PDT 24 | Aug 11 04:32:32 PM PDT 24 | 1504230000 ps | ||
| T58 | /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.2017742067 | Aug 11 04:32:29 PM PDT 24 | Aug 11 04:32:39 PM PDT 24 | 1550570000 ps | ||
| T59 | /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.1928076268 | Aug 11 04:32:43 PM PDT 24 | Aug 11 04:32:50 PM PDT 24 | 1367190000 ps | ||
| T60 | /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.3288797968 | Aug 11 04:32:49 PM PDT 24 | Aug 11 04:32:58 PM PDT 24 | 1515890000 ps | ||
| T61 | /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.1938036404 | Aug 11 04:32:38 PM PDT 24 | Aug 11 04:32:45 PM PDT 24 | 1393010000 ps | ||
| T62 | /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.389457619 | Aug 11 04:32:25 PM PDT 24 | Aug 11 04:32:34 PM PDT 24 | 1524030000 ps | ||
| T63 | /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.1075863734 | Aug 11 04:32:30 PM PDT 24 | Aug 11 04:32:40 PM PDT 24 | 1524330000 ps | ||
| T64 | /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.43696594 | Aug 11 04:32:25 PM PDT 24 | Aug 11 04:32:34 PM PDT 24 | 1466190000 ps | ||
| T65 | /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.856440441 | Aug 11 04:32:30 PM PDT 24 | Aug 11 04:32:38 PM PDT 24 | 1384970000 ps | ||
| T66 | /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.2040146306 | Aug 11 04:32:42 PM PDT 24 | Aug 11 04:32:51 PM PDT 24 | 1397690000 ps | ||
| T67 | /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.1998891464 | Aug 11 04:32:30 PM PDT 24 | Aug 11 04:32:37 PM PDT 24 | 1451470000 ps | ||
| T68 | /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.709398818 | Aug 11 04:32:31 PM PDT 24 | Aug 11 04:32:39 PM PDT 24 | 1567850000 ps | ||
| T69 | /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.859883406 | Aug 11 04:32:20 PM PDT 24 | Aug 11 04:32:28 PM PDT 24 | 1414590000 ps | ||
| T70 | /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.955855519 | Aug 11 04:32:32 PM PDT 24 | Aug 11 04:32:43 PM PDT 24 | 1528050000 ps | ||
| T14 | /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.945880183 | Aug 11 04:18:45 PM PDT 24 | Aug 11 04:51:17 PM PDT 24 | 336648470000 ps | ||
| T15 | /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.4244112247 | Aug 11 04:32:26 PM PDT 24 | Aug 11 05:01:43 PM PDT 24 | 336434090000 ps | ||
| T16 | /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.1332433802 | Aug 11 04:19:03 PM PDT 24 | Aug 11 04:48:21 PM PDT 24 | 336583050000 ps | ||
| T17 | /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.499932746 | Aug 11 04:23:31 PM PDT 24 | Aug 11 04:58:41 PM PDT 24 | 336616450000 ps | ||
| T18 | /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.3851114446 | Aug 11 04:32:14 PM PDT 24 | Aug 11 05:02:00 PM PDT 24 | 336480670000 ps | ||
| T19 | /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.1854141777 | Aug 11 04:23:39 PM PDT 24 | Aug 11 04:50:48 PM PDT 24 | 336835790000 ps | ||
| T20 | /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.984596270 | Aug 11 04:23:22 PM PDT 24 | Aug 11 04:56:32 PM PDT 24 | 336851070000 ps | ||
| T21 | /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.1005568871 | Aug 11 04:23:42 PM PDT 24 | Aug 11 04:53:10 PM PDT 24 | 336825150000 ps | ||
| T22 | /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.3226090656 | Aug 11 04:23:23 PM PDT 24 | Aug 11 04:54:40 PM PDT 24 | 336636230000 ps | ||
| T23 | /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.1231555462 | Aug 11 04:21:31 PM PDT 24 | Aug 11 04:58:46 PM PDT 24 | 336632490000 ps | ||
| T71 | /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.65423999 | Aug 11 04:18:58 PM PDT 24 | Aug 11 04:56:03 PM PDT 24 | 336880890000 ps | ||
| T72 | /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.194469691 | Aug 11 04:21:47 PM PDT 24 | Aug 11 04:57:45 PM PDT 24 | 336479370000 ps | ||
| T73 | /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.2271334772 | Aug 11 04:32:21 PM PDT 24 | Aug 11 05:07:01 PM PDT 24 | 336722290000 ps | ||
| T74 | /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.2725054683 | Aug 11 04:21:42 PM PDT 24 | Aug 11 04:50:38 PM PDT 24 | 336278770000 ps | ||
| T75 | /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.3881569018 | Aug 11 04:21:47 PM PDT 24 | Aug 11 04:57:49 PM PDT 24 | 336747950000 ps | ||
| T76 | /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.378115117 | Aug 11 04:23:32 PM PDT 24 | Aug 11 04:48:00 PM PDT 24 | 336407030000 ps | ||
| T77 | /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.1587176225 | Aug 11 04:23:24 PM PDT 24 | Aug 11 04:54:07 PM PDT 24 | 336797870000 ps | ||
| T78 | /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.3983386216 | Aug 11 04:19:57 PM PDT 24 | Aug 11 04:53:37 PM PDT 24 | 336753170000 ps | ||
| T79 | /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.3142117374 | Aug 11 04:32:15 PM PDT 24 | Aug 11 05:01:05 PM PDT 24 | 336402390000 ps | ||
| T80 | /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.3364787094 | Aug 11 04:21:47 PM PDT 24 | Aug 11 04:57:32 PM PDT 24 | 336653930000 ps | ||
| T81 | /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.3203000896 | Aug 11 04:32:14 PM PDT 24 | Aug 11 05:05:39 PM PDT 24 | 336935790000 ps | ||
| T82 | /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3957949986 | Aug 11 04:18:29 PM PDT 24 | Aug 11 04:52:49 PM PDT 24 | 337008890000 ps | ||
| T83 | /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.2980916963 | Aug 11 04:32:16 PM PDT 24 | Aug 11 05:01:46 PM PDT 24 | 336919630000 ps | ||
| T84 | /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.1115459163 | Aug 11 04:32:20 PM PDT 24 | Aug 11 05:02:40 PM PDT 24 | 336349150000 ps | ||
| T85 | /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.95195641 | Aug 11 04:23:27 PM PDT 24 | Aug 11 04:45:04 PM PDT 24 | 336662290000 ps | ||
| T86 | /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.2239560865 | Aug 11 04:23:39 PM PDT 24 | Aug 11 04:51:12 PM PDT 24 | 337120130000 ps | ||
| T87 | /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.2888773715 | Aug 11 04:32:34 PM PDT 24 | Aug 11 05:07:06 PM PDT 24 | 336528890000 ps | ||
| T88 | /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.2455424931 | Aug 11 04:23:31 PM PDT 24 | Aug 11 04:58:05 PM PDT 24 | 336451650000 ps | ||
| T89 | /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.903658410 | Aug 11 04:23:34 PM PDT 24 | Aug 11 04:53:26 PM PDT 24 | 336859230000 ps | ||
| T90 | /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.2490791138 | Aug 11 04:21:32 PM PDT 24 | Aug 11 04:53:49 PM PDT 24 | 336489190000 ps | ||
| T91 | /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.594283971 | Aug 11 04:32:13 PM PDT 24 | Aug 11 04:59:28 PM PDT 24 | 336680870000 ps | ||
| T92 | /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.1698532393 | Aug 11 04:19:12 PM PDT 24 | Aug 11 04:54:01 PM PDT 24 | 336367110000 ps | ||
| T93 | /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.4246455778 | Aug 11 04:23:22 PM PDT 24 | Aug 11 04:57:06 PM PDT 24 | 336606790000 ps | ||
| T94 | /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.3744050357 | Aug 11 04:23:42 PM PDT 24 | Aug 11 04:53:21 PM PDT 24 | 336629650000 ps | ||
| T95 | /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.3131438762 | Aug 11 04:32:25 PM PDT 24 | Aug 11 05:06:38 PM PDT 24 | 336653190000 ps | ||
| T96 | /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.1556550631 | Aug 11 04:19:35 PM PDT 24 | Aug 11 04:55:53 PM PDT 24 | 336651930000 ps | ||
| T97 | /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.3173338370 | Aug 11 04:32:14 PM PDT 24 | Aug 11 05:02:22 PM PDT 24 | 336765370000 ps | ||
| T98 | /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.2589953028 | Aug 11 04:20:09 PM PDT 24 | Aug 11 04:53:22 PM PDT 24 | 336690390000 ps | ||
| T99 | /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.48201850 | Aug 11 04:22:12 PM PDT 24 | Aug 11 04:59:06 PM PDT 24 | 336347310000 ps | ||
| T100 | /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.1713435806 | Aug 11 04:19:54 PM PDT 24 | Aug 11 04:56:41 PM PDT 24 | 336377070000 ps | ||
| T101 | /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.1438082012 | Aug 11 04:23:22 PM PDT 24 | Aug 11 04:57:13 PM PDT 24 | 336498910000 ps | ||
| T102 | /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.450867745 | Aug 11 04:32:22 PM PDT 24 | Aug 11 05:07:43 PM PDT 24 | 336782470000 ps | ||
| T103 | /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.1984994458 | Aug 11 04:32:22 PM PDT 24 | Aug 11 05:02:10 PM PDT 24 | 337038870000 ps | ||
| T104 | /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.3163578465 | Aug 11 04:23:24 PM PDT 24 | Aug 11 04:54:17 PM PDT 24 | 336726010000 ps | ||
| T105 | /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.2196596188 | Aug 11 04:20:47 PM PDT 24 | Aug 11 04:55:41 PM PDT 24 | 336741570000 ps | ||
| T106 | /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.767483288 | Aug 11 04:32:18 PM PDT 24 | Aug 11 05:02:10 PM PDT 24 | 336490390000 ps | ||
| T107 | /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.2755214981 | Aug 11 04:32:13 PM PDT 24 | Aug 11 05:04:03 PM PDT 24 | 337089310000 ps | ||
| T108 | /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.2228314785 | Aug 11 04:23:23 PM PDT 24 | Aug 11 04:54:52 PM PDT 24 | 337107310000 ps | ||
| T109 | /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.3373374572 | Aug 11 04:20:33 PM PDT 24 | Aug 11 04:44:50 PM PDT 24 | 337067030000 ps | ||
| T110 | /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.1298240873 | Aug 11 04:18:13 PM PDT 24 | Aug 11 04:51:25 PM PDT 24 | 336867770000 ps | ||
| T4 | /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.2036381870 | Aug 11 04:32:35 PM PDT 24 | Aug 11 05:01:51 PM PDT 24 | 336769530000 ps | ||
| T5 | /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.512046129 | Aug 11 04:32:21 PM PDT 24 | Aug 11 05:07:42 PM PDT 24 | 336993730000 ps | ||
| T6 | /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.1379703629 | Aug 11 04:32:19 PM PDT 24 | Aug 11 05:08:18 PM PDT 24 | 336828490000 ps | ||
| T24 | /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.3836830826 | Aug 11 04:32:11 PM PDT 24 | Aug 11 05:05:20 PM PDT 24 | 336789590000 ps | ||
| T25 | /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.1789081582 | Aug 11 04:32:19 PM PDT 24 | Aug 11 05:07:49 PM PDT 24 | 336803330000 ps | ||
| T26 | /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.430663861 | Aug 11 04:32:19 PM PDT 24 | Aug 11 04:57:09 PM PDT 24 | 336771130000 ps | ||
| T27 | /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.1983653460 | Aug 11 04:32:17 PM PDT 24 | Aug 11 04:58:22 PM PDT 24 | 337058350000 ps | ||
| T28 | /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.396946459 | Aug 11 04:32:24 PM PDT 24 | Aug 11 05:00:49 PM PDT 24 | 337121790000 ps | ||
| T29 | /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.2378113047 | Aug 11 04:32:18 PM PDT 24 | Aug 11 04:58:18 PM PDT 24 | 336374210000 ps | ||
| T30 | /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.2356520888 | Aug 11 04:32:19 PM PDT 24 | Aug 11 05:07:40 PM PDT 24 | 336907270000 ps | ||
| T111 | /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.1594675803 | Aug 11 04:32:15 PM PDT 24 | Aug 11 05:03:02 PM PDT 24 | 336396850000 ps | ||
| T112 | /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1462380254 | Aug 11 04:32:28 PM PDT 24 | Aug 11 05:02:10 PM PDT 24 | 336516350000 ps | ||
| T113 | /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.1322484313 | Aug 11 04:32:12 PM PDT 24 | Aug 11 05:07:53 PM PDT 24 | 336704730000 ps | ||
| T114 | /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.2774488596 | Aug 11 04:32:26 PM PDT 24 | Aug 11 05:02:40 PM PDT 24 | 337063810000 ps | ||
| T115 | /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.4123590888 | Aug 11 04:32:36 PM PDT 24 | Aug 11 05:02:30 PM PDT 24 | 336808570000 ps | ||
| T116 | /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.3321952429 | Aug 11 04:32:17 PM PDT 24 | Aug 11 05:03:33 PM PDT 24 | 336545530000 ps | ||
| T117 | /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.729360438 | Aug 11 04:32:56 PM PDT 24 | Aug 11 05:05:08 PM PDT 24 | 336669510000 ps | ||
| T118 | /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.3568680110 | Aug 11 04:32:29 PM PDT 24 | Aug 11 05:10:57 PM PDT 24 | 336660630000 ps | ||
| T119 | /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.1154040112 | Aug 11 04:32:16 PM PDT 24 | Aug 11 05:03:00 PM PDT 24 | 336650090000 ps | ||
| T120 | /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.2154408057 | Aug 11 04:32:27 PM PDT 24 | Aug 11 05:04:18 PM PDT 24 | 336800370000 ps | ||
| T121 | /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.1880846761 | Aug 11 04:32:32 PM PDT 24 | Aug 11 05:08:31 PM PDT 24 | 336719190000 ps | ||
| T122 | /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.3891676562 | Aug 11 04:32:26 PM PDT 24 | Aug 11 05:07:56 PM PDT 24 | 337016990000 ps | ||
| T123 | /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.2362244969 | Aug 11 04:32:21 PM PDT 24 | Aug 11 05:01:29 PM PDT 24 | 336658810000 ps | ||
| T124 | /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.460536541 | Aug 11 04:32:28 PM PDT 24 | Aug 11 05:05:38 PM PDT 24 | 336392410000 ps | ||
| T125 | /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.4210116104 | Aug 11 04:32:18 PM PDT 24 | Aug 11 05:08:43 PM PDT 24 | 336587910000 ps | ||
| T126 | /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.3498293047 | Aug 11 04:32:28 PM PDT 24 | Aug 11 04:59:43 PM PDT 24 | 336452150000 ps | ||
| T127 | /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.3857172432 | Aug 11 04:32:23 PM PDT 24 | Aug 11 05:07:49 PM PDT 24 | 336442010000 ps | ||
| T128 | /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.3088514281 | Aug 11 04:32:35 PM PDT 24 | Aug 11 05:07:25 PM PDT 24 | 336467790000 ps | ||
| T129 | /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.162660852 | Aug 11 04:32:29 PM PDT 24 | Aug 11 05:09:15 PM PDT 24 | 337059410000 ps | ||
| T130 | /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.2546287363 | Aug 11 04:32:14 PM PDT 24 | Aug 11 05:09:11 PM PDT 24 | 336915470000 ps | ||
| T131 | /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.4130839805 | Aug 11 04:32:25 PM PDT 24 | Aug 11 05:10:39 PM PDT 24 | 336901750000 ps | ||
| T132 | /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.3013025847 | Aug 11 04:32:12 PM PDT 24 | Aug 11 05:01:30 PM PDT 24 | 336573830000 ps | ||
| T133 | /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.4184955821 | Aug 11 04:32:30 PM PDT 24 | Aug 11 05:05:56 PM PDT 24 | 336597850000 ps | ||
| T134 | /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.461844941 | Aug 11 04:32:12 PM PDT 24 | Aug 11 05:02:44 PM PDT 24 | 336675550000 ps | ||
| T135 | /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.2569003146 | Aug 11 04:32:37 PM PDT 24 | Aug 11 05:07:14 PM PDT 24 | 336367410000 ps | ||
| T136 | /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1899009485 | Aug 11 04:32:20 PM PDT 24 | Aug 11 04:59:12 PM PDT 24 | 336544090000 ps | ||
| T137 | /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.3375086119 | Aug 11 04:32:35 PM PDT 24 | Aug 11 05:06:02 PM PDT 24 | 336653410000 ps | ||
| T138 | /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.4062640181 | Aug 11 04:32:19 PM PDT 24 | Aug 11 05:08:53 PM PDT 24 | 336762430000 ps | ||
| T139 | /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.950989115 | Aug 11 04:32:14 PM PDT 24 | Aug 11 04:59:37 PM PDT 24 | 337108510000 ps | ||
| T140 | /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.3440612749 | Aug 11 04:32:31 PM PDT 24 | Aug 11 05:09:41 PM PDT 24 | 336355130000 ps | ||
| T141 | /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.2757896208 | Aug 11 04:32:22 PM PDT 24 | Aug 11 05:06:34 PM PDT 24 | 336942050000 ps | ||
| T142 | /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.2785844097 | Aug 11 04:32:15 PM PDT 24 | Aug 11 05:00:27 PM PDT 24 | 336943070000 ps | ||
| T143 | /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.3524800232 | Aug 11 04:32:19 PM PDT 24 | Aug 11 05:06:01 PM PDT 24 | 336581510000 ps | ||
| T144 | /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.2785007121 | Aug 11 04:32:22 PM PDT 24 | Aug 11 04:57:35 PM PDT 24 | 336880710000 ps | ||
| T145 | /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.1380426382 | Aug 11 04:32:20 PM PDT 24 | Aug 11 05:06:29 PM PDT 24 | 337031150000 ps | ||
| T146 | /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.3385744822 | Aug 11 04:32:33 PM PDT 24 | Aug 11 05:09:24 PM PDT 24 | 336914190000 ps | ||
| T147 | /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.3262298849 | Aug 11 04:32:24 PM PDT 24 | Aug 11 05:08:05 PM PDT 24 | 336952190000 ps | ||
| T148 | /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.1707536754 | Aug 11 04:32:11 PM PDT 24 | Aug 11 05:06:39 PM PDT 24 | 336825230000 ps | ||
| T149 | /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.3037590485 | Aug 11 04:32:21 PM PDT 24 | Aug 11 04:56:45 PM PDT 24 | 336532550000 ps | ||
| T150 | /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.958242611 | Aug 11 04:32:18 PM PDT 24 | Aug 11 05:01:52 PM PDT 24 | 336906030000 ps | ||
| T151 | /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2171490827 | Aug 11 05:35:48 PM PDT 24 | Aug 11 05:35:58 PM PDT 24 | 1453070000 ps | ||
| T152 | /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.1655776278 | Aug 11 05:35:46 PM PDT 24 | Aug 11 05:35:57 PM PDT 24 | 1562990000 ps | ||
| T153 | /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.3446472512 | Aug 11 05:35:47 PM PDT 24 | Aug 11 05:35:58 PM PDT 24 | 1591530000 ps | ||
| T154 | /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.2206745242 | Aug 11 05:35:46 PM PDT 24 | Aug 11 05:35:55 PM PDT 24 | 1477530000 ps | ||
| T155 | /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.3083688060 | Aug 11 05:35:39 PM PDT 24 | Aug 11 05:35:48 PM PDT 24 | 1424510000 ps | ||
| T156 | /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.678067835 | Aug 11 05:35:38 PM PDT 24 | Aug 11 05:35:47 PM PDT 24 | 1432610000 ps | ||
| T157 | /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.3266026648 | Aug 11 05:35:44 PM PDT 24 | Aug 11 05:35:53 PM PDT 24 | 1512730000 ps | ||
| T158 | /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.547548388 | Aug 11 05:35:42 PM PDT 24 | Aug 11 05:35:53 PM PDT 24 | 1540450000 ps | ||
| T159 | /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.3225840823 | Aug 11 05:35:41 PM PDT 24 | Aug 11 05:35:53 PM PDT 24 | 1466850000 ps | ||
| T160 | /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2479651307 | Aug 11 05:35:38 PM PDT 24 | Aug 11 05:35:45 PM PDT 24 | 1264290000 ps | ||
| T161 | /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.3571430296 | Aug 11 05:35:38 PM PDT 24 | Aug 11 05:35:48 PM PDT 24 | 1284730000 ps | ||
| T162 | /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.3067047193 | Aug 11 05:35:46 PM PDT 24 | Aug 11 05:35:55 PM PDT 24 | 1070150000 ps | ||
| T163 | /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.420065535 | Aug 11 05:35:49 PM PDT 24 | Aug 11 05:35:58 PM PDT 24 | 1381510000 ps | ||
| T164 | /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.2482885486 | Aug 11 05:35:47 PM PDT 24 | Aug 11 05:35:56 PM PDT 24 | 1436530000 ps | ||
| T165 | /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.1140705953 | Aug 11 05:35:46 PM PDT 24 | Aug 11 05:35:57 PM PDT 24 | 1567690000 ps | ||
| T166 | /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.364110029 | Aug 11 05:35:41 PM PDT 24 | Aug 11 05:35:53 PM PDT 24 | 1503870000 ps | ||
| T167 | /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.4003845370 | Aug 11 05:35:39 PM PDT 24 | Aug 11 05:35:46 PM PDT 24 | 1007210000 ps | ||
| T168 | /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.2356618961 | Aug 11 05:35:44 PM PDT 24 | Aug 11 05:35:52 PM PDT 24 | 1163570000 ps | ||
| T169 | /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.3533276716 | Aug 11 05:35:38 PM PDT 24 | Aug 11 05:35:45 PM PDT 24 | 1384430000 ps | ||
| T170 | /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.396709965 | Aug 11 05:35:48 PM PDT 24 | Aug 11 05:35:56 PM PDT 24 | 1450790000 ps | ||
| T171 | /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.195760248 | Aug 11 05:35:44 PM PDT 24 | Aug 11 05:35:55 PM PDT 24 | 1451370000 ps | ||
| T172 | /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.122746873 | Aug 11 05:35:45 PM PDT 24 | Aug 11 05:35:57 PM PDT 24 | 1534110000 ps | ||
| T173 | /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.2860164181 | Aug 11 05:35:44 PM PDT 24 | Aug 11 05:35:53 PM PDT 24 | 1281390000 ps | ||
| T174 | /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3447449961 | Aug 11 05:35:43 PM PDT 24 | Aug 11 05:35:53 PM PDT 24 | 1462010000 ps | ||
| T175 | /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.3040224804 | Aug 11 05:35:41 PM PDT 24 | Aug 11 05:35:51 PM PDT 24 | 1521490000 ps | ||
| T176 | /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.3037843402 | Aug 11 05:35:48 PM PDT 24 | Aug 11 05:35:58 PM PDT 24 | 1545190000 ps | ||
| T177 | /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.1411161637 | Aug 11 05:35:37 PM PDT 24 | Aug 11 05:35:50 PM PDT 24 | 1531570000 ps | ||
| T178 | /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.2013783844 | Aug 11 05:35:47 PM PDT 24 | Aug 11 05:35:58 PM PDT 24 | 1424710000 ps | ||
| T179 | /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.805763181 | Aug 11 05:35:44 PM PDT 24 | Aug 11 05:35:52 PM PDT 24 | 1415730000 ps | ||
| T180 | /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.3981455511 | Aug 11 05:35:49 PM PDT 24 | Aug 11 05:35:57 PM PDT 24 | 1346410000 ps | ||
| T181 | /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.3128424139 | Aug 11 05:35:42 PM PDT 24 | Aug 11 05:35:52 PM PDT 24 | 1339930000 ps | ||
| T182 | /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.2069461319 | Aug 11 05:35:38 PM PDT 24 | Aug 11 05:35:49 PM PDT 24 | 1563110000 ps | ||
| T183 | /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.798895769 | Aug 11 05:35:42 PM PDT 24 | Aug 11 05:35:53 PM PDT 24 | 1488970000 ps | ||
| T184 | /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.1531299545 | Aug 11 05:35:38 PM PDT 24 | Aug 11 05:35:50 PM PDT 24 | 1558070000 ps | ||
| T185 | /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.396154987 | Aug 11 05:35:47 PM PDT 24 | Aug 11 05:35:57 PM PDT 24 | 1357170000 ps | ||
| T186 | /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.2065947793 | Aug 11 05:35:36 PM PDT 24 | Aug 11 05:35:46 PM PDT 24 | 1519770000 ps | ||
| T187 | /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.4087445990 | Aug 11 05:35:47 PM PDT 24 | Aug 11 05:35:57 PM PDT 24 | 1470450000 ps | ||
| T188 | /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.1642318611 | Aug 11 05:35:42 PM PDT 24 | Aug 11 05:35:54 PM PDT 24 | 1492410000 ps | ||
| T189 | /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.2190096922 | Aug 11 05:35:47 PM PDT 24 | Aug 11 05:35:57 PM PDT 24 | 1479950000 ps | ||
| T190 | /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1265012774 | Aug 11 05:35:45 PM PDT 24 | Aug 11 05:35:55 PM PDT 24 | 1337130000 ps | ||
| T191 | /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.2517695081 | Aug 11 05:35:45 PM PDT 24 | Aug 11 05:35:56 PM PDT 24 | 1477650000 ps | ||
| T192 | /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.3639380483 | Aug 11 05:35:46 PM PDT 24 | Aug 11 05:35:57 PM PDT 24 | 1535790000 ps | ||
| T193 | /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.2136266006 | Aug 11 05:35:49 PM PDT 24 | Aug 11 05:35:56 PM PDT 24 | 1149050000 ps | ||
| T194 | /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.769104548 | Aug 11 05:35:41 PM PDT 24 | Aug 11 05:35:49 PM PDT 24 | 1547270000 ps | ||
| T195 | /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.2914777635 | Aug 11 05:35:40 PM PDT 24 | Aug 11 05:35:49 PM PDT 24 | 1488290000 ps | ||
| T196 | /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.289179793 | Aug 11 05:35:42 PM PDT 24 | Aug 11 05:35:49 PM PDT 24 | 1468330000 ps | ||
| T197 | /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.3624629292 | Aug 11 05:35:43 PM PDT 24 | Aug 11 05:35:49 PM PDT 24 | 1266150000 ps | ||
| T198 | /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.2263860700 | Aug 11 05:35:44 PM PDT 24 | Aug 11 05:35:55 PM PDT 24 | 1515170000 ps | ||
| T199 | /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.2826644324 | Aug 11 05:35:39 PM PDT 24 | Aug 11 05:35:51 PM PDT 24 | 1440130000 ps | ||
| T200 | /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.3076642022 | Aug 11 05:35:45 PM PDT 24 | Aug 11 05:35:52 PM PDT 24 | 1417790000 ps |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.1895119420 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 1354710000 ps |
| CPU time | 3.56 seconds |
| Started | Aug 11 04:32:31 PM PDT 24 |
| Finished | Aug 11 04:32:39 PM PDT 24 |
| Peak memory | 164732 kb |
| Host | smart-7fd28525-6403-42ba-909d-0cab4c483cdb |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1895119420 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.1895119420 |
| Directory | /workspace/15.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.3226090656 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 336636230000 ps |
| CPU time | 757.83 seconds |
| Started | Aug 11 04:23:23 PM PDT 24 |
| Finished | Aug 11 04:54:40 PM PDT 24 |
| Peak memory | 159480 kb |
| Host | smart-48464aca-b622-420f-a67a-a6b727fcafe9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3226090656 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.3226090656 |
| Directory | /workspace/0.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.1789081582 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 336803330000 ps |
| CPU time | 849.3 seconds |
| Started | Aug 11 04:32:19 PM PDT 24 |
| Finished | Aug 11 05:07:49 PM PDT 24 |
| Peak memory | 160696 kb |
| Host | smart-9ad841c9-6a79-4a32-9f59-3cf7c05f0a6b |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1789081582 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.1789081582 |
| Directory | /workspace/1.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.4123590888 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 336808570000 ps |
| CPU time | 720.43 seconds |
| Started | Aug 11 04:32:36 PM PDT 24 |
| Finished | Aug 11 05:02:30 PM PDT 24 |
| Peak memory | 160680 kb |
| Host | smart-07999d23-2072-4768-b821-5b668f8a7c79 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4123590888 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.4123590888 |
| Directory | /workspace/0.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.3568680110 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 336660630000 ps |
| CPU time | 947.73 seconds |
| Started | Aug 11 04:32:29 PM PDT 24 |
| Finished | Aug 11 05:10:57 PM PDT 24 |
| Peak memory | 160692 kb |
| Host | smart-3f11c79c-9115-4d9c-968d-84e92828d8b9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3568680110 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.3568680110 |
| Directory | /workspace/10.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.162660852 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 337059410000 ps |
| CPU time | 900.86 seconds |
| Started | Aug 11 04:32:29 PM PDT 24 |
| Finished | Aug 11 05:09:15 PM PDT 24 |
| Peak memory | 160680 kb |
| Host | smart-1801ebc4-a763-45c4-9c9f-4d932844440c |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=162660852 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.162660852 |
| Directory | /workspace/11.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.3498293047 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 336452150000 ps |
| CPU time | 662.39 seconds |
| Started | Aug 11 04:32:28 PM PDT 24 |
| Finished | Aug 11 04:59:43 PM PDT 24 |
| Peak memory | 160708 kb |
| Host | smart-260b2e18-bcbe-46b3-b75a-445e05dd9b5f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3498293047 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.3498293047 |
| Directory | /workspace/12.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.4130839805 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 336901750000 ps |
| CPU time | 944.8 seconds |
| Started | Aug 11 04:32:25 PM PDT 24 |
| Finished | Aug 11 05:10:39 PM PDT 24 |
| Peak memory | 160692 kb |
| Host | smart-664e4f29-86cf-40b4-888d-207470cb761a |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4130839805 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.4130839805 |
| Directory | /workspace/13.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.1379703629 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 336828490000 ps |
| CPU time | 877.15 seconds |
| Started | Aug 11 04:32:19 PM PDT 24 |
| Finished | Aug 11 05:08:18 PM PDT 24 |
| Peak memory | 160644 kb |
| Host | smart-07b99b66-14dc-423c-a588-9f82d64b72dd |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1379703629 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.1379703629 |
| Directory | /workspace/14.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.2757896208 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 336942050000 ps |
| CPU time | 824.07 seconds |
| Started | Aug 11 04:32:22 PM PDT 24 |
| Finished | Aug 11 05:06:34 PM PDT 24 |
| Peak memory | 160692 kb |
| Host | smart-67c95877-c96a-442f-871e-c96d1918b2d5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2757896208 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.2757896208 |
| Directory | /workspace/15.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.4062640181 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 336762430000 ps |
| CPU time | 886.33 seconds |
| Started | Aug 11 04:32:19 PM PDT 24 |
| Finished | Aug 11 05:08:53 PM PDT 24 |
| Peak memory | 160704 kb |
| Host | smart-38d1c5dc-a25e-45d3-96ef-93a0d4c932eb |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4062640181 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.4062640181 |
| Directory | /workspace/16.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.1707536754 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 336825230000 ps |
| CPU time | 845.38 seconds |
| Started | Aug 11 04:32:11 PM PDT 24 |
| Finished | Aug 11 05:06:39 PM PDT 24 |
| Peak memory | 160680 kb |
| Host | smart-e8d61b2a-7c98-4d0b-9cf0-601eed1c4eb3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1707536754 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.1707536754 |
| Directory | /workspace/17.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.512046129 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 336993730000 ps |
| CPU time | 848.47 seconds |
| Started | Aug 11 04:32:21 PM PDT 24 |
| Finished | Aug 11 05:07:42 PM PDT 24 |
| Peak memory | 160692 kb |
| Host | smart-9db17255-a7f1-4707-8022-244786ecfa12 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=512046129 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.512046129 |
| Directory | /workspace/18.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.1322484313 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 336704730000 ps |
| CPU time | 880.48 seconds |
| Started | Aug 11 04:32:12 PM PDT 24 |
| Finished | Aug 11 05:07:53 PM PDT 24 |
| Peak memory | 160676 kb |
| Host | smart-be270153-880f-4dbd-abe7-5ed2726dbcb2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1322484313 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.1322484313 |
| Directory | /workspace/19.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.729360438 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 336669510000 ps |
| CPU time | 783.22 seconds |
| Started | Aug 11 04:32:56 PM PDT 24 |
| Finished | Aug 11 05:05:08 PM PDT 24 |
| Peak memory | 160724 kb |
| Host | smart-1885003d-1646-417c-a50b-817c36f62ecb |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=729360438 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.729360438 |
| Directory | /workspace/2.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.2785844097 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 336943070000 ps |
| CPU time | 688.74 seconds |
| Started | Aug 11 04:32:15 PM PDT 24 |
| Finished | Aug 11 05:00:27 PM PDT 24 |
| Peak memory | 160644 kb |
| Host | smart-a9502fdb-2574-49ba-bcd9-3b0dd4a49665 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2785844097 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.2785844097 |
| Directory | /workspace/20.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.430663861 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 336771130000 ps |
| CPU time | 575.76 seconds |
| Started | Aug 11 04:32:19 PM PDT 24 |
| Finished | Aug 11 04:57:09 PM PDT 24 |
| Peak memory | 159756 kb |
| Host | smart-f40a0421-3aa4-4466-8389-c57832709450 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=430663861 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.430663861 |
| Directory | /workspace/21.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.950989115 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 337108510000 ps |
| CPU time | 661.04 seconds |
| Started | Aug 11 04:32:14 PM PDT 24 |
| Finished | Aug 11 04:59:37 PM PDT 24 |
| Peak memory | 160696 kb |
| Host | smart-69b6383d-799f-47ef-9132-c2eac44ce912 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=950989115 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.950989115 |
| Directory | /workspace/22.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.2356520888 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 336907270000 ps |
| CPU time | 867.78 seconds |
| Started | Aug 11 04:32:19 PM PDT 24 |
| Finished | Aug 11 05:07:40 PM PDT 24 |
| Peak memory | 160688 kb |
| Host | smart-c036a24f-086b-40ed-a7d4-85d6d9be31a4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2356520888 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.2356520888 |
| Directory | /workspace/23.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.3088514281 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 336467790000 ps |
| CPU time | 865.93 seconds |
| Started | Aug 11 04:32:35 PM PDT 24 |
| Finished | Aug 11 05:07:25 PM PDT 24 |
| Peak memory | 160692 kb |
| Host | smart-9118934a-30ef-4bb6-ab12-396fd4082e08 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3088514281 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.3088514281 |
| Directory | /workspace/24.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.1594675803 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 336396850000 ps |
| CPU time | 758.99 seconds |
| Started | Aug 11 04:32:15 PM PDT 24 |
| Finished | Aug 11 05:03:02 PM PDT 24 |
| Peak memory | 160704 kb |
| Host | smart-025a6f03-d803-4868-9d03-3465d43e6651 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1594675803 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.1594675803 |
| Directory | /workspace/25.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1899009485 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 336544090000 ps |
| CPU time | 648.84 seconds |
| Started | Aug 11 04:32:20 PM PDT 24 |
| Finished | Aug 11 04:59:12 PM PDT 24 |
| Peak memory | 160696 kb |
| Host | smart-1c92b355-da20-4bf7-aeaa-a27fbdc59d6a |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1899009485 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.1899009485 |
| Directory | /workspace/26.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.3321952429 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 336545530000 ps |
| CPU time | 768.05 seconds |
| Started | Aug 11 04:32:17 PM PDT 24 |
| Finished | Aug 11 05:03:33 PM PDT 24 |
| Peak memory | 160660 kb |
| Host | smart-db89c95d-f62e-4834-8efe-8cd6db92abb6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3321952429 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.3321952429 |
| Directory | /workspace/27.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.3440612749 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 336355130000 ps |
| CPU time | 907.8 seconds |
| Started | Aug 11 04:32:31 PM PDT 24 |
| Finished | Aug 11 05:09:41 PM PDT 24 |
| Peak memory | 160672 kb |
| Host | smart-5aca30ff-1164-4636-9ba8-ce7154a41e3b |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3440612749 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.3440612749 |
| Directory | /workspace/28.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.1154040112 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 336650090000 ps |
| CPU time | 758.08 seconds |
| Started | Aug 11 04:32:16 PM PDT 24 |
| Finished | Aug 11 05:03:00 PM PDT 24 |
| Peak memory | 160740 kb |
| Host | smart-425baa99-5b26-4a26-aa43-3a68a76c7eee |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1154040112 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.1154040112 |
| Directory | /workspace/29.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.4184955821 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 336597850000 ps |
| CPU time | 826.25 seconds |
| Started | Aug 11 04:32:30 PM PDT 24 |
| Finished | Aug 11 05:05:56 PM PDT 24 |
| Peak memory | 160696 kb |
| Host | smart-0587b538-d19a-4795-a7f1-29198c8bc3d3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4184955821 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.4184955821 |
| Directory | /workspace/3.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.461844941 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 336675550000 ps |
| CPU time | 751.09 seconds |
| Started | Aug 11 04:32:12 PM PDT 24 |
| Finished | Aug 11 05:02:44 PM PDT 24 |
| Peak memory | 160680 kb |
| Host | smart-e677cb68-cb68-4af5-945a-18e2bd0d60ea |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=461844941 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.461844941 |
| Directory | /workspace/30.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.3385744822 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 336914190000 ps |
| CPU time | 890.37 seconds |
| Started | Aug 11 04:32:33 PM PDT 24 |
| Finished | Aug 11 05:09:24 PM PDT 24 |
| Peak memory | 160704 kb |
| Host | smart-df4c2be0-c8f8-4c22-ac71-34f9f2a6f0a4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3385744822 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.3385744822 |
| Directory | /workspace/31.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.2546287363 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 336915470000 ps |
| CPU time | 906.56 seconds |
| Started | Aug 11 04:32:14 PM PDT 24 |
| Finished | Aug 11 05:09:11 PM PDT 24 |
| Peak memory | 160672 kb |
| Host | smart-a4c49c09-ac0e-49a2-b29c-32294f57f4e3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2546287363 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.2546287363 |
| Directory | /workspace/32.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.3262298849 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 336952190000 ps |
| CPU time | 867.54 seconds |
| Started | Aug 11 04:32:24 PM PDT 24 |
| Finished | Aug 11 05:08:05 PM PDT 24 |
| Peak memory | 160692 kb |
| Host | smart-1c37c770-1cb0-4a1a-875c-be2dfe3da964 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3262298849 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.3262298849 |
| Directory | /workspace/33.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.1880846761 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 336719190000 ps |
| CPU time | 871.98 seconds |
| Started | Aug 11 04:32:32 PM PDT 24 |
| Finished | Aug 11 05:08:31 PM PDT 24 |
| Peak memory | 160644 kb |
| Host | smart-d23d89ac-6813-49f3-840b-e5b35e95f82d |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1880846761 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.1880846761 |
| Directory | /workspace/34.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.4210116104 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 336587910000 ps |
| CPU time | 879.98 seconds |
| Started | Aug 11 04:32:18 PM PDT 24 |
| Finished | Aug 11 05:08:43 PM PDT 24 |
| Peak memory | 160704 kb |
| Host | smart-875df074-055b-464d-8030-8ec3bc94c7c0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4210116104 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.4210116104 |
| Directory | /workspace/35.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.1983653460 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 337058350000 ps |
| CPU time | 634.86 seconds |
| Started | Aug 11 04:32:17 PM PDT 24 |
| Finished | Aug 11 04:58:22 PM PDT 24 |
| Peak memory | 160704 kb |
| Host | smart-08bb9d67-c6fb-4796-bbea-e36645bf40db |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1983653460 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.1983653460 |
| Directory | /workspace/36.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.460536541 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 336392410000 ps |
| CPU time | 825.56 seconds |
| Started | Aug 11 04:32:28 PM PDT 24 |
| Finished | Aug 11 05:05:38 PM PDT 24 |
| Peak memory | 160740 kb |
| Host | smart-990101fd-7bd9-461f-b74e-bda9d966d5db |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=460536541 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.460536541 |
| Directory | /workspace/37.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.3836830826 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 336789590000 ps |
| CPU time | 822.89 seconds |
| Started | Aug 11 04:32:11 PM PDT 24 |
| Finished | Aug 11 05:05:20 PM PDT 24 |
| Peak memory | 160660 kb |
| Host | smart-38a3ccf5-e312-4f61-8d90-23f6e667fff2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3836830826 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.3836830826 |
| Directory | /workspace/38.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.3013025847 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 336573830000 ps |
| CPU time | 716.62 seconds |
| Started | Aug 11 04:32:12 PM PDT 24 |
| Finished | Aug 11 05:01:30 PM PDT 24 |
| Peak memory | 160708 kb |
| Host | smart-65730b88-8a75-4610-abb0-e107ac3eb417 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3013025847 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.3013025847 |
| Directory | /workspace/39.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.1380426382 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 337031150000 ps |
| CPU time | 835.02 seconds |
| Started | Aug 11 04:32:20 PM PDT 24 |
| Finished | Aug 11 05:06:29 PM PDT 24 |
| Peak memory | 160784 kb |
| Host | smart-6ee7a7c2-26ca-4c24-899d-983e6ebfc6c1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1380426382 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.1380426382 |
| Directory | /workspace/4.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.2362244969 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 336658810000 ps |
| CPU time | 719.76 seconds |
| Started | Aug 11 04:32:21 PM PDT 24 |
| Finished | Aug 11 05:01:29 PM PDT 24 |
| Peak memory | 160676 kb |
| Host | smart-632b5886-120e-4393-8e9e-054e0f0d78d4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2362244969 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.2362244969 |
| Directory | /workspace/40.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.3524800232 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 336581510000 ps |
| CPU time | 825.28 seconds |
| Started | Aug 11 04:32:19 PM PDT 24 |
| Finished | Aug 11 05:06:01 PM PDT 24 |
| Peak memory | 160792 kb |
| Host | smart-07dbb054-2569-4a11-9da1-8abeb19d8fe4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3524800232 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.3524800232 |
| Directory | /workspace/41.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.2774488596 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 337063810000 ps |
| CPU time | 748.97 seconds |
| Started | Aug 11 04:32:26 PM PDT 24 |
| Finished | Aug 11 05:02:40 PM PDT 24 |
| Peak memory | 160700 kb |
| Host | smart-9f54edfa-56d5-4554-acb5-d67bf20807f8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2774488596 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.2774488596 |
| Directory | /workspace/42.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.958242611 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 336906030000 ps |
| CPU time | 730.43 seconds |
| Started | Aug 11 04:32:18 PM PDT 24 |
| Finished | Aug 11 05:01:52 PM PDT 24 |
| Peak memory | 160644 kb |
| Host | smart-51e79fb2-fd18-42aa-a5ea-7c8449f47888 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=958242611 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.958242611 |
| Directory | /workspace/43.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.2785007121 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 336880710000 ps |
| CPU time | 620.02 seconds |
| Started | Aug 11 04:32:22 PM PDT 24 |
| Finished | Aug 11 04:57:35 PM PDT 24 |
| Peak memory | 160720 kb |
| Host | smart-af2502f0-6cd0-4274-abd2-7804950b4850 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2785007121 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.2785007121 |
| Directory | /workspace/44.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.2154408057 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 336800370000 ps |
| CPU time | 791.56 seconds |
| Started | Aug 11 04:32:27 PM PDT 24 |
| Finished | Aug 11 05:04:18 PM PDT 24 |
| Peak memory | 160692 kb |
| Host | smart-1bc522ee-c394-43cc-8f1c-73f79f785ec2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2154408057 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.2154408057 |
| Directory | /workspace/45.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.3037590485 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 336532550000 ps |
| CPU time | 587.87 seconds |
| Started | Aug 11 04:32:21 PM PDT 24 |
| Finished | Aug 11 04:56:45 PM PDT 24 |
| Peak memory | 160656 kb |
| Host | smart-90228550-08ca-4534-b04a-bc8712832ad6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3037590485 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.3037590485 |
| Directory | /workspace/46.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.3857172432 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 336442010000 ps |
| CPU time | 860.22 seconds |
| Started | Aug 11 04:32:23 PM PDT 24 |
| Finished | Aug 11 05:07:49 PM PDT 24 |
| Peak memory | 160644 kb |
| Host | smart-8d3ebf4b-dc9a-4362-ac33-1b967262028b |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3857172432 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.3857172432 |
| Directory | /workspace/47.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.396946459 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 337121790000 ps |
| CPU time | 702.51 seconds |
| Started | Aug 11 04:32:24 PM PDT 24 |
| Finished | Aug 11 05:00:49 PM PDT 24 |
| Peak memory | 160676 kb |
| Host | smart-3e7553ec-b4e9-41e1-8bc3-109c6d7ec6c5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=396946459 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.396946459 |
| Directory | /workspace/48.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.2036381870 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 336769530000 ps |
| CPU time | 716.41 seconds |
| Started | Aug 11 04:32:35 PM PDT 24 |
| Finished | Aug 11 05:01:51 PM PDT 24 |
| Peak memory | 160704 kb |
| Host | smart-3f3ea635-4170-4dbc-9703-94f7499cf76f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2036381870 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.2036381870 |
| Directory | /workspace/49.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.2569003146 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 336367410000 ps |
| CPU time | 862.06 seconds |
| Started | Aug 11 04:32:37 PM PDT 24 |
| Finished | Aug 11 05:07:14 PM PDT 24 |
| Peak memory | 160668 kb |
| Host | smart-ccbbd3c9-e71c-49f6-a170-acd4f20ef82a |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2569003146 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.2569003146 |
| Directory | /workspace/5.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.3375086119 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 336653410000 ps |
| CPU time | 824.74 seconds |
| Started | Aug 11 04:32:35 PM PDT 24 |
| Finished | Aug 11 05:06:02 PM PDT 24 |
| Peak memory | 160696 kb |
| Host | smart-925aed85-1520-4090-8d52-3179f73de225 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3375086119 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.3375086119 |
| Directory | /workspace/6.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.3891676562 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 337016990000 ps |
| CPU time | 864.12 seconds |
| Started | Aug 11 04:32:26 PM PDT 24 |
| Finished | Aug 11 05:07:56 PM PDT 24 |
| Peak memory | 160680 kb |
| Host | smart-3e2f93b7-a62a-40b0-8442-3f5667ece0dd |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3891676562 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.3891676562 |
| Directory | /workspace/7.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1462380254 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 336516350000 ps |
| CPU time | 717.94 seconds |
| Started | Aug 11 04:32:28 PM PDT 24 |
| Finished | Aug 11 05:02:10 PM PDT 24 |
| Peak memory | 160680 kb |
| Host | smart-d78030ea-950c-4ad6-9d62-6259031214b1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1462380254 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.1462380254 |
| Directory | /workspace/8.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.2378113047 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 336374210000 ps |
| CPU time | 637.7 seconds |
| Started | Aug 11 04:32:18 PM PDT 24 |
| Finished | Aug 11 04:58:18 PM PDT 24 |
| Peak memory | 160704 kb |
| Host | smart-c214f8f2-21a7-4692-b888-a57e4373b7c2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2378113047 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.2378113047 |
| Directory | /workspace/9.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.1231555462 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 336632490000 ps |
| CPU time | 911.98 seconds |
| Started | Aug 11 04:21:31 PM PDT 24 |
| Finished | Aug 11 04:58:46 PM PDT 24 |
| Peak memory | 160688 kb |
| Host | smart-a1e09cf6-2e97-40b0-a863-fc41bfd969ce |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1231555462 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.1231555462 |
| Directory | /workspace/1.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.1713435806 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 336377070000 ps |
| CPU time | 897.77 seconds |
| Started | Aug 11 04:19:54 PM PDT 24 |
| Finished | Aug 11 04:56:41 PM PDT 24 |
| Peak memory | 160668 kb |
| Host | smart-983459a0-13d4-4ea1-8097-37d3e639c3ff |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1713435806 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.1713435806 |
| Directory | /workspace/10.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.945880183 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 336648470000 ps |
| CPU time | 792.98 seconds |
| Started | Aug 11 04:18:45 PM PDT 24 |
| Finished | Aug 11 04:51:17 PM PDT 24 |
| Peak memory | 160916 kb |
| Host | smart-655d79c0-a6dd-4835-8d8f-dbd57e5c1203 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=945880183 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.945880183 |
| Directory | /workspace/11.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.3373374572 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 337067030000 ps |
| CPU time | 595.38 seconds |
| Started | Aug 11 04:20:33 PM PDT 24 |
| Finished | Aug 11 04:44:50 PM PDT 24 |
| Peak memory | 160636 kb |
| Host | smart-27958c52-5306-4058-90fd-76c98702dda5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3373374572 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.3373374572 |
| Directory | /workspace/12.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.2228314785 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 337107310000 ps |
| CPU time | 745.31 seconds |
| Started | Aug 11 04:23:23 PM PDT 24 |
| Finished | Aug 11 04:54:52 PM PDT 24 |
| Peak memory | 160332 kb |
| Host | smart-448c1a88-0466-4001-aaa4-08950ff9e27a |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2228314785 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.2228314785 |
| Directory | /workspace/13.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.2490791138 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 336489190000 ps |
| CPU time | 775.81 seconds |
| Started | Aug 11 04:21:32 PM PDT 24 |
| Finished | Aug 11 04:53:49 PM PDT 24 |
| Peak memory | 160660 kb |
| Host | smart-f9939195-6acd-431c-9fe9-6acc06f19e5d |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2490791138 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.2490791138 |
| Directory | /workspace/14.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.1438082012 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 336498910000 ps |
| CPU time | 818.44 seconds |
| Started | Aug 11 04:23:22 PM PDT 24 |
| Finished | Aug 11 04:57:13 PM PDT 24 |
| Peak memory | 158872 kb |
| Host | smart-44e61717-fa86-45da-8ab7-72dd05d373f4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1438082012 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.1438082012 |
| Directory | /workspace/15.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.1298240873 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 336867770000 ps |
| CPU time | 806.81 seconds |
| Started | Aug 11 04:18:13 PM PDT 24 |
| Finished | Aug 11 04:51:25 PM PDT 24 |
| Peak memory | 160476 kb |
| Host | smart-2749ad0c-f4f8-4a59-a30e-5d7895acb8d4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1298240873 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.1298240873 |
| Directory | /workspace/16.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.3163578465 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 336726010000 ps |
| CPU time | 740.11 seconds |
| Started | Aug 11 04:23:24 PM PDT 24 |
| Finished | Aug 11 04:54:17 PM PDT 24 |
| Peak memory | 160340 kb |
| Host | smart-fb42aee0-b738-4449-8fba-11ba7a46e468 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3163578465 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.3163578465 |
| Directory | /workspace/17.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.48201850 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 336347310000 ps |
| CPU time | 900.3 seconds |
| Started | Aug 11 04:22:12 PM PDT 24 |
| Finished | Aug 11 04:59:06 PM PDT 24 |
| Peak memory | 160784 kb |
| Host | smart-57d4feeb-aebe-43cf-a93d-92f4c5210371 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=48201850 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.48201850 |
| Directory | /workspace/18.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.65423999 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 336880890000 ps |
| CPU time | 908.09 seconds |
| Started | Aug 11 04:18:58 PM PDT 24 |
| Finished | Aug 11 04:56:03 PM PDT 24 |
| Peak memory | 160620 kb |
| Host | smart-4836d903-4046-4b18-9ee4-5ff94f7d99ff |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=65423999 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.65423999 |
| Directory | /workspace/19.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.1332433802 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 336583050000 ps |
| CPU time | 712.66 seconds |
| Started | Aug 11 04:19:03 PM PDT 24 |
| Finished | Aug 11 04:48:21 PM PDT 24 |
| Peak memory | 160640 kb |
| Host | smart-9daa791c-f636-4415-bda8-aac2478eb7fe |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1332433802 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.1332433802 |
| Directory | /workspace/2.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.903658410 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 336859230000 ps |
| CPU time | 721.11 seconds |
| Started | Aug 11 04:23:34 PM PDT 24 |
| Finished | Aug 11 04:53:26 PM PDT 24 |
| Peak memory | 159596 kb |
| Host | smart-472a3b47-01a1-45fa-8625-9d92c8263e44 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=903658410 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.903658410 |
| Directory | /workspace/20.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3957949986 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 337008890000 ps |
| CPU time | 833.4 seconds |
| Started | Aug 11 04:18:29 PM PDT 24 |
| Finished | Aug 11 04:52:49 PM PDT 24 |
| Peak memory | 160420 kb |
| Host | smart-63ff0467-7111-4a31-8be8-807c1803001e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3957949986 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.3957949986 |
| Directory | /workspace/21.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.4246455778 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 336606790000 ps |
| CPU time | 817.56 seconds |
| Started | Aug 11 04:23:22 PM PDT 24 |
| Finished | Aug 11 04:57:06 PM PDT 24 |
| Peak memory | 159636 kb |
| Host | smart-44605052-db6c-47f2-b743-99edf00d1842 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4246455778 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.4246455778 |
| Directory | /workspace/22.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.3744050357 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 336629650000 ps |
| CPU time | 706.3 seconds |
| Started | Aug 11 04:23:42 PM PDT 24 |
| Finished | Aug 11 04:53:21 PM PDT 24 |
| Peak memory | 160352 kb |
| Host | smart-85e49acc-6a73-49e1-aecc-1b5b974acb27 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3744050357 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.3744050357 |
| Directory | /workspace/23.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.1005568871 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 336825150000 ps |
| CPU time | 709.4 seconds |
| Started | Aug 11 04:23:42 PM PDT 24 |
| Finished | Aug 11 04:53:10 PM PDT 24 |
| Peak memory | 160352 kb |
| Host | smart-46e19b21-ac70-43dd-9d7a-e04b6809a97c |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1005568871 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.1005568871 |
| Directory | /workspace/24.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.194469691 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 336479370000 ps |
| CPU time | 868.92 seconds |
| Started | Aug 11 04:21:47 PM PDT 24 |
| Finished | Aug 11 04:57:45 PM PDT 24 |
| Peak memory | 160648 kb |
| Host | smart-b40f9f54-8d8f-4ede-bcd9-cc12387c3587 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=194469691 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.194469691 |
| Directory | /workspace/25.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.1587176225 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 336797870000 ps |
| CPU time | 740.66 seconds |
| Started | Aug 11 04:23:24 PM PDT 24 |
| Finished | Aug 11 04:54:07 PM PDT 24 |
| Peak memory | 160364 kb |
| Host | smart-2716b8ab-44ce-4d57-b501-d20716fdf484 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1587176225 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.1587176225 |
| Directory | /workspace/26.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.2725054683 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 336278770000 ps |
| CPU time | 708.63 seconds |
| Started | Aug 11 04:21:42 PM PDT 24 |
| Finished | Aug 11 04:50:38 PM PDT 24 |
| Peak memory | 160872 kb |
| Host | smart-b98ec00d-e2a6-411a-8e74-df30ab23d94e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2725054683 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.2725054683 |
| Directory | /workspace/27.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.2455424931 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 336451650000 ps |
| CPU time | 841.65 seconds |
| Started | Aug 11 04:23:31 PM PDT 24 |
| Finished | Aug 11 04:58:05 PM PDT 24 |
| Peak memory | 160332 kb |
| Host | smart-f10e1d5c-4312-40ba-8132-9879bc838f7c |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2455424931 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.2455424931 |
| Directory | /workspace/28.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.2589953028 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 336690390000 ps |
| CPU time | 812.62 seconds |
| Started | Aug 11 04:20:09 PM PDT 24 |
| Finished | Aug 11 04:53:22 PM PDT 24 |
| Peak memory | 160688 kb |
| Host | smart-1d1797ea-d943-42ba-a24d-2b3cd3c31741 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2589953028 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.2589953028 |
| Directory | /workspace/29.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.3364787094 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 336653930000 ps |
| CPU time | 872.01 seconds |
| Started | Aug 11 04:21:47 PM PDT 24 |
| Finished | Aug 11 04:57:32 PM PDT 24 |
| Peak memory | 160692 kb |
| Host | smart-7c94ddae-75c7-4b64-bfb5-a5fe127d7f3e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3364787094 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.3364787094 |
| Directory | /workspace/3.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.3983386216 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 336753170000 ps |
| CPU time | 825.74 seconds |
| Started | Aug 11 04:19:57 PM PDT 24 |
| Finished | Aug 11 04:53:37 PM PDT 24 |
| Peak memory | 160688 kb |
| Host | smart-e084ce08-c8af-4ec1-968c-5b65ad9e7c0a |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3983386216 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.3983386216 |
| Directory | /workspace/30.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.499932746 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 336616450000 ps |
| CPU time | 866.35 seconds |
| Started | Aug 11 04:23:31 PM PDT 24 |
| Finished | Aug 11 04:58:41 PM PDT 24 |
| Peak memory | 160332 kb |
| Host | smart-428278d0-15d1-4fbd-90c5-f63484e32fa5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=499932746 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.499932746 |
| Directory | /workspace/31.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.2196596188 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 336741570000 ps |
| CPU time | 843.21 seconds |
| Started | Aug 11 04:20:47 PM PDT 24 |
| Finished | Aug 11 04:55:41 PM PDT 24 |
| Peak memory | 160672 kb |
| Host | smart-7bf98dc2-ea44-4fc7-8554-b58d57fa0d3f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2196596188 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.2196596188 |
| Directory | /workspace/32.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.1556550631 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 336651930000 ps |
| CPU time | 884.27 seconds |
| Started | Aug 11 04:19:35 PM PDT 24 |
| Finished | Aug 11 04:55:53 PM PDT 24 |
| Peak memory | 160624 kb |
| Host | smart-4a819e43-275b-4f6e-9f19-c99bf53080f2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1556550631 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.1556550631 |
| Directory | /workspace/33.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.3881569018 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 336747950000 ps |
| CPU time | 875.02 seconds |
| Started | Aug 11 04:21:47 PM PDT 24 |
| Finished | Aug 11 04:57:49 PM PDT 24 |
| Peak memory | 160688 kb |
| Host | smart-6e30d5d3-5466-498b-88f7-65566b627f43 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3881569018 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.3881569018 |
| Directory | /workspace/34.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.3142117374 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 336402390000 ps |
| CPU time | 702.62 seconds |
| Started | Aug 11 04:32:15 PM PDT 24 |
| Finished | Aug 11 05:01:05 PM PDT 24 |
| Peak memory | 160712 kb |
| Host | smart-6388e2c7-0597-4aaf-8dd8-c9904180ffd1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3142117374 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.3142117374 |
| Directory | /workspace/35.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.3203000896 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 336935790000 ps |
| CPU time | 826.81 seconds |
| Started | Aug 11 04:32:14 PM PDT 24 |
| Finished | Aug 11 05:05:39 PM PDT 24 |
| Peak memory | 160608 kb |
| Host | smart-e8049a0f-7da5-441d-9326-c159661db672 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3203000896 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.3203000896 |
| Directory | /workspace/36.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.2755214981 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 337089310000 ps |
| CPU time | 788.48 seconds |
| Started | Aug 11 04:32:13 PM PDT 24 |
| Finished | Aug 11 05:04:03 PM PDT 24 |
| Peak memory | 160664 kb |
| Host | smart-658ff137-6673-4069-a891-ffcc1168c7f9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2755214981 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.2755214981 |
| Directory | /workspace/37.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.594283971 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 336680870000 ps |
| CPU time | 668.65 seconds |
| Started | Aug 11 04:32:13 PM PDT 24 |
| Finished | Aug 11 04:59:28 PM PDT 24 |
| Peak memory | 160652 kb |
| Host | smart-a6f81fb4-7a21-4358-b5b4-680421cee785 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=594283971 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.594283971 |
| Directory | /workspace/38.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.1115459163 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 336349150000 ps |
| CPU time | 739.73 seconds |
| Started | Aug 11 04:32:20 PM PDT 24 |
| Finished | Aug 11 05:02:40 PM PDT 24 |
| Peak memory | 160748 kb |
| Host | smart-687cc2bc-308f-4243-8c23-1cdbab79edda |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1115459163 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.1115459163 |
| Directory | /workspace/39.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.1698532393 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 336367110000 ps |
| CPU time | 844.46 seconds |
| Started | Aug 11 04:19:12 PM PDT 24 |
| Finished | Aug 11 04:54:01 PM PDT 24 |
| Peak memory | 160616 kb |
| Host | smart-bce06eba-bf74-4c14-96ee-da7919d23168 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1698532393 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.1698532393 |
| Directory | /workspace/4.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.2888773715 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 336528890000 ps |
| CPU time | 845.35 seconds |
| Started | Aug 11 04:32:34 PM PDT 24 |
| Finished | Aug 11 05:07:06 PM PDT 24 |
| Peak memory | 160796 kb |
| Host | smart-19bf8022-6d5f-4bbc-bd35-f9361b0df515 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2888773715 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.2888773715 |
| Directory | /workspace/40.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.2271334772 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 336722290000 ps |
| CPU time | 853.25 seconds |
| Started | Aug 11 04:32:21 PM PDT 24 |
| Finished | Aug 11 05:07:01 PM PDT 24 |
| Peak memory | 160708 kb |
| Host | smart-df231bd5-c842-4747-8875-6e814356f36d |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2271334772 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.2271334772 |
| Directory | /workspace/41.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.3851114446 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 336480670000 ps |
| CPU time | 737.97 seconds |
| Started | Aug 11 04:32:14 PM PDT 24 |
| Finished | Aug 11 05:02:00 PM PDT 24 |
| Peak memory | 160708 kb |
| Host | smart-24787c93-42ac-43d9-896f-1e20dfe15b4e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3851114446 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.3851114446 |
| Directory | /workspace/42.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.3131438762 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 336653190000 ps |
| CPU time | 834.61 seconds |
| Started | Aug 11 04:32:25 PM PDT 24 |
| Finished | Aug 11 05:06:38 PM PDT 24 |
| Peak memory | 160684 kb |
| Host | smart-af2ca725-e1f3-484d-b550-c25a5bb837a5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3131438762 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.3131438762 |
| Directory | /workspace/43.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.2980916963 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 336919630000 ps |
| CPU time | 724.17 seconds |
| Started | Aug 11 04:32:16 PM PDT 24 |
| Finished | Aug 11 05:01:46 PM PDT 24 |
| Peak memory | 160676 kb |
| Host | smart-80d9ae38-125d-4941-b0f8-1de3e9d8d2c1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2980916963 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.2980916963 |
| Directory | /workspace/44.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.767483288 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 336490390000 ps |
| CPU time | 735.66 seconds |
| Started | Aug 11 04:32:18 PM PDT 24 |
| Finished | Aug 11 05:02:10 PM PDT 24 |
| Peak memory | 160676 kb |
| Host | smart-9a004b98-4039-4e38-9afb-503e58c2c4ed |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=767483288 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.767483288 |
| Directory | /workspace/45.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.450867745 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 336782470000 ps |
| CPU time | 873.93 seconds |
| Started | Aug 11 04:32:22 PM PDT 24 |
| Finished | Aug 11 05:07:43 PM PDT 24 |
| Peak memory | 160916 kb |
| Host | smart-ff1b4c77-9421-4de0-8cd9-3cb1a373a2b9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=450867745 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.450867745 |
| Directory | /workspace/46.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.3173338370 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 336765370000 ps |
| CPU time | 750.03 seconds |
| Started | Aug 11 04:32:14 PM PDT 24 |
| Finished | Aug 11 05:02:22 PM PDT 24 |
| Peak memory | 160676 kb |
| Host | smart-a774896c-3ab2-4140-94fd-5a246901b958 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3173338370 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.3173338370 |
| Directory | /workspace/47.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.4244112247 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 336434090000 ps |
| CPU time | 727.96 seconds |
| Started | Aug 11 04:32:26 PM PDT 24 |
| Finished | Aug 11 05:01:43 PM PDT 24 |
| Peak memory | 160680 kb |
| Host | smart-ad7b6afb-444a-4cce-9fe9-3d61dbfded7f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4244112247 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.4244112247 |
| Directory | /workspace/48.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.1984994458 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 337038870000 ps |
| CPU time | 732.43 seconds |
| Started | Aug 11 04:32:22 PM PDT 24 |
| Finished | Aug 11 05:02:10 PM PDT 24 |
| Peak memory | 160692 kb |
| Host | smart-c3df2514-fa3d-4228-a827-f2e8debb544e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1984994458 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.1984994458 |
| Directory | /workspace/49.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.984596270 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 336851070000 ps |
| CPU time | 800.73 seconds |
| Started | Aug 11 04:23:22 PM PDT 24 |
| Finished | Aug 11 04:56:32 PM PDT 24 |
| Peak memory | 158840 kb |
| Host | smart-03eb0855-7672-4c34-9c76-346e0e10ad6e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=984596270 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.984596270 |
| Directory | /workspace/5.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.378115117 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 336407030000 ps |
| CPU time | 598.25 seconds |
| Started | Aug 11 04:23:32 PM PDT 24 |
| Finished | Aug 11 04:48:00 PM PDT 24 |
| Peak memory | 159260 kb |
| Host | smart-b6d883d9-4d3a-4a33-bf15-b2d67624544f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=378115117 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.378115117 |
| Directory | /workspace/6.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.95195641 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 336662290000 ps |
| CPU time | 516.2 seconds |
| Started | Aug 11 04:23:27 PM PDT 24 |
| Finished | Aug 11 04:45:04 PM PDT 24 |
| Peak memory | 159628 kb |
| Host | smart-5d85f8b9-0063-4386-b002-eda712025fe5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=95195641 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.95195641 |
| Directory | /workspace/7.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.2239560865 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 337120130000 ps |
| CPU time | 675.92 seconds |
| Started | Aug 11 04:23:39 PM PDT 24 |
| Finished | Aug 11 04:51:12 PM PDT 24 |
| Peak memory | 159028 kb |
| Host | smart-f6a7a369-e9bd-4400-bca2-c16a3a2d826e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2239560865 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.2239560865 |
| Directory | /workspace/8.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.1854141777 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 336835790000 ps |
| CPU time | 659.44 seconds |
| Started | Aug 11 04:23:39 PM PDT 24 |
| Finished | Aug 11 04:50:48 PM PDT 24 |
| Peak memory | 158992 kb |
| Host | smart-c681d151-b1d4-4a32-bf15-3befd8d504c3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1854141777 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.1854141777 |
| Directory | /workspace/9.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.1642318611 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 1492410000 ps |
| CPU time | 6.01 seconds |
| Started | Aug 11 05:35:42 PM PDT 24 |
| Finished | Aug 11 05:35:54 PM PDT 24 |
| Peak memory | 164892 kb |
| Host | smart-5bdd01a3-d052-4ed0-bdb0-0f63e3c63a95 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1642318611 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.1642318611 |
| Directory | /workspace/0.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.3533276716 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 1384430000 ps |
| CPU time | 2.79 seconds |
| Started | Aug 11 05:35:38 PM PDT 24 |
| Finished | Aug 11 05:35:45 PM PDT 24 |
| Peak memory | 164860 kb |
| Host | smart-c576f28d-3d5e-4243-b9dd-ea13ce1965aa |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3533276716 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.3533276716 |
| Directory | /workspace/1.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.769104548 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 1547270000 ps |
| CPU time | 3.73 seconds |
| Started | Aug 11 05:35:41 PM PDT 24 |
| Finished | Aug 11 05:35:49 PM PDT 24 |
| Peak memory | 164808 kb |
| Host | smart-a2666b39-175a-4686-a4b3-bae648ade815 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=769104548 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.769104548 |
| Directory | /workspace/10.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.2069461319 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 1563110000 ps |
| CPU time | 5.27 seconds |
| Started | Aug 11 05:35:38 PM PDT 24 |
| Finished | Aug 11 05:35:49 PM PDT 24 |
| Peak memory | 164844 kb |
| Host | smart-de7fe2a1-4649-4e66-9d4d-782bcb42adc9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2069461319 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.2069461319 |
| Directory | /workspace/11.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.678067835 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 1432610000 ps |
| CPU time | 4.3 seconds |
| Started | Aug 11 05:35:38 PM PDT 24 |
| Finished | Aug 11 05:35:47 PM PDT 24 |
| Peak memory | 164824 kb |
| Host | smart-7aea5007-02ac-416f-b8a4-eecb0a194b55 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=678067835 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.678067835 |
| Directory | /workspace/12.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.798895769 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 1488970000 ps |
| CPU time | 4.54 seconds |
| Started | Aug 11 05:35:42 PM PDT 24 |
| Finished | Aug 11 05:35:53 PM PDT 24 |
| Peak memory | 164844 kb |
| Host | smart-fad0dd21-6493-4071-860f-baba2f895750 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=798895769 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.798895769 |
| Directory | /workspace/13.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.3225840823 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 1466850000 ps |
| CPU time | 5.18 seconds |
| Started | Aug 11 05:35:41 PM PDT 24 |
| Finished | Aug 11 05:35:53 PM PDT 24 |
| Peak memory | 164784 kb |
| Host | smart-e3bfebf9-2f7c-4af8-8c88-06b3a76ac26c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3225840823 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.3225840823 |
| Directory | /workspace/14.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.3040224804 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 1521490000 ps |
| CPU time | 4.6 seconds |
| Started | Aug 11 05:35:41 PM PDT 24 |
| Finished | Aug 11 05:35:51 PM PDT 24 |
| Peak memory | 164756 kb |
| Host | smart-a22f3755-d299-4b7e-8eb6-8d828749b775 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3040224804 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.3040224804 |
| Directory | /workspace/15.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.289179793 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 1468330000 ps |
| CPU time | 3.15 seconds |
| Started | Aug 11 05:35:42 PM PDT 24 |
| Finished | Aug 11 05:35:49 PM PDT 24 |
| Peak memory | 164828 kb |
| Host | smart-33badacc-f68c-4ed6-9b98-7153ed163908 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=289179793 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.289179793 |
| Directory | /workspace/16.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.3571430296 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 1284730000 ps |
| CPU time | 4.75 seconds |
| Started | Aug 11 05:35:38 PM PDT 24 |
| Finished | Aug 11 05:35:48 PM PDT 24 |
| Peak memory | 164784 kb |
| Host | smart-3ecc7512-af51-4b9f-b743-3d78c78666fe |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3571430296 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.3571430296 |
| Directory | /workspace/17.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.2065947793 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 1519770000 ps |
| CPU time | 4.49 seconds |
| Started | Aug 11 05:35:36 PM PDT 24 |
| Finished | Aug 11 05:35:46 PM PDT 24 |
| Peak memory | 164840 kb |
| Host | smart-cf2696a4-0964-4937-8d6f-4e4a82813a86 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2065947793 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.2065947793 |
| Directory | /workspace/18.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.2914777635 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 1488290000 ps |
| CPU time | 3.71 seconds |
| Started | Aug 11 05:35:40 PM PDT 24 |
| Finished | Aug 11 05:35:49 PM PDT 24 |
| Peak memory | 164848 kb |
| Host | smart-99c4f8eb-2f0e-4f16-81a1-bb0758a6a8e9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2914777635 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.2914777635 |
| Directory | /workspace/19.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.1411161637 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 1531570000 ps |
| CPU time | 5.88 seconds |
| Started | Aug 11 05:35:37 PM PDT 24 |
| Finished | Aug 11 05:35:50 PM PDT 24 |
| Peak memory | 164892 kb |
| Host | smart-264f61a5-d490-4e59-aac3-029017018584 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1411161637 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.1411161637 |
| Directory | /workspace/2.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.3083688060 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 1424510000 ps |
| CPU time | 3.86 seconds |
| Started | Aug 11 05:35:39 PM PDT 24 |
| Finished | Aug 11 05:35:48 PM PDT 24 |
| Peak memory | 164852 kb |
| Host | smart-125ec5e2-9fb3-4473-a1b0-8c01a7f36fc5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3083688060 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.3083688060 |
| Directory | /workspace/20.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.364110029 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 1503870000 ps |
| CPU time | 5.22 seconds |
| Started | Aug 11 05:35:41 PM PDT 24 |
| Finished | Aug 11 05:35:53 PM PDT 24 |
| Peak memory | 164796 kb |
| Host | smart-c03b562d-7aa8-4978-9f30-e300d16d9adb |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=364110029 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.364110029 |
| Directory | /workspace/21.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.3076642022 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 1417790000 ps |
| CPU time | 3.25 seconds |
| Started | Aug 11 05:35:45 PM PDT 24 |
| Finished | Aug 11 05:35:52 PM PDT 24 |
| Peak memory | 164812 kb |
| Host | smart-a5b7f507-d33e-4a38-9ca9-a58c2b7b600b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3076642022 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.3076642022 |
| Directory | /workspace/22.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.3981455511 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 1346410000 ps |
| CPU time | 3.48 seconds |
| Started | Aug 11 05:35:49 PM PDT 24 |
| Finished | Aug 11 05:35:57 PM PDT 24 |
| Peak memory | 164784 kb |
| Host | smart-54c1140d-d01f-4878-86de-24ad994065bc |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3981455511 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.3981455511 |
| Directory | /workspace/23.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.1140705953 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 1567690000 ps |
| CPU time | 5.04 seconds |
| Started | Aug 11 05:35:46 PM PDT 24 |
| Finished | Aug 11 05:35:57 PM PDT 24 |
| Peak memory | 164844 kb |
| Host | smart-a232b9fb-c9d4-41ca-8bad-737e7cda60d1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1140705953 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.1140705953 |
| Directory | /workspace/24.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.2190096922 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 1479950000 ps |
| CPU time | 4.73 seconds |
| Started | Aug 11 05:35:47 PM PDT 24 |
| Finished | Aug 11 05:35:57 PM PDT 24 |
| Peak memory | 164868 kb |
| Host | smart-bf98fdce-923d-4219-8442-dd08fe914c3e |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2190096922 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.2190096922 |
| Directory | /workspace/25.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2171490827 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 1453070000 ps |
| CPU time | 4.41 seconds |
| Started | Aug 11 05:35:48 PM PDT 24 |
| Finished | Aug 11 05:35:58 PM PDT 24 |
| Peak memory | 164844 kb |
| Host | smart-03a03266-c74e-440c-80a8-9970f5da2916 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2171490827 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.2171490827 |
| Directory | /workspace/26.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.2517695081 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 1477650000 ps |
| CPU time | 4.71 seconds |
| Started | Aug 11 05:35:45 PM PDT 24 |
| Finished | Aug 11 05:35:56 PM PDT 24 |
| Peak memory | 164832 kb |
| Host | smart-98e03d1c-d800-49d1-9789-5316d3ef185b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2517695081 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.2517695081 |
| Directory | /workspace/27.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.2206745242 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 1477530000 ps |
| CPU time | 4 seconds |
| Started | Aug 11 05:35:46 PM PDT 24 |
| Finished | Aug 11 05:35:55 PM PDT 24 |
| Peak memory | 164824 kb |
| Host | smart-61bc07dc-fd1b-4290-a1a8-854a66cd6cc7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2206745242 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.2206745242 |
| Directory | /workspace/28.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.805763181 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 1415730000 ps |
| CPU time | 3.58 seconds |
| Started | Aug 11 05:35:44 PM PDT 24 |
| Finished | Aug 11 05:35:52 PM PDT 24 |
| Peak memory | 164864 kb |
| Host | smart-3488a7a1-6117-4a21-98eb-af5eca44139e |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=805763181 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.805763181 |
| Directory | /workspace/29.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.4003845370 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 1007210000 ps |
| CPU time | 2.84 seconds |
| Started | Aug 11 05:35:39 PM PDT 24 |
| Finished | Aug 11 05:35:46 PM PDT 24 |
| Peak memory | 164768 kb |
| Host | smart-ee684997-db8e-4b9e-ae01-9ddb380357b1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4003845370 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.4003845370 |
| Directory | /workspace/3.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.420065535 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 1381510000 ps |
| CPU time | 4.32 seconds |
| Started | Aug 11 05:35:49 PM PDT 24 |
| Finished | Aug 11 05:35:58 PM PDT 24 |
| Peak memory | 164740 kb |
| Host | smart-2e961fa4-a2ae-4b3d-b022-ec907247e478 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=420065535 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.420065535 |
| Directory | /workspace/30.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.2263860700 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 1515170000 ps |
| CPU time | 4.92 seconds |
| Started | Aug 11 05:35:44 PM PDT 24 |
| Finished | Aug 11 05:35:55 PM PDT 24 |
| Peak memory | 164820 kb |
| Host | smart-9816fdad-2699-4f78-8f5d-029ad2df0bd5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2263860700 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.2263860700 |
| Directory | /workspace/31.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.195760248 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 1451370000 ps |
| CPU time | 5.26 seconds |
| Started | Aug 11 05:35:44 PM PDT 24 |
| Finished | Aug 11 05:35:55 PM PDT 24 |
| Peak memory | 164804 kb |
| Host | smart-83d2385b-994f-4e5b-8b67-4b6565449236 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=195760248 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.195760248 |
| Directory | /workspace/32.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.3446472512 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 1591530000 ps |
| CPU time | 5.14 seconds |
| Started | Aug 11 05:35:47 PM PDT 24 |
| Finished | Aug 11 05:35:58 PM PDT 24 |
| Peak memory | 164792 kb |
| Host | smart-dae5844d-922c-4d64-81b1-d40c21c562cd |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3446472512 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.3446472512 |
| Directory | /workspace/33.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.2356618961 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 1163570000 ps |
| CPU time | 3.68 seconds |
| Started | Aug 11 05:35:44 PM PDT 24 |
| Finished | Aug 11 05:35:52 PM PDT 24 |
| Peak memory | 164816 kb |
| Host | smart-d7667739-41a1-46b3-822b-44a0991a1900 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2356618961 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.2356618961 |
| Directory | /workspace/34.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.2482885486 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 1436530000 ps |
| CPU time | 4.06 seconds |
| Started | Aug 11 05:35:47 PM PDT 24 |
| Finished | Aug 11 05:35:56 PM PDT 24 |
| Peak memory | 164840 kb |
| Host | smart-b64ebc0e-2ce6-4bed-acd7-43af87814774 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2482885486 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.2482885486 |
| Directory | /workspace/35.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.1655776278 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 1562990000 ps |
| CPU time | 5.05 seconds |
| Started | Aug 11 05:35:46 PM PDT 24 |
| Finished | Aug 11 05:35:57 PM PDT 24 |
| Peak memory | 164792 kb |
| Host | smart-998de980-0193-4800-9571-62d0cbbd9899 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1655776278 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.1655776278 |
| Directory | /workspace/36.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1265012774 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 1337130000 ps |
| CPU time | 4.79 seconds |
| Started | Aug 11 05:35:45 PM PDT 24 |
| Finished | Aug 11 05:35:55 PM PDT 24 |
| Peak memory | 164852 kb |
| Host | smart-edcbe10e-40fd-45ca-b0da-93dc11db91d8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1265012774 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.1265012774 |
| Directory | /workspace/37.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.396709965 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 1450790000 ps |
| CPU time | 3.9 seconds |
| Started | Aug 11 05:35:48 PM PDT 24 |
| Finished | Aug 11 05:35:56 PM PDT 24 |
| Peak memory | 164740 kb |
| Host | smart-9e47b9a1-ccfd-4f4a-8ef5-92ed6158b338 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=396709965 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.396709965 |
| Directory | /workspace/38.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.2013783844 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 1424710000 ps |
| CPU time | 4.87 seconds |
| Started | Aug 11 05:35:47 PM PDT 24 |
| Finished | Aug 11 05:35:58 PM PDT 24 |
| Peak memory | 164804 kb |
| Host | smart-d788ee6a-e574-4a5f-8a38-57341ff1b984 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2013783844 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.2013783844 |
| Directory | /workspace/39.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3447449961 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 1462010000 ps |
| CPU time | 4.37 seconds |
| Started | Aug 11 05:35:43 PM PDT 24 |
| Finished | Aug 11 05:35:53 PM PDT 24 |
| Peak memory | 164848 kb |
| Host | smart-3fd5a8fc-70a5-4e94-84d4-b97df4f8c7af |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3447449961 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.3447449961 |
| Directory | /workspace/4.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.3639380483 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 1535790000 ps |
| CPU time | 5.07 seconds |
| Started | Aug 11 05:35:46 PM PDT 24 |
| Finished | Aug 11 05:35:57 PM PDT 24 |
| Peak memory | 164756 kb |
| Host | smart-db5d5f6a-cbe3-48d1-ae8c-159ce7f34174 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3639380483 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.3639380483 |
| Directory | /workspace/40.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.3037843402 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 1545190000 ps |
| CPU time | 4.43 seconds |
| Started | Aug 11 05:35:48 PM PDT 24 |
| Finished | Aug 11 05:35:58 PM PDT 24 |
| Peak memory | 164912 kb |
| Host | smart-4fdf4960-cdb5-4969-8718-e5b8bc03545f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3037843402 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.3037843402 |
| Directory | /workspace/41.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.2136266006 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 1149050000 ps |
| CPU time | 3.22 seconds |
| Started | Aug 11 05:35:49 PM PDT 24 |
| Finished | Aug 11 05:35:56 PM PDT 24 |
| Peak memory | 164740 kb |
| Host | smart-a1ce2fd8-45e1-4f76-9ec1-8f27746ee120 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2136266006 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.2136266006 |
| Directory | /workspace/42.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.3624629292 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 1266150000 ps |
| CPU time | 2.7 seconds |
| Started | Aug 11 05:35:43 PM PDT 24 |
| Finished | Aug 11 05:35:49 PM PDT 24 |
| Peak memory | 164832 kb |
| Host | smart-927ae303-41a5-4fcd-be16-d2420741d7b0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3624629292 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.3624629292 |
| Directory | /workspace/43.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.396154987 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 1357170000 ps |
| CPU time | 4.6 seconds |
| Started | Aug 11 05:35:47 PM PDT 24 |
| Finished | Aug 11 05:35:57 PM PDT 24 |
| Peak memory | 164768 kb |
| Host | smart-dbb47787-7245-4d66-950c-c737423c2fc0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=396154987 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.396154987 |
| Directory | /workspace/44.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.4087445990 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 1470450000 ps |
| CPU time | 4.85 seconds |
| Started | Aug 11 05:35:47 PM PDT 24 |
| Finished | Aug 11 05:35:57 PM PDT 24 |
| Peak memory | 164868 kb |
| Host | smart-a1a50a12-f198-4672-848e-e31f96eaff23 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4087445990 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.4087445990 |
| Directory | /workspace/45.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.122746873 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 1534110000 ps |
| CPU time | 5.27 seconds |
| Started | Aug 11 05:35:45 PM PDT 24 |
| Finished | Aug 11 05:35:57 PM PDT 24 |
| Peak memory | 164780 kb |
| Host | smart-7b5eb8e6-287d-4707-8c90-f58c1a4cf31c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=122746873 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.122746873 |
| Directory | /workspace/46.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.3067047193 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 1070150000 ps |
| CPU time | 4.03 seconds |
| Started | Aug 11 05:35:46 PM PDT 24 |
| Finished | Aug 11 05:35:55 PM PDT 24 |
| Peak memory | 164744 kb |
| Host | smart-2c993971-eaa3-436d-956b-1d6dd5738944 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3067047193 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.3067047193 |
| Directory | /workspace/47.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.3266026648 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 1512730000 ps |
| CPU time | 3.69 seconds |
| Started | Aug 11 05:35:44 PM PDT 24 |
| Finished | Aug 11 05:35:53 PM PDT 24 |
| Peak memory | 164808 kb |
| Host | smart-db981b9e-7c56-4d1c-bc17-db3c9dcf4a7c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3266026648 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.3266026648 |
| Directory | /workspace/48.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.2860164181 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 1281390000 ps |
| CPU time | 3.99 seconds |
| Started | Aug 11 05:35:44 PM PDT 24 |
| Finished | Aug 11 05:35:53 PM PDT 24 |
| Peak memory | 164820 kb |
| Host | smart-41bbd9cc-6142-4220-87e6-27dd513f4437 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2860164181 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.2860164181 |
| Directory | /workspace/49.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.1531299545 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 1558070000 ps |
| CPU time | 5.29 seconds |
| Started | Aug 11 05:35:38 PM PDT 24 |
| Finished | Aug 11 05:35:50 PM PDT 24 |
| Peak memory | 164752 kb |
| Host | smart-f644c5fc-9a93-47b4-b481-6e7dcee9f5ee |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1531299545 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.1531299545 |
| Directory | /workspace/5.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.3128424139 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 1339930000 ps |
| CPU time | 4.65 seconds |
| Started | Aug 11 05:35:42 PM PDT 24 |
| Finished | Aug 11 05:35:52 PM PDT 24 |
| Peak memory | 164892 kb |
| Host | smart-17a0ce67-238e-4dc7-bc9c-271e27505f3f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3128424139 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.3128424139 |
| Directory | /workspace/6.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.2826644324 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 1440130000 ps |
| CPU time | 5.93 seconds |
| Started | Aug 11 05:35:39 PM PDT 24 |
| Finished | Aug 11 05:35:51 PM PDT 24 |
| Peak memory | 164788 kb |
| Host | smart-296e4f0a-546e-41ca-a8a8-e7b27d31e018 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2826644324 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.2826644324 |
| Directory | /workspace/7.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.547548388 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 1540450000 ps |
| CPU time | 4.9 seconds |
| Started | Aug 11 05:35:42 PM PDT 24 |
| Finished | Aug 11 05:35:53 PM PDT 24 |
| Peak memory | 164832 kb |
| Host | smart-5cc53921-231d-429e-8696-0b47d2c89b07 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=547548388 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.547548388 |
| Directory | /workspace/8.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2479651307 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 1264290000 ps |
| CPU time | 3.11 seconds |
| Started | Aug 11 05:35:38 PM PDT 24 |
| Finished | Aug 11 05:35:45 PM PDT 24 |
| Peak memory | 164844 kb |
| Host | smart-6dbdee2a-60d9-4999-a5b8-d057f27eb7bf |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2479651307 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.2479651307 |
| Directory | /workspace/9.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.1938036404 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 1393010000 ps |
| CPU time | 2.7 seconds |
| Started | Aug 11 04:32:38 PM PDT 24 |
| Finished | Aug 11 04:32:45 PM PDT 24 |
| Peak memory | 164788 kb |
| Host | smart-56589569-66ca-4da1-a1a2-4c155c9f27b3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1938036404 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.1938036404 |
| Directory | /workspace/0.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.4160103544 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 1275790000 ps |
| CPU time | 3.17 seconds |
| Started | Aug 11 04:32:34 PM PDT 24 |
| Finished | Aug 11 04:32:42 PM PDT 24 |
| Peak memory | 164748 kb |
| Host | smart-de3600d5-5de3-4f48-8154-e98bbeaf2b67 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4160103544 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.4160103544 |
| Directory | /workspace/1.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.3007921149 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 1482890000 ps |
| CPU time | 3.7 seconds |
| Started | Aug 11 04:32:45 PM PDT 24 |
| Finished | Aug 11 04:32:53 PM PDT 24 |
| Peak memory | 164800 kb |
| Host | smart-7c70793b-f184-48ab-b0c1-ff2ff059ca3d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3007921149 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.3007921149 |
| Directory | /workspace/10.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.856440441 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 1384970000 ps |
| CPU time | 3.26 seconds |
| Started | Aug 11 04:32:30 PM PDT 24 |
| Finished | Aug 11 04:32:38 PM PDT 24 |
| Peak memory | 164776 kb |
| Host | smart-b953c5fd-778b-4f6f-bd9f-5d4ed5d87360 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=856440441 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.856440441 |
| Directory | /workspace/11.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.1998891464 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 1451470000 ps |
| CPU time | 2.98 seconds |
| Started | Aug 11 04:32:30 PM PDT 24 |
| Finished | Aug 11 04:32:37 PM PDT 24 |
| Peak memory | 164700 kb |
| Host | smart-a4657f9d-e416-4db3-90f7-9eb774bc601e |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1998891464 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.1998891464 |
| Directory | /workspace/12.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.4292208724 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 1264190000 ps |
| CPU time | 3.67 seconds |
| Started | Aug 11 04:32:39 PM PDT 24 |
| Finished | Aug 11 04:32:47 PM PDT 24 |
| Peak memory | 164796 kb |
| Host | smart-5a813304-573b-41eb-8ab2-cf50db44b577 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4292208724 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.4292208724 |
| Directory | /workspace/13.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.43696594 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 1466190000 ps |
| CPU time | 3.94 seconds |
| Started | Aug 11 04:32:25 PM PDT 24 |
| Finished | Aug 11 04:32:34 PM PDT 24 |
| Peak memory | 164808 kb |
| Host | smart-63737047-4ee0-4463-914f-0654474378e4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=43696594 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.43696594 |
| Directory | /workspace/14.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.3130511545 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 1422070000 ps |
| CPU time | 4.5 seconds |
| Started | Aug 11 04:32:27 PM PDT 24 |
| Finished | Aug 11 04:32:37 PM PDT 24 |
| Peak memory | 164796 kb |
| Host | smart-7378aaf2-5fef-4fee-ad58-46285f75cfe9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3130511545 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.3130511545 |
| Directory | /workspace/16.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.923717632 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 1551070000 ps |
| CPU time | 3.14 seconds |
| Started | Aug 11 04:32:31 PM PDT 24 |
| Finished | Aug 11 04:32:38 PM PDT 24 |
| Peak memory | 164796 kb |
| Host | smart-fc3e33d8-9e12-41ab-9847-979ff91bd52a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=923717632 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.923717632 |
| Directory | /workspace/17.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.4178159803 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 1137630000 ps |
| CPU time | 3.45 seconds |
| Started | Aug 11 04:32:40 PM PDT 24 |
| Finished | Aug 11 04:32:47 PM PDT 24 |
| Peak memory | 164748 kb |
| Host | smart-6e8cf78a-db75-4f02-aff1-7d141f5d6b28 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4178159803 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.4178159803 |
| Directory | /workspace/18.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.3218191922 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 1537970000 ps |
| CPU time | 3.52 seconds |
| Started | Aug 11 04:32:17 PM PDT 24 |
| Finished | Aug 11 04:32:25 PM PDT 24 |
| Peak memory | 164764 kb |
| Host | smart-01c18d64-ab3c-4a04-b9e8-77f3fdd82c28 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3218191922 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.3218191922 |
| Directory | /workspace/19.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.3081705912 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 1500330000 ps |
| CPU time | 4.16 seconds |
| Started | Aug 11 04:32:27 PM PDT 24 |
| Finished | Aug 11 04:32:37 PM PDT 24 |
| Peak memory | 164728 kb |
| Host | smart-d8f6dd52-7e61-41bd-8c6d-21a5fd568960 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3081705912 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.3081705912 |
| Directory | /workspace/2.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.2763594921 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 1331610000 ps |
| CPU time | 3.78 seconds |
| Started | Aug 11 04:32:17 PM PDT 24 |
| Finished | Aug 11 04:32:26 PM PDT 24 |
| Peak memory | 164772 kb |
| Host | smart-0837753d-2b9e-416e-993a-88f505717afb |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2763594921 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.2763594921 |
| Directory | /workspace/20.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.2161168367 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 1474990000 ps |
| CPU time | 3.35 seconds |
| Started | Aug 11 04:32:38 PM PDT 24 |
| Finished | Aug 11 04:32:45 PM PDT 24 |
| Peak memory | 164800 kb |
| Host | smart-20e4a51e-d176-41be-afc1-fcdbbac32848 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2161168367 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.2161168367 |
| Directory | /workspace/21.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.2285211378 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 1526410000 ps |
| CPU time | 3.65 seconds |
| Started | Aug 11 04:32:20 PM PDT 24 |
| Finished | Aug 11 04:32:28 PM PDT 24 |
| Peak memory | 164760 kb |
| Host | smart-7b08f358-5ab2-47af-96bf-b7b18d0b7e8b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2285211378 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.2285211378 |
| Directory | /workspace/22.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.969404516 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 1219010000 ps |
| CPU time | 3.42 seconds |
| Started | Aug 11 04:32:13 PM PDT 24 |
| Finished | Aug 11 04:32:21 PM PDT 24 |
| Peak memory | 163720 kb |
| Host | smart-df9dce08-8067-4f24-980e-2c355de0eabf |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=969404516 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.969404516 |
| Directory | /workspace/23.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.3288797968 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 1515890000 ps |
| CPU time | 4.08 seconds |
| Started | Aug 11 04:32:49 PM PDT 24 |
| Finished | Aug 11 04:32:58 PM PDT 24 |
| Peak memory | 164824 kb |
| Host | smart-2551394c-4acc-4ef6-afb9-d3a2547ba9bd |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3288797968 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.3288797968 |
| Directory | /workspace/24.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.2374329601 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 1599810000 ps |
| CPU time | 3.11 seconds |
| Started | Aug 11 04:32:25 PM PDT 24 |
| Finished | Aug 11 04:32:32 PM PDT 24 |
| Peak memory | 164772 kb |
| Host | smart-33efb25a-10f1-45c6-9aaa-8e11cbc8870f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2374329601 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.2374329601 |
| Directory | /workspace/25.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.4065232222 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 1405730000 ps |
| CPU time | 3.59 seconds |
| Started | Aug 11 04:32:43 PM PDT 24 |
| Finished | Aug 11 04:32:51 PM PDT 24 |
| Peak memory | 164792 kb |
| Host | smart-3057d3e0-5318-4f64-986c-b6384b28ec18 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4065232222 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.4065232222 |
| Directory | /workspace/26.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.1979330321 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 1472350000 ps |
| CPU time | 3.52 seconds |
| Started | Aug 11 04:32:17 PM PDT 24 |
| Finished | Aug 11 04:32:25 PM PDT 24 |
| Peak memory | 164792 kb |
| Host | smart-6e65d37f-33f0-41a8-9c0a-807853287189 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1979330321 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.1979330321 |
| Directory | /workspace/27.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.2017742067 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 1550570000 ps |
| CPU time | 4.52 seconds |
| Started | Aug 11 04:32:29 PM PDT 24 |
| Finished | Aug 11 04:32:39 PM PDT 24 |
| Peak memory | 163720 kb |
| Host | smart-c644e049-f477-4c55-8915-9535973bcab3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2017742067 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.2017742067 |
| Directory | /workspace/28.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.859883406 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 1414590000 ps |
| CPU time | 3.52 seconds |
| Started | Aug 11 04:32:20 PM PDT 24 |
| Finished | Aug 11 04:32:28 PM PDT 24 |
| Peak memory | 164796 kb |
| Host | smart-e45653c5-10ef-40c5-ab8a-b2b35dfb82fa |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=859883406 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.859883406 |
| Directory | /workspace/29.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.3012591560 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 1460810000 ps |
| CPU time | 3.68 seconds |
| Started | Aug 11 04:32:34 PM PDT 24 |
| Finished | Aug 11 04:32:43 PM PDT 24 |
| Peak memory | 164716 kb |
| Host | smart-49292342-31dd-4a16-add0-4969de0e7f43 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3012591560 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.3012591560 |
| Directory | /workspace/3.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.955855519 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 1528050000 ps |
| CPU time | 4.72 seconds |
| Started | Aug 11 04:32:32 PM PDT 24 |
| Finished | Aug 11 04:32:43 PM PDT 24 |
| Peak memory | 164788 kb |
| Host | smart-e9219078-9e0f-4827-a1b2-dfbc0ce2b521 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=955855519 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.955855519 |
| Directory | /workspace/30.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.121540512 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 1504230000 ps |
| CPU time | 4.96 seconds |
| Started | Aug 11 04:32:21 PM PDT 24 |
| Finished | Aug 11 04:32:32 PM PDT 24 |
| Peak memory | 164952 kb |
| Host | smart-22779763-ef22-4929-b0cb-09e2335b1a5d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=121540512 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.121540512 |
| Directory | /workspace/31.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.2040146306 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 1397690000 ps |
| CPU time | 3.99 seconds |
| Started | Aug 11 04:32:42 PM PDT 24 |
| Finished | Aug 11 04:32:51 PM PDT 24 |
| Peak memory | 164844 kb |
| Host | smart-689d2d4a-7606-44a4-a56b-34735b439972 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2040146306 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.2040146306 |
| Directory | /workspace/32.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.84419991 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 1399890000 ps |
| CPU time | 4.67 seconds |
| Started | Aug 11 04:32:35 PM PDT 24 |
| Finished | Aug 11 04:32:46 PM PDT 24 |
| Peak memory | 164816 kb |
| Host | smart-4ee2a6c5-a15c-4ad4-aa9b-aca47e7f6b07 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=84419991 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.84419991 |
| Directory | /workspace/33.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.894382432 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 1316310000 ps |
| CPU time | 3.16 seconds |
| Started | Aug 11 04:32:28 PM PDT 24 |
| Finished | Aug 11 04:32:35 PM PDT 24 |
| Peak memory | 164796 kb |
| Host | smart-bcd65349-bb05-435c-838c-90718e9c02ac |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=894382432 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.894382432 |
| Directory | /workspace/34.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.1304356403 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 1318530000 ps |
| CPU time | 4.44 seconds |
| Started | Aug 11 04:32:20 PM PDT 24 |
| Finished | Aug 11 04:32:30 PM PDT 24 |
| Peak memory | 164940 kb |
| Host | smart-cf9bffd9-d875-4eae-a163-3282cb97ad2a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1304356403 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.1304356403 |
| Directory | /workspace/35.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.3189614815 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 1560130000 ps |
| CPU time | 3.81 seconds |
| Started | Aug 11 04:32:17 PM PDT 24 |
| Finished | Aug 11 04:32:26 PM PDT 24 |
| Peak memory | 164940 kb |
| Host | smart-8db14d1d-fa16-41f4-83d2-6c66b4d37f94 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3189614815 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.3189614815 |
| Directory | /workspace/36.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.389457619 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 1524030000 ps |
| CPU time | 4.07 seconds |
| Started | Aug 11 04:32:25 PM PDT 24 |
| Finished | Aug 11 04:32:34 PM PDT 24 |
| Peak memory | 164700 kb |
| Host | smart-b5db537a-7b63-44d2-81b8-cad7ee02d03f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=389457619 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.389457619 |
| Directory | /workspace/37.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.1075863734 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 1524330000 ps |
| CPU time | 4.63 seconds |
| Started | Aug 11 04:32:30 PM PDT 24 |
| Finished | Aug 11 04:32:40 PM PDT 24 |
| Peak memory | 164772 kb |
| Host | smart-d3f0610e-cccb-46e9-93a7-a84ec09e2f11 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1075863734 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.1075863734 |
| Directory | /workspace/38.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.1521653075 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 1490110000 ps |
| CPU time | 3.1 seconds |
| Started | Aug 11 04:32:36 PM PDT 24 |
| Finished | Aug 11 04:32:43 PM PDT 24 |
| Peak memory | 164700 kb |
| Host | smart-462c2689-6f54-4bc8-b04f-b1959ac97726 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1521653075 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.1521653075 |
| Directory | /workspace/39.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.232102185 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 1566030000 ps |
| CPU time | 3.91 seconds |
| Started | Aug 11 04:32:27 PM PDT 24 |
| Finished | Aug 11 04:32:36 PM PDT 24 |
| Peak memory | 164756 kb |
| Host | smart-5aca18dc-f96f-4c2f-91f7-d6fe2797271d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=232102185 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.232102185 |
| Directory | /workspace/4.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.838066415 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 1364870000 ps |
| CPU time | 3.18 seconds |
| Started | Aug 11 04:32:25 PM PDT 24 |
| Finished | Aug 11 04:32:33 PM PDT 24 |
| Peak memory | 164824 kb |
| Host | smart-bec58dbd-6ec0-4987-8047-46aad4d89797 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=838066415 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.838066415 |
| Directory | /workspace/40.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.1437255112 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 1441410000 ps |
| CPU time | 3.61 seconds |
| Started | Aug 11 04:32:27 PM PDT 24 |
| Finished | Aug 11 04:32:35 PM PDT 24 |
| Peak memory | 164756 kb |
| Host | smart-c791a947-f9ff-4999-9081-08f7f724df7d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1437255112 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.1437255112 |
| Directory | /workspace/41.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.670265276 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 1457970000 ps |
| CPU time | 4.33 seconds |
| Started | Aug 11 04:32:14 PM PDT 24 |
| Finished | Aug 11 04:32:24 PM PDT 24 |
| Peak memory | 163720 kb |
| Host | smart-999497bd-7618-4e27-b1f8-a716acced10b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=670265276 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.670265276 |
| Directory | /workspace/42.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.3470446257 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 1444610000 ps |
| CPU time | 4.46 seconds |
| Started | Aug 11 04:32:25 PM PDT 24 |
| Finished | Aug 11 04:32:36 PM PDT 24 |
| Peak memory | 164760 kb |
| Host | smart-6a698dfd-1e86-4022-9630-25c1031d673e |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3470446257 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.3470446257 |
| Directory | /workspace/43.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.1088280849 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 1484870000 ps |
| CPU time | 3.23 seconds |
| Started | Aug 11 04:32:43 PM PDT 24 |
| Finished | Aug 11 04:32:50 PM PDT 24 |
| Peak memory | 164768 kb |
| Host | smart-4345e774-7997-45f7-b067-1a417abfbd9f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1088280849 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.1088280849 |
| Directory | /workspace/44.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.709398818 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 1567850000 ps |
| CPU time | 3.62 seconds |
| Started | Aug 11 04:32:31 PM PDT 24 |
| Finished | Aug 11 04:32:39 PM PDT 24 |
| Peak memory | 164712 kb |
| Host | smart-9f3e226b-e3a3-4fa1-966d-b86118ea9a32 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=709398818 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.709398818 |
| Directory | /workspace/45.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.3580292318 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 1486810000 ps |
| CPU time | 3.71 seconds |
| Started | Aug 11 04:32:43 PM PDT 24 |
| Finished | Aug 11 04:32:51 PM PDT 24 |
| Peak memory | 164772 kb |
| Host | smart-f6038331-e0fa-4bee-aa98-6252cd7173e3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3580292318 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.3580292318 |
| Directory | /workspace/46.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.1928076268 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 1367190000 ps |
| CPU time | 3.38 seconds |
| Started | Aug 11 04:32:43 PM PDT 24 |
| Finished | Aug 11 04:32:50 PM PDT 24 |
| Peak memory | 164744 kb |
| Host | smart-3fa7963b-95e4-4c6f-ae22-537c3636e681 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1928076268 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.1928076268 |
| Directory | /workspace/47.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.3540782395 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 1382290000 ps |
| CPU time | 3.19 seconds |
| Started | Aug 11 04:32:23 PM PDT 24 |
| Finished | Aug 11 04:32:31 PM PDT 24 |
| Peak memory | 164792 kb |
| Host | smart-0c1efec2-4a21-4748-a25b-f72892fe5fd1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3540782395 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.3540782395 |
| Directory | /workspace/48.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.553313825 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 1192790000 ps |
| CPU time | 3.31 seconds |
| Started | Aug 11 04:32:35 PM PDT 24 |
| Finished | Aug 11 04:32:42 PM PDT 24 |
| Peak memory | 164736 kb |
| Host | smart-fe7125d0-57b9-4fa9-b7d2-bf1f946ecd73 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=553313825 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.553313825 |
| Directory | /workspace/49.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.3290869568 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 1472150000 ps |
| CPU time | 4.05 seconds |
| Started | Aug 11 04:32:31 PM PDT 24 |
| Finished | Aug 11 04:32:40 PM PDT 24 |
| Peak memory | 164776 kb |
| Host | smart-d76f9f57-e9bc-4c4e-a06c-29ee704e75bc |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3290869568 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.3290869568 |
| Directory | /workspace/5.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.1384098770 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 1532510000 ps |
| CPU time | 4.04 seconds |
| Started | Aug 11 04:32:46 PM PDT 24 |
| Finished | Aug 11 04:32:55 PM PDT 24 |
| Peak memory | 164768 kb |
| Host | smart-d523bc87-7670-4531-bee4-00147d8bd92e |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1384098770 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.1384098770 |
| Directory | /workspace/6.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.228457454 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 1522650000 ps |
| CPU time | 3.66 seconds |
| Started | Aug 11 04:32:29 PM PDT 24 |
| Finished | Aug 11 04:32:37 PM PDT 24 |
| Peak memory | 164836 kb |
| Host | smart-a67742d8-658b-41f9-b92a-bfa8e0449c82 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=228457454 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.228457454 |
| Directory | /workspace/7.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.2641980914 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 1507350000 ps |
| CPU time | 4.89 seconds |
| Started | Aug 11 04:32:25 PM PDT 24 |
| Finished | Aug 11 04:32:36 PM PDT 24 |
| Peak memory | 164748 kb |
| Host | smart-685774f7-95a5-4225-8fbf-2d369c54001a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2641980914 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.2641980914 |
| Directory | /workspace/8.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.741221 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 1489130000 ps |
| CPU time | 3.27 seconds |
| Started | Aug 11 04:32:34 PM PDT 24 |
| Finished | Aug 11 04:32:41 PM PDT 24 |
| Peak memory | 164808 kb |
| Host | smart-42c9be02-5ca7-4a35-88c1-064a6c43b847 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=741221 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.741221 |
| Directory | /workspace/9.prim_lfsr_gal_smoke/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |