Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.31 100.00 96.55 100.00 100.00 95.00


Total tests in report: 200
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
87.31 87.31 100.00 100.00 96.55 96.55 100.00 100.00 100.00 100.00 40.00 40.00 /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.3680467088
95.31 8.00 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 80.00 40.00 /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.1984621782
98.31 3.00 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 95.00 15.00 /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.2634849995

Tests that do not contribute to grading

Name
/workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.2403708472
/workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.2471918147
/workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.1684666205
/workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.3379075061
/workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.971669907
/workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.903083319
/workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.1837421726
/workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.1937229311
/workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.1860546268
/workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.2098211866
/workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.539329899
/workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.1973668490
/workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.3847187754
/workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.2628805734
/workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.3991193915
/workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.3130107646
/workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.759558969
/workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.2231268218
/workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1600951001
/workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.2833161851
/workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.2743590235
/workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.447323799
/workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.552381355
/workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.272500295
/workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.1985308483
/workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.1126587933
/workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.1631187006
/workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.399237893
/workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.649911911
/workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.4283116824
/workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.2723005802
/workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.1884399914
/workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.4228527712
/workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.4223381765
/workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.2880481465
/workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.2411087389
/workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.3752222601
/workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.2381662169
/workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.2848566099
/workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.1426093347
/workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.4289643093
/workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.1354849116
/workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.3223108449
/workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.157688989
/workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.1036778905
/workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.694682671
/workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.41370880
/workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.933808292
/workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.1529309385
/workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.2214710624
/workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.3927251067
/workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.2724890475
/workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.3396842744
/workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.3259982022
/workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.3975035968
/workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.20184370
/workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.3824948797
/workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.36864800
/workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.1419534241
/workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.1385856996
/workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.2704121336
/workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.3077949653
/workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.2485129728
/workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.3263432823
/workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.1982060626
/workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.4096228640
/workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.641920861
/workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.411386717
/workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.4130356921
/workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.504486216
/workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.592161717
/workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.2450098843
/workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.2009431312
/workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.763163668
/workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.1099776038
/workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.1335677161
/workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.483412606
/workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.3057510876
/workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.820737790
/workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.229161980
/workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3824162398
/workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.1177436022
/workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.1347097815
/workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.232357096
/workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.716993600
/workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.1330283868
/workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.25168435
/workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.2616850915
/workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.203502980
/workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.2182045269
/workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.2188150696
/workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1687313565
/workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.1695822506
/workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.554483742
/workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.803420973
/workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.2110081527
/workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.2725371343
/workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.3880336343
/workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.777458902
/workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.1957425771
/workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.218559300
/workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.314556050
/workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.2713206190
/workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.1931744654
/workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.758743695
/workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.754206876
/workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.3929733658
/workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.2854555388
/workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.2864763374
/workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.3299177640
/workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.1504715361
/workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.1238450715
/workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.821385189
/workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.3997916503
/workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.2804545735
/workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.1771025938
/workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.1606800324
/workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2223213804
/workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.1461111807
/workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.3461723777
/workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.3124774996
/workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.1701356729
/workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.964069381
/workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.3845342670
/workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.651713322
/workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.420140066
/workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.4066721492
/workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.1837003813
/workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.1020396132
/workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1567185837
/workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.849804143
/workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.4208438357
/workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.1783300985
/workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.721356286
/workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.512447372
/workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.3069662528
/workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.2016983785
/workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.546046216
/workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.1915101243
/workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.945776551
/workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.240643178
/workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.770257730
/workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.446963566
/workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.942308901
/workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.546219336
/workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.4154056987
/workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.914230965
/workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2722080866
/workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.2131700549
/workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.4105113613
/workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.2729458498
/workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.3791973827
/workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.3258733163
/workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.3109624151
/workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.100574208
/workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.2262443084
/workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.3139015650
/workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.3315887900
/workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.1384079832
/workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.1323787684
/workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.2531326944
/workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.4230207172
/workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.4056368237
/workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.2801420146
/workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.2620022460
/workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.3336306844
/workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.3394731151
/workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.86660035
/workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.1064934720
/workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.2717628560
/workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.551261381
/workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.242669298
/workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.4071768436
/workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.585810202
/workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.3835753631
/workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.1396324705
/workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.2488788881
/workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.2252809593
/workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.2146340911
/workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.3306884013
/workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.793703332
/workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.1994552282
/workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.356388895
/workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.4062172688
/workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.3535828526
/workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.607258431
/workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.1128978085
/workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.824882131
/workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.620384062
/workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.2678649182
/workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.2824360196
/workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.3399164922
/workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.3848699150
/workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.1594934193
/workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.1652748697
/workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.2963238776
/workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.1509725965



Total test records in report: 200
tests.html | tests1.html | tests2.html | tests3.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.242669298 Aug 12 04:26:24 PM PDT 24 Aug 12 04:26:33 PM PDT 24 1345470000 ps
T2 /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.1323787684 Aug 12 04:23:33 PM PDT 24 Aug 12 04:23:43 PM PDT 24 1615870000 ps
T3 /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.3139015650 Aug 12 04:26:31 PM PDT 24 Aug 12 04:26:39 PM PDT 24 1359710000 ps
T4 /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.2146340911 Aug 12 04:26:32 PM PDT 24 Aug 12 04:26:41 PM PDT 24 1392670000 ps
T8 /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.4056368237 Aug 12 04:23:36 PM PDT 24 Aug 12 04:23:46 PM PDT 24 1446010000 ps
T9 /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.3258733163 Aug 12 04:24:30 PM PDT 24 Aug 12 04:24:40 PM PDT 24 1526290000 ps
T10 /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.607258431 Aug 12 04:26:32 PM PDT 24 Aug 12 04:26:41 PM PDT 24 1531190000 ps
T11 /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.3394731151 Aug 12 04:26:14 PM PDT 24 Aug 12 04:26:23 PM PDT 24 1380670000 ps
T12 /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.3315887900 Aug 12 04:26:38 PM PDT 24 Aug 12 04:26:48 PM PDT 24 1633430000 ps
T13 /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.3680467088 Aug 12 04:26:30 PM PDT 24 Aug 12 04:26:38 PM PDT 24 1557750000 ps
T31 /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.1594934193 Aug 12 04:25:18 PM PDT 24 Aug 12 04:25:25 PM PDT 24 1375450000 ps
T32 /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.4062172688 Aug 12 04:25:15 PM PDT 24 Aug 12 04:25:27 PM PDT 24 1445190000 ps
T33 /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.1064934720 Aug 12 04:25:47 PM PDT 24 Aug 12 04:25:56 PM PDT 24 1417190000 ps
T34 /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.2488788881 Aug 12 04:26:19 PM PDT 24 Aug 12 04:26:29 PM PDT 24 1370070000 ps
T35 /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.2824360196 Aug 12 04:21:49 PM PDT 24 Aug 12 04:21:58 PM PDT 24 1345430000 ps
T36 /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.3848699150 Aug 12 04:26:30 PM PDT 24 Aug 12 04:26:39 PM PDT 24 1453670000 ps
T37 /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.551261381 Aug 12 04:27:10 PM PDT 24 Aug 12 04:27:20 PM PDT 24 1473850000 ps
T38 /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.620384062 Aug 12 04:23:39 PM PDT 24 Aug 12 04:23:48 PM PDT 24 1441650000 ps
T39 /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.2262443084 Aug 12 04:26:45 PM PDT 24 Aug 12 04:26:55 PM PDT 24 1481030000 ps
T40 /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.1396324705 Aug 12 04:26:28 PM PDT 24 Aug 12 04:26:37 PM PDT 24 1310470000 ps
T41 /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.1994552282 Aug 12 04:27:11 PM PDT 24 Aug 12 04:27:19 PM PDT 24 1313370000 ps
T42 /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.2620022460 Aug 12 04:26:25 PM PDT 24 Aug 12 04:26:35 PM PDT 24 1523270000 ps
T43 /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.824882131 Aug 12 04:26:32 PM PDT 24 Aug 12 04:26:41 PM PDT 24 1516470000 ps
T44 /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.585810202 Aug 12 04:24:53 PM PDT 24 Aug 12 04:25:03 PM PDT 24 1276070000 ps
T45 /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.356388895 Aug 12 04:26:25 PM PDT 24 Aug 12 04:26:33 PM PDT 24 1369650000 ps
T46 /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.1652748697 Aug 12 04:26:21 PM PDT 24 Aug 12 04:26:30 PM PDT 24 1545890000 ps
T47 /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.793703332 Aug 12 04:23:29 PM PDT 24 Aug 12 04:23:39 PM PDT 24 1473010000 ps
T48 /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.3399164922 Aug 12 04:26:44 PM PDT 24 Aug 12 04:26:52 PM PDT 24 1500750000 ps
T49 /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.3109624151 Aug 12 04:26:24 PM PDT 24 Aug 12 04:26:35 PM PDT 24 1497890000 ps
T50 /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.86660035 Aug 12 04:26:14 PM PDT 24 Aug 12 04:26:23 PM PDT 24 1456870000 ps
T51 /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.3791973827 Aug 12 04:26:45 PM PDT 24 Aug 12 04:26:53 PM PDT 24 1273150000 ps
T52 /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.4071768436 Aug 12 04:24:54 PM PDT 24 Aug 12 04:25:07 PM PDT 24 1431770000 ps
T53 /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.2963238776 Aug 12 04:26:13 PM PDT 24 Aug 12 04:26:21 PM PDT 24 1189110000 ps
T54 /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.2131700549 Aug 12 04:26:26 PM PDT 24 Aug 12 04:26:36 PM PDT 24 1400930000 ps
T55 /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.3306884013 Aug 12 04:24:22 PM PDT 24 Aug 12 04:24:31 PM PDT 24 1359870000 ps
T56 /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.2717628560 Aug 12 04:21:54 PM PDT 24 Aug 12 04:22:03 PM PDT 24 1155710000 ps
T57 /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.4230207172 Aug 12 04:24:58 PM PDT 24 Aug 12 04:25:08 PM PDT 24 1419470000 ps
T58 /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.2678649182 Aug 12 04:26:45 PM PDT 24 Aug 12 04:26:53 PM PDT 24 1467410000 ps
T59 /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.3535828526 Aug 12 04:27:13 PM PDT 24 Aug 12 04:27:22 PM PDT 24 1427330000 ps
T60 /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.1128978085 Aug 12 04:26:17 PM PDT 24 Aug 12 04:26:26 PM PDT 24 1400050000 ps
T61 /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.3835753631 Aug 12 04:23:00 PM PDT 24 Aug 12 04:23:10 PM PDT 24 1413350000 ps
T62 /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.100574208 Aug 12 04:26:57 PM PDT 24 Aug 12 04:27:08 PM PDT 24 1549090000 ps
T63 /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.2801420146 Aug 12 04:26:57 PM PDT 24 Aug 12 04:27:06 PM PDT 24 1567110000 ps
T64 /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.1509725965 Aug 12 04:24:12 PM PDT 24 Aug 12 04:24:26 PM PDT 24 1514370000 ps
T65 /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.3336306844 Aug 12 04:25:46 PM PDT 24 Aug 12 04:25:56 PM PDT 24 1535450000 ps
T66 /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.2729458498 Aug 12 04:26:14 PM PDT 24 Aug 12 04:26:24 PM PDT 24 1537010000 ps
T67 /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.2531326944 Aug 12 04:23:29 PM PDT 24 Aug 12 04:23:39 PM PDT 24 1516930000 ps
T68 /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.1384079832 Aug 12 04:26:55 PM PDT 24 Aug 12 04:27:05 PM PDT 24 1457570000 ps
T69 /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.4105113613 Aug 12 04:26:34 PM PDT 24 Aug 12 04:26:44 PM PDT 24 1543590000 ps
T70 /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.2252809593 Aug 12 04:23:59 PM PDT 24 Aug 12 04:24:07 PM PDT 24 1132310000 ps
T14 /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.3263432823 Aug 12 04:27:43 PM PDT 24 Aug 12 04:50:37 PM PDT 24 336893590000 ps
T15 /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.1984621782 Aug 12 04:24:20 PM PDT 24 Aug 12 05:00:46 PM PDT 24 336770270000 ps
T16 /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.4130356921 Aug 12 04:26:28 PM PDT 24 Aug 12 04:57:22 PM PDT 24 336346390000 ps
T17 /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.1177436022 Aug 12 04:26:33 PM PDT 24 Aug 12 04:51:51 PM PDT 24 336926450000 ps
T18 /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.1335677161 Aug 12 04:26:27 PM PDT 24 Aug 12 04:51:31 PM PDT 24 336705630000 ps
T19 /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.763163668 Aug 12 04:24:41 PM PDT 24 Aug 12 04:53:56 PM PDT 24 337063770000 ps
T20 /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.3077949653 Aug 12 04:24:17 PM PDT 24 Aug 12 04:54:50 PM PDT 24 336460090000 ps
T21 /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.1982060626 Aug 12 04:26:32 PM PDT 24 Aug 12 04:56:54 PM PDT 24 336650950000 ps
T22 /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.232357096 Aug 12 04:26:25 PM PDT 24 Aug 12 04:51:13 PM PDT 24 336579550000 ps
T23 /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.2616850915 Aug 12 04:27:13 PM PDT 24 Aug 12 04:56:55 PM PDT 24 336499930000 ps
T71 /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.4096228640 Aug 12 04:25:47 PM PDT 24 Aug 12 04:55:00 PM PDT 24 336798270000 ps
T72 /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.3396842744 Aug 12 04:21:52 PM PDT 24 Aug 12 05:03:47 PM PDT 24 336883290000 ps
T73 /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.2450098843 Aug 12 04:26:31 PM PDT 24 Aug 12 04:58:32 PM PDT 24 336728950000 ps
T74 /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3824162398 Aug 12 04:26:34 PM PDT 24 Aug 12 04:59:18 PM PDT 24 336894370000 ps
T75 /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.1347097815 Aug 12 04:22:17 PM PDT 24 Aug 12 04:55:45 PM PDT 24 336351630000 ps
T76 /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.3880336343 Aug 12 04:26:16 PM PDT 24 Aug 12 04:51:17 PM PDT 24 337054530000 ps
T77 /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.1695822506 Aug 12 04:26:41 PM PDT 24 Aug 12 04:51:35 PM PDT 24 336359830000 ps
T78 /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.2485129728 Aug 12 04:26:56 PM PDT 24 Aug 12 04:52:21 PM PDT 24 336299610000 ps
T79 /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.3927251067 Aug 12 04:26:55 PM PDT 24 Aug 12 04:53:43 PM PDT 24 336892010000 ps
T80 /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.803420973 Aug 12 04:23:00 PM PDT 24 Aug 12 04:52:54 PM PDT 24 336347210000 ps
T81 /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.20184370 Aug 12 04:24:09 PM PDT 24 Aug 12 04:54:56 PM PDT 24 336831610000 ps
T82 /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.1330283868 Aug 12 04:21:47 PM PDT 24 Aug 12 04:57:50 PM PDT 24 336473390000 ps
T83 /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.2188150696 Aug 12 04:25:59 PM PDT 24 Aug 12 04:54:24 PM PDT 24 336542850000 ps
T84 /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.2110081527 Aug 12 04:22:39 PM PDT 24 Aug 12 05:05:59 PM PDT 24 336748810000 ps
T85 /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.2725371343 Aug 12 04:26:32 PM PDT 24 Aug 12 04:53:59 PM PDT 24 337021990000 ps
T86 /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.641920861 Aug 12 04:26:34 PM PDT 24 Aug 12 04:56:03 PM PDT 24 336486050000 ps
T87 /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.2182045269 Aug 12 04:26:27 PM PDT 24 Aug 12 04:57:01 PM PDT 24 336966410000 ps
T88 /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.2214710624 Aug 12 04:24:15 PM PDT 24 Aug 12 04:54:10 PM PDT 24 336690410000 ps
T89 /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.1385856996 Aug 12 04:24:18 PM PDT 24 Aug 12 05:02:55 PM PDT 24 336968210000 ps
T90 /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.1419534241 Aug 12 04:23:48 PM PDT 24 Aug 12 04:53:45 PM PDT 24 336347010000 ps
T91 /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.36864800 Aug 12 04:23:29 PM PDT 24 Aug 12 05:07:40 PM PDT 24 336437650000 ps
T92 /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.3259982022 Aug 12 04:25:00 PM PDT 24 Aug 12 05:01:28 PM PDT 24 336921570000 ps
T93 /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.3824948797 Aug 12 04:22:44 PM PDT 24 Aug 12 04:59:54 PM PDT 24 336845730000 ps
T94 /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.483412606 Aug 12 04:26:16 PM PDT 24 Aug 12 04:55:08 PM PDT 24 336907210000 ps
T95 /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.3975035968 Aug 12 04:21:53 PM PDT 24 Aug 12 05:03:25 PM PDT 24 336677450000 ps
T96 /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.592161717 Aug 12 04:25:56 PM PDT 24 Aug 12 04:54:00 PM PDT 24 336490910000 ps
T97 /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.1099776038 Aug 12 04:26:40 PM PDT 24 Aug 12 04:54:30 PM PDT 24 336439770000 ps
T98 /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.3057510876 Aug 12 04:23:35 PM PDT 24 Aug 12 05:04:10 PM PDT 24 336513570000 ps
T99 /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.2724890475 Aug 12 04:26:28 PM PDT 24 Aug 12 04:51:19 PM PDT 24 336721070000 ps
T100 /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.554483742 Aug 12 04:27:24 PM PDT 24 Aug 12 04:56:35 PM PDT 24 336999990000 ps
T101 /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1687313565 Aug 12 04:21:53 PM PDT 24 Aug 12 05:01:25 PM PDT 24 336984850000 ps
T102 /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.411386717 Aug 12 04:26:00 PM PDT 24 Aug 12 04:56:33 PM PDT 24 336866630000 ps
T103 /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.504486216 Aug 12 04:23:19 PM PDT 24 Aug 12 05:00:30 PM PDT 24 336989430000 ps
T104 /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.2704121336 Aug 12 04:26:45 PM PDT 24 Aug 12 05:01:08 PM PDT 24 336400610000 ps
T105 /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.2009431312 Aug 12 04:25:47 PM PDT 24 Aug 12 04:52:59 PM PDT 24 337046390000 ps
T106 /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.716993600 Aug 12 04:26:17 PM PDT 24 Aug 12 04:55:37 PM PDT 24 336673750000 ps
T107 /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.25168435 Aug 12 04:21:48 PM PDT 24 Aug 12 04:59:23 PM PDT 24 337064590000 ps
T108 /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.820737790 Aug 12 04:24:09 PM PDT 24 Aug 12 05:02:35 PM PDT 24 337086950000 ps
T109 /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.203502980 Aug 12 04:22:38 PM PDT 24 Aug 12 04:59:06 PM PDT 24 336910910000 ps
T110 /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.229161980 Aug 12 04:23:09 PM PDT 24 Aug 12 05:00:17 PM PDT 24 336899210000 ps
T5 /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.4223381765 Aug 12 04:26:31 PM PDT 24 Aug 12 04:57:57 PM PDT 24 336796650000 ps
T6 /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.447323799 Aug 12 04:23:49 PM PDT 24 Aug 12 05:01:48 PM PDT 24 336526310000 ps
T7 /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.2634849995 Aug 12 04:22:29 PM PDT 24 Aug 12 04:58:59 PM PDT 24 336464030000 ps
T24 /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.2880481465 Aug 12 04:27:13 PM PDT 24 Aug 12 04:57:11 PM PDT 24 336892910000 ps
T25 /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.157688989 Aug 12 04:22:04 PM PDT 24 Aug 12 05:05:34 PM PDT 24 336486010000 ps
T26 /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.41370880 Aug 12 04:22:59 PM PDT 24 Aug 12 05:05:22 PM PDT 24 336722610000 ps
T27 /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.1529309385 Aug 12 04:27:24 PM PDT 24 Aug 12 04:56:17 PM PDT 24 336826810000 ps
T28 /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.2848566099 Aug 12 04:26:33 PM PDT 24 Aug 12 04:50:32 PM PDT 24 336881190000 ps
T29 /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.2833161851 Aug 12 04:25:55 PM PDT 24 Aug 12 04:54:09 PM PDT 24 336831170000 ps
T30 /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.971669907 Aug 12 04:23:17 PM PDT 24 Aug 12 05:00:06 PM PDT 24 336533570000 ps
T111 /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.2381662169 Aug 12 04:22:26 PM PDT 24 Aug 12 05:00:24 PM PDT 24 336367410000 ps
T112 /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.759558969 Aug 12 04:26:32 PM PDT 24 Aug 12 04:57:10 PM PDT 24 336683310000 ps
T113 /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.1985308483 Aug 12 04:21:54 PM PDT 24 Aug 12 05:01:22 PM PDT 24 336635390000 ps
T114 /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.1860546268 Aug 12 04:26:34 PM PDT 24 Aug 12 04:59:26 PM PDT 24 336666430000 ps
T115 /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.2723005802 Aug 12 04:24:43 PM PDT 24 Aug 12 05:07:29 PM PDT 24 336386350000 ps
T116 /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.2743590235 Aug 12 04:25:46 PM PDT 24 Aug 12 04:51:49 PM PDT 24 336879130000 ps
T117 /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.539329899 Aug 12 04:26:00 PM PDT 24 Aug 12 04:55:19 PM PDT 24 336869290000 ps
T118 /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.2403708472 Aug 12 04:26:27 PM PDT 24 Aug 12 04:55:08 PM PDT 24 336307510000 ps
T119 /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.4283116824 Aug 12 04:26:16 PM PDT 24 Aug 12 04:55:47 PM PDT 24 336326450000 ps
T120 /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.649911911 Aug 12 04:26:16 PM PDT 24 Aug 12 04:55:31 PM PDT 24 336483230000 ps
T121 /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.694682671 Aug 12 04:26:30 PM PDT 24 Aug 12 04:57:53 PM PDT 24 336514830000 ps
T122 /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.2411087389 Aug 12 04:26:25 PM PDT 24 Aug 12 04:56:35 PM PDT 24 336403370000 ps
T123 /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.1837421726 Aug 12 04:22:36 PM PDT 24 Aug 12 05:01:41 PM PDT 24 336537010000 ps
T124 /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.3223108449 Aug 12 04:26:27 PM PDT 24 Aug 12 04:55:38 PM PDT 24 336721630000 ps
T125 /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.933808292 Aug 12 04:23:00 PM PDT 24 Aug 12 04:53:37 PM PDT 24 336661250000 ps
T126 /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.1354849116 Aug 12 04:23:04 PM PDT 24 Aug 12 04:57:42 PM PDT 24 336382990000 ps
T127 /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.1036778905 Aug 12 04:27:11 PM PDT 24 Aug 12 04:57:32 PM PDT 24 336954030000 ps
T128 /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1600951001 Aug 12 04:26:14 PM PDT 24 Aug 12 04:54:31 PM PDT 24 336465430000 ps
T129 /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.3379075061 Aug 12 04:26:21 PM PDT 24 Aug 12 04:51:03 PM PDT 24 336377270000 ps
T130 /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.272500295 Aug 12 04:23:32 PM PDT 24 Aug 12 05:07:38 PM PDT 24 336798630000 ps
T131 /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.2098211866 Aug 12 04:24:15 PM PDT 24 Aug 12 05:05:22 PM PDT 24 336693010000 ps
T132 /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.1684666205 Aug 12 04:26:41 PM PDT 24 Aug 12 04:55:32 PM PDT 24 336498670000 ps
T133 /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.399237893 Aug 12 04:26:28 PM PDT 24 Aug 12 04:51:53 PM PDT 24 337075950000 ps
T134 /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.552381355 Aug 12 04:26:40 PM PDT 24 Aug 12 04:55:31 PM PDT 24 337075030000 ps
T135 /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.1426093347 Aug 12 04:26:34 PM PDT 24 Aug 12 04:54:00 PM PDT 24 336525790000 ps
T136 /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.1884399914 Aug 12 04:22:28 PM PDT 24 Aug 12 05:06:16 PM PDT 24 336522930000 ps
T137 /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.1937229311 Aug 12 04:24:05 PM PDT 24 Aug 12 04:57:28 PM PDT 24 336868570000 ps
T138 /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.3752222601 Aug 12 04:22:40 PM PDT 24 Aug 12 05:06:32 PM PDT 24 336606770000 ps
T139 /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.1631187006 Aug 12 04:22:37 PM PDT 24 Aug 12 04:58:53 PM PDT 24 336741450000 ps
T140 /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.903083319 Aug 12 04:23:04 PM PDT 24 Aug 12 04:54:43 PM PDT 24 337059470000 ps
T141 /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.3847187754 Aug 12 04:26:39 PM PDT 24 Aug 12 04:55:27 PM PDT 24 336358030000 ps
T142 /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.1126587933 Aug 12 04:24:10 PM PDT 24 Aug 12 05:05:50 PM PDT 24 336789210000 ps
T143 /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.2628805734 Aug 12 04:24:17 PM PDT 24 Aug 12 04:53:47 PM PDT 24 336708850000 ps
T144 /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.3130107646 Aug 12 04:26:25 PM PDT 24 Aug 12 04:56:01 PM PDT 24 336920330000 ps
T145 /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.3991193915 Aug 12 04:25:52 PM PDT 24 Aug 12 04:54:52 PM PDT 24 337059470000 ps
T146 /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.2231268218 Aug 12 04:25:47 PM PDT 24 Aug 12 04:55:09 PM PDT 24 336820550000 ps
T147 /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.4289643093 Aug 12 04:22:35 PM PDT 24 Aug 12 05:04:38 PM PDT 24 336875290000 ps
T148 /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.1973668490 Aug 12 04:21:52 PM PDT 24 Aug 12 05:04:19 PM PDT 24 336926450000 ps
T149 /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.4228527712 Aug 12 04:23:30 PM PDT 24 Aug 12 05:06:50 PM PDT 24 336308170000 ps
T150 /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.2471918147 Aug 12 04:22:29 PM PDT 24 Aug 12 05:05:53 PM PDT 24 336811570000 ps
T151 /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.1606800324 Aug 12 04:25:46 PM PDT 24 Aug 12 04:25:57 PM PDT 24 1576190000 ps
T152 /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.4208438357 Aug 12 04:26:25 PM PDT 24 Aug 12 04:26:33 PM PDT 24 1437610000 ps
T153 /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.240643178 Aug 12 04:26:33 PM PDT 24 Aug 12 04:26:41 PM PDT 24 1259530000 ps
T154 /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.3845342670 Aug 12 04:26:28 PM PDT 24 Aug 12 04:26:36 PM PDT 24 1386490000 ps
T155 /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2722080866 Aug 12 04:26:45 PM PDT 24 Aug 12 04:26:54 PM PDT 24 1394770000 ps
T156 /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.2864763374 Aug 12 04:22:36 PM PDT 24 Aug 12 04:22:47 PM PDT 24 1292490000 ps
T157 /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.3461723777 Aug 12 04:26:41 PM PDT 24 Aug 12 04:26:49 PM PDT 24 1570850000 ps
T158 /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.2016983785 Aug 12 04:26:33 PM PDT 24 Aug 12 04:26:41 PM PDT 24 1401330000 ps
T159 /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.1771025938 Aug 12 04:25:47 PM PDT 24 Aug 12 04:25:56 PM PDT 24 1322250000 ps
T160 /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.4154056987 Aug 12 04:22:27 PM PDT 24 Aug 12 04:22:36 PM PDT 24 1341870000 ps
T161 /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.1957425771 Aug 12 04:26:11 PM PDT 24 Aug 12 04:26:20 PM PDT 24 1536130000 ps
T162 /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.964069381 Aug 12 04:26:27 PM PDT 24 Aug 12 04:26:34 PM PDT 24 1309190000 ps
T163 /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.1504715361 Aug 12 04:26:27 PM PDT 24 Aug 12 04:26:36 PM PDT 24 1509630000 ps
T164 /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.1238450715 Aug 12 04:26:53 PM PDT 24 Aug 12 04:27:02 PM PDT 24 1601970000 ps
T165 /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.314556050 Aug 12 04:23:26 PM PDT 24 Aug 12 04:23:34 PM PDT 24 1358370000 ps
T166 /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.1783300985 Aug 12 04:26:45 PM PDT 24 Aug 12 04:26:54 PM PDT 24 1527270000 ps
T167 /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.546219336 Aug 12 04:27:23 PM PDT 24 Aug 12 04:27:32 PM PDT 24 1358230000 ps
T168 /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.546046216 Aug 12 04:21:56 PM PDT 24 Aug 12 04:22:06 PM PDT 24 1348410000 ps
T169 /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1567185837 Aug 12 04:22:39 PM PDT 24 Aug 12 04:22:47 PM PDT 24 1411190000 ps
T170 /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.1020396132 Aug 12 04:26:28 PM PDT 24 Aug 12 04:26:39 PM PDT 24 1623910000 ps
T171 /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.914230965 Aug 12 04:26:31 PM PDT 24 Aug 12 04:26:40 PM PDT 24 1477710000 ps
T172 /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.3299177640 Aug 12 04:22:43 PM PDT 24 Aug 12 04:22:56 PM PDT 24 1546050000 ps
T173 /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.770257730 Aug 12 04:25:45 PM PDT 24 Aug 12 04:25:53 PM PDT 24 1459590000 ps
T174 /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.1837003813 Aug 12 04:26:26 PM PDT 24 Aug 12 04:26:36 PM PDT 24 1471390000 ps
T175 /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.1931744654 Aug 12 04:26:00 PM PDT 24 Aug 12 04:26:10 PM PDT 24 1535290000 ps
T176 /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.1701356729 Aug 12 04:23:12 PM PDT 24 Aug 12 04:23:22 PM PDT 24 1456770000 ps
T177 /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.651713322 Aug 12 04:26:18 PM PDT 24 Aug 12 04:26:27 PM PDT 24 1256190000 ps
T178 /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.2713206190 Aug 12 04:24:57 PM PDT 24 Aug 12 04:25:10 PM PDT 24 1544050000 ps
T179 /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.1461111807 Aug 12 04:25:55 PM PDT 24 Aug 12 04:26:04 PM PDT 24 1378230000 ps
T180 /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.754206876 Aug 12 04:26:45 PM PDT 24 Aug 12 04:26:54 PM PDT 24 1341570000 ps
T181 /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.3124774996 Aug 12 04:23:39 PM PDT 24 Aug 12 04:23:47 PM PDT 24 1186890000 ps
T182 /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.758743695 Aug 12 04:23:36 PM PDT 24 Aug 12 04:23:44 PM PDT 24 925730000 ps
T183 /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.777458902 Aug 12 04:21:56 PM PDT 24 Aug 12 04:22:07 PM PDT 24 1400250000 ps
T184 /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.2854555388 Aug 12 04:24:10 PM PDT 24 Aug 12 04:24:21 PM PDT 24 1537590000 ps
T185 /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.942308901 Aug 12 04:26:30 PM PDT 24 Aug 12 04:26:39 PM PDT 24 1426170000 ps
T186 /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.3929733658 Aug 12 04:21:42 PM PDT 24 Aug 12 04:21:52 PM PDT 24 1245150000 ps
T187 /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.849804143 Aug 12 04:26:20 PM PDT 24 Aug 12 04:26:27 PM PDT 24 1497150000 ps
T188 /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.446963566 Aug 12 04:21:47 PM PDT 24 Aug 12 04:21:57 PM PDT 24 1471390000 ps
T189 /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.512447372 Aug 12 04:26:33 PM PDT 24 Aug 12 04:26:42 PM PDT 24 1496350000 ps
T190 /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.2804545735 Aug 12 04:25:46 PM PDT 24 Aug 12 04:25:56 PM PDT 24 1528410000 ps
T191 /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.821385189 Aug 12 04:26:56 PM PDT 24 Aug 12 04:27:05 PM PDT 24 1453210000 ps
T192 /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.945776551 Aug 12 04:24:44 PM PDT 24 Aug 12 04:24:55 PM PDT 24 1609330000 ps
T193 /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2223213804 Aug 12 04:23:51 PM PDT 24 Aug 12 04:24:01 PM PDT 24 1304610000 ps
T194 /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.218559300 Aug 12 04:26:16 PM PDT 24 Aug 12 04:26:24 PM PDT 24 1326670000 ps
T195 /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.3997916503 Aug 12 04:24:27 PM PDT 24 Aug 12 04:24:35 PM PDT 24 1367310000 ps
T196 /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.420140066 Aug 12 04:26:19 PM PDT 24 Aug 12 04:26:27 PM PDT 24 1288090000 ps
T197 /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.1915101243 Aug 12 04:23:41 PM PDT 24 Aug 12 04:23:55 PM PDT 24 1543290000 ps
T198 /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.3069662528 Aug 12 04:22:49 PM PDT 24 Aug 12 04:23:03 PM PDT 24 1611950000 ps
T199 /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.721356286 Aug 12 04:26:17 PM PDT 24 Aug 12 04:26:28 PM PDT 24 1614670000 ps
T200 /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.4066721492 Aug 12 04:26:18 PM PDT 24 Aug 12 04:26:27 PM PDT 24 1179630000 ps

Test location /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.3680467088
Short name T13
Test name
Test status
Simulation time 1557750000 ps
CPU time 3.67 seconds
Started Aug 12 04:26:30 PM PDT 24
Finished Aug 12 04:26:38 PM PDT 24
Peak memory 164348 kb
Host smart-c5b70dce-2dd4-4510-9c9f-628d7c20ea31
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3680467088 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.3680467088
Directory /workspace/0.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.1984621782
Short name T15
Test name
Test status
Simulation time 336770270000 ps
CPU time 885.84 seconds
Started Aug 12 04:24:20 PM PDT 24
Finished Aug 12 05:00:46 PM PDT 24
Peak memory 160704 kb
Host smart-6f642546-549a-42b0-bb6e-44249e27559d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1984621782 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.1984621782
Directory /workspace/13.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.2634849995
Short name T7
Test name
Test status
Simulation time 336464030000 ps
CPU time 892.23 seconds
Started Aug 12 04:22:29 PM PDT 24
Finished Aug 12 04:58:59 PM PDT 24
Peak memory 160456 kb
Host smart-496b45d7-d0ae-4f4e-8e4d-ad04b3031da0
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2634849995 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.2634849995
Directory /workspace/1.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.2403708472
Short name T118
Test name
Test status
Simulation time 336307510000 ps
CPU time 697.7 seconds
Started Aug 12 04:26:27 PM PDT 24
Finished Aug 12 04:55:08 PM PDT 24
Peak memory 159168 kb
Host smart-91a71adc-e02a-4688-b05b-f7a8a8e0a64d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2403708472 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.2403708472
Directory /workspace/0.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.2471918147
Short name T150
Test name
Test status
Simulation time 336811570000 ps
CPU time 1046.07 seconds
Started Aug 12 04:22:29 PM PDT 24
Finished Aug 12 05:05:53 PM PDT 24
Peak memory 160628 kb
Host smart-21139d03-2464-4b62-ba63-b2ee00c6aa62
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2471918147 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.2471918147
Directory /workspace/10.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.1684666205
Short name T132
Test name
Test status
Simulation time 336498670000 ps
CPU time 708.69 seconds
Started Aug 12 04:26:41 PM PDT 24
Finished Aug 12 04:55:32 PM PDT 24
Peak memory 160236 kb
Host smart-2f0045ff-1939-4dd5-ba77-f9ce48b3d3f8
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1684666205 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.1684666205
Directory /workspace/11.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.3379075061
Short name T129
Test name
Test status
Simulation time 336377270000 ps
CPU time 587.45 seconds
Started Aug 12 04:26:21 PM PDT 24
Finished Aug 12 04:51:03 PM PDT 24
Peak memory 160444 kb
Host smart-180a0680-f52f-4362-885b-0315e11b0012
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3379075061 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.3379075061
Directory /workspace/12.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.971669907
Short name T30
Test name
Test status
Simulation time 336533570000 ps
CPU time 884.72 seconds
Started Aug 12 04:23:17 PM PDT 24
Finished Aug 12 05:00:06 PM PDT 24
Peak memory 160680 kb
Host smart-20882175-283a-44bc-a520-181ddb9d9284
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=971669907 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.971669907
Directory /workspace/13.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.903083319
Short name T140
Test name
Test status
Simulation time 337059470000 ps
CPU time 762.45 seconds
Started Aug 12 04:23:04 PM PDT 24
Finished Aug 12 04:54:43 PM PDT 24
Peak memory 160612 kb
Host smart-a57bdd56-f44a-4eb0-96c1-f9b5a0ddaadd
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=903083319 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.903083319
Directory /workspace/14.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.1837421726
Short name T123
Test name
Test status
Simulation time 336537010000 ps
CPU time 938.61 seconds
Started Aug 12 04:22:36 PM PDT 24
Finished Aug 12 05:01:41 PM PDT 24
Peak memory 160860 kb
Host smart-8c9e7b26-9f80-408b-bc9b-ed3475465a92
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1837421726 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.1837421726
Directory /workspace/15.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.1937229311
Short name T137
Test name
Test status
Simulation time 336868570000 ps
CPU time 815.27 seconds
Started Aug 12 04:24:05 PM PDT 24
Finished Aug 12 04:57:28 PM PDT 24
Peak memory 160660 kb
Host smart-73ae3a2c-de84-4bd8-9b86-96f7b2cdf751
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1937229311 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.1937229311
Directory /workspace/16.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.1860546268
Short name T114
Test name
Test status
Simulation time 336666430000 ps
CPU time 808.97 seconds
Started Aug 12 04:26:34 PM PDT 24
Finished Aug 12 04:59:26 PM PDT 24
Peak memory 160620 kb
Host smart-a3b3aae0-6dc6-453d-9c5d-05cc49a71aa3
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1860546268 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.1860546268
Directory /workspace/17.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.2098211866
Short name T131
Test name
Test status
Simulation time 336693010000 ps
CPU time 992.59 seconds
Started Aug 12 04:24:15 PM PDT 24
Finished Aug 12 05:05:22 PM PDT 24
Peak memory 160712 kb
Host smart-d61c081f-8bb3-4b26-8ae7-899eeb7d2255
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2098211866 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.2098211866
Directory /workspace/18.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.539329899
Short name T117
Test name
Test status
Simulation time 336869290000 ps
CPU time 723.1 seconds
Started Aug 12 04:26:00 PM PDT 24
Finished Aug 12 04:55:19 PM PDT 24
Peak memory 160560 kb
Host smart-33b5e040-6da5-4870-b4fb-261ca5c34655
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=539329899 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.539329899
Directory /workspace/19.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.1973668490
Short name T148
Test name
Test status
Simulation time 336926450000 ps
CPU time 1032.1 seconds
Started Aug 12 04:21:52 PM PDT 24
Finished Aug 12 05:04:19 PM PDT 24
Peak memory 160720 kb
Host smart-ee7ef8bd-4825-456f-9231-55ed4957fe2e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1973668490 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.1973668490
Directory /workspace/2.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.3847187754
Short name T141
Test name
Test status
Simulation time 336358030000 ps
CPU time 705.89 seconds
Started Aug 12 04:26:39 PM PDT 24
Finished Aug 12 04:55:27 PM PDT 24
Peak memory 160584 kb
Host smart-a21608a7-c9ff-46a7-89a8-eced35073ae8
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3847187754 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.3847187754
Directory /workspace/20.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.2628805734
Short name T143
Test name
Test status
Simulation time 336708850000 ps
CPU time 710.96 seconds
Started Aug 12 04:24:17 PM PDT 24
Finished Aug 12 04:53:47 PM PDT 24
Peak memory 160628 kb
Host smart-0e6d8432-34d3-4223-b9c6-ee876a62bec1
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2628805734 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.2628805734
Directory /workspace/21.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.3991193915
Short name T145
Test name
Test status
Simulation time 337059470000 ps
CPU time 706.25 seconds
Started Aug 12 04:25:52 PM PDT 24
Finished Aug 12 04:54:52 PM PDT 24
Peak memory 160684 kb
Host smart-e1b313b0-d500-4e22-83c1-486386afc650
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3991193915 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.3991193915
Directory /workspace/22.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.3130107646
Short name T144
Test name
Test status
Simulation time 336920330000 ps
CPU time 727.73 seconds
Started Aug 12 04:26:25 PM PDT 24
Finished Aug 12 04:56:01 PM PDT 24
Peak memory 159368 kb
Host smart-f16ea79a-a70e-4985-bada-4adc1616fd28
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3130107646 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.3130107646
Directory /workspace/23.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.759558969
Short name T112
Test name
Test status
Simulation time 336683310000 ps
CPU time 756.22 seconds
Started Aug 12 04:26:32 PM PDT 24
Finished Aug 12 04:57:10 PM PDT 24
Peak memory 160616 kb
Host smart-f3c333ee-fd9f-4c0f-af40-c39998317e92
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=759558969 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.759558969
Directory /workspace/24.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.2231268218
Short name T146
Test name
Test status
Simulation time 336820550000 ps
CPU time 706.37 seconds
Started Aug 12 04:25:47 PM PDT 24
Finished Aug 12 04:55:09 PM PDT 24
Peak memory 158980 kb
Host smart-17b4f8c5-9dd7-407e-b530-c37703a5236d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2231268218 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.2231268218
Directory /workspace/25.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1600951001
Short name T128
Test name
Test status
Simulation time 336465430000 ps
CPU time 689.78 seconds
Started Aug 12 04:26:14 PM PDT 24
Finished Aug 12 04:54:31 PM PDT 24
Peak memory 160188 kb
Host smart-8abb5225-2c31-48d4-9468-7cbfb6abd9ca
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1600951001 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.1600951001
Directory /workspace/26.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.2833161851
Short name T29
Test name
Test status
Simulation time 336831170000 ps
CPU time 690.64 seconds
Started Aug 12 04:25:55 PM PDT 24
Finished Aug 12 04:54:09 PM PDT 24
Peak memory 159772 kb
Host smart-bb44ad5d-16df-4917-821e-4bed8252197c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2833161851 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.2833161851
Directory /workspace/27.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.2743590235
Short name T116
Test name
Test status
Simulation time 336879130000 ps
CPU time 637.32 seconds
Started Aug 12 04:25:46 PM PDT 24
Finished Aug 12 04:51:49 PM PDT 24
Peak memory 158752 kb
Host smart-47aa080b-7e14-424b-a608-3444194899be
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2743590235 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.2743590235
Directory /workspace/28.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.447323799
Short name T6
Test name
Test status
Simulation time 336526310000 ps
CPU time 922.08 seconds
Started Aug 12 04:23:49 PM PDT 24
Finished Aug 12 05:01:48 PM PDT 24
Peak memory 160692 kb
Host smart-a9d1e354-529c-422d-83b2-317b2a192593
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=447323799 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.447323799
Directory /workspace/29.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.552381355
Short name T134
Test name
Test status
Simulation time 337075030000 ps
CPU time 691.26 seconds
Started Aug 12 04:26:40 PM PDT 24
Finished Aug 12 04:55:31 PM PDT 24
Peak memory 160480 kb
Host smart-4b49fb4b-4e5c-4fa8-80b7-3099b3f709d8
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=552381355 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.552381355
Directory /workspace/3.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.272500295
Short name T130
Test name
Test status
Simulation time 336798630000 ps
CPU time 1053.93 seconds
Started Aug 12 04:23:32 PM PDT 24
Finished Aug 12 05:07:38 PM PDT 24
Peak memory 160656 kb
Host smart-66e8f910-a9bc-4bbc-a8ea-6441ec889e91
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=272500295 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.272500295
Directory /workspace/30.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.1985308483
Short name T113
Test name
Test status
Simulation time 336635390000 ps
CPU time 941.19 seconds
Started Aug 12 04:21:54 PM PDT 24
Finished Aug 12 05:01:22 PM PDT 24
Peak memory 160860 kb
Host smart-696a258d-61a4-4f9e-928e-44135c20d068
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1985308483 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.1985308483
Directory /workspace/31.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.1126587933
Short name T142
Test name
Test status
Simulation time 336789210000 ps
CPU time 1014.13 seconds
Started Aug 12 04:24:10 PM PDT 24
Finished Aug 12 05:05:50 PM PDT 24
Peak memory 160624 kb
Host smart-f5ebd009-0073-4f6c-b237-982b97fc7ed2
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1126587933 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.1126587933
Directory /workspace/32.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.1631187006
Short name T139
Test name
Test status
Simulation time 336741450000 ps
CPU time 880.3 seconds
Started Aug 12 04:22:37 PM PDT 24
Finished Aug 12 04:58:53 PM PDT 24
Peak memory 160540 kb
Host smart-2a7793e5-a2b0-4fcf-bb6b-81215eb49363
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1631187006 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.1631187006
Directory /workspace/33.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.399237893
Short name T133
Test name
Test status
Simulation time 337075950000 ps
CPU time 599.96 seconds
Started Aug 12 04:26:28 PM PDT 24
Finished Aug 12 04:51:53 PM PDT 24
Peak memory 160320 kb
Host smart-032781be-6dba-4566-acd9-1addb5a172d8
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=399237893 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.399237893
Directory /workspace/34.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.649911911
Short name T120
Test name
Test status
Simulation time 336483230000 ps
CPU time 700.51 seconds
Started Aug 12 04:26:16 PM PDT 24
Finished Aug 12 04:55:31 PM PDT 24
Peak memory 159304 kb
Host smart-28787529-5058-4a5b-a14d-4cd2676db104
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=649911911 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.649911911
Directory /workspace/35.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.4283116824
Short name T119
Test name
Test status
Simulation time 336326450000 ps
CPU time 706.82 seconds
Started Aug 12 04:26:16 PM PDT 24
Finished Aug 12 04:55:47 PM PDT 24
Peak memory 159224 kb
Host smart-48aa61f5-34df-402e-8ffc-c359b3d26c2e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4283116824 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.4283116824
Directory /workspace/36.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.2723005802
Short name T115
Test name
Test status
Simulation time 336386350000 ps
CPU time 1048.25 seconds
Started Aug 12 04:24:43 PM PDT 24
Finished Aug 12 05:07:29 PM PDT 24
Peak memory 160624 kb
Host smart-5f078c55-acb2-4fef-a945-babc92811dbb
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2723005802 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.2723005802
Directory /workspace/37.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.1884399914
Short name T136
Test name
Test status
Simulation time 336522930000 ps
CPU time 1077.58 seconds
Started Aug 12 04:22:28 PM PDT 24
Finished Aug 12 05:06:16 PM PDT 24
Peak memory 160624 kb
Host smart-390fd7e4-d0ba-457c-b732-2d2614cc569f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1884399914 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.1884399914
Directory /workspace/38.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.4228527712
Short name T149
Test name
Test status
Simulation time 336308170000 ps
CPU time 1039.27 seconds
Started Aug 12 04:23:30 PM PDT 24
Finished Aug 12 05:06:50 PM PDT 24
Peak memory 160664 kb
Host smart-04605e27-2fc3-4eb6-935d-46c6dae392f8
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4228527712 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.4228527712
Directory /workspace/39.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.4223381765
Short name T5
Test name
Test status
Simulation time 336796650000 ps
CPU time 740.65 seconds
Started Aug 12 04:26:31 PM PDT 24
Finished Aug 12 04:57:57 PM PDT 24
Peak memory 160400 kb
Host smart-79a0b1cf-24cc-4af7-acbc-9315ad82b487
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4223381765 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.4223381765
Directory /workspace/4.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.2880481465
Short name T24
Test name
Test status
Simulation time 336892910000 ps
CPU time 737.96 seconds
Started Aug 12 04:27:13 PM PDT 24
Finished Aug 12 04:57:11 PM PDT 24
Peak memory 159132 kb
Host smart-82c45d80-ff81-4991-acc9-4b8f1b747904
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2880481465 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.2880481465
Directory /workspace/40.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.2411087389
Short name T122
Test name
Test status
Simulation time 336403370000 ps
CPU time 722.72 seconds
Started Aug 12 04:26:25 PM PDT 24
Finished Aug 12 04:56:35 PM PDT 24
Peak memory 160344 kb
Host smart-64ffae49-4b36-42a4-90eb-ab5853b01289
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2411087389 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.2411087389
Directory /workspace/41.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.3752222601
Short name T138
Test name
Test status
Simulation time 336606770000 ps
CPU time 1052.31 seconds
Started Aug 12 04:22:40 PM PDT 24
Finished Aug 12 05:06:32 PM PDT 24
Peak memory 160628 kb
Host smart-aa5b6f17-4619-4340-8fd6-763f8c99a9c1
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3752222601 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.3752222601
Directory /workspace/42.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.2381662169
Short name T111
Test name
Test status
Simulation time 336367410000 ps
CPU time 940.23 seconds
Started Aug 12 04:22:26 PM PDT 24
Finished Aug 12 05:00:24 PM PDT 24
Peak memory 160592 kb
Host smart-874308f9-5d97-4227-8572-dc6b2fbd1da8
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2381662169 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.2381662169
Directory /workspace/43.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.2848566099
Short name T28
Test name
Test status
Simulation time 336881190000 ps
CPU time 579.19 seconds
Started Aug 12 04:26:33 PM PDT 24
Finished Aug 12 04:50:32 PM PDT 24
Peak memory 160324 kb
Host smart-0bc05843-7182-4468-841b-94be663871b7
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2848566099 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.2848566099
Directory /workspace/44.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.1426093347
Short name T135
Test name
Test status
Simulation time 336525790000 ps
CPU time 670.46 seconds
Started Aug 12 04:26:34 PM PDT 24
Finished Aug 12 04:54:00 PM PDT 24
Peak memory 160228 kb
Host smart-2bf0f816-37b2-4ba4-bfbc-1cc4daaa35b1
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1426093347 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.1426093347
Directory /workspace/45.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.4289643093
Short name T147
Test name
Test status
Simulation time 336875290000 ps
CPU time 1014.98 seconds
Started Aug 12 04:22:35 PM PDT 24
Finished Aug 12 05:04:38 PM PDT 24
Peak memory 160712 kb
Host smart-2a4cdb32-1e2b-4369-b4d5-3001806466f5
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4289643093 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.4289643093
Directory /workspace/46.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.1354849116
Short name T126
Test name
Test status
Simulation time 336382990000 ps
CPU time 848.71 seconds
Started Aug 12 04:23:04 PM PDT 24
Finished Aug 12 04:57:42 PM PDT 24
Peak memory 160640 kb
Host smart-d8ba3bc1-e966-43da-9389-a14d81a11a67
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1354849116 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.1354849116
Directory /workspace/47.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.3223108449
Short name T124
Test name
Test status
Simulation time 336721630000 ps
CPU time 710.01 seconds
Started Aug 12 04:26:27 PM PDT 24
Finished Aug 12 04:55:38 PM PDT 24
Peak memory 159120 kb
Host smart-026310e7-1a33-445a-a909-4d5deef5b25b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3223108449 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.3223108449
Directory /workspace/48.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.157688989
Short name T25
Test name
Test status
Simulation time 336486010000 ps
CPU time 1079.31 seconds
Started Aug 12 04:22:04 PM PDT 24
Finished Aug 12 05:05:34 PM PDT 24
Peak memory 160644 kb
Host smart-5c20e5dd-3dda-4f04-99ec-6d45639de307
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=157688989 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.157688989
Directory /workspace/49.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.1036778905
Short name T127
Test name
Test status
Simulation time 336954030000 ps
CPU time 751.01 seconds
Started Aug 12 04:27:11 PM PDT 24
Finished Aug 12 04:57:32 PM PDT 24
Peak memory 160480 kb
Host smart-0b3e4bb5-baee-40a0-83d9-61be923b92f6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1036778905 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.1036778905
Directory /workspace/5.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.694682671
Short name T121
Test name
Test status
Simulation time 336514830000 ps
CPU time 749.13 seconds
Started Aug 12 04:26:30 PM PDT 24
Finished Aug 12 04:57:53 PM PDT 24
Peak memory 160140 kb
Host smart-6d977e1f-67f0-4ca8-af66-607654d196eb
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=694682671 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.694682671
Directory /workspace/6.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.41370880
Short name T26
Test name
Test status
Simulation time 336722610000 ps
CPU time 1036.21 seconds
Started Aug 12 04:22:59 PM PDT 24
Finished Aug 12 05:05:22 PM PDT 24
Peak memory 160612 kb
Host smart-df5b8cd2-c7ca-4d16-bf86-e18b001f5927
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=41370880 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.41370880
Directory /workspace/7.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.933808292
Short name T125
Test name
Test status
Simulation time 336661250000 ps
CPU time 747.53 seconds
Started Aug 12 04:23:00 PM PDT 24
Finished Aug 12 04:53:37 PM PDT 24
Peak memory 160624 kb
Host smart-2079254d-d2e1-4813-80b5-c7afe9385bbe
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=933808292 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.933808292
Directory /workspace/8.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.1529309385
Short name T27
Test name
Test status
Simulation time 336826810000 ps
CPU time 715.77 seconds
Started Aug 12 04:27:24 PM PDT 24
Finished Aug 12 04:56:17 PM PDT 24
Peak memory 160284 kb
Host smart-ce55ff08-4ced-45bd-9e97-1f4a4a249e91
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1529309385 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.1529309385
Directory /workspace/9.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.2214710624
Short name T88
Test name
Test status
Simulation time 336690410000 ps
CPU time 722.66 seconds
Started Aug 12 04:24:15 PM PDT 24
Finished Aug 12 04:54:10 PM PDT 24
Peak memory 160632 kb
Host smart-0136cfbd-6266-49f8-9515-f818a2a1cee5
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2214710624 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.2214710624
Directory /workspace/0.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.3927251067
Short name T79
Test name
Test status
Simulation time 336892010000 ps
CPU time 651.94 seconds
Started Aug 12 04:26:55 PM PDT 24
Finished Aug 12 04:53:43 PM PDT 24
Peak memory 159760 kb
Host smart-8b8865e0-9ec2-4179-983d-35ea0ea1ba1c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3927251067 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.3927251067
Directory /workspace/1.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.2724890475
Short name T99
Test name
Test status
Simulation time 336721070000 ps
CPU time 599.39 seconds
Started Aug 12 04:26:28 PM PDT 24
Finished Aug 12 04:51:19 PM PDT 24
Peak memory 160472 kb
Host smart-bce0c892-437c-4ae4-8101-8058099020aa
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2724890475 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.2724890475
Directory /workspace/10.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.3396842744
Short name T72
Test name
Test status
Simulation time 336883290000 ps
CPU time 1006.86 seconds
Started Aug 12 04:21:52 PM PDT 24
Finished Aug 12 05:03:47 PM PDT 24
Peak memory 160712 kb
Host smart-6db1e127-77a1-4ed1-863f-19b9b1ac0f31
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3396842744 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.3396842744
Directory /workspace/11.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.3259982022
Short name T92
Test name
Test status
Simulation time 336921570000 ps
CPU time 876.11 seconds
Started Aug 12 04:25:00 PM PDT 24
Finished Aug 12 05:01:28 PM PDT 24
Peak memory 160696 kb
Host smart-527f0f66-f0a6-4a3d-b632-2154107efc3b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3259982022 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.3259982022
Directory /workspace/12.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.3975035968
Short name T95
Test name
Test status
Simulation time 336677450000 ps
CPU time 1002.77 seconds
Started Aug 12 04:21:53 PM PDT 24
Finished Aug 12 05:03:25 PM PDT 24
Peak memory 160716 kb
Host smart-478f5406-f21c-4d61-8d87-4a544512ecbd
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3975035968 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.3975035968
Directory /workspace/14.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.20184370
Short name T81
Test name
Test status
Simulation time 336831610000 ps
CPU time 748.53 seconds
Started Aug 12 04:24:09 PM PDT 24
Finished Aug 12 04:54:56 PM PDT 24
Peak memory 160636 kb
Host smart-d1aacf7c-8429-407c-883e-1d4986ad6267
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=20184370 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.20184370
Directory /workspace/15.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.3824948797
Short name T93
Test name
Test status
Simulation time 336845730000 ps
CPU time 921.2 seconds
Started Aug 12 04:22:44 PM PDT 24
Finished Aug 12 04:59:54 PM PDT 24
Peak memory 160596 kb
Host smart-173d815f-b960-47d8-ab76-7ce0520a5d35
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3824948797 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.3824948797
Directory /workspace/16.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.36864800
Short name T91
Test name
Test status
Simulation time 336437650000 ps
CPU time 1055.62 seconds
Started Aug 12 04:23:29 PM PDT 24
Finished Aug 12 05:07:40 PM PDT 24
Peak memory 160664 kb
Host smart-42ab06b1-9ab6-4f85-9ecb-407a7421e783
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=36864800 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.36864800
Directory /workspace/17.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.1419534241
Short name T90
Test name
Test status
Simulation time 336347010000 ps
CPU time 726.71 seconds
Started Aug 12 04:23:48 PM PDT 24
Finished Aug 12 04:53:45 PM PDT 24
Peak memory 160632 kb
Host smart-15cebb30-df10-471d-b442-5d293c4c9170
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1419534241 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.1419534241
Directory /workspace/18.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.1385856996
Short name T89
Test name
Test status
Simulation time 336968210000 ps
CPU time 923.35 seconds
Started Aug 12 04:24:18 PM PDT 24
Finished Aug 12 05:02:55 PM PDT 24
Peak memory 160864 kb
Host smart-b3026a6a-2074-47af-8f2c-7631c00c089f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1385856996 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.1385856996
Directory /workspace/19.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.2704121336
Short name T104
Test name
Test status
Simulation time 336400610000 ps
CPU time 849.95 seconds
Started Aug 12 04:26:45 PM PDT 24
Finished Aug 12 05:01:08 PM PDT 24
Peak memory 160616 kb
Host smart-f73b6c5a-2784-40cf-a7a3-842d38485db8
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2704121336 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.2704121336
Directory /workspace/2.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.3077949653
Short name T20
Test name
Test status
Simulation time 336460090000 ps
CPU time 732.25 seconds
Started Aug 12 04:24:17 PM PDT 24
Finished Aug 12 04:54:50 PM PDT 24
Peak memory 160632 kb
Host smart-4e69a078-225f-4888-be73-6f58d1265454
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3077949653 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.3077949653
Directory /workspace/20.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.2485129728
Short name T78
Test name
Test status
Simulation time 336299610000 ps
CPU time 624.03 seconds
Started Aug 12 04:26:56 PM PDT 24
Finished Aug 12 04:52:21 PM PDT 24
Peak memory 160684 kb
Host smart-f51e472f-f295-4a56-8aa4-e4c734e5e9e2
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2485129728 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.2485129728
Directory /workspace/21.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.3263432823
Short name T14
Test name
Test status
Simulation time 336893590000 ps
CPU time 547.59 seconds
Started Aug 12 04:27:43 PM PDT 24
Finished Aug 12 04:50:37 PM PDT 24
Peak memory 160412 kb
Host smart-942e701a-97da-4088-8839-91b57fe9c32d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3263432823 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.3263432823
Directory /workspace/22.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.1982060626
Short name T21
Test name
Test status
Simulation time 336650950000 ps
CPU time 741.31 seconds
Started Aug 12 04:26:32 PM PDT 24
Finished Aug 12 04:56:54 PM PDT 24
Peak memory 160636 kb
Host smart-bdc7ea10-8b32-43f2-95d2-f13b2eafa193
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1982060626 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.1982060626
Directory /workspace/23.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.4096228640
Short name T71
Test name
Test status
Simulation time 336798270000 ps
CPU time 702.9 seconds
Started Aug 12 04:25:47 PM PDT 24
Finished Aug 12 04:55:00 PM PDT 24
Peak memory 158896 kb
Host smart-3ed7d634-37cc-4726-9861-00b7358d377e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4096228640 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.4096228640
Directory /workspace/24.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.641920861
Short name T86
Test name
Test status
Simulation time 336486050000 ps
CPU time 709.21 seconds
Started Aug 12 04:26:34 PM PDT 24
Finished Aug 12 04:56:03 PM PDT 24
Peak memory 160312 kb
Host smart-47a7b058-0a89-446e-acf5-914e071d1301
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=641920861 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.641920861
Directory /workspace/25.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.411386717
Short name T102
Test name
Test status
Simulation time 336866630000 ps
CPU time 736.75 seconds
Started Aug 12 04:26:00 PM PDT 24
Finished Aug 12 04:56:33 PM PDT 24
Peak memory 160500 kb
Host smart-8f22e783-f40a-4585-8fb1-9a451c44cca5
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=411386717 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.411386717
Directory /workspace/26.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.4130356921
Short name T16
Test name
Test status
Simulation time 336346390000 ps
CPU time 754.71 seconds
Started Aug 12 04:26:28 PM PDT 24
Finished Aug 12 04:57:22 PM PDT 24
Peak memory 160552 kb
Host smart-27960537-5b8e-4f3d-8e45-387fbe122349
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4130356921 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.4130356921
Directory /workspace/27.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.504486216
Short name T103
Test name
Test status
Simulation time 336989430000 ps
CPU time 891.54 seconds
Started Aug 12 04:23:19 PM PDT 24
Finished Aug 12 05:00:30 PM PDT 24
Peak memory 160684 kb
Host smart-2283db30-33b0-4a14-a08f-057140744588
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=504486216 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.504486216
Directory /workspace/28.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.592161717
Short name T96
Test name
Test status
Simulation time 336490910000 ps
CPU time 686.06 seconds
Started Aug 12 04:25:56 PM PDT 24
Finished Aug 12 04:54:00 PM PDT 24
Peak memory 160316 kb
Host smart-dfba7827-457f-4d41-80ff-5117ba93331c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=592161717 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.592161717
Directory /workspace/29.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.2450098843
Short name T73
Test name
Test status
Simulation time 336728950000 ps
CPU time 764.29 seconds
Started Aug 12 04:26:31 PM PDT 24
Finished Aug 12 04:58:32 PM PDT 24
Peak memory 160428 kb
Host smart-d49358d6-459c-4f77-adc1-f881b1d0d38b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2450098843 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.2450098843
Directory /workspace/3.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.2009431312
Short name T105
Test name
Test status
Simulation time 337046390000 ps
CPU time 668.41 seconds
Started Aug 12 04:25:47 PM PDT 24
Finished Aug 12 04:52:59 PM PDT 24
Peak memory 159284 kb
Host smart-79e7f85b-96f2-4cbe-89cb-351044705692
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2009431312 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.2009431312
Directory /workspace/30.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.763163668
Short name T19
Test name
Test status
Simulation time 337063770000 ps
CPU time 701.88 seconds
Started Aug 12 04:24:41 PM PDT 24
Finished Aug 12 04:53:56 PM PDT 24
Peak memory 160708 kb
Host smart-bc449194-42f2-466a-b76c-c5ee9b10f86b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=763163668 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.763163668
Directory /workspace/31.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.1099776038
Short name T97
Test name
Test status
Simulation time 336439770000 ps
CPU time 675.08 seconds
Started Aug 12 04:26:40 PM PDT 24
Finished Aug 12 04:54:30 PM PDT 24
Peak memory 160632 kb
Host smart-cc2c0195-329c-483b-94ed-c346f5ceaa4f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1099776038 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.1099776038
Directory /workspace/32.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.1335677161
Short name T18
Test name
Test status
Simulation time 336705630000 ps
CPU time 608.41 seconds
Started Aug 12 04:26:27 PM PDT 24
Finished Aug 12 04:51:31 PM PDT 24
Peak memory 159716 kb
Host smart-a70ae4f1-b0a7-4d6b-92d7-89c1487a5c74
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1335677161 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.1335677161
Directory /workspace/33.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.483412606
Short name T94
Test name
Test status
Simulation time 336907210000 ps
CPU time 689.06 seconds
Started Aug 12 04:26:16 PM PDT 24
Finished Aug 12 04:55:08 PM PDT 24
Peak memory 159588 kb
Host smart-c7bfbd02-8a82-4725-a5e1-582ff6c8b751
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=483412606 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.483412606
Directory /workspace/34.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.3057510876
Short name T98
Test name
Test status
Simulation time 336513570000 ps
CPU time 975.23 seconds
Started Aug 12 04:23:35 PM PDT 24
Finished Aug 12 05:04:10 PM PDT 24
Peak memory 160628 kb
Host smart-48f17fb6-739c-4802-b110-e3e4b0f14bda
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3057510876 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.3057510876
Directory /workspace/35.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.820737790
Short name T108
Test name
Test status
Simulation time 337086950000 ps
CPU time 909.53 seconds
Started Aug 12 04:24:09 PM PDT 24
Finished Aug 12 05:02:35 PM PDT 24
Peak memory 160860 kb
Host smart-cf3ead12-499a-475c-aba4-492d9f186f57
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=820737790 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.820737790
Directory /workspace/36.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.229161980
Short name T110
Test name
Test status
Simulation time 336899210000 ps
CPU time 891.77 seconds
Started Aug 12 04:23:09 PM PDT 24
Finished Aug 12 05:00:17 PM PDT 24
Peak memory 160684 kb
Host smart-873be6a9-65bf-4ce7-8cce-635f69167fb1
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=229161980 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.229161980
Directory /workspace/37.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3824162398
Short name T74
Test name
Test status
Simulation time 336894370000 ps
CPU time 803.74 seconds
Started Aug 12 04:26:34 PM PDT 24
Finished Aug 12 04:59:18 PM PDT 24
Peak memory 160624 kb
Host smart-6ed20ab2-d0fa-4ac2-9028-96d6b0212793
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3824162398 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.3824162398
Directory /workspace/38.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.1177436022
Short name T17
Test name
Test status
Simulation time 336926450000 ps
CPU time 617.33 seconds
Started Aug 12 04:26:33 PM PDT 24
Finished Aug 12 04:51:51 PM PDT 24
Peak memory 160348 kb
Host smart-a42664e6-babc-456d-9087-134b39ef299f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1177436022 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.1177436022
Directory /workspace/39.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.1347097815
Short name T75
Test name
Test status
Simulation time 336351630000 ps
CPU time 821.95 seconds
Started Aug 12 04:22:17 PM PDT 24
Finished Aug 12 04:55:45 PM PDT 24
Peak memory 160620 kb
Host smart-779c0529-2b14-49df-aaa7-53138fb95af6
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1347097815 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.1347097815
Directory /workspace/4.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.232357096
Short name T22
Test name
Test status
Simulation time 336579550000 ps
CPU time 609.41 seconds
Started Aug 12 04:26:25 PM PDT 24
Finished Aug 12 04:51:13 PM PDT 24
Peak memory 160452 kb
Host smart-e094a1dc-aac2-4958-a9d3-5b68fa301dcc
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=232357096 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.232357096
Directory /workspace/40.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.716993600
Short name T106
Test name
Test status
Simulation time 336673750000 ps
CPU time 708.72 seconds
Started Aug 12 04:26:17 PM PDT 24
Finished Aug 12 04:55:37 PM PDT 24
Peak memory 159388 kb
Host smart-f653d856-6375-45f2-baed-405630c63593
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=716993600 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.716993600
Directory /workspace/41.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.1330283868
Short name T82
Test name
Test status
Simulation time 336473390000 ps
CPU time 869.56 seconds
Started Aug 12 04:21:47 PM PDT 24
Finished Aug 12 04:57:50 PM PDT 24
Peak memory 160664 kb
Host smart-3e9f59a6-38f2-4b06-b49c-6f3765784446
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1330283868 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.1330283868
Directory /workspace/42.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.25168435
Short name T107
Test name
Test status
Simulation time 337064590000 ps
CPU time 909.13 seconds
Started Aug 12 04:21:48 PM PDT 24
Finished Aug 12 04:59:23 PM PDT 24
Peak memory 160668 kb
Host smart-ec293ed0-87a6-47e3-b777-8ac8914f31f2
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=25168435 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.25168435
Directory /workspace/43.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.2616850915
Short name T23
Test name
Test status
Simulation time 336499930000 ps
CPU time 730.62 seconds
Started Aug 12 04:27:13 PM PDT 24
Finished Aug 12 04:56:55 PM PDT 24
Peak memory 159172 kb
Host smart-609deef0-0c0f-432b-853b-c44c6d4b5b97
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2616850915 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.2616850915
Directory /workspace/44.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.203502980
Short name T109
Test name
Test status
Simulation time 336910910000 ps
CPU time 885.49 seconds
Started Aug 12 04:22:38 PM PDT 24
Finished Aug 12 04:59:06 PM PDT 24
Peak memory 160544 kb
Host smart-541d0c2f-5f8f-4c7a-aa64-161c3ac35bdf
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=203502980 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.203502980
Directory /workspace/45.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.2182045269
Short name T87
Test name
Test status
Simulation time 336966410000 ps
CPU time 756.04 seconds
Started Aug 12 04:26:27 PM PDT 24
Finished Aug 12 04:57:01 PM PDT 24
Peak memory 160260 kb
Host smart-7d66e2ee-06be-445f-a1ec-ea5ecd51b40b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2182045269 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.2182045269
Directory /workspace/46.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.2188150696
Short name T83
Test name
Test status
Simulation time 336542850000 ps
CPU time 702.71 seconds
Started Aug 12 04:25:59 PM PDT 24
Finished Aug 12 04:54:24 PM PDT 24
Peak memory 160480 kb
Host smart-187f0332-a5eb-4aec-9f1b-3e9875705176
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2188150696 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.2188150696
Directory /workspace/47.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1687313565
Short name T101
Test name
Test status
Simulation time 336984850000 ps
CPU time 950.97 seconds
Started Aug 12 04:21:53 PM PDT 24
Finished Aug 12 05:01:25 PM PDT 24
Peak memory 160864 kb
Host smart-b57148fa-dcdd-4af9-97dc-8fd515b19148
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1687313565 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.1687313565
Directory /workspace/48.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.1695822506
Short name T77
Test name
Test status
Simulation time 336359830000 ps
CPU time 605.69 seconds
Started Aug 12 04:26:41 PM PDT 24
Finished Aug 12 04:51:35 PM PDT 24
Peak memory 159760 kb
Host smart-e7077aaa-b15c-47f8-9b27-8c4d97a4af7f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1695822506 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.1695822506
Directory /workspace/49.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.554483742
Short name T100
Test name
Test status
Simulation time 336999990000 ps
CPU time 717.09 seconds
Started Aug 12 04:27:24 PM PDT 24
Finished Aug 12 04:56:35 PM PDT 24
Peak memory 160324 kb
Host smart-f4b88964-5b7b-411a-83c5-6a29fbaae3ed
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=554483742 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.554483742
Directory /workspace/5.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.803420973
Short name T80
Test name
Test status
Simulation time 336347210000 ps
CPU time 726.3 seconds
Started Aug 12 04:23:00 PM PDT 24
Finished Aug 12 04:52:54 PM PDT 24
Peak memory 160628 kb
Host smart-3e194dd5-08ad-4fd4-a6fc-ced79ff26248
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=803420973 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.803420973
Directory /workspace/6.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.2110081527
Short name T84
Test name
Test status
Simulation time 336748810000 ps
CPU time 1059.04 seconds
Started Aug 12 04:22:39 PM PDT 24
Finished Aug 12 05:05:59 PM PDT 24
Peak memory 160668 kb
Host smart-5bb337bc-cba1-40ea-a5fe-b6efb9318d66
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2110081527 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.2110081527
Directory /workspace/7.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.2725371343
Short name T85
Test name
Test status
Simulation time 337021990000 ps
CPU time 677.13 seconds
Started Aug 12 04:26:32 PM PDT 24
Finished Aug 12 04:53:59 PM PDT 24
Peak memory 160444 kb
Host smart-3dba7ec6-bd5f-4fb8-a70f-03c8bf3f29f9
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2725371343 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.2725371343
Directory /workspace/8.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.3880336343
Short name T76
Test name
Test status
Simulation time 337054530000 ps
CPU time 602.21 seconds
Started Aug 12 04:26:16 PM PDT 24
Finished Aug 12 04:51:17 PM PDT 24
Peak memory 160284 kb
Host smart-a866dc1f-4ea3-4a99-b126-649f2351bec9
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3880336343 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.3880336343
Directory /workspace/9.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.777458902
Short name T183
Test name
Test status
Simulation time 1400250000 ps
CPU time 4.69 seconds
Started Aug 12 04:21:56 PM PDT 24
Finished Aug 12 04:22:07 PM PDT 24
Peak memory 164656 kb
Host smart-e5f3850e-6dcb-4caf-b133-e448f7d654c2
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=777458902 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.777458902
Directory /workspace/0.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.1957425771
Short name T161
Test name
Test status
Simulation time 1536130000 ps
CPU time 3.91 seconds
Started Aug 12 04:26:11 PM PDT 24
Finished Aug 12 04:26:20 PM PDT 24
Peak memory 163308 kb
Host smart-39f0b6f0-b348-4ec3-a423-3b79ca6cb8f7
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1957425771 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.1957425771
Directory /workspace/1.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.218559300
Short name T194
Test name
Test status
Simulation time 1326670000 ps
CPU time 3.83 seconds
Started Aug 12 04:26:16 PM PDT 24
Finished Aug 12 04:26:24 PM PDT 24
Peak memory 163824 kb
Host smart-43b8ab73-31ef-45fe-8d41-ea635239d491
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=218559300 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.218559300
Directory /workspace/10.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.314556050
Short name T165
Test name
Test status
Simulation time 1358370000 ps
CPU time 3.53 seconds
Started Aug 12 04:23:26 PM PDT 24
Finished Aug 12 04:23:34 PM PDT 24
Peak memory 164628 kb
Host smart-eb768346-caa3-4e20-8822-0b1fbe97452c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=314556050 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.314556050
Directory /workspace/11.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.2713206190
Short name T178
Test name
Test status
Simulation time 1544050000 ps
CPU time 5.99 seconds
Started Aug 12 04:24:57 PM PDT 24
Finished Aug 12 04:25:10 PM PDT 24
Peak memory 164744 kb
Host smart-98299915-e547-4d77-9f52-69ba0cc59507
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2713206190 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.2713206190
Directory /workspace/12.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.1931744654
Short name T175
Test name
Test status
Simulation time 1535290000 ps
CPU time 4.61 seconds
Started Aug 12 04:26:00 PM PDT 24
Finished Aug 12 04:26:10 PM PDT 24
Peak memory 164636 kb
Host smart-52ac85a8-266d-4b54-871e-7cfe09413260
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1931744654 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.1931744654
Directory /workspace/13.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.758743695
Short name T182
Test name
Test status
Simulation time 925730000 ps
CPU time 3.38 seconds
Started Aug 12 04:23:36 PM PDT 24
Finished Aug 12 04:23:44 PM PDT 24
Peak memory 164800 kb
Host smart-f9489a26-3efa-4c6e-ad45-1f7246bfa713
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=758743695 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.758743695
Directory /workspace/14.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.754206876
Short name T180
Test name
Test status
Simulation time 1341570000 ps
CPU time 3.67 seconds
Started Aug 12 04:26:45 PM PDT 24
Finished Aug 12 04:26:54 PM PDT 24
Peak memory 164708 kb
Host smart-6c29fc5b-faa6-4414-b93d-c9ab1228d43a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=754206876 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.754206876
Directory /workspace/15.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.3929733658
Short name T186
Test name
Test status
Simulation time 1245150000 ps
CPU time 4.47 seconds
Started Aug 12 04:21:42 PM PDT 24
Finished Aug 12 04:21:52 PM PDT 24
Peak memory 164688 kb
Host smart-330b9503-c722-4220-a37e-5a95f005ca9b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3929733658 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.3929733658
Directory /workspace/16.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.2854555388
Short name T184
Test name
Test status
Simulation time 1537590000 ps
CPU time 5.11 seconds
Started Aug 12 04:24:10 PM PDT 24
Finished Aug 12 04:24:21 PM PDT 24
Peak memory 164792 kb
Host smart-02fb36f3-65d0-4224-a8f1-bd9c85fe26de
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2854555388 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.2854555388
Directory /workspace/17.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.2864763374
Short name T156
Test name
Test status
Simulation time 1292490000 ps
CPU time 4.91 seconds
Started Aug 12 04:22:36 PM PDT 24
Finished Aug 12 04:22:47 PM PDT 24
Peak memory 165004 kb
Host smart-b93d9416-2d3c-4e27-ad02-8e9416885b7a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2864763374 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.2864763374
Directory /workspace/18.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.3299177640
Short name T172
Test name
Test status
Simulation time 1546050000 ps
CPU time 5.39 seconds
Started Aug 12 04:22:43 PM PDT 24
Finished Aug 12 04:22:56 PM PDT 24
Peak memory 164744 kb
Host smart-8ebb7163-c496-4fe3-a9de-3c0621059348
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3299177640 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.3299177640
Directory /workspace/19.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.1504715361
Short name T163
Test name
Test status
Simulation time 1509630000 ps
CPU time 3.71 seconds
Started Aug 12 04:26:27 PM PDT 24
Finished Aug 12 04:26:36 PM PDT 24
Peak memory 163816 kb
Host smart-14792a18-5afb-4adc-8fd8-c5e9b1271a8f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1504715361 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.1504715361
Directory /workspace/2.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.1238450715
Short name T164
Test name
Test status
Simulation time 1601970000 ps
CPU time 3.83 seconds
Started Aug 12 04:26:53 PM PDT 24
Finished Aug 12 04:27:02 PM PDT 24
Peak memory 165848 kb
Host smart-cf648e66-7995-4657-820c-8f4d85f760cd
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1238450715 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.1238450715
Directory /workspace/20.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.821385189
Short name T191
Test name
Test status
Simulation time 1453210000 ps
CPU time 4.07 seconds
Started Aug 12 04:26:56 PM PDT 24
Finished Aug 12 04:27:05 PM PDT 24
Peak memory 166212 kb
Host smart-dca84ea3-336a-4993-b37e-c118b78d495d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=821385189 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.821385189
Directory /workspace/21.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.3997916503
Short name T195
Test name
Test status
Simulation time 1367310000 ps
CPU time 3.77 seconds
Started Aug 12 04:24:27 PM PDT 24
Finished Aug 12 04:24:35 PM PDT 24
Peak memory 164716 kb
Host smart-3b6a8b1a-d2ec-446a-bd48-79690728d632
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3997916503 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.3997916503
Directory /workspace/22.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.2804545735
Short name T190
Test name
Test status
Simulation time 1528410000 ps
CPU time 4.25 seconds
Started Aug 12 04:25:46 PM PDT 24
Finished Aug 12 04:25:56 PM PDT 24
Peak memory 163912 kb
Host smart-75ccceac-4ddc-4409-9648-1be3ab106c3e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2804545735 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.2804545735
Directory /workspace/23.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.1771025938
Short name T159
Test name
Test status
Simulation time 1322250000 ps
CPU time 4.22 seconds
Started Aug 12 04:25:47 PM PDT 24
Finished Aug 12 04:25:56 PM PDT 24
Peak memory 165956 kb
Host smart-bcfb8908-9343-404b-9362-795dea4b062d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1771025938 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.1771025938
Directory /workspace/24.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.1606800324
Short name T151
Test name
Test status
Simulation time 1576190000 ps
CPU time 4.78 seconds
Started Aug 12 04:25:46 PM PDT 24
Finished Aug 12 04:25:57 PM PDT 24
Peak memory 163780 kb
Host smart-b440352a-e8ea-46d2-9451-f6a018251088
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1606800324 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.1606800324
Directory /workspace/25.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2223213804
Short name T193
Test name
Test status
Simulation time 1304610000 ps
CPU time 4.63 seconds
Started Aug 12 04:23:51 PM PDT 24
Finished Aug 12 04:24:01 PM PDT 24
Peak memory 164732 kb
Host smart-5cbd1f2c-589f-4b64-abe1-446111aef61d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2223213804 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.2223213804
Directory /workspace/26.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.1461111807
Short name T179
Test name
Test status
Simulation time 1378230000 ps
CPU time 3.89 seconds
Started Aug 12 04:25:55 PM PDT 24
Finished Aug 12 04:26:04 PM PDT 24
Peak memory 163904 kb
Host smart-536ae7fd-889d-4793-a06e-b639403d3891
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1461111807 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.1461111807
Directory /workspace/27.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.3461723777
Short name T157
Test name
Test status
Simulation time 1570850000 ps
CPU time 3.84 seconds
Started Aug 12 04:26:41 PM PDT 24
Finished Aug 12 04:26:49 PM PDT 24
Peak memory 164688 kb
Host smart-0ce7190c-4e12-4e79-a1a3-fe034f003ad7
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3461723777 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.3461723777
Directory /workspace/28.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.3124774996
Short name T181
Test name
Test status
Simulation time 1186890000 ps
CPU time 3.67 seconds
Started Aug 12 04:23:39 PM PDT 24
Finished Aug 12 04:23:47 PM PDT 24
Peak memory 164732 kb
Host smart-6ce58ca4-5bfd-4e9f-85fd-fd823191b7c4
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3124774996 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.3124774996
Directory /workspace/29.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.1701356729
Short name T176
Test name
Test status
Simulation time 1456770000 ps
CPU time 4.91 seconds
Started Aug 12 04:23:12 PM PDT 24
Finished Aug 12 04:23:22 PM PDT 24
Peak memory 164776 kb
Host smart-3b6d2aa1-c43c-4cfd-a7a7-8d2404bb50c5
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1701356729 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.1701356729
Directory /workspace/3.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.964069381
Short name T162
Test name
Test status
Simulation time 1309190000 ps
CPU time 3.38 seconds
Started Aug 12 04:26:27 PM PDT 24
Finished Aug 12 04:26:34 PM PDT 24
Peak memory 163564 kb
Host smart-6815ce78-c276-4903-b136-3ed130f6d9cf
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=964069381 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.964069381
Directory /workspace/30.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.3845342670
Short name T154
Test name
Test status
Simulation time 1386490000 ps
CPU time 3.58 seconds
Started Aug 12 04:26:28 PM PDT 24
Finished Aug 12 04:26:36 PM PDT 24
Peak memory 164396 kb
Host smart-47c76903-fea6-4803-8680-51cd70bb28e9
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3845342670 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.3845342670
Directory /workspace/31.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.651713322
Short name T177
Test name
Test status
Simulation time 1256190000 ps
CPU time 3.81 seconds
Started Aug 12 04:26:18 PM PDT 24
Finished Aug 12 04:26:27 PM PDT 24
Peak memory 163540 kb
Host smart-933ec4f2-f585-4371-9b28-1e5a4833851a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=651713322 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.651713322
Directory /workspace/32.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.420140066
Short name T196
Test name
Test status
Simulation time 1288090000 ps
CPU time 3.83 seconds
Started Aug 12 04:26:19 PM PDT 24
Finished Aug 12 04:26:27 PM PDT 24
Peak memory 164152 kb
Host smart-e1abef57-363f-4853-8a60-9b53b5d90356
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=420140066 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.420140066
Directory /workspace/33.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.4066721492
Short name T200
Test name
Test status
Simulation time 1179630000 ps
CPU time 3.86 seconds
Started Aug 12 04:26:18 PM PDT 24
Finished Aug 12 04:26:27 PM PDT 24
Peak memory 164128 kb
Host smart-92fc5bc6-ddc0-4e8c-8d9b-2e4e590a795c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4066721492 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.4066721492
Directory /workspace/34.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.1837003813
Short name T174
Test name
Test status
Simulation time 1471390000 ps
CPU time 4.05 seconds
Started Aug 12 04:26:26 PM PDT 24
Finished Aug 12 04:26:36 PM PDT 24
Peak memory 164268 kb
Host smart-5a3b8a8f-8856-4a4a-8e4e-67fe7de57b92
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1837003813 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.1837003813
Directory /workspace/35.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.1020396132
Short name T170
Test name
Test status
Simulation time 1623910000 ps
CPU time 4.38 seconds
Started Aug 12 04:26:28 PM PDT 24
Finished Aug 12 04:26:39 PM PDT 24
Peak memory 164268 kb
Host smart-f6544860-1180-4425-90c0-f708b0577d0f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1020396132 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.1020396132
Directory /workspace/36.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1567185837
Short name T169
Test name
Test status
Simulation time 1411190000 ps
CPU time 3.72 seconds
Started Aug 12 04:22:39 PM PDT 24
Finished Aug 12 04:22:47 PM PDT 24
Peak memory 164512 kb
Host smart-a6a5c1f8-b0bf-4011-b9ff-c82a8556aae2
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1567185837 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.1567185837
Directory /workspace/37.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.849804143
Short name T187
Test name
Test status
Simulation time 1497150000 ps
CPU time 3.6 seconds
Started Aug 12 04:26:20 PM PDT 24
Finished Aug 12 04:26:27 PM PDT 24
Peak memory 163664 kb
Host smart-2bf2aecf-ddd5-4e11-a884-0b2e8db0617a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=849804143 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.849804143
Directory /workspace/38.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.4208438357
Short name T152
Test name
Test status
Simulation time 1437610000 ps
CPU time 3.34 seconds
Started Aug 12 04:26:25 PM PDT 24
Finished Aug 12 04:26:33 PM PDT 24
Peak memory 164528 kb
Host smart-6a456845-841a-44e4-99d3-69ea7cf24bcf
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4208438357 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.4208438357
Directory /workspace/39.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.1783300985
Short name T166
Test name
Test status
Simulation time 1527270000 ps
CPU time 3.61 seconds
Started Aug 12 04:26:45 PM PDT 24
Finished Aug 12 04:26:54 PM PDT 24
Peak memory 164704 kb
Host smart-688bdbdd-45ab-44a9-b6bc-80a064ac7060
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1783300985 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.1783300985
Directory /workspace/4.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.721356286
Short name T199
Test name
Test status
Simulation time 1614670000 ps
CPU time 4.61 seconds
Started Aug 12 04:26:17 PM PDT 24
Finished Aug 12 04:26:28 PM PDT 24
Peak memory 164156 kb
Host smart-45866698-668f-4946-9d0c-a82de1e2679d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=721356286 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.721356286
Directory /workspace/40.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.512447372
Short name T189
Test name
Test status
Simulation time 1496350000 ps
CPU time 3.79 seconds
Started Aug 12 04:26:33 PM PDT 24
Finished Aug 12 04:26:42 PM PDT 24
Peak memory 164280 kb
Host smart-1b873aa9-8a2b-4ed7-9027-0074d63e7865
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=512447372 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.512447372
Directory /workspace/41.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.3069662528
Short name T198
Test name
Test status
Simulation time 1611950000 ps
CPU time 6.18 seconds
Started Aug 12 04:22:49 PM PDT 24
Finished Aug 12 04:23:03 PM PDT 24
Peak memory 164816 kb
Host smart-0215e58f-f6b1-4efe-95fa-6122d49a8a0e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3069662528 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.3069662528
Directory /workspace/42.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.2016983785
Short name T158
Test name
Test status
Simulation time 1401330000 ps
CPU time 3.49 seconds
Started Aug 12 04:26:33 PM PDT 24
Finished Aug 12 04:26:41 PM PDT 24
Peak memory 164396 kb
Host smart-0846a1d9-af2e-4f8d-ba16-cfe0ceba20be
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2016983785 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.2016983785
Directory /workspace/43.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.546046216
Short name T168
Test name
Test status
Simulation time 1348410000 ps
CPU time 4.37 seconds
Started Aug 12 04:21:56 PM PDT 24
Finished Aug 12 04:22:06 PM PDT 24
Peak memory 164764 kb
Host smart-39d191bd-8936-4e57-afb5-d3abb3267dd0
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=546046216 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.546046216
Directory /workspace/44.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.1915101243
Short name T197
Test name
Test status
Simulation time 1543290000 ps
CPU time 6.21 seconds
Started Aug 12 04:23:41 PM PDT 24
Finished Aug 12 04:23:55 PM PDT 24
Peak memory 164756 kb
Host smart-d6123f7f-9eeb-4f81-b0c0-e6c73123b44f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1915101243 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.1915101243
Directory /workspace/45.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.945776551
Short name T192
Test name
Test status
Simulation time 1609330000 ps
CPU time 5.14 seconds
Started Aug 12 04:24:44 PM PDT 24
Finished Aug 12 04:24:55 PM PDT 24
Peak memory 164800 kb
Host smart-d04ce76b-6295-4e25-be9a-723280d3a93f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=945776551 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.945776551
Directory /workspace/46.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.240643178
Short name T153
Test name
Test status
Simulation time 1259530000 ps
CPU time 3.47 seconds
Started Aug 12 04:26:33 PM PDT 24
Finished Aug 12 04:26:41 PM PDT 24
Peak memory 163328 kb
Host smart-6caebb1a-8fa8-4e49-aa37-8df01acc2a31
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=240643178 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.240643178
Directory /workspace/47.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.770257730
Short name T173
Test name
Test status
Simulation time 1459590000 ps
CPU time 3.52 seconds
Started Aug 12 04:25:45 PM PDT 24
Finished Aug 12 04:25:53 PM PDT 24
Peak memory 163740 kb
Host smart-f1de4a4a-cc0e-46d9-91fd-f647119ab162
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=770257730 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.770257730
Directory /workspace/48.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.446963566
Short name T188
Test name
Test status
Simulation time 1471390000 ps
CPU time 4.55 seconds
Started Aug 12 04:21:47 PM PDT 24
Finished Aug 12 04:21:57 PM PDT 24
Peak memory 164736 kb
Host smart-60152824-d80c-4bb1-a579-d7f423d3a24b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=446963566 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.446963566
Directory /workspace/49.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.942308901
Short name T185
Test name
Test status
Simulation time 1426170000 ps
CPU time 3.99 seconds
Started Aug 12 04:26:30 PM PDT 24
Finished Aug 12 04:26:39 PM PDT 24
Peak memory 165204 kb
Host smart-0fcb7b04-1ec9-44d8-9e4f-4c8ba18d00fa
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=942308901 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.942308901
Directory /workspace/5.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.546219336
Short name T167
Test name
Test status
Simulation time 1358230000 ps
CPU time 4.15 seconds
Started Aug 12 04:27:23 PM PDT 24
Finished Aug 12 04:27:32 PM PDT 24
Peak memory 163824 kb
Host smart-c62271ab-a6aa-466c-96f7-21d4beeb19f6
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=546219336 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.546219336
Directory /workspace/6.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.4154056987
Short name T160
Test name
Test status
Simulation time 1341870000 ps
CPU time 3.98 seconds
Started Aug 12 04:22:27 PM PDT 24
Finished Aug 12 04:22:36 PM PDT 24
Peak memory 164772 kb
Host smart-072cde34-de2e-4c57-b8ba-dddb824b0fd1
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4154056987 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.4154056987
Directory /workspace/7.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.914230965
Short name T171
Test name
Test status
Simulation time 1477710000 ps
CPU time 3.74 seconds
Started Aug 12 04:26:31 PM PDT 24
Finished Aug 12 04:26:40 PM PDT 24
Peak memory 163440 kb
Host smart-79cf9ede-3df4-4f35-8681-186da7e7877e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=914230965 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.914230965
Directory /workspace/8.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2722080866
Short name T155
Test name
Test status
Simulation time 1394770000 ps
CPU time 3.75 seconds
Started Aug 12 04:26:45 PM PDT 24
Finished Aug 12 04:26:54 PM PDT 24
Peak memory 164556 kb
Host smart-0ebef09a-1b33-4cf0-901f-e49e10070058
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2722080866 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.2722080866
Directory /workspace/9.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.2131700549
Short name T54
Test name
Test status
Simulation time 1400930000 ps
CPU time 4.58 seconds
Started Aug 12 04:26:26 PM PDT 24
Finished Aug 12 04:26:36 PM PDT 24
Peak memory 164676 kb
Host smart-a2853b0c-36f5-4124-8849-71aecea9f43e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2131700549 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.2131700549
Directory /workspace/1.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.4105113613
Short name T69
Test name
Test status
Simulation time 1543590000 ps
CPU time 4.43 seconds
Started Aug 12 04:26:34 PM PDT 24
Finished Aug 12 04:26:44 PM PDT 24
Peak memory 164564 kb
Host smart-1c1212b2-91d5-49ec-8a93-f8c7f33ed839
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4105113613 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.4105113613
Directory /workspace/10.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.2729458498
Short name T66
Test name
Test status
Simulation time 1537010000 ps
CPU time 4.48 seconds
Started Aug 12 04:26:14 PM PDT 24
Finished Aug 12 04:26:24 PM PDT 24
Peak memory 165760 kb
Host smart-d9b68568-c207-49ee-9852-a1bf59f94e3f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2729458498 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.2729458498
Directory /workspace/11.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.3791973827
Short name T51
Test name
Test status
Simulation time 1273150000 ps
CPU time 3.43 seconds
Started Aug 12 04:26:45 PM PDT 24
Finished Aug 12 04:26:53 PM PDT 24
Peak memory 164564 kb
Host smart-9d208439-9b08-4053-81ba-e8198ff0cde5
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3791973827 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.3791973827
Directory /workspace/12.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.3258733163
Short name T9
Test name
Test status
Simulation time 1526290000 ps
CPU time 4.56 seconds
Started Aug 12 04:24:30 PM PDT 24
Finished Aug 12 04:24:40 PM PDT 24
Peak memory 164796 kb
Host smart-80f523ab-9282-4fad-97bb-c5dc7ed517d5
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3258733163 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.3258733163
Directory /workspace/13.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.3109624151
Short name T49
Test name
Test status
Simulation time 1497890000 ps
CPU time 4.89 seconds
Started Aug 12 04:26:24 PM PDT 24
Finished Aug 12 04:26:35 PM PDT 24
Peak memory 164716 kb
Host smart-9ca1be7d-38bd-476b-8568-793acb737a7e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3109624151 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.3109624151
Directory /workspace/14.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.100574208
Short name T62
Test name
Test status
Simulation time 1549090000 ps
CPU time 5.06 seconds
Started Aug 12 04:26:57 PM PDT 24
Finished Aug 12 04:27:08 PM PDT 24
Peak memory 164740 kb
Host smart-6898c36d-e7d2-4b3b-b7c3-db5ac4bf37cb
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=100574208 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.100574208
Directory /workspace/15.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.2262443084
Short name T39
Test name
Test status
Simulation time 1481030000 ps
CPU time 4.71 seconds
Started Aug 12 04:26:45 PM PDT 24
Finished Aug 12 04:26:55 PM PDT 24
Peak memory 164780 kb
Host smart-6de85ae5-5bc7-4563-a723-f6219a460fdb
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2262443084 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.2262443084
Directory /workspace/16.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.3139015650
Short name T3
Test name
Test status
Simulation time 1359710000 ps
CPU time 3.81 seconds
Started Aug 12 04:26:31 PM PDT 24
Finished Aug 12 04:26:39 PM PDT 24
Peak memory 164496 kb
Host smart-023914b7-811d-48ae-901c-2c5c37bcab84
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3139015650 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.3139015650
Directory /workspace/17.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.3315887900
Short name T12
Test name
Test status
Simulation time 1633430000 ps
CPU time 4.48 seconds
Started Aug 12 04:26:38 PM PDT 24
Finished Aug 12 04:26:48 PM PDT 24
Peak memory 166100 kb
Host smart-182e8ed3-e544-4c97-8855-41aea533a0c4
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3315887900 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.3315887900
Directory /workspace/18.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.1384079832
Short name T68
Test name
Test status
Simulation time 1457570000 ps
CPU time 4.37 seconds
Started Aug 12 04:26:55 PM PDT 24
Finished Aug 12 04:27:05 PM PDT 24
Peak memory 164716 kb
Host smart-2f9ad025-3426-4267-97bc-584bdbe9f4d1
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1384079832 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.1384079832
Directory /workspace/19.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.1323787684
Short name T2
Test name
Test status
Simulation time 1615870000 ps
CPU time 4.46 seconds
Started Aug 12 04:23:33 PM PDT 24
Finished Aug 12 04:23:43 PM PDT 24
Peak memory 164632 kb
Host smart-0e05e58f-a838-480f-9009-0cdecb3e2f35
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1323787684 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.1323787684
Directory /workspace/2.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.2531326944
Short name T67
Test name
Test status
Simulation time 1516930000 ps
CPU time 4.24 seconds
Started Aug 12 04:23:29 PM PDT 24
Finished Aug 12 04:23:39 PM PDT 24
Peak memory 164636 kb
Host smart-57500f2f-4b8f-4528-8ed0-dc7ef0c24691
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2531326944 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.2531326944
Directory /workspace/20.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.4230207172
Short name T57
Test name
Test status
Simulation time 1419470000 ps
CPU time 4.69 seconds
Started Aug 12 04:24:58 PM PDT 24
Finished Aug 12 04:25:08 PM PDT 24
Peak memory 164716 kb
Host smart-4bf1c904-cdbc-4c31-9ee3-52bd3c17900f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4230207172 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.4230207172
Directory /workspace/21.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.4056368237
Short name T8
Test name
Test status
Simulation time 1446010000 ps
CPU time 4.4 seconds
Started Aug 12 04:23:36 PM PDT 24
Finished Aug 12 04:23:46 PM PDT 24
Peak memory 164780 kb
Host smart-853aeda6-6f6a-4d7f-b2f4-2780036437be
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4056368237 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.4056368237
Directory /workspace/22.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.2801420146
Short name T63
Test name
Test status
Simulation time 1567110000 ps
CPU time 4.36 seconds
Started Aug 12 04:26:57 PM PDT 24
Finished Aug 12 04:27:06 PM PDT 24
Peak memory 166304 kb
Host smart-bcab9dea-49a0-4d09-897e-3ee1691b7783
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2801420146 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.2801420146
Directory /workspace/23.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.2620022460
Short name T42
Test name
Test status
Simulation time 1523270000 ps
CPU time 4.53 seconds
Started Aug 12 04:26:25 PM PDT 24
Finished Aug 12 04:26:35 PM PDT 24
Peak memory 163940 kb
Host smart-77bfffc4-3782-4964-8a22-237ada46fbc0
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2620022460 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.2620022460
Directory /workspace/24.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.3336306844
Short name T65
Test name
Test status
Simulation time 1535450000 ps
CPU time 4.29 seconds
Started Aug 12 04:25:46 PM PDT 24
Finished Aug 12 04:25:56 PM PDT 24
Peak memory 163908 kb
Host smart-8eccd32b-cfdd-4bd9-b2cb-63e958d5f69f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3336306844 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.3336306844
Directory /workspace/25.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.3394731151
Short name T11
Test name
Test status
Simulation time 1380670000 ps
CPU time 3.73 seconds
Started Aug 12 04:26:14 PM PDT 24
Finished Aug 12 04:26:23 PM PDT 24
Peak memory 164320 kb
Host smart-be9cbbad-50ea-4c18-91fd-4c965dd8f7e2
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3394731151 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.3394731151
Directory /workspace/26.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.86660035
Short name T50
Test name
Test status
Simulation time 1456870000 ps
CPU time 3.84 seconds
Started Aug 12 04:26:14 PM PDT 24
Finished Aug 12 04:26:23 PM PDT 24
Peak memory 164016 kb
Host smart-692b52eb-cb22-4adb-8989-492e0c35ca25
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=86660035 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.86660035
Directory /workspace/27.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.1064934720
Short name T33
Test name
Test status
Simulation time 1417190000 ps
CPU time 3.89 seconds
Started Aug 12 04:25:47 PM PDT 24
Finished Aug 12 04:25:56 PM PDT 24
Peak memory 163380 kb
Host smart-103937a1-a78c-4021-b352-bc1746666007
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1064934720 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.1064934720
Directory /workspace/28.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.2717628560
Short name T56
Test name
Test status
Simulation time 1155710000 ps
CPU time 4.09 seconds
Started Aug 12 04:21:54 PM PDT 24
Finished Aug 12 04:22:03 PM PDT 24
Peak memory 164740 kb
Host smart-cd7ac323-e539-4c7a-8eeb-7c369abb6e34
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2717628560 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.2717628560
Directory /workspace/29.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.551261381
Short name T37
Test name
Test status
Simulation time 1473850000 ps
CPU time 4.21 seconds
Started Aug 12 04:27:10 PM PDT 24
Finished Aug 12 04:27:20 PM PDT 24
Peak memory 164396 kb
Host smart-5cc1d437-2e40-4561-aeb0-f5fb47d7836d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=551261381 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.551261381
Directory /workspace/3.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.242669298
Short name T1
Test name
Test status
Simulation time 1345470000 ps
CPU time 4.23 seconds
Started Aug 12 04:26:24 PM PDT 24
Finished Aug 12 04:26:33 PM PDT 24
Peak memory 164972 kb
Host smart-73dc8e6b-2640-4793-bd9b-f31c3d4ac4cf
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=242669298 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.242669298
Directory /workspace/30.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.4071768436
Short name T52
Test name
Test status
Simulation time 1431770000 ps
CPU time 5.54 seconds
Started Aug 12 04:24:54 PM PDT 24
Finished Aug 12 04:25:07 PM PDT 24
Peak memory 164744 kb
Host smart-4c6f3cdd-c2b8-494e-9eb1-6168cbf62b27
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4071768436 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.4071768436
Directory /workspace/31.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.585810202
Short name T44
Test name
Test status
Simulation time 1276070000 ps
CPU time 4.38 seconds
Started Aug 12 04:24:53 PM PDT 24
Finished Aug 12 04:25:03 PM PDT 24
Peak memory 164772 kb
Host smart-3f66cac3-8029-4f82-97bc-3e4811d93f96
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=585810202 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.585810202
Directory /workspace/32.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.3835753631
Short name T61
Test name
Test status
Simulation time 1413350000 ps
CPU time 4.49 seconds
Started Aug 12 04:23:00 PM PDT 24
Finished Aug 12 04:23:10 PM PDT 24
Peak memory 164732 kb
Host smart-06615775-5a2b-4632-95e4-92e048375a75
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3835753631 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.3835753631
Directory /workspace/33.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.1396324705
Short name T40
Test name
Test status
Simulation time 1310470000 ps
CPU time 3.88 seconds
Started Aug 12 04:26:28 PM PDT 24
Finished Aug 12 04:26:37 PM PDT 24
Peak memory 164268 kb
Host smart-f8a580ae-a8ee-4ae1-91e6-35f1e05e8952
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1396324705 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.1396324705
Directory /workspace/34.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.2488788881
Short name T34
Test name
Test status
Simulation time 1370070000 ps
CPU time 4.24 seconds
Started Aug 12 04:26:19 PM PDT 24
Finished Aug 12 04:26:29 PM PDT 24
Peak memory 164256 kb
Host smart-30ae75a9-083f-4b7a-9109-3e424c3cebbd
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2488788881 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.2488788881
Directory /workspace/35.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.2252809593
Short name T70
Test name
Test status
Simulation time 1132310000 ps
CPU time 3.96 seconds
Started Aug 12 04:23:59 PM PDT 24
Finished Aug 12 04:24:07 PM PDT 24
Peak memory 164744 kb
Host smart-7cd29c29-589b-4fea-bef3-24007e8ba551
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2252809593 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.2252809593
Directory /workspace/36.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.2146340911
Short name T4
Test name
Test status
Simulation time 1392670000 ps
CPU time 3.55 seconds
Started Aug 12 04:26:32 PM PDT 24
Finished Aug 12 04:26:41 PM PDT 24
Peak memory 164256 kb
Host smart-3ee3c912-6d70-4bce-a62b-db86bf746980
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2146340911 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.2146340911
Directory /workspace/37.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.3306884013
Short name T55
Test name
Test status
Simulation time 1359870000 ps
CPU time 4.34 seconds
Started Aug 12 04:24:22 PM PDT 24
Finished Aug 12 04:24:31 PM PDT 24
Peak memory 164744 kb
Host smart-a11636ed-bd60-4b49-ae58-9c6a80e67717
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3306884013 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.3306884013
Directory /workspace/38.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.793703332
Short name T47
Test name
Test status
Simulation time 1473010000 ps
CPU time 4.63 seconds
Started Aug 12 04:23:29 PM PDT 24
Finished Aug 12 04:23:39 PM PDT 24
Peak memory 164708 kb
Host smart-4f2e365b-72aa-43e9-a016-dbc36c1a120f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=793703332 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.793703332
Directory /workspace/39.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.1994552282
Short name T41
Test name
Test status
Simulation time 1313370000 ps
CPU time 3.34 seconds
Started Aug 12 04:27:11 PM PDT 24
Finished Aug 12 04:27:19 PM PDT 24
Peak memory 164524 kb
Host smart-23729a2e-d6be-4644-b582-eda1fd5ceac2
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1994552282 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.1994552282
Directory /workspace/4.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.356388895
Short name T45
Test name
Test status
Simulation time 1369650000 ps
CPU time 3.61 seconds
Started Aug 12 04:26:25 PM PDT 24
Finished Aug 12 04:26:33 PM PDT 24
Peak memory 164516 kb
Host smart-2a315a5b-95f4-46d4-80c3-fe6929ebd882
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=356388895 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.356388895
Directory /workspace/40.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.4062172688
Short name T32
Test name
Test status
Simulation time 1445190000 ps
CPU time 5.12 seconds
Started Aug 12 04:25:15 PM PDT 24
Finished Aug 12 04:25:27 PM PDT 24
Peak memory 164732 kb
Host smart-4788cf0a-c3c3-44d0-8a69-ed80b29b785a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4062172688 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.4062172688
Directory /workspace/41.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.3535828526
Short name T59
Test name
Test status
Simulation time 1427330000 ps
CPU time 3.96 seconds
Started Aug 12 04:27:13 PM PDT 24
Finished Aug 12 04:27:22 PM PDT 24
Peak memory 164356 kb
Host smart-b5664099-880c-4dc9-b6c5-1dbf697ea412
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3535828526 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.3535828526
Directory /workspace/42.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.607258431
Short name T10
Test name
Test status
Simulation time 1531190000 ps
CPU time 4.21 seconds
Started Aug 12 04:26:32 PM PDT 24
Finished Aug 12 04:26:41 PM PDT 24
Peak memory 164420 kb
Host smart-af1985e0-514e-4bf4-9dbb-67c385702a84
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=607258431 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.607258431
Directory /workspace/43.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.1128978085
Short name T60
Test name
Test status
Simulation time 1400050000 ps
CPU time 3.95 seconds
Started Aug 12 04:26:17 PM PDT 24
Finished Aug 12 04:26:26 PM PDT 24
Peak memory 163852 kb
Host smart-da75269e-eb9b-48df-a1e4-27120bf90105
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1128978085 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.1128978085
Directory /workspace/44.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.824882131
Short name T43
Test name
Test status
Simulation time 1516470000 ps
CPU time 4.2 seconds
Started Aug 12 04:26:32 PM PDT 24
Finished Aug 12 04:26:41 PM PDT 24
Peak memory 164204 kb
Host smart-297eeae2-8b96-445e-bf6c-f19925ba264c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=824882131 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.824882131
Directory /workspace/45.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.620384062
Short name T38
Test name
Test status
Simulation time 1441650000 ps
CPU time 3.99 seconds
Started Aug 12 04:23:39 PM PDT 24
Finished Aug 12 04:23:48 PM PDT 24
Peak memory 164708 kb
Host smart-3f925412-7683-45ea-98b2-62a1080a4cab
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=620384062 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.620384062
Directory /workspace/46.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.2678649182
Short name T58
Test name
Test status
Simulation time 1467410000 ps
CPU time 3.6 seconds
Started Aug 12 04:26:45 PM PDT 24
Finished Aug 12 04:26:53 PM PDT 24
Peak memory 164472 kb
Host smart-a40531b0-42f5-4110-8d38-7b86662e2600
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2678649182 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.2678649182
Directory /workspace/47.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.2824360196
Short name T35
Test name
Test status
Simulation time 1345430000 ps
CPU time 4.06 seconds
Started Aug 12 04:21:49 PM PDT 24
Finished Aug 12 04:21:58 PM PDT 24
Peak memory 164768 kb
Host smart-30442aae-eaba-4bcd-a4fa-22da1dc46609
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2824360196 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.2824360196
Directory /workspace/48.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.3399164922
Short name T48
Test name
Test status
Simulation time 1500750000 ps
CPU time 3.6 seconds
Started Aug 12 04:26:44 PM PDT 24
Finished Aug 12 04:26:52 PM PDT 24
Peak memory 164472 kb
Host smart-26383128-5e4d-4c36-8483-35370adbf945
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3399164922 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.3399164922
Directory /workspace/49.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.3848699150
Short name T36
Test name
Test status
Simulation time 1453670000 ps
CPU time 3.85 seconds
Started Aug 12 04:26:30 PM PDT 24
Finished Aug 12 04:26:39 PM PDT 24
Peak memory 163984 kb
Host smart-b207c8f1-40b6-499a-a825-f8822710a2e5
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3848699150 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.3848699150
Directory /workspace/5.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.1594934193
Short name T31
Test name
Test status
Simulation time 1375450000 ps
CPU time 3.07 seconds
Started Aug 12 04:25:18 PM PDT 24
Finished Aug 12 04:25:25 PM PDT 24
Peak memory 163744 kb
Host smart-6f6585c3-1ab4-401d-97f0-99ce83487069
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1594934193 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.1594934193
Directory /workspace/6.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.1652748697
Short name T46
Test name
Test status
Simulation time 1545890000 ps
CPU time 4.36 seconds
Started Aug 12 04:26:21 PM PDT 24
Finished Aug 12 04:26:30 PM PDT 24
Peak memory 165832 kb
Host smart-c4d71dce-819c-4262-b5bf-8617281a9655
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1652748697 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.1652748697
Directory /workspace/7.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.2963238776
Short name T53
Test name
Test status
Simulation time 1189110000 ps
CPU time 3.7 seconds
Started Aug 12 04:26:13 PM PDT 24
Finished Aug 12 04:26:21 PM PDT 24
Peak memory 163548 kb
Host smart-8c0382e8-8e28-4348-948d-b981284ee0cd
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2963238776 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.2963238776
Directory /workspace/8.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.1509725965
Short name T64
Test name
Test status
Simulation time 1514370000 ps
CPU time 5.86 seconds
Started Aug 12 04:24:12 PM PDT 24
Finished Aug 12 04:24:26 PM PDT 24
Peak memory 164816 kb
Host smart-cf51ecec-64ff-4ed2-81f3-807702ce88b7
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1509725965 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.1509725965
Directory /workspace/9.prim_lfsr_gal_smoke/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%