Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.31 100.00 96.55 100.00 100.00 95.00


Total tests in report: 200
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
87.31 87.31 100.00 100.00 96.55 96.55 100.00 100.00 100.00 100.00 40.00 40.00 /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.855254240
95.31 8.00 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 80.00 40.00 /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.223780923
98.31 3.00 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 95.00 15.00 /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.2578205452

Tests that do not contribute to grading

Name
/workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.668412377
/workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.2987327978
/workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.3742771474
/workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.3135941696
/workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.3116227780
/workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.2850700244
/workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.3346890130
/workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.4047885612
/workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.157454223
/workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.2140096122
/workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.229597786
/workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.2122836362
/workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.559429480
/workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.4132108409
/workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.2972861941
/workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.4251079915
/workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.15354948
/workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.2120581606
/workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1856548137
/workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.665620080
/workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.3139461865
/workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.3434837248
/workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.3502436051
/workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.2379148315
/workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.1909260907
/workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.796860906
/workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.3291177288
/workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.3154669343
/workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.2347361055
/workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.286416878
/workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.3093368147
/workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.3548451503
/workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.1369093476
/workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.2112507921
/workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.4257109604
/workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.2685277609
/workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.2089189066
/workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.483937178
/workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.3846102985
/workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.2402560324
/workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.1458357137
/workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.1015330271
/workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.3742282726
/workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.3049125447
/workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.680305479
/workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.1003491093
/workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.1248245247
/workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.3932363382
/workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.3448347575
/workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.228783704
/workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.3699040416
/workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.1923721959
/workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.620862125
/workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.2118888373
/workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.241068658
/workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.1265003751
/workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.1259716675
/workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.2129393693
/workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.2956869306
/workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.2928813786
/workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.2263926737
/workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.395796594
/workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.593901822
/workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.3496263352
/workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.3070997125
/workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.1750758168
/workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.1951510384
/workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.1387119212
/workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.3399493281
/workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.1006051577
/workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.39415913
/workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.396798734
/workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.2787184242
/workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.3844052980
/workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.3163873421
/workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.1365728254
/workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.899485690
/workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.3927667738
/workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.2048063291
/workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.3075057676
/workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.1135539726
/workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.3919531788
/workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.3909919177
/workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.3693151209
/workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.1447078387
/workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.2330504579
/workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.4098226095
/workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.899896194
/workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.520864864
/workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.2818222221
/workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.1296611911
/workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.187810441
/workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.2788838477
/workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.877050460
/workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.35756443
/workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.3913893678
/workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.3174455624
/workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.3029380367
/workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.3493573063
/workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.1821185469
/workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.1244077070
/workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.769091277
/workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.3981355848
/workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.1410109390
/workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.2397605953
/workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.2454844036
/workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.2074715792
/workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.3438954772
/workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.1743476378
/workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.2695966074
/workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.556346363
/workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.1854648920
/workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3678182861
/workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.2850634114
/workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.3832148142
/workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.3393769495
/workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.1822527376
/workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.1505449952
/workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.3768660895
/workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.1932542225
/workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.4159438788
/workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.3459163177
/workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.1490643248
/workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.2036472198
/workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.2597011193
/workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.2570886765
/workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.1132022160
/workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.3399456351
/workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.1379231018
/workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.2009926600
/workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.3205809186
/workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.3262941654
/workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.2047201413
/workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.1938901199
/workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.3623407061
/workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.2948782453
/workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.803343739
/workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.3227727430
/workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.881639854
/workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.3078203106
/workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.1512562728
/workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.1124845042
/workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.3617022319
/workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.55598493
/workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.415481527
/workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.81430315
/workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1304746899
/workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2134304633
/workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.3006691096
/workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.3661224040
/workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.2663094884
/workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.4092639396
/workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.4119820691
/workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.3033520674
/workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.3544763684
/workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.3106803153
/workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.3280489103
/workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.2972106768
/workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.687835951
/workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.688861644
/workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.2355242832
/workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.1324901274
/workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.3260173407
/workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.558566921
/workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.4192691388
/workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.2033856381
/workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.2242362086
/workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.2267677408
/workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.112755352
/workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.2264271151
/workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.1602635935
/workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.1402132912
/workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.715253948
/workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.1453251454
/workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.1276653021
/workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.3668791047
/workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.275305962
/workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.528561214
/workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.3638583954
/workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.3984549333
/workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.1523043257
/workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.2270958112
/workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.3988786922
/workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.3486201158
/workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.3985539037
/workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.2341262668
/workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.3156842281
/workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.2335586804
/workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.731102073
/workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.943106288
/workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.3896752222
/workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.2570475213
/workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.4176607328
/workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.3411707274
/workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.3050939052
/workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.2309038009
/workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.1896815826



Total test records in report: 200
tests.html | tests1.html | tests2.html | tests3.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.4176607328 Aug 13 04:45:14 PM PDT 24 Aug 13 04:45:24 PM PDT 24 1439370000 ps
T2 /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.855254240 Aug 13 04:45:14 PM PDT 24 Aug 13 04:45:23 PM PDT 24 1434230000 ps
T3 /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.1324901274 Aug 13 04:45:13 PM PDT 24 Aug 13 04:45:23 PM PDT 24 1392430000 ps
T7 /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.2267677408 Aug 13 04:45:24 PM PDT 24 Aug 13 04:45:35 PM PDT 24 1321670000 ps
T8 /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.688861644 Aug 13 04:45:14 PM PDT 24 Aug 13 04:45:24 PM PDT 24 1475530000 ps
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T128 /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.2379148315 Aug 13 04:45:14 PM PDT 24 Aug 13 05:21:06 PM PDT 24 336452930000 ps
T129 /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.4047885612 Aug 13 04:45:04 PM PDT 24 Aug 13 05:16:48 PM PDT 24 337083930000 ps
T130 /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.796860906 Aug 13 04:45:11 PM PDT 24 Aug 13 05:13:59 PM PDT 24 336988170000 ps
T131 /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.3093368147 Aug 13 04:45:12 PM PDT 24 Aug 13 05:13:15 PM PDT 24 336441990000 ps
T132 /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.1003491093 Aug 13 04:45:02 PM PDT 24 Aug 13 05:15:54 PM PDT 24 336751390000 ps
T133 /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1856548137 Aug 13 04:45:05 PM PDT 24 Aug 13 05:21:39 PM PDT 24 336651670000 ps
T134 /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.3742282726 Aug 13 04:45:14 PM PDT 24 Aug 13 05:16:30 PM PDT 24 337145650000 ps
T135 /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.665620080 Aug 13 04:45:07 PM PDT 24 Aug 13 05:18:01 PM PDT 24 336959990000 ps
T136 /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.668412377 Aug 13 04:45:02 PM PDT 24 Aug 13 05:14:11 PM PDT 24 336667410000 ps
T137 /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.2987327978 Aug 13 04:45:02 PM PDT 24 Aug 13 05:22:59 PM PDT 24 337071050000 ps
T138 /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.2089189066 Aug 13 04:45:13 PM PDT 24 Aug 13 05:15:31 PM PDT 24 336598830000 ps
T139 /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.1015330271 Aug 13 04:45:12 PM PDT 24 Aug 13 05:19:46 PM PDT 24 336941330000 ps
T140 /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.3742771474 Aug 13 04:45:01 PM PDT 24 Aug 13 05:17:10 PM PDT 24 336785350000 ps
T141 /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.2850700244 Aug 13 04:45:05 PM PDT 24 Aug 13 05:21:41 PM PDT 24 336754030000 ps
T142 /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.4132108409 Aug 13 04:45:05 PM PDT 24 Aug 13 05:23:09 PM PDT 24 336786950000 ps
T143 /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.15354948 Aug 13 04:45:05 PM PDT 24 Aug 13 05:23:01 PM PDT 24 336425950000 ps
T144 /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.3932363382 Aug 13 04:45:03 PM PDT 24 Aug 13 05:15:59 PM PDT 24 337047570000 ps
T145 /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.3135941696 Aug 13 04:45:01 PM PDT 24 Aug 13 05:20:21 PM PDT 24 336856270000 ps
T146 /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.680305479 Aug 13 04:45:02 PM PDT 24 Aug 13 05:14:57 PM PDT 24 336746810000 ps
T147 /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.559429480 Aug 13 04:45:06 PM PDT 24 Aug 13 05:17:20 PM PDT 24 336970910000 ps
T148 /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.229597786 Aug 13 04:45:02 PM PDT 24 Aug 13 05:17:19 PM PDT 24 336999550000 ps
T149 /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.4257109604 Aug 13 04:45:13 PM PDT 24 Aug 13 05:25:31 PM PDT 24 337071070000 ps
T150 /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.1909260907 Aug 13 04:45:12 PM PDT 24 Aug 13 05:12:59 PM PDT 24 336657030000 ps
T151 /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.1379231018 Aug 13 04:45:26 PM PDT 24 Aug 13 04:45:40 PM PDT 24 1553450000 ps
T152 /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.3438954772 Aug 13 04:45:24 PM PDT 24 Aug 13 04:45:36 PM PDT 24 1516810000 ps
T153 /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3678182861 Aug 13 04:45:25 PM PDT 24 Aug 13 04:45:35 PM PDT 24 1221710000 ps
T154 /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.1512562728 Aug 13 04:45:30 PM PDT 24 Aug 13 04:45:38 PM PDT 24 1270750000 ps
T155 /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.1244077070 Aug 13 04:45:26 PM PDT 24 Aug 13 04:45:37 PM PDT 24 1444510000 ps
T156 /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.1124845042 Aug 13 04:45:27 PM PDT 24 Aug 13 04:45:34 PM PDT 24 1329910000 ps
T157 /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.1505449952 Aug 13 04:45:24 PM PDT 24 Aug 13 04:45:34 PM PDT 24 1331310000 ps
T158 /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.81430315 Aug 13 04:45:25 PM PDT 24 Aug 13 04:45:36 PM PDT 24 1510190000 ps
T159 /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.2397605953 Aug 13 04:45:24 PM PDT 24 Aug 13 04:45:36 PM PDT 24 1283450000 ps
T160 /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.3227727430 Aug 13 04:45:25 PM PDT 24 Aug 13 04:45:35 PM PDT 24 1526230000 ps
T161 /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2134304633 Aug 13 04:45:25 PM PDT 24 Aug 13 04:45:36 PM PDT 24 1443050000 ps
T162 /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.769091277 Aug 13 04:45:25 PM PDT 24 Aug 13 04:45:39 PM PDT 24 1523390000 ps
T163 /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.2850634114 Aug 13 04:45:24 PM PDT 24 Aug 13 04:45:33 PM PDT 24 1521150000 ps
T164 /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.3262941654 Aug 13 04:45:30 PM PDT 24 Aug 13 04:45:41 PM PDT 24 1429890000 ps
T165 /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.3205809186 Aug 13 04:45:31 PM PDT 24 Aug 13 04:45:41 PM PDT 24 1456810000 ps
T166 /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.3493573063 Aug 13 04:45:25 PM PDT 24 Aug 13 04:45:36 PM PDT 24 1487810000 ps
T167 /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.1822527376 Aug 13 04:45:21 PM PDT 24 Aug 13 04:45:32 PM PDT 24 1239170000 ps
T168 /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.3832148142 Aug 13 04:45:24 PM PDT 24 Aug 13 04:45:36 PM PDT 24 1483970000 ps
T169 /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.1490643248 Aug 13 04:45:27 PM PDT 24 Aug 13 04:45:35 PM PDT 24 1479450000 ps
T170 /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.2570886765 Aug 13 04:45:28 PM PDT 24 Aug 13 04:45:37 PM PDT 24 1169350000 ps
T171 /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.3399456351 Aug 13 04:45:26 PM PDT 24 Aug 13 04:45:37 PM PDT 24 1369490000 ps
T172 /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.1821185469 Aug 13 04:45:20 PM PDT 24 Aug 13 04:45:28 PM PDT 24 1470950000 ps
T173 /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.2948782453 Aug 13 04:45:31 PM PDT 24 Aug 13 04:45:40 PM PDT 24 1466530000 ps
T174 /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.1410109390 Aug 13 04:45:25 PM PDT 24 Aug 13 04:45:39 PM PDT 24 1540470000 ps
T175 /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1304746899 Aug 13 04:45:20 PM PDT 24 Aug 13 04:45:32 PM PDT 24 1393510000 ps
T176 /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.556346363 Aug 13 04:45:21 PM PDT 24 Aug 13 04:45:33 PM PDT 24 1454750000 ps
T177 /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.1938901199 Aug 13 04:45:32 PM PDT 24 Aug 13 04:45:44 PM PDT 24 1388510000 ps
T178 /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.1854648920 Aug 13 04:45:29 PM PDT 24 Aug 13 04:45:37 PM PDT 24 1186370000 ps
T179 /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.2695966074 Aug 13 04:45:19 PM PDT 24 Aug 13 04:45:28 PM PDT 24 1438650000 ps
T180 /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.3393769495 Aug 13 04:45:21 PM PDT 24 Aug 13 04:45:31 PM PDT 24 1410850000 ps
T181 /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.803343739 Aug 13 04:45:32 PM PDT 24 Aug 13 04:45:41 PM PDT 24 1531070000 ps
T182 /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.3617022319 Aug 13 04:45:29 PM PDT 24 Aug 13 04:45:36 PM PDT 24 1407050000 ps
T183 /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.2047201413 Aug 13 04:45:26 PM PDT 24 Aug 13 04:45:35 PM PDT 24 1322290000 ps
T184 /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.3459163177 Aug 13 04:45:22 PM PDT 24 Aug 13 04:45:33 PM PDT 24 1369510000 ps
T185 /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.2454844036 Aug 13 04:45:25 PM PDT 24 Aug 13 04:45:37 PM PDT 24 1543970000 ps
T186 /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.3623407061 Aug 13 04:45:30 PM PDT 24 Aug 13 04:45:42 PM PDT 24 1372410000 ps
T187 /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.3768660895 Aug 13 04:45:23 PM PDT 24 Aug 13 04:45:34 PM PDT 24 1513910000 ps
T188 /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.3078203106 Aug 13 04:45:28 PM PDT 24 Aug 13 04:45:39 PM PDT 24 1406790000 ps
T189 /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.2036472198 Aug 13 04:45:27 PM PDT 24 Aug 13 04:45:39 PM PDT 24 1553150000 ps
T190 /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.1932542225 Aug 13 04:45:29 PM PDT 24 Aug 13 04:45:37 PM PDT 24 1115150000 ps
T191 /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.1132022160 Aug 13 04:45:26 PM PDT 24 Aug 13 04:45:34 PM PDT 24 1292090000 ps
T192 /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.55598493 Aug 13 04:45:21 PM PDT 24 Aug 13 04:45:32 PM PDT 24 1562610000 ps
T193 /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.2597011193 Aug 13 04:45:25 PM PDT 24 Aug 13 04:45:33 PM PDT 24 1527450000 ps
T194 /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.1743476378 Aug 13 04:45:24 PM PDT 24 Aug 13 04:45:34 PM PDT 24 1211230000 ps
T195 /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.415481527 Aug 13 04:45:22 PM PDT 24 Aug 13 04:45:32 PM PDT 24 1529750000 ps
T196 /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.4159438788 Aug 13 04:45:29 PM PDT 24 Aug 13 04:45:39 PM PDT 24 1352770000 ps
T197 /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.2009926600 Aug 13 04:45:29 PM PDT 24 Aug 13 04:45:40 PM PDT 24 1334810000 ps
T198 /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.3981355848 Aug 13 04:45:25 PM PDT 24 Aug 13 04:45:38 PM PDT 24 1425290000 ps
T199 /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.2074715792 Aug 13 04:45:24 PM PDT 24 Aug 13 04:45:33 PM PDT 24 1329990000 ps
T200 /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.881639854 Aug 13 04:45:29 PM PDT 24 Aug 13 04:45:41 PM PDT 24 1605970000 ps

Test location /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.855254240
Short name T2
Test name
Test status
Simulation time 1434230000 ps
CPU time 3.79 seconds
Started Aug 13 04:45:14 PM PDT 24
Finished Aug 13 04:45:23 PM PDT 24
Peak memory 164804 kb
Host smart-4a8aa17d-94cf-4ce4-b949-1899c515559c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=855254240 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.855254240
Directory /workspace/10.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.223780923
Short name T21
Test name
Test status
Simulation time 336283170000 ps
CPU time 825.52 seconds
Started Aug 13 04:44:49 PM PDT 24
Finished Aug 13 05:18:14 PM PDT 24
Peak memory 160684 kb
Host smart-4c7e5614-b4a2-48a5-978a-faa87c3b5f9a
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=223780923 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.223780923
Directory /workspace/1.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.2578205452
Short name T29
Test name
Test status
Simulation time 336917250000 ps
CPU time 907.83 seconds
Started Aug 13 04:45:03 PM PDT 24
Finished Aug 13 05:22:29 PM PDT 24
Peak memory 160748 kb
Host smart-eaedbd37-6b0e-4745-ac60-51d988c08f08
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2578205452 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.2578205452
Directory /workspace/11.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.668412377
Short name T136
Test name
Test status
Simulation time 336667410000 ps
CPU time 715.02 seconds
Started Aug 13 04:45:02 PM PDT 24
Finished Aug 13 05:14:11 PM PDT 24
Peak memory 160724 kb
Host smart-a918c754-1d6a-4494-bb28-f7b6b03c886c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=668412377 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.668412377
Directory /workspace/0.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.2987327978
Short name T137
Test name
Test status
Simulation time 337071050000 ps
CPU time 920.84 seconds
Started Aug 13 04:45:02 PM PDT 24
Finished Aug 13 05:22:59 PM PDT 24
Peak memory 160740 kb
Host smart-0540e689-a4c3-4f05-b527-0fbf5c415986
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2987327978 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.2987327978
Directory /workspace/1.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.3742771474
Short name T140
Test name
Test status
Simulation time 336785350000 ps
CPU time 783.43 seconds
Started Aug 13 04:45:01 PM PDT 24
Finished Aug 13 05:17:10 PM PDT 24
Peak memory 160708 kb
Host smart-94ddbf6b-44f9-4e41-baf3-1279ab61917b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3742771474 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.3742771474
Directory /workspace/10.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.3135941696
Short name T145
Test name
Test status
Simulation time 336856270000 ps
CPU time 874.66 seconds
Started Aug 13 04:45:01 PM PDT 24
Finished Aug 13 05:20:21 PM PDT 24
Peak memory 160720 kb
Host smart-bbcc67ef-9563-4f1c-a5b0-187b551976e8
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3135941696 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.3135941696
Directory /workspace/12.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.3116227780
Short name T118
Test name
Test status
Simulation time 336990370000 ps
CPU time 621.81 seconds
Started Aug 13 04:45:00 PM PDT 24
Finished Aug 13 05:10:57 PM PDT 24
Peak memory 160832 kb
Host smart-458dd39b-6a2e-4246-9055-8ed68a8ede4c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3116227780 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.3116227780
Directory /workspace/13.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.2850700244
Short name T141
Test name
Test status
Simulation time 336754030000 ps
CPU time 895.84 seconds
Started Aug 13 04:45:05 PM PDT 24
Finished Aug 13 05:21:41 PM PDT 24
Peak memory 160696 kb
Host smart-c2eae0be-d2a2-4950-9995-f0eb45c50def
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2850700244 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.2850700244
Directory /workspace/14.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.3346890130
Short name T4
Test name
Test status
Simulation time 336670430000 ps
CPU time 794.3 seconds
Started Aug 13 04:44:59 PM PDT 24
Finished Aug 13 05:17:21 PM PDT 24
Peak memory 160780 kb
Host smart-d2c084da-a306-496c-9782-8a29ba5e8ddf
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3346890130 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.3346890130
Directory /workspace/15.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.4047885612
Short name T129
Test name
Test status
Simulation time 337083930000 ps
CPU time 776.34 seconds
Started Aug 13 04:45:04 PM PDT 24
Finished Aug 13 05:16:48 PM PDT 24
Peak memory 160828 kb
Host smart-c34939fb-b142-4f6e-84ee-196666f7e18f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4047885612 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.4047885612
Directory /workspace/16.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.157454223
Short name T126
Test name
Test status
Simulation time 336718850000 ps
CPU time 788.78 seconds
Started Aug 13 04:45:03 PM PDT 24
Finished Aug 13 05:17:17 PM PDT 24
Peak memory 160696 kb
Host smart-ee4ea2f8-69bf-4c85-bd80-3be7aa387268
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=157454223 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.157454223
Directory /workspace/17.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.2140096122
Short name T117
Test name
Test status
Simulation time 336590290000 ps
CPU time 778.28 seconds
Started Aug 13 04:45:04 PM PDT 24
Finished Aug 13 05:16:49 PM PDT 24
Peak memory 160820 kb
Host smart-7a2b5cd0-7a3d-4af8-94e7-2fa551569309
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2140096122 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.2140096122
Directory /workspace/18.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.229597786
Short name T148
Test name
Test status
Simulation time 336999550000 ps
CPU time 793.71 seconds
Started Aug 13 04:45:02 PM PDT 24
Finished Aug 13 05:17:19 PM PDT 24
Peak memory 160668 kb
Host smart-7f96fc8f-ee9d-432a-9fc7-9665d2312bef
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=229597786 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.229597786
Directory /workspace/19.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.2122836362
Short name T26
Test name
Test status
Simulation time 336409770000 ps
CPU time 726.42 seconds
Started Aug 13 04:45:01 PM PDT 24
Finished Aug 13 05:14:52 PM PDT 24
Peak memory 160732 kb
Host smart-74161716-1513-4921-907c-a499ea3c7a7a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2122836362 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.2122836362
Directory /workspace/2.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.559429480
Short name T147
Test name
Test status
Simulation time 336970910000 ps
CPU time 792.59 seconds
Started Aug 13 04:45:06 PM PDT 24
Finished Aug 13 05:17:20 PM PDT 24
Peak memory 160712 kb
Host smart-d01fb282-db47-45a0-b5c4-48237ca4c174
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=559429480 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.559429480
Directory /workspace/20.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.4132108409
Short name T142
Test name
Test status
Simulation time 336786950000 ps
CPU time 923.63 seconds
Started Aug 13 04:45:05 PM PDT 24
Finished Aug 13 05:23:09 PM PDT 24
Peak memory 160708 kb
Host smart-3a35aa6f-f316-4442-86d2-e3cae4732090
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4132108409 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.4132108409
Directory /workspace/21.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.2972861941
Short name T123
Test name
Test status
Simulation time 336758150000 ps
CPU time 888.7 seconds
Started Aug 13 04:45:10 PM PDT 24
Finished Aug 13 05:21:41 PM PDT 24
Peak memory 160692 kb
Host smart-355bb935-8fbb-44e6-b419-c3760632f842
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2972861941 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.2972861941
Directory /workspace/22.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.4251079915
Short name T120
Test name
Test status
Simulation time 336929390000 ps
CPU time 971.34 seconds
Started Aug 13 04:45:03 PM PDT 24
Finished Aug 13 05:25:26 PM PDT 24
Peak memory 160828 kb
Host smart-044d1bc5-4fc7-4f84-b6f1-1acde1967926
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4251079915 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.4251079915
Directory /workspace/23.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.15354948
Short name T143
Test name
Test status
Simulation time 336425950000 ps
CPU time 922.01 seconds
Started Aug 13 04:45:05 PM PDT 24
Finished Aug 13 05:23:01 PM PDT 24
Peak memory 160680 kb
Host smart-0ad7d263-be32-4fd6-b2bc-062e4ea25c3d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=15354948 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.15354948
Directory /workspace/24.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.2120581606
Short name T111
Test name
Test status
Simulation time 336973570000 ps
CPU time 664.12 seconds
Started Aug 13 04:45:01 PM PDT 24
Finished Aug 13 05:12:15 PM PDT 24
Peak memory 160744 kb
Host smart-942dd145-6308-4d75-a6c8-15087e72ae8a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2120581606 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.2120581606
Directory /workspace/25.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1856548137
Short name T133
Test name
Test status
Simulation time 336651670000 ps
CPU time 889.8 seconds
Started Aug 13 04:45:05 PM PDT 24
Finished Aug 13 05:21:39 PM PDT 24
Peak memory 160692 kb
Host smart-cedbc8bf-3a3d-4566-a0dc-87b6b288c4d6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1856548137 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.1856548137
Directory /workspace/26.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.665620080
Short name T135
Test name
Test status
Simulation time 336959990000 ps
CPU time 803.16 seconds
Started Aug 13 04:45:07 PM PDT 24
Finished Aug 13 05:18:01 PM PDT 24
Peak memory 160712 kb
Host smart-40209829-4637-4f64-8426-3bc72455844e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=665620080 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.665620080
Directory /workspace/27.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.3139461865
Short name T6
Test name
Test status
Simulation time 336588310000 ps
CPU time 796.64 seconds
Started Aug 13 04:45:01 PM PDT 24
Finished Aug 13 05:17:39 PM PDT 24
Peak memory 160728 kb
Host smart-ce640a27-6fd0-4c78-9c51-502879faa62f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3139461865 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.3139461865
Directory /workspace/28.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.3434837248
Short name T124
Test name
Test status
Simulation time 336449830000 ps
CPU time 772.65 seconds
Started Aug 13 04:45:13 PM PDT 24
Finished Aug 13 05:16:47 PM PDT 24
Peak memory 160744 kb
Host smart-9ec3b0ef-91e2-48d5-a653-4934e30fc3b7
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3434837248 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.3434837248
Directory /workspace/29.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.3502436051
Short name T27
Test name
Test status
Simulation time 336385990000 ps
CPU time 906.72 seconds
Started Aug 13 04:45:02 PM PDT 24
Finished Aug 13 05:22:23 PM PDT 24
Peak memory 160740 kb
Host smart-ba7c3ad7-471d-4620-8aee-a740bab11d24
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3502436051 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.3502436051
Directory /workspace/3.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.2379148315
Short name T128
Test name
Test status
Simulation time 336452930000 ps
CPU time 879.05 seconds
Started Aug 13 04:45:14 PM PDT 24
Finished Aug 13 05:21:06 PM PDT 24
Peak memory 160816 kb
Host smart-510878d3-10aa-4c94-85cc-f1c5c60321e6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2379148315 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.2379148315
Directory /workspace/30.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.1909260907
Short name T150
Test name
Test status
Simulation time 336657030000 ps
CPU time 686.58 seconds
Started Aug 13 04:45:12 PM PDT 24
Finished Aug 13 05:12:59 PM PDT 24
Peak memory 160832 kb
Host smart-c12ac657-2e08-4563-819a-56369ef70fea
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1909260907 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.1909260907
Directory /workspace/31.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.796860906
Short name T130
Test name
Test status
Simulation time 336988170000 ps
CPU time 697.51 seconds
Started Aug 13 04:45:11 PM PDT 24
Finished Aug 13 05:13:59 PM PDT 24
Peak memory 160696 kb
Host smart-11f8ff2e-4c8e-4a55-8e5b-a1784adf1e20
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=796860906 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.796860906
Directory /workspace/32.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.3291177288
Short name T125
Test name
Test status
Simulation time 336586610000 ps
CPU time 789 seconds
Started Aug 13 04:45:11 PM PDT 24
Finished Aug 13 05:17:44 PM PDT 24
Peak memory 160732 kb
Host smart-845ede79-d53b-48ee-9ea5-a24fcce37e39
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3291177288 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.3291177288
Directory /workspace/33.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.3154669343
Short name T122
Test name
Test status
Simulation time 336890430000 ps
CPU time 783.4 seconds
Started Aug 13 04:45:13 PM PDT 24
Finished Aug 13 05:17:12 PM PDT 24
Peak memory 160744 kb
Host smart-842da9f0-c91b-4010-ae35-0fddea2f8706
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3154669343 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.3154669343
Directory /workspace/34.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.2347361055
Short name T24
Test name
Test status
Simulation time 336732650000 ps
CPU time 703.97 seconds
Started Aug 13 04:45:10 PM PDT 24
Finished Aug 13 05:13:52 PM PDT 24
Peak memory 160744 kb
Host smart-9c3c28bc-d63e-47bb-b78a-3e80f842e353
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2347361055 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.2347361055
Directory /workspace/35.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.286416878
Short name T121
Test name
Test status
Simulation time 336551190000 ps
CPU time 794.76 seconds
Started Aug 13 04:45:11 PM PDT 24
Finished Aug 13 05:17:44 PM PDT 24
Peak memory 160744 kb
Host smart-4f662145-12c1-4054-b426-dfa74994c9f0
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=286416878 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.286416878
Directory /workspace/36.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.3093368147
Short name T131
Test name
Test status
Simulation time 336441990000 ps
CPU time 691.3 seconds
Started Aug 13 04:45:12 PM PDT 24
Finished Aug 13 05:13:15 PM PDT 24
Peak memory 160744 kb
Host smart-19c9da60-2457-4ea6-ae98-c2ccd9ee845f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3093368147 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.3093368147
Directory /workspace/37.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.3548451503
Short name T116
Test name
Test status
Simulation time 336508890000 ps
CPU time 757.88 seconds
Started Aug 13 04:45:14 PM PDT 24
Finished Aug 13 05:16:20 PM PDT 24
Peak memory 160832 kb
Host smart-79f8fc89-53b3-4931-87da-3e1919d4d246
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3548451503 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.3548451503
Directory /workspace/38.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.1369093476
Short name T5
Test name
Test status
Simulation time 336747490000 ps
CPU time 700.41 seconds
Started Aug 13 04:45:12 PM PDT 24
Finished Aug 13 05:13:46 PM PDT 24
Peak memory 160780 kb
Host smart-2c71dfc7-9f63-4558-8884-4d1f3779aba0
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1369093476 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.1369093476
Directory /workspace/39.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.2112507921
Short name T28
Test name
Test status
Simulation time 336890690000 ps
CPU time 919.2 seconds
Started Aug 13 04:45:04 PM PDT 24
Finished Aug 13 05:22:57 PM PDT 24
Peak memory 160700 kb
Host smart-80a4754f-b25d-4e80-9e9a-6fb45f96bb89
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2112507921 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.2112507921
Directory /workspace/4.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.4257109604
Short name T149
Test name
Test status
Simulation time 337071070000 ps
CPU time 968.85 seconds
Started Aug 13 04:45:13 PM PDT 24
Finished Aug 13 05:25:31 PM PDT 24
Peak memory 160828 kb
Host smart-e707c87b-5aa6-4070-a3c4-f239a54bad69
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4257109604 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.4257109604
Directory /workspace/40.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.2685277609
Short name T119
Test name
Test status
Simulation time 336982570000 ps
CPU time 573.73 seconds
Started Aug 13 04:45:13 PM PDT 24
Finished Aug 13 05:09:30 PM PDT 24
Peak memory 160752 kb
Host smart-4f5868b2-e385-4cf7-93e3-ca4991238924
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2685277609 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.2685277609
Directory /workspace/41.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.2089189066
Short name T138
Test name
Test status
Simulation time 336598830000 ps
CPU time 745.3 seconds
Started Aug 13 04:45:13 PM PDT 24
Finished Aug 13 05:15:31 PM PDT 24
Peak memory 160752 kb
Host smart-20e4f85e-0481-476e-95aa-9e0d8c49f26b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2089189066 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.2089189066
Directory /workspace/42.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.483937178
Short name T25
Test name
Test status
Simulation time 336719770000 ps
CPU time 680.17 seconds
Started Aug 13 04:45:10 PM PDT 24
Finished Aug 13 05:13:17 PM PDT 24
Peak memory 160804 kb
Host smart-030268e6-a679-4b18-b4a5-3dd30a684b1e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=483937178 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.483937178
Directory /workspace/43.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.3846102985
Short name T112
Test name
Test status
Simulation time 336826310000 ps
CPU time 644.99 seconds
Started Aug 13 04:45:14 PM PDT 24
Finished Aug 13 05:11:58 PM PDT 24
Peak memory 160788 kb
Host smart-8efe5d59-04dd-4d8a-97ef-743e645b535d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3846102985 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.3846102985
Directory /workspace/44.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.2402560324
Short name T113
Test name
Test status
Simulation time 336392170000 ps
CPU time 820.86 seconds
Started Aug 13 04:45:11 PM PDT 24
Finished Aug 13 05:19:07 PM PDT 24
Peak memory 160736 kb
Host smart-c54e429d-51f4-4057-8645-2d12414c0bf2
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2402560324 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.2402560324
Directory /workspace/45.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.1458357137
Short name T127
Test name
Test status
Simulation time 336814770000 ps
CPU time 836.08 seconds
Started Aug 13 04:45:12 PM PDT 24
Finished Aug 13 05:19:26 PM PDT 24
Peak memory 160832 kb
Host smart-826e1b2a-ac56-4de4-a310-ffcd49a6bc19
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1458357137 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.1458357137
Directory /workspace/46.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.1015330271
Short name T139
Test name
Test status
Simulation time 336941330000 ps
CPU time 855.39 seconds
Started Aug 13 04:45:12 PM PDT 24
Finished Aug 13 05:19:46 PM PDT 24
Peak memory 160796 kb
Host smart-c1337a87-0970-483d-9f57-cdbcd73487cb
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1015330271 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.1015330271
Directory /workspace/47.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.3742282726
Short name T134
Test name
Test status
Simulation time 337145650000 ps
CPU time 766.73 seconds
Started Aug 13 04:45:14 PM PDT 24
Finished Aug 13 05:16:30 PM PDT 24
Peak memory 160828 kb
Host smart-0f435af7-a98a-4057-b709-fecec7f69208
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3742282726 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.3742282726
Directory /workspace/48.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.3049125447
Short name T115
Test name
Test status
Simulation time 337021770000 ps
CPU time 895.07 seconds
Started Aug 13 04:45:15 PM PDT 24
Finished Aug 13 05:21:55 PM PDT 24
Peak memory 160816 kb
Host smart-3fe9b6e6-69ac-4c9d-892c-50a769889109
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3049125447 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.3049125447
Directory /workspace/49.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.680305479
Short name T146
Test name
Test status
Simulation time 336746810000 ps
CPU time 736.99 seconds
Started Aug 13 04:45:02 PM PDT 24
Finished Aug 13 05:14:57 PM PDT 24
Peak memory 160804 kb
Host smart-7b336611-b94b-4a8f-9dde-427f7af796f7
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=680305479 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.680305479
Directory /workspace/5.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.1003491093
Short name T132
Test name
Test status
Simulation time 336751390000 ps
CPU time 756.75 seconds
Started Aug 13 04:45:02 PM PDT 24
Finished Aug 13 05:15:54 PM PDT 24
Peak memory 160724 kb
Host smart-f005b49c-dcb6-4000-a576-bd2cc82fd87c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1003491093 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.1003491093
Directory /workspace/6.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.1248245247
Short name T30
Test name
Test status
Simulation time 336338210000 ps
CPU time 836.37 seconds
Started Aug 13 04:45:01 PM PDT 24
Finished Aug 13 05:18:44 PM PDT 24
Peak memory 160680 kb
Host smart-d0bdc054-9708-4157-a09b-d0919fd39318
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1248245247 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.1248245247
Directory /workspace/7.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.3932363382
Short name T144
Test name
Test status
Simulation time 337047570000 ps
CPU time 762.43 seconds
Started Aug 13 04:45:03 PM PDT 24
Finished Aug 13 05:15:59 PM PDT 24
Peak memory 160724 kb
Host smart-a3c7f703-8149-447c-9ef1-f6fea22313e3
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3932363382 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.3932363382
Directory /workspace/8.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.3448347575
Short name T114
Test name
Test status
Simulation time 336714910000 ps
CPU time 625.89 seconds
Started Aug 13 04:45:02 PM PDT 24
Finished Aug 13 05:11:06 PM PDT 24
Peak memory 160724 kb
Host smart-33b11c0e-4c0b-4128-8973-9889dd8dbf04
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3448347575 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.3448347575
Directory /workspace/9.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.228783704
Short name T93
Test name
Test status
Simulation time 336335950000 ps
CPU time 766.17 seconds
Started Aug 13 04:44:51 PM PDT 24
Finished Aug 13 05:15:43 PM PDT 24
Peak memory 160676 kb
Host smart-f5eb3c8e-4900-47f5-8169-0dc072c8b206
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=228783704 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.228783704
Directory /workspace/0.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.3699040416
Short name T86
Test name
Test status
Simulation time 336712610000 ps
CPU time 723.75 seconds
Started Aug 13 04:44:55 PM PDT 24
Finished Aug 13 05:14:12 PM PDT 24
Peak memory 160732 kb
Host smart-f09be53b-c268-426d-ab43-ec5e1f45f426
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3699040416 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.3699040416
Directory /workspace/10.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.1923721959
Short name T82
Test name
Test status
Simulation time 336423110000 ps
CPU time 744.71 seconds
Started Aug 13 04:44:56 PM PDT 24
Finished Aug 13 05:15:37 PM PDT 24
Peak memory 160736 kb
Host smart-8e40c8fb-68aa-403d-aebb-4633eb1b9c32
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1923721959 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.1923721959
Directory /workspace/11.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.620862125
Short name T19
Test name
Test status
Simulation time 336887570000 ps
CPU time 1035.36 seconds
Started Aug 13 04:45:01 PM PDT 24
Finished Aug 13 05:28:51 PM PDT 24
Peak memory 160720 kb
Host smart-b9fe1df8-0d9a-41c4-903f-1e5e6d48b034
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=620862125 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.620862125
Directory /workspace/12.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.2118888373
Short name T90
Test name
Test status
Simulation time 337050110000 ps
CPU time 632.87 seconds
Started Aug 13 04:44:55 PM PDT 24
Finished Aug 13 05:11:11 PM PDT 24
Peak memory 160748 kb
Host smart-fe9e32db-f958-4935-8283-c1b4c2707d3f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2118888373 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.2118888373
Directory /workspace/13.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.241068658
Short name T22
Test name
Test status
Simulation time 336712750000 ps
CPU time 753.05 seconds
Started Aug 13 04:44:55 PM PDT 24
Finished Aug 13 05:15:29 PM PDT 24
Peak memory 160712 kb
Host smart-f9a15556-8007-4aad-83d9-4f3cbdc3b2e2
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=241068658 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.241068658
Directory /workspace/14.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.1265003751
Short name T14
Test name
Test status
Simulation time 336411350000 ps
CPU time 790.63 seconds
Started Aug 13 04:44:56 PM PDT 24
Finished Aug 13 05:17:11 PM PDT 24
Peak memory 160740 kb
Host smart-bef27d6d-6440-4dc9-a196-38bf3e959cb4
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1265003751 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.1265003751
Directory /workspace/15.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.1259716675
Short name T97
Test name
Test status
Simulation time 336858370000 ps
CPU time 714.77 seconds
Started Aug 13 04:44:54 PM PDT 24
Finished Aug 13 05:14:13 PM PDT 24
Peak memory 160716 kb
Host smart-98270c2c-de48-4e08-9255-2419f35699e4
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1259716675 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.1259716675
Directory /workspace/16.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.2129393693
Short name T96
Test name
Test status
Simulation time 336893150000 ps
CPU time 780.68 seconds
Started Aug 13 04:44:55 PM PDT 24
Finished Aug 13 05:16:38 PM PDT 24
Peak memory 160716 kb
Host smart-f6764048-271f-4386-ad66-66ba148eae07
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2129393693 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.2129393693
Directory /workspace/17.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.2956869306
Short name T17
Test name
Test status
Simulation time 336894110000 ps
CPU time 672.27 seconds
Started Aug 13 04:44:57 PM PDT 24
Finished Aug 13 05:12:19 PM PDT 24
Peak memory 160756 kb
Host smart-4d03429b-2e33-4034-9f48-e3f558a7136f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2956869306 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.2956869306
Directory /workspace/18.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.2928813786
Short name T101
Test name
Test status
Simulation time 337089530000 ps
CPU time 1031.23 seconds
Started Aug 13 04:45:01 PM PDT 24
Finished Aug 13 05:28:42 PM PDT 24
Peak memory 160748 kb
Host smart-2f9b0142-b3e4-4ed4-aba7-36306c5b343a
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2928813786 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.2928813786
Directory /workspace/19.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.2263926737
Short name T72
Test name
Test status
Simulation time 336962930000 ps
CPU time 761.36 seconds
Started Aug 13 04:44:49 PM PDT 24
Finished Aug 13 05:15:56 PM PDT 24
Peak memory 160676 kb
Host smart-38216e28-0f6a-4f42-b20a-323b025a6426
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2263926737 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.2263926737
Directory /workspace/2.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.395796594
Short name T109
Test name
Test status
Simulation time 336746790000 ps
CPU time 851.02 seconds
Started Aug 13 04:44:55 PM PDT 24
Finished Aug 13 05:19:40 PM PDT 24
Peak memory 160828 kb
Host smart-50f452e6-150b-4e5c-a021-bcd2a3494502
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=395796594 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.395796594
Directory /workspace/20.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.593901822
Short name T81
Test name
Test status
Simulation time 336598250000 ps
CPU time 766.33 seconds
Started Aug 13 04:44:55 PM PDT 24
Finished Aug 13 05:16:17 PM PDT 24
Peak memory 160792 kb
Host smart-5a729fa1-8dcc-46ef-a68d-4b4d65eac937
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=593901822 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.593901822
Directory /workspace/21.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.3496263352
Short name T80
Test name
Test status
Simulation time 336808170000 ps
CPU time 870.14 seconds
Started Aug 13 04:45:02 PM PDT 24
Finished Aug 13 05:20:42 PM PDT 24
Peak memory 160752 kb
Host smart-754defd3-7aec-4ae8-8054-9eb9763265eb
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3496263352 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.3496263352
Directory /workspace/22.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.3070997125
Short name T76
Test name
Test status
Simulation time 336623950000 ps
CPU time 868.76 seconds
Started Aug 13 04:45:01 PM PDT 24
Finished Aug 13 05:20:38 PM PDT 24
Peak memory 160752 kb
Host smart-ff1f83f0-8f39-48f1-9eee-47201b6f5e57
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3070997125 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.3070997125
Directory /workspace/23.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.1750758168
Short name T18
Test name
Test status
Simulation time 337021490000 ps
CPU time 865.87 seconds
Started Aug 13 04:44:56 PM PDT 24
Finished Aug 13 05:19:57 PM PDT 24
Peak memory 160800 kb
Host smart-1ec24622-1dc9-4b42-968d-ea2bd28c33cd
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1750758168 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.1750758168
Directory /workspace/24.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.1951510384
Short name T92
Test name
Test status
Simulation time 336728010000 ps
CPU time 859.61 seconds
Started Aug 13 04:45:01 PM PDT 24
Finished Aug 13 05:20:27 PM PDT 24
Peak memory 160752 kb
Host smart-9c546886-b097-4d34-abd6-4f0178045593
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1951510384 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.1951510384
Directory /workspace/25.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.1387119212
Short name T110
Test name
Test status
Simulation time 336465390000 ps
CPU time 744.47 seconds
Started Aug 13 04:44:58 PM PDT 24
Finished Aug 13 05:15:28 PM PDT 24
Peak memory 160760 kb
Host smart-3221fb66-24ad-4be4-a982-5db80bde9355
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1387119212 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.1387119212
Directory /workspace/26.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.3399493281
Short name T71
Test name
Test status
Simulation time 336899330000 ps
CPU time 806.55 seconds
Started Aug 13 04:44:55 PM PDT 24
Finished Aug 13 05:17:48 PM PDT 24
Peak memory 160740 kb
Host smart-3944903c-531b-4cf0-a96d-2df7cfbc1c9d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3399493281 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.3399493281
Directory /workspace/27.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.1006051577
Short name T102
Test name
Test status
Simulation time 336886610000 ps
CPU time 799.28 seconds
Started Aug 13 04:44:54 PM PDT 24
Finished Aug 13 05:17:34 PM PDT 24
Peak memory 160732 kb
Host smart-cd7bac44-50a2-4767-995a-25271d5e0e5f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1006051577 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.1006051577
Directory /workspace/28.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.39415913
Short name T88
Test name
Test status
Simulation time 337011790000 ps
CPU time 1047.48 seconds
Started Aug 13 04:45:01 PM PDT 24
Finished Aug 13 05:29:07 PM PDT 24
Peak memory 160728 kb
Host smart-4f29a702-6a6f-4c32-9cbf-613590bd9b96
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=39415913 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.39415913
Directory /workspace/29.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.396798734
Short name T104
Test name
Test status
Simulation time 337117250000 ps
CPU time 751.79 seconds
Started Aug 13 04:44:57 PM PDT 24
Finished Aug 13 05:15:34 PM PDT 24
Peak memory 160728 kb
Host smart-b7def3bd-fa2f-461e-8e62-9552b50b7ecc
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=396798734 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.396798734
Directory /workspace/3.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.2787184242
Short name T106
Test name
Test status
Simulation time 336629130000 ps
CPU time 801.4 seconds
Started Aug 13 04:44:58 PM PDT 24
Finished Aug 13 05:17:44 PM PDT 24
Peak memory 160756 kb
Host smart-a8ed1efa-54fc-487c-b382-d037ca526d9b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2787184242 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.2787184242
Directory /workspace/30.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.3844052980
Short name T73
Test name
Test status
Simulation time 336795070000 ps
CPU time 822.94 seconds
Started Aug 13 04:44:56 PM PDT 24
Finished Aug 13 05:19:09 PM PDT 24
Peak memory 160740 kb
Host smart-0b430cd5-7cc7-4e60-90ec-d90a53830613
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3844052980 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.3844052980
Directory /workspace/31.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.3163873421
Short name T79
Test name
Test status
Simulation time 336517990000 ps
CPU time 785.67 seconds
Started Aug 13 04:44:55 PM PDT 24
Finished Aug 13 05:17:04 PM PDT 24
Peak memory 160712 kb
Host smart-387c0674-7fdb-40ee-b0fc-7633f1f55774
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3163873421 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.3163873421
Directory /workspace/32.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.1365728254
Short name T77
Test name
Test status
Simulation time 336829110000 ps
CPU time 819.31 seconds
Started Aug 13 04:44:55 PM PDT 24
Finished Aug 13 05:18:58 PM PDT 24
Peak memory 160740 kb
Host smart-774cdc4b-1973-486f-93a9-bc1cb4633b61
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1365728254 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.1365728254
Directory /workspace/33.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.899485690
Short name T85
Test name
Test status
Simulation time 336771670000 ps
CPU time 739 seconds
Started Aug 13 04:44:55 PM PDT 24
Finished Aug 13 05:15:22 PM PDT 24
Peak memory 160736 kb
Host smart-c59324d1-4206-43ab-9527-3c22c60de99b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=899485690 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.899485690
Directory /workspace/34.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.3927667738
Short name T20
Test name
Test status
Simulation time 337126330000 ps
CPU time 785.01 seconds
Started Aug 13 04:44:58 PM PDT 24
Finished Aug 13 05:17:06 PM PDT 24
Peak memory 160748 kb
Host smart-997b7358-faf6-48d4-85a8-691b41c6da3e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3927667738 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.3927667738
Directory /workspace/35.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.2048063291
Short name T103
Test name
Test status
Simulation time 336362210000 ps
CPU time 741.53 seconds
Started Aug 13 04:44:54 PM PDT 24
Finished Aug 13 05:15:14 PM PDT 24
Peak memory 160756 kb
Host smart-69b40f2a-a468-4918-9e34-7ee3a067bdcc
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2048063291 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.2048063291
Directory /workspace/36.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.3075057676
Short name T98
Test name
Test status
Simulation time 336835110000 ps
CPU time 970.77 seconds
Started Aug 13 04:44:57 PM PDT 24
Finished Aug 13 05:25:19 PM PDT 24
Peak memory 160832 kb
Host smart-0d2f80ab-8c41-4772-919a-0c4e7354b7d1
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3075057676 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.3075057676
Directory /workspace/37.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.1135539726
Short name T15
Test name
Test status
Simulation time 336726110000 ps
CPU time 896.72 seconds
Started Aug 13 04:44:56 PM PDT 24
Finished Aug 13 05:21:40 PM PDT 24
Peak memory 160820 kb
Host smart-02d65f9b-bda3-4006-9cf2-39f216544b8c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1135539726 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.1135539726
Directory /workspace/38.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.3919531788
Short name T108
Test name
Test status
Simulation time 336385350000 ps
CPU time 571.7 seconds
Started Aug 13 04:44:56 PM PDT 24
Finished Aug 13 05:09:05 PM PDT 24
Peak memory 160748 kb
Host smart-5e69676b-d2a7-4ee5-8061-b6572d274898
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3919531788 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.3919531788
Directory /workspace/39.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.3909919177
Short name T107
Test name
Test status
Simulation time 336780270000 ps
CPU time 698.14 seconds
Started Aug 13 04:44:54 PM PDT 24
Finished Aug 13 05:13:34 PM PDT 24
Peak memory 160776 kb
Host smart-416b74bf-45df-4bec-80b0-f9e04a46cd20
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3909919177 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.3909919177
Directory /workspace/4.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.3693151209
Short name T89
Test name
Test status
Simulation time 336990670000 ps
CPU time 1039.69 seconds
Started Aug 13 04:45:01 PM PDT 24
Finished Aug 13 05:28:57 PM PDT 24
Peak memory 160716 kb
Host smart-a91af034-a87b-496e-9e3c-3dd7b069a73c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3693151209 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.3693151209
Directory /workspace/40.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.1447078387
Short name T84
Test name
Test status
Simulation time 336869710000 ps
CPU time 850.74 seconds
Started Aug 13 04:45:02 PM PDT 24
Finished Aug 13 05:19:59 PM PDT 24
Peak memory 160740 kb
Host smart-3e9d1bb6-bac5-4734-9dc6-e9725980f79c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1447078387 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.1447078387
Directory /workspace/41.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.2330504579
Short name T16
Test name
Test status
Simulation time 336481370000 ps
CPU time 779.02 seconds
Started Aug 13 04:44:56 PM PDT 24
Finished Aug 13 05:16:46 PM PDT 24
Peak memory 160748 kb
Host smart-36fad0ef-ec02-4421-9939-5ec545d6dcaf
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2330504579 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.2330504579
Directory /workspace/42.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.4098226095
Short name T99
Test name
Test status
Simulation time 336964630000 ps
CPU time 747.85 seconds
Started Aug 13 04:44:57 PM PDT 24
Finished Aug 13 05:15:11 PM PDT 24
Peak memory 160836 kb
Host smart-831f11c6-7a1b-419c-8c0a-3be07fd418aa
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4098226095 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.4098226095
Directory /workspace/43.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.899896194
Short name T95
Test name
Test status
Simulation time 336624410000 ps
CPU time 831.68 seconds
Started Aug 13 04:44:55 PM PDT 24
Finished Aug 13 05:18:38 PM PDT 24
Peak memory 160752 kb
Host smart-ad34194f-7567-4640-a181-f6102009157c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=899896194 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.899896194
Directory /workspace/44.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.520864864
Short name T75
Test name
Test status
Simulation time 336963890000 ps
CPU time 791.56 seconds
Started Aug 13 04:44:55 PM PDT 24
Finished Aug 13 05:17:22 PM PDT 24
Peak memory 160808 kb
Host smart-d751a66e-6a22-47f5-905f-c15a1aae1b56
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=520864864 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.520864864
Directory /workspace/45.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.2818222221
Short name T105
Test name
Test status
Simulation time 336908750000 ps
CPU time 694.68 seconds
Started Aug 13 04:44:55 PM PDT 24
Finished Aug 13 05:13:11 PM PDT 24
Peak memory 160748 kb
Host smart-8d2be217-d6ac-4baf-8475-0cd84525e65d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2818222221 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.2818222221
Directory /workspace/46.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.1296611911
Short name T100
Test name
Test status
Simulation time 336338910000 ps
CPU time 853.43 seconds
Started Aug 13 04:45:02 PM PDT 24
Finished Aug 13 05:20:01 PM PDT 24
Peak memory 160728 kb
Host smart-9ee5e3b0-5e9c-4387-936a-3123fa9a1ebd
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1296611911 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.1296611911
Directory /workspace/47.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.187810441
Short name T23
Test name
Test status
Simulation time 336677910000 ps
CPU time 820.09 seconds
Started Aug 13 04:45:01 PM PDT 24
Finished Aug 13 05:18:16 PM PDT 24
Peak memory 160752 kb
Host smart-2a57ec3c-a19c-48b9-86f1-5e44ff903bbc
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=187810441 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.187810441
Directory /workspace/48.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.2788838477
Short name T83
Test name
Test status
Simulation time 336696090000 ps
CPU time 749.9 seconds
Started Aug 13 04:45:01 PM PDT 24
Finished Aug 13 05:15:37 PM PDT 24
Peak memory 160756 kb
Host smart-b4db8f8b-ac57-4c0d-b48b-40bee1bf48bb
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2788838477 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.2788838477
Directory /workspace/49.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.877050460
Short name T78
Test name
Test status
Simulation time 336543750000 ps
CPU time 869.62 seconds
Started Aug 13 04:45:02 PM PDT 24
Finished Aug 13 05:20:42 PM PDT 24
Peak memory 160732 kb
Host smart-1c681a4c-a173-40fd-8730-fb7781333be8
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=877050460 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.877050460
Directory /workspace/5.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.35756443
Short name T74
Test name
Test status
Simulation time 336603870000 ps
CPU time 672.9 seconds
Started Aug 13 04:44:52 PM PDT 24
Finished Aug 13 05:12:33 PM PDT 24
Peak memory 160728 kb
Host smart-fb4c67a7-419f-45fe-aeef-6646b4b64992
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=35756443 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.35756443
Directory /workspace/6.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.3913893678
Short name T87
Test name
Test status
Simulation time 336596610000 ps
CPU time 873.29 seconds
Started Aug 13 04:44:55 PM PDT 24
Finished Aug 13 05:20:13 PM PDT 24
Peak memory 160716 kb
Host smart-1fd83f7c-d681-4fa2-b952-20422db83c19
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3913893678 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.3913893678
Directory /workspace/7.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.3174455624
Short name T94
Test name
Test status
Simulation time 336509750000 ps
CPU time 951.83 seconds
Started Aug 13 04:44:57 PM PDT 24
Finished Aug 13 05:24:34 PM PDT 24
Peak memory 160824 kb
Host smart-570390f0-67c8-41d6-aea5-2d829b028309
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3174455624 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.3174455624
Directory /workspace/8.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.3029380367
Short name T91
Test name
Test status
Simulation time 336620790000 ps
CPU time 1023.09 seconds
Started Aug 13 04:45:02 PM PDT 24
Finished Aug 13 05:28:16 PM PDT 24
Peak memory 160728 kb
Host smart-d660ccc0-6ed1-4576-975e-bbbf0d23b872
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3029380367 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.3029380367
Directory /workspace/9.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.3493573063
Short name T166
Test name
Test status
Simulation time 1487810000 ps
CPU time 4.9 seconds
Started Aug 13 04:45:25 PM PDT 24
Finished Aug 13 04:45:36 PM PDT 24
Peak memory 164848 kb
Host smart-5170ae5d-e370-468a-9d8d-97da9bd67aa2
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3493573063 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.3493573063
Directory /workspace/0.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.1821185469
Short name T172
Test name
Test status
Simulation time 1470950000 ps
CPU time 3.96 seconds
Started Aug 13 04:45:20 PM PDT 24
Finished Aug 13 04:45:28 PM PDT 24
Peak memory 164820 kb
Host smart-6dc44087-043a-4d09-a822-1ca2904b8dfe
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1821185469 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.1821185469
Directory /workspace/1.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.1244077070
Short name T155
Test name
Test status
Simulation time 1444510000 ps
CPU time 4.84 seconds
Started Aug 13 04:45:26 PM PDT 24
Finished Aug 13 04:45:37 PM PDT 24
Peak memory 164804 kb
Host smart-f21642ee-05cb-4993-a273-8678557f58a7
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1244077070 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.1244077070
Directory /workspace/10.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.769091277
Short name T162
Test name
Test status
Simulation time 1523390000 ps
CPU time 6.02 seconds
Started Aug 13 04:45:25 PM PDT 24
Finished Aug 13 04:45:39 PM PDT 24
Peak memory 164780 kb
Host smart-49213834-0e02-47eb-95ef-8f64763ecebb
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=769091277 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.769091277
Directory /workspace/11.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.3981355848
Short name T198
Test name
Test status
Simulation time 1425290000 ps
CPU time 5.64 seconds
Started Aug 13 04:45:25 PM PDT 24
Finished Aug 13 04:45:38 PM PDT 24
Peak memory 164788 kb
Host smart-6d6a7d0f-14db-48bd-ac8d-db4d61ff262f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3981355848 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.3981355848
Directory /workspace/12.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.1410109390
Short name T174
Test name
Test status
Simulation time 1540470000 ps
CPU time 6.01 seconds
Started Aug 13 04:45:25 PM PDT 24
Finished Aug 13 04:45:39 PM PDT 24
Peak memory 164788 kb
Host smart-02b3fbd2-6a85-44fb-b33d-9d52b12af97b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1410109390 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.1410109390
Directory /workspace/13.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.2397605953
Short name T159
Test name
Test status
Simulation time 1283450000 ps
CPU time 4.92 seconds
Started Aug 13 04:45:24 PM PDT 24
Finished Aug 13 04:45:36 PM PDT 24
Peak memory 164788 kb
Host smart-51235386-7919-4531-bd0d-3993fb56f0d8
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2397605953 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.2397605953
Directory /workspace/14.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.2454844036
Short name T185
Test name
Test status
Simulation time 1543970000 ps
CPU time 5.45 seconds
Started Aug 13 04:45:25 PM PDT 24
Finished Aug 13 04:45:37 PM PDT 24
Peak memory 164800 kb
Host smart-ab5e62a4-4f2f-4524-9cb6-db166211ea20
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2454844036 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.2454844036
Directory /workspace/15.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.2074715792
Short name T199
Test name
Test status
Simulation time 1329990000 ps
CPU time 3.78 seconds
Started Aug 13 04:45:24 PM PDT 24
Finished Aug 13 04:45:33 PM PDT 24
Peak memory 164864 kb
Host smart-808eedcd-2a9d-422f-a287-94215239edbd
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2074715792 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.2074715792
Directory /workspace/16.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.3438954772
Short name T152
Test name
Test status
Simulation time 1516810000 ps
CPU time 4.73 seconds
Started Aug 13 04:45:24 PM PDT 24
Finished Aug 13 04:45:36 PM PDT 24
Peak memory 164772 kb
Host smart-d00ea575-1a28-4e3b-9ca6-691bb6b593cd
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3438954772 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.3438954772
Directory /workspace/17.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.1743476378
Short name T194
Test name
Test status
Simulation time 1211230000 ps
CPU time 3.95 seconds
Started Aug 13 04:45:24 PM PDT 24
Finished Aug 13 04:45:34 PM PDT 24
Peak memory 164856 kb
Host smart-9ea1e05a-48b2-4666-b8fc-637fc4c850c6
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1743476378 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.1743476378
Directory /workspace/18.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.2695966074
Short name T179
Test name
Test status
Simulation time 1438650000 ps
CPU time 4.04 seconds
Started Aug 13 04:45:19 PM PDT 24
Finished Aug 13 04:45:28 PM PDT 24
Peak memory 164848 kb
Host smart-dd732ea2-8990-4059-a4bc-3a4360dabd3a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2695966074 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.2695966074
Directory /workspace/19.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.556346363
Short name T176
Test name
Test status
Simulation time 1454750000 ps
CPU time 5.61 seconds
Started Aug 13 04:45:21 PM PDT 24
Finished Aug 13 04:45:33 PM PDT 24
Peak memory 166424 kb
Host smart-3c7396a0-1a14-4bbd-a23f-5170cb832af0
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=556346363 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.556346363
Directory /workspace/2.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.1854648920
Short name T178
Test name
Test status
Simulation time 1186370000 ps
CPU time 3.3 seconds
Started Aug 13 04:45:29 PM PDT 24
Finished Aug 13 04:45:37 PM PDT 24
Peak memory 164780 kb
Host smart-1295c6f5-3a8f-4984-8eed-e523e66b44cb
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1854648920 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.1854648920
Directory /workspace/20.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3678182861
Short name T153
Test name
Test status
Simulation time 1221710000 ps
CPU time 4.5 seconds
Started Aug 13 04:45:25 PM PDT 24
Finished Aug 13 04:45:35 PM PDT 24
Peak memory 164800 kb
Host smart-2a4116c5-08e2-497b-bf3b-2df14e069847
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3678182861 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.3678182861
Directory /workspace/21.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.2850634114
Short name T163
Test name
Test status
Simulation time 1521150000 ps
CPU time 4.36 seconds
Started Aug 13 04:45:24 PM PDT 24
Finished Aug 13 04:45:33 PM PDT 24
Peak memory 164796 kb
Host smart-db8eaa61-742e-4443-abb9-785537f1bdfa
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2850634114 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.2850634114
Directory /workspace/22.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.3832148142
Short name T168
Test name
Test status
Simulation time 1483970000 ps
CPU time 4.56 seconds
Started Aug 13 04:45:24 PM PDT 24
Finished Aug 13 04:45:36 PM PDT 24
Peak memory 164772 kb
Host smart-de525af8-ce89-43ff-9d87-aacf4d2c8ca0
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3832148142 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.3832148142
Directory /workspace/23.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.3393769495
Short name T180
Test name
Test status
Simulation time 1410850000 ps
CPU time 4.56 seconds
Started Aug 13 04:45:21 PM PDT 24
Finished Aug 13 04:45:31 PM PDT 24
Peak memory 164868 kb
Host smart-1192fa0a-7f3f-4bd7-8da4-27d9b6bba03d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3393769495 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.3393769495
Directory /workspace/24.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.1822527376
Short name T167
Test name
Test status
Simulation time 1239170000 ps
CPU time 4.48 seconds
Started Aug 13 04:45:21 PM PDT 24
Finished Aug 13 04:45:32 PM PDT 24
Peak memory 164792 kb
Host smart-9c8a8198-1f4f-47fa-af4f-839a9de20d0f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1822527376 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.1822527376
Directory /workspace/25.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.1505449952
Short name T157
Test name
Test status
Simulation time 1331310000 ps
CPU time 4.88 seconds
Started Aug 13 04:45:24 PM PDT 24
Finished Aug 13 04:45:34 PM PDT 24
Peak memory 164864 kb
Host smart-686f4331-e60d-4e3e-8627-a8fc7f1275f3
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1505449952 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.1505449952
Directory /workspace/26.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.3768660895
Short name T187
Test name
Test status
Simulation time 1513910000 ps
CPU time 5.03 seconds
Started Aug 13 04:45:23 PM PDT 24
Finished Aug 13 04:45:34 PM PDT 24
Peak memory 164796 kb
Host smart-79f38b98-83df-4a06-a0ca-fa4146e1405d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3768660895 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.3768660895
Directory /workspace/27.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.1932542225
Short name T190
Test name
Test status
Simulation time 1115150000 ps
CPU time 3.48 seconds
Started Aug 13 04:45:29 PM PDT 24
Finished Aug 13 04:45:37 PM PDT 24
Peak memory 164780 kb
Host smart-60e864ed-f553-44a5-adf0-1698b2c61d5c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1932542225 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.1932542225
Directory /workspace/28.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.4159438788
Short name T196
Test name
Test status
Simulation time 1352770000 ps
CPU time 4.3 seconds
Started Aug 13 04:45:29 PM PDT 24
Finished Aug 13 04:45:39 PM PDT 24
Peak memory 164780 kb
Host smart-1de17f42-b245-458e-8ca5-e765df2e46c2
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4159438788 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.4159438788
Directory /workspace/29.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.3459163177
Short name T184
Test name
Test status
Simulation time 1369510000 ps
CPU time 5.14 seconds
Started Aug 13 04:45:22 PM PDT 24
Finished Aug 13 04:45:33 PM PDT 24
Peak memory 164808 kb
Host smart-92bf4ab5-cfb4-4877-94e0-59362a7ccc8a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3459163177 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.3459163177
Directory /workspace/3.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.1490643248
Short name T169
Test name
Test status
Simulation time 1479450000 ps
CPU time 3.52 seconds
Started Aug 13 04:45:27 PM PDT 24
Finished Aug 13 04:45:35 PM PDT 24
Peak memory 164824 kb
Host smart-9bc59b73-3ca3-4e76-a241-880590e068b0
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1490643248 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.1490643248
Directory /workspace/30.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.2036472198
Short name T189
Test name
Test status
Simulation time 1553150000 ps
CPU time 5.01 seconds
Started Aug 13 04:45:27 PM PDT 24
Finished Aug 13 04:45:39 PM PDT 24
Peak memory 164852 kb
Host smart-1ed12a86-9a2a-4b68-b383-827dac6c101e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2036472198 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.2036472198
Directory /workspace/31.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.2597011193
Short name T193
Test name
Test status
Simulation time 1527450000 ps
CPU time 3.75 seconds
Started Aug 13 04:45:25 PM PDT 24
Finished Aug 13 04:45:33 PM PDT 24
Peak memory 164872 kb
Host smart-5f5f9137-c4a8-4158-a4c4-6e610d3ce1ea
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2597011193 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.2597011193
Directory /workspace/32.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.2570886765
Short name T170
Test name
Test status
Simulation time 1169350000 ps
CPU time 3.86 seconds
Started Aug 13 04:45:28 PM PDT 24
Finished Aug 13 04:45:37 PM PDT 24
Peak memory 164824 kb
Host smart-c74192d7-53ca-4f40-80b3-805c0f652e66
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2570886765 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.2570886765
Directory /workspace/33.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.1132022160
Short name T191
Test name
Test status
Simulation time 1292090000 ps
CPU time 3.78 seconds
Started Aug 13 04:45:26 PM PDT 24
Finished Aug 13 04:45:34 PM PDT 24
Peak memory 164872 kb
Host smart-11791d64-bf6c-40f0-bf80-1d50ed45dfc5
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1132022160 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.1132022160
Directory /workspace/34.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.3399456351
Short name T171
Test name
Test status
Simulation time 1369490000 ps
CPU time 4.57 seconds
Started Aug 13 04:45:26 PM PDT 24
Finished Aug 13 04:45:37 PM PDT 24
Peak memory 164804 kb
Host smart-eefd8917-acaf-4824-9eb6-4855fde835c5
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3399456351 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.3399456351
Directory /workspace/35.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.1379231018
Short name T151
Test name
Test status
Simulation time 1553450000 ps
CPU time 5.61 seconds
Started Aug 13 04:45:26 PM PDT 24
Finished Aug 13 04:45:40 PM PDT 24
Peak memory 164820 kb
Host smart-1712ea9b-1beb-4b85-8e4a-7383c4e58ac7
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1379231018 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.1379231018
Directory /workspace/36.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.2009926600
Short name T197
Test name
Test status
Simulation time 1334810000 ps
CPU time 5.15 seconds
Started Aug 13 04:45:29 PM PDT 24
Finished Aug 13 04:45:40 PM PDT 24
Peak memory 164872 kb
Host smart-dce0d31b-9dc7-4468-8a77-e222e755f39c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2009926600 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.2009926600
Directory /workspace/37.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.3205809186
Short name T165
Test name
Test status
Simulation time 1456810000 ps
CPU time 4.69 seconds
Started Aug 13 04:45:31 PM PDT 24
Finished Aug 13 04:45:41 PM PDT 24
Peak memory 164812 kb
Host smart-f2f8ac84-c696-44ba-aa69-c01a9c2dc082
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3205809186 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.3205809186
Directory /workspace/38.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.3262941654
Short name T164
Test name
Test status
Simulation time 1429890000 ps
CPU time 4.73 seconds
Started Aug 13 04:45:30 PM PDT 24
Finished Aug 13 04:45:41 PM PDT 24
Peak memory 164832 kb
Host smart-b4e273c1-70b1-455b-89d0-9f00fb12802d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3262941654 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.3262941654
Directory /workspace/39.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.2047201413
Short name T183
Test name
Test status
Simulation time 1322290000 ps
CPU time 4.52 seconds
Started Aug 13 04:45:26 PM PDT 24
Finished Aug 13 04:45:35 PM PDT 24
Peak memory 164872 kb
Host smart-9ee60395-2109-4385-9943-74d27e1ace60
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2047201413 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.2047201413
Directory /workspace/4.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.1938901199
Short name T177
Test name
Test status
Simulation time 1388510000 ps
CPU time 5.59 seconds
Started Aug 13 04:45:32 PM PDT 24
Finished Aug 13 04:45:44 PM PDT 24
Peak memory 164872 kb
Host smart-76dd3d6b-09a9-49be-825b-ad58fb5d5ef3
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1938901199 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.1938901199
Directory /workspace/40.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.3623407061
Short name T186
Test name
Test status
Simulation time 1372410000 ps
CPU time 5.77 seconds
Started Aug 13 04:45:30 PM PDT 24
Finished Aug 13 04:45:42 PM PDT 24
Peak memory 164872 kb
Host smart-eb65ad92-89ac-4c7c-9a8d-699e7a98469c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3623407061 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.3623407061
Directory /workspace/41.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.2948782453
Short name T173
Test name
Test status
Simulation time 1466530000 ps
CPU time 4.25 seconds
Started Aug 13 04:45:31 PM PDT 24
Finished Aug 13 04:45:40 PM PDT 24
Peak memory 164872 kb
Host smart-386747dd-de3a-4afc-a5b7-7f6f99b8f1e5
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2948782453 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.2948782453
Directory /workspace/42.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.803343739
Short name T181
Test name
Test status
Simulation time 1531070000 ps
CPU time 4 seconds
Started Aug 13 04:45:32 PM PDT 24
Finished Aug 13 04:45:41 PM PDT 24
Peak memory 164868 kb
Host smart-b3fd1a1f-4df4-4451-a689-104d66287786
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=803343739 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.803343739
Directory /workspace/43.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.3227727430
Short name T160
Test name
Test status
Simulation time 1526230000 ps
CPU time 4.46 seconds
Started Aug 13 04:45:25 PM PDT 24
Finished Aug 13 04:45:35 PM PDT 24
Peak memory 164816 kb
Host smart-c4fd0604-9c04-4805-ac6b-2f318be231a1
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3227727430 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.3227727430
Directory /workspace/44.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.881639854
Short name T200
Test name
Test status
Simulation time 1605970000 ps
CPU time 5.02 seconds
Started Aug 13 04:45:29 PM PDT 24
Finished Aug 13 04:45:41 PM PDT 24
Peak memory 164844 kb
Host smart-052c976d-fe1f-42c1-b15f-81d997357abb
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=881639854 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.881639854
Directory /workspace/45.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.3078203106
Short name T188
Test name
Test status
Simulation time 1406790000 ps
CPU time 4.91 seconds
Started Aug 13 04:45:28 PM PDT 24
Finished Aug 13 04:45:39 PM PDT 24
Peak memory 164936 kb
Host smart-2209df9b-d044-4125-8497-62b98be86b61
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3078203106 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.3078203106
Directory /workspace/46.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.1512562728
Short name T154
Test name
Test status
Simulation time 1270750000 ps
CPU time 3.97 seconds
Started Aug 13 04:45:30 PM PDT 24
Finished Aug 13 04:45:38 PM PDT 24
Peak memory 164776 kb
Host smart-10bb0cf8-6d6d-43d1-b4a2-a60c357e084d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1512562728 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.1512562728
Directory /workspace/47.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.1124845042
Short name T156
Test name
Test status
Simulation time 1329910000 ps
CPU time 3.12 seconds
Started Aug 13 04:45:27 PM PDT 24
Finished Aug 13 04:45:34 PM PDT 24
Peak memory 164800 kb
Host smart-19b3761b-8548-424a-9c8b-1a1d0156498c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1124845042 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.1124845042
Directory /workspace/48.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.3617022319
Short name T182
Test name
Test status
Simulation time 1407050000 ps
CPU time 3.03 seconds
Started Aug 13 04:45:29 PM PDT 24
Finished Aug 13 04:45:36 PM PDT 24
Peak memory 164800 kb
Host smart-84c72340-371f-4c0a-b434-939a67dd02b6
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3617022319 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.3617022319
Directory /workspace/49.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.55598493
Short name T192
Test name
Test status
Simulation time 1562610000 ps
CPU time 4.45 seconds
Started Aug 13 04:45:21 PM PDT 24
Finished Aug 13 04:45:32 PM PDT 24
Peak memory 164788 kb
Host smart-36c136a4-5aed-46b9-8d49-6a51981aab64
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=55598493 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.55598493
Directory /workspace/5.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.415481527
Short name T195
Test name
Test status
Simulation time 1529750000 ps
CPU time 4.07 seconds
Started Aug 13 04:45:22 PM PDT 24
Finished Aug 13 04:45:32 PM PDT 24
Peak memory 164816 kb
Host smart-5b58fd7a-00a6-491f-91f9-4ddc175ce0f9
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=415481527 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.415481527
Directory /workspace/6.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.81430315
Short name T158
Test name
Test status
Simulation time 1510190000 ps
CPU time 5.01 seconds
Started Aug 13 04:45:25 PM PDT 24
Finished Aug 13 04:45:36 PM PDT 24
Peak memory 164848 kb
Host smart-18d60e26-2ae3-4c9a-9e98-c7af566782da
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=81430315 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.81430315
Directory /workspace/7.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1304746899
Short name T175
Test name
Test status
Simulation time 1393510000 ps
CPU time 5.45 seconds
Started Aug 13 04:45:20 PM PDT 24
Finished Aug 13 04:45:32 PM PDT 24
Peak memory 164864 kb
Host smart-21bc98c9-d723-4f2a-8249-2aafbc8eb0b5
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1304746899 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.1304746899
Directory /workspace/8.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2134304633
Short name T161
Test name
Test status
Simulation time 1443050000 ps
CPU time 4.72 seconds
Started Aug 13 04:45:25 PM PDT 24
Finished Aug 13 04:45:36 PM PDT 24
Peak memory 164848 kb
Host smart-386f3d38-0df5-43d7-97b7-132d63be825c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2134304633 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.2134304633
Directory /workspace/9.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.3006691096
Short name T45
Test name
Test status
Simulation time 1560210000 ps
CPU time 4.73 seconds
Started Aug 13 04:45:15 PM PDT 24
Finished Aug 13 04:45:25 PM PDT 24
Peak memory 164820 kb
Host smart-0c4e5638-09fe-4531-be4d-9ad512ef0107
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3006691096 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.3006691096
Directory /workspace/0.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.3661224040
Short name T32
Test name
Test status
Simulation time 1488730000 ps
CPU time 5.42 seconds
Started Aug 13 04:45:11 PM PDT 24
Finished Aug 13 04:45:23 PM PDT 24
Peak memory 164820 kb
Host smart-29967b9b-ea3f-4dd6-bdc1-7fd13332fa80
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3661224040 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.3661224040
Directory /workspace/1.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.2663094884
Short name T59
Test name
Test status
Simulation time 1573330000 ps
CPU time 5.92 seconds
Started Aug 13 04:45:12 PM PDT 24
Finished Aug 13 04:45:26 PM PDT 24
Peak memory 164800 kb
Host smart-e1f07b3f-85b2-48c6-b140-1d51af6d80ed
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2663094884 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.2663094884
Directory /workspace/11.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.4092639396
Short name T50
Test name
Test status
Simulation time 1491210000 ps
CPU time 4.73 seconds
Started Aug 13 04:45:17 PM PDT 24
Finished Aug 13 04:45:27 PM PDT 24
Peak memory 164816 kb
Host smart-da8b685c-23e0-4529-9f04-38592c8a3cc1
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4092639396 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.4092639396
Directory /workspace/12.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.4119820691
Short name T67
Test name
Test status
Simulation time 1512970000 ps
CPU time 5.61 seconds
Started Aug 13 04:45:16 PM PDT 24
Finished Aug 13 04:45:29 PM PDT 24
Peak memory 164824 kb
Host smart-d5059298-059d-4240-9892-6c5576e12b65
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4119820691 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.4119820691
Directory /workspace/13.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.3033520674
Short name T43
Test name
Test status
Simulation time 1468810000 ps
CPU time 4.65 seconds
Started Aug 13 04:45:16 PM PDT 24
Finished Aug 13 04:45:27 PM PDT 24
Peak memory 164816 kb
Host smart-cd989419-43cd-4324-827f-65947d543982
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3033520674 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.3033520674
Directory /workspace/14.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.3544763684
Short name T68
Test name
Test status
Simulation time 1550310000 ps
CPU time 5.91 seconds
Started Aug 13 04:45:12 PM PDT 24
Finished Aug 13 04:45:25 PM PDT 24
Peak memory 164804 kb
Host smart-de0427e4-1d9a-4da5-873c-d391d0a916b6
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3544763684 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.3544763684
Directory /workspace/15.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.3106803153
Short name T47
Test name
Test status
Simulation time 1183970000 ps
CPU time 4.22 seconds
Started Aug 13 04:45:14 PM PDT 24
Finished Aug 13 04:45:24 PM PDT 24
Peak memory 164796 kb
Host smart-a7cb618e-3141-455f-991f-50e9f611dc15
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3106803153 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.3106803153
Directory /workspace/16.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.3280489103
Short name T42
Test name
Test status
Simulation time 1545550000 ps
CPU time 5.05 seconds
Started Aug 13 04:45:12 PM PDT 24
Finished Aug 13 04:45:23 PM PDT 24
Peak memory 164872 kb
Host smart-da66d550-7d4a-433f-ba7c-ea913d57d1c9
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3280489103 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.3280489103
Directory /workspace/17.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.2972106768
Short name T37
Test name
Test status
Simulation time 1459430000 ps
CPU time 4.16 seconds
Started Aug 13 04:45:15 PM PDT 24
Finished Aug 13 04:45:25 PM PDT 24
Peak memory 164720 kb
Host smart-5afdeedd-319f-43ae-8653-16dfb6408938
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2972106768 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.2972106768
Directory /workspace/18.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.687835951
Short name T55
Test name
Test status
Simulation time 1601790000 ps
CPU time 5.74 seconds
Started Aug 13 04:45:12 PM PDT 24
Finished Aug 13 04:45:25 PM PDT 24
Peak memory 164812 kb
Host smart-2f979fec-4d50-452a-9c93-c1528199a6dd
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=687835951 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.687835951
Directory /workspace/19.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.688861644
Short name T8
Test name
Test status
Simulation time 1475530000 ps
CPU time 4.07 seconds
Started Aug 13 04:45:14 PM PDT 24
Finished Aug 13 04:45:24 PM PDT 24
Peak memory 164868 kb
Host smart-71eebd3b-7699-4402-a3ac-0553239d578f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=688861644 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.688861644
Directory /workspace/2.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.2355242832
Short name T40
Test name
Test status
Simulation time 1391950000 ps
CPU time 4.38 seconds
Started Aug 13 04:45:16 PM PDT 24
Finished Aug 13 04:45:26 PM PDT 24
Peak memory 164816 kb
Host smart-5c61588b-2021-401c-ab4d-96d49cce8884
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2355242832 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.2355242832
Directory /workspace/20.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.1324901274
Short name T3
Test name
Test status
Simulation time 1392430000 ps
CPU time 4.09 seconds
Started Aug 13 04:45:13 PM PDT 24
Finished Aug 13 04:45:23 PM PDT 24
Peak memory 164824 kb
Host smart-58a6c08b-26dd-4dc6-bddd-6d3be7f90f54
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1324901274 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.1324901274
Directory /workspace/21.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.3260173407
Short name T52
Test name
Test status
Simulation time 1402970000 ps
CPU time 3.56 seconds
Started Aug 13 04:45:15 PM PDT 24
Finished Aug 13 04:45:24 PM PDT 24
Peak memory 164688 kb
Host smart-571dda72-aeff-4a1f-aefd-84173e418c4b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3260173407 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.3260173407
Directory /workspace/22.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.558566921
Short name T38
Test name
Test status
Simulation time 1450590000 ps
CPU time 5.07 seconds
Started Aug 13 04:45:13 PM PDT 24
Finished Aug 13 04:45:25 PM PDT 24
Peak memory 164788 kb
Host smart-2070fea2-3974-4c89-98ad-ba1c85789b66
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=558566921 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.558566921
Directory /workspace/23.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.4192691388
Short name T51
Test name
Test status
Simulation time 1380490000 ps
CPU time 3.16 seconds
Started Aug 13 04:45:12 PM PDT 24
Finished Aug 13 04:45:19 PM PDT 24
Peak memory 164872 kb
Host smart-a2dff40f-0570-4176-9bbe-5c9dbcac26de
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4192691388 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.4192691388
Directory /workspace/24.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.2033856381
Short name T69
Test name
Test status
Simulation time 1367110000 ps
CPU time 5.16 seconds
Started Aug 13 04:45:12 PM PDT 24
Finished Aug 13 04:45:24 PM PDT 24
Peak memory 164804 kb
Host smart-5498ae97-c4f5-45ab-9371-babcdeb0e09c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2033856381 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.2033856381
Directory /workspace/25.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.2242362086
Short name T48
Test name
Test status
Simulation time 1500230000 ps
CPU time 5.33 seconds
Started Aug 13 04:45:21 PM PDT 24
Finished Aug 13 04:45:33 PM PDT 24
Peak memory 164884 kb
Host smart-d6db5a07-4791-437e-8a67-6d9eae54bef9
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2242362086 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.2242362086
Directory /workspace/26.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.2267677408
Short name T7
Test name
Test status
Simulation time 1321670000 ps
CPU time 4.67 seconds
Started Aug 13 04:45:24 PM PDT 24
Finished Aug 13 04:45:35 PM PDT 24
Peak memory 164856 kb
Host smart-0a37b006-7db4-4814-a5d2-ac913dee75e3
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2267677408 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.2267677408
Directory /workspace/27.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.112755352
Short name T10
Test name
Test status
Simulation time 1124330000 ps
CPU time 3.87 seconds
Started Aug 13 04:45:24 PM PDT 24
Finished Aug 13 04:45:32 PM PDT 24
Peak memory 164800 kb
Host smart-1a02e712-0264-4151-8150-fdda72f97498
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=112755352 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.112755352
Directory /workspace/28.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.2264271151
Short name T33
Test name
Test status
Simulation time 1390790000 ps
CPU time 4.03 seconds
Started Aug 13 04:45:19 PM PDT 24
Finished Aug 13 04:45:28 PM PDT 24
Peak memory 164824 kb
Host smart-bcbb4698-a7be-45b3-846e-8ad8baa90a10
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2264271151 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.2264271151
Directory /workspace/29.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.1602635935
Short name T49
Test name
Test status
Simulation time 1451850000 ps
CPU time 5.39 seconds
Started Aug 13 04:45:11 PM PDT 24
Finished Aug 13 04:45:23 PM PDT 24
Peak memory 164808 kb
Host smart-bd608e8d-2cac-4e6e-a92f-f8f867ce9aa8
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1602635935 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.1602635935
Directory /workspace/3.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.1402132912
Short name T9
Test name
Test status
Simulation time 1347070000 ps
CPU time 5.08 seconds
Started Aug 13 04:45:25 PM PDT 24
Finished Aug 13 04:45:36 PM PDT 24
Peak memory 164804 kb
Host smart-596f4e74-322d-498b-9c70-fa290ac1d01a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1402132912 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.1402132912
Directory /workspace/30.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.715253948
Short name T41
Test name
Test status
Simulation time 1521870000 ps
CPU time 5.89 seconds
Started Aug 13 04:45:23 PM PDT 24
Finished Aug 13 04:45:36 PM PDT 24
Peak memory 164852 kb
Host smart-5682cb30-0861-4bfd-98b7-48ec2e21dc20
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=715253948 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.715253948
Directory /workspace/31.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.1453251454
Short name T58
Test name
Test status
Simulation time 1452290000 ps
CPU time 4.72 seconds
Started Aug 13 04:45:21 PM PDT 24
Finished Aug 13 04:45:32 PM PDT 24
Peak memory 164784 kb
Host smart-18144f91-e968-40dc-8e02-b9a20a4b9f0c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1453251454 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.1453251454
Directory /workspace/32.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.1276653021
Short name T53
Test name
Test status
Simulation time 1200090000 ps
CPU time 4.44 seconds
Started Aug 13 04:45:21 PM PDT 24
Finished Aug 13 04:45:31 PM PDT 24
Peak memory 164852 kb
Host smart-fc5e104b-841e-4f92-bf96-4b203e17e235
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1276653021 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.1276653021
Directory /workspace/33.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.3668791047
Short name T56
Test name
Test status
Simulation time 1287050000 ps
CPU time 4.35 seconds
Started Aug 13 04:45:19 PM PDT 24
Finished Aug 13 04:45:28 PM PDT 24
Peak memory 164828 kb
Host smart-315210a4-8593-4c97-91c8-e3175627db32
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3668791047 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.3668791047
Directory /workspace/34.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.275305962
Short name T12
Test name
Test status
Simulation time 1563050000 ps
CPU time 5.18 seconds
Started Aug 13 04:45:27 PM PDT 24
Finished Aug 13 04:45:38 PM PDT 24
Peak memory 164800 kb
Host smart-9bd430b9-3de7-485b-aca3-228c7c4f85a8
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=275305962 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.275305962
Directory /workspace/35.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.528561214
Short name T31
Test name
Test status
Simulation time 1445070000 ps
CPU time 5.71 seconds
Started Aug 13 04:45:24 PM PDT 24
Finished Aug 13 04:45:37 PM PDT 24
Peak memory 164792 kb
Host smart-2993f8a5-6dc9-4c8e-8a5e-925d3f83ec62
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=528561214 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.528561214
Directory /workspace/36.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.3638583954
Short name T65
Test name
Test status
Simulation time 1336310000 ps
CPU time 3.51 seconds
Started Aug 13 04:45:19 PM PDT 24
Finished Aug 13 04:45:27 PM PDT 24
Peak memory 164848 kb
Host smart-0cb87dad-9649-4605-b5df-cb928bc9ad03
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3638583954 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.3638583954
Directory /workspace/37.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.3984549333
Short name T34
Test name
Test status
Simulation time 1379750000 ps
CPU time 3.22 seconds
Started Aug 13 04:45:19 PM PDT 24
Finished Aug 13 04:45:26 PM PDT 24
Peak memory 164824 kb
Host smart-ec7349b8-475b-4e2a-9f28-303201d62938
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3984549333 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.3984549333
Directory /workspace/38.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.1523043257
Short name T36
Test name
Test status
Simulation time 1497030000 ps
CPU time 4.95 seconds
Started Aug 13 04:45:23 PM PDT 24
Finished Aug 13 04:45:35 PM PDT 24
Peak memory 164776 kb
Host smart-a91f2fee-49f7-429e-b396-60a1afe4eb3a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1523043257 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.1523043257
Directory /workspace/39.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.2270958112
Short name T44
Test name
Test status
Simulation time 1417270000 ps
CPU time 3.7 seconds
Started Aug 13 04:45:11 PM PDT 24
Finished Aug 13 04:45:19 PM PDT 24
Peak memory 164844 kb
Host smart-939d7132-77a8-4b03-8550-83990ab3ec87
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2270958112 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.2270958112
Directory /workspace/4.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.3988786922
Short name T13
Test name
Test status
Simulation time 1574630000 ps
CPU time 4.77 seconds
Started Aug 13 04:45:24 PM PDT 24
Finished Aug 13 04:45:35 PM PDT 24
Peak memory 164808 kb
Host smart-63daa391-7c21-421a-bd01-7dfee45d0a94
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3988786922 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.3988786922
Directory /workspace/40.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.3486201158
Short name T60
Test name
Test status
Simulation time 1498430000 ps
CPU time 5.12 seconds
Started Aug 13 04:45:25 PM PDT 24
Finished Aug 13 04:45:36 PM PDT 24
Peak memory 164872 kb
Host smart-a84fa1c1-0a4c-40a7-b3ee-3f7a5e69419c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3486201158 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.3486201158
Directory /workspace/41.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.3985539037
Short name T64
Test name
Test status
Simulation time 1368250000 ps
CPU time 3.32 seconds
Started Aug 13 04:45:21 PM PDT 24
Finished Aug 13 04:45:28 PM PDT 24
Peak memory 164800 kb
Host smart-10379049-2dfb-4ef9-a43a-f7d5729df273
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3985539037 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.3985539037
Directory /workspace/42.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.2341262668
Short name T62
Test name
Test status
Simulation time 1468110000 ps
CPU time 4.28 seconds
Started Aug 13 04:45:24 PM PDT 24
Finished Aug 13 04:45:34 PM PDT 24
Peak memory 164808 kb
Host smart-b677d7f4-217d-46eb-921b-9524e3845918
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2341262668 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.2341262668
Directory /workspace/43.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.3156842281
Short name T57
Test name
Test status
Simulation time 1443510000 ps
CPU time 5.63 seconds
Started Aug 13 04:45:24 PM PDT 24
Finished Aug 13 04:45:37 PM PDT 24
Peak memory 164864 kb
Host smart-e9494c8f-b363-42b8-8f1e-56c1e818a07c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3156842281 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.3156842281
Directory /workspace/44.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.2335586804
Short name T70
Test name
Test status
Simulation time 1483430000 ps
CPU time 6.09 seconds
Started Aug 13 04:45:22 PM PDT 24
Finished Aug 13 04:45:34 PM PDT 24
Peak memory 164812 kb
Host smart-cc7781d5-b861-4507-9f2b-09e38fb9dcba
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2335586804 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.2335586804
Directory /workspace/45.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.731102073
Short name T66
Test name
Test status
Simulation time 1247870000 ps
CPU time 4.04 seconds
Started Aug 13 04:45:20 PM PDT 24
Finished Aug 13 04:45:29 PM PDT 24
Peak memory 164792 kb
Host smart-7ae0c5bc-658e-4ff3-89dc-19597dad6ce1
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=731102073 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.731102073
Directory /workspace/46.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.943106288
Short name T11
Test name
Test status
Simulation time 1605830000 ps
CPU time 5.13 seconds
Started Aug 13 04:45:21 PM PDT 24
Finished Aug 13 04:45:33 PM PDT 24
Peak memory 164792 kb
Host smart-af3f0922-ccc6-4beb-b378-11bc83bca4d2
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=943106288 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.943106288
Directory /workspace/47.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.3896752222
Short name T54
Test name
Test status
Simulation time 1416970000 ps
CPU time 4.37 seconds
Started Aug 13 04:45:19 PM PDT 24
Finished Aug 13 04:45:29 PM PDT 24
Peak memory 164884 kb
Host smart-c8511d13-18d3-419c-a8ca-f04e5b006b4b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3896752222 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.3896752222
Directory /workspace/48.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.2570475213
Short name T35
Test name
Test status
Simulation time 1420590000 ps
CPU time 4.51 seconds
Started Aug 13 04:45:20 PM PDT 24
Finished Aug 13 04:45:30 PM PDT 24
Peak memory 164928 kb
Host smart-f9201d8c-3ff0-411c-8721-98475e458816
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2570475213 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.2570475213
Directory /workspace/49.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.4176607328
Short name T1
Test name
Test status
Simulation time 1439370000 ps
CPU time 4.73 seconds
Started Aug 13 04:45:14 PM PDT 24
Finished Aug 13 04:45:24 PM PDT 24
Peak memory 164832 kb
Host smart-6dbcd679-1bd2-4aba-adf4-a416e3871e36
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4176607328 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.4176607328
Directory /workspace/5.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.3411707274
Short name T39
Test name
Test status
Simulation time 952510000 ps
CPU time 3.67 seconds
Started Aug 13 04:45:12 PM PDT 24
Finished Aug 13 04:45:20 PM PDT 24
Peak memory 164796 kb
Host smart-ad16867b-0f25-4466-bbf4-2b2e6e5e17d8
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3411707274 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.3411707274
Directory /workspace/6.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.3050939052
Short name T63
Test name
Test status
Simulation time 1344710000 ps
CPU time 4.13 seconds
Started Aug 13 04:45:15 PM PDT 24
Finished Aug 13 04:45:24 PM PDT 24
Peak memory 164872 kb
Host smart-a36a3455-4982-4bef-aebd-19ce32feb32e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3050939052 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.3050939052
Directory /workspace/7.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.2309038009
Short name T61
Test name
Test status
Simulation time 1537810000 ps
CPU time 4.74 seconds
Started Aug 13 04:45:13 PM PDT 24
Finished Aug 13 04:45:24 PM PDT 24
Peak memory 164780 kb
Host smart-3b72de17-5c96-4a9a-a9e9-894f12ac6957
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2309038009 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.2309038009
Directory /workspace/8.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.1896815826
Short name T46
Test name
Test status
Simulation time 1557270000 ps
CPU time 5.45 seconds
Started Aug 13 04:45:16 PM PDT 24
Finished Aug 13 04:45:29 PM PDT 24
Peak memory 164888 kb
Host smart-6556f612-e584-4783-a86f-0efc3ef2f66c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1896815826 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.1896815826
Directory /workspace/9.prim_lfsr_gal_smoke/latest
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