Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.31 100.00 96.55 100.00 100.00 95.00


Total tests in report: 200
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
87.31 87.31 100.00 100.00 96.55 96.55 100.00 100.00 100.00 100.00 40.00 40.00 /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.3967054776
95.31 8.00 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 80.00 40.00 /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.3440937805
98.31 3.00 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 95.00 15.00 /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.4121632180

Tests that do not contribute to grading

Name
/workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.827104450
/workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.4289415942
/workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.2108244462
/workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.140685008
/workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.1372354576
/workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.1123995365
/workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.3421651259
/workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.2532412557
/workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.2186755492
/workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.98302652
/workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2432249920
/workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.727902582
/workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.57031766
/workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.2899669957
/workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.4042972688
/workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.3752174924
/workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.265166019
/workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.908695004
/workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1316442904
/workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.1875680431
/workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.2143810585
/workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.2969764571
/workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.1435342449
/workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.44326971
/workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.3422656134
/workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.3395677952
/workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.1481590566
/workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.203985708
/workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.1849698142
/workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.635229666
/workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.1394729950
/workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.2205231809
/workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.3004114399
/workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.2025825959
/workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.1421480970
/workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.4068528849
/workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.3181461596
/workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.597428184
/workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.2584702904
/workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.3338095984
/workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.317402133
/workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.712380021
/workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.3342436393
/workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.2269982414
/workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.431945585
/workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.3704961447
/workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.729709255
/workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.3030021326
/workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.784461438
/workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.2729423946
/workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.612243106
/workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.3011111436
/workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.429129111
/workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.2629709250
/workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.2454237065
/workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.4169122223
/workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.3637110824
/workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.775217584
/workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.2969254162
/workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.3621728496
/workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.2332004184
/workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.787319945
/workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3307522691
/workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.3080425081
/workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.3992956102
/workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.135791304
/workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.1900734936
/workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.7824044
/workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.2492317337
/workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.2325100448
/workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.2320835944
/workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.3097096389
/workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.1680594630
/workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.1248346287
/workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.3573324402
/workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.1080975755
/workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.3513106566
/workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.2722904997
/workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.2755257061
/workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.402152422
/workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.2419201964
/workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.335176055
/workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.421428555
/workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.4143410028
/workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.315258242
/workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.3454658445
/workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.3858008203
/workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.1670389363
/workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.1392618927
/workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.1071946995
/workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.1479769577
/workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.513886380
/workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.3756260963
/workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.1833652196
/workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.2412860465
/workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.4129336280
/workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.550129256
/workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.2931736740
/workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.2849883698
/workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.3255652904
/workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.2571753095
/workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.1132003172
/workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.18509496
/workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.3813285048
/workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.3946013281
/workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.9619027
/workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.1827300762
/workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.2711111709
/workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.424033510
/workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.2165963270
/workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.3553334144
/workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.4093946150
/workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.42890691
/workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.4253253409
/workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.3283042708
/workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.1391426563
/workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.961352137
/workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.1364844113
/workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.3486606498
/workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.2639058633
/workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.1891343274
/workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.4104299063
/workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.2468769367
/workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.844542522
/workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.1368193872
/workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.2511065808
/workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.1089577087
/workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.1195187848
/workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.427789501
/workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1345078062
/workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.871757953
/workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.133699886
/workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.4051469219
/workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.1973791396
/workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.1401165188
/workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.1739185884
/workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.3249324993
/workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.3880367079
/workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.1650400193
/workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.2382747223
/workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.815137968
/workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.294888487
/workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.1116058342
/workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.2600944252
/workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.143023124
/workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.3292232454
/workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1423523050
/workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2161084517
/workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.3292860650
/workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.1181566024
/workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.1440377398
/workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.516764834
/workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.931671083
/workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.2401647951
/workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.1871451004
/workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.1546041198
/workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.1442156000
/workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.427043601
/workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.323946311
/workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.2963084747
/workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.1438821397
/workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.2422984800
/workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.4108771780
/workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.1667525335
/workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.1207035912
/workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.3996422835
/workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.1961653517
/workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.3976583303
/workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.570053978
/workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.3500001852
/workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.1682904653
/workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.652635160
/workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.4248121845
/workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.1761797446
/workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.3618083740
/workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.2159589528
/workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.1301294257
/workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.1470850560
/workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.3144785028
/workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.1305810400
/workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.4025155136
/workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.1215970698
/workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.702034292
/workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.1962506519
/workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.4032468580
/workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.639020570
/workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.555433506
/workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.296504853
/workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.820234611
/workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.3288432503
/workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.4095081328
/workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.2358282883
/workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.1527644901
/workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.1478939646
/workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.3376289840
/workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.3946351967
/workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.2507058034



Total test records in report: 200
tests.html | tests1.html | tests2.html | tests3.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.1961653517 Aug 15 04:24:01 PM PDT 24 Aug 15 04:24:09 PM PDT 24 1605910000 ps
T2 /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.1440377398 Aug 15 04:20:17 PM PDT 24 Aug 15 04:20:28 PM PDT 24 1510970000 ps
T3 /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.1761797446 Aug 15 04:23:09 PM PDT 24 Aug 15 04:23:21 PM PDT 24 1561810000 ps
T7 /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.1301294257 Aug 15 04:23:16 PM PDT 24 Aug 15 04:23:26 PM PDT 24 1444690000 ps
T8 /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.4108771780 Aug 15 04:23:20 PM PDT 24 Aug 15 04:23:30 PM PDT 24 1519870000 ps
T9 /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.3967054776 Aug 15 04:23:32 PM PDT 24 Aug 15 04:23:42 PM PDT 24 1499490000 ps
T10 /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.652635160 Aug 15 04:23:28 PM PDT 24 Aug 15 04:23:38 PM PDT 24 1411690000 ps
T11 /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.4032468580 Aug 15 04:21:09 PM PDT 24 Aug 15 04:21:17 PM PDT 24 1383470000 ps
T12 /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.3144785028 Aug 15 04:23:16 PM PDT 24 Aug 15 04:23:26 PM PDT 24 1515850000 ps
T13 /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.1442156000 Aug 15 04:20:20 PM PDT 24 Aug 15 04:20:30 PM PDT 24 1493170000 ps
T31 /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.820234611 Aug 15 04:23:22 PM PDT 24 Aug 15 04:23:27 PM PDT 24 1202830000 ps
T32 /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.3996422835 Aug 15 04:23:59 PM PDT 24 Aug 15 04:24:07 PM PDT 24 1388930000 ps
T33 /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.931671083 Aug 15 04:19:58 PM PDT 24 Aug 15 04:20:09 PM PDT 24 1360010000 ps
T34 /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.1207035912 Aug 15 04:23:04 PM PDT 24 Aug 15 04:23:11 PM PDT 24 1503950000 ps
T35 /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.2401647951 Aug 15 04:23:23 PM PDT 24 Aug 15 04:23:34 PM PDT 24 1559310000 ps
T36 /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.639020570 Aug 15 04:23:38 PM PDT 24 Aug 15 04:23:46 PM PDT 24 1392930000 ps
T37 /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.1470850560 Aug 15 04:23:30 PM PDT 24 Aug 15 04:23:40 PM PDT 24 1432290000 ps
T38 /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.2358282883 Aug 15 04:18:36 PM PDT 24 Aug 15 04:18:51 PM PDT 24 1527490000 ps
T39 /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.4248121845 Aug 15 04:23:28 PM PDT 24 Aug 15 04:23:39 PM PDT 24 1507510000 ps
T40 /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.427043601 Aug 15 04:23:24 PM PDT 24 Aug 15 04:23:34 PM PDT 24 1558330000 ps
T41 /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.555433506 Aug 15 04:23:37 PM PDT 24 Aug 15 04:23:45 PM PDT 24 1195550000 ps
T42 /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.2159589528 Aug 15 04:23:09 PM PDT 24 Aug 15 04:23:20 PM PDT 24 1478210000 ps
T43 /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.2963084747 Aug 15 04:18:30 PM PDT 24 Aug 15 04:18:41 PM PDT 24 1596010000 ps
T44 /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.4095081328 Aug 15 04:19:46 PM PDT 24 Aug 15 04:19:56 PM PDT 24 1319730000 ps
T45 /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.1667525335 Aug 15 04:20:11 PM PDT 24 Aug 15 04:20:19 PM PDT 24 1445270000 ps
T46 /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.1962506519 Aug 15 04:18:41 PM PDT 24 Aug 15 04:18:52 PM PDT 24 1513510000 ps
T47 /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.702034292 Aug 15 04:23:09 PM PDT 24 Aug 15 04:23:19 PM PDT 24 1563670000 ps
T48 /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.296504853 Aug 15 04:19:02 PM PDT 24 Aug 15 04:19:12 PM PDT 24 1573890000 ps
T49 /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.2507058034 Aug 15 04:23:22 PM PDT 24 Aug 15 04:23:31 PM PDT 24 1523150000 ps
T50 /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.3376289840 Aug 15 04:23:29 PM PDT 24 Aug 15 04:23:38 PM PDT 24 1335270000 ps
T51 /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.1478939646 Aug 15 04:23:14 PM PDT 24 Aug 15 04:23:23 PM PDT 24 1549210000 ps
T52 /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.516764834 Aug 15 04:19:58 PM PDT 24 Aug 15 04:20:11 PM PDT 24 1589810000 ps
T53 /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.2422984800 Aug 15 04:23:20 PM PDT 24 Aug 15 04:23:29 PM PDT 24 1372730000 ps
T54 /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.3288432503 Aug 15 04:21:09 PM PDT 24 Aug 15 04:21:17 PM PDT 24 1406090000 ps
T55 /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.3292860650 Aug 15 04:18:41 PM PDT 24 Aug 15 04:18:49 PM PDT 24 1422810000 ps
T56 /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.3500001852 Aug 15 04:23:28 PM PDT 24 Aug 15 04:23:38 PM PDT 24 1492110000 ps
T57 /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.1546041198 Aug 15 04:24:23 PM PDT 24 Aug 15 04:24:32 PM PDT 24 1527190000 ps
T58 /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.1527644901 Aug 15 04:23:32 PM PDT 24 Aug 15 04:23:41 PM PDT 24 1225470000 ps
T59 /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.1181566024 Aug 15 04:19:05 PM PDT 24 Aug 15 04:19:13 PM PDT 24 1321150000 ps
T60 /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.4025155136 Aug 15 04:24:21 PM PDT 24 Aug 15 04:24:33 PM PDT 24 1595390000 ps
T61 /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.1215970698 Aug 15 04:23:29 PM PDT 24 Aug 15 04:23:38 PM PDT 24 1318490000 ps
T62 /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.1682904653 Aug 15 04:23:28 PM PDT 24 Aug 15 04:23:35 PM PDT 24 1540550000 ps
T63 /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.3618083740 Aug 15 04:23:12 PM PDT 24 Aug 15 04:23:22 PM PDT 24 1537590000 ps
T64 /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.570053978 Aug 15 04:23:22 PM PDT 24 Aug 15 04:23:30 PM PDT 24 1435210000 ps
T65 /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.3946351967 Aug 15 04:23:00 PM PDT 24 Aug 15 04:23:09 PM PDT 24 1341970000 ps
T66 /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.323946311 Aug 15 04:19:28 PM PDT 24 Aug 15 04:19:37 PM PDT 24 1540670000 ps
T67 /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.3976583303 Aug 15 04:23:22 PM PDT 24 Aug 15 04:23:30 PM PDT 24 1551270000 ps
T68 /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.1871451004 Aug 15 04:21:54 PM PDT 24 Aug 15 04:22:01 PM PDT 24 1397950000 ps
T69 /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.1305810400 Aug 15 04:23:16 PM PDT 24 Aug 15 04:23:24 PM PDT 24 1092030000 ps
T70 /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.1438821397 Aug 15 04:23:21 PM PDT 24 Aug 15 04:23:31 PM PDT 24 1325970000 ps
T14 /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.1071946995 Aug 15 04:23:09 PM PDT 24 Aug 15 05:00:46 PM PDT 24 336672990000 ps
T15 /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.2332004184 Aug 15 04:18:24 PM PDT 24 Aug 15 04:50:27 PM PDT 24 336761450000 ps
T16 /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.2412860465 Aug 15 04:23:28 PM PDT 24 Aug 15 04:56:43 PM PDT 24 336317270000 ps
T17 /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.3080425081 Aug 15 04:23:10 PM PDT 24 Aug 15 05:00:38 PM PDT 24 336391230000 ps
T18 /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.2722904997 Aug 15 04:24:21 PM PDT 24 Aug 15 05:10:04 PM PDT 24 336926210000 ps
T19 /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.3513106566 Aug 15 04:24:22 PM PDT 24 Aug 15 05:09:57 PM PDT 24 336813910000 ps
T20 /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.1392618927 Aug 15 04:23:09 PM PDT 24 Aug 15 04:58:11 PM PDT 24 336491930000 ps
T21 /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.3440937805 Aug 15 04:24:01 PM PDT 24 Aug 15 04:50:04 PM PDT 24 337085890000 ps
T22 /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.1080975755 Aug 15 04:24:21 PM PDT 24 Aug 15 05:10:08 PM PDT 24 336428230000 ps
T23 /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3307522691 Aug 15 04:23:28 PM PDT 24 Aug 15 04:53:00 PM PDT 24 336882530000 ps
T71 /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.2320835944 Aug 15 04:21:14 PM PDT 24 Aug 15 05:00:23 PM PDT 24 337015550000 ps
T72 /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.2419201964 Aug 15 04:19:08 PM PDT 24 Aug 15 04:47:07 PM PDT 24 336427610000 ps
T73 /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.1680594630 Aug 15 04:24:24 PM PDT 24 Aug 15 04:57:40 PM PDT 24 336613050000 ps
T74 /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.402152422 Aug 15 04:24:00 PM PDT 24 Aug 15 04:53:16 PM PDT 24 336615510000 ps
T75 /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.2454237065 Aug 15 04:23:21 PM PDT 24 Aug 15 04:54:12 PM PDT 24 336823430000 ps
T76 /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.7824044 Aug 15 04:19:21 PM PDT 24 Aug 15 04:55:52 PM PDT 24 336310670000 ps
T77 /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.3573324402 Aug 15 04:24:24 PM PDT 24 Aug 15 04:57:35 PM PDT 24 336395030000 ps
T78 /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.2931736740 Aug 15 04:23:22 PM PDT 24 Aug 15 04:54:59 PM PDT 24 336603850000 ps
T79 /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.1479769577 Aug 15 04:23:58 PM PDT 24 Aug 15 04:53:44 PM PDT 24 336507470000 ps
T80 /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.421428555 Aug 15 04:23:28 PM PDT 24 Aug 15 04:56:23 PM PDT 24 336680370000 ps
T81 /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.3097096389 Aug 15 04:23:03 PM PDT 24 Aug 15 05:01:03 PM PDT 24 337074930000 ps
T82 /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.2755257061 Aug 15 04:23:17 PM PDT 24 Aug 15 04:55:57 PM PDT 24 336456070000 ps
T83 /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.135791304 Aug 15 04:23:09 PM PDT 24 Aug 15 05:00:13 PM PDT 24 336798590000 ps
T84 /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.4169122223 Aug 15 04:23:19 PM PDT 24 Aug 15 04:54:52 PM PDT 24 336976050000 ps
T85 /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.3454658445 Aug 15 04:19:21 PM PDT 24 Aug 15 05:00:46 PM PDT 24 336763890000 ps
T86 /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.550129256 Aug 15 04:23:24 PM PDT 24 Aug 15 04:55:06 PM PDT 24 337009150000 ps
T87 /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.612243106 Aug 15 04:23:27 PM PDT 24 Aug 15 04:56:41 PM PDT 24 337089270000 ps
T88 /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.429129111 Aug 15 04:23:32 PM PDT 24 Aug 15 04:57:28 PM PDT 24 336614470000 ps
T89 /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.2325100448 Aug 15 04:23:12 PM PDT 24 Aug 15 04:55:59 PM PDT 24 336319910000 ps
T90 /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.4143410028 Aug 15 04:23:23 PM PDT 24 Aug 15 04:50:23 PM PDT 24 336682530000 ps
T91 /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.3637110824 Aug 15 04:23:11 PM PDT 24 Aug 15 04:53:53 PM PDT 24 336473250000 ps
T92 /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.2969254162 Aug 15 04:23:21 PM PDT 24 Aug 15 04:50:38 PM PDT 24 336458390000 ps
T93 /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.2492317337 Aug 15 04:21:37 PM PDT 24 Aug 15 04:55:35 PM PDT 24 336934230000 ps
T94 /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.335176055 Aug 15 04:23:32 PM PDT 24 Aug 15 04:55:19 PM PDT 24 336580550000 ps
T95 /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.4129336280 Aug 15 04:23:23 PM PDT 24 Aug 15 04:55:42 PM PDT 24 336405570000 ps
T96 /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.3756260963 Aug 15 04:23:58 PM PDT 24 Aug 15 04:52:46 PM PDT 24 336747950000 ps
T97 /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.513886380 Aug 15 04:22:59 PM PDT 24 Aug 15 04:47:47 PM PDT 24 336834890000 ps
T98 /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.3621728496 Aug 15 04:20:53 PM PDT 24 Aug 15 05:00:20 PM PDT 24 336430150000 ps
T99 /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.315258242 Aug 15 04:22:58 PM PDT 24 Aug 15 04:51:58 PM PDT 24 337103090000 ps
T100 /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.1670389363 Aug 15 04:23:57 PM PDT 24 Aug 15 04:52:45 PM PDT 24 336800250000 ps
T101 /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.1900734936 Aug 15 04:20:54 PM PDT 24 Aug 15 05:00:00 PM PDT 24 336478710000 ps
T102 /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.2629709250 Aug 15 04:23:19 PM PDT 24 Aug 15 04:54:44 PM PDT 24 336894930000 ps
T103 /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.775217584 Aug 15 04:23:28 PM PDT 24 Aug 15 04:53:10 PM PDT 24 336910090000 ps
T104 /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.787319945 Aug 15 04:23:21 PM PDT 24 Aug 15 04:51:10 PM PDT 24 336982750000 ps
T105 /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.3011111436 Aug 15 04:23:22 PM PDT 24 Aug 15 04:55:24 PM PDT 24 337062550000 ps
T106 /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.2729423946 Aug 15 04:23:28 PM PDT 24 Aug 15 04:56:47 PM PDT 24 336892130000 ps
T107 /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.3858008203 Aug 15 04:23:19 PM PDT 24 Aug 15 04:52:23 PM PDT 24 336584310000 ps
T108 /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.1248346287 Aug 15 04:21:34 PM PDT 24 Aug 15 04:53:25 PM PDT 24 336783450000 ps
T109 /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.3992956102 Aug 15 04:19:39 PM PDT 24 Aug 15 04:47:32 PM PDT 24 336552670000 ps
T110 /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.1833652196 Aug 15 04:23:02 PM PDT 24 Aug 15 05:00:35 PM PDT 24 337067650000 ps
T4 /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.265166019 Aug 15 04:23:11 PM PDT 24 Aug 15 04:54:14 PM PDT 24 336482650000 ps
T5 /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.3395677952 Aug 15 04:19:31 PM PDT 24 Aug 15 04:54:51 PM PDT 24 336690510000 ps
T6 /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.3704961447 Aug 15 04:23:29 PM PDT 24 Aug 15 04:56:50 PM PDT 24 336538990000 ps
T24 /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.4121632180 Aug 15 04:23:15 PM PDT 24 Aug 15 04:54:01 PM PDT 24 336766450000 ps
T25 /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.1394729950 Aug 15 04:24:24 PM PDT 24 Aug 15 04:57:30 PM PDT 24 336509370000 ps
T26 /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.2025825959 Aug 15 04:23:32 PM PDT 24 Aug 15 04:56:57 PM PDT 24 337104910000 ps
T27 /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.431945585 Aug 15 04:23:15 PM PDT 24 Aug 15 04:55:33 PM PDT 24 336913430000 ps
T28 /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.1421480970 Aug 15 04:24:24 PM PDT 24 Aug 15 04:57:49 PM PDT 24 336834950000 ps
T29 /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.2584702904 Aug 15 04:23:17 PM PDT 24 Aug 15 04:56:22 PM PDT 24 336362850000 ps
T30 /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.1435342449 Aug 15 04:20:48 PM PDT 24 Aug 15 04:47:41 PM PDT 24 336379670000 ps
T111 /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.317402133 Aug 15 04:23:27 PM PDT 24 Aug 15 04:56:37 PM PDT 24 336545870000 ps
T112 /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.3181461596 Aug 15 04:23:59 PM PDT 24 Aug 15 04:50:25 PM PDT 24 336926430000 ps
T113 /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.729709255 Aug 15 04:23:02 PM PDT 24 Aug 15 05:00:42 PM PDT 24 337080850000 ps
T114 /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.57031766 Aug 15 04:23:10 PM PDT 24 Aug 15 04:53:47 PM PDT 24 337026790000 ps
T115 /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.3421651259 Aug 15 04:23:15 PM PDT 24 Aug 15 04:53:36 PM PDT 24 337107990000 ps
T116 /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.4042972688 Aug 15 04:19:33 PM PDT 24 Aug 15 04:56:49 PM PDT 24 336859430000 ps
T117 /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.3030021326 Aug 15 04:24:22 PM PDT 24 Aug 15 04:53:18 PM PDT 24 336656930000 ps
T118 /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.98302652 Aug 15 04:23:32 PM PDT 24 Aug 15 04:55:55 PM PDT 24 336747850000 ps
T119 /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.908695004 Aug 15 04:22:54 PM PDT 24 Aug 15 04:50:51 PM PDT 24 336542110000 ps
T120 /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.1372354576 Aug 15 04:19:28 PM PDT 24 Aug 15 04:53:42 PM PDT 24 336624770000 ps
T121 /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1316442904 Aug 15 04:24:00 PM PDT 24 Aug 15 04:50:07 PM PDT 24 336526610000 ps
T122 /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.203985708 Aug 15 04:23:16 PM PDT 24 Aug 15 04:53:28 PM PDT 24 336299570000 ps
T123 /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.2108244462 Aug 15 04:24:23 PM PDT 24 Aug 15 04:53:17 PM PDT 24 336444110000 ps
T124 /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.2969764571 Aug 15 04:23:28 PM PDT 24 Aug 15 04:53:12 PM PDT 24 337116490000 ps
T125 /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.2899669957 Aug 15 04:23:11 PM PDT 24 Aug 15 04:54:03 PM PDT 24 336974570000 ps
T126 /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.3422656134 Aug 15 04:23:09 PM PDT 24 Aug 15 05:00:40 PM PDT 24 336595530000 ps
T127 /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.1123995365 Aug 15 04:23:00 PM PDT 24 Aug 15 04:51:16 PM PDT 24 337042990000 ps
T128 /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.1849698142 Aug 15 04:22:57 PM PDT 24 Aug 15 04:52:29 PM PDT 24 336554590000 ps
T129 /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.1481590566 Aug 15 04:23:16 PM PDT 24 Aug 15 04:54:29 PM PDT 24 336461190000 ps
T130 /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.2143810585 Aug 15 04:23:09 PM PDT 24 Aug 15 05:00:55 PM PDT 24 336899470000 ps
T131 /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.1875680431 Aug 15 04:22:55 PM PDT 24 Aug 15 04:50:25 PM PDT 24 336883950000 ps
T132 /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.2205231809 Aug 15 04:24:22 PM PDT 24 Aug 15 05:09:35 PM PDT 24 336805190000 ps
T133 /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.712380021 Aug 15 04:23:14 PM PDT 24 Aug 15 04:55:08 PM PDT 24 336676990000 ps
T134 /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.635229666 Aug 15 04:21:14 PM PDT 24 Aug 15 04:55:12 PM PDT 24 336870190000 ps
T135 /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.3338095984 Aug 15 04:20:22 PM PDT 24 Aug 15 04:51:06 PM PDT 24 336463910000 ps
T136 /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.140685008 Aug 15 04:23:03 PM PDT 24 Aug 15 04:59:47 PM PDT 24 337027130000 ps
T137 /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.2269982414 Aug 15 04:23:09 PM PDT 24 Aug 15 04:52:07 PM PDT 24 336720870000 ps
T138 /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.4068528849 Aug 15 04:20:36 PM PDT 24 Aug 15 04:59:21 PM PDT 24 337072450000 ps
T139 /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.597428184 Aug 15 04:20:38 PM PDT 24 Aug 15 04:55:53 PM PDT 24 336531050000 ps
T140 /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.3752174924 Aug 15 04:23:20 PM PDT 24 Aug 15 04:54:10 PM PDT 24 336345910000 ps
T141 /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.4289415942 Aug 15 04:23:17 PM PDT 24 Aug 15 04:56:32 PM PDT 24 336757810000 ps
T142 /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.2532412557 Aug 15 04:22:00 PM PDT 24 Aug 15 05:03:17 PM PDT 24 337071950000 ps
T143 /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2432249920 Aug 15 04:23:02 PM PDT 24 Aug 15 04:52:47 PM PDT 24 337094950000 ps
T144 /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.3004114399 Aug 15 04:24:21 PM PDT 24 Aug 15 05:09:55 PM PDT 24 336460430000 ps
T145 /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.727902582 Aug 15 04:23:17 PM PDT 24 Aug 15 04:56:40 PM PDT 24 336457270000 ps
T146 /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.2186755492 Aug 15 04:23:22 PM PDT 24 Aug 15 04:54:35 PM PDT 24 336759010000 ps
T147 /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.827104450 Aug 15 04:24:04 PM PDT 24 Aug 15 05:09:19 PM PDT 24 336899250000 ps
T148 /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.44326971 Aug 15 04:23:30 PM PDT 24 Aug 15 04:56:25 PM PDT 24 336867050000 ps
T149 /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.3342436393 Aug 15 04:23:15 PM PDT 24 Aug 15 04:55:30 PM PDT 24 336371910000 ps
T150 /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.784461438 Aug 15 04:24:24 PM PDT 24 Aug 15 04:52:17 PM PDT 24 336432910000 ps
T151 /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.1891343274 Aug 15 04:23:22 PM PDT 24 Aug 15 04:23:30 PM PDT 24 1481410000 ps
T152 /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.3283042708 Aug 15 04:20:36 PM PDT 24 Aug 15 04:20:50 PM PDT 24 1546490000 ps
T153 /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1423523050 Aug 15 04:24:04 PM PDT 24 Aug 15 04:24:13 PM PDT 24 1502530000 ps
T154 /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.2511065808 Aug 15 04:20:30 PM PDT 24 Aug 15 04:20:42 PM PDT 24 1567990000 ps
T155 /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.4253253409 Aug 15 04:23:15 PM PDT 24 Aug 15 04:23:24 PM PDT 24 1483510000 ps
T156 /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.2165963270 Aug 15 04:24:24 PM PDT 24 Aug 15 04:24:33 PM PDT 24 1414170000 ps
T157 /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.3813285048 Aug 15 04:18:41 PM PDT 24 Aug 15 04:18:48 PM PDT 24 1198350000 ps
T158 /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.1116058342 Aug 15 04:22:59 PM PDT 24 Aug 15 04:23:08 PM PDT 24 1173110000 ps
T159 /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.427789501 Aug 15 04:23:14 PM PDT 24 Aug 15 04:23:24 PM PDT 24 1476790000 ps
T160 /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.1195187848 Aug 15 04:24:24 PM PDT 24 Aug 15 04:24:32 PM PDT 24 1375750000 ps
T161 /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.1650400193 Aug 15 04:23:18 PM PDT 24 Aug 15 04:23:27 PM PDT 24 1357510000 ps
T162 /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.4093946150 Aug 15 04:23:02 PM PDT 24 Aug 15 04:23:10 PM PDT 24 1498770000 ps
T163 /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.1368193872 Aug 15 04:22:54 PM PDT 24 Aug 15 04:23:02 PM PDT 24 1437530000 ps
T164 /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.424033510 Aug 15 04:24:24 PM PDT 24 Aug 15 04:24:34 PM PDT 24 1534110000 ps
T165 /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.4104299063 Aug 15 04:24:04 PM PDT 24 Aug 15 04:24:11 PM PDT 24 1100270000 ps
T166 /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.2711111709 Aug 15 04:23:15 PM PDT 24 Aug 15 04:23:23 PM PDT 24 1456470000 ps
T167 /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.2600944252 Aug 15 04:24:04 PM PDT 24 Aug 15 04:24:13 PM PDT 24 1523990000 ps
T168 /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.42890691 Aug 15 04:23:00 PM PDT 24 Aug 15 04:23:09 PM PDT 24 1314790000 ps
T169 /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1345078062 Aug 15 04:23:18 PM PDT 24 Aug 15 04:23:27 PM PDT 24 1412850000 ps
T170 /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2161084517 Aug 15 04:20:48 PM PDT 24 Aug 15 04:20:57 PM PDT 24 1393890000 ps
T171 /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.1364844113 Aug 15 04:24:06 PM PDT 24 Aug 15 04:24:14 PM PDT 24 1570670000 ps
T172 /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.143023124 Aug 15 04:24:04 PM PDT 24 Aug 15 04:24:13 PM PDT 24 1535650000 ps
T173 /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.3486606498 Aug 15 04:23:09 PM PDT 24 Aug 15 04:23:17 PM PDT 24 1358590000 ps
T174 /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.1973791396 Aug 15 04:23:15 PM PDT 24 Aug 15 04:23:21 PM PDT 24 1313330000 ps
T175 /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.3292232454 Aug 15 04:24:04 PM PDT 24 Aug 15 04:24:11 PM PDT 24 1189750000 ps
T176 /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.1132003172 Aug 15 04:23:27 PM PDT 24 Aug 15 04:23:34 PM PDT 24 1327070000 ps
T177 /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.2639058633 Aug 15 04:19:58 PM PDT 24 Aug 15 04:20:10 PM PDT 24 1519970000 ps
T178 /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.2382747223 Aug 15 04:23:18 PM PDT 24 Aug 15 04:23:27 PM PDT 24 1347890000 ps
T179 /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.1089577087 Aug 15 04:23:20 PM PDT 24 Aug 15 04:23:32 PM PDT 24 1603250000 ps
T180 /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.2849883698 Aug 15 04:24:24 PM PDT 24 Aug 15 04:24:33 PM PDT 24 1533430000 ps
T181 /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.133699886 Aug 15 04:23:50 PM PDT 24 Aug 15 04:23:59 PM PDT 24 1437990000 ps
T182 /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.871757953 Aug 15 04:21:54 PM PDT 24 Aug 15 04:22:03 PM PDT 24 1257650000 ps
T183 /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.1401165188 Aug 15 04:20:25 PM PDT 24 Aug 15 04:20:35 PM PDT 24 1427370000 ps
T184 /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.1391426563 Aug 15 04:23:02 PM PDT 24 Aug 15 04:23:12 PM PDT 24 1422650000 ps
T185 /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.3946013281 Aug 15 04:20:54 PM PDT 24 Aug 15 04:21:03 PM PDT 24 1440850000 ps
T186 /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.844542522 Aug 15 04:23:19 PM PDT 24 Aug 15 04:23:27 PM PDT 24 1251270000 ps
T187 /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.294888487 Aug 15 04:23:19 PM PDT 24 Aug 15 04:23:27 PM PDT 24 1240010000 ps
T188 /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.3553334144 Aug 15 04:19:26 PM PDT 24 Aug 15 04:19:36 PM PDT 24 1482710000 ps
T189 /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.18509496 Aug 15 04:20:48 PM PDT 24 Aug 15 04:20:56 PM PDT 24 1345430000 ps
T190 /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.3249324993 Aug 15 04:23:34 PM PDT 24 Aug 15 04:23:41 PM PDT 24 1423810000 ps
T191 /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.9619027 Aug 15 04:23:15 PM PDT 24 Aug 15 04:23:22 PM PDT 24 1417150000 ps
T192 /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.2468769367 Aug 15 04:23:21 PM PDT 24 Aug 15 04:23:31 PM PDT 24 1359630000 ps
T193 /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.2571753095 Aug 15 04:18:30 PM PDT 24 Aug 15 04:18:39 PM PDT 24 1341390000 ps
T194 /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.4051469219 Aug 15 04:24:00 PM PDT 24 Aug 15 04:24:06 PM PDT 24 1231530000 ps
T195 /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.1739185884 Aug 15 04:23:31 PM PDT 24 Aug 15 04:23:38 PM PDT 24 1486990000 ps
T196 /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.3255652904 Aug 15 04:23:46 PM PDT 24 Aug 15 04:23:54 PM PDT 24 1581050000 ps
T197 /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.3880367079 Aug 15 04:23:19 PM PDT 24 Aug 15 04:23:28 PM PDT 24 1561690000 ps
T198 /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.961352137 Aug 15 04:23:51 PM PDT 24 Aug 15 04:23:59 PM PDT 24 1361550000 ps
T199 /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.1827300762 Aug 15 04:23:30 PM PDT 24 Aug 15 04:23:41 PM PDT 24 1553770000 ps
T200 /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.815137968 Aug 15 04:21:12 PM PDT 24 Aug 15 04:21:23 PM PDT 24 1407270000 ps

Test location /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.3967054776
Short name T9
Test name
Test status
Simulation time 1499490000 ps
CPU time 4.63 seconds
Started Aug 15 04:23:32 PM PDT 24
Finished Aug 15 04:23:42 PM PDT 24
Peak memory 164344 kb
Host smart-41b916a6-e273-4a05-8182-096760399ef8
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3967054776 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.3967054776
Directory /workspace/0.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.3440937805
Short name T21
Test name
Test status
Simulation time 337085890000 ps
CPU time 631.05 seconds
Started Aug 15 04:24:01 PM PDT 24
Finished Aug 15 04:50:04 PM PDT 24
Peak memory 160428 kb
Host smart-572268d8-180d-415c-8939-8b85950f091f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3440937805 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.3440937805
Directory /workspace/16.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.4121632180
Short name T24
Test name
Test status
Simulation time 336766450000 ps
CPU time 753.02 seconds
Started Aug 15 04:23:15 PM PDT 24
Finished Aug 15 04:54:01 PM PDT 24
Peak memory 160616 kb
Host smart-b57f81f6-4fa1-44d8-962f-71e24310ebbf
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4121632180 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.4121632180
Directory /workspace/15.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.827104450
Short name T147
Test name
Test status
Simulation time 336899250000 ps
CPU time 1089.27 seconds
Started Aug 15 04:24:04 PM PDT 24
Finished Aug 15 05:09:19 PM PDT 24
Peak memory 159140 kb
Host smart-ae97c5df-191e-4597-8b28-9367a57e1d87
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=827104450 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.827104450
Directory /workspace/0.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.4289415942
Short name T141
Test name
Test status
Simulation time 336757810000 ps
CPU time 796.66 seconds
Started Aug 15 04:23:17 PM PDT 24
Finished Aug 15 04:56:32 PM PDT 24
Peak memory 160208 kb
Host smart-fbe61344-15be-45e0-8524-fbcce27a7161
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4289415942 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.4289415942
Directory /workspace/1.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.2108244462
Short name T123
Test name
Test status
Simulation time 336444110000 ps
CPU time 702.07 seconds
Started Aug 15 04:24:23 PM PDT 24
Finished Aug 15 04:53:17 PM PDT 24
Peak memory 160644 kb
Host smart-f8660717-86e3-47b4-924c-667022c19a8e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2108244462 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.2108244462
Directory /workspace/10.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.140685008
Short name T136
Test name
Test status
Simulation time 337027130000 ps
CPU time 867.84 seconds
Started Aug 15 04:23:03 PM PDT 24
Finished Aug 15 04:59:47 PM PDT 24
Peak memory 160292 kb
Host smart-c8d8b821-360b-4ad7-aca7-e1ce4ab8901a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=140685008 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.140685008
Directory /workspace/11.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.1372354576
Short name T120
Test name
Test status
Simulation time 336624770000 ps
CPU time 848.95 seconds
Started Aug 15 04:19:28 PM PDT 24
Finished Aug 15 04:53:42 PM PDT 24
Peak memory 159388 kb
Host smart-0394aeb5-62a8-49d4-9e86-8124227e2e72
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1372354576 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.1372354576
Directory /workspace/12.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.1123995365
Short name T127
Test name
Test status
Simulation time 337042990000 ps
CPU time 697 seconds
Started Aug 15 04:23:00 PM PDT 24
Finished Aug 15 04:51:16 PM PDT 24
Peak memory 159224 kb
Host smart-8672f1ca-460a-4275-942f-45efb2d9df13
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1123995365 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.1123995365
Directory /workspace/13.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.3421651259
Short name T115
Test name
Test status
Simulation time 337107990000 ps
CPU time 740.17 seconds
Started Aug 15 04:23:15 PM PDT 24
Finished Aug 15 04:53:36 PM PDT 24
Peak memory 160620 kb
Host smart-f210fa6c-a599-4975-a005-d3fb8ead9749
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3421651259 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.3421651259
Directory /workspace/14.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.2532412557
Short name T142
Test name
Test status
Simulation time 337071950000 ps
CPU time 1011.46 seconds
Started Aug 15 04:22:00 PM PDT 24
Finished Aug 15 05:03:17 PM PDT 24
Peak memory 160724 kb
Host smart-bf8a8775-0a01-4fd2-9a26-48e592e6a70d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2532412557 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.2532412557
Directory /workspace/16.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.2186755492
Short name T146
Test name
Test status
Simulation time 336759010000 ps
CPU time 751.55 seconds
Started Aug 15 04:23:22 PM PDT 24
Finished Aug 15 04:54:35 PM PDT 24
Peak memory 160228 kb
Host smart-5f8046ad-aec0-48b7-aaa6-0b0ce757d6d6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2186755492 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.2186755492
Directory /workspace/17.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.98302652
Short name T118
Test name
Test status
Simulation time 336747850000 ps
CPU time 773.98 seconds
Started Aug 15 04:23:32 PM PDT 24
Finished Aug 15 04:55:55 PM PDT 24
Peak memory 160424 kb
Host smart-c60fb7a2-6144-42b3-ba63-012162dfa048
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=98302652 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.98302652
Directory /workspace/18.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2432249920
Short name T143
Test name
Test status
Simulation time 337094950000 ps
CPU time 727.76 seconds
Started Aug 15 04:23:02 PM PDT 24
Finished Aug 15 04:52:47 PM PDT 24
Peak memory 159712 kb
Host smart-ba6629b0-6983-49ec-a549-405b5e751237
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2432249920 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.2432249920
Directory /workspace/19.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.727902582
Short name T145
Test name
Test status
Simulation time 336457270000 ps
CPU time 808.29 seconds
Started Aug 15 04:23:17 PM PDT 24
Finished Aug 15 04:56:40 PM PDT 24
Peak memory 159516 kb
Host smart-264bf69b-4300-4e9b-a145-16dafd5f3712
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=727902582 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.727902582
Directory /workspace/2.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.57031766
Short name T114
Test name
Test status
Simulation time 337026790000 ps
CPU time 747.83 seconds
Started Aug 15 04:23:10 PM PDT 24
Finished Aug 15 04:53:47 PM PDT 24
Peak memory 160592 kb
Host smart-c9c37e6c-210f-48ef-90ca-196582dc6a06
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=57031766 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.57031766
Directory /workspace/20.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.2899669957
Short name T125
Test name
Test status
Simulation time 336974570000 ps
CPU time 739.93 seconds
Started Aug 15 04:23:11 PM PDT 24
Finished Aug 15 04:54:03 PM PDT 24
Peak memory 159384 kb
Host smart-7a930f33-56c4-4b88-928c-122a98364445
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2899669957 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.2899669957
Directory /workspace/21.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.4042972688
Short name T116
Test name
Test status
Simulation time 336859430000 ps
CPU time 917.53 seconds
Started Aug 15 04:19:33 PM PDT 24
Finished Aug 15 04:56:49 PM PDT 24
Peak memory 160644 kb
Host smart-5ffedbca-cbdf-410e-a55d-9196bdf6a26e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4042972688 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.4042972688
Directory /workspace/22.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.3752174924
Short name T140
Test name
Test status
Simulation time 336345910000 ps
CPU time 734.14 seconds
Started Aug 15 04:23:20 PM PDT 24
Finished Aug 15 04:54:10 PM PDT 24
Peak memory 160200 kb
Host smart-7bca9209-daed-40f8-84a3-c02a0673dcd8
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3752174924 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.3752174924
Directory /workspace/23.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.265166019
Short name T4
Test name
Test status
Simulation time 336482650000 ps
CPU time 741.58 seconds
Started Aug 15 04:23:11 PM PDT 24
Finished Aug 15 04:54:14 PM PDT 24
Peak memory 159420 kb
Host smart-aaab5317-68cf-44f2-aded-b0d1bab4f9cb
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=265166019 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.265166019
Directory /workspace/24.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.908695004
Short name T119
Test name
Test status
Simulation time 336542110000 ps
CPU time 687.97 seconds
Started Aug 15 04:22:54 PM PDT 24
Finished Aug 15 04:50:51 PM PDT 24
Peak memory 159396 kb
Host smart-5e6f1e52-b128-44f3-a8f4-eabd98d641a6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=908695004 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.908695004
Directory /workspace/25.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1316442904
Short name T121
Test name
Test status
Simulation time 336526610000 ps
CPU time 639.08 seconds
Started Aug 15 04:24:00 PM PDT 24
Finished Aug 15 04:50:07 PM PDT 24
Peak memory 160424 kb
Host smart-054b9e4c-beb9-4ac0-86d0-65181662dc14
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1316442904 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.1316442904
Directory /workspace/26.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.1875680431
Short name T131
Test name
Test status
Simulation time 336883950000 ps
CPU time 664.56 seconds
Started Aug 15 04:22:55 PM PDT 24
Finished Aug 15 04:50:25 PM PDT 24
Peak memory 160576 kb
Host smart-2210402e-a62f-4d0c-9cb6-08d30dbaba41
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1875680431 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.1875680431
Directory /workspace/27.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.2143810585
Short name T130
Test name
Test status
Simulation time 336899470000 ps
CPU time 911.48 seconds
Started Aug 15 04:23:09 PM PDT 24
Finished Aug 15 05:00:55 PM PDT 24
Peak memory 160276 kb
Host smart-1716c37e-aa94-4599-be96-48e6165c4d42
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2143810585 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.2143810585
Directory /workspace/28.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.2969764571
Short name T124
Test name
Test status
Simulation time 337116490000 ps
CPU time 722.14 seconds
Started Aug 15 04:23:28 PM PDT 24
Finished Aug 15 04:53:12 PM PDT 24
Peak memory 160552 kb
Host smart-d017faa6-6009-4c0f-881a-097bef42cba9
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2969764571 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.2969764571
Directory /workspace/29.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.1435342449
Short name T30
Test name
Test status
Simulation time 336379670000 ps
CPU time 659.91 seconds
Started Aug 15 04:20:48 PM PDT 24
Finished Aug 15 04:47:41 PM PDT 24
Peak memory 159004 kb
Host smart-278a00de-f4f6-4484-9080-e9e6b42e3dd6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1435342449 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.1435342449
Directory /workspace/3.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.44326971
Short name T148
Test name
Test status
Simulation time 336867050000 ps
CPU time 801.7 seconds
Started Aug 15 04:23:30 PM PDT 24
Finished Aug 15 04:56:25 PM PDT 24
Peak memory 160556 kb
Host smart-6a6bfbf1-6e6a-484a-bc95-eb92de73b125
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=44326971 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.44326971
Directory /workspace/30.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.3422656134
Short name T126
Test name
Test status
Simulation time 336595530000 ps
CPU time 897.77 seconds
Started Aug 15 04:23:09 PM PDT 24
Finished Aug 15 05:00:40 PM PDT 24
Peak memory 158760 kb
Host smart-df325015-4b17-460b-bb32-89111d6d78cc
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3422656134 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.3422656134
Directory /workspace/31.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.3395677952
Short name T5
Test name
Test status
Simulation time 336690510000 ps
CPU time 862.11 seconds
Started Aug 15 04:19:31 PM PDT 24
Finished Aug 15 04:54:51 PM PDT 24
Peak memory 160632 kb
Host smart-4999b9ce-1a97-4b16-affb-e90b4b4dcea4
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3395677952 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.3395677952
Directory /workspace/32.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.1481590566
Short name T129
Test name
Test status
Simulation time 336461190000 ps
CPU time 747.78 seconds
Started Aug 15 04:23:16 PM PDT 24
Finished Aug 15 04:54:29 PM PDT 24
Peak memory 159008 kb
Host smart-68572adb-58f7-4a7c-b902-ad90a437707b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1481590566 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.1481590566
Directory /workspace/33.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.203985708
Short name T122
Test name
Test status
Simulation time 336299570000 ps
CPU time 718.57 seconds
Started Aug 15 04:23:16 PM PDT 24
Finished Aug 15 04:53:28 PM PDT 24
Peak memory 160052 kb
Host smart-3071b377-6e72-49ca-8b07-249dac3a815b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=203985708 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.203985708
Directory /workspace/34.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.1849698142
Short name T128
Test name
Test status
Simulation time 336554590000 ps
CPU time 710.42 seconds
Started Aug 15 04:22:57 PM PDT 24
Finished Aug 15 04:52:29 PM PDT 24
Peak memory 159156 kb
Host smart-47686e0b-f5d8-4833-878d-e3e99ff93e0f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1849698142 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.1849698142
Directory /workspace/35.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.635229666
Short name T134
Test name
Test status
Simulation time 336870190000 ps
CPU time 824.61 seconds
Started Aug 15 04:21:14 PM PDT 24
Finished Aug 15 04:55:12 PM PDT 24
Peak memory 160620 kb
Host smart-f2764532-2441-4eb5-af6f-8cd88a74157e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=635229666 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.635229666
Directory /workspace/36.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.1394729950
Short name T25
Test name
Test status
Simulation time 336509370000 ps
CPU time 800.4 seconds
Started Aug 15 04:24:24 PM PDT 24
Finished Aug 15 04:57:30 PM PDT 24
Peak memory 160644 kb
Host smart-4c96845c-5a40-4dea-8121-d8a951315e15
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1394729950 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.1394729950
Directory /workspace/37.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.2205231809
Short name T132
Test name
Test status
Simulation time 336805190000 ps
CPU time 1068.07 seconds
Started Aug 15 04:24:22 PM PDT 24
Finished Aug 15 05:09:35 PM PDT 24
Peak memory 160624 kb
Host smart-eef59ef3-1ee5-49e0-9e94-e38b57f27b38
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2205231809 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.2205231809
Directory /workspace/38.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.3004114399
Short name T144
Test name
Test status
Simulation time 336460430000 ps
CPU time 1079.44 seconds
Started Aug 15 04:24:21 PM PDT 24
Finished Aug 15 05:09:55 PM PDT 24
Peak memory 160620 kb
Host smart-28f04ffe-6fd1-4e3e-992f-980985e73411
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3004114399 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.3004114399
Directory /workspace/39.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.2025825959
Short name T26
Test name
Test status
Simulation time 337104910000 ps
CPU time 803.4 seconds
Started Aug 15 04:23:32 PM PDT 24
Finished Aug 15 04:56:57 PM PDT 24
Peak memory 160436 kb
Host smart-252ef87e-74a5-4e4e-a5ce-8603a3131cf2
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2025825959 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.2025825959
Directory /workspace/4.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.1421480970
Short name T28
Test name
Test status
Simulation time 336834950000 ps
CPU time 811.2 seconds
Started Aug 15 04:24:24 PM PDT 24
Finished Aug 15 04:57:49 PM PDT 24
Peak memory 160644 kb
Host smart-e8f53f8b-620c-4f72-a745-3f4c78037b69
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1421480970 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.1421480970
Directory /workspace/40.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.4068528849
Short name T138
Test name
Test status
Simulation time 337072450000 ps
CPU time 925.94 seconds
Started Aug 15 04:20:36 PM PDT 24
Finished Aug 15 04:59:21 PM PDT 24
Peak memory 160720 kb
Host smart-c350c616-bcf2-4bd3-a259-a88bf284aa42
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4068528849 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.4068528849
Directory /workspace/41.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.3181461596
Short name T112
Test name
Test status
Simulation time 336926430000 ps
CPU time 644.36 seconds
Started Aug 15 04:23:59 PM PDT 24
Finished Aug 15 04:50:25 PM PDT 24
Peak memory 160624 kb
Host smart-b3c05f63-e1bb-4475-840a-b13efca91320
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3181461596 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.3181461596
Directory /workspace/42.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.597428184
Short name T139
Test name
Test status
Simulation time 336531050000 ps
CPU time 864.02 seconds
Started Aug 15 04:20:38 PM PDT 24
Finished Aug 15 04:55:53 PM PDT 24
Peak memory 160616 kb
Host smart-0fd931a2-6e04-4516-90e7-758e89861ef6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=597428184 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.597428184
Directory /workspace/43.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.2584702904
Short name T29
Test name
Test status
Simulation time 336362850000 ps
CPU time 789.46 seconds
Started Aug 15 04:23:17 PM PDT 24
Finished Aug 15 04:56:22 PM PDT 24
Peak memory 160332 kb
Host smart-2018d1d9-bf25-4a32-871b-658a1450aff0
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2584702904 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.2584702904
Directory /workspace/44.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.3338095984
Short name T135
Test name
Test status
Simulation time 336463910000 ps
CPU time 761.76 seconds
Started Aug 15 04:20:22 PM PDT 24
Finished Aug 15 04:51:06 PM PDT 24
Peak memory 160640 kb
Host smart-3108c9d4-0588-435f-a8a8-6255430488a9
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3338095984 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.3338095984
Directory /workspace/45.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.317402133
Short name T111
Test name
Test status
Simulation time 336545870000 ps
CPU time 794.8 seconds
Started Aug 15 04:23:27 PM PDT 24
Finished Aug 15 04:56:37 PM PDT 24
Peak memory 160432 kb
Host smart-f29f3f93-8abb-48fc-84bf-e90908395f25
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=317402133 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.317402133
Directory /workspace/46.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.712380021
Short name T133
Test name
Test status
Simulation time 336676990000 ps
CPU time 774.3 seconds
Started Aug 15 04:23:14 PM PDT 24
Finished Aug 15 04:55:08 PM PDT 24
Peak memory 159524 kb
Host smart-27dd9dfc-1ba0-4749-8810-b25271f55aa9
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=712380021 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.712380021
Directory /workspace/47.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.3342436393
Short name T149
Test name
Test status
Simulation time 336371910000 ps
CPU time 765.69 seconds
Started Aug 15 04:23:15 PM PDT 24
Finished Aug 15 04:55:30 PM PDT 24
Peak memory 159504 kb
Host smart-a079d477-601b-4ae5-9b26-e8f7b681f0d6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3342436393 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.3342436393
Directory /workspace/48.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.2269982414
Short name T137
Test name
Test status
Simulation time 336720870000 ps
CPU time 704.78 seconds
Started Aug 15 04:23:09 PM PDT 24
Finished Aug 15 04:52:07 PM PDT 24
Peak memory 159432 kb
Host smart-bfdb4a24-290f-4e27-af1e-e8104970ad2e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2269982414 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.2269982414
Directory /workspace/49.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.431945585
Short name T27
Test name
Test status
Simulation time 336913430000 ps
CPU time 774.81 seconds
Started Aug 15 04:23:15 PM PDT 24
Finished Aug 15 04:55:33 PM PDT 24
Peak memory 160264 kb
Host smart-2a46e241-4011-45ca-ba94-59721517391a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=431945585 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.431945585
Directory /workspace/5.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.3704961447
Short name T6
Test name
Test status
Simulation time 336538990000 ps
CPU time 806.64 seconds
Started Aug 15 04:23:29 PM PDT 24
Finished Aug 15 04:56:50 PM PDT 24
Peak memory 160584 kb
Host smart-35a4ea83-a23b-4463-a056-db2b47c63831
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3704961447 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.3704961447
Directory /workspace/6.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.729709255
Short name T113
Test name
Test status
Simulation time 337080850000 ps
CPU time 896.38 seconds
Started Aug 15 04:23:02 PM PDT 24
Finished Aug 15 05:00:42 PM PDT 24
Peak memory 159544 kb
Host smart-72971301-46be-4e8e-a77e-18affb2a7cae
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=729709255 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.729709255
Directory /workspace/7.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.3030021326
Short name T117
Test name
Test status
Simulation time 336656930000 ps
CPU time 703.02 seconds
Started Aug 15 04:24:22 PM PDT 24
Finished Aug 15 04:53:18 PM PDT 24
Peak memory 160636 kb
Host smart-7fca6c17-50d4-485b-9aba-db80765f9f61
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3030021326 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.3030021326
Directory /workspace/8.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.784461438
Short name T150
Test name
Test status
Simulation time 336432910000 ps
CPU time 674.96 seconds
Started Aug 15 04:24:24 PM PDT 24
Finished Aug 15 04:52:17 PM PDT 24
Peak memory 160616 kb
Host smart-0e8b34f8-dca0-427c-bc2c-9ec56e93a7bf
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=784461438 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.784461438
Directory /workspace/9.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.2729423946
Short name T106
Test name
Test status
Simulation time 336892130000 ps
CPU time 793.63 seconds
Started Aug 15 04:23:28 PM PDT 24
Finished Aug 15 04:56:47 PM PDT 24
Peak memory 160348 kb
Host smart-cdb8533c-b707-4093-b1f2-fbae793ebe48
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2729423946 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.2729423946
Directory /workspace/0.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.612243106
Short name T87
Test name
Test status
Simulation time 337089270000 ps
CPU time 794.18 seconds
Started Aug 15 04:23:27 PM PDT 24
Finished Aug 15 04:56:41 PM PDT 24
Peak memory 159636 kb
Host smart-eb0e56ce-c330-44c8-a359-8d71616cbd69
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=612243106 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.612243106
Directory /workspace/1.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.3011111436
Short name T105
Test name
Test status
Simulation time 337062550000 ps
CPU time 771.89 seconds
Started Aug 15 04:23:22 PM PDT 24
Finished Aug 15 04:55:24 PM PDT 24
Peak memory 160232 kb
Host smart-d9633700-6553-42d2-a194-9ef211d63028
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3011111436 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.3011111436
Directory /workspace/10.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.429129111
Short name T88
Test name
Test status
Simulation time 336614470000 ps
CPU time 822.3 seconds
Started Aug 15 04:23:32 PM PDT 24
Finished Aug 15 04:57:28 PM PDT 24
Peak memory 160620 kb
Host smart-109fc3c1-2628-4379-8a98-e9cc198e319b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=429129111 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.429129111
Directory /workspace/11.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.2629709250
Short name T102
Test name
Test status
Simulation time 336894930000 ps
CPU time 761.13 seconds
Started Aug 15 04:23:19 PM PDT 24
Finished Aug 15 04:54:44 PM PDT 24
Peak memory 160648 kb
Host smart-56e9e8c3-68e3-4757-9c08-cb647768b4b8
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2629709250 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.2629709250
Directory /workspace/12.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.2454237065
Short name T75
Test name
Test status
Simulation time 336823430000 ps
CPU time 737.25 seconds
Started Aug 15 04:23:21 PM PDT 24
Finished Aug 15 04:54:12 PM PDT 24
Peak memory 160396 kb
Host smart-1511fff5-5a74-4b8a-ad1b-fde49942a4c1
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2454237065 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.2454237065
Directory /workspace/13.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.4169122223
Short name T84
Test name
Test status
Simulation time 336976050000 ps
CPU time 766.05 seconds
Started Aug 15 04:23:19 PM PDT 24
Finished Aug 15 04:54:52 PM PDT 24
Peak memory 160648 kb
Host smart-ff1d856d-76a2-4fdb-b6d3-fa99436988ca
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4169122223 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.4169122223
Directory /workspace/14.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.3637110824
Short name T91
Test name
Test status
Simulation time 336473250000 ps
CPU time 740.33 seconds
Started Aug 15 04:23:11 PM PDT 24
Finished Aug 15 04:53:53 PM PDT 24
Peak memory 159736 kb
Host smart-ede42898-753f-4b98-82c9-225732d2b072
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3637110824 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.3637110824
Directory /workspace/15.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.775217584
Short name T103
Test name
Test status
Simulation time 336910090000 ps
CPU time 716.19 seconds
Started Aug 15 04:23:28 PM PDT 24
Finished Aug 15 04:53:10 PM PDT 24
Peak memory 160596 kb
Host smart-b0c1efb0-4f98-4ac1-93d8-e8e193d1b43a
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=775217584 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.775217584
Directory /workspace/17.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.2969254162
Short name T92
Test name
Test status
Simulation time 336458390000 ps
CPU time 658.62 seconds
Started Aug 15 04:23:21 PM PDT 24
Finished Aug 15 04:50:38 PM PDT 24
Peak memory 160520 kb
Host smart-201ddb15-f4eb-4e98-803c-a84c8c02d235
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2969254162 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.2969254162
Directory /workspace/18.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.3621728496
Short name T98
Test name
Test status
Simulation time 336430150000 ps
CPU time 962.1 seconds
Started Aug 15 04:20:53 PM PDT 24
Finished Aug 15 05:00:20 PM PDT 24
Peak memory 160908 kb
Host smart-d8f7e4e9-5592-49b5-bf63-dd42157b6a75
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3621728496 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.3621728496
Directory /workspace/19.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.2332004184
Short name T15
Test name
Test status
Simulation time 336761450000 ps
CPU time 797.09 seconds
Started Aug 15 04:18:24 PM PDT 24
Finished Aug 15 04:50:27 PM PDT 24
Peak memory 159712 kb
Host smart-796fb752-54c0-4b04-a5c3-011a51ba6c1d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2332004184 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.2332004184
Directory /workspace/2.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.787319945
Short name T104
Test name
Test status
Simulation time 336982750000 ps
CPU time 675.8 seconds
Started Aug 15 04:23:21 PM PDT 24
Finished Aug 15 04:51:10 PM PDT 24
Peak memory 160536 kb
Host smart-cbd87762-907b-4a07-88b3-f51fd010ef8b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=787319945 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.787319945
Directory /workspace/20.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3307522691
Short name T23
Test name
Test status
Simulation time 336882530000 ps
CPU time 716.35 seconds
Started Aug 15 04:23:28 PM PDT 24
Finished Aug 15 04:53:00 PM PDT 24
Peak memory 160552 kb
Host smart-b070af23-ee69-4dc7-974a-f5b9b451ba29
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3307522691 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.3307522691
Directory /workspace/21.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.3080425081
Short name T17
Test name
Test status
Simulation time 336391230000 ps
CPU time 900.96 seconds
Started Aug 15 04:23:10 PM PDT 24
Finished Aug 15 05:00:38 PM PDT 24
Peak memory 160292 kb
Host smart-0113a0e0-00f8-417c-a764-b0df7586e100
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3080425081 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.3080425081
Directory /workspace/22.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.3992956102
Short name T109
Test name
Test status
Simulation time 336552670000 ps
CPU time 666.44 seconds
Started Aug 15 04:19:39 PM PDT 24
Finished Aug 15 04:47:32 PM PDT 24
Peak memory 159764 kb
Host smart-df03c0d4-9787-46cb-a730-9afbde3b871b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3992956102 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.3992956102
Directory /workspace/23.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.135791304
Short name T83
Test name
Test status
Simulation time 336798590000 ps
CPU time 890.75 seconds
Started Aug 15 04:23:09 PM PDT 24
Finished Aug 15 05:00:13 PM PDT 24
Peak memory 160288 kb
Host smart-20eeeab0-f8ee-4e8f-889d-7d47886c486e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=135791304 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.135791304
Directory /workspace/24.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.1900734936
Short name T101
Test name
Test status
Simulation time 336478710000 ps
CPU time 952.68 seconds
Started Aug 15 04:20:54 PM PDT 24
Finished Aug 15 05:00:00 PM PDT 24
Peak memory 160908 kb
Host smart-7eff0ab2-154d-4795-8774-d7f6ab6549fc
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1900734936 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.1900734936
Directory /workspace/25.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.7824044
Short name T76
Test name
Test status
Simulation time 336310670000 ps
CPU time 901.11 seconds
Started Aug 15 04:19:21 PM PDT 24
Finished Aug 15 04:55:52 PM PDT 24
Peak memory 160624 kb
Host smart-b2ab7d8d-1cd0-436a-8766-4bb215228207
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=7824044 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.7824044
Directory /workspace/26.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.2492317337
Short name T93
Test name
Test status
Simulation time 336934230000 ps
CPU time 831.77 seconds
Started Aug 15 04:21:37 PM PDT 24
Finished Aug 15 04:55:35 PM PDT 24
Peak memory 160640 kb
Host smart-c9c793d3-7931-440c-8f04-5ab7d3a708f7
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2492317337 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.2492317337
Directory /workspace/27.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.2325100448
Short name T89
Test name
Test status
Simulation time 336319910000 ps
CPU time 798.17 seconds
Started Aug 15 04:23:12 PM PDT 24
Finished Aug 15 04:55:59 PM PDT 24
Peak memory 160604 kb
Host smart-ba980a0e-3f4a-440a-992d-c6f5f67430ec
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2325100448 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.2325100448
Directory /workspace/28.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.2320835944
Short name T71
Test name
Test status
Simulation time 337015550000 ps
CPU time 953.03 seconds
Started Aug 15 04:21:14 PM PDT 24
Finished Aug 15 05:00:23 PM PDT 24
Peak memory 160908 kb
Host smart-bb0b7fd6-a21c-43e6-95d6-317f8c4a07ec
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2320835944 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.2320835944
Directory /workspace/29.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.3097096389
Short name T81
Test name
Test status
Simulation time 337074930000 ps
CPU time 907.53 seconds
Started Aug 15 04:23:03 PM PDT 24
Finished Aug 15 05:01:03 PM PDT 24
Peak memory 160460 kb
Host smart-d94dc079-c2c2-4f8f-9831-a6e2b66c46df
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3097096389 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.3097096389
Directory /workspace/3.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.1680594630
Short name T73
Test name
Test status
Simulation time 336613050000 ps
CPU time 799.14 seconds
Started Aug 15 04:24:24 PM PDT 24
Finished Aug 15 04:57:40 PM PDT 24
Peak memory 160648 kb
Host smart-1d3d7805-556d-4d20-984a-57e424e74143
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1680594630 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.1680594630
Directory /workspace/30.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.1248346287
Short name T108
Test name
Test status
Simulation time 336783450000 ps
CPU time 779.25 seconds
Started Aug 15 04:21:34 PM PDT 24
Finished Aug 15 04:53:25 PM PDT 24
Peak memory 160656 kb
Host smart-07f58c41-7d13-4844-a1c3-3db3197e50f4
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1248346287 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.1248346287
Directory /workspace/31.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.3573324402
Short name T77
Test name
Test status
Simulation time 336395030000 ps
CPU time 799.38 seconds
Started Aug 15 04:24:24 PM PDT 24
Finished Aug 15 04:57:35 PM PDT 24
Peak memory 160628 kb
Host smart-704b21aa-e8f1-4152-9a50-8117529b18ce
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3573324402 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.3573324402
Directory /workspace/32.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.1080975755
Short name T22
Test name
Test status
Simulation time 336428230000 ps
CPU time 1089.3 seconds
Started Aug 15 04:24:21 PM PDT 24
Finished Aug 15 05:10:08 PM PDT 24
Peak memory 160624 kb
Host smart-88e66b58-0a0f-49ec-b77a-96b4d20fe712
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1080975755 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.1080975755
Directory /workspace/33.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.3513106566
Short name T19
Test name
Test status
Simulation time 336813910000 ps
CPU time 1080.07 seconds
Started Aug 15 04:24:22 PM PDT 24
Finished Aug 15 05:09:57 PM PDT 24
Peak memory 160628 kb
Host smart-029543d0-77d1-485b-8dbf-b605ab4446cf
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3513106566 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.3513106566
Directory /workspace/34.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.2722904997
Short name T18
Test name
Test status
Simulation time 336926210000 ps
CPU time 1085.62 seconds
Started Aug 15 04:24:21 PM PDT 24
Finished Aug 15 05:10:04 PM PDT 24
Peak memory 160620 kb
Host smart-8dae4660-0f5f-4769-8423-0c4d1ad6d20d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2722904997 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.2722904997
Directory /workspace/35.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.2755257061
Short name T82
Test name
Test status
Simulation time 336456070000 ps
CPU time 779.25 seconds
Started Aug 15 04:23:17 PM PDT 24
Finished Aug 15 04:55:57 PM PDT 24
Peak memory 160240 kb
Host smart-aae0cd6f-1422-4ed4-86d3-263c6b43f3c8
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2755257061 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.2755257061
Directory /workspace/36.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.402152422
Short name T74
Test name
Test status
Simulation time 336615510000 ps
CPU time 716.76 seconds
Started Aug 15 04:24:00 PM PDT 24
Finished Aug 15 04:53:16 PM PDT 24
Peak memory 160624 kb
Host smart-14c77f04-b923-439b-9035-147e2a294343
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=402152422 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.402152422
Directory /workspace/37.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.2419201964
Short name T72
Test name
Test status
Simulation time 336427610000 ps
CPU time 673.15 seconds
Started Aug 15 04:19:08 PM PDT 24
Finished Aug 15 04:47:07 PM PDT 24
Peak memory 159764 kb
Host smart-0aca5a57-dd2f-4898-9b4c-1b0ebd1db2aa
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2419201964 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.2419201964
Directory /workspace/38.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.335176055
Short name T94
Test name
Test status
Simulation time 336580550000 ps
CPU time 755.69 seconds
Started Aug 15 04:23:32 PM PDT 24
Finished Aug 15 04:55:19 PM PDT 24
Peak memory 160436 kb
Host smart-407e723f-de49-48bb-b85a-344be6e41dfb
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=335176055 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.335176055
Directory /workspace/39.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.421428555
Short name T80
Test name
Test status
Simulation time 336680370000 ps
CPU time 779.58 seconds
Started Aug 15 04:23:28 PM PDT 24
Finished Aug 15 04:56:23 PM PDT 24
Peak memory 160328 kb
Host smart-fe62b084-bffd-441f-ba00-a8ac64cafa77
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=421428555 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.421428555
Directory /workspace/4.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.4143410028
Short name T90
Test name
Test status
Simulation time 336682530000 ps
CPU time 650.69 seconds
Started Aug 15 04:23:23 PM PDT 24
Finished Aug 15 04:50:23 PM PDT 24
Peak memory 160628 kb
Host smart-612138e5-349e-4d92-a7d3-f8f3748bedb3
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4143410028 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.4143410028
Directory /workspace/40.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.315258242
Short name T99
Test name
Test status
Simulation time 337103090000 ps
CPU time 697.15 seconds
Started Aug 15 04:22:58 PM PDT 24
Finished Aug 15 04:51:58 PM PDT 24
Peak memory 160408 kb
Host smart-32a26d40-d146-4aee-a41c-860e47b0c01a
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=315258242 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.315258242
Directory /workspace/41.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.3454658445
Short name T85
Test name
Test status
Simulation time 336763890000 ps
CPU time 1013.15 seconds
Started Aug 15 04:19:21 PM PDT 24
Finished Aug 15 05:00:46 PM PDT 24
Peak memory 160632 kb
Host smart-1c7a300e-7426-4845-b846-a8edde398154
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3454658445 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.3454658445
Directory /workspace/42.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.3858008203
Short name T107
Test name
Test status
Simulation time 336584310000 ps
CPU time 700.61 seconds
Started Aug 15 04:23:19 PM PDT 24
Finished Aug 15 04:52:23 PM PDT 24
Peak memory 160460 kb
Host smart-1ac0f798-1579-461a-91fb-e17cb669aa93
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3858008203 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.3858008203
Directory /workspace/43.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.1670389363
Short name T100
Test name
Test status
Simulation time 336800250000 ps
CPU time 701.53 seconds
Started Aug 15 04:23:57 PM PDT 24
Finished Aug 15 04:52:45 PM PDT 24
Peak memory 160492 kb
Host smart-ef042b86-b502-492b-816f-ff5cfba3afd2
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1670389363 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.1670389363
Directory /workspace/44.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.1392618927
Short name T20
Test name
Test status
Simulation time 336491930000 ps
CPU time 835.91 seconds
Started Aug 15 04:23:09 PM PDT 24
Finished Aug 15 04:58:11 PM PDT 24
Peak memory 160284 kb
Host smart-f2306cad-7ce2-401b-badb-88ba31a24e1a
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1392618927 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.1392618927
Directory /workspace/45.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.1071946995
Short name T14
Test name
Test status
Simulation time 336672990000 ps
CPU time 905.2 seconds
Started Aug 15 04:23:09 PM PDT 24
Finished Aug 15 05:00:46 PM PDT 24
Peak memory 158912 kb
Host smart-5838968a-bf74-411c-95e6-b61592f14f43
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1071946995 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.1071946995
Directory /workspace/46.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.1479769577
Short name T79
Test name
Test status
Simulation time 336507470000 ps
CPU time 728.13 seconds
Started Aug 15 04:23:58 PM PDT 24
Finished Aug 15 04:53:44 PM PDT 24
Peak memory 160404 kb
Host smart-f624f3e6-0964-4636-9144-1081734e06a2
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1479769577 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.1479769577
Directory /workspace/47.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.513886380
Short name T97
Test name
Test status
Simulation time 336834890000 ps
CPU time 607.01 seconds
Started Aug 15 04:22:59 PM PDT 24
Finished Aug 15 04:47:47 PM PDT 24
Peak memory 160300 kb
Host smart-451b6909-23a5-41a2-8081-47319846ad77
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=513886380 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.513886380
Directory /workspace/48.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.3756260963
Short name T96
Test name
Test status
Simulation time 336747950000 ps
CPU time 702.72 seconds
Started Aug 15 04:23:58 PM PDT 24
Finished Aug 15 04:52:46 PM PDT 24
Peak memory 160492 kb
Host smart-36481159-8d2f-4859-951d-3cd76ba1aebd
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3756260963 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.3756260963
Directory /workspace/49.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.1833652196
Short name T110
Test name
Test status
Simulation time 337067650000 ps
CPU time 896.81 seconds
Started Aug 15 04:23:02 PM PDT 24
Finished Aug 15 05:00:35 PM PDT 24
Peak memory 159332 kb
Host smart-39752f67-7b92-4141-8709-abf64ab4e40c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1833652196 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.1833652196
Directory /workspace/5.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.2412860465
Short name T16
Test name
Test status
Simulation time 336317270000 ps
CPU time 789.83 seconds
Started Aug 15 04:23:28 PM PDT 24
Finished Aug 15 04:56:43 PM PDT 24
Peak memory 160412 kb
Host smart-07f3d684-a12d-4080-883e-b7c2056d853d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2412860465 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.2412860465
Directory /workspace/6.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.4129336280
Short name T95
Test name
Test status
Simulation time 336405570000 ps
CPU time 785.73 seconds
Started Aug 15 04:23:23 PM PDT 24
Finished Aug 15 04:55:42 PM PDT 24
Peak memory 160464 kb
Host smart-0359b9e9-2ebd-4f86-9fc8-11f560660c09
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4129336280 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.4129336280
Directory /workspace/7.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.550129256
Short name T86
Test name
Test status
Simulation time 337009150000 ps
CPU time 762.8 seconds
Started Aug 15 04:23:24 PM PDT 24
Finished Aug 15 04:55:06 PM PDT 24
Peak memory 160460 kb
Host smart-be89c602-9c71-4f3e-b585-8bc651f2a553
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=550129256 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.550129256
Directory /workspace/8.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.2931736740
Short name T78
Test name
Test status
Simulation time 336603850000 ps
CPU time 761.69 seconds
Started Aug 15 04:23:22 PM PDT 24
Finished Aug 15 04:54:59 PM PDT 24
Peak memory 160224 kb
Host smart-2157c1b2-245b-4991-9256-f83566700ff3
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2931736740 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.2931736740
Directory /workspace/9.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.2849883698
Short name T180
Test name
Test status
Simulation time 1533430000 ps
CPU time 4.32 seconds
Started Aug 15 04:24:24 PM PDT 24
Finished Aug 15 04:24:33 PM PDT 24
Peak memory 164468 kb
Host smart-36f5c5af-58ef-45bb-bb53-3c079d00a8ae
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2849883698 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.2849883698
Directory /workspace/0.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.3255652904
Short name T196
Test name
Test status
Simulation time 1581050000 ps
CPU time 3.37 seconds
Started Aug 15 04:23:46 PM PDT 24
Finished Aug 15 04:23:54 PM PDT 24
Peak memory 164280 kb
Host smart-46259b7f-b42a-4faa-9fc0-54ad6d95c472
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3255652904 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.3255652904
Directory /workspace/1.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.2571753095
Short name T193
Test name
Test status
Simulation time 1341390000 ps
CPU time 4.16 seconds
Started Aug 15 04:18:30 PM PDT 24
Finished Aug 15 04:18:39 PM PDT 24
Peak memory 163652 kb
Host smart-2041c31f-553b-4944-a010-a218e66b0f55
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2571753095 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.2571753095
Directory /workspace/10.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.1132003172
Short name T176
Test name
Test status
Simulation time 1327070000 ps
CPU time 3.28 seconds
Started Aug 15 04:23:27 PM PDT 24
Finished Aug 15 04:23:34 PM PDT 24
Peak memory 164476 kb
Host smart-2f5d35a1-faab-46b8-9f21-e90a231c13ba
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1132003172 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.1132003172
Directory /workspace/11.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.18509496
Short name T189
Test name
Test status
Simulation time 1345430000 ps
CPU time 4.02 seconds
Started Aug 15 04:20:48 PM PDT 24
Finished Aug 15 04:20:56 PM PDT 24
Peak memory 162908 kb
Host smart-30aed8ed-3036-40d1-88a9-be4cdffed225
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=18509496 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.18509496
Directory /workspace/12.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.3813285048
Short name T157
Test name
Test status
Simulation time 1198350000 ps
CPU time 3.42 seconds
Started Aug 15 04:18:41 PM PDT 24
Finished Aug 15 04:18:48 PM PDT 24
Peak memory 164520 kb
Host smart-19bd191b-e96b-434a-917f-bca028f6f01a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3813285048 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.3813285048
Directory /workspace/13.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.3946013281
Short name T185
Test name
Test status
Simulation time 1440850000 ps
CPU time 4 seconds
Started Aug 15 04:20:54 PM PDT 24
Finished Aug 15 04:21:03 PM PDT 24
Peak memory 166208 kb
Host smart-2e5ff20e-e0ff-40e7-801e-a252e5e0c671
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3946013281 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.3946013281
Directory /workspace/14.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.9619027
Short name T191
Test name
Test status
Simulation time 1417150000 ps
CPU time 3.19 seconds
Started Aug 15 04:23:15 PM PDT 24
Finished Aug 15 04:23:22 PM PDT 24
Peak memory 164036 kb
Host smart-5e9cd741-d8b2-4deb-8928-a0d015004297
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=9619027 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.9619027
Directory /workspace/15.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.1827300762
Short name T199
Test name
Test status
Simulation time 1553770000 ps
CPU time 4.79 seconds
Started Aug 15 04:23:30 PM PDT 24
Finished Aug 15 04:23:41 PM PDT 24
Peak memory 164480 kb
Host smart-0fe37ede-ecce-4519-930f-66de039f4588
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1827300762 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.1827300762
Directory /workspace/16.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.2711111709
Short name T166
Test name
Test status
Simulation time 1456470000 ps
CPU time 3.84 seconds
Started Aug 15 04:23:15 PM PDT 24
Finished Aug 15 04:23:23 PM PDT 24
Peak memory 164352 kb
Host smart-f6cf8033-6fe5-41f4-b31a-54e3456c9651
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2711111709 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.2711111709
Directory /workspace/17.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.424033510
Short name T164
Test name
Test status
Simulation time 1534110000 ps
CPU time 4.26 seconds
Started Aug 15 04:24:24 PM PDT 24
Finished Aug 15 04:24:34 PM PDT 24
Peak memory 164684 kb
Host smart-b95675aa-6c98-48d7-a629-b709bf06a771
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=424033510 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.424033510
Directory /workspace/18.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.2165963270
Short name T156
Test name
Test status
Simulation time 1414170000 ps
CPU time 3.94 seconds
Started Aug 15 04:24:24 PM PDT 24
Finished Aug 15 04:24:33 PM PDT 24
Peak memory 164696 kb
Host smart-bacf2537-6fec-4c43-832d-cc4e0dffbaff
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2165963270 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.2165963270
Directory /workspace/19.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.3553334144
Short name T188
Test name
Test status
Simulation time 1482710000 ps
CPU time 4.49 seconds
Started Aug 15 04:19:26 PM PDT 24
Finished Aug 15 04:19:36 PM PDT 24
Peak memory 164688 kb
Host smart-cbed9fc7-8bf3-4b00-b2c1-717a54e77c3f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3553334144 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.3553334144
Directory /workspace/2.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.4093946150
Short name T162
Test name
Test status
Simulation time 1498770000 ps
CPU time 3.74 seconds
Started Aug 15 04:23:02 PM PDT 24
Finished Aug 15 04:23:10 PM PDT 24
Peak memory 164488 kb
Host smart-922f4269-0a92-4b6b-9625-30ba6abfdd46
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4093946150 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.4093946150
Directory /workspace/20.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.42890691
Short name T168
Test name
Test status
Simulation time 1314790000 ps
CPU time 3.82 seconds
Started Aug 15 04:23:00 PM PDT 24
Finished Aug 15 04:23:09 PM PDT 24
Peak memory 162860 kb
Host smart-0a32f214-e790-4e87-949c-3e518618d4b3
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=42890691 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.42890691
Directory /workspace/21.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.4253253409
Short name T155
Test name
Test status
Simulation time 1483510000 ps
CPU time 3.93 seconds
Started Aug 15 04:23:15 PM PDT 24
Finished Aug 15 04:23:24 PM PDT 24
Peak memory 164732 kb
Host smart-a8e32b0e-e84d-4631-b9d6-545d5d26bb78
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4253253409 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.4253253409
Directory /workspace/22.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.3283042708
Short name T152
Test name
Test status
Simulation time 1546490000 ps
CPU time 5.89 seconds
Started Aug 15 04:20:36 PM PDT 24
Finished Aug 15 04:20:50 PM PDT 24
Peak memory 164780 kb
Host smart-2b87e08e-23ca-43d4-9d69-8569f98c2cc1
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3283042708 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.3283042708
Directory /workspace/23.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.1391426563
Short name T184
Test name
Test status
Simulation time 1422650000 ps
CPU time 4.26 seconds
Started Aug 15 04:23:02 PM PDT 24
Finished Aug 15 04:23:12 PM PDT 24
Peak memory 163252 kb
Host smart-cdf68a3f-3eec-4d58-aee6-4955ed989f16
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1391426563 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.1391426563
Directory /workspace/24.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.961352137
Short name T198
Test name
Test status
Simulation time 1361550000 ps
CPU time 3.52 seconds
Started Aug 15 04:23:51 PM PDT 24
Finished Aug 15 04:23:59 PM PDT 24
Peak memory 164732 kb
Host smart-53c81b6f-d51c-4387-8bb9-fc56d9906ebf
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=961352137 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.961352137
Directory /workspace/25.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.1364844113
Short name T171
Test name
Test status
Simulation time 1570670000 ps
CPU time 3.26 seconds
Started Aug 15 04:24:06 PM PDT 24
Finished Aug 15 04:24:14 PM PDT 24
Peak memory 164324 kb
Host smart-e796617f-2197-4417-ab2c-08980aa67358
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1364844113 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.1364844113
Directory /workspace/26.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.3486606498
Short name T173
Test name
Test status
Simulation time 1358590000 ps
CPU time 3.56 seconds
Started Aug 15 04:23:09 PM PDT 24
Finished Aug 15 04:23:17 PM PDT 24
Peak memory 164744 kb
Host smart-9f029eb1-bfbf-4c78-81c4-874c01d4ea81
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3486606498 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.3486606498
Directory /workspace/27.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.2639058633
Short name T177
Test name
Test status
Simulation time 1519970000 ps
CPU time 5.37 seconds
Started Aug 15 04:19:58 PM PDT 24
Finished Aug 15 04:20:10 PM PDT 24
Peak memory 164740 kb
Host smart-f8ce9afa-0c0a-4c55-884b-ec6f8cdef86e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2639058633 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.2639058633
Directory /workspace/28.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.1891343274
Short name T151
Test name
Test status
Simulation time 1481410000 ps
CPU time 3.51 seconds
Started Aug 15 04:23:22 PM PDT 24
Finished Aug 15 04:23:30 PM PDT 24
Peak memory 164804 kb
Host smart-cf0e0c3e-699c-4255-9bf8-ab8fffa454e1
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1891343274 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.1891343274
Directory /workspace/29.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.4104299063
Short name T165
Test name
Test status
Simulation time 1100270000 ps
CPU time 3.07 seconds
Started Aug 15 04:24:04 PM PDT 24
Finished Aug 15 04:24:11 PM PDT 24
Peak memory 164728 kb
Host smart-6715eca8-b482-4a9f-9a60-c95c1f253542
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4104299063 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.4104299063
Directory /workspace/3.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.2468769367
Short name T192
Test name
Test status
Simulation time 1359630000 ps
CPU time 4.4 seconds
Started Aug 15 04:23:21 PM PDT 24
Finished Aug 15 04:23:31 PM PDT 24
Peak memory 166040 kb
Host smart-6d24f627-514d-44d7-b5e3-c8254357d160
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2468769367 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.2468769367
Directory /workspace/30.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.844542522
Short name T186
Test name
Test status
Simulation time 1251270000 ps
CPU time 3.65 seconds
Started Aug 15 04:23:19 PM PDT 24
Finished Aug 15 04:23:27 PM PDT 24
Peak memory 164708 kb
Host smart-9fd458e4-73e3-41d0-bc9d-7feaa6087803
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=844542522 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.844542522
Directory /workspace/31.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.1368193872
Short name T163
Test name
Test status
Simulation time 1437530000 ps
CPU time 3.22 seconds
Started Aug 15 04:22:54 PM PDT 24
Finished Aug 15 04:23:02 PM PDT 24
Peak memory 163256 kb
Host smart-55a3a558-1e53-401b-8b88-076a96d860bb
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1368193872 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.1368193872
Directory /workspace/32.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.2511065808
Short name T154
Test name
Test status
Simulation time 1567990000 ps
CPU time 5.24 seconds
Started Aug 15 04:20:30 PM PDT 24
Finished Aug 15 04:20:42 PM PDT 24
Peak memory 164716 kb
Host smart-13ee4b80-5311-4ca2-92a1-35485c18d9dc
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2511065808 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.2511065808
Directory /workspace/33.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.1089577087
Short name T179
Test name
Test status
Simulation time 1603250000 ps
CPU time 5.22 seconds
Started Aug 15 04:23:20 PM PDT 24
Finished Aug 15 04:23:32 PM PDT 24
Peak memory 165776 kb
Host smart-65614392-404b-4d49-86b6-7cf1fd8b612a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1089577087 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.1089577087
Directory /workspace/34.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.1195187848
Short name T160
Test name
Test status
Simulation time 1375750000 ps
CPU time 3.5 seconds
Started Aug 15 04:24:24 PM PDT 24
Finished Aug 15 04:24:32 PM PDT 24
Peak memory 164704 kb
Host smart-6af1a6e3-026d-4bf3-b36f-deb5a3fce6cf
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1195187848 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.1195187848
Directory /workspace/35.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.427789501
Short name T159
Test name
Test status
Simulation time 1476790000 ps
CPU time 4.05 seconds
Started Aug 15 04:23:14 PM PDT 24
Finished Aug 15 04:23:24 PM PDT 24
Peak memory 164732 kb
Host smart-3617a5ba-e356-4f06-9a86-e35fd2587cf5
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=427789501 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.427789501
Directory /workspace/36.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1345078062
Short name T169
Test name
Test status
Simulation time 1412850000 ps
CPU time 4.29 seconds
Started Aug 15 04:23:18 PM PDT 24
Finished Aug 15 04:23:27 PM PDT 24
Peak memory 164712 kb
Host smart-7f8c40fd-d8e4-44e9-9490-5df64e7d955b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1345078062 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.1345078062
Directory /workspace/37.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.871757953
Short name T182
Test name
Test status
Simulation time 1257650000 ps
CPU time 3.56 seconds
Started Aug 15 04:21:54 PM PDT 24
Finished Aug 15 04:22:03 PM PDT 24
Peak memory 164720 kb
Host smart-3cae4fc4-d998-462e-8ed2-4effc1cc2b26
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=871757953 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.871757953
Directory /workspace/38.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.133699886
Short name T181
Test name
Test status
Simulation time 1437990000 ps
CPU time 3.73 seconds
Started Aug 15 04:23:50 PM PDT 24
Finished Aug 15 04:23:59 PM PDT 24
Peak memory 164732 kb
Host smart-262d28b8-534d-4fc0-aaac-046f9708e749
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=133699886 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.133699886
Directory /workspace/39.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.4051469219
Short name T194
Test name
Test status
Simulation time 1231530000 ps
CPU time 2.88 seconds
Started Aug 15 04:24:00 PM PDT 24
Finished Aug 15 04:24:06 PM PDT 24
Peak memory 164728 kb
Host smart-0d242fc7-af00-406d-8134-27cccfa30489
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4051469219 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.4051469219
Directory /workspace/4.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.1973791396
Short name T174
Test name
Test status
Simulation time 1313330000 ps
CPU time 2.74 seconds
Started Aug 15 04:23:15 PM PDT 24
Finished Aug 15 04:23:21 PM PDT 24
Peak memory 164320 kb
Host smart-8058c406-700f-4487-9139-f5388aa53871
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1973791396 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.1973791396
Directory /workspace/40.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.1401165188
Short name T183
Test name
Test status
Simulation time 1427370000 ps
CPU time 4.77 seconds
Started Aug 15 04:20:25 PM PDT 24
Finished Aug 15 04:20:35 PM PDT 24
Peak memory 164740 kb
Host smart-279a90e3-4ebc-4edd-ab67-36fe7eeaecda
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1401165188 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.1401165188
Directory /workspace/41.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.1739185884
Short name T195
Test name
Test status
Simulation time 1486990000 ps
CPU time 3.29 seconds
Started Aug 15 04:23:31 PM PDT 24
Finished Aug 15 04:23:38 PM PDT 24
Peak memory 164400 kb
Host smart-ead69349-1950-422a-b862-260216d11872
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1739185884 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.1739185884
Directory /workspace/42.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.3249324993
Short name T190
Test name
Test status
Simulation time 1423810000 ps
CPU time 3.03 seconds
Started Aug 15 04:23:34 PM PDT 24
Finished Aug 15 04:23:41 PM PDT 24
Peak memory 164692 kb
Host smart-fa7e1398-7d60-455e-8b83-e4c47fefc34f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3249324993 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.3249324993
Directory /workspace/43.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.3880367079
Short name T197
Test name
Test status
Simulation time 1561690000 ps
CPU time 3.83 seconds
Started Aug 15 04:23:19 PM PDT 24
Finished Aug 15 04:23:28 PM PDT 24
Peak memory 164408 kb
Host smart-bdd4346e-8d2e-4290-8e25-1f64c4c90822
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3880367079 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.3880367079
Directory /workspace/44.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.1650400193
Short name T161
Test name
Test status
Simulation time 1357510000 ps
CPU time 3.76 seconds
Started Aug 15 04:23:18 PM PDT 24
Finished Aug 15 04:23:27 PM PDT 24
Peak memory 163052 kb
Host smart-22e126cb-9528-4c82-990c-7081a74d63ac
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1650400193 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.1650400193
Directory /workspace/45.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.2382747223
Short name T178
Test name
Test status
Simulation time 1347890000 ps
CPU time 3.71 seconds
Started Aug 15 04:23:18 PM PDT 24
Finished Aug 15 04:23:27 PM PDT 24
Peak memory 163168 kb
Host smart-0dd046ad-d8ec-435e-92a3-bcf7eaf9b018
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2382747223 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.2382747223
Directory /workspace/46.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.815137968
Short name T200
Test name
Test status
Simulation time 1407270000 ps
CPU time 4.95 seconds
Started Aug 15 04:21:12 PM PDT 24
Finished Aug 15 04:21:23 PM PDT 24
Peak memory 166284 kb
Host smart-8c9c7513-49b8-42a6-b7b1-6a679086c79f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=815137968 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.815137968
Directory /workspace/47.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.294888487
Short name T187
Test name
Test status
Simulation time 1240010000 ps
CPU time 3.1 seconds
Started Aug 15 04:23:19 PM PDT 24
Finished Aug 15 04:23:27 PM PDT 24
Peak memory 165968 kb
Host smart-3093944b-6579-4b30-a701-c0bf4c33eb46
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=294888487 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.294888487
Directory /workspace/48.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.1116058342
Short name T158
Test name
Test status
Simulation time 1173110000 ps
CPU time 3.99 seconds
Started Aug 15 04:22:59 PM PDT 24
Finished Aug 15 04:23:08 PM PDT 24
Peak memory 163716 kb
Host smart-7a1fad2a-66d2-4494-b02a-0f82aaae998f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1116058342 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.1116058342
Directory /workspace/49.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.2600944252
Short name T167
Test name
Test status
Simulation time 1523990000 ps
CPU time 3.9 seconds
Started Aug 15 04:24:04 PM PDT 24
Finished Aug 15 04:24:13 PM PDT 24
Peak memory 166244 kb
Host smart-87ffde2e-e19d-4ba1-b723-d1a9369e7635
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2600944252 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.2600944252
Directory /workspace/5.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.143023124
Short name T172
Test name
Test status
Simulation time 1535650000 ps
CPU time 3.79 seconds
Started Aug 15 04:24:04 PM PDT 24
Finished Aug 15 04:24:13 PM PDT 24
Peak memory 164724 kb
Host smart-9108addc-e416-4d7f-8fa1-ad35c4364703
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=143023124 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.143023124
Directory /workspace/6.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.3292232454
Short name T175
Test name
Test status
Simulation time 1189750000 ps
CPU time 2.88 seconds
Started Aug 15 04:24:04 PM PDT 24
Finished Aug 15 04:24:11 PM PDT 24
Peak memory 164640 kb
Host smart-6f2198de-d80b-47b1-94c2-8a23fc561d88
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3292232454 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.3292232454
Directory /workspace/7.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1423523050
Short name T153
Test name
Test status
Simulation time 1502530000 ps
CPU time 3.56 seconds
Started Aug 15 04:24:04 PM PDT 24
Finished Aug 15 04:24:13 PM PDT 24
Peak memory 164728 kb
Host smart-2c99931f-adbe-4af2-a8bd-fb62327bee0e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1423523050 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.1423523050
Directory /workspace/8.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2161084517
Short name T170
Test name
Test status
Simulation time 1393890000 ps
CPU time 4.34 seconds
Started Aug 15 04:20:48 PM PDT 24
Finished Aug 15 04:20:57 PM PDT 24
Peak memory 164396 kb
Host smart-2e9cc653-9a6f-4ea7-b5c4-698c6eed2c61
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2161084517 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.2161084517
Directory /workspace/9.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.3292860650
Short name T55
Test name
Test status
Simulation time 1422810000 ps
CPU time 3.74 seconds
Started Aug 15 04:18:41 PM PDT 24
Finished Aug 15 04:18:49 PM PDT 24
Peak memory 164520 kb
Host smart-a9fd1f77-896c-4ab5-8ef0-c7bb8f2be495
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3292860650 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.3292860650
Directory /workspace/1.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.1181566024
Short name T59
Test name
Test status
Simulation time 1321150000 ps
CPU time 3.5 seconds
Started Aug 15 04:19:05 PM PDT 24
Finished Aug 15 04:19:13 PM PDT 24
Peak memory 164772 kb
Host smart-efa4b6fb-566a-4437-bf66-55a7e544cb93
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1181566024 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.1181566024
Directory /workspace/10.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.1440377398
Short name T2
Test name
Test status
Simulation time 1510970000 ps
CPU time 4.49 seconds
Started Aug 15 04:20:17 PM PDT 24
Finished Aug 15 04:20:28 PM PDT 24
Peak memory 164684 kb
Host smart-aa1f3e31-b1fd-475e-acbe-9216303e4aa2
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1440377398 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.1440377398
Directory /workspace/11.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.516764834
Short name T52
Test name
Test status
Simulation time 1589810000 ps
CPU time 5.62 seconds
Started Aug 15 04:19:58 PM PDT 24
Finished Aug 15 04:20:11 PM PDT 24
Peak memory 164748 kb
Host smart-0954582e-effc-45ca-ac90-ab580d8fee25
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=516764834 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.516764834
Directory /workspace/12.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.931671083
Short name T33
Test name
Test status
Simulation time 1360010000 ps
CPU time 4.94 seconds
Started Aug 15 04:19:58 PM PDT 24
Finished Aug 15 04:20:09 PM PDT 24
Peak memory 164732 kb
Host smart-8ba004bc-700b-4d30-b1e5-1289956980a8
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=931671083 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.931671083
Directory /workspace/13.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.2401647951
Short name T35
Test name
Test status
Simulation time 1559310000 ps
CPU time 4.59 seconds
Started Aug 15 04:23:23 PM PDT 24
Finished Aug 15 04:23:34 PM PDT 24
Peak memory 166104 kb
Host smart-b32c6ba4-fcbb-4438-8501-dbaedd16c2da
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2401647951 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.2401647951
Directory /workspace/14.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.1871451004
Short name T68
Test name
Test status
Simulation time 1397950000 ps
CPU time 3.11 seconds
Started Aug 15 04:21:54 PM PDT 24
Finished Aug 15 04:22:01 PM PDT 24
Peak memory 164784 kb
Host smart-4592044a-2646-41b1-b45a-210a00cd108c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1871451004 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.1871451004
Directory /workspace/15.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.1546041198
Short name T57
Test name
Test status
Simulation time 1527190000 ps
CPU time 4.33 seconds
Started Aug 15 04:24:23 PM PDT 24
Finished Aug 15 04:24:32 PM PDT 24
Peak memory 164704 kb
Host smart-7f3153b2-50cd-4b71-b383-9cf20be9afd1
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1546041198 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.1546041198
Directory /workspace/16.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.1442156000
Short name T13
Test name
Test status
Simulation time 1493170000 ps
CPU time 4.44 seconds
Started Aug 15 04:20:20 PM PDT 24
Finished Aug 15 04:20:30 PM PDT 24
Peak memory 165040 kb
Host smart-3a444c5c-4ccd-48af-b047-09b9b4fe0018
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1442156000 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.1442156000
Directory /workspace/17.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.427043601
Short name T40
Test name
Test status
Simulation time 1558330000 ps
CPU time 4.6 seconds
Started Aug 15 04:23:24 PM PDT 24
Finished Aug 15 04:23:34 PM PDT 24
Peak memory 164576 kb
Host smart-1fca3247-2446-4aa7-b754-9a352199ba6d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=427043601 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.427043601
Directory /workspace/18.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.323946311
Short name T66
Test name
Test status
Simulation time 1540670000 ps
CPU time 4.06 seconds
Started Aug 15 04:19:28 PM PDT 24
Finished Aug 15 04:19:37 PM PDT 24
Peak memory 163192 kb
Host smart-640dafcf-fd39-4c3b-996a-8db6df72a38e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=323946311 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.323946311
Directory /workspace/19.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.2963084747
Short name T43
Test name
Test status
Simulation time 1596010000 ps
CPU time 5.07 seconds
Started Aug 15 04:18:30 PM PDT 24
Finished Aug 15 04:18:41 PM PDT 24
Peak memory 163356 kb
Host smart-3875a24e-d497-4d29-90f7-8c8181a562b7
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2963084747 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.2963084747
Directory /workspace/2.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.1438821397
Short name T70
Test name
Test status
Simulation time 1325970000 ps
CPU time 4.18 seconds
Started Aug 15 04:23:21 PM PDT 24
Finished Aug 15 04:23:31 PM PDT 24
Peak memory 166068 kb
Host smart-7af11771-33e8-4e8b-a6f1-a1ad5a2cfdf3
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1438821397 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.1438821397
Directory /workspace/20.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.2422984800
Short name T53
Test name
Test status
Simulation time 1372730000 ps
CPU time 4.18 seconds
Started Aug 15 04:23:20 PM PDT 24
Finished Aug 15 04:23:29 PM PDT 24
Peak memory 165692 kb
Host smart-c69c686a-561a-4da2-bbe8-98b1d84ca8b7
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2422984800 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.2422984800
Directory /workspace/21.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.4108771780
Short name T8
Test name
Test status
Simulation time 1519870000 ps
CPU time 4.58 seconds
Started Aug 15 04:23:20 PM PDT 24
Finished Aug 15 04:23:30 PM PDT 24
Peak memory 165660 kb
Host smart-4a6e35f8-b868-489b-8f34-dc7f8e0f4c13
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4108771780 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.4108771780
Directory /workspace/22.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.1667525335
Short name T45
Test name
Test status
Simulation time 1445270000 ps
CPU time 3.35 seconds
Started Aug 15 04:20:11 PM PDT 24
Finished Aug 15 04:20:19 PM PDT 24
Peak memory 164716 kb
Host smart-b297bbf8-8546-4f46-b3b1-35f7d001caf8
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1667525335 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.1667525335
Directory /workspace/23.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.1207035912
Short name T34
Test name
Test status
Simulation time 1503950000 ps
CPU time 3.14 seconds
Started Aug 15 04:23:04 PM PDT 24
Finished Aug 15 04:23:11 PM PDT 24
Peak memory 163536 kb
Host smart-c11e6ad4-5e8c-4735-955e-515552961bab
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1207035912 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.1207035912
Directory /workspace/24.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.3996422835
Short name T32
Test name
Test status
Simulation time 1388930000 ps
CPU time 3.62 seconds
Started Aug 15 04:23:59 PM PDT 24
Finished Aug 15 04:24:07 PM PDT 24
Peak memory 166064 kb
Host smart-ebe75bae-fb63-41bf-8b24-bd86b8b93784
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3996422835 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.3996422835
Directory /workspace/25.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.1961653517
Short name T1
Test name
Test status
Simulation time 1605910000 ps
CPU time 3.9 seconds
Started Aug 15 04:24:01 PM PDT 24
Finished Aug 15 04:24:09 PM PDT 24
Peak memory 166064 kb
Host smart-e98a5ab5-2873-4473-9d7d-d57c0a8f64e6
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1961653517 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.1961653517
Directory /workspace/26.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.3976583303
Short name T67
Test name
Test status
Simulation time 1551270000 ps
CPU time 3.58 seconds
Started Aug 15 04:23:22 PM PDT 24
Finished Aug 15 04:23:30 PM PDT 24
Peak memory 164728 kb
Host smart-05ac043c-9065-45a1-90ca-9fdde78f02ed
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3976583303 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.3976583303
Directory /workspace/27.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.570053978
Short name T64
Test name
Test status
Simulation time 1435210000 ps
CPU time 3.41 seconds
Started Aug 15 04:23:22 PM PDT 24
Finished Aug 15 04:23:30 PM PDT 24
Peak memory 164788 kb
Host smart-8315942d-cc9e-4648-830f-93d252839a9b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=570053978 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.570053978
Directory /workspace/28.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.3500001852
Short name T56
Test name
Test status
Simulation time 1492110000 ps
CPU time 4.38 seconds
Started Aug 15 04:23:28 PM PDT 24
Finished Aug 15 04:23:38 PM PDT 24
Peak memory 166268 kb
Host smart-49902438-d009-41a2-a733-f90991874d98
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3500001852 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.3500001852
Directory /workspace/29.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.1682904653
Short name T62
Test name
Test status
Simulation time 1540550000 ps
CPU time 3.27 seconds
Started Aug 15 04:23:28 PM PDT 24
Finished Aug 15 04:23:35 PM PDT 24
Peak memory 164324 kb
Host smart-85311256-0310-4f59-b6bb-2af55339827e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1682904653 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.1682904653
Directory /workspace/3.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.652635160
Short name T10
Test name
Test status
Simulation time 1411690000 ps
CPU time 4.34 seconds
Started Aug 15 04:23:28 PM PDT 24
Finished Aug 15 04:23:38 PM PDT 24
Peak memory 164736 kb
Host smart-e125a04c-a940-4714-8d5d-cfc70f7fcd38
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=652635160 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.652635160
Directory /workspace/30.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.4248121845
Short name T39
Test name
Test status
Simulation time 1507510000 ps
CPU time 4.85 seconds
Started Aug 15 04:23:28 PM PDT 24
Finished Aug 15 04:23:39 PM PDT 24
Peak memory 166304 kb
Host smart-984b1fda-e985-4a67-9bec-22aa91f569a9
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4248121845 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.4248121845
Directory /workspace/31.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.1761797446
Short name T3
Test name
Test status
Simulation time 1561810000 ps
CPU time 5.27 seconds
Started Aug 15 04:23:09 PM PDT 24
Finished Aug 15 04:23:21 PM PDT 24
Peak memory 162608 kb
Host smart-90e8efae-d2a6-4877-afdd-1f58081d405e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1761797446 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.1761797446
Directory /workspace/32.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.3618083740
Short name T63
Test name
Test status
Simulation time 1537590000 ps
CPU time 4.23 seconds
Started Aug 15 04:23:12 PM PDT 24
Finished Aug 15 04:23:22 PM PDT 24
Peak memory 164724 kb
Host smart-c1b7684d-f485-498f-a225-a770cad2a876
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3618083740 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.3618083740
Directory /workspace/33.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.2159589528
Short name T42
Test name
Test status
Simulation time 1478210000 ps
CPU time 4.93 seconds
Started Aug 15 04:23:09 PM PDT 24
Finished Aug 15 04:23:20 PM PDT 24
Peak memory 162520 kb
Host smart-337440f7-e000-4c46-abce-16fbc0fb55d1
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2159589528 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.2159589528
Directory /workspace/34.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.1301294257
Short name T7
Test name
Test status
Simulation time 1444690000 ps
CPU time 4.25 seconds
Started Aug 15 04:23:16 PM PDT 24
Finished Aug 15 04:23:26 PM PDT 24
Peak memory 164344 kb
Host smart-3babaa3c-8cf9-4bcd-ae50-950f3523f245
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1301294257 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.1301294257
Directory /workspace/35.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.1470850560
Short name T37
Test name
Test status
Simulation time 1432290000 ps
CPU time 4.57 seconds
Started Aug 15 04:23:30 PM PDT 24
Finished Aug 15 04:23:40 PM PDT 24
Peak memory 166212 kb
Host smart-bf93e1b2-2e1c-4303-be55-de4731e28ced
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1470850560 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.1470850560
Directory /workspace/36.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.3144785028
Short name T12
Test name
Test status
Simulation time 1515850000 ps
CPU time 4.28 seconds
Started Aug 15 04:23:16 PM PDT 24
Finished Aug 15 04:23:26 PM PDT 24
Peak memory 165376 kb
Host smart-8909dbc4-5645-4cf9-861f-35bfd0c63773
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3144785028 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.3144785028
Directory /workspace/37.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.1305810400
Short name T69
Test name
Test status
Simulation time 1092030000 ps
CPU time 3.6 seconds
Started Aug 15 04:23:16 PM PDT 24
Finished Aug 15 04:23:24 PM PDT 24
Peak memory 164860 kb
Host smart-3728f8b2-3051-460e-9490-11620e88223c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1305810400 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.1305810400
Directory /workspace/38.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.4025155136
Short name T60
Test name
Test status
Simulation time 1595390000 ps
CPU time 5.45 seconds
Started Aug 15 04:24:21 PM PDT 24
Finished Aug 15 04:24:33 PM PDT 24
Peak memory 166208 kb
Host smart-2c09956d-74ae-4d34-9fe9-f29be21a065c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4025155136 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.4025155136
Directory /workspace/39.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.1215970698
Short name T61
Test name
Test status
Simulation time 1318490000 ps
CPU time 4.09 seconds
Started Aug 15 04:23:29 PM PDT 24
Finished Aug 15 04:23:38 PM PDT 24
Peak memory 164668 kb
Host smart-7b2d955f-dbcc-4af7-b037-11fd1937b12f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1215970698 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.1215970698
Directory /workspace/4.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.702034292
Short name T47
Test name
Test status
Simulation time 1563670000 ps
CPU time 4.01 seconds
Started Aug 15 04:23:09 PM PDT 24
Finished Aug 15 04:23:19 PM PDT 24
Peak memory 165080 kb
Host smart-81311217-8c5c-4eb4-b139-64d26fb61784
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=702034292 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.702034292
Directory /workspace/40.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.1962506519
Short name T46
Test name
Test status
Simulation time 1513510000 ps
CPU time 4.71 seconds
Started Aug 15 04:18:41 PM PDT 24
Finished Aug 15 04:18:52 PM PDT 24
Peak memory 164532 kb
Host smart-b8e9e18a-f5ec-494e-a2bc-eea7dd663e85
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1962506519 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.1962506519
Directory /workspace/41.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.4032468580
Short name T11
Test name
Test status
Simulation time 1383470000 ps
CPU time 3.57 seconds
Started Aug 15 04:21:09 PM PDT 24
Finished Aug 15 04:21:17 PM PDT 24
Peak memory 164724 kb
Host smart-6ee1cb78-1083-47a1-b1bc-360e51327a18
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4032468580 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.4032468580
Directory /workspace/42.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.639020570
Short name T36
Test name
Test status
Simulation time 1392930000 ps
CPU time 3.9 seconds
Started Aug 15 04:23:38 PM PDT 24
Finished Aug 15 04:23:46 PM PDT 24
Peak memory 164708 kb
Host smart-c15ac358-14e7-453c-a55f-8c4e51840783
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=639020570 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.639020570
Directory /workspace/43.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.555433506
Short name T41
Test name
Test status
Simulation time 1195550000 ps
CPU time 3.4 seconds
Started Aug 15 04:23:37 PM PDT 24
Finished Aug 15 04:23:45 PM PDT 24
Peak memory 164708 kb
Host smart-aa371c7a-feea-4fe1-894a-786f58c63319
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=555433506 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.555433506
Directory /workspace/44.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.296504853
Short name T48
Test name
Test status
Simulation time 1573890000 ps
CPU time 4.74 seconds
Started Aug 15 04:19:02 PM PDT 24
Finished Aug 15 04:19:12 PM PDT 24
Peak memory 164700 kb
Host smart-54a8e134-f09a-40f6-89b6-aaf1221b0812
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=296504853 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.296504853
Directory /workspace/45.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.820234611
Short name T31
Test name
Test status
Simulation time 1202830000 ps
CPU time 2.46 seconds
Started Aug 15 04:23:22 PM PDT 24
Finished Aug 15 04:23:27 PM PDT 24
Peak memory 163660 kb
Host smart-61f5a76d-43c4-43be-82be-2dc4f82ab900
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=820234611 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.820234611
Directory /workspace/46.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.3288432503
Short name T54
Test name
Test status
Simulation time 1406090000 ps
CPU time 3.84 seconds
Started Aug 15 04:21:09 PM PDT 24
Finished Aug 15 04:21:17 PM PDT 24
Peak memory 164724 kb
Host smart-3b2681ad-b4f6-48ae-b240-1ebd0cddff65
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3288432503 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.3288432503
Directory /workspace/47.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.4095081328
Short name T44
Test name
Test status
Simulation time 1319730000 ps
CPU time 4.51 seconds
Started Aug 15 04:19:46 PM PDT 24
Finished Aug 15 04:19:56 PM PDT 24
Peak memory 164724 kb
Host smart-bdfe8a63-679f-4104-b942-d8114f890b4b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4095081328 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.4095081328
Directory /workspace/48.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.2358282883
Short name T38
Test name
Test status
Simulation time 1527490000 ps
CPU time 7.22 seconds
Started Aug 15 04:18:36 PM PDT 24
Finished Aug 15 04:18:51 PM PDT 24
Peak memory 163648 kb
Host smart-cc24c642-fdca-4d15-b0b1-a3418d0ac1ce
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2358282883 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.2358282883
Directory /workspace/49.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.1527644901
Short name T58
Test name
Test status
Simulation time 1225470000 ps
CPU time 3.88 seconds
Started Aug 15 04:23:32 PM PDT 24
Finished Aug 15 04:23:41 PM PDT 24
Peak memory 164472 kb
Host smart-9bbe5be3-7ce8-439d-88ce-eeb2a32f193a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1527644901 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.1527644901
Directory /workspace/5.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.1478939646
Short name T51
Test name
Test status
Simulation time 1549210000 ps
CPU time 3.96 seconds
Started Aug 15 04:23:14 PM PDT 24
Finished Aug 15 04:23:23 PM PDT 24
Peak memory 163316 kb
Host smart-882b33eb-0f41-49a1-93ab-99ddbed6cb1f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1478939646 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.1478939646
Directory /workspace/6.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.3376289840
Short name T50
Test name
Test status
Simulation time 1335270000 ps
CPU time 4.38 seconds
Started Aug 15 04:23:29 PM PDT 24
Finished Aug 15 04:23:38 PM PDT 24
Peak memory 164668 kb
Host smart-13debff9-3dc3-4d6a-aa60-558d07902197
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3376289840 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.3376289840
Directory /workspace/7.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.3946351967
Short name T65
Test name
Test status
Simulation time 1341970000 ps
CPU time 3.87 seconds
Started Aug 15 04:23:00 PM PDT 24
Finished Aug 15 04:23:09 PM PDT 24
Peak memory 162848 kb
Host smart-7bc71dfc-8dbd-4cb5-a453-f62a6706a7f1
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3946351967 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.3946351967
Directory /workspace/8.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.2507058034
Short name T49
Test name
Test status
Simulation time 1523150000 ps
CPU time 3.9 seconds
Started Aug 15 04:23:22 PM PDT 24
Finished Aug 15 04:23:31 PM PDT 24
Peak memory 165836 kb
Host smart-9c29ac97-4c13-4306-bfd3-98bb01ecae41
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2507058034 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.2507058034
Directory /workspace/9.prim_lfsr_gal_smoke/latest
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