Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.31 100.00 96.55 100.00 100.00 95.00


Total tests in report: 200
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
87.31 87.31 100.00 100.00 96.55 96.55 100.00 100.00 100.00 100.00 40.00 40.00 /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.3125645457
95.31 8.00 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 80.00 40.00 /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.2729383599
98.31 3.00 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 95.00 15.00 /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.529469665

Tests that do not contribute to grading

Name
/workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.14550614
/workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.612462390
/workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.1449173436
/workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.726505168
/workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.4116857422
/workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.1273894576
/workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.3174610438
/workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.2830636964
/workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.2933773568
/workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.1283640345
/workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.3509214640
/workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.2024827600
/workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.3394585166
/workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.869731109
/workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.2918134907
/workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.1197579547
/workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.824271601
/workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.835033368
/workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.3199265800
/workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.3787347292
/workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.12481280
/workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.100503285
/workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.1593480678
/workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.1809968161
/workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.834915762
/workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.1139915249
/workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.1825140770
/workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.1997705793
/workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.3986346705
/workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.3764595168
/workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.2926978008
/workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.501568678
/workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.3995791123
/workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.1304689081
/workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.1429541139
/workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.328547111
/workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.3280716200
/workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.3922451707
/workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.2697150551
/workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.4205474831
/workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.415515108
/workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.677626414
/workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.2970987861
/workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.757936509
/workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.1699472444
/workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.2806893428
/workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.806941940
/workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1471823806
/workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.1299921960
/workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.1703704989
/workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.2375244498
/workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.2865688470
/workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.377296559
/workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.2178163033
/workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.1524618968
/workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.3236457261
/workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.3248852607
/workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.2939883164
/workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.1356381271
/workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.1303857018
/workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.2501133518
/workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.158785966
/workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.270263353
/workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.2053950722
/workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.1662218004
/workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.3509208810
/workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.2540490651
/workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.1145787290
/workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.2330245501
/workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.1168582662
/workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.1778819038
/workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.1865171801
/workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.1054881257
/workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.193823241
/workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.3985729525
/workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.3945092496
/workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.1948943119
/workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.2508923274
/workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.3080967846
/workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.3736453457
/workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.2460578267
/workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.3391688892
/workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.1562361260
/workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.459600574
/workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.451274827
/workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.2320638676
/workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.815718216
/workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.604706561
/workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.3287205734
/workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.1082017759
/workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.2688475372
/workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1283119063
/workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.2904371429
/workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.450602747
/workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.2243940028
/workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.690096885
/workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.1269277014
/workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.2306022014
/workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.650568822
/workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.2782215166
/workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.1722093716
/workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.631680290
/workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.1385744662
/workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.2118079742
/workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.4094696998
/workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.1148567076
/workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.3200983833
/workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.619272923
/workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.1078598500
/workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.1589688064
/workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.1911763612
/workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.468848120
/workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.2274891774
/workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.3251280772
/workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.4047043060
/workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.844682763
/workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.1007209989
/workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.3639689396
/workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.2592951750
/workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.2155053385
/workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.1477305067
/workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.3017569220
/workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.3344555407
/workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.2352779194
/workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.4215727453
/workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.986797756
/workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.3694828028
/workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.769644989
/workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.1031089451
/workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1054147989
/workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.2473434871
/workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.1215485468
/workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.2711140743
/workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.2238030635
/workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.1700774201
/workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.2409770879
/workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.3820462002
/workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.3259943882
/workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.1834698852
/workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.4033411868
/workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.2990970308
/workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.1317791801
/workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.3285239206
/workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.3320766675
/workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.566329079
/workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.796220056
/workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.851898485
/workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.3768237772
/workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.2908135897
/workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.2297705437
/workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.517151015
/workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.3391410930
/workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.3884819824
/workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.1198655614
/workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.238340957
/workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.1359056212
/workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.1069050303
/workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.4240409606
/workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.1156242059
/workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.1210493990
/workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.2299109491
/workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.977449731
/workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.1358060773
/workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.3017874223
/workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.338656560
/workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.3259763273
/workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.2601133424
/workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.2267165203
/workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.604363327
/workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.3990062695
/workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.2911129797
/workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.3033058211
/workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.1007804734
/workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.1147478783
/workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.3954866534
/workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.664647
/workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.123383310
/workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.3125854019
/workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.3849630345
/workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.2990885388
/workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.1542179828
/workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.3227743529
/workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.2037149824
/workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.378493611
/workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.2305113811
/workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.1616416781
/workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.738384560
/workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.2259253549
/workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.3407567427
/workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.4264834543
/workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.1462200286
/workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.3963437227
/workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.3890094518
/workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.3635889467
/workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.814519030
/workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.1463721081
/workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.3493266779



Total test records in report: 200
tests.html | tests1.html | tests2.html | tests3.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.1463721081 Aug 16 04:19:35 PM PDT 24 Aug 16 04:19:44 PM PDT 24 1410870000 ps
T2 /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.2267165203 Aug 16 04:22:54 PM PDT 24 Aug 16 04:23:03 PM PDT 24 1597670000 ps
T3 /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.2259253549 Aug 16 04:24:44 PM PDT 24 Aug 16 04:24:54 PM PDT 24 1534970000 ps
T4 /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.1462200286 Aug 16 04:24:41 PM PDT 24 Aug 16 04:24:55 PM PDT 24 1497950000 ps
T8 /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.2037149824 Aug 16 04:24:40 PM PDT 24 Aug 16 04:24:49 PM PDT 24 1560970000 ps
T9 /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.977449731 Aug 16 04:22:54 PM PDT 24 Aug 16 04:23:04 PM PDT 24 1560350000 ps
T10 /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.3125645457 Aug 16 04:24:17 PM PDT 24 Aug 16 04:24:25 PM PDT 24 1385370000 ps
T11 /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.3033058211 Aug 16 04:24:33 PM PDT 24 Aug 16 04:24:42 PM PDT 24 1297610000 ps
T12 /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.123383310 Aug 16 04:24:31 PM PDT 24 Aug 16 04:24:40 PM PDT 24 1530470000 ps
T13 /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.604363327 Aug 16 04:22:20 PM PDT 24 Aug 16 04:22:32 PM PDT 24 1476870000 ps
T31 /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.1616416781 Aug 16 04:24:42 PM PDT 24 Aug 16 04:24:52 PM PDT 24 1587910000 ps
T32 /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.3990062695 Aug 16 04:23:57 PM PDT 24 Aug 16 04:24:04 PM PDT 24 1376250000 ps
T33 /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.2297705437 Aug 16 04:19:47 PM PDT 24 Aug 16 04:20:00 PM PDT 24 1485690000 ps
T34 /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.1069050303 Aug 16 04:22:54 PM PDT 24 Aug 16 04:23:03 PM PDT 24 1439530000 ps
T35 /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.2911129797 Aug 16 04:19:48 PM PDT 24 Aug 16 04:19:57 PM PDT 24 1266130000 ps
T36 /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.3884819824 Aug 16 04:20:34 PM PDT 24 Aug 16 04:20:45 PM PDT 24 1488490000 ps
T37 /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.4240409606 Aug 16 04:23:49 PM PDT 24 Aug 16 04:23:56 PM PDT 24 1384530000 ps
T38 /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.3963437227 Aug 16 04:24:41 PM PDT 24 Aug 16 04:24:52 PM PDT 24 1541350000 ps
T39 /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.1007804734 Aug 16 04:24:32 PM PDT 24 Aug 16 04:24:40 PM PDT 24 1334930000 ps
T40 /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.1210493990 Aug 16 04:19:35 PM PDT 24 Aug 16 04:19:44 PM PDT 24 1358850000 ps
T41 /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.814519030 Aug 16 04:19:28 PM PDT 24 Aug 16 04:19:38 PM PDT 24 1512690000 ps
T42 /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.3635889467 Aug 16 04:19:47 PM PDT 24 Aug 16 04:20:00 PM PDT 24 1517210000 ps
T43 /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.1358060773 Aug 16 04:23:12 PM PDT 24 Aug 16 04:23:22 PM PDT 24 1570150000 ps
T44 /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.2299109491 Aug 16 04:21:12 PM PDT 24 Aug 16 04:21:23 PM PDT 24 1411350000 ps
T45 /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.2990885388 Aug 16 04:24:40 PM PDT 24 Aug 16 04:24:51 PM PDT 24 1542470000 ps
T46 /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.2305113811 Aug 16 04:24:42 PM PDT 24 Aug 16 04:24:51 PM PDT 24 1476050000 ps
T47 /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.3954866534 Aug 16 04:24:42 PM PDT 24 Aug 16 04:24:53 PM PDT 24 1454650000 ps
T48 /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.338656560 Aug 16 04:21:56 PM PDT 24 Aug 16 04:22:07 PM PDT 24 1374150000 ps
T49 /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.1198655614 Aug 16 04:20:50 PM PDT 24 Aug 16 04:21:00 PM PDT 24 1346210000 ps
T50 /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.378493611 Aug 16 04:24:40 PM PDT 24 Aug 16 04:24:47 PM PDT 24 1141470000 ps
T51 /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.517151015 Aug 16 04:19:42 PM PDT 24 Aug 16 04:19:51 PM PDT 24 1288650000 ps
T52 /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.3125854019 Aug 16 04:24:35 PM PDT 24 Aug 16 04:24:45 PM PDT 24 1407310000 ps
T53 /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.3391410930 Aug 16 04:20:13 PM PDT 24 Aug 16 04:20:24 PM PDT 24 1516210000 ps
T54 /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.1542179828 Aug 16 04:24:44 PM PDT 24 Aug 16 04:24:54 PM PDT 24 1434030000 ps
T55 /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.3017874223 Aug 16 04:22:26 PM PDT 24 Aug 16 04:22:34 PM PDT 24 1350990000 ps
T56 /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.3890094518 Aug 16 04:19:25 PM PDT 24 Aug 16 04:19:35 PM PDT 24 1534270000 ps
T57 /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.1147478783 Aug 16 04:24:31 PM PDT 24 Aug 16 04:24:44 PM PDT 24 1454110000 ps
T58 /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.3227743529 Aug 16 04:18:30 PM PDT 24 Aug 16 04:18:40 PM PDT 24 1389030000 ps
T59 /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.2908135897 Aug 16 04:20:34 PM PDT 24 Aug 16 04:20:44 PM PDT 24 1330210000 ps
T60 /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.2601133424 Aug 16 04:21:44 PM PDT 24 Aug 16 04:21:52 PM PDT 24 1350630000 ps
T61 /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.664647 Aug 16 04:24:42 PM PDT 24 Aug 16 04:24:54 PM PDT 24 1638650000 ps
T62 /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.238340957 Aug 16 04:19:43 PM PDT 24 Aug 16 04:19:53 PM PDT 24 1570870000 ps
T63 /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.4264834543 Aug 16 04:24:44 PM PDT 24 Aug 16 04:24:54 PM PDT 24 1549690000 ps
T64 /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.3407567427 Aug 16 04:24:42 PM PDT 24 Aug 16 04:24:54 PM PDT 24 1585170000 ps
T65 /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.3849630345 Aug 16 04:24:40 PM PDT 24 Aug 16 04:24:49 PM PDT 24 1451750000 ps
T66 /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.3493266779 Aug 16 04:18:58 PM PDT 24 Aug 16 04:19:09 PM PDT 24 1483630000 ps
T67 /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.3259763273 Aug 16 04:22:08 PM PDT 24 Aug 16 04:22:19 PM PDT 24 1337970000 ps
T68 /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.1156242059 Aug 16 04:20:55 PM PDT 24 Aug 16 04:21:04 PM PDT 24 1296590000 ps
T69 /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.738384560 Aug 16 04:24:41 PM PDT 24 Aug 16 04:24:52 PM PDT 24 1424430000 ps
T70 /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.1359056212 Aug 16 04:20:51 PM PDT 24 Aug 16 04:21:02 PM PDT 24 1456350000 ps
T14 /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.1948943119 Aug 16 04:19:35 PM PDT 24 Aug 16 04:49:18 PM PDT 24 336760350000 ps
T15 /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.3236457261 Aug 16 04:21:10 PM PDT 24 Aug 16 04:58:11 PM PDT 24 337103650000 ps
T16 /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.815718216 Aug 16 04:21:45 PM PDT 24 Aug 16 04:52:15 PM PDT 24 336522110000 ps
T17 /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.2053950722 Aug 16 04:24:24 PM PDT 24 Aug 16 04:53:30 PM PDT 24 337030570000 ps
T18 /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.270263353 Aug 16 04:23:35 PM PDT 24 Aug 16 04:55:12 PM PDT 24 336608490000 ps
T19 /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.1145787290 Aug 16 04:23:01 PM PDT 24 Aug 16 04:53:31 PM PDT 24 336933990000 ps
T20 /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.2729383599 Aug 16 04:20:34 PM PDT 24 Aug 16 05:01:46 PM PDT 24 337010630000 ps
T21 /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.2306022014 Aug 16 04:19:55 PM PDT 24 Aug 16 04:55:35 PM PDT 24 337095870000 ps
T22 /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.3985729525 Aug 16 04:23:21 PM PDT 24 Aug 16 04:51:45 PM PDT 24 336836610000 ps
T23 /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1283119063 Aug 16 04:24:42 PM PDT 24 Aug 16 05:00:57 PM PDT 24 336587570000 ps
T71 /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.2320638676 Aug 16 04:19:47 PM PDT 24 Aug 16 04:57:35 PM PDT 24 336622930000 ps
T72 /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.690096885 Aug 16 04:22:55 PM PDT 24 Aug 16 04:49:35 PM PDT 24 336332410000 ps
T73 /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.1524618968 Aug 16 04:21:24 PM PDT 24 Aug 16 04:49:18 PM PDT 24 336443870000 ps
T74 /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.1356381271 Aug 16 04:24:59 PM PDT 24 Aug 16 04:54:47 PM PDT 24 336605610000 ps
T75 /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.2375244498 Aug 16 04:23:04 PM PDT 24 Aug 16 04:56:57 PM PDT 24 336953770000 ps
T76 /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.2904371429 Aug 16 04:24:42 PM PDT 24 Aug 16 05:00:13 PM PDT 24 336531730000 ps
T77 /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.3080967846 Aug 16 04:19:37 PM PDT 24 Aug 16 04:52:47 PM PDT 24 336569830000 ps
T78 /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.2508923274 Aug 16 04:19:28 PM PDT 24 Aug 16 04:54:24 PM PDT 24 336759090000 ps
T79 /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.2501133518 Aug 16 04:22:32 PM PDT 24 Aug 16 04:55:44 PM PDT 24 336935450000 ps
T80 /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.604706561 Aug 16 04:24:32 PM PDT 24 Aug 16 05:05:44 PM PDT 24 336927570000 ps
T81 /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.2330245501 Aug 16 04:19:40 PM PDT 24 Aug 16 04:50:35 PM PDT 24 336743670000 ps
T82 /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.2540490651 Aug 16 04:23:03 PM PDT 24 Aug 16 04:58:18 PM PDT 24 336405050000 ps
T83 /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.377296559 Aug 16 04:25:00 PM PDT 24 Aug 16 04:55:49 PM PDT 24 336873250000 ps
T84 /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.3248852607 Aug 16 04:23:35 PM PDT 24 Aug 16 04:52:22 PM PDT 24 336582590000 ps
T85 /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.451274827 Aug 16 04:24:34 PM PDT 24 Aug 16 04:57:03 PM PDT 24 336981210000 ps
T86 /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.1778819038 Aug 16 04:23:16 PM PDT 24 Aug 16 04:55:47 PM PDT 24 336788150000 ps
T87 /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.2939883164 Aug 16 04:23:36 PM PDT 24 Aug 16 04:56:09 PM PDT 24 336402590000 ps
T88 /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.193823241 Aug 16 04:23:16 PM PDT 24 Aug 16 04:55:21 PM PDT 24 336735530000 ps
T89 /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.3391688892 Aug 16 04:19:38 PM PDT 24 Aug 16 04:54:18 PM PDT 24 336301370000 ps
T90 /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.459600574 Aug 16 04:18:30 PM PDT 24 Aug 16 05:01:10 PM PDT 24 336317850000 ps
T91 /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.3736453457 Aug 16 04:18:31 PM PDT 24 Aug 16 05:01:07 PM PDT 24 336479070000 ps
T92 /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.2243940028 Aug 16 04:20:20 PM PDT 24 Aug 16 04:52:54 PM PDT 24 337048710000 ps
T93 /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.1703704989 Aug 16 04:23:59 PM PDT 24 Aug 16 04:51:18 PM PDT 24 336815390000 ps
T94 /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.1662218004 Aug 16 04:19:04 PM PDT 24 Aug 16 04:57:30 PM PDT 24 336984650000 ps
T95 /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.158785966 Aug 16 04:19:19 PM PDT 24 Aug 16 04:51:35 PM PDT 24 336945630000 ps
T96 /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.1082017759 Aug 16 04:24:34 PM PDT 24 Aug 16 04:50:52 PM PDT 24 336310150000 ps
T97 /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.2688475372 Aug 16 04:24:32 PM PDT 24 Aug 16 04:56:38 PM PDT 24 336631030000 ps
T98 /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.2865688470 Aug 16 04:22:51 PM PDT 24 Aug 16 05:04:46 PM PDT 24 336790810000 ps
T99 /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.3287205734 Aug 16 04:24:31 PM PDT 24 Aug 16 04:59:31 PM PDT 24 336945590000 ps
T100 /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.1562361260 Aug 16 04:22:07 PM PDT 24 Aug 16 04:49:42 PM PDT 24 336551790000 ps
T101 /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.1054881257 Aug 16 04:23:01 PM PDT 24 Aug 16 04:53:34 PM PDT 24 336450670000 ps
T102 /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.1168582662 Aug 16 04:19:59 PM PDT 24 Aug 16 04:54:43 PM PDT 24 336617670000 ps
T103 /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.3509208810 Aug 16 04:19:54 PM PDT 24 Aug 16 04:55:48 PM PDT 24 336774230000 ps
T104 /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.2460578267 Aug 16 04:19:28 PM PDT 24 Aug 16 04:45:50 PM PDT 24 336395630000 ps
T105 /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.1269277014 Aug 16 04:22:54 PM PDT 24 Aug 16 04:54:26 PM PDT 24 336517850000 ps
T106 /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.1303857018 Aug 16 04:24:15 PM PDT 24 Aug 16 04:52:08 PM PDT 24 336654310000 ps
T107 /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.1865171801 Aug 16 04:21:36 PM PDT 24 Aug 16 04:54:58 PM PDT 24 336413910000 ps
T108 /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.2178163033 Aug 16 04:19:53 PM PDT 24 Aug 16 05:00:24 PM PDT 24 337024550000 ps
T109 /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.3945092496 Aug 16 04:23:52 PM PDT 24 Aug 16 04:54:01 PM PDT 24 336892630000 ps
T110 /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.450602747 Aug 16 04:21:03 PM PDT 24 Aug 16 04:51:47 PM PDT 24 336832070000 ps
T5 /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.677626414 Aug 16 04:24:31 PM PDT 24 Aug 16 04:59:24 PM PDT 24 336894390000 ps
T6 /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1471823806 Aug 16 04:20:18 PM PDT 24 Aug 16 04:56:28 PM PDT 24 337027650000 ps
T7 /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.3995791123 Aug 16 04:23:33 PM PDT 24 Aug 16 04:48:51 PM PDT 24 336858730000 ps
T24 /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.835033368 Aug 16 04:24:24 PM PDT 24 Aug 16 04:53:05 PM PDT 24 336500850000 ps
T25 /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.2926978008 Aug 16 04:24:17 PM PDT 24 Aug 16 04:50:38 PM PDT 24 336655410000 ps
T26 /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.3922451707 Aug 16 04:24:36 PM PDT 24 Aug 16 05:01:20 PM PDT 24 336629310000 ps
T27 /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.529469665 Aug 16 04:25:00 PM PDT 24 Aug 16 04:55:47 PM PDT 24 336689410000 ps
T28 /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.1139915249 Aug 16 04:24:24 PM PDT 24 Aug 16 04:53:10 PM PDT 24 336964790000 ps
T29 /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.12481280 Aug 16 04:19:54 PM PDT 24 Aug 16 04:55:59 PM PDT 24 336810970000 ps
T30 /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.3199265800 Aug 16 04:21:49 PM PDT 24 Aug 16 04:53:46 PM PDT 24 337060930000 ps
T111 /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.1429541139 Aug 16 04:24:42 PM PDT 24 Aug 16 05:00:42 PM PDT 24 336369270000 ps
T112 /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.824271601 Aug 16 04:20:41 PM PDT 24 Aug 16 04:57:39 PM PDT 24 336989330000 ps
T113 /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.1809968161 Aug 16 04:23:16 PM PDT 24 Aug 16 04:55:44 PM PDT 24 336861710000 ps
T114 /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.1197579547 Aug 16 04:24:25 PM PDT 24 Aug 16 04:53:07 PM PDT 24 336395430000 ps
T115 /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.3764595168 Aug 16 04:24:18 PM PDT 24 Aug 16 04:51:08 PM PDT 24 336474190000 ps
T116 /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.3394585166 Aug 16 04:23:21 PM PDT 24 Aug 16 04:49:39 PM PDT 24 336602450000 ps
T117 /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.501568678 Aug 16 04:19:45 PM PDT 24 Aug 16 04:55:39 PM PDT 24 336814690000 ps
T118 /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.612462390 Aug 16 04:19:38 PM PDT 24 Aug 16 04:52:01 PM PDT 24 336472870000 ps
T119 /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.1283640345 Aug 16 04:23:42 PM PDT 24 Aug 16 04:49:47 PM PDT 24 336977230000 ps
T120 /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.2970987861 Aug 16 04:24:35 PM PDT 24 Aug 16 05:01:07 PM PDT 24 336729510000 ps
T121 /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.2806893428 Aug 16 04:19:18 PM PDT 24 Aug 16 05:02:13 PM PDT 24 336913570000 ps
T122 /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.3986346705 Aug 16 04:19:10 PM PDT 24 Aug 16 04:54:47 PM PDT 24 336616170000 ps
T123 /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.1273894576 Aug 16 04:23:39 PM PDT 24 Aug 16 04:52:20 PM PDT 24 336805910000 ps
T124 /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.869731109 Aug 16 04:23:49 PM PDT 24 Aug 16 04:57:02 PM PDT 24 336589810000 ps
T125 /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.834915762 Aug 16 04:21:39 PM PDT 24 Aug 16 04:56:14 PM PDT 24 336821990000 ps
T126 /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.2024827600 Aug 16 04:18:31 PM PDT 24 Aug 16 05:01:13 PM PDT 24 337027790000 ps
T127 /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.3509214640 Aug 16 04:23:36 PM PDT 24 Aug 16 04:55:02 PM PDT 24 337029230000 ps
T128 /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.14550614 Aug 16 04:20:28 PM PDT 24 Aug 16 04:51:28 PM PDT 24 336809230000 ps
T129 /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.3174610438 Aug 16 04:19:42 PM PDT 24 Aug 16 04:55:05 PM PDT 24 336375770000 ps
T130 /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.100503285 Aug 16 04:19:22 PM PDT 24 Aug 16 04:51:26 PM PDT 24 336820130000 ps
T131 /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.328547111 Aug 16 04:24:32 PM PDT 24 Aug 16 04:54:21 PM PDT 24 336527450000 ps
T132 /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.1825140770 Aug 16 04:23:21 PM PDT 24 Aug 16 04:51:56 PM PDT 24 336473170000 ps
T133 /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.1449173436 Aug 16 04:23:21 PM PDT 24 Aug 16 04:49:38 PM PDT 24 336820850000 ps
T134 /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.415515108 Aug 16 04:24:33 PM PDT 24 Aug 16 04:56:24 PM PDT 24 336599090000 ps
T135 /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.757936509 Aug 16 04:24:32 PM PDT 24 Aug 16 04:54:24 PM PDT 24 336998370000 ps
T136 /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.726505168 Aug 16 04:21:18 PM PDT 24 Aug 16 05:02:43 PM PDT 24 336459970000 ps
T137 /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.2830636964 Aug 16 04:25:02 PM PDT 24 Aug 16 04:50:55 PM PDT 24 336535330000 ps
T138 /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.4116857422 Aug 16 04:20:45 PM PDT 24 Aug 16 04:48:00 PM PDT 24 336627150000 ps
T139 /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.1699472444 Aug 16 04:23:51 PM PDT 24 Aug 16 04:50:26 PM PDT 24 337020050000 ps
T140 /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.3787347292 Aug 16 04:23:02 PM PDT 24 Aug 16 04:58:31 PM PDT 24 336333890000 ps
T141 /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.1304689081 Aug 16 04:21:44 PM PDT 24 Aug 16 04:57:37 PM PDT 24 336793950000 ps
T142 /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.2933773568 Aug 16 04:23:52 PM PDT 24 Aug 16 04:50:38 PM PDT 24 336735550000 ps
T143 /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.3280716200 Aug 16 04:24:35 PM PDT 24 Aug 16 05:01:18 PM PDT 24 336520690000 ps
T144 /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.2918134907 Aug 16 04:19:12 PM PDT 24 Aug 16 04:51:30 PM PDT 24 336722830000 ps
T145 /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.1593480678 Aug 16 04:22:25 PM PDT 24 Aug 16 04:58:09 PM PDT 24 336899450000 ps
T146 /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.4205474831 Aug 16 04:24:34 PM PDT 24 Aug 16 04:52:06 PM PDT 24 336609530000 ps
T147 /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.806941940 Aug 16 04:23:58 PM PDT 24 Aug 16 04:51:18 PM PDT 24 337018470000 ps
T148 /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.1299921960 Aug 16 04:22:28 PM PDT 24 Aug 16 05:04:08 PM PDT 24 337027590000 ps
T149 /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.2697150551 Aug 16 04:24:32 PM PDT 24 Aug 16 04:55:05 PM PDT 24 336956310000 ps
T150 /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.1997705793 Aug 16 04:23:01 PM PDT 24 Aug 16 04:53:33 PM PDT 24 336940730000 ps
T151 /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.3017569220 Aug 16 04:21:58 PM PDT 24 Aug 16 04:22:10 PM PDT 24 1552710000 ps
T152 /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.986797756 Aug 16 04:24:41 PM PDT 24 Aug 16 04:24:52 PM PDT 24 1431870000 ps
T153 /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.1834698852 Aug 16 04:24:39 PM PDT 24 Aug 16 04:24:53 PM PDT 24 1630530000 ps
T154 /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.619272923 Aug 16 04:20:48 PM PDT 24 Aug 16 04:20:59 PM PDT 24 1449650000 ps
T155 /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.2592951750 Aug 16 04:19:42 PM PDT 24 Aug 16 04:19:53 PM PDT 24 1468610000 ps
T156 /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1054147989 Aug 16 04:24:43 PM PDT 24 Aug 16 04:24:51 PM PDT 24 1324690000 ps
T157 /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.851898485 Aug 16 04:24:24 PM PDT 24 Aug 16 04:24:34 PM PDT 24 1425210000 ps
T158 /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.3259943882 Aug 16 04:24:38 PM PDT 24 Aug 16 04:24:44 PM PDT 24 1368890000 ps
T159 /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.2473434871 Aug 16 04:24:40 PM PDT 24 Aug 16 04:24:47 PM PDT 24 1496690000 ps
T160 /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.3344555407 Aug 16 04:24:40 PM PDT 24 Aug 16 04:24:49 PM PDT 24 1265350000 ps
T161 /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.1589688064 Aug 16 04:20:28 PM PDT 24 Aug 16 04:20:38 PM PDT 24 1649410000 ps
T162 /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.1078598500 Aug 16 04:23:52 PM PDT 24 Aug 16 04:24:01 PM PDT 24 1500090000 ps
T163 /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.3694828028 Aug 16 04:24:48 PM PDT 24 Aug 16 04:24:58 PM PDT 24 1445410000 ps
T164 /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.3285239206 Aug 16 04:24:42 PM PDT 24 Aug 16 04:24:53 PM PDT 24 1528510000 ps
T165 /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.2274891774 Aug 16 04:18:32 PM PDT 24 Aug 16 04:18:43 PM PDT 24 1585650000 ps
T166 /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.468848120 Aug 16 04:21:20 PM PDT 24 Aug 16 04:21:33 PM PDT 24 1446570000 ps
T167 /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.2711140743 Aug 16 04:21:38 PM PDT 24 Aug 16 04:21:51 PM PDT 24 1538190000 ps
T168 /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.1700774201 Aug 16 04:24:43 PM PDT 24 Aug 16 04:24:53 PM PDT 24 1440650000 ps
T169 /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.1385744662 Aug 16 04:23:16 PM PDT 24 Aug 16 04:23:24 PM PDT 24 1512710000 ps
T170 /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.4094696998 Aug 16 04:24:24 PM PDT 24 Aug 16 04:24:33 PM PDT 24 1234130000 ps
T171 /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.4215727453 Aug 16 04:24:44 PM PDT 24 Aug 16 04:24:54 PM PDT 24 1556970000 ps
T172 /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.631680290 Aug 16 04:24:24 PM PDT 24 Aug 16 04:24:34 PM PDT 24 1319770000 ps
T173 /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.796220056 Aug 16 04:20:39 PM PDT 24 Aug 16 04:20:52 PM PDT 24 1512170000 ps
T174 /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.3639689396 Aug 16 04:19:29 PM PDT 24 Aug 16 04:19:40 PM PDT 24 1539470000 ps
T175 /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.2155053385 Aug 16 04:19:35 PM PDT 24 Aug 16 04:19:43 PM PDT 24 1284330000 ps
T176 /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.3768237772 Aug 16 04:21:26 PM PDT 24 Aug 16 04:21:35 PM PDT 24 1430850000 ps
T177 /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.3820462002 Aug 16 04:24:42 PM PDT 24 Aug 16 04:24:53 PM PDT 24 1529350000 ps
T178 /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.1477305067 Aug 16 04:21:01 PM PDT 24 Aug 16 04:21:09 PM PDT 24 1222610000 ps
T179 /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.1722093716 Aug 16 04:23:02 PM PDT 24 Aug 16 04:23:09 PM PDT 24 1104890000 ps
T180 /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.1911763612 Aug 16 04:23:24 PM PDT 24 Aug 16 04:23:33 PM PDT 24 1389050000 ps
T181 /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.3320766675 Aug 16 04:19:19 PM PDT 24 Aug 16 04:19:30 PM PDT 24 1475550000 ps
T182 /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.2238030635 Aug 16 04:24:43 PM PDT 24 Aug 16 04:24:52 PM PDT 24 1467870000 ps
T183 /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.1317791801 Aug 16 04:24:40 PM PDT 24 Aug 16 04:24:49 PM PDT 24 1505050000 ps
T184 /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.2118079742 Aug 16 04:19:20 PM PDT 24 Aug 16 04:19:28 PM PDT 24 1132250000 ps
T185 /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.3200983833 Aug 16 04:23:11 PM PDT 24 Aug 16 04:23:23 PM PDT 24 1378510000 ps
T186 /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.650568822 Aug 16 04:21:48 PM PDT 24 Aug 16 04:22:00 PM PDT 24 1601670000 ps
T187 /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.1148567076 Aug 16 04:19:51 PM PDT 24 Aug 16 04:20:01 PM PDT 24 1533490000 ps
T188 /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.2352779194 Aug 16 04:24:44 PM PDT 24 Aug 16 04:24:54 PM PDT 24 1314310000 ps
T189 /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.1007209989 Aug 16 04:18:31 PM PDT 24 Aug 16 04:18:42 PM PDT 24 1420110000 ps
T190 /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.769644989 Aug 16 04:24:39 PM PDT 24 Aug 16 04:24:45 PM PDT 24 1435150000 ps
T191 /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.1031089451 Aug 16 04:24:38 PM PDT 24 Aug 16 04:24:45 PM PDT 24 1517630000 ps
T192 /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.4033411868 Aug 16 04:24:42 PM PDT 24 Aug 16 04:24:51 PM PDT 24 1297650000 ps
T193 /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.1215485468 Aug 16 04:24:42 PM PDT 24 Aug 16 04:24:53 PM PDT 24 1592150000 ps
T194 /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.2990970308 Aug 16 04:24:42 PM PDT 24 Aug 16 04:24:51 PM PDT 24 1514970000 ps
T195 /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.3251280772 Aug 16 04:19:48 PM PDT 24 Aug 16 04:19:58 PM PDT 24 1490270000 ps
T196 /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.844682763 Aug 16 04:19:38 PM PDT 24 Aug 16 04:19:48 PM PDT 24 1433350000 ps
T197 /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.2782215166 Aug 16 04:20:33 PM PDT 24 Aug 16 04:20:43 PM PDT 24 1584890000 ps
T198 /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.4047043060 Aug 16 04:19:48 PM PDT 24 Aug 16 04:19:58 PM PDT 24 1418650000 ps
T199 /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.566329079 Aug 16 04:19:56 PM PDT 24 Aug 16 04:20:06 PM PDT 24 1398770000 ps
T200 /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.2409770879 Aug 16 04:24:42 PM PDT 24 Aug 16 04:24:49 PM PDT 24 1420970000 ps

Test location /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.3125645457
Short name T10
Test name
Test status
Simulation time 1385370000 ps
CPU time 3.47 seconds
Started Aug 16 04:24:17 PM PDT 24
Finished Aug 16 04:24:25 PM PDT 24
Peak memory 164008 kb
Host smart-ff272ba4-893f-4505-8244-d98975b80944
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3125645457 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.3125645457
Directory /workspace/14.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.2729383599
Short name T20
Test name
Test status
Simulation time 337010630000 ps
CPU time 975.68 seconds
Started Aug 16 04:20:34 PM PDT 24
Finished Aug 16 05:01:46 PM PDT 24
Peak memory 160408 kb
Host smart-3a1fbad2-dc62-4cc2-9bde-4904537aa956
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2729383599 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.2729383599
Directory /workspace/0.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.529469665
Short name T27
Test name
Test status
Simulation time 336689410000 ps
CPU time 754.02 seconds
Started Aug 16 04:25:00 PM PDT 24
Finished Aug 16 04:55:47 PM PDT 24
Peak memory 160292 kb
Host smart-0ca03d39-3d1d-4b1a-af7b-2ad0151eb8a0
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=529469665 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.529469665
Directory /workspace/16.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.14550614
Short name T128
Test name
Test status
Simulation time 336809230000 ps
CPU time 755.45 seconds
Started Aug 16 04:20:28 PM PDT 24
Finished Aug 16 04:51:28 PM PDT 24
Peak memory 160452 kb
Host smart-09b5d3c2-394d-4639-932e-6d5942b43883
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=14550614 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.14550614
Directory /workspace/0.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.612462390
Short name T118
Test name
Test status
Simulation time 336472870000 ps
CPU time 793.86 seconds
Started Aug 16 04:19:38 PM PDT 24
Finished Aug 16 04:52:01 PM PDT 24
Peak memory 160556 kb
Host smart-f3b4855a-b617-4efe-bd75-ea520cf76f00
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=612462390 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.612462390
Directory /workspace/1.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.1449173436
Short name T133
Test name
Test status
Simulation time 336820850000 ps
CPU time 647.08 seconds
Started Aug 16 04:23:21 PM PDT 24
Finished Aug 16 04:49:38 PM PDT 24
Peak memory 159628 kb
Host smart-e56a6adc-8cf0-4278-adbd-13d3b77819e9
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1449173436 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.1449173436
Directory /workspace/10.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.726505168
Short name T136
Test name
Test status
Simulation time 336459970000 ps
CPU time 988 seconds
Started Aug 16 04:21:18 PM PDT 24
Finished Aug 16 05:02:43 PM PDT 24
Peak memory 160492 kb
Host smart-d48ab4f5-18e1-4ffc-8659-fbf3dbe009d9
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=726505168 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.726505168
Directory /workspace/11.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.4116857422
Short name T138
Test name
Test status
Simulation time 336627150000 ps
CPU time 666.49 seconds
Started Aug 16 04:20:45 PM PDT 24
Finished Aug 16 04:48:00 PM PDT 24
Peak memory 160588 kb
Host smart-70947457-7822-46de-9098-f63776530d2e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4116857422 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.4116857422
Directory /workspace/12.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.1273894576
Short name T123
Test name
Test status
Simulation time 336805910000 ps
CPU time 700.67 seconds
Started Aug 16 04:23:39 PM PDT 24
Finished Aug 16 04:52:20 PM PDT 24
Peak memory 160340 kb
Host smart-f75d27ac-124e-44af-ac6d-65cadbc7904d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1273894576 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.1273894576
Directory /workspace/13.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.3174610438
Short name T129
Test name
Test status
Simulation time 336375770000 ps
CPU time 861.26 seconds
Started Aug 16 04:19:42 PM PDT 24
Finished Aug 16 04:55:05 PM PDT 24
Peak memory 160740 kb
Host smart-cc1b5446-8ca5-4a46-8fb5-a67cfdc204c4
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3174610438 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.3174610438
Directory /workspace/14.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.2830636964
Short name T137
Test name
Test status
Simulation time 336535330000 ps
CPU time 633.74 seconds
Started Aug 16 04:25:02 PM PDT 24
Finished Aug 16 04:50:55 PM PDT 24
Peak memory 160360 kb
Host smart-de9fbcf6-7858-4d92-9ac9-542bac4f5e8f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2830636964 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.2830636964
Directory /workspace/15.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.2933773568
Short name T142
Test name
Test status
Simulation time 336735550000 ps
CPU time 650.57 seconds
Started Aug 16 04:23:52 PM PDT 24
Finished Aug 16 04:50:38 PM PDT 24
Peak memory 160380 kb
Host smart-d7f40b14-d16b-4e83-ae49-21831fdfb6eb
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2933773568 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.2933773568
Directory /workspace/17.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.1283640345
Short name T119
Test name
Test status
Simulation time 336977230000 ps
CPU time 641.85 seconds
Started Aug 16 04:23:42 PM PDT 24
Finished Aug 16 04:49:47 PM PDT 24
Peak memory 159768 kb
Host smart-0802bd67-fde0-41a1-b81a-8058db5bb1d7
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1283640345 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.1283640345
Directory /workspace/18.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.3509214640
Short name T127
Test name
Test status
Simulation time 337029230000 ps
CPU time 765.56 seconds
Started Aug 16 04:23:36 PM PDT 24
Finished Aug 16 04:55:02 PM PDT 24
Peak memory 160372 kb
Host smart-84be027e-34f2-488a-aeea-e74883551afd
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3509214640 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.3509214640
Directory /workspace/19.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.2024827600
Short name T126
Test name
Test status
Simulation time 337027790000 ps
CPU time 1040.75 seconds
Started Aug 16 04:18:31 PM PDT 24
Finished Aug 16 05:01:13 PM PDT 24
Peak memory 160848 kb
Host smart-0b07100f-26ac-4e44-a624-5173494b7610
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2024827600 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.2024827600
Directory /workspace/2.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.3394585166
Short name T116
Test name
Test status
Simulation time 336602450000 ps
CPU time 645.62 seconds
Started Aug 16 04:23:21 PM PDT 24
Finished Aug 16 04:49:39 PM PDT 24
Peak memory 159508 kb
Host smart-6e5152c2-352f-47c3-92d0-068bfc747799
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3394585166 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.3394585166
Directory /workspace/20.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.869731109
Short name T124
Test name
Test status
Simulation time 336589810000 ps
CPU time 811.92 seconds
Started Aug 16 04:23:49 PM PDT 24
Finished Aug 16 04:57:02 PM PDT 24
Peak memory 160496 kb
Host smart-188bcd7a-4f59-4cba-b474-ac6c44835d31
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=869731109 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.869731109
Directory /workspace/21.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.2918134907
Short name T144
Test name
Test status
Simulation time 336722830000 ps
CPU time 795.35 seconds
Started Aug 16 04:19:12 PM PDT 24
Finished Aug 16 04:51:30 PM PDT 24
Peak memory 160660 kb
Host smart-ce3939b9-9e8f-4201-afd1-1a7d3628ec60
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2918134907 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.2918134907
Directory /workspace/22.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.1197579547
Short name T114
Test name
Test status
Simulation time 336395430000 ps
CPU time 697.03 seconds
Started Aug 16 04:24:25 PM PDT 24
Finished Aug 16 04:53:07 PM PDT 24
Peak memory 160364 kb
Host smart-92e1cad0-7c92-4a93-afef-6d01e7915497
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1197579547 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.1197579547
Directory /workspace/23.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.824271601
Short name T112
Test name
Test status
Simulation time 336989330000 ps
CPU time 892.45 seconds
Started Aug 16 04:20:41 PM PDT 24
Finished Aug 16 04:57:39 PM PDT 24
Peak memory 160564 kb
Host smart-4abe3e30-62c1-41cc-84e0-a012b04d94fd
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=824271601 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.824271601
Directory /workspace/24.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.835033368
Short name T24
Test name
Test status
Simulation time 336500850000 ps
CPU time 696.78 seconds
Started Aug 16 04:24:24 PM PDT 24
Finished Aug 16 04:53:05 PM PDT 24
Peak memory 160352 kb
Host smart-db187fb7-b1c0-431c-879b-5976450792fe
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=835033368 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.835033368
Directory /workspace/25.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.3199265800
Short name T30
Test name
Test status
Simulation time 337060930000 ps
CPU time 782.04 seconds
Started Aug 16 04:21:49 PM PDT 24
Finished Aug 16 04:53:46 PM PDT 24
Peak memory 160660 kb
Host smart-0e524e07-bb6a-4a07-8c3a-b66ec7597792
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3199265800 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.3199265800
Directory /workspace/26.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.3787347292
Short name T140
Test name
Test status
Simulation time 336333890000 ps
CPU time 867.38 seconds
Started Aug 16 04:23:02 PM PDT 24
Finished Aug 16 04:58:31 PM PDT 24
Peak memory 159664 kb
Host smart-07e60239-8ff0-4d42-8965-ca8adbacb710
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3787347292 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.3787347292
Directory /workspace/27.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.12481280
Short name T29
Test name
Test status
Simulation time 336810970000 ps
CPU time 885.04 seconds
Started Aug 16 04:19:54 PM PDT 24
Finished Aug 16 04:55:59 PM PDT 24
Peak memory 160728 kb
Host smart-6af355c0-c8f0-44b5-a6ef-f3cde5c3cf8d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=12481280 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.12481280
Directory /workspace/28.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.100503285
Short name T130
Test name
Test status
Simulation time 336820130000 ps
CPU time 787.84 seconds
Started Aug 16 04:19:22 PM PDT 24
Finished Aug 16 04:51:26 PM PDT 24
Peak memory 160440 kb
Host smart-a4070520-7cb4-4d04-b988-11959f86af06
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=100503285 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.100503285
Directory /workspace/29.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.1593480678
Short name T145
Test name
Test status
Simulation time 336899450000 ps
CPU time 880.75 seconds
Started Aug 16 04:22:25 PM PDT 24
Finished Aug 16 04:58:09 PM PDT 24
Peak memory 160464 kb
Host smart-57dd5dea-b94b-445d-b65a-edb8c817f721
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1593480678 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.1593480678
Directory /workspace/3.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.1809968161
Short name T113
Test name
Test status
Simulation time 336861710000 ps
CPU time 799.31 seconds
Started Aug 16 04:23:16 PM PDT 24
Finished Aug 16 04:55:44 PM PDT 24
Peak memory 160240 kb
Host smart-5b8da7b6-a4e7-4b3f-8c10-411e34b96720
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1809968161 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.1809968161
Directory /workspace/30.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.834915762
Short name T125
Test name
Test status
Simulation time 336821990000 ps
CPU time 846.6 seconds
Started Aug 16 04:21:39 PM PDT 24
Finished Aug 16 04:56:14 PM PDT 24
Peak memory 160588 kb
Host smart-9b229efe-cbda-4247-9307-c3c4596afd28
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=834915762 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.834915762
Directory /workspace/31.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.1139915249
Short name T28
Test name
Test status
Simulation time 336964790000 ps
CPU time 695.41 seconds
Started Aug 16 04:24:24 PM PDT 24
Finished Aug 16 04:53:10 PM PDT 24
Peak memory 158868 kb
Host smart-510562c4-b7a5-437e-a0dc-f92755a28366
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1139915249 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.1139915249
Directory /workspace/32.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.1825140770
Short name T132
Test name
Test status
Simulation time 336473170000 ps
CPU time 698.86 seconds
Started Aug 16 04:23:21 PM PDT 24
Finished Aug 16 04:51:56 PM PDT 24
Peak memory 160316 kb
Host smart-cce0ac0c-1fd3-406e-a0e9-7bebee1b8967
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1825140770 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.1825140770
Directory /workspace/33.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.1997705793
Short name T150
Test name
Test status
Simulation time 336940730000 ps
CPU time 727.88 seconds
Started Aug 16 04:23:01 PM PDT 24
Finished Aug 16 04:53:33 PM PDT 24
Peak memory 158824 kb
Host smart-74141fec-059c-4dd3-a004-0a3aa3cfe84c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1997705793 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.1997705793
Directory /workspace/34.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.3986346705
Short name T122
Test name
Test status
Simulation time 336616170000 ps
CPU time 871.37 seconds
Started Aug 16 04:19:10 PM PDT 24
Finished Aug 16 04:54:47 PM PDT 24
Peak memory 160740 kb
Host smart-aa4501b2-94d1-4459-926b-5382a00fa33a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3986346705 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.3986346705
Directory /workspace/35.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.3764595168
Short name T115
Test name
Test status
Simulation time 336474190000 ps
CPU time 649.43 seconds
Started Aug 16 04:24:18 PM PDT 24
Finished Aug 16 04:51:08 PM PDT 24
Peak memory 160376 kb
Host smart-defc4189-fab1-451b-a946-084c03691bdc
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3764595168 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.3764595168
Directory /workspace/36.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.2926978008
Short name T25
Test name
Test status
Simulation time 336655410000 ps
CPU time 639.56 seconds
Started Aug 16 04:24:17 PM PDT 24
Finished Aug 16 04:50:38 PM PDT 24
Peak memory 160280 kb
Host smart-e8ea748f-9aae-446e-91bf-08fcf39b34dc
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2926978008 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.2926978008
Directory /workspace/37.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.501568678
Short name T117
Test name
Test status
Simulation time 336814690000 ps
CPU time 878.47 seconds
Started Aug 16 04:19:45 PM PDT 24
Finished Aug 16 04:55:39 PM PDT 24
Peak memory 160760 kb
Host smart-edbde655-07f0-4ac1-84a1-3ca55f6288a3
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=501568678 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.501568678
Directory /workspace/38.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.3995791123
Short name T7
Test name
Test status
Simulation time 336858730000 ps
CPU time 606.01 seconds
Started Aug 16 04:23:33 PM PDT 24
Finished Aug 16 04:48:51 PM PDT 24
Peak memory 160292 kb
Host smart-807106ee-7d0a-42c8-af4a-b164101928c8
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3995791123 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.3995791123
Directory /workspace/39.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.1304689081
Short name T141
Test name
Test status
Simulation time 336793950000 ps
CPU time 881.46 seconds
Started Aug 16 04:21:44 PM PDT 24
Finished Aug 16 04:57:37 PM PDT 24
Peak memory 160628 kb
Host smart-e35dd6ce-69f5-4954-9a25-ef9a99d5e01e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1304689081 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.1304689081
Directory /workspace/4.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.1429541139
Short name T111
Test name
Test status
Simulation time 336369270000 ps
CPU time 883.76 seconds
Started Aug 16 04:24:42 PM PDT 24
Finished Aug 16 05:00:42 PM PDT 24
Peak memory 160616 kb
Host smart-dd9a4a38-e120-4e90-ab1c-f55da70c8eaa
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1429541139 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.1429541139
Directory /workspace/40.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.328547111
Short name T131
Test name
Test status
Simulation time 336527450000 ps
CPU time 735.98 seconds
Started Aug 16 04:24:32 PM PDT 24
Finished Aug 16 04:54:21 PM PDT 24
Peak memory 160496 kb
Host smart-7d5ba25b-8434-47d9-8386-8f2c5ca17167
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=328547111 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.328547111
Directory /workspace/41.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.3280716200
Short name T143
Test name
Test status
Simulation time 336520690000 ps
CPU time 906.87 seconds
Started Aug 16 04:24:35 PM PDT 24
Finished Aug 16 05:01:18 PM PDT 24
Peak memory 160536 kb
Host smart-10a2f06c-d2de-424c-a488-f43066500b55
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3280716200 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.3280716200
Directory /workspace/42.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.3922451707
Short name T26
Test name
Test status
Simulation time 336629310000 ps
CPU time 908.75 seconds
Started Aug 16 04:24:36 PM PDT 24
Finished Aug 16 05:01:20 PM PDT 24
Peak memory 160536 kb
Host smart-94f4af53-6ecc-4694-96f7-b40167a6df94
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3922451707 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.3922451707
Directory /workspace/43.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.2697150551
Short name T149
Test name
Test status
Simulation time 336956310000 ps
CPU time 754.32 seconds
Started Aug 16 04:24:32 PM PDT 24
Finished Aug 16 04:55:05 PM PDT 24
Peak memory 160728 kb
Host smart-8902f226-be08-4f88-aff8-d433175b3af3
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2697150551 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.2697150551
Directory /workspace/44.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.4205474831
Short name T146
Test name
Test status
Simulation time 336609530000 ps
CPU time 669.37 seconds
Started Aug 16 04:24:34 PM PDT 24
Finished Aug 16 04:52:06 PM PDT 24
Peak memory 160428 kb
Host smart-ca328f9b-8678-432a-b287-c4b2e9662bc1
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4205474831 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.4205474831
Directory /workspace/45.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.415515108
Short name T134
Test name
Test status
Simulation time 336599090000 ps
CPU time 787.88 seconds
Started Aug 16 04:24:33 PM PDT 24
Finished Aug 16 04:56:24 PM PDT 24
Peak memory 160496 kb
Host smart-46616dfe-5c48-41ba-94e6-e9d38b2a62d7
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=415515108 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.415515108
Directory /workspace/46.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.677626414
Short name T5
Test name
Test status
Simulation time 336894390000 ps
CPU time 838.98 seconds
Started Aug 16 04:24:31 PM PDT 24
Finished Aug 16 04:59:24 PM PDT 24
Peak memory 160476 kb
Host smart-9c4772ac-ea44-4006-862b-8903f529223e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=677626414 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.677626414
Directory /workspace/47.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.2970987861
Short name T120
Test name
Test status
Simulation time 336729510000 ps
CPU time 910.67 seconds
Started Aug 16 04:24:35 PM PDT 24
Finished Aug 16 05:01:07 PM PDT 24
Peak memory 160536 kb
Host smart-709feff4-efaa-4ed2-bcb5-1ffc27e4eca2
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2970987861 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.2970987861
Directory /workspace/48.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.757936509
Short name T135
Test name
Test status
Simulation time 336998370000 ps
CPU time 727.77 seconds
Started Aug 16 04:24:32 PM PDT 24
Finished Aug 16 04:54:24 PM PDT 24
Peak memory 160608 kb
Host smart-223d111b-af31-4e88-b4d1-b7df7195ff3a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=757936509 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.757936509
Directory /workspace/49.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.1699472444
Short name T139
Test name
Test status
Simulation time 337020050000 ps
CPU time 644.41 seconds
Started Aug 16 04:23:51 PM PDT 24
Finished Aug 16 04:50:26 PM PDT 24
Peak memory 160368 kb
Host smart-f8353fbe-29ed-41b7-a0e3-a1ba1f9b46c0
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1699472444 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.1699472444
Directory /workspace/5.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.2806893428
Short name T121
Test name
Test status
Simulation time 336913570000 ps
CPU time 1048.3 seconds
Started Aug 16 04:19:18 PM PDT 24
Finished Aug 16 05:02:13 PM PDT 24
Peak memory 160848 kb
Host smart-cb13385a-5074-4fff-829d-548f78040ade
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2806893428 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.2806893428
Directory /workspace/6.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.806941940
Short name T147
Test name
Test status
Simulation time 337018470000 ps
CPU time 672.63 seconds
Started Aug 16 04:23:58 PM PDT 24
Finished Aug 16 04:51:18 PM PDT 24
Peak memory 160352 kb
Host smart-81fad126-7f77-494c-9fa1-aab60d276a19
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=806941940 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.806941940
Directory /workspace/7.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1471823806
Short name T6
Test name
Test status
Simulation time 337027650000 ps
CPU time 896.68 seconds
Started Aug 16 04:20:18 PM PDT 24
Finished Aug 16 04:56:28 PM PDT 24
Peak memory 160464 kb
Host smart-eb561b65-ee25-4db7-83f7-f0b997196baa
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1471823806 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.1471823806
Directory /workspace/8.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.1299921960
Short name T148
Test name
Test status
Simulation time 337027590000 ps
CPU time 986.15 seconds
Started Aug 16 04:22:28 PM PDT 24
Finished Aug 16 05:04:08 PM PDT 24
Peak memory 160488 kb
Host smart-f94fcae5-91ac-4171-938c-cbfe3cbd36f5
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1299921960 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.1299921960
Directory /workspace/9.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.1703704989
Short name T93
Test name
Test status
Simulation time 336815390000 ps
CPU time 665.62 seconds
Started Aug 16 04:23:59 PM PDT 24
Finished Aug 16 04:51:18 PM PDT 24
Peak memory 160548 kb
Host smart-8b898bce-8819-4cd2-85a3-3fad965b87ff
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1703704989 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.1703704989
Directory /workspace/1.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.2375244498
Short name T75
Test name
Test status
Simulation time 336953770000 ps
CPU time 837.79 seconds
Started Aug 16 04:23:04 PM PDT 24
Finished Aug 16 04:56:57 PM PDT 24
Peak memory 160488 kb
Host smart-bf1d9a45-b70c-4268-a677-78a504776a76
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2375244498 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.2375244498
Directory /workspace/10.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.2865688470
Short name T98
Test name
Test status
Simulation time 336790810000 ps
CPU time 1019.78 seconds
Started Aug 16 04:22:51 PM PDT 24
Finished Aug 16 05:04:46 PM PDT 24
Peak memory 160812 kb
Host smart-441e431e-8202-49d7-8115-f23bf41b0903
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2865688470 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.2865688470
Directory /workspace/11.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.377296559
Short name T83
Test name
Test status
Simulation time 336873250000 ps
CPU time 748.4 seconds
Started Aug 16 04:25:00 PM PDT 24
Finished Aug 16 04:55:49 PM PDT 24
Peak memory 160296 kb
Host smart-578e0399-36c4-4faf-97e3-1303e41ec2ea
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=377296559 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.377296559
Directory /workspace/12.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.2178163033
Short name T108
Test name
Test status
Simulation time 337024550000 ps
CPU time 958.34 seconds
Started Aug 16 04:19:53 PM PDT 24
Finished Aug 16 05:00:24 PM PDT 24
Peak memory 160512 kb
Host smart-a642cad0-b847-453d-81ab-b42dd1c81569
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2178163033 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.2178163033
Directory /workspace/13.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.1524618968
Short name T73
Test name
Test status
Simulation time 336443870000 ps
CPU time 676.96 seconds
Started Aug 16 04:21:24 PM PDT 24
Finished Aug 16 04:49:18 PM PDT 24
Peak memory 160592 kb
Host smart-e1be755d-1a30-4ff3-821e-a5534381e791
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1524618968 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.1524618968
Directory /workspace/14.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.3236457261
Short name T15
Test name
Test status
Simulation time 337103650000 ps
CPU time 893.84 seconds
Started Aug 16 04:21:10 PM PDT 24
Finished Aug 16 04:58:11 PM PDT 24
Peak memory 160628 kb
Host smart-07959240-71ac-414d-bcbe-c38cda2ab98e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3236457261 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.3236457261
Directory /workspace/15.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.3248852607
Short name T84
Test name
Test status
Simulation time 336582590000 ps
CPU time 703.52 seconds
Started Aug 16 04:23:35 PM PDT 24
Finished Aug 16 04:52:22 PM PDT 24
Peak memory 160572 kb
Host smart-d905fe1b-18eb-4b50-b1fd-aa8629805e6b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3248852607 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.3248852607
Directory /workspace/16.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.2939883164
Short name T87
Test name
Test status
Simulation time 336402590000 ps
CPU time 787.14 seconds
Started Aug 16 04:23:36 PM PDT 24
Finished Aug 16 04:56:09 PM PDT 24
Peak memory 160376 kb
Host smart-0551dea0-a39b-4c69-8f67-54a00863a678
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2939883164 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.2939883164
Directory /workspace/17.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.1356381271
Short name T74
Test name
Test status
Simulation time 336605610000 ps
CPU time 732.16 seconds
Started Aug 16 04:24:59 PM PDT 24
Finished Aug 16 04:54:47 PM PDT 24
Peak memory 159340 kb
Host smart-e419aac8-1768-4ee7-b20d-6de63eca98af
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1356381271 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.1356381271
Directory /workspace/18.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.1303857018
Short name T106
Test name
Test status
Simulation time 336654310000 ps
CPU time 681.11 seconds
Started Aug 16 04:24:15 PM PDT 24
Finished Aug 16 04:52:08 PM PDT 24
Peak memory 159928 kb
Host smart-50b9d686-79d5-4994-bc85-7683022bba72
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1303857018 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.1303857018
Directory /workspace/19.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.2501133518
Short name T79
Test name
Test status
Simulation time 336935450000 ps
CPU time 817.92 seconds
Started Aug 16 04:22:32 PM PDT 24
Finished Aug 16 04:55:44 PM PDT 24
Peak memory 160704 kb
Host smart-2c529986-1714-4847-83b5-398729fb5248
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2501133518 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.2501133518
Directory /workspace/2.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.158785966
Short name T95
Test name
Test status
Simulation time 336945630000 ps
CPU time 799.69 seconds
Started Aug 16 04:19:19 PM PDT 24
Finished Aug 16 04:51:35 PM PDT 24
Peak memory 160472 kb
Host smart-0ae37c97-6487-4c2f-9f17-f2f77a0067bf
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=158785966 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.158785966
Directory /workspace/20.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.270263353
Short name T18
Test name
Test status
Simulation time 336608490000 ps
CPU time 764.75 seconds
Started Aug 16 04:23:35 PM PDT 24
Finished Aug 16 04:55:12 PM PDT 24
Peak memory 159200 kb
Host smart-0d992aeb-f395-4210-9161-ef251f4872f0
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=270263353 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.270263353
Directory /workspace/21.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.2053950722
Short name T17
Test name
Test status
Simulation time 337030570000 ps
CPU time 706.6 seconds
Started Aug 16 04:24:24 PM PDT 24
Finished Aug 16 04:53:30 PM PDT 24
Peak memory 160368 kb
Host smart-ccbf3c48-e7ed-49a2-806f-74463c520b9a
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2053950722 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.2053950722
Directory /workspace/22.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.1662218004
Short name T94
Test name
Test status
Simulation time 336984650000 ps
CPU time 895.21 seconds
Started Aug 16 04:19:04 PM PDT 24
Finished Aug 16 04:57:30 PM PDT 24
Peak memory 160512 kb
Host smart-ac5ff506-8b00-4d60-8cdb-fbb98356e957
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1662218004 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.1662218004
Directory /workspace/23.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.3509208810
Short name T103
Test name
Test status
Simulation time 336774230000 ps
CPU time 874.45 seconds
Started Aug 16 04:19:54 PM PDT 24
Finished Aug 16 04:55:48 PM PDT 24
Peak memory 160744 kb
Host smart-72d192d8-8c85-4341-8245-7a7838e7474e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3509208810 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.3509208810
Directory /workspace/24.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.2540490651
Short name T82
Test name
Test status
Simulation time 336405050000 ps
CPU time 854.74 seconds
Started Aug 16 04:23:03 PM PDT 24
Finished Aug 16 04:58:18 PM PDT 24
Peak memory 160220 kb
Host smart-64f598e3-af2a-4930-a958-3de33df1e1b1
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2540490651 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.2540490651
Directory /workspace/25.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.1145787290
Short name T19
Test name
Test status
Simulation time 336933990000 ps
CPU time 738.14 seconds
Started Aug 16 04:23:01 PM PDT 24
Finished Aug 16 04:53:31 PM PDT 24
Peak memory 158880 kb
Host smart-973b06a9-7df2-415d-bf00-0ca07892e48b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1145787290 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.1145787290
Directory /workspace/26.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.2330245501
Short name T81
Test name
Test status
Simulation time 336743670000 ps
CPU time 770.61 seconds
Started Aug 16 04:19:40 PM PDT 24
Finished Aug 16 04:50:35 PM PDT 24
Peak memory 160728 kb
Host smart-04c66261-a76c-45da-97cf-4adb70846ee1
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2330245501 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.2330245501
Directory /workspace/27.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.1168582662
Short name T102
Test name
Test status
Simulation time 336617670000 ps
CPU time 857.03 seconds
Started Aug 16 04:19:59 PM PDT 24
Finished Aug 16 04:54:43 PM PDT 24
Peak memory 160428 kb
Host smart-808aed52-b20b-44f2-b750-ef5d7fdf2cc4
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1168582662 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.1168582662
Directory /workspace/28.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.1778819038
Short name T86
Test name
Test status
Simulation time 336788150000 ps
CPU time 798.24 seconds
Started Aug 16 04:23:16 PM PDT 24
Finished Aug 16 04:55:47 PM PDT 24
Peak memory 160244 kb
Host smart-03e1217b-86fe-4e15-b60d-e8d3496f0adc
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1778819038 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.1778819038
Directory /workspace/29.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.1865171801
Short name T107
Test name
Test status
Simulation time 336413910000 ps
CPU time 818.97 seconds
Started Aug 16 04:21:36 PM PDT 24
Finished Aug 16 04:54:58 PM PDT 24
Peak memory 160588 kb
Host smart-5ebbd350-c5c4-415d-8c33-4bec4fd019d5
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1865171801 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.1865171801
Directory /workspace/3.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.1054881257
Short name T101
Test name
Test status
Simulation time 336450670000 ps
CPU time 731.29 seconds
Started Aug 16 04:23:01 PM PDT 24
Finished Aug 16 04:53:34 PM PDT 24
Peak memory 158756 kb
Host smart-94c3234b-7b2d-4b34-8cb2-f60d2178ff4f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1054881257 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.1054881257
Directory /workspace/30.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.193823241
Short name T88
Test name
Test status
Simulation time 336735530000 ps
CPU time 783.18 seconds
Started Aug 16 04:23:16 PM PDT 24
Finished Aug 16 04:55:21 PM PDT 24
Peak memory 160224 kb
Host smart-a24368ce-55f7-48c5-9077-31d0e3c0aeeb
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=193823241 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.193823241
Directory /workspace/31.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.3985729525
Short name T22
Test name
Test status
Simulation time 336836610000 ps
CPU time 698.7 seconds
Started Aug 16 04:23:21 PM PDT 24
Finished Aug 16 04:51:45 PM PDT 24
Peak memory 159500 kb
Host smart-fe0c136a-b765-49a9-970b-7936d31f1b86
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3985729525 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.3985729525
Directory /workspace/32.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.3945092496
Short name T109
Test name
Test status
Simulation time 336892630000 ps
CPU time 745.61 seconds
Started Aug 16 04:23:52 PM PDT 24
Finished Aug 16 04:54:01 PM PDT 24
Peak memory 160248 kb
Host smart-1aeb205b-92f8-4e2f-8e17-d85e6d140812
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3945092496 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.3945092496
Directory /workspace/33.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.1948943119
Short name T14
Test name
Test status
Simulation time 336760350000 ps
CPU time 726.81 seconds
Started Aug 16 04:19:35 PM PDT 24
Finished Aug 16 04:49:18 PM PDT 24
Peak memory 159172 kb
Host smart-dd9b815c-9499-45db-9117-f722cc52ff0b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1948943119 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.1948943119
Directory /workspace/34.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.2508923274
Short name T78
Test name
Test status
Simulation time 336759090000 ps
CPU time 856.35 seconds
Started Aug 16 04:19:28 PM PDT 24
Finished Aug 16 04:54:24 PM PDT 24
Peak memory 158936 kb
Host smart-273564d7-e9f7-47f9-abf8-ba05684a2b1c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2508923274 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.2508923274
Directory /workspace/35.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.3080967846
Short name T77
Test name
Test status
Simulation time 336569830000 ps
CPU time 800.53 seconds
Started Aug 16 04:19:37 PM PDT 24
Finished Aug 16 04:52:47 PM PDT 24
Peak memory 160320 kb
Host smart-69bb948a-5869-4b74-820a-c778719631fe
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3080967846 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.3080967846
Directory /workspace/36.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.3736453457
Short name T91
Test name
Test status
Simulation time 336479070000 ps
CPU time 1039.05 seconds
Started Aug 16 04:18:31 PM PDT 24
Finished Aug 16 05:01:07 PM PDT 24
Peak memory 160812 kb
Host smart-f7743529-0fe4-4d2a-9cd9-9e2d0fa6f19d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3736453457 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.3736453457
Directory /workspace/37.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.2460578267
Short name T104
Test name
Test status
Simulation time 336395630000 ps
CPU time 642.88 seconds
Started Aug 16 04:19:28 PM PDT 24
Finished Aug 16 04:45:50 PM PDT 24
Peak memory 159172 kb
Host smart-09f0edb8-60e6-4f20-b0ec-8f0d8963861c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2460578267 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.2460578267
Directory /workspace/38.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.3391688892
Short name T89
Test name
Test status
Simulation time 336301370000 ps
CPU time 837.09 seconds
Started Aug 16 04:19:38 PM PDT 24
Finished Aug 16 04:54:18 PM PDT 24
Peak memory 160320 kb
Host smart-05ddac81-7f01-44e5-a345-68874244f2b7
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3391688892 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.3391688892
Directory /workspace/39.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.1562361260
Short name T100
Test name
Test status
Simulation time 336551790000 ps
CPU time 666.11 seconds
Started Aug 16 04:22:07 PM PDT 24
Finished Aug 16 04:49:42 PM PDT 24
Peak memory 160768 kb
Host smart-5e253ad4-fbb1-4fa5-b0a4-0c12f82f115b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1562361260 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.1562361260
Directory /workspace/4.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.459600574
Short name T90
Test name
Test status
Simulation time 336317850000 ps
CPU time 1044.25 seconds
Started Aug 16 04:18:30 PM PDT 24
Finished Aug 16 05:01:10 PM PDT 24
Peak memory 160832 kb
Host smart-c0abca88-25c1-4557-8286-89d3769a5baa
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=459600574 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.459600574
Directory /workspace/40.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.451274827
Short name T85
Test name
Test status
Simulation time 336981210000 ps
CPU time 800.17 seconds
Started Aug 16 04:24:34 PM PDT 24
Finished Aug 16 04:57:03 PM PDT 24
Peak memory 160684 kb
Host smart-99536d2b-15e1-42a6-a985-42e59c0e7df5
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=451274827 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.451274827
Directory /workspace/41.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.2320638676
Short name T71
Test name
Test status
Simulation time 336622930000 ps
CPU time 915.04 seconds
Started Aug 16 04:19:47 PM PDT 24
Finished Aug 16 04:57:35 PM PDT 24
Peak memory 159216 kb
Host smart-d4fc8a79-271b-4c3c-817f-b528cb32469c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2320638676 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.2320638676
Directory /workspace/42.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.815718216
Short name T16
Test name
Test status
Simulation time 336522110000 ps
CPU time 741.55 seconds
Started Aug 16 04:21:45 PM PDT 24
Finished Aug 16 04:52:15 PM PDT 24
Peak memory 160684 kb
Host smart-0600464d-d261-40a7-bb98-80d55a46d60e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=815718216 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.815718216
Directory /workspace/43.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.604706561
Short name T80
Test name
Test status
Simulation time 336927570000 ps
CPU time 984.47 seconds
Started Aug 16 04:24:32 PM PDT 24
Finished Aug 16 05:05:44 PM PDT 24
Peak memory 160496 kb
Host smart-5d23644c-3225-48e6-9f3f-5279f687dde0
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=604706561 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.604706561
Directory /workspace/44.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.3287205734
Short name T99
Test name
Test status
Simulation time 336945590000 ps
CPU time 841.54 seconds
Started Aug 16 04:24:31 PM PDT 24
Finished Aug 16 04:59:31 PM PDT 24
Peak memory 160496 kb
Host smart-d1147c12-a1b0-4a2d-9cfb-a903187655bf
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3287205734 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.3287205734
Directory /workspace/45.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.1082017759
Short name T96
Test name
Test status
Simulation time 336310150000 ps
CPU time 642.46 seconds
Started Aug 16 04:24:34 PM PDT 24
Finished Aug 16 04:50:52 PM PDT 24
Peak memory 160444 kb
Host smart-3c261937-8efa-47fe-9d4c-13bd3c8db851
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1082017759 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.1082017759
Directory /workspace/46.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.2688475372
Short name T97
Test name
Test status
Simulation time 336631030000 ps
CPU time 797.19 seconds
Started Aug 16 04:24:32 PM PDT 24
Finished Aug 16 04:56:38 PM PDT 24
Peak memory 160420 kb
Host smart-cba4294e-5bae-4773-b763-7969abebf2c8
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2688475372 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.2688475372
Directory /workspace/47.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1283119063
Short name T23
Test name
Test status
Simulation time 336587570000 ps
CPU time 890.37 seconds
Started Aug 16 04:24:42 PM PDT 24
Finished Aug 16 05:00:57 PM PDT 24
Peak memory 160620 kb
Host smart-40809cf1-f3e1-4da5-a75e-2efc2f99aa46
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1283119063 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.1283119063
Directory /workspace/48.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.2904371429
Short name T76
Test name
Test status
Simulation time 336531730000 ps
CPU time 872.98 seconds
Started Aug 16 04:24:42 PM PDT 24
Finished Aug 16 05:00:13 PM PDT 24
Peak memory 160620 kb
Host smart-e791ba4f-2f6f-42a1-89b2-21978fc24289
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2904371429 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.2904371429
Directory /workspace/49.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.450602747
Short name T110
Test name
Test status
Simulation time 336832070000 ps
CPU time 763.27 seconds
Started Aug 16 04:21:03 PM PDT 24
Finished Aug 16 04:51:47 PM PDT 24
Peak memory 160736 kb
Host smart-43623104-513a-49ef-bf88-e7d37cbaf633
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=450602747 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.450602747
Directory /workspace/5.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.2243940028
Short name T92
Test name
Test status
Simulation time 337048710000 ps
CPU time 798.46 seconds
Started Aug 16 04:20:20 PM PDT 24
Finished Aug 16 04:52:54 PM PDT 24
Peak memory 160540 kb
Host smart-c3d2fc1b-cac3-4448-a5d0-17c07244b45c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2243940028 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.2243940028
Directory /workspace/6.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.690096885
Short name T72
Test name
Test status
Simulation time 336332410000 ps
CPU time 649.58 seconds
Started Aug 16 04:22:55 PM PDT 24
Finished Aug 16 04:49:35 PM PDT 24
Peak memory 159960 kb
Host smart-ad4f86ed-f006-4001-b6a0-653ef847ea20
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=690096885 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.690096885
Directory /workspace/7.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.1269277014
Short name T105
Test name
Test status
Simulation time 336517850000 ps
CPU time 770.61 seconds
Started Aug 16 04:22:54 PM PDT 24
Finished Aug 16 04:54:26 PM PDT 24
Peak memory 160308 kb
Host smart-a29bf2c8-f00c-4456-80eb-7611ee24995b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1269277014 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.1269277014
Directory /workspace/8.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.2306022014
Short name T21
Test name
Test status
Simulation time 337095870000 ps
CPU time 864.94 seconds
Started Aug 16 04:19:55 PM PDT 24
Finished Aug 16 04:55:35 PM PDT 24
Peak memory 160784 kb
Host smart-3d190d48-b8aa-4cd4-a1db-63a8d332c7cf
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2306022014 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.2306022014
Directory /workspace/9.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.650568822
Short name T186
Test name
Test status
Simulation time 1601670000 ps
CPU time 5.22 seconds
Started Aug 16 04:21:48 PM PDT 24
Finished Aug 16 04:22:00 PM PDT 24
Peak memory 164820 kb
Host smart-965c7c07-0fea-4389-92ec-25fd14d6b14a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=650568822 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.650568822
Directory /workspace/0.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.2782215166
Short name T197
Test name
Test status
Simulation time 1584890000 ps
CPU time 4.51 seconds
Started Aug 16 04:20:33 PM PDT 24
Finished Aug 16 04:20:43 PM PDT 24
Peak memory 164740 kb
Host smart-83b2ae43-b4e9-463d-84b4-711cfe3f74e9
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2782215166 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.2782215166
Directory /workspace/1.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.1722093716
Short name T179
Test name
Test status
Simulation time 1104890000 ps
CPU time 3.19 seconds
Started Aug 16 04:23:02 PM PDT 24
Finished Aug 16 04:23:09 PM PDT 24
Peak memory 164424 kb
Host smart-3ca09a65-19c2-48e7-981a-2813731898a7
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1722093716 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.1722093716
Directory /workspace/10.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.631680290
Short name T172
Test name
Test status
Simulation time 1319770000 ps
CPU time 4.08 seconds
Started Aug 16 04:24:24 PM PDT 24
Finished Aug 16 04:24:34 PM PDT 24
Peak memory 162188 kb
Host smart-9942fcf8-9a5c-4fea-84e4-9a9ad571b122
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=631680290 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.631680290
Directory /workspace/11.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.1385744662
Short name T169
Test name
Test status
Simulation time 1512710000 ps
CPU time 3.64 seconds
Started Aug 16 04:23:16 PM PDT 24
Finished Aug 16 04:23:24 PM PDT 24
Peak memory 164460 kb
Host smart-f1918c17-bc3e-4b60-8e39-386d0384a155
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1385744662 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.1385744662
Directory /workspace/12.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.2118079742
Short name T184
Test name
Test status
Simulation time 1132250000 ps
CPU time 3.86 seconds
Started Aug 16 04:19:20 PM PDT 24
Finished Aug 16 04:19:28 PM PDT 24
Peak memory 164920 kb
Host smart-e85fb634-5889-4f6c-a3fd-6f7710b59872
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2118079742 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.2118079742
Directory /workspace/13.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.4094696998
Short name T170
Test name
Test status
Simulation time 1234130000 ps
CPU time 3.77 seconds
Started Aug 16 04:24:24 PM PDT 24
Finished Aug 16 04:24:33 PM PDT 24
Peak memory 162260 kb
Host smart-ebf1a9ed-5cc6-49ab-bbac-3834d534e191
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4094696998 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.4094696998
Directory /workspace/14.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.1148567076
Short name T187
Test name
Test status
Simulation time 1533490000 ps
CPU time 4.51 seconds
Started Aug 16 04:19:51 PM PDT 24
Finished Aug 16 04:20:01 PM PDT 24
Peak memory 164736 kb
Host smart-8b168ff4-f54e-4766-b5fa-202dc79884b3
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1148567076 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.1148567076
Directory /workspace/15.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.3200983833
Short name T185
Test name
Test status
Simulation time 1378510000 ps
CPU time 5.53 seconds
Started Aug 16 04:23:11 PM PDT 24
Finished Aug 16 04:23:23 PM PDT 24
Peak memory 164920 kb
Host smart-03c78692-effd-4d32-8e24-c38b7cce790e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3200983833 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.3200983833
Directory /workspace/16.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.619272923
Short name T154
Test name
Test status
Simulation time 1449650000 ps
CPU time 5.08 seconds
Started Aug 16 04:20:48 PM PDT 24
Finished Aug 16 04:20:59 PM PDT 24
Peak memory 164476 kb
Host smart-8484bbf7-a438-4dc9-8bb7-626f8b09c0e5
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=619272923 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.619272923
Directory /workspace/17.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.1078598500
Short name T162
Test name
Test status
Simulation time 1500090000 ps
CPU time 3.98 seconds
Started Aug 16 04:23:52 PM PDT 24
Finished Aug 16 04:24:01 PM PDT 24
Peak memory 164940 kb
Host smart-951f5eab-9096-4975-af0f-62654aef4b5e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1078598500 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.1078598500
Directory /workspace/18.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.1589688064
Short name T161
Test name
Test status
Simulation time 1649410000 ps
CPU time 4.51 seconds
Started Aug 16 04:20:28 PM PDT 24
Finished Aug 16 04:20:38 PM PDT 24
Peak memory 164440 kb
Host smart-555a4bf2-bf34-489d-8e2e-ef75a409809d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1589688064 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.1589688064
Directory /workspace/19.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.1911763612
Short name T180
Test name
Test status
Simulation time 1389050000 ps
CPU time 4.21 seconds
Started Aug 16 04:23:24 PM PDT 24
Finished Aug 16 04:23:33 PM PDT 24
Peak memory 164424 kb
Host smart-a5c096e0-017a-4b75-a2c1-60db329b2118
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1911763612 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.1911763612
Directory /workspace/2.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.468848120
Short name T166
Test name
Test status
Simulation time 1446570000 ps
CPU time 5.62 seconds
Started Aug 16 04:21:20 PM PDT 24
Finished Aug 16 04:21:33 PM PDT 24
Peak memory 165004 kb
Host smart-8151589c-8454-4d28-85e3-3bad8588843f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=468848120 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.468848120
Directory /workspace/20.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.2274891774
Short name T165
Test name
Test status
Simulation time 1585650000 ps
CPU time 4.92 seconds
Started Aug 16 04:18:32 PM PDT 24
Finished Aug 16 04:18:43 PM PDT 24
Peak memory 164300 kb
Host smart-62b332b1-3dfc-46e6-9bde-b9c5a22747b9
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2274891774 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.2274891774
Directory /workspace/21.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.3251280772
Short name T195
Test name
Test status
Simulation time 1490270000 ps
CPU time 4.66 seconds
Started Aug 16 04:19:48 PM PDT 24
Finished Aug 16 04:19:58 PM PDT 24
Peak memory 164440 kb
Host smart-ccc6ec32-fa4d-4339-896b-1e18e846cf36
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3251280772 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.3251280772
Directory /workspace/22.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.4047043060
Short name T198
Test name
Test status
Simulation time 1418650000 ps
CPU time 4.39 seconds
Started Aug 16 04:19:48 PM PDT 24
Finished Aug 16 04:19:58 PM PDT 24
Peak memory 164440 kb
Host smart-f433837c-e3aa-4d2f-b8ea-40a07a74b42a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4047043060 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.4047043060
Directory /workspace/23.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.844682763
Short name T196
Test name
Test status
Simulation time 1433350000 ps
CPU time 4.49 seconds
Started Aug 16 04:19:38 PM PDT 24
Finished Aug 16 04:19:48 PM PDT 24
Peak memory 164248 kb
Host smart-fbb78c30-4fe7-44be-a939-5d7033732141
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=844682763 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.844682763
Directory /workspace/24.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.1007209989
Short name T189
Test name
Test status
Simulation time 1420110000 ps
CPU time 4.98 seconds
Started Aug 16 04:18:31 PM PDT 24
Finished Aug 16 04:18:42 PM PDT 24
Peak memory 164948 kb
Host smart-529ea2b5-f543-44b7-b54b-e5500e2435b2
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1007209989 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.1007209989
Directory /workspace/25.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.3639689396
Short name T174
Test name
Test status
Simulation time 1539470000 ps
CPU time 4.79 seconds
Started Aug 16 04:19:29 PM PDT 24
Finished Aug 16 04:19:40 PM PDT 24
Peak memory 164856 kb
Host smart-9d8ae07e-c2b0-465d-b194-ad1794841b7e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3639689396 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.3639689396
Directory /workspace/26.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.2592951750
Short name T155
Test name
Test status
Simulation time 1468610000 ps
CPU time 5.02 seconds
Started Aug 16 04:19:42 PM PDT 24
Finished Aug 16 04:19:53 PM PDT 24
Peak memory 164592 kb
Host smart-1d7a73e4-0fa6-4122-ae6a-3a9fc8d0a223
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2592951750 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.2592951750
Directory /workspace/27.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.2155053385
Short name T175
Test name
Test status
Simulation time 1284330000 ps
CPU time 3.79 seconds
Started Aug 16 04:19:35 PM PDT 24
Finished Aug 16 04:19:43 PM PDT 24
Peak memory 163032 kb
Host smart-02945e83-62e1-4870-8f7c-89ffdc5d9741
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2155053385 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.2155053385
Directory /workspace/28.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.1477305067
Short name T178
Test name
Test status
Simulation time 1222610000 ps
CPU time 3.91 seconds
Started Aug 16 04:21:01 PM PDT 24
Finished Aug 16 04:21:09 PM PDT 24
Peak memory 164736 kb
Host smart-4b310a1f-ea7e-41b4-a85f-1f2a2e70f2f9
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1477305067 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.1477305067
Directory /workspace/29.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.3017569220
Short name T151
Test name
Test status
Simulation time 1552710000 ps
CPU time 5.19 seconds
Started Aug 16 04:21:58 PM PDT 24
Finished Aug 16 04:22:10 PM PDT 24
Peak memory 164920 kb
Host smart-58a2dd84-c566-47b2-9c11-2fdec8353506
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3017569220 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.3017569220
Directory /workspace/3.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.3344555407
Short name T160
Test name
Test status
Simulation time 1265350000 ps
CPU time 3.87 seconds
Started Aug 16 04:24:40 PM PDT 24
Finished Aug 16 04:24:49 PM PDT 24
Peak memory 164580 kb
Host smart-171dfa73-e2e6-430f-9e73-0ca15191e987
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3344555407 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.3344555407
Directory /workspace/30.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.2352779194
Short name T188
Test name
Test status
Simulation time 1314310000 ps
CPU time 4.54 seconds
Started Aug 16 04:24:44 PM PDT 24
Finished Aug 16 04:24:54 PM PDT 24
Peak memory 164696 kb
Host smart-da81dd02-fba3-469e-bda1-de02dba6d45d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2352779194 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.2352779194
Directory /workspace/31.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.4215727453
Short name T171
Test name
Test status
Simulation time 1556970000 ps
CPU time 4.78 seconds
Started Aug 16 04:24:44 PM PDT 24
Finished Aug 16 04:24:54 PM PDT 24
Peak memory 164484 kb
Host smart-4f835bb7-6b0a-4041-8812-83a681136282
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4215727453 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.4215727453
Directory /workspace/32.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.986797756
Short name T152
Test name
Test status
Simulation time 1431870000 ps
CPU time 4.92 seconds
Started Aug 16 04:24:41 PM PDT 24
Finished Aug 16 04:24:52 PM PDT 24
Peak memory 164440 kb
Host smart-5c589fbc-3abb-466d-8b08-4484e3b9504b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=986797756 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.986797756
Directory /workspace/33.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.3694828028
Short name T163
Test name
Test status
Simulation time 1445410000 ps
CPU time 4.38 seconds
Started Aug 16 04:24:48 PM PDT 24
Finished Aug 16 04:24:58 PM PDT 24
Peak memory 164328 kb
Host smart-985b3ca5-8a20-419b-8143-4ebb97194264
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3694828028 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.3694828028
Directory /workspace/34.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.769644989
Short name T190
Test name
Test status
Simulation time 1435150000 ps
CPU time 2.88 seconds
Started Aug 16 04:24:39 PM PDT 24
Finished Aug 16 04:24:45 PM PDT 24
Peak memory 164468 kb
Host smart-97df1f83-2e42-4f0d-9160-e189d139cd46
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=769644989 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.769644989
Directory /workspace/35.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.1031089451
Short name T191
Test name
Test status
Simulation time 1517630000 ps
CPU time 2.96 seconds
Started Aug 16 04:24:38 PM PDT 24
Finished Aug 16 04:24:45 PM PDT 24
Peak memory 164492 kb
Host smart-d233a247-e842-41b6-b076-b44d4ac0ac94
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1031089451 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.1031089451
Directory /workspace/36.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1054147989
Short name T156
Test name
Test status
Simulation time 1324690000 ps
CPU time 3.5 seconds
Started Aug 16 04:24:43 PM PDT 24
Finished Aug 16 04:24:51 PM PDT 24
Peak memory 164372 kb
Host smart-ddb20394-2f43-4825-b29b-5958fca4ca19
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1054147989 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.1054147989
Directory /workspace/37.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.2473434871
Short name T159
Test name
Test status
Simulation time 1496690000 ps
CPU time 2.9 seconds
Started Aug 16 04:24:40 PM PDT 24
Finished Aug 16 04:24:47 PM PDT 24
Peak memory 164468 kb
Host smart-646999c0-2ff4-4b78-b32d-3bb61052082a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2473434871 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.2473434871
Directory /workspace/38.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.1215485468
Short name T193
Test name
Test status
Simulation time 1592150000 ps
CPU time 5.07 seconds
Started Aug 16 04:24:42 PM PDT 24
Finished Aug 16 04:24:53 PM PDT 24
Peak memory 164836 kb
Host smart-f1a41ada-1e68-4064-ae4b-293579528e8c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1215485468 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.1215485468
Directory /workspace/39.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.2711140743
Short name T167
Test name
Test status
Simulation time 1538190000 ps
CPU time 6.15 seconds
Started Aug 16 04:21:38 PM PDT 24
Finished Aug 16 04:21:51 PM PDT 24
Peak memory 164480 kb
Host smart-ded27ec9-3174-4d56-8f0a-30213307db00
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2711140743 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.2711140743
Directory /workspace/4.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.2238030635
Short name T182
Test name
Test status
Simulation time 1467870000 ps
CPU time 3.81 seconds
Started Aug 16 04:24:43 PM PDT 24
Finished Aug 16 04:24:52 PM PDT 24
Peak memory 164304 kb
Host smart-9a64f5d9-3ad6-4039-9eca-9f702e65ff0b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2238030635 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.2238030635
Directory /workspace/40.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.1700774201
Short name T168
Test name
Test status
Simulation time 1440650000 ps
CPU time 4.21 seconds
Started Aug 16 04:24:43 PM PDT 24
Finished Aug 16 04:24:53 PM PDT 24
Peak memory 164416 kb
Host smart-e3e71d84-c3cd-480e-9b65-e88c6cf0151c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1700774201 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.1700774201
Directory /workspace/41.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.2409770879
Short name T200
Test name
Test status
Simulation time 1420970000 ps
CPU time 2.94 seconds
Started Aug 16 04:24:42 PM PDT 24
Finished Aug 16 04:24:49 PM PDT 24
Peak memory 164516 kb
Host smart-79efde1a-3c53-4168-aed5-2635a9420862
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2409770879 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.2409770879
Directory /workspace/42.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.3820462002
Short name T177
Test name
Test status
Simulation time 1529350000 ps
CPU time 4.83 seconds
Started Aug 16 04:24:42 PM PDT 24
Finished Aug 16 04:24:53 PM PDT 24
Peak memory 165968 kb
Host smart-0129b277-e236-4ea5-9361-91b0ff73ad93
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3820462002 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.3820462002
Directory /workspace/43.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.3259943882
Short name T158
Test name
Test status
Simulation time 1368890000 ps
CPU time 2.73 seconds
Started Aug 16 04:24:38 PM PDT 24
Finished Aug 16 04:24:44 PM PDT 24
Peak memory 164492 kb
Host smart-c677d6b5-d9a1-452d-ba00-82b02b8e37ce
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3259943882 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.3259943882
Directory /workspace/44.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.1834698852
Short name T153
Test name
Test status
Simulation time 1630530000 ps
CPU time 6.42 seconds
Started Aug 16 04:24:39 PM PDT 24
Finished Aug 16 04:24:53 PM PDT 24
Peak memory 164948 kb
Host smart-36a1c899-7497-4b10-8c3d-be46bdfec707
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1834698852 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.1834698852
Directory /workspace/45.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.4033411868
Short name T192
Test name
Test status
Simulation time 1297650000 ps
CPU time 3.76 seconds
Started Aug 16 04:24:42 PM PDT 24
Finished Aug 16 04:24:51 PM PDT 24
Peak memory 164488 kb
Host smart-e40cf17b-cefe-4f8c-9e47-926e109993ea
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4033411868 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.4033411868
Directory /workspace/46.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.2990970308
Short name T194
Test name
Test status
Simulation time 1514970000 ps
CPU time 3.66 seconds
Started Aug 16 04:24:42 PM PDT 24
Finished Aug 16 04:24:51 PM PDT 24
Peak memory 164660 kb
Host smart-0689f647-34dd-4d09-b93f-091d7fddf467
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2990970308 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.2990970308
Directory /workspace/47.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.1317791801
Short name T183
Test name
Test status
Simulation time 1505050000 ps
CPU time 4.41 seconds
Started Aug 16 04:24:40 PM PDT 24
Finished Aug 16 04:24:49 PM PDT 24
Peak memory 164668 kb
Host smart-d449cbf3-6db1-4893-b703-649464945d9c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1317791801 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.1317791801
Directory /workspace/48.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.3285239206
Short name T164
Test name
Test status
Simulation time 1528510000 ps
CPU time 4.54 seconds
Started Aug 16 04:24:42 PM PDT 24
Finished Aug 16 04:24:53 PM PDT 24
Peak memory 165968 kb
Host smart-f043b47f-6c5d-4ada-af10-be569c33ad49
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3285239206 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.3285239206
Directory /workspace/49.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.3320766675
Short name T181
Test name
Test status
Simulation time 1475550000 ps
CPU time 4.86 seconds
Started Aug 16 04:19:19 PM PDT 24
Finished Aug 16 04:19:30 PM PDT 24
Peak memory 163716 kb
Host smart-8e09ce7e-3712-4d3b-8583-aba3a66ba736
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3320766675 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.3320766675
Directory /workspace/5.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.566329079
Short name T199
Test name
Test status
Simulation time 1398770000 ps
CPU time 4.74 seconds
Started Aug 16 04:19:56 PM PDT 24
Finished Aug 16 04:20:06 PM PDT 24
Peak memory 164888 kb
Host smart-05388a84-6314-462f-9b54-43d6f50b7440
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=566329079 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.566329079
Directory /workspace/6.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.796220056
Short name T173
Test name
Test status
Simulation time 1512170000 ps
CPU time 5.92 seconds
Started Aug 16 04:20:39 PM PDT 24
Finished Aug 16 04:20:52 PM PDT 24
Peak memory 164512 kb
Host smart-e2dc65e1-3cd3-4ee6-aa5c-6676dc998e8d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=796220056 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.796220056
Directory /workspace/7.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.851898485
Short name T157
Test name
Test status
Simulation time 1425210000 ps
CPU time 4.32 seconds
Started Aug 16 04:24:24 PM PDT 24
Finished Aug 16 04:24:34 PM PDT 24
Peak memory 162200 kb
Host smart-89ca60fc-92e6-49ec-ad77-40369d1496fd
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=851898485 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.851898485
Directory /workspace/8.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.3768237772
Short name T176
Test name
Test status
Simulation time 1430850000 ps
CPU time 4.22 seconds
Started Aug 16 04:21:26 PM PDT 24
Finished Aug 16 04:21:35 PM PDT 24
Peak memory 164652 kb
Host smart-f9a82c00-8f18-4522-bc00-8102d3e74c96
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3768237772 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.3768237772
Directory /workspace/9.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.2908135897
Short name T59
Test name
Test status
Simulation time 1330210000 ps
CPU time 4.37 seconds
Started Aug 16 04:20:34 PM PDT 24
Finished Aug 16 04:20:44 PM PDT 24
Peak memory 164412 kb
Host smart-18674599-93b9-459e-98dd-d47416e4ae81
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2908135897 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.2908135897
Directory /workspace/0.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.2297705437
Short name T33
Test name
Test status
Simulation time 1485690000 ps
CPU time 5.34 seconds
Started Aug 16 04:19:47 PM PDT 24
Finished Aug 16 04:20:00 PM PDT 24
Peak memory 163648 kb
Host smart-f0dae8e8-c173-4395-82e0-aeac83068410
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2297705437 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.2297705437
Directory /workspace/1.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.517151015
Short name T51
Test name
Test status
Simulation time 1288650000 ps
CPU time 4.45 seconds
Started Aug 16 04:19:42 PM PDT 24
Finished Aug 16 04:19:51 PM PDT 24
Peak memory 164652 kb
Host smart-d9578f86-a3a3-4122-8d03-46f78ebc50d5
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=517151015 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.517151015
Directory /workspace/10.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.3391410930
Short name T53
Test name
Test status
Simulation time 1516210000 ps
CPU time 5.04 seconds
Started Aug 16 04:20:13 PM PDT 24
Finished Aug 16 04:20:24 PM PDT 24
Peak memory 164492 kb
Host smart-8678ce9e-1089-4fe8-9d1f-daafe915d9f3
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3391410930 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.3391410930
Directory /workspace/11.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.3884819824
Short name T36
Test name
Test status
Simulation time 1488490000 ps
CPU time 4.8 seconds
Started Aug 16 04:20:34 PM PDT 24
Finished Aug 16 04:20:45 PM PDT 24
Peak memory 164484 kb
Host smart-30a8adde-c666-428f-bdfa-199d0acf9ee5
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3884819824 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.3884819824
Directory /workspace/12.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.1198655614
Short name T49
Test name
Test status
Simulation time 1346210000 ps
CPU time 4.4 seconds
Started Aug 16 04:20:50 PM PDT 24
Finished Aug 16 04:21:00 PM PDT 24
Peak memory 164836 kb
Host smart-daeab398-2dfe-4f1d-a61f-3e6ad44ede01
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1198655614 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.1198655614
Directory /workspace/13.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.238340957
Short name T62
Test name
Test status
Simulation time 1570870000 ps
CPU time 4.22 seconds
Started Aug 16 04:19:43 PM PDT 24
Finished Aug 16 04:19:53 PM PDT 24
Peak memory 163724 kb
Host smart-a7f81a56-c458-4913-942c-33ebb0fd9a55
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=238340957 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.238340957
Directory /workspace/15.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.1359056212
Short name T70
Test name
Test status
Simulation time 1456350000 ps
CPU time 5.09 seconds
Started Aug 16 04:20:51 PM PDT 24
Finished Aug 16 04:21:02 PM PDT 24
Peak memory 164736 kb
Host smart-bc1fba74-498e-4dce-8f17-e46314250de4
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1359056212 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.1359056212
Directory /workspace/16.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.1069050303
Short name T34
Test name
Test status
Simulation time 1439530000 ps
CPU time 4.05 seconds
Started Aug 16 04:22:54 PM PDT 24
Finished Aug 16 04:23:03 PM PDT 24
Peak memory 163200 kb
Host smart-3201f168-63a8-4fb8-93da-7cd9a20c55d4
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1069050303 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.1069050303
Directory /workspace/17.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.4240409606
Short name T37
Test name
Test status
Simulation time 1384530000 ps
CPU time 3.32 seconds
Started Aug 16 04:23:49 PM PDT 24
Finished Aug 16 04:23:56 PM PDT 24
Peak memory 164480 kb
Host smart-d4934b60-1199-498a-982b-55885f60c01a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4240409606 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.4240409606
Directory /workspace/18.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.1156242059
Short name T68
Test name
Test status
Simulation time 1296590000 ps
CPU time 4.16 seconds
Started Aug 16 04:20:55 PM PDT 24
Finished Aug 16 04:21:04 PM PDT 24
Peak memory 164772 kb
Host smart-6d1a2199-7f15-4e7f-b741-ad60474f9acf
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1156242059 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.1156242059
Directory /workspace/19.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.1210493990
Short name T40
Test name
Test status
Simulation time 1358850000 ps
CPU time 3.95 seconds
Started Aug 16 04:19:35 PM PDT 24
Finished Aug 16 04:19:44 PM PDT 24
Peak memory 162800 kb
Host smart-b2fea7d8-58b7-4994-a7b2-a5c7352d9e29
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1210493990 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.1210493990
Directory /workspace/2.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.2299109491
Short name T44
Test name
Test status
Simulation time 1411350000 ps
CPU time 4.69 seconds
Started Aug 16 04:21:12 PM PDT 24
Finished Aug 16 04:21:23 PM PDT 24
Peak memory 164480 kb
Host smart-f6377f05-dc7e-4541-9850-38cceea4c993
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2299109491 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.2299109491
Directory /workspace/20.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.977449731
Short name T9
Test name
Test status
Simulation time 1560350000 ps
CPU time 4.24 seconds
Started Aug 16 04:22:54 PM PDT 24
Finished Aug 16 04:23:04 PM PDT 24
Peak memory 163152 kb
Host smart-4ca0369a-31f4-464c-865e-47d595ba0f8e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=977449731 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.977449731
Directory /workspace/21.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.1358060773
Short name T43
Test name
Test status
Simulation time 1570150000 ps
CPU time 4.09 seconds
Started Aug 16 04:23:12 PM PDT 24
Finished Aug 16 04:23:22 PM PDT 24
Peak memory 162872 kb
Host smart-c4539d59-0286-450e-9c0d-0a4d24f31eea
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1358060773 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.1358060773
Directory /workspace/22.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.3017874223
Short name T55
Test name
Test status
Simulation time 1350990000 ps
CPU time 3.72 seconds
Started Aug 16 04:22:26 PM PDT 24
Finished Aug 16 04:22:34 PM PDT 24
Peak memory 164736 kb
Host smart-4e55d78e-341d-4fda-a5b6-a5384fe7d52e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3017874223 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.3017874223
Directory /workspace/23.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.338656560
Short name T48
Test name
Test status
Simulation time 1374150000 ps
CPU time 4.98 seconds
Started Aug 16 04:21:56 PM PDT 24
Finished Aug 16 04:22:07 PM PDT 24
Peak memory 164660 kb
Host smart-a99b890a-0090-416c-abf9-cfdffa8b03f4
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=338656560 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.338656560
Directory /workspace/24.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.3259763273
Short name T67
Test name
Test status
Simulation time 1337970000 ps
CPU time 4.82 seconds
Started Aug 16 04:22:08 PM PDT 24
Finished Aug 16 04:22:19 PM PDT 24
Peak memory 164668 kb
Host smart-66c18040-1847-4e06-9b04-61f1c015d43f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3259763273 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.3259763273
Directory /workspace/25.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.2601133424
Short name T60
Test name
Test status
Simulation time 1350630000 ps
CPU time 3.71 seconds
Started Aug 16 04:21:44 PM PDT 24
Finished Aug 16 04:21:52 PM PDT 24
Peak memory 164736 kb
Host smart-0b94593d-e9c8-4557-b455-955627bf9454
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2601133424 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.2601133424
Directory /workspace/26.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.2267165203
Short name T2
Test name
Test status
Simulation time 1597670000 ps
CPU time 4.24 seconds
Started Aug 16 04:22:54 PM PDT 24
Finished Aug 16 04:23:03 PM PDT 24
Peak memory 163736 kb
Host smart-ddc9c0f9-1964-4fc7-adb0-b7833066db26
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2267165203 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.2267165203
Directory /workspace/27.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.604363327
Short name T13
Test name
Test status
Simulation time 1476870000 ps
CPU time 5.53 seconds
Started Aug 16 04:22:20 PM PDT 24
Finished Aug 16 04:22:32 PM PDT 24
Peak memory 164848 kb
Host smart-d7c4bc4a-b4ab-49c2-9d88-282b7cacc980
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=604363327 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.604363327
Directory /workspace/28.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.3990062695
Short name T32
Test name
Test status
Simulation time 1376250000 ps
CPU time 3.37 seconds
Started Aug 16 04:23:57 PM PDT 24
Finished Aug 16 04:24:04 PM PDT 24
Peak memory 164480 kb
Host smart-b4b1d36e-f540-4270-ad79-9beae257f967
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3990062695 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.3990062695
Directory /workspace/29.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.2911129797
Short name T35
Test name
Test status
Simulation time 1266130000 ps
CPU time 4.22 seconds
Started Aug 16 04:19:48 PM PDT 24
Finished Aug 16 04:19:57 PM PDT 24
Peak memory 164440 kb
Host smart-340b5c14-5677-4ccc-9c25-82469084664a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2911129797 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.2911129797
Directory /workspace/3.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.3033058211
Short name T11
Test name
Test status
Simulation time 1297610000 ps
CPU time 3.91 seconds
Started Aug 16 04:24:33 PM PDT 24
Finished Aug 16 04:24:42 PM PDT 24
Peak memory 164936 kb
Host smart-0f7973c7-5f54-4a83-bfa9-8fc9cdff414b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3033058211 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.3033058211
Directory /workspace/30.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.1007804734
Short name T39
Test name
Test status
Simulation time 1334930000 ps
CPU time 3.62 seconds
Started Aug 16 04:24:32 PM PDT 24
Finished Aug 16 04:24:40 PM PDT 24
Peak memory 164772 kb
Host smart-488c994d-a3a2-43ad-bc25-dfb84305f252
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1007804734 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.1007804734
Directory /workspace/31.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.1147478783
Short name T57
Test name
Test status
Simulation time 1454110000 ps
CPU time 5.4 seconds
Started Aug 16 04:24:31 PM PDT 24
Finished Aug 16 04:24:44 PM PDT 24
Peak memory 164484 kb
Host smart-6881c724-7d1c-44a3-8627-9e09a9689320
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1147478783 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.1147478783
Directory /workspace/32.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.3954866534
Short name T47
Test name
Test status
Simulation time 1454650000 ps
CPU time 4.86 seconds
Started Aug 16 04:24:42 PM PDT 24
Finished Aug 16 04:24:53 PM PDT 24
Peak memory 164696 kb
Host smart-8653f09f-f10f-40a7-813f-371b5090e58f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3954866534 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.3954866534
Directory /workspace/33.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.664647
Short name T61
Test name
Test status
Simulation time 1638650000 ps
CPU time 5.28 seconds
Started Aug 16 04:24:42 PM PDT 24
Finished Aug 16 04:24:54 PM PDT 24
Peak memory 164692 kb
Host smart-31fbbc3c-e963-491a-9f6b-1d26a2dcf782
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=664647 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.664647
Directory /workspace/34.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.123383310
Short name T12
Test name
Test status
Simulation time 1530470000 ps
CPU time 3.8 seconds
Started Aug 16 04:24:31 PM PDT 24
Finished Aug 16 04:24:40 PM PDT 24
Peak memory 164620 kb
Host smart-106faa5e-51e4-452b-8861-672caa47f4d0
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=123383310 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.123383310
Directory /workspace/35.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.3125854019
Short name T52
Test name
Test status
Simulation time 1407310000 ps
CPU time 4.29 seconds
Started Aug 16 04:24:35 PM PDT 24
Finished Aug 16 04:24:45 PM PDT 24
Peak memory 164620 kb
Host smart-15f02f65-168b-4613-8df6-de5a81f60f1e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3125854019 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.3125854019
Directory /workspace/36.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.3849630345
Short name T65
Test name
Test status
Simulation time 1451750000 ps
CPU time 3.75 seconds
Started Aug 16 04:24:40 PM PDT 24
Finished Aug 16 04:24:49 PM PDT 24
Peak memory 164748 kb
Host smart-8a79db4e-18b5-4e7a-8d0d-fe753dc0e148
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3849630345 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.3849630345
Directory /workspace/37.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.2990885388
Short name T45
Test name
Test status
Simulation time 1542470000 ps
CPU time 5.37 seconds
Started Aug 16 04:24:40 PM PDT 24
Finished Aug 16 04:24:51 PM PDT 24
Peak memory 164620 kb
Host smart-fb1d81fd-6c54-4ac0-9750-223e2d7c87b8
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2990885388 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.2990885388
Directory /workspace/38.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.1542179828
Short name T54
Test name
Test status
Simulation time 1434030000 ps
CPU time 4.44 seconds
Started Aug 16 04:24:44 PM PDT 24
Finished Aug 16 04:24:54 PM PDT 24
Peak memory 164168 kb
Host smart-5adecd1b-d11f-4811-9db2-32b75100b454
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1542179828 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.1542179828
Directory /workspace/39.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.3227743529
Short name T58
Test name
Test status
Simulation time 1389030000 ps
CPU time 4.59 seconds
Started Aug 16 04:18:30 PM PDT 24
Finished Aug 16 04:18:40 PM PDT 24
Peak memory 164952 kb
Host smart-0911b893-b717-4cca-8caa-da13e7de2772
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3227743529 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.3227743529
Directory /workspace/4.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.2037149824
Short name T8
Test name
Test status
Simulation time 1560970000 ps
CPU time 4.26 seconds
Started Aug 16 04:24:40 PM PDT 24
Finished Aug 16 04:24:49 PM PDT 24
Peak memory 164668 kb
Host smart-63457044-311a-4f5c-ac72-e16b12d5e115
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2037149824 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.2037149824
Directory /workspace/40.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.378493611
Short name T50
Test name
Test status
Simulation time 1141470000 ps
CPU time 3.29 seconds
Started Aug 16 04:24:40 PM PDT 24
Finished Aug 16 04:24:47 PM PDT 24
Peak memory 164620 kb
Host smart-69a43113-7299-4431-b71c-350c053e959f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=378493611 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.378493611
Directory /workspace/41.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.2305113811
Short name T46
Test name
Test status
Simulation time 1476050000 ps
CPU time 4.03 seconds
Started Aug 16 04:24:42 PM PDT 24
Finished Aug 16 04:24:51 PM PDT 24
Peak memory 164476 kb
Host smart-4b735e11-c4c1-4002-8c5a-7a9a4c8951c1
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2305113811 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.2305113811
Directory /workspace/42.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.1616416781
Short name T31
Test name
Test status
Simulation time 1587910000 ps
CPU time 4.25 seconds
Started Aug 16 04:24:42 PM PDT 24
Finished Aug 16 04:24:52 PM PDT 24
Peak memory 164484 kb
Host smart-7ea3b92d-0873-4402-9e11-9ffad64bac11
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1616416781 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.1616416781
Directory /workspace/43.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.738384560
Short name T69
Test name
Test status
Simulation time 1424430000 ps
CPU time 5.07 seconds
Started Aug 16 04:24:41 PM PDT 24
Finished Aug 16 04:24:52 PM PDT 24
Peak memory 164660 kb
Host smart-be822567-8d9d-41fd-8973-719e0e3e6c54
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=738384560 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.738384560
Directory /workspace/44.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.2259253549
Short name T3
Test name
Test status
Simulation time 1534970000 ps
CPU time 4.72 seconds
Started Aug 16 04:24:44 PM PDT 24
Finished Aug 16 04:24:54 PM PDT 24
Peak memory 164252 kb
Host smart-5d66b65b-05db-46c0-a7a8-9c28ef9d1953
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2259253549 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.2259253549
Directory /workspace/45.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.3407567427
Short name T64
Test name
Test status
Simulation time 1585170000 ps
CPU time 5.47 seconds
Started Aug 16 04:24:42 PM PDT 24
Finished Aug 16 04:24:54 PM PDT 24
Peak memory 164640 kb
Host smart-2fc82319-4307-4210-a5ca-bb7005161e2a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3407567427 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.3407567427
Directory /workspace/46.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.4264834543
Short name T63
Test name
Test status
Simulation time 1549690000 ps
CPU time 4.83 seconds
Started Aug 16 04:24:44 PM PDT 24
Finished Aug 16 04:24:54 PM PDT 24
Peak memory 164640 kb
Host smart-ea081676-ec5b-446d-b1ce-4257cacb1e0e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4264834543 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.4264834543
Directory /workspace/47.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.1462200286
Short name T4
Test name
Test status
Simulation time 1497950000 ps
CPU time 5.87 seconds
Started Aug 16 04:24:41 PM PDT 24
Finished Aug 16 04:24:55 PM PDT 24
Peak memory 164484 kb
Host smart-da102d4e-67be-4f97-91fd-8600e5ded535
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1462200286 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.1462200286
Directory /workspace/48.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.3963437227
Short name T38
Test name
Test status
Simulation time 1541350000 ps
CPU time 5 seconds
Started Aug 16 04:24:41 PM PDT 24
Finished Aug 16 04:24:52 PM PDT 24
Peak memory 164580 kb
Host smart-5762584d-f8f5-4dac-b25b-27b343de9e15
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3963437227 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.3963437227
Directory /workspace/49.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.3890094518
Short name T56
Test name
Test status
Simulation time 1534270000 ps
CPU time 4.63 seconds
Started Aug 16 04:19:25 PM PDT 24
Finished Aug 16 04:19:35 PM PDT 24
Peak memory 164852 kb
Host smart-1d83b768-fd2a-4879-90a6-81d5cbde68ae
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3890094518 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.3890094518
Directory /workspace/5.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.3635889467
Short name T42
Test name
Test status
Simulation time 1517210000 ps
CPU time 5.55 seconds
Started Aug 16 04:19:47 PM PDT 24
Finished Aug 16 04:20:00 PM PDT 24
Peak memory 162704 kb
Host smart-e25f6cba-b3db-42a2-94a0-361e0ec77088
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3635889467 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.3635889467
Directory /workspace/6.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.814519030
Short name T41
Test name
Test status
Simulation time 1512690000 ps
CPU time 4.35 seconds
Started Aug 16 04:19:28 PM PDT 24
Finished Aug 16 04:19:38 PM PDT 24
Peak memory 164676 kb
Host smart-68eeccbf-11ce-49fe-a5a7-7cd3688ba473
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=814519030 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.814519030
Directory /workspace/7.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.1463721081
Short name T1
Test name
Test status
Simulation time 1410870000 ps
CPU time 4.27 seconds
Started Aug 16 04:19:35 PM PDT 24
Finished Aug 16 04:19:44 PM PDT 24
Peak memory 162420 kb
Host smart-3ccdb0bf-3e6e-4dd9-ac68-8f8207ed0171
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1463721081 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.1463721081
Directory /workspace/8.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.3493266779
Short name T66
Test name
Test status
Simulation time 1483630000 ps
CPU time 4.91 seconds
Started Aug 16 04:18:58 PM PDT 24
Finished Aug 16 04:19:09 PM PDT 24
Peak memory 164480 kb
Host smart-1c710045-c61d-4da5-943b-c15e38cf2203
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3493266779 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.3493266779
Directory /workspace/9.prim_lfsr_gal_smoke/latest
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