Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.31 100.00 96.55 100.00 100.00 95.00


Total tests in report: 200
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
87.31 87.31 100.00 100.00 96.55 96.55 100.00 100.00 100.00 100.00 40.00 40.00 /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.3447818649
95.31 8.00 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 80.00 40.00 /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.1769324834
98.31 3.00 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 95.00 15.00 /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.1963690327

Tests that do not contribute to grading

Name
/workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.1338810951
/workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.1301085067
/workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.3199681701
/workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.3165757946
/workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.562621997
/workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.3216855424
/workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.126747098
/workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.4242140358
/workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.2575948286
/workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.807936885
/workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.1493148176
/workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2596850922
/workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.529425932
/workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.4102975387
/workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.1536798823
/workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.178141196
/workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.1735812654
/workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.789823013
/workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.3408109618
/workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.2335236769
/workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.976282127
/workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.2060303012
/workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.2551067073
/workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.560178632
/workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.778212880
/workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.410449600
/workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.3855627747
/workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.546322235
/workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.1811760950
/workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.894903094
/workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.1088529189
/workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.435915706
/workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.2263645279
/workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.2400145532
/workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.2291187077
/workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.2049352838
/workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.296065445
/workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.2870196582
/workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.3354490495
/workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.122854272
/workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.2380420142
/workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.1068383009
/workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.4128844766
/workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.1175668724
/workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.3404279499
/workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.2857629187
/workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.3866771256
/workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1131917333
/workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.3842515754
/workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.1047938607
/workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.3507730204
/workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.3082541631
/workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.3226711814
/workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.1282694022
/workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.252054440
/workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.1859997561
/workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.1569413080
/workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.253522933
/workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.3932786206
/workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.1885985000
/workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.2189364360
/workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.3758978140
/workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.1233409608
/workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.1130159501
/workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.1251432158
/workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.3222222625
/workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.426276572
/workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.1233933604
/workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.1634852170
/workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.3820975188
/workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.2730173808
/workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.3901734654
/workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.2157078851
/workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.2487550382
/workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.352673998
/workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.2349572824
/workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.803242088
/workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.3516574522
/workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.2928372126
/workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.4178281693
/workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3277593727
/workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.3193674891
/workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.1579997285
/workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.3930618299
/workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.885604875
/workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.1743029025
/workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.4077021460
/workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.2140579392
/workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.4143490172
/workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.1169259531
/workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.1221871439
/workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.3385660157
/workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.2572466571
/workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.1455034123
/workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.1459730788
/workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.3758714620
/workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.1173968104
/workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.4114100293
/workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.4042249054
/workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.2468670396
/workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.2620271564
/workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.2420868979
/workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.1226628340
/workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.3742731794
/workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.2851939967
/workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.2717067231
/workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.1203666049
/workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.104584553
/workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.1847830076
/workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.100248776
/workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.2063882397
/workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.532924246
/workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.981769401
/workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.966879162
/workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.1242073255
/workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.1440283614
/workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.3758016133
/workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2611299514
/workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.3974970241
/workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.3372411847
/workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.518917456
/workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.1579659511
/workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.2206136006
/workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.551974403
/workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.3106916604
/workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.471482926
/workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.874460367
/workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.4197194301
/workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.166548153
/workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.294109544
/workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.2203114700
/workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.1068699261
/workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.1287896184
/workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.3284903597
/workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.3076230125
/workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.893377239
/workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1181301270
/workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.890453794
/workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.3145407083
/workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.230103394
/workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.2287778226
/workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.3768315597
/workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.2336742671
/workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.2300947197
/workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.1354866400
/workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.1469013277
/workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.254771431
/workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.968859366
/workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.2295317139
/workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.281540587
/workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.1322901764
/workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.4236808219
/workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.2944667692
/workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.938950711
/workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.1619063212
/workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.1255914292
/workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.3448486287
/workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.3471879537
/workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.498839812
/workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.3583859500
/workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.335070254
/workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.3227502879
/workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.2773809486
/workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.579846489
/workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.2936946046
/workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.4074951604
/workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.1364529935
/workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.1995203596
/workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.3396397694
/workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.2593002277
/workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.3763883101
/workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.167059515
/workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.3247489519
/workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.469055360
/workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.4293693913
/workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.3925311970
/workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.792818254
/workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.3768216579
/workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.1453452612
/workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.591106644
/workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.764979850
/workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.2496870082
/workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.3028714201
/workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.2041083340
/workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.2734207621
/workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.1066405664
/workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.1160921841
/workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.3041215179
/workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.666360397
/workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.934873799
/workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.3184692793
/workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.1459660744
/workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.4277994467
/workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.1567416461
/workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.2147754520
/workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.3598759664
/workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.3545574400



Total test records in report: 200
tests.html | tests1.html | tests2.html | tests3.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.498839812 Aug 17 04:49:58 PM PDT 24 Aug 17 04:50:09 PM PDT 24 1532610000 ps
T2 /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.4277994467 Aug 17 04:50:01 PM PDT 24 Aug 17 04:50:10 PM PDT 24 1364090000 ps
T3 /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.335070254 Aug 17 04:50:11 PM PDT 24 Aug 17 04:50:20 PM PDT 24 1434330000 ps
T7 /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.2773809486 Aug 17 04:50:04 PM PDT 24 Aug 17 04:50:12 PM PDT 24 1372810000 ps
T8 /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.2944667692 Aug 17 04:50:09 PM PDT 24 Aug 17 04:50:18 PM PDT 24 1476770000 ps
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T128 /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.1088529189 Aug 17 04:25:57 PM PDT 24 Aug 17 05:00:42 PM PDT 24 336860570000 ps
T129 /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.529425932 Aug 17 04:25:08 PM PDT 24 Aug 17 04:56:14 PM PDT 24 336720030000 ps
T130 /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.3866771256 Aug 17 04:22:32 PM PDT 24 Aug 17 04:57:18 PM PDT 24 336272810000 ps
T131 /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.1338810951 Aug 17 04:21:51 PM PDT 24 Aug 17 04:51:25 PM PDT 24 336702190000 ps
T132 /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.2870196582 Aug 17 04:24:56 PM PDT 24 Aug 17 04:51:48 PM PDT 24 336570250000 ps
T133 /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.2335236769 Aug 17 04:25:46 PM PDT 24 Aug 17 04:52:08 PM PDT 24 336499150000 ps
T134 /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.2857629187 Aug 17 04:23:16 PM PDT 24 Aug 17 04:53:52 PM PDT 24 336665210000 ps
T135 /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.4102975387 Aug 17 04:24:58 PM PDT 24 Aug 17 04:50:03 PM PDT 24 336546550000 ps
T136 /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.3354490495 Aug 17 04:22:32 PM PDT 24 Aug 17 04:54:31 PM PDT 24 336700050000 ps
T137 /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.1493148176 Aug 17 04:21:54 PM PDT 24 Aug 17 04:51:01 PM PDT 24 336812510000 ps
T138 /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.1301085067 Aug 17 04:24:56 PM PDT 24 Aug 17 04:50:19 PM PDT 24 336826810000 ps
T139 /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.410449600 Aug 17 04:25:46 PM PDT 24 Aug 17 04:58:38 PM PDT 24 337006430000 ps
T140 /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.894903094 Aug 17 04:23:43 PM PDT 24 Aug 17 04:58:21 PM PDT 24 337052690000 ps
T141 /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.2575948286 Aug 17 04:21:56 PM PDT 24 Aug 17 04:49:43 PM PDT 24 336735430000 ps
T142 /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.1068383009 Aug 17 04:23:33 PM PDT 24 Aug 17 04:53:55 PM PDT 24 336753690000 ps
T143 /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.4128844766 Aug 17 04:22:16 PM PDT 24 Aug 17 04:54:16 PM PDT 24 336386790000 ps
T144 /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.2380420142 Aug 17 04:22:05 PM PDT 24 Aug 17 04:50:37 PM PDT 24 336853350000 ps
T145 /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.3216855424 Aug 17 04:25:12 PM PDT 24 Aug 17 04:47:37 PM PDT 24 336706090000 ps
T146 /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.546322235 Aug 17 04:25:57 PM PDT 24 Aug 17 05:01:08 PM PDT 24 336677690000 ps
T147 /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.976282127 Aug 17 04:25:46 PM PDT 24 Aug 17 04:59:36 PM PDT 24 336983870000 ps
T148 /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.1735812654 Aug 17 04:21:53 PM PDT 24 Aug 17 04:49:23 PM PDT 24 336475750000 ps
T149 /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.560178632 Aug 17 04:25:51 PM PDT 24 Aug 17 04:52:21 PM PDT 24 337034170000 ps
T150 /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.3855627747 Aug 17 04:25:52 PM PDT 24 Aug 17 04:53:33 PM PDT 24 337054170000 ps
T151 /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.968859366 Aug 17 04:24:54 PM PDT 24 Aug 17 04:25:02 PM PDT 24 1543210000 ps
T152 /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.3106916604 Aug 17 04:25:47 PM PDT 24 Aug 17 04:25:55 PM PDT 24 1249130000 ps
T153 /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.1242073255 Aug 17 04:22:12 PM PDT 24 Aug 17 04:22:24 PM PDT 24 1538570000 ps
T154 /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.104584553 Aug 17 04:24:31 PM PDT 24 Aug 17 04:24:39 PM PDT 24 1485650000 ps
T155 /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.2287778226 Aug 17 04:25:59 PM PDT 24 Aug 17 04:26:08 PM PDT 24 1438190000 ps
T156 /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.2336742671 Aug 17 04:21:41 PM PDT 24 Aug 17 04:21:50 PM PDT 24 1462450000 ps
T157 /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.3974970241 Aug 17 04:25:51 PM PDT 24 Aug 17 04:25:59 PM PDT 24 1505870000 ps
T158 /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.166548153 Aug 17 04:24:17 PM PDT 24 Aug 17 04:24:26 PM PDT 24 1241430000 ps
T159 /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.2620271564 Aug 17 04:21:55 PM PDT 24 Aug 17 04:22:07 PM PDT 24 1523830000 ps
T160 /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.1203666049 Aug 17 04:24:58 PM PDT 24 Aug 17 04:25:09 PM PDT 24 1553750000 ps
T161 /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.981769401 Aug 17 04:25:48 PM PDT 24 Aug 17 04:25:57 PM PDT 24 1447250000 ps
T162 /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.518917456 Aug 17 04:25:59 PM PDT 24 Aug 17 04:26:12 PM PDT 24 1560770000 ps
T163 /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.2206136006 Aug 17 04:26:00 PM PDT 24 Aug 17 04:26:10 PM PDT 24 1289850000 ps
T164 /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.100248776 Aug 17 04:26:00 PM PDT 24 Aug 17 04:26:07 PM PDT 24 1472870000 ps
T165 /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.874460367 Aug 17 04:21:14 PM PDT 24 Aug 17 04:21:23 PM PDT 24 1291870000 ps
T166 /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.551974403 Aug 17 04:25:27 PM PDT 24 Aug 17 04:25:35 PM PDT 24 1448170000 ps
T167 /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.966879162 Aug 17 04:24:58 PM PDT 24 Aug 17 04:25:09 PM PDT 24 1524970000 ps
T168 /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.3758016133 Aug 17 04:25:45 PM PDT 24 Aug 17 04:25:54 PM PDT 24 1344210000 ps
T169 /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.2063882397 Aug 17 04:24:56 PM PDT 24 Aug 17 04:25:03 PM PDT 24 1312890000 ps
T170 /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.1469013277 Aug 17 04:25:47 PM PDT 24 Aug 17 04:25:53 PM PDT 24 1225370000 ps
T171 /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.3768315597 Aug 17 04:25:46 PM PDT 24 Aug 17 04:25:55 PM PDT 24 1555050000 ps
T172 /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.471482926 Aug 17 04:25:37 PM PDT 24 Aug 17 04:25:46 PM PDT 24 1533650000 ps
T173 /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.1287896184 Aug 17 04:25:11 PM PDT 24 Aug 17 04:25:21 PM PDT 24 1494690000 ps
T174 /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.4197194301 Aug 17 04:25:48 PM PDT 24 Aug 17 04:25:56 PM PDT 24 1496770000 ps
T175 /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.2851939967 Aug 17 04:24:17 PM PDT 24 Aug 17 04:24:27 PM PDT 24 1385170000 ps
T176 /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.294109544 Aug 17 04:21:24 PM PDT 24 Aug 17 04:21:34 PM PDT 24 1289090000 ps
T177 /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.1068699261 Aug 17 04:25:04 PM PDT 24 Aug 17 04:25:15 PM PDT 24 1535130000 ps
T178 /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.3742731794 Aug 17 04:24:48 PM PDT 24 Aug 17 04:24:57 PM PDT 24 1431170000 ps
T179 /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.2468670396 Aug 17 04:21:54 PM PDT 24 Aug 17 04:22:04 PM PDT 24 1494310000 ps
T180 /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.3145407083 Aug 17 04:26:04 PM PDT 24 Aug 17 04:26:13 PM PDT 24 1544050000 ps
T181 /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.1226628340 Aug 17 04:25:12 PM PDT 24 Aug 17 04:25:22 PM PDT 24 1514810000 ps
T182 /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.1847830076 Aug 17 04:25:48 PM PDT 24 Aug 17 04:25:57 PM PDT 24 1586910000 ps
T183 /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.3372411847 Aug 17 04:21:43 PM PDT 24 Aug 17 04:21:52 PM PDT 24 1231930000 ps
T184 /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1181301270 Aug 17 04:25:03 PM PDT 24 Aug 17 04:25:13 PM PDT 24 1547710000 ps
T185 /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.1579659511 Aug 17 04:24:55 PM PDT 24 Aug 17 04:25:04 PM PDT 24 1506870000 ps
T186 /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.3076230125 Aug 17 04:24:35 PM PDT 24 Aug 17 04:24:44 PM PDT 24 1489530000 ps
T187 /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.1440283614 Aug 17 04:24:17 PM PDT 24 Aug 17 04:24:28 PM PDT 24 1555930000 ps
T188 /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2611299514 Aug 17 04:21:56 PM PDT 24 Aug 17 04:22:07 PM PDT 24 1379430000 ps
T189 /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.2717067231 Aug 17 04:24:58 PM PDT 24 Aug 17 04:25:07 PM PDT 24 1396970000 ps
T190 /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.2300947197 Aug 17 04:22:05 PM PDT 24 Aug 17 04:22:14 PM PDT 24 1361190000 ps
T191 /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.254771431 Aug 17 04:24:48 PM PDT 24 Aug 17 04:24:56 PM PDT 24 1411890000 ps
T192 /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.2203114700 Aug 17 04:24:54 PM PDT 24 Aug 17 04:25:02 PM PDT 24 1338750000 ps
T193 /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.4042249054 Aug 17 04:24:55 PM PDT 24 Aug 17 04:25:02 PM PDT 24 1073270000 ps
T194 /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.3284903597 Aug 17 04:22:33 PM PDT 24 Aug 17 04:22:42 PM PDT 24 1576510000 ps
T195 /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.2420868979 Aug 17 04:25:47 PM PDT 24 Aug 17 04:25:55 PM PDT 24 1546950000 ps
T196 /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.890453794 Aug 17 04:24:54 PM PDT 24 Aug 17 04:25:02 PM PDT 24 1282230000 ps
T197 /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.230103394 Aug 17 04:25:08 PM PDT 24 Aug 17 04:25:16 PM PDT 24 1517770000 ps
T198 /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.893377239 Aug 17 04:24:36 PM PDT 24 Aug 17 04:24:48 PM PDT 24 1528850000 ps
T199 /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.532924246 Aug 17 04:26:01 PM PDT 24 Aug 17 04:26:10 PM PDT 24 1467190000 ps
T200 /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.1354866400 Aug 17 04:22:55 PM PDT 24 Aug 17 04:23:03 PM PDT 24 1155730000 ps

Test location /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.3447818649
Short name T12
Test name
Test status
Simulation time 1575730000 ps
CPU time 4.36 seconds
Started Aug 17 04:50:01 PM PDT 24
Finished Aug 17 04:50:11 PM PDT 24
Peak memory 164820 kb
Host smart-926bc9b4-67b6-447f-af50-bd63d0cb26c6
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3447818649 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.3447818649
Directory /workspace/1.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.1769324834
Short name T14
Test name
Test status
Simulation time 336416970000 ps
CPU time 748.39 seconds
Started Aug 17 04:49:15 PM PDT 24
Finished Aug 17 05:19:27 PM PDT 24
Peak memory 160792 kb
Host smart-3b075efc-be97-4ed6-b42a-7ac6de5bfc39
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1769324834 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.1769324834
Directory /workspace/2.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.1963690327
Short name T29
Test name
Test status
Simulation time 336426970000 ps
CPU time 624.46 seconds
Started Aug 17 04:25:32 PM PDT 24
Finished Aug 17 04:51:17 PM PDT 24
Peak memory 160268 kb
Host smart-52770940-b341-4422-8ab3-f9a5c304eddb
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1963690327 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.1963690327
Directory /workspace/20.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.1338810951
Short name T131
Test name
Test status
Simulation time 336702190000 ps
CPU time 721.47 seconds
Started Aug 17 04:21:51 PM PDT 24
Finished Aug 17 04:51:25 PM PDT 24
Peak memory 160904 kb
Host smart-88c0e760-7268-431b-adbc-9eb718ab712d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1338810951 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.1338810951
Directory /workspace/0.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.1301085067
Short name T138
Test name
Test status
Simulation time 336826810000 ps
CPU time 614.52 seconds
Started Aug 17 04:24:56 PM PDT 24
Finished Aug 17 04:50:19 PM PDT 24
Peak memory 159552 kb
Host smart-7e97cd65-b045-4979-98e0-3c82137167aa
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1301085067 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.1301085067
Directory /workspace/1.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.3199681701
Short name T124
Test name
Test status
Simulation time 336703270000 ps
CPU time 868.91 seconds
Started Aug 17 04:22:46 PM PDT 24
Finished Aug 17 04:58:19 PM PDT 24
Peak memory 160584 kb
Host smart-eb72ed34-b688-4f96-a14a-d0c91542418a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3199681701 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.3199681701
Directory /workspace/10.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.3165757946
Short name T121
Test name
Test status
Simulation time 336954490000 ps
CPU time 613.96 seconds
Started Aug 17 04:24:56 PM PDT 24
Finished Aug 17 04:50:08 PM PDT 24
Peak memory 159524 kb
Host smart-1c9b3aa0-bdf4-433d-887e-9962eb27b302
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3165757946 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.3165757946
Directory /workspace/11.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.562621997
Short name T122
Test name
Test status
Simulation time 337053970000 ps
CPU time 791.73 seconds
Started Aug 17 04:23:16 PM PDT 24
Finished Aug 17 04:55:24 PM PDT 24
Peak memory 160620 kb
Host smart-8fc00d35-c6c1-45dc-9acc-6f09675d0c37
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=562621997 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.562621997
Directory /workspace/12.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.3216855424
Short name T145
Test name
Test status
Simulation time 336706090000 ps
CPU time 524.04 seconds
Started Aug 17 04:25:12 PM PDT 24
Finished Aug 17 04:47:37 PM PDT 24
Peak memory 160448 kb
Host smart-4be48850-066a-4193-8c40-0e6c0c2ac107
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3216855424 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.3216855424
Directory /workspace/13.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.126747098
Short name T112
Test name
Test status
Simulation time 336676630000 ps
CPU time 759.2 seconds
Started Aug 17 04:23:17 PM PDT 24
Finished Aug 17 04:54:23 PM PDT 24
Peak memory 160656 kb
Host smart-383b50ce-1443-4664-bc1b-4d6cd667b320
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=126747098 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.126747098
Directory /workspace/14.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.4242140358
Short name T125
Test name
Test status
Simulation time 336415590000 ps
CPU time 589.83 seconds
Started Aug 17 04:24:58 PM PDT 24
Finished Aug 17 04:49:37 PM PDT 24
Peak memory 159636 kb
Host smart-56f4d549-05c9-4afb-8146-69bbe9d97c8e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4242140358 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.4242140358
Directory /workspace/15.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.2575948286
Short name T141
Test name
Test status
Simulation time 336735430000 ps
CPU time 671.26 seconds
Started Aug 17 04:21:56 PM PDT 24
Finished Aug 17 04:49:43 PM PDT 24
Peak memory 160644 kb
Host smart-2d344d30-6d36-452c-a351-cd91ab49148a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2575948286 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.2575948286
Directory /workspace/16.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.807936885
Short name T118
Test name
Test status
Simulation time 336998810000 ps
CPU time 738.3 seconds
Started Aug 17 04:25:05 PM PDT 24
Finished Aug 17 04:55:21 PM PDT 24
Peak memory 160564 kb
Host smart-bfc8efae-c8e6-4a9d-9757-7533ede4970f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=807936885 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.807936885
Directory /workspace/17.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.1493148176
Short name T137
Test name
Test status
Simulation time 336812510000 ps
CPU time 710.37 seconds
Started Aug 17 04:21:54 PM PDT 24
Finished Aug 17 04:51:01 PM PDT 24
Peak memory 160664 kb
Host smart-79eaa2d3-fd25-4178-b7a7-6f8e3fca4007
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1493148176 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.1493148176
Directory /workspace/18.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2596850922
Short name T117
Test name
Test status
Simulation time 336622890000 ps
CPU time 673.35 seconds
Started Aug 17 04:23:50 PM PDT 24
Finished Aug 17 04:51:29 PM PDT 24
Peak memory 160628 kb
Host smart-21b7f757-6983-4526-b26f-699103f6affd
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2596850922 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.2596850922
Directory /workspace/19.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.529425932
Short name T129
Test name
Test status
Simulation time 336720030000 ps
CPU time 755.04 seconds
Started Aug 17 04:25:08 PM PDT 24
Finished Aug 17 04:56:14 PM PDT 24
Peak memory 160440 kb
Host smart-83215022-1d10-4453-91a8-c372dfc59d39
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=529425932 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.529425932
Directory /workspace/2.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.4102975387
Short name T135
Test name
Test status
Simulation time 336546550000 ps
CPU time 604.66 seconds
Started Aug 17 04:24:58 PM PDT 24
Finished Aug 17 04:50:03 PM PDT 24
Peak memory 160368 kb
Host smart-e8b47424-0551-4d69-be97-0139cc75e3a4
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4102975387 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.4102975387
Directory /workspace/21.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.1536798823
Short name T5
Test name
Test status
Simulation time 336347510000 ps
CPU time 857.55 seconds
Started Aug 17 04:21:18 PM PDT 24
Finished Aug 17 04:56:00 PM PDT 24
Peak memory 160528 kb
Host smart-cbcf8754-1afb-4dbe-92e9-01c6d71deb98
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1536798823 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.1536798823
Directory /workspace/22.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.178141196
Short name T119
Test name
Test status
Simulation time 336936330000 ps
CPU time 647.72 seconds
Started Aug 17 04:25:29 PM PDT 24
Finished Aug 17 04:51:37 PM PDT 24
Peak memory 159740 kb
Host smart-62a13bf1-666d-41eb-b574-430c33be9c78
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=178141196 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.178141196
Directory /workspace/23.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.1735812654
Short name T148
Test name
Test status
Simulation time 336475750000 ps
CPU time 676.49 seconds
Started Aug 17 04:21:53 PM PDT 24
Finished Aug 17 04:49:23 PM PDT 24
Peak memory 160552 kb
Host smart-afe26734-535b-4735-abe4-bc745ebcdb1f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1735812654 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.1735812654
Directory /workspace/24.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.789823013
Short name T30
Test name
Test status
Simulation time 337118310000 ps
CPU time 788.1 seconds
Started Aug 17 04:25:47 PM PDT 24
Finished Aug 17 04:58:59 PM PDT 24
Peak memory 160200 kb
Host smart-a39927a5-33e0-4bc6-b923-7d1f4cba16d2
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=789823013 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.789823013
Directory /workspace/25.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.3408109618
Short name T6
Test name
Test status
Simulation time 337060790000 ps
CPU time 659.17 seconds
Started Aug 17 04:25:46 PM PDT 24
Finished Aug 17 04:52:46 PM PDT 24
Peak memory 160336 kb
Host smart-7b9b5f16-f5cb-48c5-9b43-4fa62f7364ad
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3408109618 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.3408109618
Directory /workspace/26.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.2335236769
Short name T133
Test name
Test status
Simulation time 336499150000 ps
CPU time 649.97 seconds
Started Aug 17 04:25:46 PM PDT 24
Finished Aug 17 04:52:08 PM PDT 24
Peak memory 160268 kb
Host smart-c866871f-ccb3-4ac6-a7b2-0424c6ff40ac
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2335236769 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.2335236769
Directory /workspace/27.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.976282127
Short name T147
Test name
Test status
Simulation time 336983870000 ps
CPU time 805.62 seconds
Started Aug 17 04:25:46 PM PDT 24
Finished Aug 17 04:59:36 PM PDT 24
Peak memory 159352 kb
Host smart-df15669f-c69b-4e8e-a836-63731d84faad
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=976282127 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.976282127
Directory /workspace/28.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.2060303012
Short name T25
Test name
Test status
Simulation time 336992970000 ps
CPU time 799.9 seconds
Started Aug 17 04:25:46 PM PDT 24
Finished Aug 17 04:59:32 PM PDT 24
Peak memory 159304 kb
Host smart-429cd1f6-c4dc-49b8-b2ea-ca56718c9fcf
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2060303012 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.2060303012
Directory /workspace/29.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.2551067073
Short name T28
Test name
Test status
Simulation time 336630550000 ps
CPU time 713.06 seconds
Started Aug 17 04:23:13 PM PDT 24
Finished Aug 17 04:52:22 PM PDT 24
Peak memory 160616 kb
Host smart-c658eb9d-798c-4093-a7af-9a80fa696db1
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2551067073 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.2551067073
Directory /workspace/3.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.560178632
Short name T149
Test name
Test status
Simulation time 337034170000 ps
CPU time 649.29 seconds
Started Aug 17 04:25:51 PM PDT 24
Finished Aug 17 04:52:21 PM PDT 24
Peak memory 160348 kb
Host smart-c84fea2c-8ec5-4f6a-81e3-8dd5042135c9
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=560178632 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.560178632
Directory /workspace/30.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.778212880
Short name T113
Test name
Test status
Simulation time 336861730000 ps
CPU time 741.25 seconds
Started Aug 17 04:24:24 PM PDT 24
Finished Aug 17 04:54:35 PM PDT 24
Peak memory 160656 kb
Host smart-eca1f667-5b6a-46ee-8cad-3c6f18d9bc24
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=778212880 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.778212880
Directory /workspace/31.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.410449600
Short name T139
Test name
Test status
Simulation time 337006430000 ps
CPU time 796.07 seconds
Started Aug 17 04:25:46 PM PDT 24
Finished Aug 17 04:58:38 PM PDT 24
Peak memory 160344 kb
Host smart-04a26b3d-0a34-478d-ad9d-a30a98e8b40c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=410449600 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.410449600
Directory /workspace/32.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.3855627747
Short name T150
Test name
Test status
Simulation time 337054170000 ps
CPU time 660.26 seconds
Started Aug 17 04:25:52 PM PDT 24
Finished Aug 17 04:53:33 PM PDT 24
Peak memory 159764 kb
Host smart-b1d7d29e-4182-4b92-a37d-7a796891694c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3855627747 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.3855627747
Directory /workspace/33.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.546322235
Short name T146
Test name
Test status
Simulation time 336677690000 ps
CPU time 855.27 seconds
Started Aug 17 04:25:57 PM PDT 24
Finished Aug 17 05:01:08 PM PDT 24
Peak memory 160496 kb
Host smart-e125ff25-d1a7-4e1e-9b64-e8282da175ae
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=546322235 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.546322235
Directory /workspace/34.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.1811760950
Short name T115
Test name
Test status
Simulation time 336799510000 ps
CPU time 608.69 seconds
Started Aug 17 04:25:47 PM PDT 24
Finished Aug 17 04:50:37 PM PDT 24
Peak memory 160372 kb
Host smart-ac003582-35ce-4379-8006-23b0e764e38c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1811760950 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.1811760950
Directory /workspace/35.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.894903094
Short name T140
Test name
Test status
Simulation time 337052690000 ps
CPU time 840.41 seconds
Started Aug 17 04:23:43 PM PDT 24
Finished Aug 17 04:58:21 PM PDT 24
Peak memory 160664 kb
Host smart-8ca6d028-8ac4-485c-a049-222564edd080
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=894903094 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.894903094
Directory /workspace/36.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.1088529189
Short name T128
Test name
Test status
Simulation time 336860570000 ps
CPU time 842.13 seconds
Started Aug 17 04:25:57 PM PDT 24
Finished Aug 17 05:00:42 PM PDT 24
Peak memory 160512 kb
Host smart-6a3dff1e-c618-4165-ac2d-321e81291744
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1088529189 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.1088529189
Directory /workspace/37.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.435915706
Short name T120
Test name
Test status
Simulation time 336486210000 ps
CPU time 665.76 seconds
Started Aug 17 04:25:03 PM PDT 24
Finished Aug 17 04:51:57 PM PDT 24
Peak memory 160320 kb
Host smart-8c72d9f5-a030-4797-9a22-db167a3f0769
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=435915706 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.435915706
Directory /workspace/38.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.2263645279
Short name T111
Test name
Test status
Simulation time 336973750000 ps
CPU time 606.66 seconds
Started Aug 17 04:25:47 PM PDT 24
Finished Aug 17 04:50:47 PM PDT 24
Peak memory 159520 kb
Host smart-7b951997-2fc8-486f-a10e-5d3bfa466e04
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2263645279 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.2263645279
Directory /workspace/39.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.2400145532
Short name T24
Test name
Test status
Simulation time 336513790000 ps
CPU time 837.43 seconds
Started Aug 17 04:22:55 PM PDT 24
Finished Aug 17 04:57:28 PM PDT 24
Peak memory 160676 kb
Host smart-7db80bec-4c61-4a4b-b589-1c58f6bf74e6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2400145532 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.2400145532
Directory /workspace/4.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.2291187077
Short name T127
Test name
Test status
Simulation time 336879310000 ps
CPU time 758.22 seconds
Started Aug 17 04:21:03 PM PDT 24
Finished Aug 17 04:51:48 PM PDT 24
Peak memory 160584 kb
Host smart-be7e8ecb-e879-455a-83d1-082c6f34f326
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2291187077 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.2291187077
Directory /workspace/40.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.2049352838
Short name T4
Test name
Test status
Simulation time 336676910000 ps
CPU time 705.95 seconds
Started Aug 17 04:26:07 PM PDT 24
Finished Aug 17 04:54:52 PM PDT 24
Peak memory 160368 kb
Host smart-9136a86b-d587-4323-a47a-0eeb536c0c7e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2049352838 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.2049352838
Directory /workspace/41.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.296065445
Short name T123
Test name
Test status
Simulation time 336715870000 ps
CPU time 657.31 seconds
Started Aug 17 04:24:54 PM PDT 24
Finished Aug 17 04:51:46 PM PDT 24
Peak memory 160252 kb
Host smart-587b5017-f666-446e-9034-6839cb2e09de
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=296065445 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.296065445
Directory /workspace/42.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.2870196582
Short name T132
Test name
Test status
Simulation time 336570250000 ps
CPU time 648.26 seconds
Started Aug 17 04:24:56 PM PDT 24
Finished Aug 17 04:51:48 PM PDT 24
Peak memory 160588 kb
Host smart-5cb35b30-2528-4686-a91c-14dce136d83b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2870196582 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.2870196582
Directory /workspace/43.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.3354490495
Short name T136
Test name
Test status
Simulation time 336700050000 ps
CPU time 785.61 seconds
Started Aug 17 04:22:32 PM PDT 24
Finished Aug 17 04:54:31 PM PDT 24
Peak memory 160592 kb
Host smart-6bcf574c-aa70-493d-9f07-30ca5a67c79e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3354490495 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.3354490495
Directory /workspace/44.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.122854272
Short name T27
Test name
Test status
Simulation time 337036470000 ps
CPU time 588.3 seconds
Started Aug 17 04:24:17 PM PDT 24
Finished Aug 17 04:48:51 PM PDT 24
Peak memory 160600 kb
Host smart-5a3dcaa7-3cc4-4b2f-a765-ffa5200146d5
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=122854272 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.122854272
Directory /workspace/45.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.2380420142
Short name T144
Test name
Test status
Simulation time 336853350000 ps
CPU time 703.08 seconds
Started Aug 17 04:22:05 PM PDT 24
Finished Aug 17 04:50:37 PM PDT 24
Peak memory 160644 kb
Host smart-b1cc8977-1779-4db0-a94d-9a6ed922fcd1
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2380420142 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.2380420142
Directory /workspace/46.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.1068383009
Short name T142
Test name
Test status
Simulation time 336753690000 ps
CPU time 743.8 seconds
Started Aug 17 04:23:33 PM PDT 24
Finished Aug 17 04:53:55 PM PDT 24
Peak memory 160588 kb
Host smart-f0416a94-51b3-4ce8-a0a9-2030bd33aba4
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1068383009 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.1068383009
Directory /workspace/47.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.4128844766
Short name T143
Test name
Test status
Simulation time 336386790000 ps
CPU time 789.29 seconds
Started Aug 17 04:22:16 PM PDT 24
Finished Aug 17 04:54:16 PM PDT 24
Peak memory 160588 kb
Host smart-4acc5579-cc22-4a2c-a1af-37e8433f4ec8
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4128844766 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.4128844766
Directory /workspace/48.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.1175668724
Short name T116
Test name
Test status
Simulation time 336891650000 ps
CPU time 705.76 seconds
Started Aug 17 04:24:54 PM PDT 24
Finished Aug 17 04:53:43 PM PDT 24
Peak memory 159652 kb
Host smart-18bcdeb3-b35f-4b50-a66d-90958a0f3776
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1175668724 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.1175668724
Directory /workspace/49.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.3404279499
Short name T114
Test name
Test status
Simulation time 336818870000 ps
CPU time 642.09 seconds
Started Aug 17 04:25:10 PM PDT 24
Finished Aug 17 04:52:07 PM PDT 24
Peak memory 160396 kb
Host smart-12ff31fb-e7cc-47e2-9ad5-c635f15c9157
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3404279499 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.3404279499
Directory /workspace/5.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.2857629187
Short name T134
Test name
Test status
Simulation time 336665210000 ps
CPU time 742.65 seconds
Started Aug 17 04:23:16 PM PDT 24
Finished Aug 17 04:53:52 PM PDT 24
Peak memory 160616 kb
Host smart-2bbbafb5-88e7-4d00-81d3-a58b6fc4f945
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2857629187 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.2857629187
Directory /workspace/6.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.3866771256
Short name T130
Test name
Test status
Simulation time 336272810000 ps
CPU time 849.9 seconds
Started Aug 17 04:22:32 PM PDT 24
Finished Aug 17 04:57:18 PM PDT 24
Peak memory 160564 kb
Host smart-9204935a-ba80-4d87-9cc6-1975aecc686a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3866771256 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.3866771256
Directory /workspace/7.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1131917333
Short name T26
Test name
Test status
Simulation time 336393890000 ps
CPU time 836.55 seconds
Started Aug 17 04:23:15 PM PDT 24
Finished Aug 17 04:58:02 PM PDT 24
Peak memory 160676 kb
Host smart-e365dca3-fd8d-4f1d-b6b2-ea74384da4ce
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1131917333 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.1131917333
Directory /workspace/8.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.3842515754
Short name T126
Test name
Test status
Simulation time 336516290000 ps
CPU time 672.81 seconds
Started Aug 17 04:24:48 PM PDT 24
Finished Aug 17 04:52:18 PM PDT 24
Peak memory 159476 kb
Host smart-4df0f540-523d-418c-b725-752e7495de2f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3842515754 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.3842515754
Directory /workspace/9.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.1047938607
Short name T96
Test name
Test status
Simulation time 336491870000 ps
CPU time 805.59 seconds
Started Aug 17 04:49:12 PM PDT 24
Finished Aug 17 05:22:38 PM PDT 24
Peak memory 160720 kb
Host smart-6935b4b6-4083-4cf9-a7af-e641eca5d0db
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1047938607 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.1047938607
Directory /workspace/0.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.3507730204
Short name T100
Test name
Test status
Simulation time 336437010000 ps
CPU time 832.67 seconds
Started Aug 17 04:49:12 PM PDT 24
Finished Aug 17 05:23:27 PM PDT 24
Peak memory 160728 kb
Host smart-840f912e-2866-43a1-8db2-51065a0ebaff
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3507730204 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.3507730204
Directory /workspace/1.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.3082541631
Short name T82
Test name
Test status
Simulation time 336389010000 ps
CPU time 683.9 seconds
Started Aug 17 04:49:10 PM PDT 24
Finished Aug 17 05:17:22 PM PDT 24
Peak memory 160752 kb
Host smart-0f59e7db-d55b-4874-bfc5-a24dcf3f6f93
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3082541631 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.3082541631
Directory /workspace/10.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.3226711814
Short name T90
Test name
Test status
Simulation time 336582690000 ps
CPU time 746.37 seconds
Started Aug 17 04:49:15 PM PDT 24
Finished Aug 17 05:19:37 PM PDT 24
Peak memory 160688 kb
Host smart-e626b0fc-70f7-489f-a0c0-4c8072a88011
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3226711814 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.3226711814
Directory /workspace/11.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.1282694022
Short name T87
Test name
Test status
Simulation time 336323470000 ps
CPU time 843.98 seconds
Started Aug 17 04:49:12 PM PDT 24
Finished Aug 17 05:23:59 PM PDT 24
Peak memory 160792 kb
Host smart-1ca2cf64-dd14-4fdd-8488-eb400ad670be
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1282694022 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.1282694022
Directory /workspace/12.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.252054440
Short name T72
Test name
Test status
Simulation time 336456610000 ps
CPU time 729.75 seconds
Started Aug 17 04:49:13 PM PDT 24
Finished Aug 17 05:19:22 PM PDT 24
Peak memory 160736 kb
Host smart-17df74a5-8f79-41d5-beae-16d91fad9bbb
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=252054440 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.252054440
Directory /workspace/13.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.1859997561
Short name T92
Test name
Test status
Simulation time 336736750000 ps
CPU time 942.23 seconds
Started Aug 17 04:49:13 PM PDT 24
Finished Aug 17 05:27:22 PM PDT 24
Peak memory 160656 kb
Host smart-13ef29d8-a68e-430e-9b7a-54413d3eb067
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1859997561 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.1859997561
Directory /workspace/14.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.1569413080
Short name T93
Test name
Test status
Simulation time 336629690000 ps
CPU time 793.17 seconds
Started Aug 17 04:49:14 PM PDT 24
Finished Aug 17 05:21:55 PM PDT 24
Peak memory 160760 kb
Host smart-251d6e1f-00cf-4227-8a4a-40f0f2b70b7d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1569413080 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.1569413080
Directory /workspace/15.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.253522933
Short name T101
Test name
Test status
Simulation time 337077510000 ps
CPU time 798.54 seconds
Started Aug 17 04:49:16 PM PDT 24
Finished Aug 17 05:22:34 PM PDT 24
Peak memory 160724 kb
Host smart-6a982a76-a54b-457a-a4c6-7b6cf203eaa2
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=253522933 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.253522933
Directory /workspace/16.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.3932786206
Short name T85
Test name
Test status
Simulation time 336662550000 ps
CPU time 834.45 seconds
Started Aug 17 04:49:12 PM PDT 24
Finished Aug 17 05:23:25 PM PDT 24
Peak memory 160748 kb
Host smart-d919ef42-9253-4edc-a1a1-220b298adbbd
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3932786206 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.3932786206
Directory /workspace/17.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.1885985000
Short name T95
Test name
Test status
Simulation time 336348850000 ps
CPU time 742.96 seconds
Started Aug 17 04:49:14 PM PDT 24
Finished Aug 17 05:19:36 PM PDT 24
Peak memory 160744 kb
Host smart-11450ea5-efc9-4289-9773-063e9271c3a3
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1885985000 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.1885985000
Directory /workspace/18.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.2189364360
Short name T79
Test name
Test status
Simulation time 336618630000 ps
CPU time 783.33 seconds
Started Aug 17 04:49:17 PM PDT 24
Finished Aug 17 05:21:16 PM PDT 24
Peak memory 160796 kb
Host smart-fcdcaedb-c53e-4846-bbc6-6d195cd0cb2b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2189364360 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.2189364360
Directory /workspace/19.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.3758978140
Short name T20
Test name
Test status
Simulation time 336574090000 ps
CPU time 710.19 seconds
Started Aug 17 04:49:23 PM PDT 24
Finished Aug 17 05:18:23 PM PDT 24
Peak memory 160800 kb
Host smart-3f2be63d-ad52-47aa-8697-cb3df995ec05
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3758978140 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.3758978140
Directory /workspace/20.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.1233409608
Short name T94
Test name
Test status
Simulation time 336943370000 ps
CPU time 829.53 seconds
Started Aug 17 04:49:29 PM PDT 24
Finished Aug 17 05:23:20 PM PDT 24
Peak memory 160776 kb
Host smart-02fa55c2-7cef-4b11-a318-018f0f95d300
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1233409608 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.1233409608
Directory /workspace/21.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.1130159501
Short name T71
Test name
Test status
Simulation time 336677570000 ps
CPU time 813.39 seconds
Started Aug 17 04:49:12 PM PDT 24
Finished Aug 17 05:22:21 PM PDT 24
Peak memory 160700 kb
Host smart-8496b68f-afe1-4e97-92c4-443c327251e4
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1130159501 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.1130159501
Directory /workspace/22.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.1251432158
Short name T15
Test name
Test status
Simulation time 336502150000 ps
CPU time 930.73 seconds
Started Aug 17 04:49:14 PM PDT 24
Finished Aug 17 05:27:28 PM PDT 24
Peak memory 160652 kb
Host smart-1bc8398d-3014-486f-b382-4e4c9ab0e4c9
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1251432158 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.1251432158
Directory /workspace/23.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.3222222625
Short name T80
Test name
Test status
Simulation time 336974290000 ps
CPU time 861.94 seconds
Started Aug 17 04:49:16 PM PDT 24
Finished Aug 17 05:24:39 PM PDT 24
Peak memory 160804 kb
Host smart-f43c477e-7df5-4c5f-8f78-6213f8fa7a7b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3222222625 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.3222222625
Directory /workspace/24.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.426276572
Short name T89
Test name
Test status
Simulation time 336601070000 ps
CPU time 848.49 seconds
Started Aug 17 04:49:22 PM PDT 24
Finished Aug 17 05:24:21 PM PDT 24
Peak memory 160776 kb
Host smart-e491c8eb-3b9e-49e9-ad1e-104cab236187
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=426276572 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.426276572
Directory /workspace/25.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.1233933604
Short name T83
Test name
Test status
Simulation time 336382350000 ps
CPU time 821.5 seconds
Started Aug 17 04:49:18 PM PDT 24
Finished Aug 17 05:23:02 PM PDT 24
Peak memory 160792 kb
Host smart-b575e7d3-8de5-4e8c-948e-2493ab4a20fd
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1233933604 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.1233933604
Directory /workspace/26.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.1634852170
Short name T81
Test name
Test status
Simulation time 336430650000 ps
CPU time 839.9 seconds
Started Aug 17 04:49:13 PM PDT 24
Finished Aug 17 05:23:28 PM PDT 24
Peak memory 160752 kb
Host smart-44e25701-56b6-4e19-9209-437c2500e8b4
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1634852170 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.1634852170
Directory /workspace/27.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.3820975188
Short name T76
Test name
Test status
Simulation time 337008490000 ps
CPU time 662.26 seconds
Started Aug 17 04:49:14 PM PDT 24
Finished Aug 17 05:16:48 PM PDT 24
Peak memory 160828 kb
Host smart-c41e3f3a-ee10-4334-a38d-d9fb083e14c8
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3820975188 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.3820975188
Directory /workspace/28.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.2730173808
Short name T102
Test name
Test status
Simulation time 336758710000 ps
CPU time 782.58 seconds
Started Aug 17 04:49:13 PM PDT 24
Finished Aug 17 05:21:19 PM PDT 24
Peak memory 160728 kb
Host smart-af32e2ac-dda0-44fd-8759-7d511b4f0faa
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2730173808 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.2730173808
Directory /workspace/29.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.3901734654
Short name T91
Test name
Test status
Simulation time 336763170000 ps
CPU time 753.48 seconds
Started Aug 17 04:49:17 PM PDT 24
Finished Aug 17 05:19:54 PM PDT 24
Peak memory 160768 kb
Host smart-54baa195-5889-48b5-af14-38df9426d537
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3901734654 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.3901734654
Directory /workspace/3.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.2157078851
Short name T106
Test name
Test status
Simulation time 336421990000 ps
CPU time 634.49 seconds
Started Aug 17 04:49:12 PM PDT 24
Finished Aug 17 05:15:14 PM PDT 24
Peak memory 160792 kb
Host smart-a8c3da19-7fcc-4c0c-96a7-43fc2ead0f2f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2157078851 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.2157078851
Directory /workspace/30.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.2487550382
Short name T86
Test name
Test status
Simulation time 336810450000 ps
CPU time 788.27 seconds
Started Aug 17 04:49:14 PM PDT 24
Finished Aug 17 05:21:00 PM PDT 24
Peak memory 160740 kb
Host smart-cb569827-6a9e-47e5-b0ee-a6a3f124547b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2487550382 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.2487550382
Directory /workspace/31.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.352673998
Short name T18
Test name
Test status
Simulation time 336441270000 ps
CPU time 759.41 seconds
Started Aug 17 04:49:22 PM PDT 24
Finished Aug 17 05:20:12 PM PDT 24
Peak memory 160780 kb
Host smart-9afd29dc-6863-4c76-91ff-8936244b60ba
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=352673998 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.352673998
Directory /workspace/32.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.2349572824
Short name T107
Test name
Test status
Simulation time 336465890000 ps
CPU time 545.45 seconds
Started Aug 17 04:49:12 PM PDT 24
Finished Aug 17 05:12:19 PM PDT 24
Peak memory 160816 kb
Host smart-c4fabaff-25ba-4164-a8eb-ca162c78e87c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2349572824 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.2349572824
Directory /workspace/33.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.803242088
Short name T22
Test name
Test status
Simulation time 336661390000 ps
CPU time 645.15 seconds
Started Aug 17 04:49:13 PM PDT 24
Finished Aug 17 05:15:54 PM PDT 24
Peak memory 160724 kb
Host smart-7ba1cd19-1fdc-4e5c-bc69-8c9d319bf3db
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=803242088 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.803242088
Directory /workspace/34.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.3516574522
Short name T19
Test name
Test status
Simulation time 336542190000 ps
CPU time 690.1 seconds
Started Aug 17 04:49:18 PM PDT 24
Finished Aug 17 05:17:26 PM PDT 24
Peak memory 160664 kb
Host smart-77814c7c-cd70-4be2-a654-f3e91bbf571b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3516574522 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.3516574522
Directory /workspace/35.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.2928372126
Short name T108
Test name
Test status
Simulation time 336422790000 ps
CPU time 520.37 seconds
Started Aug 17 04:49:39 PM PDT 24
Finished Aug 17 05:12:15 PM PDT 24
Peak memory 160772 kb
Host smart-abeaa101-4a2c-42f3-a09c-566fd7c83026
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2928372126 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.2928372126
Directory /workspace/36.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.4178281693
Short name T98
Test name
Test status
Simulation time 336397310000 ps
CPU time 720.72 seconds
Started Aug 17 04:49:16 PM PDT 24
Finished Aug 17 05:18:31 PM PDT 24
Peak memory 160736 kb
Host smart-eb728687-441b-43c8-aed3-8ce13016995c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4178281693 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.4178281693
Directory /workspace/37.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3277593727
Short name T23
Test name
Test status
Simulation time 337112030000 ps
CPU time 727.33 seconds
Started Aug 17 04:49:13 PM PDT 24
Finished Aug 17 05:19:05 PM PDT 24
Peak memory 160780 kb
Host smart-c6f0d67c-7911-4b9a-890a-6c12c8bcb958
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3277593727 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.3277593727
Directory /workspace/38.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.3193674891
Short name T73
Test name
Test status
Simulation time 336753130000 ps
CPU time 705.92 seconds
Started Aug 17 04:49:14 PM PDT 24
Finished Aug 17 05:18:13 PM PDT 24
Peak memory 160732 kb
Host smart-35c9ebe9-3a89-41a1-aba2-401641869e91
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3193674891 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.3193674891
Directory /workspace/39.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.1579997285
Short name T104
Test name
Test status
Simulation time 337092190000 ps
CPU time 859.18 seconds
Started Aug 17 04:49:19 PM PDT 24
Finished Aug 17 05:24:40 PM PDT 24
Peak memory 160776 kb
Host smart-0caf3a71-2784-42da-9916-e6608657f527
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1579997285 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.1579997285
Directory /workspace/4.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.3930618299
Short name T21
Test name
Test status
Simulation time 336827070000 ps
CPU time 750.48 seconds
Started Aug 17 04:49:18 PM PDT 24
Finished Aug 17 05:19:51 PM PDT 24
Peak memory 160788 kb
Host smart-2fd41058-92d8-499e-90aa-4318fae5d4f1
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3930618299 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.3930618299
Directory /workspace/40.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.885604875
Short name T88
Test name
Test status
Simulation time 337043850000 ps
CPU time 853.39 seconds
Started Aug 17 04:49:30 PM PDT 24
Finished Aug 17 05:24:57 PM PDT 24
Peak memory 160776 kb
Host smart-f134cf43-dd54-4829-8141-3f52bd6bf12c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=885604875 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.885604875
Directory /workspace/41.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.1743029025
Short name T17
Test name
Test status
Simulation time 336739530000 ps
CPU time 840.11 seconds
Started Aug 17 04:49:13 PM PDT 24
Finished Aug 17 05:24:05 PM PDT 24
Peak memory 160792 kb
Host smart-a70e6a7c-9118-4dc1-b0ea-064575c70c78
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1743029025 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.1743029025
Directory /workspace/42.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.4077021460
Short name T84
Test name
Test status
Simulation time 336723470000 ps
CPU time 797.11 seconds
Started Aug 17 04:49:11 PM PDT 24
Finished Aug 17 05:21:28 PM PDT 24
Peak memory 160796 kb
Host smart-fec0cea9-bc4b-424d-bc2c-3e290e0d36e0
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4077021460 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.4077021460
Directory /workspace/43.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.2140579392
Short name T78
Test name
Test status
Simulation time 336446310000 ps
CPU time 840.74 seconds
Started Aug 17 04:49:13 PM PDT 24
Finished Aug 17 05:24:03 PM PDT 24
Peak memory 160792 kb
Host smart-1e15f6eb-e272-4406-b1c3-931f7573f432
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2140579392 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.2140579392
Directory /workspace/44.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.4143490172
Short name T99
Test name
Test status
Simulation time 336662130000 ps
CPU time 826.5 seconds
Started Aug 17 04:49:32 PM PDT 24
Finished Aug 17 05:22:51 PM PDT 24
Peak memory 160792 kb
Host smart-7c741e75-f4b0-4895-a4af-542febd70437
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4143490172 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.4143490172
Directory /workspace/45.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.1169259531
Short name T109
Test name
Test status
Simulation time 337100590000 ps
CPU time 801.63 seconds
Started Aug 17 04:49:15 PM PDT 24
Finished Aug 17 05:22:01 PM PDT 24
Peak memory 160776 kb
Host smart-03562e78-9716-492d-97c0-79a590cf932e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1169259531 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.1169259531
Directory /workspace/46.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.1221871439
Short name T75
Test name
Test status
Simulation time 336516710000 ps
CPU time 858.08 seconds
Started Aug 17 04:49:15 PM PDT 24
Finished Aug 17 05:24:31 PM PDT 24
Peak memory 160804 kb
Host smart-441b80e7-3b42-40df-84dc-81c8d6be314a
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1221871439 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.1221871439
Directory /workspace/47.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.3385660157
Short name T16
Test name
Test status
Simulation time 336797370000 ps
CPU time 803.13 seconds
Started Aug 17 04:49:13 PM PDT 24
Finished Aug 17 05:21:57 PM PDT 24
Peak memory 160692 kb
Host smart-b2f83f40-1873-4f72-ab24-dda4385cb484
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3385660157 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.3385660157
Directory /workspace/48.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.2572466571
Short name T74
Test name
Test status
Simulation time 336571190000 ps
CPU time 771.27 seconds
Started Aug 17 04:49:15 PM PDT 24
Finished Aug 17 05:20:17 PM PDT 24
Peak memory 160800 kb
Host smart-bb6be40b-f558-44a1-a38e-cd79603f10d1
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2572466571 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.2572466571
Directory /workspace/49.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.1455034123
Short name T103
Test name
Test status
Simulation time 337056530000 ps
CPU time 792.87 seconds
Started Aug 17 04:49:10 PM PDT 24
Finished Aug 17 05:21:12 PM PDT 24
Peak memory 160712 kb
Host smart-0a3eddda-1b06-402e-bc74-f3b964526dcc
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1455034123 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.1455034123
Directory /workspace/5.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.1459730788
Short name T77
Test name
Test status
Simulation time 336537930000 ps
CPU time 781.12 seconds
Started Aug 17 04:49:13 PM PDT 24
Finished Aug 17 05:21:46 PM PDT 24
Peak memory 160752 kb
Host smart-d74a45b4-64f2-4c94-8903-f1c1a7275b69
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1459730788 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.1459730788
Directory /workspace/6.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.3758714620
Short name T97
Test name
Test status
Simulation time 336659570000 ps
CPU time 844.74 seconds
Started Aug 17 04:49:17 PM PDT 24
Finished Aug 17 05:23:41 PM PDT 24
Peak memory 160784 kb
Host smart-9f258671-e2aa-441d-b2dc-a98dd218a6ed
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3758714620 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.3758714620
Directory /workspace/7.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.1173968104
Short name T110
Test name
Test status
Simulation time 336706750000 ps
CPU time 848.3 seconds
Started Aug 17 04:49:12 PM PDT 24
Finished Aug 17 05:24:12 PM PDT 24
Peak memory 160772 kb
Host smart-d670e309-d178-4237-94e8-c7ff1f0bf5ee
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1173968104 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.1173968104
Directory /workspace/8.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.4114100293
Short name T105
Test name
Test status
Simulation time 336391170000 ps
CPU time 692.6 seconds
Started Aug 17 04:49:17 PM PDT 24
Finished Aug 17 05:17:44 PM PDT 24
Peak memory 160728 kb
Host smart-ea158750-bcdd-4c20-a70d-6f9dc7f4d3ac
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4114100293 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.4114100293
Directory /workspace/9.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.4042249054
Short name T193
Test name
Test status
Simulation time 1073270000 ps
CPU time 3.31 seconds
Started Aug 17 04:24:55 PM PDT 24
Finished Aug 17 04:25:02 PM PDT 24
Peak memory 164844 kb
Host smart-22859c5a-5146-4d32-a86f-d8d35b36841d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4042249054 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.4042249054
Directory /workspace/0.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.2468670396
Short name T179
Test name
Test status
Simulation time 1494310000 ps
CPU time 4.51 seconds
Started Aug 17 04:21:54 PM PDT 24
Finished Aug 17 04:22:04 PM PDT 24
Peak memory 164708 kb
Host smart-1b837d03-adea-4ae4-9cb3-78433366d609
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2468670396 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.2468670396
Directory /workspace/1.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.2620271564
Short name T159
Test name
Test status
Simulation time 1523830000 ps
CPU time 5.45 seconds
Started Aug 17 04:21:55 PM PDT 24
Finished Aug 17 04:22:07 PM PDT 24
Peak memory 164648 kb
Host smart-7470696f-bb38-4d9e-a5eb-54a0a4d4a999
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2620271564 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.2620271564
Directory /workspace/10.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.2420868979
Short name T195
Test name
Test status
Simulation time 1546950000 ps
CPU time 3.8 seconds
Started Aug 17 04:25:47 PM PDT 24
Finished Aug 17 04:25:55 PM PDT 24
Peak memory 164360 kb
Host smart-9fc6b030-db73-4d92-9665-62f9d253c633
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2420868979 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.2420868979
Directory /workspace/11.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.1226628340
Short name T181
Test name
Test status
Simulation time 1514810000 ps
CPU time 4.15 seconds
Started Aug 17 04:25:12 PM PDT 24
Finished Aug 17 04:25:22 PM PDT 24
Peak memory 164396 kb
Host smart-a3cb6ff9-c8f6-40eb-bcab-356fdf1fc03c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1226628340 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.1226628340
Directory /workspace/12.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.3742731794
Short name T178
Test name
Test status
Simulation time 1431170000 ps
CPU time 3.83 seconds
Started Aug 17 04:24:48 PM PDT 24
Finished Aug 17 04:24:57 PM PDT 24
Peak memory 164032 kb
Host smart-a0dfd528-ac6a-43b9-89c9-27acb8b55b59
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3742731794 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.3742731794
Directory /workspace/13.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.2851939967
Short name T175
Test name
Test status
Simulation time 1385170000 ps
CPU time 4.25 seconds
Started Aug 17 04:24:17 PM PDT 24
Finished Aug 17 04:24:27 PM PDT 24
Peak memory 164500 kb
Host smart-243168ff-2d84-4802-9335-331c1934c378
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2851939967 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.2851939967
Directory /workspace/14.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.2717067231
Short name T189
Test name
Test status
Simulation time 1396970000 ps
CPU time 4.21 seconds
Started Aug 17 04:24:58 PM PDT 24
Finished Aug 17 04:25:07 PM PDT 24
Peak memory 164928 kb
Host smart-eed444a1-31d9-407d-a08a-ec994523a415
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2717067231 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.2717067231
Directory /workspace/15.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.1203666049
Short name T160
Test name
Test status
Simulation time 1553750000 ps
CPU time 4.65 seconds
Started Aug 17 04:24:58 PM PDT 24
Finished Aug 17 04:25:09 PM PDT 24
Peak memory 162868 kb
Host smart-46827f14-801a-4202-9d93-f19a26b7fc21
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1203666049 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.1203666049
Directory /workspace/16.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.104584553
Short name T154
Test name
Test status
Simulation time 1485650000 ps
CPU time 3.78 seconds
Started Aug 17 04:24:31 PM PDT 24
Finished Aug 17 04:24:39 PM PDT 24
Peak memory 164576 kb
Host smart-118bca6e-9883-48e6-a5e2-70e8f073c730
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=104584553 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.104584553
Directory /workspace/17.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.1847830076
Short name T182
Test name
Test status
Simulation time 1586910000 ps
CPU time 3.97 seconds
Started Aug 17 04:25:48 PM PDT 24
Finished Aug 17 04:25:57 PM PDT 24
Peak memory 164612 kb
Host smart-68ff42a7-ef0b-4c1b-9e22-f7538351d56e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1847830076 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.1847830076
Directory /workspace/18.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.100248776
Short name T164
Test name
Test status
Simulation time 1472870000 ps
CPU time 3.39 seconds
Started Aug 17 04:26:00 PM PDT 24
Finished Aug 17 04:26:07 PM PDT 24
Peak memory 164880 kb
Host smart-f9e02587-745b-44b9-a25d-596a1d885e96
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=100248776 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.100248776
Directory /workspace/19.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.2063882397
Short name T169
Test name
Test status
Simulation time 1312890000 ps
CPU time 3.29 seconds
Started Aug 17 04:24:56 PM PDT 24
Finished Aug 17 04:25:03 PM PDT 24
Peak memory 164056 kb
Host smart-2556b65c-0369-485f-9836-07f04c519591
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2063882397 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.2063882397
Directory /workspace/2.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.532924246
Short name T199
Test name
Test status
Simulation time 1467190000 ps
CPU time 3.78 seconds
Started Aug 17 04:26:01 PM PDT 24
Finished Aug 17 04:26:10 PM PDT 24
Peak memory 164912 kb
Host smart-2e9afc0e-fdac-46aa-8592-a8891d097b3e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=532924246 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.532924246
Directory /workspace/20.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.981769401
Short name T161
Test name
Test status
Simulation time 1447250000 ps
CPU time 3.76 seconds
Started Aug 17 04:25:48 PM PDT 24
Finished Aug 17 04:25:57 PM PDT 24
Peak memory 164580 kb
Host smart-f6a938c7-7988-4de3-bfdc-91b871b02bd0
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=981769401 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.981769401
Directory /workspace/21.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.966879162
Short name T167
Test name
Test status
Simulation time 1524970000 ps
CPU time 4.69 seconds
Started Aug 17 04:24:58 PM PDT 24
Finished Aug 17 04:25:09 PM PDT 24
Peak memory 163772 kb
Host smart-68f9679d-2869-4120-a92d-f4d43972cbde
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=966879162 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.966879162
Directory /workspace/22.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.1242073255
Short name T153
Test name
Test status
Simulation time 1538570000 ps
CPU time 5.37 seconds
Started Aug 17 04:22:12 PM PDT 24
Finished Aug 17 04:22:24 PM PDT 24
Peak memory 164572 kb
Host smart-712ba1d8-7b41-4d21-9a04-8dfd24c1f88a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1242073255 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.1242073255
Directory /workspace/23.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.1440283614
Short name T187
Test name
Test status
Simulation time 1555930000 ps
CPU time 4.57 seconds
Started Aug 17 04:24:17 PM PDT 24
Finished Aug 17 04:24:28 PM PDT 24
Peak memory 164540 kb
Host smart-d8a97c7b-d350-430e-a579-4a7e4c18ab0a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1440283614 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.1440283614
Directory /workspace/24.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.3758016133
Short name T168
Test name
Test status
Simulation time 1344210000 ps
CPU time 4.07 seconds
Started Aug 17 04:25:45 PM PDT 24
Finished Aug 17 04:25:54 PM PDT 24
Peak memory 164328 kb
Host smart-3ae4eb94-d4cf-4bfc-8d16-666e0cbb9296
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3758016133 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.3758016133
Directory /workspace/25.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2611299514
Short name T188
Test name
Test status
Simulation time 1379430000 ps
CPU time 4.87 seconds
Started Aug 17 04:21:56 PM PDT 24
Finished Aug 17 04:22:07 PM PDT 24
Peak memory 164648 kb
Host smart-f0bdba71-bcd1-4201-bb75-f4cfa82e9992
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2611299514 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.2611299514
Directory /workspace/26.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.3974970241
Short name T157
Test name
Test status
Simulation time 1505870000 ps
CPU time 3.74 seconds
Started Aug 17 04:25:51 PM PDT 24
Finished Aug 17 04:25:59 PM PDT 24
Peak memory 165108 kb
Host smart-9267c145-191f-4687-8fe4-45fa4d84ea85
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3974970241 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.3974970241
Directory /workspace/27.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.3372411847
Short name T183
Test name
Test status
Simulation time 1231930000 ps
CPU time 4.23 seconds
Started Aug 17 04:21:43 PM PDT 24
Finished Aug 17 04:21:52 PM PDT 24
Peak memory 164572 kb
Host smart-ef344abc-0f99-4e13-af75-a275e4823b99
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3372411847 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.3372411847
Directory /workspace/28.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.518917456
Short name T162
Test name
Test status
Simulation time 1560770000 ps
CPU time 5.86 seconds
Started Aug 17 04:25:59 PM PDT 24
Finished Aug 17 04:26:12 PM PDT 24
Peak memory 164504 kb
Host smart-f51236ef-e5c5-4ac8-b7c0-b124996e2f97
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=518917456 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.518917456
Directory /workspace/29.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.1579659511
Short name T185
Test name
Test status
Simulation time 1506870000 ps
CPU time 3.83 seconds
Started Aug 17 04:24:55 PM PDT 24
Finished Aug 17 04:25:04 PM PDT 24
Peak memory 164168 kb
Host smart-97a2c55c-9c19-46cd-bb43-a9af4559540b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1579659511 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.1579659511
Directory /workspace/3.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.2206136006
Short name T163
Test name
Test status
Simulation time 1289850000 ps
CPU time 4.41 seconds
Started Aug 17 04:26:00 PM PDT 24
Finished Aug 17 04:26:10 PM PDT 24
Peak memory 164496 kb
Host smart-69112fc7-3597-4dd5-9558-f1e68692c176
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2206136006 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.2206136006
Directory /workspace/30.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.551974403
Short name T166
Test name
Test status
Simulation time 1448170000 ps
CPU time 4.06 seconds
Started Aug 17 04:25:27 PM PDT 24
Finished Aug 17 04:25:35 PM PDT 24
Peak memory 164292 kb
Host smart-2f0ced30-8626-41d3-8f9c-96bd0201fba0
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=551974403 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.551974403
Directory /workspace/31.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.3106916604
Short name T152
Test name
Test status
Simulation time 1249130000 ps
CPU time 3.71 seconds
Started Aug 17 04:25:47 PM PDT 24
Finished Aug 17 04:25:55 PM PDT 24
Peak memory 163992 kb
Host smart-cb04fab3-3e7e-4b39-9e2c-9cd46596323a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3106916604 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.3106916604
Directory /workspace/32.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.471482926
Short name T172
Test name
Test status
Simulation time 1533650000 ps
CPU time 3.66 seconds
Started Aug 17 04:25:37 PM PDT 24
Finished Aug 17 04:25:46 PM PDT 24
Peak memory 164324 kb
Host smart-278f0771-ce22-4239-b46d-a1f80ba1cc98
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=471482926 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.471482926
Directory /workspace/33.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.874460367
Short name T165
Test name
Test status
Simulation time 1291870000 ps
CPU time 3.82 seconds
Started Aug 17 04:21:14 PM PDT 24
Finished Aug 17 04:21:23 PM PDT 24
Peak memory 164492 kb
Host smart-d018c5ed-c907-4b81-9a95-f6d3c2abc3a0
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=874460367 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.874460367
Directory /workspace/34.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.4197194301
Short name T174
Test name
Test status
Simulation time 1496770000 ps
CPU time 3.51 seconds
Started Aug 17 04:25:48 PM PDT 24
Finished Aug 17 04:25:56 PM PDT 24
Peak memory 164268 kb
Host smart-efdcb019-fa1d-4869-9163-a4b72a6fdc74
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4197194301 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.4197194301
Directory /workspace/35.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.166548153
Short name T158
Test name
Test status
Simulation time 1241430000 ps
CPU time 4.02 seconds
Started Aug 17 04:24:17 PM PDT 24
Finished Aug 17 04:24:26 PM PDT 24
Peak memory 164500 kb
Host smart-ad9e0c59-3b0b-4900-8bda-17e886095024
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=166548153 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.166548153
Directory /workspace/36.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.294109544
Short name T176
Test name
Test status
Simulation time 1289090000 ps
CPU time 4.5 seconds
Started Aug 17 04:21:24 PM PDT 24
Finished Aug 17 04:21:34 PM PDT 24
Peak memory 164640 kb
Host smart-288def0b-2f78-484b-9b91-6f87a79060a1
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=294109544 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.294109544
Directory /workspace/37.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.2203114700
Short name T192
Test name
Test status
Simulation time 1338750000 ps
CPU time 3.77 seconds
Started Aug 17 04:24:54 PM PDT 24
Finished Aug 17 04:25:02 PM PDT 24
Peak memory 164184 kb
Host smart-ec3ae852-efca-4578-b168-4fdf1e268b8d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2203114700 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.2203114700
Directory /workspace/38.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.1068699261
Short name T177
Test name
Test status
Simulation time 1535130000 ps
CPU time 4.96 seconds
Started Aug 17 04:25:04 PM PDT 24
Finished Aug 17 04:25:15 PM PDT 24
Peak memory 164300 kb
Host smart-40eea9c5-27fb-41e5-986a-f06018ee0817
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1068699261 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.1068699261
Directory /workspace/39.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.1287896184
Short name T173
Test name
Test status
Simulation time 1494690000 ps
CPU time 4.37 seconds
Started Aug 17 04:25:11 PM PDT 24
Finished Aug 17 04:25:21 PM PDT 24
Peak memory 164448 kb
Host smart-0a474916-2aa2-45fa-8eef-4ca0ad64144b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1287896184 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.1287896184
Directory /workspace/4.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.3284903597
Short name T194
Test name
Test status
Simulation time 1576510000 ps
CPU time 3.94 seconds
Started Aug 17 04:22:33 PM PDT 24
Finished Aug 17 04:22:42 PM PDT 24
Peak memory 164592 kb
Host smart-fc795bdf-d94c-494f-8922-a498c1cb5439
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3284903597 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.3284903597
Directory /workspace/40.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.3076230125
Short name T186
Test name
Test status
Simulation time 1489530000 ps
CPU time 3.84 seconds
Started Aug 17 04:24:35 PM PDT 24
Finished Aug 17 04:24:44 PM PDT 24
Peak memory 164712 kb
Host smart-533fb783-ff6c-4913-89fe-d8fe59e4031e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3076230125 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.3076230125
Directory /workspace/41.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.893377239
Short name T198
Test name
Test status
Simulation time 1528850000 ps
CPU time 5.23 seconds
Started Aug 17 04:24:36 PM PDT 24
Finished Aug 17 04:24:48 PM PDT 24
Peak memory 164716 kb
Host smart-bcf27b25-52b2-4dc5-9049-dc56cdccc2c1
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=893377239 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.893377239
Directory /workspace/42.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1181301270
Short name T184
Test name
Test status
Simulation time 1547710000 ps
CPU time 4.55 seconds
Started Aug 17 04:25:03 PM PDT 24
Finished Aug 17 04:25:13 PM PDT 24
Peak memory 164272 kb
Host smart-470e58f2-b098-4ff6-b200-da0af6c6ca19
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1181301270 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.1181301270
Directory /workspace/43.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.890453794
Short name T196
Test name
Test status
Simulation time 1282230000 ps
CPU time 3.71 seconds
Started Aug 17 04:24:54 PM PDT 24
Finished Aug 17 04:25:02 PM PDT 24
Peak memory 163352 kb
Host smart-9f6a4e9b-debe-46e6-b368-600aa2a239d4
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=890453794 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.890453794
Directory /workspace/44.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.3145407083
Short name T180
Test name
Test status
Simulation time 1544050000 ps
CPU time 4.27 seconds
Started Aug 17 04:26:04 PM PDT 24
Finished Aug 17 04:26:13 PM PDT 24
Peak memory 164336 kb
Host smart-4d4eca12-4c85-4d57-b952-939fa6994dc1
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3145407083 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.3145407083
Directory /workspace/45.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.230103394
Short name T197
Test name
Test status
Simulation time 1517770000 ps
CPU time 3.37 seconds
Started Aug 17 04:25:08 PM PDT 24
Finished Aug 17 04:25:16 PM PDT 24
Peak memory 164568 kb
Host smart-cafaae84-a86f-41a6-86db-13d9f9c74c25
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=230103394 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.230103394
Directory /workspace/46.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.2287778226
Short name T155
Test name
Test status
Simulation time 1438190000 ps
CPU time 3.74 seconds
Started Aug 17 04:25:59 PM PDT 24
Finished Aug 17 04:26:08 PM PDT 24
Peak memory 164276 kb
Host smart-db4e3969-6751-45dc-ac48-a0182a3b08c0
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2287778226 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.2287778226
Directory /workspace/47.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.3768315597
Short name T171
Test name
Test status
Simulation time 1555050000 ps
CPU time 4 seconds
Started Aug 17 04:25:46 PM PDT 24
Finished Aug 17 04:25:55 PM PDT 24
Peak memory 163528 kb
Host smart-ed5fd02e-0e7d-4696-825f-b28fac02e36d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3768315597 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.3768315597
Directory /workspace/48.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.2336742671
Short name T156
Test name
Test status
Simulation time 1462450000 ps
CPU time 4.14 seconds
Started Aug 17 04:21:41 PM PDT 24
Finished Aug 17 04:21:50 PM PDT 24
Peak memory 164712 kb
Host smart-84bcb4c1-7fdb-449f-8eb3-ef59a86cfdda
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2336742671 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.2336742671
Directory /workspace/49.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.2300947197
Short name T190
Test name
Test status
Simulation time 1361190000 ps
CPU time 4.13 seconds
Started Aug 17 04:22:05 PM PDT 24
Finished Aug 17 04:22:14 PM PDT 24
Peak memory 164656 kb
Host smart-f73f102a-4f14-4fe8-8cf0-51bc660ac35b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2300947197 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.2300947197
Directory /workspace/5.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.1354866400
Short name T200
Test name
Test status
Simulation time 1155730000 ps
CPU time 3.99 seconds
Started Aug 17 04:22:55 PM PDT 24
Finished Aug 17 04:23:03 PM PDT 24
Peak memory 164720 kb
Host smart-6fd73d74-60df-46b3-8092-b3d5b7db0c42
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1354866400 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.1354866400
Directory /workspace/6.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.1469013277
Short name T170
Test name
Test status
Simulation time 1225370000 ps
CPU time 3.04 seconds
Started Aug 17 04:25:47 PM PDT 24
Finished Aug 17 04:25:53 PM PDT 24
Peak memory 164980 kb
Host smart-1cf97483-3857-43d9-850e-c1d9fbd2b930
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1469013277 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.1469013277
Directory /workspace/7.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.254771431
Short name T191
Test name
Test status
Simulation time 1411890000 ps
CPU time 3.61 seconds
Started Aug 17 04:24:48 PM PDT 24
Finished Aug 17 04:24:56 PM PDT 24
Peak memory 164556 kb
Host smart-d3435a25-4c73-4043-be76-01dc91218121
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=254771431 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.254771431
Directory /workspace/8.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.968859366
Short name T151
Test name
Test status
Simulation time 1543210000 ps
CPU time 3.4 seconds
Started Aug 17 04:24:54 PM PDT 24
Finished Aug 17 04:25:02 PM PDT 24
Peak memory 165224 kb
Host smart-3d36ff97-902c-4286-957f-56e9834ec724
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=968859366 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.968859366
Directory /workspace/9.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.2295317139
Short name T61
Test name
Test status
Simulation time 1261970000 ps
CPU time 2.98 seconds
Started Aug 17 04:49:57 PM PDT 24
Finished Aug 17 04:50:03 PM PDT 24
Peak memory 164832 kb
Host smart-d4bd1bc5-0c1f-403f-965b-ebc2c9ee7557
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2295317139 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.2295317139
Directory /workspace/0.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.281540587
Short name T51
Test name
Test status
Simulation time 1426350000 ps
CPU time 3.84 seconds
Started Aug 17 04:50:08 PM PDT 24
Finished Aug 17 04:50:17 PM PDT 24
Peak memory 164836 kb
Host smart-127ea073-f3a0-4f1f-a036-86ee3c0a0a62
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=281540587 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.281540587
Directory /workspace/10.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.1322901764
Short name T67
Test name
Test status
Simulation time 1530630000 ps
CPU time 4.65 seconds
Started Aug 17 04:50:10 PM PDT 24
Finished Aug 17 04:50:26 PM PDT 24
Peak memory 164800 kb
Host smart-106f9525-2643-4964-b51e-77769d576b25
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1322901764 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.1322901764
Directory /workspace/11.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.4236808219
Short name T36
Test name
Test status
Simulation time 1448590000 ps
CPU time 4.91 seconds
Started Aug 17 04:50:09 PM PDT 24
Finished Aug 17 04:50:20 PM PDT 24
Peak memory 164740 kb
Host smart-0307974a-90cc-41a2-b424-ebbf67fd6698
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4236808219 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.4236808219
Directory /workspace/12.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.2944667692
Short name T8
Test name
Test status
Simulation time 1476770000 ps
CPU time 4.02 seconds
Started Aug 17 04:50:09 PM PDT 24
Finished Aug 17 04:50:18 PM PDT 24
Peak memory 164836 kb
Host smart-d8dfb0e5-af4d-4d7c-bdee-4376bc8a3981
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2944667692 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.2944667692
Directory /workspace/13.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.938950711
Short name T10
Test name
Test status
Simulation time 1345010000 ps
CPU time 3.33 seconds
Started Aug 17 04:49:57 PM PDT 24
Finished Aug 17 04:50:04 PM PDT 24
Peak memory 164828 kb
Host smart-33a4b580-c0b9-40ad-8835-e88c1d1a2a39
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=938950711 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.938950711
Directory /workspace/14.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.1619063212
Short name T41
Test name
Test status
Simulation time 1500070000 ps
CPU time 4.15 seconds
Started Aug 17 04:49:58 PM PDT 24
Finished Aug 17 04:50:07 PM PDT 24
Peak memory 164800 kb
Host smart-61a314f9-9731-453f-bc4f-2e750d99ff67
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1619063212 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.1619063212
Directory /workspace/15.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.1255914292
Short name T35
Test name
Test status
Simulation time 1385710000 ps
CPU time 4.03 seconds
Started Aug 17 04:50:05 PM PDT 24
Finished Aug 17 04:50:14 PM PDT 24
Peak memory 164820 kb
Host smart-69af3cee-5505-4eb9-a164-6cbd6e198258
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1255914292 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.1255914292
Directory /workspace/16.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.3448486287
Short name T11
Test name
Test status
Simulation time 1602430000 ps
CPU time 4.78 seconds
Started Aug 17 04:50:04 PM PDT 24
Finished Aug 17 04:50:15 PM PDT 24
Peak memory 164820 kb
Host smart-1baa8756-9da6-45d6-ac80-dab2a27f0f41
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3448486287 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.3448486287
Directory /workspace/17.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.3471879537
Short name T52
Test name
Test status
Simulation time 1452350000 ps
CPU time 3.22 seconds
Started Aug 17 04:50:03 PM PDT 24
Finished Aug 17 04:50:10 PM PDT 24
Peak memory 163752 kb
Host smart-55228c91-d532-4e76-ac95-6febe9a50606
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3471879537 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.3471879537
Directory /workspace/18.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.498839812
Short name T1
Test name
Test status
Simulation time 1532610000 ps
CPU time 4.84 seconds
Started Aug 17 04:49:58 PM PDT 24
Finished Aug 17 04:50:09 PM PDT 24
Peak memory 164908 kb
Host smart-f3c7e0a6-37cd-4976-844d-e80120e02164
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=498839812 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.498839812
Directory /workspace/19.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.3583859500
Short name T39
Test name
Test status
Simulation time 1476570000 ps
CPU time 4.07 seconds
Started Aug 17 04:50:08 PM PDT 24
Finished Aug 17 04:50:17 PM PDT 24
Peak memory 164816 kb
Host smart-67b7565d-c83b-4929-8ebc-829415ae962f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3583859500 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.3583859500
Directory /workspace/2.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.335070254
Short name T3
Test name
Test status
Simulation time 1434330000 ps
CPU time 3.85 seconds
Started Aug 17 04:50:11 PM PDT 24
Finished Aug 17 04:50:20 PM PDT 24
Peak memory 164896 kb
Host smart-4c233873-ada5-4a81-b022-f34c41882cde
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=335070254 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.335070254
Directory /workspace/20.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.3227502879
Short name T58
Test name
Test status
Simulation time 1188790000 ps
CPU time 3.85 seconds
Started Aug 17 04:50:10 PM PDT 24
Finished Aug 17 04:50:18 PM PDT 24
Peak memory 164800 kb
Host smart-d1e732fb-32e5-4e7f-97d2-5647c73a406c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3227502879 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.3227502879
Directory /workspace/21.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.2773809486
Short name T7
Test name
Test status
Simulation time 1372810000 ps
CPU time 3.58 seconds
Started Aug 17 04:50:04 PM PDT 24
Finished Aug 17 04:50:12 PM PDT 24
Peak memory 164824 kb
Host smart-7df259d1-b6fb-47c4-bb45-70dc22ab3a47
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2773809486 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.2773809486
Directory /workspace/22.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.579846489
Short name T65
Test name
Test status
Simulation time 1362610000 ps
CPU time 3.82 seconds
Started Aug 17 04:50:09 PM PDT 24
Finished Aug 17 04:50:17 PM PDT 24
Peak memory 164788 kb
Host smart-1f559a75-ca47-4e8c-87cb-9a48b327f64a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=579846489 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.579846489
Directory /workspace/23.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.2936946046
Short name T64
Test name
Test status
Simulation time 1498990000 ps
CPU time 4.06 seconds
Started Aug 17 04:50:03 PM PDT 24
Finished Aug 17 04:50:12 PM PDT 24
Peak memory 164796 kb
Host smart-d6d66b3e-691b-4410-a933-175cd6265050
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2936946046 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.2936946046
Directory /workspace/24.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.4074951604
Short name T60
Test name
Test status
Simulation time 1367570000 ps
CPU time 4.74 seconds
Started Aug 17 04:50:06 PM PDT 24
Finished Aug 17 04:50:16 PM PDT 24
Peak memory 164868 kb
Host smart-fe3e0d9d-c72c-4f4b-a16b-e57634f17e94
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4074951604 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.4074951604
Directory /workspace/25.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.1364529935
Short name T34
Test name
Test status
Simulation time 1456650000 ps
CPU time 4.54 seconds
Started Aug 17 04:49:55 PM PDT 24
Finished Aug 17 04:50:04 PM PDT 24
Peak memory 164828 kb
Host smart-222725ed-016b-4b8e-ad8d-e167e91131af
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1364529935 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.1364529935
Directory /workspace/26.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.1995203596
Short name T66
Test name
Test status
Simulation time 1146970000 ps
CPU time 3.71 seconds
Started Aug 17 04:49:59 PM PDT 24
Finished Aug 17 04:50:07 PM PDT 24
Peak memory 164988 kb
Host smart-5e8097d1-3d5d-4b0c-8d42-65f6a3b9d849
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1995203596 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.1995203596
Directory /workspace/27.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.3396397694
Short name T62
Test name
Test status
Simulation time 1448930000 ps
CPU time 4.31 seconds
Started Aug 17 04:50:03 PM PDT 24
Finished Aug 17 04:50:13 PM PDT 24
Peak memory 164804 kb
Host smart-9e7022d1-c2fe-448d-a4ff-f4304a63b492
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3396397694 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.3396397694
Directory /workspace/28.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.2593002277
Short name T33
Test name
Test status
Simulation time 1240790000 ps
CPU time 3.8 seconds
Started Aug 17 04:50:09 PM PDT 24
Finished Aug 17 04:50:17 PM PDT 24
Peak memory 164876 kb
Host smart-2fcf7629-1a70-48c3-aa5f-6ef35858e91e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2593002277 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.2593002277
Directory /workspace/29.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.3763883101
Short name T59
Test name
Test status
Simulation time 1185750000 ps
CPU time 4.16 seconds
Started Aug 17 04:49:59 PM PDT 24
Finished Aug 17 04:50:08 PM PDT 24
Peak memory 164816 kb
Host smart-62577e57-41b0-4142-b6a5-398d95227b9f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3763883101 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.3763883101
Directory /workspace/3.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.167059515
Short name T56
Test name
Test status
Simulation time 1479870000 ps
CPU time 4.44 seconds
Started Aug 17 04:50:01 PM PDT 24
Finished Aug 17 04:50:11 PM PDT 24
Peak memory 164788 kb
Host smart-eafb425c-b716-4d00-bc12-16e27733f0fc
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=167059515 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.167059515
Directory /workspace/30.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.3247489519
Short name T45
Test name
Test status
Simulation time 1524250000 ps
CPU time 4.94 seconds
Started Aug 17 04:50:02 PM PDT 24
Finished Aug 17 04:50:13 PM PDT 24
Peak memory 164820 kb
Host smart-bf10c2c3-d9e1-4172-b6c1-e07adf1ad1f1
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3247489519 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.3247489519
Directory /workspace/31.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.469055360
Short name T46
Test name
Test status
Simulation time 1496570000 ps
CPU time 3.49 seconds
Started Aug 17 04:50:11 PM PDT 24
Finished Aug 17 04:50:24 PM PDT 24
Peak memory 164812 kb
Host smart-7785a80b-6cca-4a55-b59d-73c1ab04a65b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=469055360 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.469055360
Directory /workspace/32.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.4293693913
Short name T55
Test name
Test status
Simulation time 1454790000 ps
CPU time 3.9 seconds
Started Aug 17 04:50:07 PM PDT 24
Finished Aug 17 04:50:16 PM PDT 24
Peak memory 164836 kb
Host smart-df2221d0-f8f5-4dfc-b5f4-74d6a9cd3933
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4293693913 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.4293693913
Directory /workspace/33.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.3925311970
Short name T43
Test name
Test status
Simulation time 1550670000 ps
CPU time 4.68 seconds
Started Aug 17 04:50:10 PM PDT 24
Finished Aug 17 04:50:21 PM PDT 24
Peak memory 164800 kb
Host smart-ebcec84b-b25c-445d-be2e-0fa3574384b4
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3925311970 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.3925311970
Directory /workspace/34.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.792818254
Short name T70
Test name
Test status
Simulation time 1516270000 ps
CPU time 4.63 seconds
Started Aug 17 04:50:04 PM PDT 24
Finished Aug 17 04:50:14 PM PDT 24
Peak memory 164828 kb
Host smart-d7d48986-59d7-42fa-a4f7-eafad7a4ca8f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=792818254 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.792818254
Directory /workspace/35.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.3768216579
Short name T54
Test name
Test status
Simulation time 1540790000 ps
CPU time 3.85 seconds
Started Aug 17 04:50:09 PM PDT 24
Finished Aug 17 04:50:17 PM PDT 24
Peak memory 164820 kb
Host smart-235ba6aa-44f6-45fd-8962-db0468348def
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3768216579 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.3768216579
Directory /workspace/36.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.1453452612
Short name T57
Test name
Test status
Simulation time 1509810000 ps
CPU time 4.71 seconds
Started Aug 17 04:49:59 PM PDT 24
Finished Aug 17 04:50:09 PM PDT 24
Peak memory 164812 kb
Host smart-31d9b9d3-0f4d-4112-8c29-d159937c0391
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1453452612 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.1453452612
Directory /workspace/37.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.591106644
Short name T44
Test name
Test status
Simulation time 1495950000 ps
CPU time 4.29 seconds
Started Aug 17 04:50:05 PM PDT 24
Finished Aug 17 04:50:14 PM PDT 24
Peak memory 164812 kb
Host smart-c5a737d4-2206-4e3f-9949-6581b819c59a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=591106644 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.591106644
Directory /workspace/38.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.764979850
Short name T13
Test name
Test status
Simulation time 1274970000 ps
CPU time 4.65 seconds
Started Aug 17 04:49:56 PM PDT 24
Finished Aug 17 04:50:06 PM PDT 24
Peak memory 164780 kb
Host smart-1989c332-8674-49b2-9982-c1dbd4299422
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=764979850 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.764979850
Directory /workspace/39.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.2496870082
Short name T68
Test name
Test status
Simulation time 1353490000 ps
CPU time 3.57 seconds
Started Aug 17 04:50:09 PM PDT 24
Finished Aug 17 04:50:17 PM PDT 24
Peak memory 164880 kb
Host smart-5518a9bd-d584-4ccc-aced-64e8470dd866
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2496870082 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.2496870082
Directory /workspace/4.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.3028714201
Short name T37
Test name
Test status
Simulation time 1542890000 ps
CPU time 3.89 seconds
Started Aug 17 04:50:13 PM PDT 24
Finished Aug 17 04:50:21 PM PDT 24
Peak memory 164832 kb
Host smart-61645353-0cd6-48fe-a4a8-ee2cb1ea413b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3028714201 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.3028714201
Directory /workspace/40.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.2041083340
Short name T53
Test name
Test status
Simulation time 1410650000 ps
CPU time 3.32 seconds
Started Aug 17 04:50:05 PM PDT 24
Finished Aug 17 04:50:12 PM PDT 24
Peak memory 163752 kb
Host smart-f21958b2-8205-4408-8944-cd4f724cc909
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2041083340 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.2041083340
Directory /workspace/41.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.2734207621
Short name T47
Test name
Test status
Simulation time 1384710000 ps
CPU time 3.6 seconds
Started Aug 17 04:50:08 PM PDT 24
Finished Aug 17 04:50:16 PM PDT 24
Peak memory 164820 kb
Host smart-7d31c9bc-aac5-42f6-ab6e-f18a9ab2cac8
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2734207621 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.2734207621
Directory /workspace/42.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.1066405664
Short name T9
Test name
Test status
Simulation time 1586890000 ps
CPU time 5.33 seconds
Started Aug 17 04:49:57 PM PDT 24
Finished Aug 17 04:50:09 PM PDT 24
Peak memory 164820 kb
Host smart-a94ad5ca-4870-407f-a29e-5df4e0e2662b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1066405664 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.1066405664
Directory /workspace/43.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.1160921841
Short name T49
Test name
Test status
Simulation time 1287650000 ps
CPU time 3.88 seconds
Started Aug 17 04:49:58 PM PDT 24
Finished Aug 17 04:50:06 PM PDT 24
Peak memory 164816 kb
Host smart-46120413-19b6-4a96-abe4-2c0ea74f9038
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1160921841 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.1160921841
Directory /workspace/44.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.3041215179
Short name T42
Test name
Test status
Simulation time 1493750000 ps
CPU time 4.22 seconds
Started Aug 17 04:50:04 PM PDT 24
Finished Aug 17 04:50:13 PM PDT 24
Peak memory 164816 kb
Host smart-f98221ea-da22-4ebb-b0bf-1cdb5e84803c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3041215179 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.3041215179
Directory /workspace/45.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.666360397
Short name T31
Test name
Test status
Simulation time 1452130000 ps
CPU time 3.95 seconds
Started Aug 17 04:50:01 PM PDT 24
Finished Aug 17 04:50:11 PM PDT 24
Peak memory 164864 kb
Host smart-440067c6-2938-4b45-812f-bd480bb89910
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=666360397 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.666360397
Directory /workspace/46.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.934873799
Short name T32
Test name
Test status
Simulation time 1594750000 ps
CPU time 4.7 seconds
Started Aug 17 04:50:06 PM PDT 24
Finished Aug 17 04:50:17 PM PDT 24
Peak memory 164796 kb
Host smart-2387b1a7-e8ba-465d-b818-ac7a524539e4
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=934873799 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.934873799
Directory /workspace/47.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.3184692793
Short name T38
Test name
Test status
Simulation time 1260550000 ps
CPU time 3.59 seconds
Started Aug 17 04:49:59 PM PDT 24
Finished Aug 17 04:50:07 PM PDT 24
Peak memory 164800 kb
Host smart-4b6ce175-ee6c-4d79-a6c1-60bcae07c04f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3184692793 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.3184692793
Directory /workspace/48.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.1459660744
Short name T50
Test name
Test status
Simulation time 1566630000 ps
CPU time 3.95 seconds
Started Aug 17 04:50:09 PM PDT 24
Finished Aug 17 04:50:18 PM PDT 24
Peak memory 164820 kb
Host smart-27f9ef15-7b55-4d3c-962e-5ee366709844
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1459660744 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.1459660744
Directory /workspace/49.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.4277994467
Short name T2
Test name
Test status
Simulation time 1364090000 ps
CPU time 4.07 seconds
Started Aug 17 04:50:01 PM PDT 24
Finished Aug 17 04:50:10 PM PDT 24
Peak memory 164792 kb
Host smart-6d2cc44f-20cf-4a10-85fc-fa7583e0f917
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4277994467 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.4277994467
Directory /workspace/5.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.1567416461
Short name T40
Test name
Test status
Simulation time 1421670000 ps
CPU time 4.47 seconds
Started Aug 17 04:49:58 PM PDT 24
Finished Aug 17 04:50:08 PM PDT 24
Peak memory 164860 kb
Host smart-e295bd3e-a5b6-44f5-9ed8-58eae4169006
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1567416461 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.1567416461
Directory /workspace/6.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.2147754520
Short name T63
Test name
Test status
Simulation time 1436190000 ps
CPU time 4.3 seconds
Started Aug 17 04:50:07 PM PDT 24
Finished Aug 17 04:50:17 PM PDT 24
Peak memory 164800 kb
Host smart-7daf4dba-414a-429c-bae2-306dd7947cb0
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2147754520 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.2147754520
Directory /workspace/7.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.3598759664
Short name T69
Test name
Test status
Simulation time 1542130000 ps
CPU time 4.73 seconds
Started Aug 17 04:50:09 PM PDT 24
Finished Aug 17 04:50:20 PM PDT 24
Peak memory 164800 kb
Host smart-80f839f2-0f82-4413-9cea-846b1e2ba8d4
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3598759664 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.3598759664
Directory /workspace/8.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.3545574400
Short name T48
Test name
Test status
Simulation time 1072850000 ps
CPU time 3.7 seconds
Started Aug 17 04:49:54 PM PDT 24
Finished Aug 17 04:50:02 PM PDT 24
Peak memory 164856 kb
Host smart-ec6947a3-7a11-4684-86f4-7fe5311dd375
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3545574400 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.3545574400
Directory /workspace/9.prim_lfsr_gal_smoke/latest
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