Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.31 100.00 96.55 100.00 100.00 95.00


Total tests in report: 200
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
87.31 87.31 100.00 100.00 96.55 96.55 100.00 100.00 100.00 100.00 40.00 40.00 /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.3288067710
95.31 8.00 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 80.00 40.00 /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.1687039767
98.31 3.00 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 95.00 15.00 /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.523632608

Tests that do not contribute to grading

Name
/workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.266491941
/workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.439798867
/workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.2236002417
/workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.2828189562
/workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.2296848657
/workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.4197707897
/workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.4075247650
/workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.23589916
/workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.2386362579
/workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.3605363853
/workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.3841244954
/workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.846792320
/workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.2404374076
/workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.1229114582
/workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.2494849497
/workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.1916716450
/workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.1612805190
/workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.3071347974
/workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.650083339
/workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.1345006591
/workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.1207613686
/workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.290785675
/workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.1736352084
/workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3913896217
/workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.1266010444
/workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.3395645493
/workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.2958498149
/workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.1277892041
/workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.1805758498
/workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.2323097583
/workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.2567841933
/workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.124341366
/workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.4253696308
/workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.2448276374
/workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.3355831665
/workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.1452032623
/workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.1652131572
/workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.626884606
/workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.2054970940
/workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.2785224352
/workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.2884002651
/workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.979794750
/workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.1675638956
/workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.565040505
/workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.644811412
/workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.1332170094
/workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.1461483287
/workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.2384629300
/workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.2305779176
/workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.1374645039
/workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.3856978423
/workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.3082744795
/workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.1710990217
/workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.1311417406
/workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.4242315332
/workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.1501153509
/workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.2824709830
/workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.1834847553
/workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.253443292
/workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.771424987
/workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.671267122
/workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.1642942680
/workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3373440996
/workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.4294338291
/workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.3327387530
/workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.2994831773
/workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.1005398537
/workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.4167976386
/workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.1526564622
/workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.2990436655
/workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.301556586
/workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.2576779571
/workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.1824594498
/workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.2087458224
/workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.3645692355
/workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.2797741146
/workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.1819058747
/workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.579778984
/workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.3173566906
/workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.1471534533
/workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.711986785
/workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.2010373909
/workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.3562925416
/workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.2611839148
/workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.1521833820
/workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.2132460009
/workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.235949801
/workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.913902897
/workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.3066443965
/workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.1332238592
/workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.2762403053
/workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.593577433
/workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.383773388
/workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.1478258677
/workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.328124449
/workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.1710298931
/workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.2493288969
/workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.3519690680
/workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.300662212
/workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.1711148290
/workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.2426927205
/workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.3905493641
/workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.1285418478
/workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.1452742997
/workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.4098540458
/workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.3482098206
/workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.2471489067
/workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.1016723572
/workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.2415790608
/workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.2000196735
/workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.4216983589
/workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.596712603
/workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3388527010
/workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.242979717
/workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.3333685509
/workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.2605181262
/workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.73239830
/workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.825329483
/workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.405837033
/workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.2721608480
/workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.3927441131
/workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.272524988
/workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.892673426
/workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.4220321377
/workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.81220014
/workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.3249145247
/workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.3211901042
/workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.2704096875
/workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.699302815
/workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1341959499
/workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.592505961
/workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.124292874
/workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.2503248715
/workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.3940259182
/workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.4112362507
/workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.2771571738
/workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.233108534
/workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.4251562195
/workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.43956160
/workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.1766864396
/workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.1888344470
/workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.1638985492
/workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.3627440418
/workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.159957420
/workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.226764043
/workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.2300479391
/workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.2333865899
/workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.484285893
/workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.3504478100
/workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.1287071984
/workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.46326942
/workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.392397055
/workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.1179929792
/workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.4048686420
/workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.4234653062
/workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.3114297031
/workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.3917409988
/workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.459828547
/workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.908478432
/workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.2622974899
/workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.3400728927
/workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.1831376023
/workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.2648197540
/workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.2904554207
/workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.2649101389
/workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.1602332859
/workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.3028129640
/workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.625391113
/workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.675506950
/workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.3947050248
/workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.1877363669
/workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.1496058067
/workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.2098199933
/workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.2434255595
/workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.3819419943
/workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.2304463252
/workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.1008489439
/workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.842920518
/workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.3886685316
/workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.1326506709
/workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.1147748620
/workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.715362706
/workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.1499199007
/workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.760528605
/workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.4252194236
/workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.1437000806
/workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.837204793
/workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.4244511280
/workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.1571287271
/workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.3750886689
/workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.3343429790
/workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.4289034916
/workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.3026940968
/workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.3472289892
/workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.505240646
/workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.102144272
/workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.315642559



Total test records in report: 200
tests.html | tests1.html | tests2.html | tests3.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.505240646 Aug 18 05:08:20 PM PDT 24 Aug 18 05:08:32 PM PDT 24 1539190000 ps
T2 /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.315642559 Aug 18 05:08:21 PM PDT 24 Aug 18 05:08:30 PM PDT 24 1326030000 ps
T3 /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.102144272 Aug 18 05:08:20 PM PDT 24 Aug 18 05:08:27 PM PDT 24 1481630000 ps
T7 /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.1602332859 Aug 18 05:08:32 PM PDT 24 Aug 18 05:08:45 PM PDT 24 1616890000 ps
T8 /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.2649101389 Aug 18 05:08:33 PM PDT 24 Aug 18 05:08:41 PM PDT 24 1555710000 ps
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T128 /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.1612805190 Aug 18 05:07:58 PM PDT 24 Aug 18 05:39:20 PM PDT 24 336437970000 ps
T129 /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.2054970940 Aug 18 05:08:20 PM PDT 24 Aug 18 05:37:28 PM PDT 24 336650990000 ps
T130 /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.290785675 Aug 18 05:08:09 PM PDT 24 Aug 18 05:40:25 PM PDT 24 336889250000 ps
T131 /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.2305779176 Aug 18 05:08:00 PM PDT 24 Aug 18 05:44:28 PM PDT 24 336424850000 ps
T132 /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3913896217 Aug 18 05:08:07 PM PDT 24 Aug 18 05:37:52 PM PDT 24 336383990000 ps
T133 /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.2828189562 Aug 18 05:07:59 PM PDT 24 Aug 18 05:39:06 PM PDT 24 336889770000 ps
T134 /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.1675638956 Aug 18 05:08:18 PM PDT 24 Aug 18 05:37:06 PM PDT 24 336969050000 ps
T135 /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.4253696308 Aug 18 05:08:09 PM PDT 24 Aug 18 05:38:13 PM PDT 24 337035650000 ps
T136 /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.1452032623 Aug 18 05:08:10 PM PDT 24 Aug 18 05:40:09 PM PDT 24 336720110000 ps
T137 /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.4075247650 Aug 18 05:08:04 PM PDT 24 Aug 18 05:44:27 PM PDT 24 336633890000 ps
T138 /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.4197707897 Aug 18 05:07:58 PM PDT 24 Aug 18 05:39:21 PM PDT 24 336868710000 ps
T139 /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.2494849497 Aug 18 05:07:57 PM PDT 24 Aug 18 05:35:23 PM PDT 24 336737270000 ps
T140 /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.1916716450 Aug 18 05:07:59 PM PDT 24 Aug 18 05:40:47 PM PDT 24 336304230000 ps
T141 /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.2958498149 Aug 18 05:08:10 PM PDT 24 Aug 18 05:39:59 PM PDT 24 336551310000 ps
T142 /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.626884606 Aug 18 05:08:08 PM PDT 24 Aug 18 05:35:25 PM PDT 24 336995790000 ps
T143 /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.1332170094 Aug 18 05:07:59 PM PDT 24 Aug 18 05:39:00 PM PDT 24 337133150000 ps
T144 /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.2296848657 Aug 18 05:07:59 PM PDT 24 Aug 18 05:40:14 PM PDT 24 337121370000 ps
T145 /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.1736352084 Aug 18 05:08:04 PM PDT 24 Aug 18 05:44:23 PM PDT 24 336931970000 ps
T146 /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.650083339 Aug 18 05:08:00 PM PDT 24 Aug 18 05:41:19 PM PDT 24 336657790000 ps
T147 /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.2567841933 Aug 18 05:08:10 PM PDT 24 Aug 18 05:39:39 PM PDT 24 336986610000 ps
T148 /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.23589916 Aug 18 05:08:04 PM PDT 24 Aug 18 05:44:32 PM PDT 24 336719250000 ps
T149 /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.1345006591 Aug 18 05:08:09 PM PDT 24 Aug 18 05:39:37 PM PDT 24 336867890000 ps
T150 /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.2236002417 Aug 18 05:07:58 PM PDT 24 Aug 18 05:38:47 PM PDT 24 336452610000 ps
T151 /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3388527010 Aug 18 04:21:54 PM PDT 24 Aug 18 04:22:03 PM PDT 24 1495510000 ps
T152 /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.43956160 Aug 18 04:20:46 PM PDT 24 Aug 18 04:20:56 PM PDT 24 1417610000 ps
T153 /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.2771571738 Aug 18 04:22:17 PM PDT 24 Aug 18 04:22:27 PM PDT 24 1547610000 ps
T154 /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.3333685509 Aug 18 04:22:10 PM PDT 24 Aug 18 04:22:17 PM PDT 24 1517750000 ps
T155 /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.3482098206 Aug 18 04:22:16 PM PDT 24 Aug 18 04:22:27 PM PDT 24 1560290000 ps
T156 /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.699302815 Aug 18 04:17:20 PM PDT 24 Aug 18 04:17:29 PM PDT 24 1339990000 ps
T157 /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.596712603 Aug 18 04:18:22 PM PDT 24 Aug 18 04:18:33 PM PDT 24 1551610000 ps
T158 /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.1766864396 Aug 18 04:22:28 PM PDT 24 Aug 18 04:22:36 PM PDT 24 1350070000 ps
T159 /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.1452742997 Aug 18 04:21:54 PM PDT 24 Aug 18 04:22:04 PM PDT 24 1492670000 ps
T160 /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.892673426 Aug 18 04:22:18 PM PDT 24 Aug 18 04:22:25 PM PDT 24 1346890000 ps
T161 /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.2721608480 Aug 18 04:21:56 PM PDT 24 Aug 18 04:22:05 PM PDT 24 1567890000 ps
T162 /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.2704096875 Aug 18 04:17:54 PM PDT 24 Aug 18 04:18:04 PM PDT 24 1224930000 ps
T163 /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.3249145247 Aug 18 04:17:55 PM PDT 24 Aug 18 04:18:07 PM PDT 24 1510690000 ps
T164 /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.1711148290 Aug 18 04:21:36 PM PDT 24 Aug 18 04:21:44 PM PDT 24 1454270000 ps
T165 /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.4216983589 Aug 18 04:21:38 PM PDT 24 Aug 18 04:21:49 PM PDT 24 1579050000 ps
T166 /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.4098540458 Aug 18 04:20:33 PM PDT 24 Aug 18 04:20:42 PM PDT 24 1158550000 ps
T167 /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.242979717 Aug 18 04:19:29 PM PDT 24 Aug 18 04:19:40 PM PDT 24 1507290000 ps
T168 /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.300662212 Aug 18 04:21:52 PM PDT 24 Aug 18 04:22:03 PM PDT 24 1543510000 ps
T169 /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.1285418478 Aug 18 04:22:18 PM PDT 24 Aug 18 04:22:26 PM PDT 24 1297090000 ps
T170 /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.3927441131 Aug 18 04:22:29 PM PDT 24 Aug 18 04:22:40 PM PDT 24 1554610000 ps
T171 /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.272524988 Aug 18 04:22:28 PM PDT 24 Aug 18 04:22:38 PM PDT 24 1562850000 ps
T172 /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.825329483 Aug 18 04:22:16 PM PDT 24 Aug 18 04:22:24 PM PDT 24 1222810000 ps
T173 /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.2333865899 Aug 18 04:22:56 PM PDT 24 Aug 18 04:23:04 PM PDT 24 1528190000 ps
T174 /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.233108534 Aug 18 04:19:19 PM PDT 24 Aug 18 04:19:29 PM PDT 24 1309590000 ps
T175 /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.2605181262 Aug 18 04:22:12 PM PDT 24 Aug 18 04:22:20 PM PDT 24 1395710000 ps
T176 /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.3940259182 Aug 18 04:18:44 PM PDT 24 Aug 18 04:18:55 PM PDT 24 1509930000 ps
T177 /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.124292874 Aug 18 04:21:54 PM PDT 24 Aug 18 04:22:03 PM PDT 24 1422990000 ps
T178 /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.1638985492 Aug 18 04:17:18 PM PDT 24 Aug 18 04:17:28 PM PDT 24 1183550000 ps
T179 /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.226764043 Aug 18 04:22:01 PM PDT 24 Aug 18 04:22:08 PM PDT 24 1178430000 ps
T180 /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.2000196735 Aug 18 04:18:25 PM PDT 24 Aug 18 04:18:37 PM PDT 24 1539470000 ps
T181 /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.4112362507 Aug 18 04:17:42 PM PDT 24 Aug 18 04:17:52 PM PDT 24 1553050000 ps
T182 /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.3627440418 Aug 18 04:22:17 PM PDT 24 Aug 18 04:22:24 PM PDT 24 1346490000 ps
T183 /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.592505961 Aug 18 04:22:17 PM PDT 24 Aug 18 04:22:25 PM PDT 24 1494610000 ps
T184 /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.484285893 Aug 18 04:21:58 PM PDT 24 Aug 18 04:22:06 PM PDT 24 1279850000 ps
T185 /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.3211901042 Aug 18 04:22:19 PM PDT 24 Aug 18 04:22:27 PM PDT 24 1593230000 ps
T186 /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.2503248715 Aug 18 04:18:42 PM PDT 24 Aug 18 04:18:52 PM PDT 24 1422550000 ps
T187 /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.3905493641 Aug 18 04:19:29 PM PDT 24 Aug 18 04:19:39 PM PDT 24 1410070000 ps
T188 /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.2415790608 Aug 18 04:22:23 PM PDT 24 Aug 18 04:22:31 PM PDT 24 1250970000 ps
T189 /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.2471489067 Aug 18 04:17:25 PM PDT 24 Aug 18 04:17:35 PM PDT 24 1538290000 ps
T190 /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.1888344470 Aug 18 04:22:18 PM PDT 24 Aug 18 04:22:25 PM PDT 24 1509150000 ps
T191 /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.1016723572 Aug 18 04:22:22 PM PDT 24 Aug 18 04:22:31 PM PDT 24 1569410000 ps
T192 /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.2426927205 Aug 18 04:22:23 PM PDT 24 Aug 18 04:22:34 PM PDT 24 1629950000 ps
T193 /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1341959499 Aug 18 04:22:12 PM PDT 24 Aug 18 04:22:21 PM PDT 24 1532070000 ps
T194 /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.4220321377 Aug 18 04:22:32 PM PDT 24 Aug 18 04:22:40 PM PDT 24 1404690000 ps
T195 /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.159957420 Aug 18 04:21:58 PM PDT 24 Aug 18 04:22:06 PM PDT 24 1310510000 ps
T196 /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.405837033 Aug 18 04:19:16 PM PDT 24 Aug 18 04:19:28 PM PDT 24 1665410000 ps
T197 /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.4251562195 Aug 18 04:20:44 PM PDT 24 Aug 18 04:20:51 PM PDT 24 1058450000 ps
T198 /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.73239830 Aug 18 04:20:44 PM PDT 24 Aug 18 04:20:53 PM PDT 24 1532110000 ps
T199 /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.81220014 Aug 18 04:22:08 PM PDT 24 Aug 18 04:22:16 PM PDT 24 1507610000 ps
T200 /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.2300479391 Aug 18 04:21:57 PM PDT 24 Aug 18 04:22:08 PM PDT 24 1565370000 ps

Test location /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.3288067710
Short name T12
Test name
Test status
Simulation time 1544010000 ps
CPU time 6.65 seconds
Started Aug 18 05:08:20 PM PDT 24
Finished Aug 18 05:08:34 PM PDT 24
Peak memory 164780 kb
Host smart-c07ab61e-4bc4-421f-a3c0-df2df741b8c9
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3288067710 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.3288067710
Directory /workspace/0.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.1687039767
Short name T21
Test name
Test status
Simulation time 336859430000 ps
CPU time 850.14 seconds
Started Aug 18 04:21:38 PM PDT 24
Finished Aug 18 04:57:02 PM PDT 24
Peak memory 158280 kb
Host smart-014c7e97-7a17-4197-9575-6160bd471cd2
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1687039767 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.1687039767
Directory /workspace/12.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.523632608
Short name T25
Test name
Test status
Simulation time 337055590000 ps
CPU time 769.3 seconds
Started Aug 18 05:07:59 PM PDT 24
Finished Aug 18 05:39:26 PM PDT 24
Peak memory 160800 kb
Host smart-8e3ffc79-0faa-451c-bab4-d55c84a7a498
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=523632608 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.523632608
Directory /workspace/16.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.266491941
Short name T117
Test name
Test status
Simulation time 337163990000 ps
CPU time 610.67 seconds
Started Aug 18 05:07:49 PM PDT 24
Finished Aug 18 05:33:11 PM PDT 24
Peak memory 160784 kb
Host smart-b24f0778-fd32-45ad-b6c4-35b402401482
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=266491941 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.266491941
Directory /workspace/0.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.439798867
Short name T124
Test name
Test status
Simulation time 336416730000 ps
CPU time 781.9 seconds
Started Aug 18 05:07:48 PM PDT 24
Finished Aug 18 05:39:31 PM PDT 24
Peak memory 160776 kb
Host smart-dd245e1e-e4ab-49b0-a45d-97db1943ddab
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=439798867 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.439798867
Directory /workspace/1.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.2236002417
Short name T150
Test name
Test status
Simulation time 336452610000 ps
CPU time 756.46 seconds
Started Aug 18 05:07:58 PM PDT 24
Finished Aug 18 05:38:47 PM PDT 24
Peak memory 160772 kb
Host smart-ba7d8335-9ec2-4065-9661-a43430ba7c5a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2236002417 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.2236002417
Directory /workspace/10.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.2828189562
Short name T133
Test name
Test status
Simulation time 336889770000 ps
CPU time 764.2 seconds
Started Aug 18 05:07:59 PM PDT 24
Finished Aug 18 05:39:06 PM PDT 24
Peak memory 160672 kb
Host smart-50701986-9abf-4939-8732-ea96c16d93ce
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2828189562 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.2828189562
Directory /workspace/11.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.2296848657
Short name T144
Test name
Test status
Simulation time 337121370000 ps
CPU time 794.38 seconds
Started Aug 18 05:07:59 PM PDT 24
Finished Aug 18 05:40:14 PM PDT 24
Peak memory 160784 kb
Host smart-e67aa081-18b7-4ff5-8ac7-2e0814a7fd30
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2296848657 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.2296848657
Directory /workspace/12.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.4197707897
Short name T138
Test name
Test status
Simulation time 336868710000 ps
CPU time 777.78 seconds
Started Aug 18 05:07:58 PM PDT 24
Finished Aug 18 05:39:21 PM PDT 24
Peak memory 160816 kb
Host smart-aac06c16-ea6e-4ab3-804e-d67cec33b972
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4197707897 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.4197707897
Directory /workspace/13.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.4075247650
Short name T137
Test name
Test status
Simulation time 336633890000 ps
CPU time 884.81 seconds
Started Aug 18 05:08:04 PM PDT 24
Finished Aug 18 05:44:27 PM PDT 24
Peak memory 160732 kb
Host smart-0da1242e-3aa2-4fef-80ea-e4891974c8d9
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4075247650 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.4075247650
Directory /workspace/14.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.23589916
Short name T148
Test name
Test status
Simulation time 336719250000 ps
CPU time 885 seconds
Started Aug 18 05:08:04 PM PDT 24
Finished Aug 18 05:44:32 PM PDT 24
Peak memory 160704 kb
Host smart-aa85bf5f-eb8f-4c3a-8c0f-8ad730bbb2b4
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=23589916 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.23589916
Directory /workspace/15.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.2386362579
Short name T113
Test name
Test status
Simulation time 336766530000 ps
CPU time 880.74 seconds
Started Aug 18 05:08:04 PM PDT 24
Finished Aug 18 05:44:24 PM PDT 24
Peak memory 160732 kb
Host smart-d981563c-c38e-46e7-b2b5-a1c9ff6c6e9a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2386362579 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.2386362579
Directory /workspace/17.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.3605363853
Short name T5
Test name
Test status
Simulation time 336987430000 ps
CPU time 784 seconds
Started Aug 18 05:07:59 PM PDT 24
Finished Aug 18 05:39:47 PM PDT 24
Peak memory 160812 kb
Host smart-1fc69ef2-c820-47c9-baca-0eda6062645d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3605363853 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.3605363853
Directory /workspace/18.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.3841244954
Short name T126
Test name
Test status
Simulation time 336528870000 ps
CPU time 770.1 seconds
Started Aug 18 05:07:58 PM PDT 24
Finished Aug 18 05:38:56 PM PDT 24
Peak memory 160736 kb
Host smart-40af8ab7-3100-438a-81d9-a166a98c4553
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3841244954 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.3841244954
Directory /workspace/19.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.846792320
Short name T112
Test name
Test status
Simulation time 336471650000 ps
CPU time 656.59 seconds
Started Aug 18 05:07:58 PM PDT 24
Finished Aug 18 05:34:51 PM PDT 24
Peak memory 160788 kb
Host smart-6c7e9437-302b-4549-906f-65b3a843fa44
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=846792320 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.846792320
Directory /workspace/2.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.2404374076
Short name T30
Test name
Test status
Simulation time 336575550000 ps
CPU time 769.74 seconds
Started Aug 18 05:07:58 PM PDT 24
Finished Aug 18 05:39:20 PM PDT 24
Peak memory 160804 kb
Host smart-8bb04a6c-ef7a-4032-9262-9b9569ff3ec3
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2404374076 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.2404374076
Directory /workspace/20.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.1229114582
Short name T125
Test name
Test status
Simulation time 336336590000 ps
CPU time 886.46 seconds
Started Aug 18 05:08:00 PM PDT 24
Finished Aug 18 05:44:28 PM PDT 24
Peak memory 160788 kb
Host smart-ca589e9d-f931-434f-bae5-3cd1d86edeab
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1229114582 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.1229114582
Directory /workspace/21.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.2494849497
Short name T139
Test name
Test status
Simulation time 336737270000 ps
CPU time 673.28 seconds
Started Aug 18 05:07:57 PM PDT 24
Finished Aug 18 05:35:23 PM PDT 24
Peak memory 160812 kb
Host smart-d4899c28-9381-48ec-bc93-9cd9bc7286e7
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2494849497 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.2494849497
Directory /workspace/22.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.1916716450
Short name T140
Test name
Test status
Simulation time 336304230000 ps
CPU time 801.57 seconds
Started Aug 18 05:07:59 PM PDT 24
Finished Aug 18 05:40:47 PM PDT 24
Peak memory 160688 kb
Host smart-f01e654e-12de-40ee-b56e-79b8fcbb562e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1916716450 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.1916716450
Directory /workspace/23.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.1612805190
Short name T128
Test name
Test status
Simulation time 336437970000 ps
CPU time 759.78 seconds
Started Aug 18 05:07:58 PM PDT 24
Finished Aug 18 05:39:20 PM PDT 24
Peak memory 160688 kb
Host smart-a2d9fae9-8c77-4ef2-9ae8-cfb9403e03b2
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1612805190 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.1612805190
Directory /workspace/24.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.3071347974
Short name T28
Test name
Test status
Simulation time 336946810000 ps
CPU time 813.85 seconds
Started Aug 18 05:07:59 PM PDT 24
Finished Aug 18 05:41:00 PM PDT 24
Peak memory 160748 kb
Host smart-ac120a2b-13f1-49cf-a970-b785ebd87b7f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3071347974 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.3071347974
Directory /workspace/25.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.650083339
Short name T146
Test name
Test status
Simulation time 336657790000 ps
CPU time 815.37 seconds
Started Aug 18 05:08:00 PM PDT 24
Finished Aug 18 05:41:19 PM PDT 24
Peak memory 160732 kb
Host smart-4cf04259-683e-44eb-8212-eebc02d10714
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=650083339 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.650083339
Directory /workspace/26.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.1345006591
Short name T149
Test name
Test status
Simulation time 336867890000 ps
CPU time 771.12 seconds
Started Aug 18 05:08:09 PM PDT 24
Finished Aug 18 05:39:37 PM PDT 24
Peak memory 160788 kb
Host smart-e8f4e50c-9fcb-46e9-91d9-9b2784bbdd7e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1345006591 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.1345006591
Directory /workspace/27.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.1207613686
Short name T29
Test name
Test status
Simulation time 336436610000 ps
CPU time 767.82 seconds
Started Aug 18 05:08:08 PM PDT 24
Finished Aug 18 05:39:11 PM PDT 24
Peak memory 160812 kb
Host smart-318c87a2-3843-4eae-bc97-254d7a79e3a1
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1207613686 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.1207613686
Directory /workspace/28.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.290785675
Short name T130
Test name
Test status
Simulation time 336889250000 ps
CPU time 790.25 seconds
Started Aug 18 05:08:09 PM PDT 24
Finished Aug 18 05:40:25 PM PDT 24
Peak memory 160748 kb
Host smart-a9fbf763-9913-46eb-918b-e6a3d12f7cdf
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=290785675 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.290785675
Directory /workspace/29.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.1736352084
Short name T145
Test name
Test status
Simulation time 336931970000 ps
CPU time 887.31 seconds
Started Aug 18 05:08:04 PM PDT 24
Finished Aug 18 05:44:23 PM PDT 24
Peak memory 160724 kb
Host smart-c173d16a-ef2c-4d41-b39b-7504fd12c964
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1736352084 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.1736352084
Directory /workspace/3.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3913896217
Short name T132
Test name
Test status
Simulation time 336383990000 ps
CPU time 725.15 seconds
Started Aug 18 05:08:07 PM PDT 24
Finished Aug 18 05:37:52 PM PDT 24
Peak memory 160716 kb
Host smart-2fc5a2c8-1d87-4bbc-b742-f3649f9ede3a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3913896217 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.3913896217
Directory /workspace/30.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.1266010444
Short name T111
Test name
Test status
Simulation time 336521150000 ps
CPU time 702.84 seconds
Started Aug 18 05:08:10 PM PDT 24
Finished Aug 18 05:37:08 PM PDT 24
Peak memory 160852 kb
Host smart-1eed2f9a-64d1-44aa-b1be-29b98a4768d4
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1266010444 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.1266010444
Directory /workspace/31.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.3395645493
Short name T127
Test name
Test status
Simulation time 336953050000 ps
CPU time 770.12 seconds
Started Aug 18 05:08:10 PM PDT 24
Finished Aug 18 05:39:30 PM PDT 24
Peak memory 160816 kb
Host smart-7da4c114-16a7-4782-8a69-f7ac7767e037
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3395645493 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.3395645493
Directory /workspace/32.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.2958498149
Short name T141
Test name
Test status
Simulation time 336551310000 ps
CPU time 778.62 seconds
Started Aug 18 05:08:10 PM PDT 24
Finished Aug 18 05:39:59 PM PDT 24
Peak memory 160808 kb
Host smart-0af9724c-1053-49c9-8d18-945a9ff00d4a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2958498149 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.2958498149
Directory /workspace/33.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.1277892041
Short name T115
Test name
Test status
Simulation time 336436290000 ps
CPU time 781.38 seconds
Started Aug 18 05:08:09 PM PDT 24
Finished Aug 18 05:39:53 PM PDT 24
Peak memory 160804 kb
Host smart-71446d5d-2a71-4bde-bcda-8ca828989fc0
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1277892041 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.1277892041
Directory /workspace/34.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.1805758498
Short name T4
Test name
Test status
Simulation time 336368050000 ps
CPU time 691.3 seconds
Started Aug 18 05:08:08 PM PDT 24
Finished Aug 18 05:36:16 PM PDT 24
Peak memory 160816 kb
Host smart-482cb6d9-7f7f-45c3-ad1e-a26787357fbf
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1805758498 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.1805758498
Directory /workspace/35.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.2323097583
Short name T114
Test name
Test status
Simulation time 336380730000 ps
CPU time 710.97 seconds
Started Aug 18 05:08:09 PM PDT 24
Finished Aug 18 05:37:02 PM PDT 24
Peak memory 160692 kb
Host smart-19ef8c88-8b51-440b-b4de-29402a3620d4
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2323097583 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.2323097583
Directory /workspace/36.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.2567841933
Short name T147
Test name
Test status
Simulation time 336986610000 ps
CPU time 771.83 seconds
Started Aug 18 05:08:10 PM PDT 24
Finished Aug 18 05:39:39 PM PDT 24
Peak memory 160728 kb
Host smart-350553d3-01d1-4afb-ba28-0d467d4eff29
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2567841933 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.2567841933
Directory /workspace/37.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.124341366
Short name T26
Test name
Test status
Simulation time 336729450000 ps
CPU time 761.03 seconds
Started Aug 18 05:08:09 PM PDT 24
Finished Aug 18 05:38:59 PM PDT 24
Peak memory 160796 kb
Host smart-aac03bf4-ab65-41f6-83ef-9272a8edc403
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=124341366 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.124341366
Directory /workspace/38.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.4253696308
Short name T135
Test name
Test status
Simulation time 337035650000 ps
CPU time 745.59 seconds
Started Aug 18 05:08:09 PM PDT 24
Finished Aug 18 05:38:13 PM PDT 24
Peak memory 160736 kb
Host smart-9cbe76fa-74f5-47a7-8626-9f1ccda2be4c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4253696308 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.4253696308
Directory /workspace/39.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.2448276374
Short name T24
Test name
Test status
Simulation time 336428610000 ps
CPU time 772.77 seconds
Started Aug 18 05:07:59 PM PDT 24
Finished Aug 18 05:39:07 PM PDT 24
Peak memory 160804 kb
Host smart-7177c432-dd62-4937-8a10-d6d4681aa679
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2448276374 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.2448276374
Directory /workspace/4.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.3355831665
Short name T123
Test name
Test status
Simulation time 336439090000 ps
CPU time 673.85 seconds
Started Aug 18 05:08:09 PM PDT 24
Finished Aug 18 05:35:42 PM PDT 24
Peak memory 160804 kb
Host smart-62a44771-7c01-4769-adc7-ee587c942f35
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3355831665 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.3355831665
Directory /workspace/40.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.1452032623
Short name T136
Test name
Test status
Simulation time 336720110000 ps
CPU time 783.87 seconds
Started Aug 18 05:08:10 PM PDT 24
Finished Aug 18 05:40:09 PM PDT 24
Peak memory 160736 kb
Host smart-31adb215-acec-4883-ac3a-936bf79bb41f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1452032623 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.1452032623
Directory /workspace/41.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.1652131572
Short name T27
Test name
Test status
Simulation time 337068310000 ps
CPU time 885.89 seconds
Started Aug 18 05:08:10 PM PDT 24
Finished Aug 18 05:44:34 PM PDT 24
Peak memory 160788 kb
Host smart-3dd7e659-ec26-420f-9a37-6bbdcebaebd9
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1652131572 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.1652131572
Directory /workspace/42.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.626884606
Short name T142
Test name
Test status
Simulation time 336995790000 ps
CPU time 666.44 seconds
Started Aug 18 05:08:08 PM PDT 24
Finished Aug 18 05:35:25 PM PDT 24
Peak memory 160732 kb
Host smart-e483aaf3-a01e-4b37-b076-62d22b792165
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=626884606 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.626884606
Directory /workspace/43.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.2054970940
Short name T129
Test name
Test status
Simulation time 336650990000 ps
CPU time 715.99 seconds
Started Aug 18 05:08:20 PM PDT 24
Finished Aug 18 05:37:28 PM PDT 24
Peak memory 160816 kb
Host smart-793e1a60-c46a-409c-97ff-f5dbe2c1cc56
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2054970940 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.2054970940
Directory /workspace/44.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.2785224352
Short name T116
Test name
Test status
Simulation time 336957590000 ps
CPU time 926.53 seconds
Started Aug 18 05:08:20 PM PDT 24
Finished Aug 18 05:46:06 PM PDT 24
Peak memory 160792 kb
Host smart-c614e0c2-3a88-4841-aae3-057462edb2ad
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2785224352 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.2785224352
Directory /workspace/45.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.2884002651
Short name T121
Test name
Test status
Simulation time 336938730000 ps
CPU time 781.53 seconds
Started Aug 18 05:08:21 PM PDT 24
Finished Aug 18 05:39:52 PM PDT 24
Peak memory 160812 kb
Host smart-2ce040ba-18b1-4800-86e9-494432a0fa3a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2884002651 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.2884002651
Directory /workspace/46.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.979794750
Short name T6
Test name
Test status
Simulation time 337103910000 ps
CPU time 723.11 seconds
Started Aug 18 05:08:19 PM PDT 24
Finished Aug 18 05:37:50 PM PDT 24
Peak memory 160704 kb
Host smart-291e9b86-d1f6-4fd5-b712-9e882020316a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=979794750 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.979794750
Directory /workspace/47.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.1675638956
Short name T134
Test name
Test status
Simulation time 336969050000 ps
CPU time 699.09 seconds
Started Aug 18 05:08:18 PM PDT 24
Finished Aug 18 05:37:06 PM PDT 24
Peak memory 160700 kb
Host smart-0674dea8-f17b-4057-8b4c-fdcb79bc3c3b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1675638956 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.1675638956
Directory /workspace/48.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.565040505
Short name T119
Test name
Test status
Simulation time 336364930000 ps
CPU time 749.96 seconds
Started Aug 18 05:08:20 PM PDT 24
Finished Aug 18 05:38:58 PM PDT 24
Peak memory 160732 kb
Host smart-f3af4133-7bc2-4093-923b-5bd55d24952f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=565040505 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.565040505
Directory /workspace/49.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.644811412
Short name T118
Test name
Test status
Simulation time 336806230000 ps
CPU time 669.61 seconds
Started Aug 18 05:07:58 PM PDT 24
Finished Aug 18 05:35:24 PM PDT 24
Peak memory 160788 kb
Host smart-0078a4e2-a5b1-4c2d-832c-0ed81614ddc6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=644811412 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.644811412
Directory /workspace/5.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.1332170094
Short name T143
Test name
Test status
Simulation time 337133150000 ps
CPU time 763.37 seconds
Started Aug 18 05:07:59 PM PDT 24
Finished Aug 18 05:39:00 PM PDT 24
Peak memory 160708 kb
Host smart-1c482fbc-f6ac-4920-9880-2a4f0a56a0e5
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1332170094 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.1332170094
Directory /workspace/6.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.1461483287
Short name T122
Test name
Test status
Simulation time 337054610000 ps
CPU time 930.9 seconds
Started Aug 18 05:07:59 PM PDT 24
Finished Aug 18 05:45:30 PM PDT 24
Peak memory 160772 kb
Host smart-fe8ba1f3-1c54-4ea2-8766-f179f6a4538a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1461483287 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.1461483287
Directory /workspace/7.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.2384629300
Short name T120
Test name
Test status
Simulation time 336539370000 ps
CPU time 737.27 seconds
Started Aug 18 05:07:58 PM PDT 24
Finished Aug 18 05:37:50 PM PDT 24
Peak memory 160808 kb
Host smart-ac63de0b-cae8-46b3-931e-1e6ebe4bf696
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2384629300 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.2384629300
Directory /workspace/8.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.2305779176
Short name T131
Test name
Test status
Simulation time 336424850000 ps
CPU time 887 seconds
Started Aug 18 05:08:00 PM PDT 24
Finished Aug 18 05:44:28 PM PDT 24
Peak memory 160768 kb
Host smart-b561cb1b-c54f-452b-91b3-7ab935cfda6b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2305779176 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.2305779176
Directory /workspace/9.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.1374645039
Short name T108
Test name
Test status
Simulation time 336631530000 ps
CPU time 581.7 seconds
Started Aug 18 04:17:44 PM PDT 24
Finished Aug 18 04:42:45 PM PDT 24
Peak memory 159812 kb
Host smart-a072b5fe-c55e-497f-8793-2c6c3d5607f6
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1374645039 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.1374645039
Directory /workspace/0.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.3856978423
Short name T103
Test name
Test status
Simulation time 336568270000 ps
CPU time 819.24 seconds
Started Aug 18 04:18:34 PM PDT 24
Finished Aug 18 04:52:17 PM PDT 24
Peak memory 160848 kb
Host smart-50f551d2-8b39-432e-8e1b-43ca9e66eb7c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3856978423 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.3856978423
Directory /workspace/1.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.3082744795
Short name T71
Test name
Test status
Simulation time 336929170000 ps
CPU time 850.41 seconds
Started Aug 18 04:22:18 PM PDT 24
Finished Aug 18 04:57:42 PM PDT 24
Peak memory 160024 kb
Host smart-8fb08a2c-1cc3-4015-a0c0-93fd2a534a92
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3082744795 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.3082744795
Directory /workspace/10.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.1710990217
Short name T110
Test name
Test status
Simulation time 337006570000 ps
CPU time 853.02 seconds
Started Aug 18 04:21:39 PM PDT 24
Finished Aug 18 04:57:18 PM PDT 24
Peak memory 160316 kb
Host smart-cf5d1172-d3ab-4844-a70f-41db7d196e7e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1710990217 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.1710990217
Directory /workspace/11.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.1311417406
Short name T89
Test name
Test status
Simulation time 336986510000 ps
CPU time 855.81 seconds
Started Aug 18 04:21:38 PM PDT 24
Finished Aug 18 04:57:13 PM PDT 24
Peak memory 158236 kb
Host smart-a0bd6f83-1c1e-4978-9552-0fda149b6259
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1311417406 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.1311417406
Directory /workspace/13.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.4242315332
Short name T106
Test name
Test status
Simulation time 336719810000 ps
CPU time 855.73 seconds
Started Aug 18 04:22:17 PM PDT 24
Finished Aug 18 04:57:47 PM PDT 24
Peak memory 160608 kb
Host smart-dec08d10-2358-416a-aa5f-b51c17e00602
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4242315332 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.4242315332
Directory /workspace/14.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.1501153509
Short name T74
Test name
Test status
Simulation time 336588790000 ps
CPU time 858.95 seconds
Started Aug 18 04:22:17 PM PDT 24
Finished Aug 18 04:57:43 PM PDT 24
Peak memory 160612 kb
Host smart-f1d8ac81-3680-46b4-b8c3-a80d67d4e2a8
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1501153509 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.1501153509
Directory /workspace/15.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.2824709830
Short name T99
Test name
Test status
Simulation time 336971370000 ps
CPU time 764.93 seconds
Started Aug 18 04:22:29 PM PDT 24
Finished Aug 18 04:53:35 PM PDT 24
Peak memory 160500 kb
Host smart-b0ad1878-6f68-45ef-bd8c-2ad3d5cb8a44
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2824709830 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.2824709830
Directory /workspace/16.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.1834847553
Short name T14
Test name
Test status
Simulation time 336646710000 ps
CPU time 813.3 seconds
Started Aug 18 04:21:39 PM PDT 24
Finished Aug 18 04:56:00 PM PDT 24
Peak memory 160272 kb
Host smart-051f7cb6-ea7d-4863-96b5-ee5959beaf7b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1834847553 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.1834847553
Directory /workspace/17.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.253443292
Short name T95
Test name
Test status
Simulation time 336594030000 ps
CPU time 755.03 seconds
Started Aug 18 04:22:29 PM PDT 24
Finished Aug 18 04:53:27 PM PDT 24
Peak memory 160496 kb
Host smart-592d747d-704a-4d64-a0ac-e9373485765f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=253443292 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.253443292
Directory /workspace/18.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.771424987
Short name T107
Test name
Test status
Simulation time 336642730000 ps
CPU time 912.22 seconds
Started Aug 18 04:21:52 PM PDT 24
Finished Aug 18 04:58:57 PM PDT 24
Peak memory 160588 kb
Host smart-3e5931ca-fb2f-4680-aeb9-f50e339d6475
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=771424987 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.771424987
Directory /workspace/19.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.671267122
Short name T94
Test name
Test status
Simulation time 336566010000 ps
CPU time 671.03 seconds
Started Aug 18 04:22:29 PM PDT 24
Finished Aug 18 04:50:18 PM PDT 24
Peak memory 160596 kb
Host smart-1bf2f991-7f96-4bf4-a26a-eb9ddfa2a911
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=671267122 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.671267122
Directory /workspace/2.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.1642942680
Short name T73
Test name
Test status
Simulation time 336703130000 ps
CPU time 581.97 seconds
Started Aug 18 04:22:21 PM PDT 24
Finished Aug 18 04:46:24 PM PDT 24
Peak memory 160432 kb
Host smart-c83ad08e-cd06-4ea6-b836-601f5f1daedb
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1642942680 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.1642942680
Directory /workspace/20.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3373440996
Short name T82
Test name
Test status
Simulation time 336967370000 ps
CPU time 878.24 seconds
Started Aug 18 04:18:25 PM PDT 24
Finished Aug 18 04:53:45 PM PDT 24
Peak memory 160632 kb
Host smart-08308793-dd65-480e-a707-c6b4c5fc139a
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3373440996 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.3373440996
Directory /workspace/21.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.4294338291
Short name T88
Test name
Test status
Simulation time 336659130000 ps
CPU time 908.47 seconds
Started Aug 18 04:18:08 PM PDT 24
Finished Aug 18 04:55:10 PM PDT 24
Peak memory 160632 kb
Host smart-0bf5ce8a-95d7-4c24-8e7f-f7dbfc4ba1b5
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4294338291 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.4294338291
Directory /workspace/22.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.3327387530
Short name T84
Test name
Test status
Simulation time 336836850000 ps
CPU time 579.31 seconds
Started Aug 18 04:22:13 PM PDT 24
Finished Aug 18 04:46:05 PM PDT 24
Peak memory 159760 kb
Host smart-031867e4-69e5-4016-8554-646d23163502
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3327387530 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.3327387530
Directory /workspace/23.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.2994831773
Short name T72
Test name
Test status
Simulation time 336540070000 ps
CPU time 634.75 seconds
Started Aug 18 04:22:34 PM PDT 24
Finished Aug 18 04:48:25 PM PDT 24
Peak memory 160648 kb
Host smart-52a8a2b9-7406-4fc0-95f5-368acbb1669e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2994831773 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.2994831773
Directory /workspace/24.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.1005398537
Short name T85
Test name
Test status
Simulation time 337082570000 ps
CPU time 817.03 seconds
Started Aug 18 04:17:35 PM PDT 24
Finished Aug 18 04:50:59 PM PDT 24
Peak memory 160856 kb
Host smart-4ea6e933-d194-43a0-a9b8-06e408cc73f4
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1005398537 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.1005398537
Directory /workspace/25.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.4167976386
Short name T19
Test name
Test status
Simulation time 336755170000 ps
CPU time 932.13 seconds
Started Aug 18 04:20:26 PM PDT 24
Finished Aug 18 04:58:12 PM PDT 24
Peak memory 160600 kb
Host smart-48c9db8c-a09a-4bdc-9c2a-851e7185541d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4167976386 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.4167976386
Directory /workspace/26.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.1526564622
Short name T92
Test name
Test status
Simulation time 336803110000 ps
CPU time 808.15 seconds
Started Aug 18 04:19:18 PM PDT 24
Finished Aug 18 04:52:39 PM PDT 24
Peak memory 160856 kb
Host smart-965afe75-5fc1-40b8-917a-e27076a14003
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1526564622 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.1526564622
Directory /workspace/27.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.2990436655
Short name T96
Test name
Test status
Simulation time 336326750000 ps
CPU time 735.57 seconds
Started Aug 18 04:22:23 PM PDT 24
Finished Aug 18 04:53:09 PM PDT 24
Peak memory 160344 kb
Host smart-f0f9aa6d-34af-428f-bfd2-c94be1372f6c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2990436655 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.2990436655
Directory /workspace/28.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.301556586
Short name T16
Test name
Test status
Simulation time 336686570000 ps
CPU time 685.75 seconds
Started Aug 18 04:20:45 PM PDT 24
Finished Aug 18 04:49:03 PM PDT 24
Peak memory 160580 kb
Host smart-83081c66-b2f0-4a4a-8631-d64f75d69e0c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=301556586 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.301556586
Directory /workspace/29.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.2576779571
Short name T98
Test name
Test status
Simulation time 336852510000 ps
CPU time 614.75 seconds
Started Aug 18 04:21:54 PM PDT 24
Finished Aug 18 04:47:07 PM PDT 24
Peak memory 160132 kb
Host smart-79d5c77a-7bb5-423b-a708-8dcf5702f1c7
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2576779571 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.2576779571
Directory /workspace/3.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.1824594498
Short name T93
Test name
Test status
Simulation time 336861910000 ps
CPU time 676.08 seconds
Started Aug 18 04:22:23 PM PDT 24
Finished Aug 18 04:50:13 PM PDT 24
Peak memory 160636 kb
Host smart-fa5897e6-9b0f-4f99-8a3d-f6baf74c8876
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1824594498 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.1824594498
Directory /workspace/30.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.2087458224
Short name T86
Test name
Test status
Simulation time 336530990000 ps
CPU time 669.62 seconds
Started Aug 18 04:22:23 PM PDT 24
Finished Aug 18 04:50:03 PM PDT 24
Peak memory 160632 kb
Host smart-e00a67f8-d2b5-4352-a0a2-7c916886f48e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2087458224 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.2087458224
Directory /workspace/31.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.3645692355
Short name T23
Test name
Test status
Simulation time 337043290000 ps
CPU time 741.71 seconds
Started Aug 18 04:22:12 PM PDT 24
Finished Aug 18 04:53:07 PM PDT 24
Peak memory 159736 kb
Host smart-0d4aabc9-668b-4c07-b79b-d4bc3f4b93cf
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3645692355 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.3645692355
Directory /workspace/32.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.2797741146
Short name T83
Test name
Test status
Simulation time 336685650000 ps
CPU time 645.22 seconds
Started Aug 18 04:21:56 PM PDT 24
Finished Aug 18 04:48:27 PM PDT 24
Peak memory 159648 kb
Host smart-6946e427-211f-4795-b352-121dc2e221ed
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2797741146 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.2797741146
Directory /workspace/33.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.1819058747
Short name T87
Test name
Test status
Simulation time 336827390000 ps
CPU time 743.11 seconds
Started Aug 18 04:22:21 PM PDT 24
Finished Aug 18 04:53:20 PM PDT 24
Peak memory 160232 kb
Host smart-72ac6cc3-355f-4459-84b6-f2c6c9883674
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1819058747 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.1819058747
Directory /workspace/34.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.579778984
Short name T101
Test name
Test status
Simulation time 336548970000 ps
CPU time 652.93 seconds
Started Aug 18 04:22:17 PM PDT 24
Finished Aug 18 04:49:07 PM PDT 24
Peak memory 160384 kb
Host smart-c2d7bd63-8d41-4860-9333-3f49b35a8971
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=579778984 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.579778984
Directory /workspace/35.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.3173566906
Short name T97
Test name
Test status
Simulation time 336605730000 ps
CPU time 646.14 seconds
Started Aug 18 04:22:12 PM PDT 24
Finished Aug 18 04:49:06 PM PDT 24
Peak memory 160608 kb
Host smart-5ac413bf-301a-4136-9108-7bb1a9e83544
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3173566906 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.3173566906
Directory /workspace/36.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.1471534533
Short name T80
Test name
Test status
Simulation time 336687770000 ps
CPU time 927.52 seconds
Started Aug 18 04:18:05 PM PDT 24
Finished Aug 18 04:55:40 PM PDT 24
Peak memory 160632 kb
Host smart-f1d1e22b-bebb-480a-a728-6f1f1636903e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1471534533 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.1471534533
Directory /workspace/37.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.711986785
Short name T78
Test name
Test status
Simulation time 336946130000 ps
CPU time 865.43 seconds
Started Aug 18 04:18:43 PM PDT 24
Finished Aug 18 04:53:47 PM PDT 24
Peak memory 160624 kb
Host smart-5b528a2f-c6df-434e-9d15-13ae291ad082
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=711986785 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.711986785
Directory /workspace/38.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.2010373909
Short name T76
Test name
Test status
Simulation time 336980270000 ps
CPU time 725.17 seconds
Started Aug 18 04:22:21 PM PDT 24
Finished Aug 18 04:52:54 PM PDT 24
Peak memory 160232 kb
Host smart-2c8098cc-b929-47e7-9e28-f0be66217a88
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2010373909 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.2010373909
Directory /workspace/39.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.3562925416
Short name T100
Test name
Test status
Simulation time 336633050000 ps
CPU time 857.88 seconds
Started Aug 18 04:22:18 PM PDT 24
Finished Aug 18 04:57:45 PM PDT 24
Peak memory 160604 kb
Host smart-70cf6171-93ce-4c61-8162-1621a2cedd05
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3562925416 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.3562925416
Directory /workspace/4.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.2611839148
Short name T81
Test name
Test status
Simulation time 336656030000 ps
CPU time 734.04 seconds
Started Aug 18 04:22:23 PM PDT 24
Finished Aug 18 04:52:56 PM PDT 24
Peak memory 160336 kb
Host smart-bc2dd27b-abcb-4064-b7df-15bb4426a690
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2611839148 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.2611839148
Directory /workspace/40.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.1521833820
Short name T109
Test name
Test status
Simulation time 336359730000 ps
CPU time 939.61 seconds
Started Aug 18 04:20:43 PM PDT 24
Finished Aug 18 04:58:50 PM PDT 24
Peak memory 160600 kb
Host smart-028807fc-b857-4199-a25e-bb99490059d5
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1521833820 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.1521833820
Directory /workspace/41.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.2132460009
Short name T17
Test name
Test status
Simulation time 336545730000 ps
CPU time 921.64 seconds
Started Aug 18 04:18:54 PM PDT 24
Finished Aug 18 04:56:52 PM PDT 24
Peak memory 160632 kb
Host smart-bfeb8e10-0c23-450f-870e-cc7cf09f7c6c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2132460009 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.2132460009
Directory /workspace/42.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.235949801
Short name T18
Test name
Test status
Simulation time 336965970000 ps
CPU time 878.17 seconds
Started Aug 18 04:17:55 PM PDT 24
Finished Aug 18 04:53:25 PM PDT 24
Peak memory 160632 kb
Host smart-aeab51d6-b172-4dfd-be50-c89c9d98aea3
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=235949801 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.235949801
Directory /workspace/43.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.913902897
Short name T20
Test name
Test status
Simulation time 336356670000 ps
CPU time 598.96 seconds
Started Aug 18 04:22:15 PM PDT 24
Finished Aug 18 04:46:42 PM PDT 24
Peak memory 159592 kb
Host smart-584b76d4-2a7d-4ff3-8223-873338815dbe
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=913902897 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.913902897
Directory /workspace/44.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.3066443965
Short name T104
Test name
Test status
Simulation time 336799570000 ps
CPU time 739.39 seconds
Started Aug 18 04:22:22 PM PDT 24
Finished Aug 18 04:53:16 PM PDT 24
Peak memory 160228 kb
Host smart-3cab0208-5b91-47ad-85cb-74174bd25e4b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3066443965 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.3066443965
Directory /workspace/45.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.1332238592
Short name T90
Test name
Test status
Simulation time 336345230000 ps
CPU time 893.74 seconds
Started Aug 18 04:18:56 PM PDT 24
Finished Aug 18 04:55:15 PM PDT 24
Peak memory 160640 kb
Host smart-9b731216-0a52-452f-b782-870223c49af6
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1332238592 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.1332238592
Directory /workspace/46.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.2762403053
Short name T105
Test name
Test status
Simulation time 336370390000 ps
CPU time 666.5 seconds
Started Aug 18 04:22:16 PM PDT 24
Finished Aug 18 04:49:23 PM PDT 24
Peak memory 160344 kb
Host smart-1a9d74b8-1102-4024-8235-5a51310d3986
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2762403053 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.2762403053
Directory /workspace/47.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.593577433
Short name T22
Test name
Test status
Simulation time 336793530000 ps
CPU time 623.08 seconds
Started Aug 18 04:22:31 PM PDT 24
Finished Aug 18 04:47:59 PM PDT 24
Peak memory 160256 kb
Host smart-89940425-0b1b-4f5a-b60a-a3ec30fdf14f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=593577433 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.593577433
Directory /workspace/48.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.383773388
Short name T15
Test name
Test status
Simulation time 336580950000 ps
CPU time 670.13 seconds
Started Aug 18 04:22:28 PM PDT 24
Finished Aug 18 04:50:11 PM PDT 24
Peak memory 160452 kb
Host smart-71794b0f-0204-4a4e-b218-84a8997b24f9
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=383773388 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.383773388
Directory /workspace/49.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.1478258677
Short name T91
Test name
Test status
Simulation time 336687190000 ps
CPU time 783.34 seconds
Started Aug 18 04:20:44 PM PDT 24
Finished Aug 18 04:52:13 PM PDT 24
Peak memory 160656 kb
Host smart-fc102a1d-afc4-4026-bff4-e2c06f8e95ac
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1478258677 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.1478258677
Directory /workspace/5.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.328124449
Short name T77
Test name
Test status
Simulation time 336667850000 ps
CPU time 849.91 seconds
Started Aug 18 04:22:18 PM PDT 24
Finished Aug 18 04:57:40 PM PDT 24
Peak memory 160028 kb
Host smart-bc4623c9-d62f-4ae1-a3e1-b70e04ed4056
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=328124449 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.328124449
Directory /workspace/6.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.1710298931
Short name T102
Test name
Test status
Simulation time 336685430000 ps
CPU time 825.82 seconds
Started Aug 18 04:22:17 PM PDT 24
Finished Aug 18 04:56:46 PM PDT 24
Peak memory 160604 kb
Host smart-d2197fef-cbd6-4b5e-b9aa-c63216d4e476
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1710298931 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.1710298931
Directory /workspace/7.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.2493288969
Short name T79
Test name
Test status
Simulation time 336931850000 ps
CPU time 691.65 seconds
Started Aug 18 04:20:27 PM PDT 24
Finished Aug 18 04:48:45 PM PDT 24
Peak memory 160468 kb
Host smart-0e2cd9d9-f8dd-46f6-a3b0-7b8f0904454e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2493288969 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.2493288969
Directory /workspace/8.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.3519690680
Short name T75
Test name
Test status
Simulation time 336285510000 ps
CPU time 715.84 seconds
Started Aug 18 04:20:10 PM PDT 24
Finished Aug 18 04:49:08 PM PDT 24
Peak memory 160644 kb
Host smart-1c42856d-24aa-4a41-825d-2b04011a66fa
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3519690680 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.3519690680
Directory /workspace/9.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.300662212
Short name T168
Test name
Test status
Simulation time 1543510000 ps
CPU time 4.75 seconds
Started Aug 18 04:21:52 PM PDT 24
Finished Aug 18 04:22:03 PM PDT 24
Peak memory 164680 kb
Host smart-d6a5768c-83fe-45d9-8451-b389f1a3c2b6
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=300662212 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.300662212
Directory /workspace/0.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.1711148290
Short name T164
Test name
Test status
Simulation time 1454270000 ps
CPU time 3.42 seconds
Started Aug 18 04:21:36 PM PDT 24
Finished Aug 18 04:21:44 PM PDT 24
Peak memory 163744 kb
Host smart-228fadf4-0934-494f-825e-ba3ef83bd1ff
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1711148290 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.1711148290
Directory /workspace/1.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.2426927205
Short name T192
Test name
Test status
Simulation time 1629950000 ps
CPU time 4.95 seconds
Started Aug 18 04:22:23 PM PDT 24
Finished Aug 18 04:22:34 PM PDT 24
Peak memory 165884 kb
Host smart-0c82d2b1-3952-4d70-989b-da2c8030b337
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2426927205 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.2426927205
Directory /workspace/10.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.3905493641
Short name T187
Test name
Test status
Simulation time 1410070000 ps
CPU time 4.73 seconds
Started Aug 18 04:19:29 PM PDT 24
Finished Aug 18 04:19:39 PM PDT 24
Peak memory 165004 kb
Host smart-b1862702-9ecb-40d3-b46c-807612693868
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3905493641 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.3905493641
Directory /workspace/11.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.1285418478
Short name T169
Test name
Test status
Simulation time 1297090000 ps
CPU time 3.78 seconds
Started Aug 18 04:22:18 PM PDT 24
Finished Aug 18 04:22:26 PM PDT 24
Peak memory 166040 kb
Host smart-c8cc9128-c830-42a1-8f98-030d60caa225
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1285418478 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.1285418478
Directory /workspace/12.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.1452742997
Short name T159
Test name
Test status
Simulation time 1492670000 ps
CPU time 4.11 seconds
Started Aug 18 04:21:54 PM PDT 24
Finished Aug 18 04:22:04 PM PDT 24
Peak memory 163808 kb
Host smart-f7aff916-34e7-4512-86ee-3b19c4f79566
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1452742997 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.1452742997
Directory /workspace/13.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.4098540458
Short name T166
Test name
Test status
Simulation time 1158550000 ps
CPU time 4.12 seconds
Started Aug 18 04:20:33 PM PDT 24
Finished Aug 18 04:20:42 PM PDT 24
Peak memory 164744 kb
Host smart-f5d85511-4043-4cd8-9da6-fe1c0b51c0d5
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4098540458 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.4098540458
Directory /workspace/14.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.3482098206
Short name T155
Test name
Test status
Simulation time 1560290000 ps
CPU time 4.7 seconds
Started Aug 18 04:22:16 PM PDT 24
Finished Aug 18 04:22:27 PM PDT 24
Peak memory 165876 kb
Host smart-726c347f-c84a-4cf6-a0b6-f79ecdfe51f1
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3482098206 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.3482098206
Directory /workspace/15.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.2471489067
Short name T189
Test name
Test status
Simulation time 1538290000 ps
CPU time 4.7 seconds
Started Aug 18 04:17:25 PM PDT 24
Finished Aug 18 04:17:35 PM PDT 24
Peak memory 164696 kb
Host smart-83011803-e346-4c4b-8888-d701890f06ce
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2471489067 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.2471489067
Directory /workspace/16.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.1016723572
Short name T191
Test name
Test status
Simulation time 1569410000 ps
CPU time 4.03 seconds
Started Aug 18 04:22:22 PM PDT 24
Finished Aug 18 04:22:31 PM PDT 24
Peak memory 164728 kb
Host smart-51921dc6-3519-4087-8804-5bd219603c07
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1016723572 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.1016723572
Directory /workspace/17.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.2415790608
Short name T188
Test name
Test status
Simulation time 1250970000 ps
CPU time 3.74 seconds
Started Aug 18 04:22:23 PM PDT 24
Finished Aug 18 04:22:31 PM PDT 24
Peak memory 165804 kb
Host smart-db63d7ad-3c80-4454-bbd1-d121e3fb41f5
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2415790608 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.2415790608
Directory /workspace/18.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.2000196735
Short name T180
Test name
Test status
Simulation time 1539470000 ps
CPU time 5.22 seconds
Started Aug 18 04:18:25 PM PDT 24
Finished Aug 18 04:18:37 PM PDT 24
Peak memory 164768 kb
Host smart-0458c31a-2a8c-46ae-9b26-aa9980c95848
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2000196735 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.2000196735
Directory /workspace/19.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.4216983589
Short name T165
Test name
Test status
Simulation time 1579050000 ps
CPU time 4.67 seconds
Started Aug 18 04:21:38 PM PDT 24
Finished Aug 18 04:21:49 PM PDT 24
Peak memory 163236 kb
Host smart-cef3855f-3ebc-4dcc-90a0-4350b6fca8d0
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4216983589 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.4216983589
Directory /workspace/2.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.596712603
Short name T157
Test name
Test status
Simulation time 1551610000 ps
CPU time 4.89 seconds
Started Aug 18 04:18:22 PM PDT 24
Finished Aug 18 04:18:33 PM PDT 24
Peak memory 164496 kb
Host smart-22ca1bd3-75e8-4670-b7fc-39671d7358da
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=596712603 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.596712603
Directory /workspace/20.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3388527010
Short name T151
Test name
Test status
Simulation time 1495510000 ps
CPU time 4.04 seconds
Started Aug 18 04:21:54 PM PDT 24
Finished Aug 18 04:22:03 PM PDT 24
Peak memory 164012 kb
Host smart-8ae6144b-9d7f-4249-af85-50e5b6fea2d0
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3388527010 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.3388527010
Directory /workspace/21.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.242979717
Short name T167
Test name
Test status
Simulation time 1507290000 ps
CPU time 4.61 seconds
Started Aug 18 04:19:29 PM PDT 24
Finished Aug 18 04:19:40 PM PDT 24
Peak memory 164932 kb
Host smart-038209f8-065b-4ff2-9ab5-65eaca79a725
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=242979717 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.242979717
Directory /workspace/22.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.3333685509
Short name T154
Test name
Test status
Simulation time 1517750000 ps
CPU time 2.87 seconds
Started Aug 18 04:22:10 PM PDT 24
Finished Aug 18 04:22:17 PM PDT 24
Peak memory 164328 kb
Host smart-7796bf1b-0fe4-4ce7-8147-85889e148b44
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3333685509 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.3333685509
Directory /workspace/23.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.2605181262
Short name T175
Test name
Test status
Simulation time 1395710000 ps
CPU time 3.43 seconds
Started Aug 18 04:22:12 PM PDT 24
Finished Aug 18 04:22:20 PM PDT 24
Peak memory 164692 kb
Host smart-e23bd235-9c7c-4f2f-986a-42870a5d997f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2605181262 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.2605181262
Directory /workspace/24.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.73239830
Short name T198
Test name
Test status
Simulation time 1532110000 ps
CPU time 4.1 seconds
Started Aug 18 04:20:44 PM PDT 24
Finished Aug 18 04:20:53 PM PDT 24
Peak memory 164684 kb
Host smart-1110294e-49cc-4951-ba1b-72a03e71f958
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=73239830 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.73239830
Directory /workspace/25.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.825329483
Short name T172
Test name
Test status
Simulation time 1222810000 ps
CPU time 3.81 seconds
Started Aug 18 04:22:16 PM PDT 24
Finished Aug 18 04:22:24 PM PDT 24
Peak memory 164320 kb
Host smart-2814037e-4b4d-463c-9928-bad8bdb1f4bf
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=825329483 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.825329483
Directory /workspace/26.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.405837033
Short name T196
Test name
Test status
Simulation time 1665410000 ps
CPU time 5.55 seconds
Started Aug 18 04:19:16 PM PDT 24
Finished Aug 18 04:19:28 PM PDT 24
Peak memory 164712 kb
Host smart-42cdb197-6236-4a88-a32b-23bdaa59edf4
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=405837033 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.405837033
Directory /workspace/27.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.2721608480
Short name T161
Test name
Test status
Simulation time 1567890000 ps
CPU time 4.1 seconds
Started Aug 18 04:21:56 PM PDT 24
Finished Aug 18 04:22:05 PM PDT 24
Peak memory 164688 kb
Host smart-24d1450d-4df0-4e01-9b17-da92ad513bee
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2721608480 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.2721608480
Directory /workspace/28.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.3927441131
Short name T170
Test name
Test status
Simulation time 1554610000 ps
CPU time 4.75 seconds
Started Aug 18 04:22:29 PM PDT 24
Finished Aug 18 04:22:40 PM PDT 24
Peak memory 164716 kb
Host smart-dddbabd3-a820-4748-96ba-e69cbbc3ec93
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3927441131 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.3927441131
Directory /workspace/29.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.272524988
Short name T171
Test name
Test status
Simulation time 1562850000 ps
CPU time 4.45 seconds
Started Aug 18 04:22:28 PM PDT 24
Finished Aug 18 04:22:38 PM PDT 24
Peak memory 164652 kb
Host smart-512184fb-192f-4d45-a9e4-54d8b4b24117
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=272524988 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.272524988
Directory /workspace/3.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.892673426
Short name T160
Test name
Test status
Simulation time 1346890000 ps
CPU time 3.13 seconds
Started Aug 18 04:22:18 PM PDT 24
Finished Aug 18 04:22:25 PM PDT 24
Peak memory 164480 kb
Host smart-e6b2f9ab-b515-4045-b4fc-0a151aaa81da
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=892673426 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.892673426
Directory /workspace/30.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.4220321377
Short name T194
Test name
Test status
Simulation time 1404690000 ps
CPU time 3.68 seconds
Started Aug 18 04:22:32 PM PDT 24
Finished Aug 18 04:22:40 PM PDT 24
Peak memory 164720 kb
Host smart-0be6dba9-90c4-4886-a07c-b7e48691eec3
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4220321377 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.4220321377
Directory /workspace/31.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.81220014
Short name T199
Test name
Test status
Simulation time 1507610000 ps
CPU time 3.57 seconds
Started Aug 18 04:22:08 PM PDT 24
Finished Aug 18 04:22:16 PM PDT 24
Peak memory 164708 kb
Host smart-0cb8877f-d4d2-44d7-946d-9f79e1951cb6
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=81220014 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.81220014
Directory /workspace/32.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.3249145247
Short name T163
Test name
Test status
Simulation time 1510690000 ps
CPU time 5.34 seconds
Started Aug 18 04:17:55 PM PDT 24
Finished Aug 18 04:18:07 PM PDT 24
Peak memory 164680 kb
Host smart-77a82f9a-1d8e-441c-8da7-4280da2ed615
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3249145247 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.3249145247
Directory /workspace/33.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.3211901042
Short name T185
Test name
Test status
Simulation time 1593230000 ps
CPU time 3.67 seconds
Started Aug 18 04:22:19 PM PDT 24
Finished Aug 18 04:22:27 PM PDT 24
Peak memory 164660 kb
Host smart-5031cefa-374a-4441-82da-a0bb2fac7bc5
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3211901042 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.3211901042
Directory /workspace/34.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.2704096875
Short name T162
Test name
Test status
Simulation time 1224930000 ps
CPU time 4.56 seconds
Started Aug 18 04:17:54 PM PDT 24
Finished Aug 18 04:18:04 PM PDT 24
Peak memory 164688 kb
Host smart-defe32f8-5040-43b7-b4eb-2d675180d7b4
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2704096875 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.2704096875
Directory /workspace/35.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.699302815
Short name T156
Test name
Test status
Simulation time 1339990000 ps
CPU time 4.17 seconds
Started Aug 18 04:17:20 PM PDT 24
Finished Aug 18 04:17:29 PM PDT 24
Peak memory 164684 kb
Host smart-c74ee7ae-3118-4410-a2bc-bd4284e36c8e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=699302815 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.699302815
Directory /workspace/36.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1341959499
Short name T193
Test name
Test status
Simulation time 1532070000 ps
CPU time 4.19 seconds
Started Aug 18 04:22:12 PM PDT 24
Finished Aug 18 04:22:21 PM PDT 24
Peak memory 164692 kb
Host smart-17ef3419-bb45-4825-b555-32d272c5c723
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1341959499 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.1341959499
Directory /workspace/37.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.592505961
Short name T183
Test name
Test status
Simulation time 1494610000 ps
CPU time 3.5 seconds
Started Aug 18 04:22:17 PM PDT 24
Finished Aug 18 04:22:25 PM PDT 24
Peak memory 164476 kb
Host smart-5f4f070b-f732-4900-9529-e4e17ce41d0d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=592505961 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.592505961
Directory /workspace/38.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.124292874
Short name T177
Test name
Test status
Simulation time 1422990000 ps
CPU time 4.19 seconds
Started Aug 18 04:21:54 PM PDT 24
Finished Aug 18 04:22:03 PM PDT 24
Peak memory 163540 kb
Host smart-97f096d6-0a79-443b-94b6-85dfa2938884
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=124292874 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.124292874
Directory /workspace/39.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.2503248715
Short name T186
Test name
Test status
Simulation time 1422550000 ps
CPU time 4.48 seconds
Started Aug 18 04:18:42 PM PDT 24
Finished Aug 18 04:18:52 PM PDT 24
Peak memory 164676 kb
Host smart-70a308da-8e2e-442a-8378-35215480b529
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2503248715 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.2503248715
Directory /workspace/4.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.3940259182
Short name T176
Test name
Test status
Simulation time 1509930000 ps
CPU time 4.87 seconds
Started Aug 18 04:18:44 PM PDT 24
Finished Aug 18 04:18:55 PM PDT 24
Peak memory 164688 kb
Host smart-0b1cd999-4ffb-4a38-9536-84796c875a03
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3940259182 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.3940259182
Directory /workspace/40.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.4112362507
Short name T181
Test name
Test status
Simulation time 1553050000 ps
CPU time 4.46 seconds
Started Aug 18 04:17:42 PM PDT 24
Finished Aug 18 04:17:52 PM PDT 24
Peak memory 164688 kb
Host smart-e78fc16a-97e1-4fcd-b2b7-11b9fbb8495e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4112362507 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.4112362507
Directory /workspace/41.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.2771571738
Short name T153
Test name
Test status
Simulation time 1547610000 ps
CPU time 4.58 seconds
Started Aug 18 04:22:17 PM PDT 24
Finished Aug 18 04:22:27 PM PDT 24
Peak memory 166036 kb
Host smart-3cbb438e-adcd-4d83-bc67-909e85619f22
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2771571738 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.2771571738
Directory /workspace/42.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.233108534
Short name T174
Test name
Test status
Simulation time 1309590000 ps
CPU time 4.37 seconds
Started Aug 18 04:19:19 PM PDT 24
Finished Aug 18 04:19:29 PM PDT 24
Peak memory 164696 kb
Host smart-e86bc10c-b3f6-43b8-876d-d65621ba894c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=233108534 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.233108534
Directory /workspace/43.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.4251562195
Short name T197
Test name
Test status
Simulation time 1058450000 ps
CPU time 3.15 seconds
Started Aug 18 04:20:44 PM PDT 24
Finished Aug 18 04:20:51 PM PDT 24
Peak memory 164656 kb
Host smart-2353aacf-2b79-4a23-8cc0-2604ea22a224
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4251562195 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.4251562195
Directory /workspace/44.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.43956160
Short name T152
Test name
Test status
Simulation time 1417610000 ps
CPU time 4.38 seconds
Started Aug 18 04:20:46 PM PDT 24
Finished Aug 18 04:20:56 PM PDT 24
Peak memory 164712 kb
Host smart-bf28d07a-344f-49ab-a7bb-ab444069c740
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=43956160 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.43956160
Directory /workspace/45.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.1766864396
Short name T158
Test name
Test status
Simulation time 1350070000 ps
CPU time 3.46 seconds
Started Aug 18 04:22:28 PM PDT 24
Finished Aug 18 04:22:36 PM PDT 24
Peak memory 164468 kb
Host smart-bb6be6bc-28f6-4e96-bd06-f5978c2d8248
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1766864396 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.1766864396
Directory /workspace/46.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.1888344470
Short name T190
Test name
Test status
Simulation time 1509150000 ps
CPU time 3.25 seconds
Started Aug 18 04:22:18 PM PDT 24
Finished Aug 18 04:22:25 PM PDT 24
Peak memory 164324 kb
Host smart-b7ca9b35-2ad7-4d07-ba4c-a3110c61c073
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1888344470 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.1888344470
Directory /workspace/47.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.1638985492
Short name T178
Test name
Test status
Simulation time 1183550000 ps
CPU time 4.26 seconds
Started Aug 18 04:17:18 PM PDT 24
Finished Aug 18 04:17:28 PM PDT 24
Peak memory 164272 kb
Host smart-75477e99-95e2-43c1-ae67-e59348617402
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1638985492 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.1638985492
Directory /workspace/48.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.3627440418
Short name T182
Test name
Test status
Simulation time 1346490000 ps
CPU time 3.09 seconds
Started Aug 18 04:22:17 PM PDT 24
Finished Aug 18 04:22:24 PM PDT 24
Peak memory 164292 kb
Host smart-6047523c-6c50-457a-b9e3-6ef88fe19402
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3627440418 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.3627440418
Directory /workspace/49.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.159957420
Short name T195
Test name
Test status
Simulation time 1310510000 ps
CPU time 3.89 seconds
Started Aug 18 04:21:58 PM PDT 24
Finished Aug 18 04:22:06 PM PDT 24
Peak memory 164640 kb
Host smart-5cbcb320-dd36-4ecc-87f9-302531a42b85
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=159957420 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.159957420
Directory /workspace/5.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.226764043
Short name T179
Test name
Test status
Simulation time 1178430000 ps
CPU time 3.57 seconds
Started Aug 18 04:22:01 PM PDT 24
Finished Aug 18 04:22:08 PM PDT 24
Peak memory 165048 kb
Host smart-8e218d05-dbf4-4a6b-b8ed-360c40cfb36f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=226764043 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.226764043
Directory /workspace/6.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.2300479391
Short name T200
Test name
Test status
Simulation time 1565370000 ps
CPU time 4.64 seconds
Started Aug 18 04:21:57 PM PDT 24
Finished Aug 18 04:22:08 PM PDT 24
Peak memory 164644 kb
Host smart-47af0770-6134-4e9a-9eae-c11aeefaa81a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2300479391 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.2300479391
Directory /workspace/7.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.2333865899
Short name T173
Test name
Test status
Simulation time 1528190000 ps
CPU time 3.79 seconds
Started Aug 18 04:22:56 PM PDT 24
Finished Aug 18 04:23:04 PM PDT 24
Peak memory 164476 kb
Host smart-0ae2e5d1-ae4c-41d6-aa90-afd93e432b4f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2333865899 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.2333865899
Directory /workspace/8.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.484285893
Short name T184
Test name
Test status
Simulation time 1279850000 ps
CPU time 3.6 seconds
Started Aug 18 04:21:58 PM PDT 24
Finished Aug 18 04:22:06 PM PDT 24
Peak memory 164644 kb
Host smart-6e80fd9f-620e-4813-bedd-0ef484848ab7
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=484285893 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.484285893
Directory /workspace/9.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.3504478100
Short name T59
Test name
Test status
Simulation time 1249890000 ps
CPU time 3.19 seconds
Started Aug 18 05:08:20 PM PDT 24
Finished Aug 18 05:08:27 PM PDT 24
Peak memory 164796 kb
Host smart-55b8ad74-7098-4e23-982d-00aa8e8dbb3a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3504478100 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.3504478100
Directory /workspace/1.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.1287071984
Short name T11
Test name
Test status
Simulation time 1432390000 ps
CPU time 4.38 seconds
Started Aug 18 05:08:19 PM PDT 24
Finished Aug 18 05:08:28 PM PDT 24
Peak memory 164816 kb
Host smart-b18fb392-9bef-4dfa-98ba-54997fa78c8e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1287071984 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.1287071984
Directory /workspace/10.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.46326942
Short name T44
Test name
Test status
Simulation time 1415910000 ps
CPU time 5.05 seconds
Started Aug 18 05:08:30 PM PDT 24
Finished Aug 18 05:08:41 PM PDT 24
Peak memory 164800 kb
Host smart-2a6b2963-3b63-453f-9325-944d980f475c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=46326942 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.46326942
Directory /workspace/11.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.392397055
Short name T33
Test name
Test status
Simulation time 1532790000 ps
CPU time 5.86 seconds
Started Aug 18 05:08:34 PM PDT 24
Finished Aug 18 05:08:47 PM PDT 24
Peak memory 164812 kb
Host smart-33f16bbd-18f1-4a9e-a4d2-1ff8fc7fb153
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=392397055 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.392397055
Directory /workspace/12.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.1179929792
Short name T37
Test name
Test status
Simulation time 1468510000 ps
CPU time 5.02 seconds
Started Aug 18 05:08:32 PM PDT 24
Finished Aug 18 05:08:43 PM PDT 24
Peak memory 164796 kb
Host smart-7808d04f-7d4e-4f43-90fb-1dca720d8394
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1179929792 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.1179929792
Directory /workspace/13.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.4048686420
Short name T34
Test name
Test status
Simulation time 1432330000 ps
CPU time 5.62 seconds
Started Aug 18 05:08:32 PM PDT 24
Finished Aug 18 05:08:43 PM PDT 24
Peak memory 164824 kb
Host smart-e4d5ad43-9eee-4e03-82fb-5b7b9fd15e20
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4048686420 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.4048686420
Directory /workspace/14.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.4234653062
Short name T63
Test name
Test status
Simulation time 1240190000 ps
CPU time 3.09 seconds
Started Aug 18 05:08:32 PM PDT 24
Finished Aug 18 05:08:39 PM PDT 24
Peak memory 164812 kb
Host smart-1bb3af2d-03f2-4488-b3cf-077680893d60
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4234653062 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.4234653062
Directory /workspace/15.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.3114297031
Short name T51
Test name
Test status
Simulation time 1463070000 ps
CPU time 4.94 seconds
Started Aug 18 05:08:32 PM PDT 24
Finished Aug 18 05:08:43 PM PDT 24
Peak memory 164836 kb
Host smart-6a561ae1-1ade-4339-885a-f1f4960c02b9
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3114297031 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.3114297031
Directory /workspace/16.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.3917409988
Short name T43
Test name
Test status
Simulation time 1353790000 ps
CPU time 4.6 seconds
Started Aug 18 05:08:34 PM PDT 24
Finished Aug 18 05:08:44 PM PDT 24
Peak memory 164876 kb
Host smart-80665386-10a8-49f9-83f2-e8e4a3e4361b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3917409988 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.3917409988
Directory /workspace/17.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.459828547
Short name T60
Test name
Test status
Simulation time 1569230000 ps
CPU time 4.79 seconds
Started Aug 18 05:08:32 PM PDT 24
Finished Aug 18 05:08:43 PM PDT 24
Peak memory 164852 kb
Host smart-f5e20113-349a-480c-a66f-3e4358274507
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=459828547 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.459828547
Directory /workspace/18.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.908478432
Short name T31
Test name
Test status
Simulation time 1388770000 ps
CPU time 6.18 seconds
Started Aug 18 05:08:32 PM PDT 24
Finished Aug 18 05:08:45 PM PDT 24
Peak memory 164764 kb
Host smart-e24f9c41-2225-4915-a6f6-281ff1dcc57f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=908478432 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.908478432
Directory /workspace/19.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.2622974899
Short name T41
Test name
Test status
Simulation time 1013190000 ps
CPU time 3.69 seconds
Started Aug 18 05:08:22 PM PDT 24
Finished Aug 18 05:08:30 PM PDT 24
Peak memory 164716 kb
Host smart-e0dce3ed-b406-446c-977a-004d06271b31
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2622974899 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.2622974899
Directory /workspace/2.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.3400728927
Short name T40
Test name
Test status
Simulation time 1440690000 ps
CPU time 4.75 seconds
Started Aug 18 05:08:34 PM PDT 24
Finished Aug 18 05:08:45 PM PDT 24
Peak memory 164784 kb
Host smart-55e04484-fc9e-4f8f-9716-fad6f634255c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3400728927 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.3400728927
Directory /workspace/20.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.1831376023
Short name T62
Test name
Test status
Simulation time 1166090000 ps
CPU time 3.74 seconds
Started Aug 18 05:08:35 PM PDT 24
Finished Aug 18 05:08:43 PM PDT 24
Peak memory 164888 kb
Host smart-2b0e61b1-f393-4f9a-9401-117db6b29d3a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1831376023 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.1831376023
Directory /workspace/21.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.2648197540
Short name T39
Test name
Test status
Simulation time 1526490000 ps
CPU time 3.14 seconds
Started Aug 18 05:08:32 PM PDT 24
Finished Aug 18 05:08:39 PM PDT 24
Peak memory 164796 kb
Host smart-328202f4-bc64-4b8a-83c3-ba941feda274
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2648197540 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.2648197540
Directory /workspace/22.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.2904554207
Short name T54
Test name
Test status
Simulation time 1436090000 ps
CPU time 3.25 seconds
Started Aug 18 05:08:32 PM PDT 24
Finished Aug 18 05:08:40 PM PDT 24
Peak memory 164816 kb
Host smart-1d27f9d2-9c74-4a64-9d26-2c1cc52f385c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2904554207 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.2904554207
Directory /workspace/23.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.2649101389
Short name T8
Test name
Test status
Simulation time 1555710000 ps
CPU time 3.59 seconds
Started Aug 18 05:08:33 PM PDT 24
Finished Aug 18 05:08:41 PM PDT 24
Peak memory 164856 kb
Host smart-95cc14fa-c8cc-4c10-8172-e9f45ccce969
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2649101389 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.2649101389
Directory /workspace/24.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.1602332859
Short name T7
Test name
Test status
Simulation time 1616890000 ps
CPU time 6.15 seconds
Started Aug 18 05:08:32 PM PDT 24
Finished Aug 18 05:08:45 PM PDT 24
Peak memory 164860 kb
Host smart-c7f6e951-048d-4e98-8f0a-b4116f7beef9
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1602332859 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.1602332859
Directory /workspace/25.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.3028129640
Short name T67
Test name
Test status
Simulation time 1422850000 ps
CPU time 4.55 seconds
Started Aug 18 05:08:33 PM PDT 24
Finished Aug 18 05:08:43 PM PDT 24
Peak memory 164812 kb
Host smart-51f9e758-8371-44a9-a83d-6cf07593ed63
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3028129640 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.3028129640
Directory /workspace/26.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.625391113
Short name T48
Test name
Test status
Simulation time 1498030000 ps
CPU time 3.97 seconds
Started Aug 18 05:08:33 PM PDT 24
Finished Aug 18 05:08:42 PM PDT 24
Peak memory 164812 kb
Host smart-b62f4102-86b7-497a-ba30-d3eccb34550c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=625391113 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.625391113
Directory /workspace/27.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.675506950
Short name T49
Test name
Test status
Simulation time 1464870000 ps
CPU time 5.35 seconds
Started Aug 18 05:08:34 PM PDT 24
Finished Aug 18 05:08:45 PM PDT 24
Peak memory 164868 kb
Host smart-07fd13cf-f471-4592-8480-6a11d93d0d29
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=675506950 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.675506950
Directory /workspace/28.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.3947050248
Short name T69
Test name
Test status
Simulation time 1327590000 ps
CPU time 4.3 seconds
Started Aug 18 05:08:34 PM PDT 24
Finished Aug 18 05:08:44 PM PDT 24
Peak memory 164848 kb
Host smart-0d3e94c0-53d0-4d9d-9275-0222550668b5
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3947050248 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.3947050248
Directory /workspace/29.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.1877363669
Short name T66
Test name
Test status
Simulation time 1488910000 ps
CPU time 4.14 seconds
Started Aug 18 05:08:20 PM PDT 24
Finished Aug 18 05:08:29 PM PDT 24
Peak memory 164856 kb
Host smart-74e57a24-7187-46fb-923c-9d4cf4c566e2
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1877363669 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.1877363669
Directory /workspace/3.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.1496058067
Short name T13
Test name
Test status
Simulation time 1347950000 ps
CPU time 4.78 seconds
Started Aug 18 05:08:35 PM PDT 24
Finished Aug 18 05:08:45 PM PDT 24
Peak memory 164768 kb
Host smart-0423c877-b346-46b3-9190-5deaf3f60a3f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1496058067 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.1496058067
Directory /workspace/30.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.2098199933
Short name T58
Test name
Test status
Simulation time 1334610000 ps
CPU time 4.17 seconds
Started Aug 18 05:08:35 PM PDT 24
Finished Aug 18 05:08:44 PM PDT 24
Peak memory 164848 kb
Host smart-ad350f67-2d48-46ee-bafd-098106fde5ba
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2098199933 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.2098199933
Directory /workspace/31.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.2434255595
Short name T46
Test name
Test status
Simulation time 1569370000 ps
CPU time 5.45 seconds
Started Aug 18 05:08:34 PM PDT 24
Finished Aug 18 05:08:47 PM PDT 24
Peak memory 164768 kb
Host smart-4976a627-cee5-4a54-884f-5699500b4794
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2434255595 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.2434255595
Directory /workspace/32.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.3819419943
Short name T9
Test name
Test status
Simulation time 1336130000 ps
CPU time 4.82 seconds
Started Aug 18 05:08:40 PM PDT 24
Finished Aug 18 05:08:51 PM PDT 24
Peak memory 164876 kb
Host smart-dbd71226-97ee-4f7e-9fde-35450d17e217
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3819419943 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.3819419943
Directory /workspace/33.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.2304463252
Short name T32
Test name
Test status
Simulation time 1406970000 ps
CPU time 5.08 seconds
Started Aug 18 05:08:44 PM PDT 24
Finished Aug 18 05:08:56 PM PDT 24
Peak memory 164912 kb
Host smart-38bde7a9-416c-435f-8ad1-56f61533ad9f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2304463252 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.2304463252
Directory /workspace/34.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.1008489439
Short name T61
Test name
Test status
Simulation time 1524450000 ps
CPU time 6.19 seconds
Started Aug 18 05:08:40 PM PDT 24
Finished Aug 18 05:08:53 PM PDT 24
Peak memory 164876 kb
Host smart-7ac00dcf-5538-4238-ab96-08c53a8d53d5
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1008489439 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.1008489439
Directory /workspace/35.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.842920518
Short name T45
Test name
Test status
Simulation time 1435050000 ps
CPU time 5.15 seconds
Started Aug 18 05:08:44 PM PDT 24
Finished Aug 18 05:08:56 PM PDT 24
Peak memory 164844 kb
Host smart-9c7ef90b-0905-4fc1-98a5-4fa59c373691
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=842920518 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.842920518
Directory /workspace/36.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.3886685316
Short name T42
Test name
Test status
Simulation time 1562010000 ps
CPU time 3.98 seconds
Started Aug 18 05:08:40 PM PDT 24
Finished Aug 18 05:08:49 PM PDT 24
Peak memory 164880 kb
Host smart-21625065-b0aa-4d43-9a4b-89ebfab039c6
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3886685316 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.3886685316
Directory /workspace/37.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.1326506709
Short name T64
Test name
Test status
Simulation time 1580250000 ps
CPU time 3.48 seconds
Started Aug 18 05:08:43 PM PDT 24
Finished Aug 18 05:08:51 PM PDT 24
Peak memory 164884 kb
Host smart-0c4024bc-73d5-47fe-a36a-c4eb004aa3c6
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1326506709 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.1326506709
Directory /workspace/38.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.1147748620
Short name T38
Test name
Test status
Simulation time 1620550000 ps
CPU time 5.1 seconds
Started Aug 18 05:08:43 PM PDT 24
Finished Aug 18 05:08:53 PM PDT 24
Peak memory 164884 kb
Host smart-069330aa-40ec-4f9f-8cb9-ee03ac5a7cb0
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1147748620 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.1147748620
Directory /workspace/39.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.715362706
Short name T53
Test name
Test status
Simulation time 1427990000 ps
CPU time 3.65 seconds
Started Aug 18 05:08:21 PM PDT 24
Finished Aug 18 05:08:29 PM PDT 24
Peak memory 166492 kb
Host smart-f8ee615c-281f-4f61-a4af-3d715a284549
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=715362706 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.715362706
Directory /workspace/4.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.1499199007
Short name T50
Test name
Test status
Simulation time 1454290000 ps
CPU time 5.27 seconds
Started Aug 18 05:08:43 PM PDT 24
Finished Aug 18 05:08:55 PM PDT 24
Peak memory 164852 kb
Host smart-dde846d6-1626-458d-8711-0ae2c6c8c3f8
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1499199007 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.1499199007
Directory /workspace/40.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.760528605
Short name T57
Test name
Test status
Simulation time 1477390000 ps
CPU time 5.26 seconds
Started Aug 18 05:08:40 PM PDT 24
Finished Aug 18 05:08:52 PM PDT 24
Peak memory 164712 kb
Host smart-2a4874a8-1e29-440c-a278-3dbc8b03ef49
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=760528605 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.760528605
Directory /workspace/41.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.4252194236
Short name T36
Test name
Test status
Simulation time 1237010000 ps
CPU time 4.18 seconds
Started Aug 18 05:08:41 PM PDT 24
Finished Aug 18 05:08:50 PM PDT 24
Peak memory 164852 kb
Host smart-e5e9d939-22fc-4226-87a3-f2449d96c4d4
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4252194236 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.4252194236
Directory /workspace/42.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.1437000806
Short name T10
Test name
Test status
Simulation time 1452330000 ps
CPU time 5.33 seconds
Started Aug 18 05:08:45 PM PDT 24
Finished Aug 18 05:08:57 PM PDT 24
Peak memory 164852 kb
Host smart-9ede9921-07d5-40ab-bcb1-7e4ece1466b7
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1437000806 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.1437000806
Directory /workspace/43.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.837204793
Short name T65
Test name
Test status
Simulation time 1376530000 ps
CPU time 4.64 seconds
Started Aug 18 05:08:41 PM PDT 24
Finished Aug 18 05:08:52 PM PDT 24
Peak memory 164808 kb
Host smart-b642818d-6c3a-4409-b19d-45022dd16087
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=837204793 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.837204793
Directory /workspace/44.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.4244511280
Short name T56
Test name
Test status
Simulation time 1147570000 ps
CPU time 3.99 seconds
Started Aug 18 05:08:43 PM PDT 24
Finished Aug 18 05:08:51 PM PDT 24
Peak memory 164884 kb
Host smart-8a110b16-1c11-4d4a-b61e-cd5120fcde7a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4244511280 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.4244511280
Directory /workspace/45.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.1571287271
Short name T70
Test name
Test status
Simulation time 1448830000 ps
CPU time 4.86 seconds
Started Aug 18 05:08:49 PM PDT 24
Finished Aug 18 05:09:00 PM PDT 24
Peak memory 165004 kb
Host smart-c0029105-4642-4a3d-b35a-5944388e9b72
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1571287271 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.1571287271
Directory /workspace/46.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.3750886689
Short name T52
Test name
Test status
Simulation time 1328570000 ps
CPU time 4.74 seconds
Started Aug 18 05:08:50 PM PDT 24
Finished Aug 18 05:09:00 PM PDT 24
Peak memory 164876 kb
Host smart-f463da83-7a89-4eb3-be1a-ea1eef2b2ab2
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3750886689 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.3750886689
Directory /workspace/47.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.3343429790
Short name T55
Test name
Test status
Simulation time 1236070000 ps
CPU time 4.5 seconds
Started Aug 18 05:08:48 PM PDT 24
Finished Aug 18 05:08:57 PM PDT 24
Peak memory 164828 kb
Host smart-4ad7e23d-04c6-4d39-a51e-27e1d3bc80b0
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3343429790 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.3343429790
Directory /workspace/48.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.4289034916
Short name T47
Test name
Test status
Simulation time 1505330000 ps
CPU time 4.71 seconds
Started Aug 18 05:08:50 PM PDT 24
Finished Aug 18 05:09:01 PM PDT 24
Peak memory 164868 kb
Host smart-8137f4de-4949-4dda-b58f-eeb554f977cc
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4289034916 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.4289034916
Directory /workspace/49.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.3026940968
Short name T68
Test name
Test status
Simulation time 1428410000 ps
CPU time 4.15 seconds
Started Aug 18 05:08:21 PM PDT 24
Finished Aug 18 05:08:31 PM PDT 24
Peak memory 164820 kb
Host smart-bc692ef0-f251-4cee-bed3-1afab92f09bb
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3026940968 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.3026940968
Directory /workspace/5.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.3472289892
Short name T35
Test name
Test status
Simulation time 1307150000 ps
CPU time 4.81 seconds
Started Aug 18 05:08:20 PM PDT 24
Finished Aug 18 05:08:31 PM PDT 24
Peak memory 164784 kb
Host smart-518d74e4-806e-49f2-92b2-b411c702629e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3472289892 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.3472289892
Directory /workspace/6.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.505240646
Short name T1
Test name
Test status
Simulation time 1539190000 ps
CPU time 5.77 seconds
Started Aug 18 05:08:20 PM PDT 24
Finished Aug 18 05:08:32 PM PDT 24
Peak memory 164872 kb
Host smart-fa1f0df4-a295-4e61-9764-50ac4b9701b5
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=505240646 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.505240646
Directory /workspace/7.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.102144272
Short name T3
Test name
Test status
Simulation time 1481630000 ps
CPU time 3.03 seconds
Started Aug 18 05:08:20 PM PDT 24
Finished Aug 18 05:08:27 PM PDT 24
Peak memory 164776 kb
Host smart-5c3a4794-2fd8-4a32-b8b9-525f7374dbb9
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=102144272 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.102144272
Directory /workspace/8.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.315642559
Short name T2
Test name
Test status
Simulation time 1326030000 ps
CPU time 3.9 seconds
Started Aug 18 05:08:21 PM PDT 24
Finished Aug 18 05:08:30 PM PDT 24
Peak memory 166428 kb
Host smart-fd68b1d2-46b6-4024-bcf1-7b7be6f124a6
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=315642559 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.315642559
Directory /workspace/9.prim_lfsr_gal_smoke/latest
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