Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.31 100.00 96.55 100.00 100.00 95.00


Total tests in report: 200
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
87.31 87.31 100.00 100.00 96.55 96.55 100.00 100.00 100.00 100.00 40.00 40.00 /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.2807075437
95.31 8.00 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 80.00 40.00 /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.3462566933
98.31 3.00 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 95.00 15.00 /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.4143520750

Tests that do not contribute to grading

Name
/workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.1039378277
/workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.3885436398
/workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.652078345
/workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.3800620759
/workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.2001484776
/workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.2657243593
/workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.2112914866
/workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.3080165808
/workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.2669104579
/workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.2320054267
/workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2065866580
/workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.289612371
/workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.3867185635
/workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.3737062611
/workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.3025838131
/workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.2867005522
/workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.317788553
/workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.2732301763
/workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1950815709
/workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.2926917283
/workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.546665117
/workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.3056941543
/workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.654319653
/workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.613064563
/workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.725745173
/workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.3784278072
/workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.4001855003
/workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.3853584943
/workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.1241062112
/workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.3687241614
/workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.1206159315
/workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.2308273435
/workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.2713467962
/workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.1976012111
/workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.633025941
/workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.1388896831
/workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.3409614913
/workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.696024504
/workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.4123155004
/workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.4167485968
/workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.3737836353
/workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.3825394681
/workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.3092988122
/workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.776104401
/workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.1502996564
/workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.239380641
/workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.4071295864
/workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.3996316303
/workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.2398841065
/workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.4229783402
/workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.368314115
/workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.2054929094
/workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.796793781
/workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.4217528068
/workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.2505361707
/workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.920404052
/workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.2064593520
/workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.1965972895
/workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.1159483337
/workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.3657693045
/workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.2944646897
/workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.332230503
/workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3572417119
/workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.3550744523
/workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.973473517
/workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.2849787924
/workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.2430832782
/workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.341728960
/workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.1075647705
/workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.3641117221
/workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.980147646
/workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.3021949120
/workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.4010808109
/workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.419437079
/workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.931507414
/workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.4090752781
/workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.3075649551
/workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.3303129182
/workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.354113936
/workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.4011710637
/workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.607651497
/workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.1992722421
/workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.2988075725
/workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.4189209443
/workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.4264323507
/workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.1756858924
/workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.3526002220
/workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.165844727
/workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.899295554
/workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.2042409893
/workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.4066699654
/workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.4186335340
/workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.2100532693
/workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.2109154100
/workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.278790113
/workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.3556380057
/workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.1240749075
/workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.1408366882
/workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.1056497485
/workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.665803122
/workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.1309006471
/workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.3296503365
/workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.3467584762
/workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.780473550
/workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.4175354307
/workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.4208357197
/workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.3868706775
/workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.1347971545
/workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.2272565783
/workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.1322627789
/workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.4177364974
/workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.4169485075
/workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3537038944
/workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.2527823043
/workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.4158580388
/workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.2004045197
/workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.1781993507
/workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2491307948
/workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.1362082435
/workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.2131228009
/workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.3223000439
/workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.3844382904
/workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.196307127
/workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.4131086093
/workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.2074172124
/workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.4140721191
/workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.1820517452
/workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.2785862781
/workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.2581093041
/workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.866760243
/workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.111660451
/workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.3770352446
/workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3175881612
/workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.4012155874
/workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.4057247802
/workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.2684900428
/workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.3068049391
/workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.93734373
/workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.362546855
/workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.3356048830
/workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.2881158663
/workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.2666070868
/workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.1148004879
/workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.2367978715
/workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.1719839463
/workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.2358603273
/workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1372598556
/workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2270359252
/workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.2350218957
/workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.4255039161
/workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.81803029
/workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.565613155
/workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.77657439
/workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.2591997879
/workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.3648935995
/workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.605372593
/workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.855611419
/workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.3564824162
/workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.2984045021
/workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.3157339251
/workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.2246660392
/workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.1006826184
/workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.3790148158
/workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.86257081
/workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.597897036
/workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.2730988565
/workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.454705966
/workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.3055245235
/workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.2772134794
/workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.2676291912
/workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.1435797521
/workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.2125478139
/workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.2071882312
/workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.1071374057
/workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.1660618333
/workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.675139981
/workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.174461118
/workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.3569368787
/workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.3682604744
/workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.510027588
/workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.2323806359
/workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.3984507514
/workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.614212165
/workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.131070279
/workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.10188442
/workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.851952365
/workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.4113288677
/workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.805874000
/workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.1214462579
/workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.2812302846
/workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.17220291
/workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.3428154273
/workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.372738403
/workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.1260333058
/workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.3182280484
/workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.791472356
/workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.1784318519



Total test records in report: 200
tests.html | tests1.html | tests2.html | tests3.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.851952365 Aug 19 04:23:38 PM PDT 24 Aug 19 04:23:47 PM PDT 24 1394010000 ps
T2 /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.3055245235 Aug 19 04:19:17 PM PDT 24 Aug 19 04:19:26 PM PDT 24 1453850000 ps
T3 /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.565613155 Aug 19 04:18:15 PM PDT 24 Aug 19 04:18:28 PM PDT 24 1529990000 ps
T4 /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.1784318519 Aug 19 04:20:05 PM PDT 24 Aug 19 04:20:15 PM PDT 24 1474830000 ps
T8 /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.2812302846 Aug 19 04:23:38 PM PDT 24 Aug 19 04:23:47 PM PDT 24 1496850000 ps
T9 /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.1214462579 Aug 19 04:23:14 PM PDT 24 Aug 19 04:23:24 PM PDT 24 1440430000 ps
T10 /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.2807075437 Aug 19 04:18:14 PM PDT 24 Aug 19 04:18:22 PM PDT 24 1526270000 ps
T11 /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.2246660392 Aug 19 04:19:15 PM PDT 24 Aug 19 04:19:24 PM PDT 24 1475930000 ps
T12 /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.2125478139 Aug 19 04:22:57 PM PDT 24 Aug 19 04:23:05 PM PDT 24 1457650000 ps
T13 /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.1260333058 Aug 19 04:24:31 PM PDT 24 Aug 19 04:24:38 PM PDT 24 1482590000 ps
T31 /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.1071374057 Aug 19 04:19:36 PM PDT 24 Aug 19 04:19:47 PM PDT 24 1493990000 ps
T32 /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.86257081 Aug 19 04:23:00 PM PDT 24 Aug 19 04:23:08 PM PDT 24 1330510000 ps
T33 /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.2071882312 Aug 19 04:22:56 PM PDT 24 Aug 19 04:23:04 PM PDT 24 1351250000 ps
T34 /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.1660618333 Aug 19 04:22:57 PM PDT 24 Aug 19 04:23:06 PM PDT 24 1354690000 ps
T35 /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.2323806359 Aug 19 04:23:20 PM PDT 24 Aug 19 04:23:28 PM PDT 24 1603350000 ps
T36 /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.4113288677 Aug 19 04:23:14 PM PDT 24 Aug 19 04:23:25 PM PDT 24 1527330000 ps
T37 /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.791472356 Aug 19 04:23:50 PM PDT 24 Aug 19 04:24:00 PM PDT 24 1565270000 ps
T38 /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.597897036 Aug 19 04:22:44 PM PDT 24 Aug 19 04:22:52 PM PDT 24 1401550000 ps
T39 /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.3157339251 Aug 19 04:23:34 PM PDT 24 Aug 19 04:23:44 PM PDT 24 1437610000 ps
T40 /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.174461118 Aug 19 04:21:40 PM PDT 24 Aug 19 04:21:48 PM PDT 24 1322270000 ps
T41 /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.855611419 Aug 19 04:18:15 PM PDT 24 Aug 19 04:18:25 PM PDT 24 1371270000 ps
T42 /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.510027588 Aug 19 04:21:03 PM PDT 24 Aug 19 04:21:13 PM PDT 24 1461270000 ps
T43 /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.3682604744 Aug 19 04:20:51 PM PDT 24 Aug 19 04:21:00 PM PDT 24 1442650000 ps
T44 /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.3648935995 Aug 19 04:18:05 PM PDT 24 Aug 19 04:18:14 PM PDT 24 1469970000 ps
T45 /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.454705966 Aug 19 04:19:16 PM PDT 24 Aug 19 04:19:25 PM PDT 24 1422870000 ps
T46 /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.10188442 Aug 19 04:22:58 PM PDT 24 Aug 19 04:23:06 PM PDT 24 1513810000 ps
T47 /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.1006826184 Aug 19 04:20:53 PM PDT 24 Aug 19 04:21:00 PM PDT 24 1332530000 ps
T48 /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.372738403 Aug 19 04:22:57 PM PDT 24 Aug 19 04:23:06 PM PDT 24 1560010000 ps
T49 /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.614212165 Aug 19 04:23:13 PM PDT 24 Aug 19 04:23:22 PM PDT 24 1440690000 ps
T50 /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.1435797521 Aug 19 04:23:10 PM PDT 24 Aug 19 04:23:18 PM PDT 24 1503250000 ps
T51 /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.81803029 Aug 19 04:18:15 PM PDT 24 Aug 19 04:18:26 PM PDT 24 1484910000 ps
T52 /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.675139981 Aug 19 04:20:02 PM PDT 24 Aug 19 04:20:11 PM PDT 24 1451510000 ps
T53 /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.2591997879 Aug 19 04:18:20 PM PDT 24 Aug 19 04:18:29 PM PDT 24 1446830000 ps
T54 /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.805874000 Aug 19 04:20:24 PM PDT 24 Aug 19 04:20:34 PM PDT 24 1541810000 ps
T55 /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.2730988565 Aug 19 04:22:43 PM PDT 24 Aug 19 04:22:52 PM PDT 24 1571090000 ps
T56 /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.17220291 Aug 19 04:23:38 PM PDT 24 Aug 19 04:23:48 PM PDT 24 1559510000 ps
T57 /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.3790148158 Aug 19 04:22:58 PM PDT 24 Aug 19 04:23:08 PM PDT 24 1599370000 ps
T58 /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.77657439 Aug 19 04:18:15 PM PDT 24 Aug 19 04:18:28 PM PDT 24 1631490000 ps
T59 /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.3182280484 Aug 19 04:23:50 PM PDT 24 Aug 19 04:24:00 PM PDT 24 1489630000 ps
T60 /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.131070279 Aug 19 04:23:12 PM PDT 24 Aug 19 04:23:22 PM PDT 24 1426990000 ps
T61 /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.3984507514 Aug 19 04:23:15 PM PDT 24 Aug 19 04:23:22 PM PDT 24 1498990000 ps
T62 /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.3569368787 Aug 19 04:23:06 PM PDT 24 Aug 19 04:23:15 PM PDT 24 1548450000 ps
T63 /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.2676291912 Aug 19 04:23:44 PM PDT 24 Aug 19 04:23:51 PM PDT 24 1620390000 ps
T64 /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.2984045021 Aug 19 04:20:50 PM PDT 24 Aug 19 04:20:58 PM PDT 24 1470830000 ps
T65 /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.3564824162 Aug 19 04:21:08 PM PDT 24 Aug 19 04:21:21 PM PDT 24 1538290000 ps
T66 /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.605372593 Aug 19 04:18:14 PM PDT 24 Aug 19 04:18:26 PM PDT 24 1368290000 ps
T67 /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.2772134794 Aug 19 04:20:04 PM PDT 24 Aug 19 04:20:13 PM PDT 24 1439470000 ps
T68 /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.4255039161 Aug 19 04:22:59 PM PDT 24 Aug 19 04:23:07 PM PDT 24 1486770000 ps
T69 /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.3428154273 Aug 19 04:22:59 PM PDT 24 Aug 19 04:23:06 PM PDT 24 1338970000 ps
T70 /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.2350218957 Aug 19 04:22:58 PM PDT 24 Aug 19 04:23:06 PM PDT 24 1333670000 ps
T14 /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.1240749075 Aug 19 04:18:49 PM PDT 24 Aug 19 04:55:30 PM PDT 24 336507690000 ps
T15 /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.3303129182 Aug 19 04:18:09 PM PDT 24 Aug 19 04:59:00 PM PDT 24 337087770000 ps
T16 /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.3556380057 Aug 19 04:18:09 PM PDT 24 Aug 19 04:58:47 PM PDT 24 337077110000 ps
T17 /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.607651497 Aug 19 04:23:47 PM PDT 24 Aug 19 04:49:07 PM PDT 24 336590110000 ps
T18 /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.3462566933 Aug 19 04:18:09 PM PDT 24 Aug 19 04:59:19 PM PDT 24 336807670000 ps
T19 /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.3550744523 Aug 19 04:18:06 PM PDT 24 Aug 19 04:59:11 PM PDT 24 336731390000 ps
T20 /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.2505361707 Aug 19 04:18:14 PM PDT 24 Aug 19 05:00:52 PM PDT 24 336660610000 ps
T21 /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.4010808109 Aug 19 04:20:54 PM PDT 24 Aug 19 04:57:14 PM PDT 24 336934550000 ps
T22 /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.419437079 Aug 19 04:20:53 PM PDT 24 Aug 19 04:50:58 PM PDT 24 337035310000 ps
T23 /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.4189209443 Aug 19 04:18:49 PM PDT 24 Aug 19 04:55:46 PM PDT 24 336770110000 ps
T71 /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.165844727 Aug 19 04:19:58 PM PDT 24 Aug 19 04:56:00 PM PDT 24 336798110000 ps
T72 /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.4090752781 Aug 19 04:18:11 PM PDT 24 Aug 19 04:53:30 PM PDT 24 336995350000 ps
T73 /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.368314115 Aug 19 04:19:28 PM PDT 24 Aug 19 04:55:24 PM PDT 24 337151970000 ps
T74 /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.4011710637 Aug 19 04:18:11 PM PDT 24 Aug 19 04:54:50 PM PDT 24 336584190000 ps
T75 /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.3075649551 Aug 19 04:18:11 PM PDT 24 Aug 19 04:52:53 PM PDT 24 337005390000 ps
T76 /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.2988075725 Aug 19 04:18:48 PM PDT 24 Aug 19 04:55:52 PM PDT 24 336501510000 ps
T77 /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.2042409893 Aug 19 04:18:04 PM PDT 24 Aug 19 04:54:54 PM PDT 24 336527890000 ps
T78 /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.3021949120 Aug 19 04:18:11 PM PDT 24 Aug 19 04:54:17 PM PDT 24 337080150000 ps
T79 /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.3526002220 Aug 19 04:18:09 PM PDT 24 Aug 19 04:54:17 PM PDT 24 336825650000 ps
T80 /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.1075647705 Aug 19 04:19:16 PM PDT 24 Aug 19 04:52:32 PM PDT 24 336749510000 ps
T81 /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.796793781 Aug 19 04:18:15 PM PDT 24 Aug 19 05:00:58 PM PDT 24 337020310000 ps
T82 /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.4186335340 Aug 19 04:18:15 PM PDT 24 Aug 19 05:00:59 PM PDT 24 336808450000 ps
T83 /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.4066699654 Aug 19 04:18:49 PM PDT 24 Aug 19 04:55:53 PM PDT 24 336623370000 ps
T84 /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.1756858924 Aug 19 04:18:09 PM PDT 24 Aug 19 04:58:53 PM PDT 24 336565370000 ps
T85 /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.931507414 Aug 19 04:18:06 PM PDT 24 Aug 19 04:59:31 PM PDT 24 337088770000 ps
T86 /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.2109154100 Aug 19 04:18:09 PM PDT 24 Aug 19 04:54:23 PM PDT 24 336750830000 ps
T87 /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.3657693045 Aug 19 04:18:15 PM PDT 24 Aug 19 05:00:55 PM PDT 24 336916310000 ps
T88 /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.2054929094 Aug 19 04:18:14 PM PDT 24 Aug 19 04:56:08 PM PDT 24 336764830000 ps
T89 /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.2849787924 Aug 19 04:18:14 PM PDT 24 Aug 19 05:00:54 PM PDT 24 336735910000 ps
T90 /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.332230503 Aug 19 04:18:04 PM PDT 24 Aug 19 04:54:49 PM PDT 24 336994970000 ps
T91 /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.899295554 Aug 19 04:18:14 PM PDT 24 Aug 19 05:00:57 PM PDT 24 336843870000 ps
T92 /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.2100532693 Aug 19 04:18:11 PM PDT 24 Aug 19 04:58:12 PM PDT 24 336416130000 ps
T93 /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.920404052 Aug 19 04:18:09 PM PDT 24 Aug 19 04:54:08 PM PDT 24 336432430000 ps
T94 /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.973473517 Aug 19 04:18:11 PM PDT 24 Aug 19 04:58:30 PM PDT 24 336924250000 ps
T95 /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.1408366882 Aug 19 04:18:49 PM PDT 24 Aug 19 04:56:35 PM PDT 24 336629550000 ps
T96 /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.1992722421 Aug 19 04:18:48 PM PDT 24 Aug 19 04:55:59 PM PDT 24 336579710000 ps
T97 /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.1159483337 Aug 19 04:18:09 PM PDT 24 Aug 19 04:59:35 PM PDT 24 336927810000 ps
T98 /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.2064593520 Aug 19 04:18:12 PM PDT 24 Aug 19 04:57:25 PM PDT 24 336374010000 ps
T99 /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.2430832782 Aug 19 04:18:04 PM PDT 24 Aug 19 04:54:48 PM PDT 24 336795050000 ps
T100 /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.341728960 Aug 19 04:18:06 PM PDT 24 Aug 19 04:59:21 PM PDT 24 336705010000 ps
T101 /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.2944646897 Aug 19 04:18:15 PM PDT 24 Aug 19 05:00:59 PM PDT 24 336589430000 ps
T102 /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.3641117221 Aug 19 04:18:10 PM PDT 24 Aug 19 04:58:28 PM PDT 24 336704730000 ps
T103 /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.1965972895 Aug 19 04:18:10 PM PDT 24 Aug 19 04:59:34 PM PDT 24 336358370000 ps
T104 /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.4264323507 Aug 19 04:18:14 PM PDT 24 Aug 19 04:56:12 PM PDT 24 336397450000 ps
T105 /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.4217528068 Aug 19 04:18:11 PM PDT 24 Aug 19 04:53:28 PM PDT 24 337053970000 ps
T106 /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3572417119 Aug 19 04:18:48 PM PDT 24 Aug 19 04:55:40 PM PDT 24 336476870000 ps
T107 /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.980147646 Aug 19 04:18:04 PM PDT 24 Aug 19 04:54:48 PM PDT 24 336740730000 ps
T108 /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.278790113 Aug 19 04:18:04 PM PDT 24 Aug 19 04:55:00 PM PDT 24 337045630000 ps
T109 /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.4229783402 Aug 19 04:18:15 PM PDT 24 Aug 19 05:00:55 PM PDT 24 336503390000 ps
T110 /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.354113936 Aug 19 04:18:15 PM PDT 24 Aug 19 04:54:41 PM PDT 24 336825170000 ps
T5 /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.3867185635 Aug 19 04:21:34 PM PDT 24 Aug 19 05:02:29 PM PDT 24 336417030000 ps
T6 /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.2112914866 Aug 19 04:18:14 PM PDT 24 Aug 19 04:56:04 PM PDT 24 337031130000 ps
T7 /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.4123155004 Aug 19 04:20:11 PM PDT 24 Aug 19 04:55:55 PM PDT 24 337079110000 ps
T24 /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.3885436398 Aug 19 04:18:14 PM PDT 24 Aug 19 04:55:25 PM PDT 24 336703570000 ps
T25 /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.1976012111 Aug 19 04:18:15 PM PDT 24 Aug 19 05:00:56 PM PDT 24 336907470000 ps
T26 /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.3687241614 Aug 19 04:21:51 PM PDT 24 Aug 19 04:50:29 PM PDT 24 336738150000 ps
T27 /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.546665117 Aug 19 04:19:15 PM PDT 24 Aug 19 04:51:48 PM PDT 24 336576530000 ps
T28 /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.3800620759 Aug 19 04:18:05 PM PDT 24 Aug 19 04:52:38 PM PDT 24 336612150000 ps
T29 /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.3737062611 Aug 19 04:19:16 PM PDT 24 Aug 19 04:48:20 PM PDT 24 336540470000 ps
T30 /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.4143520750 Aug 19 04:18:10 PM PDT 24 Aug 19 04:57:02 PM PDT 24 336377410000 ps
T111 /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.3737836353 Aug 19 04:22:58 PM PDT 24 Aug 19 04:46:31 PM PDT 24 336823230000 ps
T112 /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.2867005522 Aug 19 04:19:16 PM PDT 24 Aug 19 04:48:52 PM PDT 24 336875550000 ps
T113 /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1950815709 Aug 19 04:19:05 PM PDT 24 Aug 19 04:50:01 PM PDT 24 336868150000 ps
T114 /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.2001484776 Aug 19 04:18:10 PM PDT 24 Aug 19 04:58:06 PM PDT 24 337025750000 ps
T115 /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.633025941 Aug 19 04:23:06 PM PDT 24 Aug 19 04:47:13 PM PDT 24 336754430000 ps
T116 /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.2669104579 Aug 19 04:19:17 PM PDT 24 Aug 19 04:44:54 PM PDT 24 336785530000 ps
T117 /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.652078345 Aug 19 04:18:02 PM PDT 24 Aug 19 04:52:32 PM PDT 24 336888750000 ps
T118 /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.2713467962 Aug 19 04:21:38 PM PDT 24 Aug 19 04:57:03 PM PDT 24 336832730000 ps
T119 /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.3056941543 Aug 19 04:19:28 PM PDT 24 Aug 19 04:55:12 PM PDT 24 336502910000 ps
T120 /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.3409614913 Aug 19 04:20:58 PM PDT 24 Aug 19 04:45:06 PM PDT 24 336591030000 ps
T121 /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.317788553 Aug 19 04:21:55 PM PDT 24 Aug 19 04:52:27 PM PDT 24 336587450000 ps
T122 /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.1206159315 Aug 19 04:19:54 PM PDT 24 Aug 19 04:50:45 PM PDT 24 336747230000 ps
T123 /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.3996316303 Aug 19 04:18:48 PM PDT 24 Aug 19 04:55:39 PM PDT 24 336681130000 ps
T124 /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.2732301763 Aug 19 04:22:44 PM PDT 24 Aug 19 04:49:47 PM PDT 24 336894530000 ps
T125 /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.1039378277 Aug 19 04:24:03 PM PDT 24 Aug 19 04:51:06 PM PDT 24 336361670000 ps
T126 /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.3853584943 Aug 19 04:20:05 PM PDT 24 Aug 19 04:55:14 PM PDT 24 336489070000 ps
T127 /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.725745173 Aug 19 04:22:45 PM PDT 24 Aug 19 04:46:59 PM PDT 24 336554710000 ps
T128 /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.239380641 Aug 19 04:18:10 PM PDT 24 Aug 19 04:59:45 PM PDT 24 336468030000 ps
T129 /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.3825394681 Aug 19 04:23:13 PM PDT 24 Aug 19 04:52:38 PM PDT 24 336809170000 ps
T130 /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2065866580 Aug 19 04:18:06 PM PDT 24 Aug 19 04:59:22 PM PDT 24 336730890000 ps
T131 /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.2657243593 Aug 19 04:19:15 PM PDT 24 Aug 19 04:52:33 PM PDT 24 336677570000 ps
T132 /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.3025838131 Aug 19 04:22:02 PM PDT 24 Aug 19 04:55:42 PM PDT 24 336604670000 ps
T133 /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.654319653 Aug 19 04:18:11 PM PDT 24 Aug 19 04:57:43 PM PDT 24 336677450000 ps
T134 /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.2926917283 Aug 19 04:19:29 PM PDT 24 Aug 19 04:47:55 PM PDT 24 336546770000 ps
T135 /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.1241062112 Aug 19 04:18:38 PM PDT 24 Aug 19 04:52:53 PM PDT 24 336845970000 ps
T136 /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.1502996564 Aug 19 04:18:13 PM PDT 24 Aug 19 05:01:00 PM PDT 24 336773050000 ps
T137 /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.2398841065 Aug 19 04:18:10 PM PDT 24 Aug 19 04:59:04 PM PDT 24 336965930000 ps
T138 /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.696024504 Aug 19 04:23:11 PM PDT 24 Aug 19 04:48:38 PM PDT 24 336395610000 ps
T139 /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.776104401 Aug 19 04:20:33 PM PDT 24 Aug 19 04:56:25 PM PDT 24 336555250000 ps
T140 /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.2308273435 Aug 19 04:22:57 PM PDT 24 Aug 19 04:48:08 PM PDT 24 336422210000 ps
T141 /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.1388896831 Aug 19 04:22:54 PM PDT 24 Aug 19 04:48:19 PM PDT 24 336335510000 ps
T142 /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.4001855003 Aug 19 04:19:54 PM PDT 24 Aug 19 04:49:30 PM PDT 24 336418590000 ps
T143 /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.3784278072 Aug 19 04:22:56 PM PDT 24 Aug 19 04:45:54 PM PDT 24 336809490000 ps
T144 /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.2320054267 Aug 19 04:18:02 PM PDT 24 Aug 19 04:52:37 PM PDT 24 336980070000 ps
T145 /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.4167485968 Aug 19 04:23:24 PM PDT 24 Aug 19 04:47:35 PM PDT 24 336894410000 ps
T146 /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.613064563 Aug 19 04:18:51 PM PDT 24 Aug 19 04:42:48 PM PDT 24 336894110000 ps
T147 /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.3080165808 Aug 19 04:18:15 PM PDT 24 Aug 19 04:55:52 PM PDT 24 336912790000 ps
T148 /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.289612371 Aug 19 04:18:10 PM PDT 24 Aug 19 04:56:54 PM PDT 24 336800610000 ps
T149 /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.3092988122 Aug 19 04:22:58 PM PDT 24 Aug 19 04:50:34 PM PDT 24 336632950000 ps
T150 /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.4071295864 Aug 19 04:18:15 PM PDT 24 Aug 19 05:00:57 PM PDT 24 336609630000 ps
T151 /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.4208357197 Aug 19 04:22:58 PM PDT 24 Aug 19 04:23:06 PM PDT 24 1381310000 ps
T152 /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.1820517452 Aug 19 04:19:30 PM PDT 24 Aug 19 04:19:38 PM PDT 24 1505950000 ps
T153 /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.1148004879 Aug 19 04:19:15 PM PDT 24 Aug 19 04:19:22 PM PDT 24 1361790000 ps
T154 /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.111660451 Aug 19 04:19:15 PM PDT 24 Aug 19 04:19:23 PM PDT 24 1336710000 ps
T155 /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.2358603273 Aug 19 04:19:54 PM PDT 24 Aug 19 04:20:02 PM PDT 24 1380510000 ps
T156 /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3537038944 Aug 19 04:23:16 PM PDT 24 Aug 19 04:23:24 PM PDT 24 1543390000 ps
T157 /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.4175354307 Aug 19 04:20:04 PM PDT 24 Aug 19 04:20:12 PM PDT 24 1354970000 ps
T158 /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.2785862781 Aug 19 04:18:20 PM PDT 24 Aug 19 04:18:29 PM PDT 24 1511250000 ps
T159 /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.1322627789 Aug 19 04:23:13 PM PDT 24 Aug 19 04:23:21 PM PDT 24 1528750000 ps
T160 /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.3467584762 Aug 19 04:20:43 PM PDT 24 Aug 19 04:20:54 PM PDT 24 1385110000 ps
T161 /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.866760243 Aug 19 04:19:15 PM PDT 24 Aug 19 04:19:25 PM PDT 24 1600710000 ps
T162 /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.1362082435 Aug 19 04:23:04 PM PDT 24 Aug 19 04:23:12 PM PDT 24 1551990000 ps
T163 /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.362546855 Aug 19 04:19:29 PM PDT 24 Aug 19 04:19:40 PM PDT 24 1492450000 ps
T164 /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.3868706775 Aug 19 04:23:35 PM PDT 24 Aug 19 04:23:42 PM PDT 24 1554050000 ps
T165 /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.2527823043 Aug 19 04:20:53 PM PDT 24 Aug 19 04:21:03 PM PDT 24 1291770000 ps
T166 /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.93734373 Aug 19 04:22:43 PM PDT 24 Aug 19 04:22:50 PM PDT 24 1065630000 ps
T167 /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.3770352446 Aug 19 04:19:16 PM PDT 24 Aug 19 04:19:24 PM PDT 24 1463110000 ps
T168 /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.2581093041 Aug 19 04:18:17 PM PDT 24 Aug 19 04:18:26 PM PDT 24 1500390000 ps
T169 /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.4012155874 Aug 19 04:22:03 PM PDT 24 Aug 19 04:22:15 PM PDT 24 1476050000 ps
T170 /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.196307127 Aug 19 04:18:05 PM PDT 24 Aug 19 04:18:12 PM PDT 24 1488430000 ps
T171 /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.2881158663 Aug 19 04:19:17 PM PDT 24 Aug 19 04:19:26 PM PDT 24 1380710000 ps
T172 /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.4140721191 Aug 19 04:18:13 PM PDT 24 Aug 19 04:18:21 PM PDT 24 1370450000 ps
T173 /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2270359252 Aug 19 04:20:08 PM PDT 24 Aug 19 04:20:18 PM PDT 24 1634030000 ps
T174 /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3175881612 Aug 19 04:22:57 PM PDT 24 Aug 19 04:23:06 PM PDT 24 1242370000 ps
T175 /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.4131086093 Aug 19 04:19:16 PM PDT 24 Aug 19 04:19:24 PM PDT 24 1499150000 ps
T176 /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.665803122 Aug 19 04:22:57 PM PDT 24 Aug 19 04:23:06 PM PDT 24 1566750000 ps
T177 /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.4158580388 Aug 19 04:19:30 PM PDT 24 Aug 19 04:19:36 PM PDT 24 1309610000 ps
T178 /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2491307948 Aug 19 04:22:57 PM PDT 24 Aug 19 04:23:06 PM PDT 24 1281570000 ps
T179 /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.2272565783 Aug 19 04:23:21 PM PDT 24 Aug 19 04:23:28 PM PDT 24 1569410000 ps
T180 /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.2004045197 Aug 19 04:21:59 PM PDT 24 Aug 19 04:22:11 PM PDT 24 1592730000 ps
T181 /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.1309006471 Aug 19 04:22:54 PM PDT 24 Aug 19 04:23:01 PM PDT 24 1501450000 ps
T182 /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.4177364974 Aug 19 04:21:52 PM PDT 24 Aug 19 04:22:03 PM PDT 24 1398170000 ps
T183 /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.1347971545 Aug 19 04:20:05 PM PDT 24 Aug 19 04:20:13 PM PDT 24 1223350000 ps
T184 /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.1781993507 Aug 19 04:23:10 PM PDT 24 Aug 19 04:23:17 PM PDT 24 1195230000 ps
T185 /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.2367978715 Aug 19 04:23:12 PM PDT 24 Aug 19 04:23:21 PM PDT 24 1258430000 ps
T186 /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.3844382904 Aug 19 04:23:06 PM PDT 24 Aug 19 04:23:14 PM PDT 24 1481970000 ps
T187 /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.3296503365 Aug 19 04:23:13 PM PDT 24 Aug 19 04:23:22 PM PDT 24 1455570000 ps
T188 /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.2131228009 Aug 19 04:23:04 PM PDT 24 Aug 19 04:23:11 PM PDT 24 1458790000 ps
T189 /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.780473550 Aug 19 04:23:24 PM PDT 24 Aug 19 04:23:32 PM PDT 24 1497050000 ps
T190 /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.4057247802 Aug 19 04:19:16 PM PDT 24 Aug 19 04:19:26 PM PDT 24 1608330000 ps
T191 /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.3223000439 Aug 19 04:21:48 PM PDT 24 Aug 19 04:21:59 PM PDT 24 1518410000 ps
T192 /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.1056497485 Aug 19 04:18:48 PM PDT 24 Aug 19 04:18:59 PM PDT 24 1561350000 ps
T193 /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.3068049391 Aug 19 04:19:15 PM PDT 24 Aug 19 04:19:23 PM PDT 24 1199190000 ps
T194 /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.1719839463 Aug 19 04:23:06 PM PDT 24 Aug 19 04:23:14 PM PDT 24 1118870000 ps
T195 /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.2684900428 Aug 19 04:21:08 PM PDT 24 Aug 19 04:21:18 PM PDT 24 1235510000 ps
T196 /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.4169485075 Aug 19 04:23:33 PM PDT 24 Aug 19 04:23:45 PM PDT 24 1559070000 ps
T197 /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.2074172124 Aug 19 04:18:13 PM PDT 24 Aug 19 04:18:22 PM PDT 24 1469990000 ps
T198 /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.2666070868 Aug 19 04:19:15 PM PDT 24 Aug 19 04:19:22 PM PDT 24 1359670000 ps
T199 /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1372598556 Aug 19 04:22:59 PM PDT 24 Aug 19 04:23:07 PM PDT 24 1443910000 ps
T200 /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.3356048830 Aug 19 04:19:16 PM PDT 24 Aug 19 04:19:25 PM PDT 24 1434250000 ps

Test location /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.2807075437
Short name T10
Test name
Test status
Simulation time 1526270000 ps
CPU time 3.95 seconds
Started Aug 19 04:18:14 PM PDT 24
Finished Aug 19 04:18:22 PM PDT 24
Peak memory 164924 kb
Host smart-7451cf56-858e-43ba-bf2a-5476c2272eda
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2807075437 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.2807075437
Directory /workspace/10.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.3462566933
Short name T18
Test name
Test status
Simulation time 336807670000 ps
CPU time 967.21 seconds
Started Aug 19 04:18:09 PM PDT 24
Finished Aug 19 04:59:19 PM PDT 24
Peak memory 159484 kb
Host smart-f4abc0d8-b0bd-4c08-af05-32f9ad89efb2
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3462566933 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.3462566933
Directory /workspace/0.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.4143520750
Short name T30
Test name
Test status
Simulation time 336377410000 ps
CPU time 956.94 seconds
Started Aug 19 04:18:10 PM PDT 24
Finished Aug 19 04:57:02 PM PDT 24
Peak memory 159700 kb
Host smart-f1c51160-c9bc-4f3b-802a-bbbb8b16e98e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4143520750 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.4143520750
Directory /workspace/0.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.1039378277
Short name T125
Test name
Test status
Simulation time 336361670000 ps
CPU time 654.91 seconds
Started Aug 19 04:24:03 PM PDT 24
Finished Aug 19 04:51:06 PM PDT 24
Peak memory 160288 kb
Host smart-c14d9b96-066f-4768-b489-ff3c2b52411f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1039378277 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.1039378277
Directory /workspace/1.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.3885436398
Short name T24
Test name
Test status
Simulation time 336703570000 ps
CPU time 880.83 seconds
Started Aug 19 04:18:14 PM PDT 24
Finished Aug 19 04:55:25 PM PDT 24
Peak memory 158692 kb
Host smart-cc86258c-f499-4931-a2d4-680fb0988137
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3885436398 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.3885436398
Directory /workspace/10.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.652078345
Short name T117
Test name
Test status
Simulation time 336888750000 ps
CPU time 849.68 seconds
Started Aug 19 04:18:02 PM PDT 24
Finished Aug 19 04:52:32 PM PDT 24
Peak memory 159848 kb
Host smart-c7167d28-c747-48ae-8b25-a5c4a37c7c21
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=652078345 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.652078345
Directory /workspace/11.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.3800620759
Short name T28
Test name
Test status
Simulation time 336612150000 ps
CPU time 848.86 seconds
Started Aug 19 04:18:05 PM PDT 24
Finished Aug 19 04:52:38 PM PDT 24
Peak memory 159848 kb
Host smart-fffa3b0c-4d66-4c52-871f-079eb13ee2e7
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3800620759 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.3800620759
Directory /workspace/12.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.2001484776
Short name T114
Test name
Test status
Simulation time 337025750000 ps
CPU time 983.84 seconds
Started Aug 19 04:18:10 PM PDT 24
Finished Aug 19 04:58:06 PM PDT 24
Peak memory 159652 kb
Host smart-acfab846-f8ae-4bb3-8e0a-ef47d349ff9f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2001484776 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.2001484776
Directory /workspace/13.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.2657243593
Short name T131
Test name
Test status
Simulation time 336677570000 ps
CPU time 806.09 seconds
Started Aug 19 04:19:15 PM PDT 24
Finished Aug 19 04:52:33 PM PDT 24
Peak memory 159148 kb
Host smart-ffab6246-bcae-4e31-b78e-2b16b0f3185a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2657243593 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.2657243593
Directory /workspace/14.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.2112914866
Short name T6
Test name
Test status
Simulation time 337031130000 ps
CPU time 911.94 seconds
Started Aug 19 04:18:14 PM PDT 24
Finished Aug 19 04:56:04 PM PDT 24
Peak memory 158260 kb
Host smart-1e882b03-887e-47db-b39a-0e1763b13321
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2112914866 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.2112914866
Directory /workspace/15.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.3080165808
Short name T147
Test name
Test status
Simulation time 336912790000 ps
CPU time 902.74 seconds
Started Aug 19 04:18:15 PM PDT 24
Finished Aug 19 04:55:52 PM PDT 24
Peak memory 160140 kb
Host smart-8fd63d32-dfbc-41bd-b11e-ebf820a718c7
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3080165808 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.3080165808
Directory /workspace/16.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.2669104579
Short name T116
Test name
Test status
Simulation time 336785530000 ps
CPU time 627.23 seconds
Started Aug 19 04:19:17 PM PDT 24
Finished Aug 19 04:44:54 PM PDT 24
Peak memory 160404 kb
Host smart-279e2d4e-1259-4d04-b9d9-90bc683887c6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2669104579 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.2669104579
Directory /workspace/17.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.2320054267
Short name T144
Test name
Test status
Simulation time 336980070000 ps
CPU time 849.48 seconds
Started Aug 19 04:18:02 PM PDT 24
Finished Aug 19 04:52:37 PM PDT 24
Peak memory 159848 kb
Host smart-3e7111fa-0a89-49df-b3eb-22f5e54ba1c6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2320054267 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.2320054267
Directory /workspace/18.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2065866580
Short name T130
Test name
Test status
Simulation time 336730890000 ps
CPU time 1002.11 seconds
Started Aug 19 04:18:06 PM PDT 24
Finished Aug 19 04:59:22 PM PDT 24
Peak memory 158464 kb
Host smart-3eba6062-c64d-4237-9676-8fbca97a5843
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2065866580 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.2065866580
Directory /workspace/19.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.289612371
Short name T148
Test name
Test status
Simulation time 336800610000 ps
CPU time 949.37 seconds
Started Aug 19 04:18:10 PM PDT 24
Finished Aug 19 04:56:54 PM PDT 24
Peak memory 159944 kb
Host smart-2ae9db19-1479-4c16-a2d0-797994dc986f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=289612371 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.289612371
Directory /workspace/2.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.3867185635
Short name T5
Test name
Test status
Simulation time 336417030000 ps
CPU time 1001.41 seconds
Started Aug 19 04:21:34 PM PDT 24
Finished Aug 19 05:02:29 PM PDT 24
Peak memory 160476 kb
Host smart-32b4d31c-de05-42c9-8c56-9623bdd2a943
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3867185635 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.3867185635
Directory /workspace/20.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.3737062611
Short name T29
Test name
Test status
Simulation time 336540470000 ps
CPU time 712.6 seconds
Started Aug 19 04:19:16 PM PDT 24
Finished Aug 19 04:48:20 PM PDT 24
Peak memory 160420 kb
Host smart-f30b1e65-3962-4abc-9a87-fbea8f6e2b21
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3737062611 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.3737062611
Directory /workspace/21.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.3025838131
Short name T132
Test name
Test status
Simulation time 336604670000 ps
CPU time 812.37 seconds
Started Aug 19 04:22:02 PM PDT 24
Finished Aug 19 04:55:42 PM PDT 24
Peak memory 160568 kb
Host smart-c08841cb-79a2-4b1e-bc0c-5afa95772702
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3025838131 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.3025838131
Directory /workspace/22.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.2867005522
Short name T112
Test name
Test status
Simulation time 336875550000 ps
CPU time 714.9 seconds
Started Aug 19 04:19:16 PM PDT 24
Finished Aug 19 04:48:52 PM PDT 24
Peak memory 160480 kb
Host smart-eede9491-24b6-456e-a47a-ca48a0fa7ddf
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2867005522 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.2867005522
Directory /workspace/23.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.317788553
Short name T121
Test name
Test status
Simulation time 336587450000 ps
CPU time 746.97 seconds
Started Aug 19 04:21:55 PM PDT 24
Finished Aug 19 04:52:27 PM PDT 24
Peak memory 160584 kb
Host smart-09de51fb-cba8-4251-bbcf-60cf6bd3be58
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=317788553 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.317788553
Directory /workspace/24.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.2732301763
Short name T124
Test name
Test status
Simulation time 336894530000 ps
CPU time 658.59 seconds
Started Aug 19 04:22:44 PM PDT 24
Finished Aug 19 04:49:47 PM PDT 24
Peak memory 160584 kb
Host smart-45b0ccc3-d7b6-4f2d-a5fe-0ff925dfe282
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2732301763 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.2732301763
Directory /workspace/25.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1950815709
Short name T113
Test name
Test status
Simulation time 336868150000 ps
CPU time 755.2 seconds
Started Aug 19 04:19:05 PM PDT 24
Finished Aug 19 04:50:01 PM PDT 24
Peak memory 160792 kb
Host smart-09a558f2-1134-487e-9edb-cf4f6dd39502
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1950815709 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.1950815709
Directory /workspace/26.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.2926917283
Short name T134
Test name
Test status
Simulation time 336546770000 ps
CPU time 693.35 seconds
Started Aug 19 04:19:29 PM PDT 24
Finished Aug 19 04:47:55 PM PDT 24
Peak memory 160628 kb
Host smart-fbf160ac-25e6-4d85-bf63-73ec0d20e8c9
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2926917283 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.2926917283
Directory /workspace/27.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.546665117
Short name T27
Test name
Test status
Simulation time 336576530000 ps
CPU time 798.32 seconds
Started Aug 19 04:19:15 PM PDT 24
Finished Aug 19 04:51:48 PM PDT 24
Peak memory 159208 kb
Host smart-c7a496d0-3e12-4c93-8404-80438c66e550
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=546665117 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.546665117
Directory /workspace/28.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.3056941543
Short name T119
Test name
Test status
Simulation time 336502910000 ps
CPU time 879.45 seconds
Started Aug 19 04:19:28 PM PDT 24
Finished Aug 19 04:55:12 PM PDT 24
Peak memory 160632 kb
Host smart-096cad6f-4715-4184-8ff3-cedcf05f8f49
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3056941543 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.3056941543
Directory /workspace/29.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.654319653
Short name T133
Test name
Test status
Simulation time 336677450000 ps
CPU time 968.77 seconds
Started Aug 19 04:18:11 PM PDT 24
Finished Aug 19 04:57:43 PM PDT 24
Peak memory 160220 kb
Host smart-bce6cbf4-bf79-406e-81ae-101a74f00d8d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=654319653 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.654319653
Directory /workspace/3.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.613064563
Short name T146
Test name
Test status
Simulation time 336894110000 ps
CPU time 565.3 seconds
Started Aug 19 04:18:51 PM PDT 24
Finished Aug 19 04:42:48 PM PDT 24
Peak memory 160928 kb
Host smart-2e465287-16e9-4e7d-8865-494e8a8769ac
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=613064563 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.613064563
Directory /workspace/30.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.725745173
Short name T127
Test name
Test status
Simulation time 336554710000 ps
CPU time 591.83 seconds
Started Aug 19 04:22:45 PM PDT 24
Finished Aug 19 04:46:59 PM PDT 24
Peak memory 158904 kb
Host smart-d5bf0497-a33b-4d39-871b-5c9002009b22
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=725745173 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.725745173
Directory /workspace/31.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.3784278072
Short name T143
Test name
Test status
Simulation time 336809490000 ps
CPU time 552.33 seconds
Started Aug 19 04:22:56 PM PDT 24
Finished Aug 19 04:45:54 PM PDT 24
Peak memory 159976 kb
Host smart-39301ea3-6d3d-4dcb-a35b-03d85cd7362d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3784278072 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.3784278072
Directory /workspace/32.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.4001855003
Short name T142
Test name
Test status
Simulation time 336418590000 ps
CPU time 717.12 seconds
Started Aug 19 04:19:54 PM PDT 24
Finished Aug 19 04:49:30 PM PDT 24
Peak memory 160796 kb
Host smart-7b1daa37-a563-4181-88dd-0988f9af3992
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4001855003 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.4001855003
Directory /workspace/33.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.3853584943
Short name T126
Test name
Test status
Simulation time 336489070000 ps
CPU time 864.63 seconds
Started Aug 19 04:20:05 PM PDT 24
Finished Aug 19 04:55:14 PM PDT 24
Peak memory 160512 kb
Host smart-b59bb2e2-cfed-4d14-a449-95e1738d0816
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3853584943 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.3853584943
Directory /workspace/34.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.1241062112
Short name T135
Test name
Test status
Simulation time 336845970000 ps
CPU time 842.37 seconds
Started Aug 19 04:18:38 PM PDT 24
Finished Aug 19 04:52:53 PM PDT 24
Peak memory 159848 kb
Host smart-a19e0f55-870d-4122-9657-35f7b492d433
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1241062112 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.1241062112
Directory /workspace/35.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.3687241614
Short name T26
Test name
Test status
Simulation time 336738150000 ps
CPU time 696.96 seconds
Started Aug 19 04:21:51 PM PDT 24
Finished Aug 19 04:50:29 PM PDT 24
Peak memory 160628 kb
Host smart-8fd53b86-fdb8-4843-b490-3dbaeecf4f84
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3687241614 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.3687241614
Directory /workspace/36.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.1206159315
Short name T122
Test name
Test status
Simulation time 336747230000 ps
CPU time 752.34 seconds
Started Aug 19 04:19:54 PM PDT 24
Finished Aug 19 04:50:45 PM PDT 24
Peak memory 160796 kb
Host smart-c4eec786-d7d1-4e10-974d-9c93b6ac3145
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1206159315 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.1206159315
Directory /workspace/37.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.2308273435
Short name T140
Test name
Test status
Simulation time 336422210000 ps
CPU time 602.01 seconds
Started Aug 19 04:22:57 PM PDT 24
Finished Aug 19 04:48:08 PM PDT 24
Peak memory 158828 kb
Host smart-184457ca-6f61-4d92-9ee5-44ec1baf8874
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2308273435 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.2308273435
Directory /workspace/38.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.2713467962
Short name T118
Test name
Test status
Simulation time 336832730000 ps
CPU time 858.92 seconds
Started Aug 19 04:21:38 PM PDT 24
Finished Aug 19 04:57:03 PM PDT 24
Peak memory 160604 kb
Host smart-ce9e5ab0-cfee-4837-afb7-877092ab85b3
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2713467962 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.2713467962
Directory /workspace/39.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.1976012111
Short name T25
Test name
Test status
Simulation time 336907470000 ps
CPU time 1034.63 seconds
Started Aug 19 04:18:15 PM PDT 24
Finished Aug 19 05:00:56 PM PDT 24
Peak memory 160856 kb
Host smart-e7c88155-aff4-4f72-9467-5ba2b39992fd
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1976012111 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.1976012111
Directory /workspace/4.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.633025941
Short name T115
Test name
Test status
Simulation time 336754430000 ps
CPU time 574.9 seconds
Started Aug 19 04:23:06 PM PDT 24
Finished Aug 19 04:47:13 PM PDT 24
Peak memory 159496 kb
Host smart-23cb984d-515b-4363-83d2-a7a0ff3cb933
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=633025941 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.633025941
Directory /workspace/40.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.1388896831
Short name T141
Test name
Test status
Simulation time 336335510000 ps
CPU time 627.9 seconds
Started Aug 19 04:22:54 PM PDT 24
Finished Aug 19 04:48:19 PM PDT 24
Peak memory 159456 kb
Host smart-adb9e372-0ece-47c3-9c5b-d8c564700c4c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1388896831 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.1388896831
Directory /workspace/41.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.3409614913
Short name T120
Test name
Test status
Simulation time 336591030000 ps
CPU time 560.26 seconds
Started Aug 19 04:20:58 PM PDT 24
Finished Aug 19 04:45:06 PM PDT 24
Peak memory 160932 kb
Host smart-8a43da08-6c7e-47f2-8c93-79221bde0893
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3409614913 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.3409614913
Directory /workspace/42.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.696024504
Short name T138
Test name
Test status
Simulation time 336395610000 ps
CPU time 618.5 seconds
Started Aug 19 04:23:11 PM PDT 24
Finished Aug 19 04:48:38 PM PDT 24
Peak memory 160508 kb
Host smart-4c1fd53f-a50c-400b-ab65-15f29fb20f0d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=696024504 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.696024504
Directory /workspace/43.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.4123155004
Short name T7
Test name
Test status
Simulation time 337079110000 ps
CPU time 879.34 seconds
Started Aug 19 04:20:11 PM PDT 24
Finished Aug 19 04:55:55 PM PDT 24
Peak memory 160632 kb
Host smart-a8b74b97-b562-4edb-b4c2-ded08f5a5cb1
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4123155004 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.4123155004
Directory /workspace/44.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.4167485968
Short name T145
Test name
Test status
Simulation time 336894410000 ps
CPU time 585.23 seconds
Started Aug 19 04:23:24 PM PDT 24
Finished Aug 19 04:47:35 PM PDT 24
Peak memory 159492 kb
Host smart-b7f11d76-9481-4360-954e-df3c052d8831
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4167485968 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.4167485968
Directory /workspace/45.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.3737836353
Short name T111
Test name
Test status
Simulation time 336823230000 ps
CPU time 570.26 seconds
Started Aug 19 04:22:58 PM PDT 24
Finished Aug 19 04:46:31 PM PDT 24
Peak memory 159756 kb
Host smart-9faf5cb0-7b70-4076-a017-90d5bfdd786f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3737836353 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.3737836353
Directory /workspace/46.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.3825394681
Short name T129
Test name
Test status
Simulation time 336809170000 ps
CPU time 704.36 seconds
Started Aug 19 04:23:13 PM PDT 24
Finished Aug 19 04:52:38 PM PDT 24
Peak memory 160428 kb
Host smart-58ac6685-d931-496c-9d8d-c3a09502b846
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3825394681 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.3825394681
Directory /workspace/47.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.3092988122
Short name T149
Test name
Test status
Simulation time 336632950000 ps
CPU time 667.58 seconds
Started Aug 19 04:22:58 PM PDT 24
Finished Aug 19 04:50:34 PM PDT 24
Peak memory 160120 kb
Host smart-51f94d4f-b275-4081-bf0a-15c2a842e007
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3092988122 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.3092988122
Directory /workspace/48.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.776104401
Short name T139
Test name
Test status
Simulation time 336555250000 ps
CPU time 839.13 seconds
Started Aug 19 04:20:33 PM PDT 24
Finished Aug 19 04:56:25 PM PDT 24
Peak memory 160480 kb
Host smart-dbeaf4ea-5f21-45ea-9a6c-d1897d968d07
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=776104401 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.776104401
Directory /workspace/49.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.1502996564
Short name T136
Test name
Test status
Simulation time 336773050000 ps
CPU time 1044.58 seconds
Started Aug 19 04:18:13 PM PDT 24
Finished Aug 19 05:01:00 PM PDT 24
Peak memory 160856 kb
Host smart-b1cebc57-d2b6-4fa7-8276-2233b2ce682c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1502996564 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.1502996564
Directory /workspace/5.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.239380641
Short name T128
Test name
Test status
Simulation time 336468030000 ps
CPU time 991.55 seconds
Started Aug 19 04:18:10 PM PDT 24
Finished Aug 19 04:59:45 PM PDT 24
Peak memory 160196 kb
Host smart-fb62cc13-01ae-42da-a4ac-245a75e34a00
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=239380641 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.239380641
Directory /workspace/6.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.4071295864
Short name T150
Test name
Test status
Simulation time 336609630000 ps
CPU time 1038.69 seconds
Started Aug 19 04:18:15 PM PDT 24
Finished Aug 19 05:00:57 PM PDT 24
Peak memory 160856 kb
Host smart-51e521b1-e79c-45af-8ac5-9cbc9916a197
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4071295864 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.4071295864
Directory /workspace/7.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.3996316303
Short name T123
Test name
Test status
Simulation time 336681130000 ps
CPU time 887.89 seconds
Started Aug 19 04:18:48 PM PDT 24
Finished Aug 19 04:55:39 PM PDT 24
Peak memory 159664 kb
Host smart-26e5a69e-4f73-4438-acdc-41a144b70c92
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3996316303 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.3996316303
Directory /workspace/8.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.2398841065
Short name T137
Test name
Test status
Simulation time 336965930000 ps
CPU time 958.19 seconds
Started Aug 19 04:18:10 PM PDT 24
Finished Aug 19 04:59:04 PM PDT 24
Peak memory 160152 kb
Host smart-fdc28565-71b4-4193-83fd-4b9547e7e8bf
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2398841065 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.2398841065
Directory /workspace/9.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.4229783402
Short name T109
Test name
Test status
Simulation time 336503390000 ps
CPU time 1038.64 seconds
Started Aug 19 04:18:15 PM PDT 24
Finished Aug 19 05:00:55 PM PDT 24
Peak memory 160860 kb
Host smart-5dfd859b-dbf9-4595-9ee1-ebbe68fd2f86
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4229783402 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.4229783402
Directory /workspace/1.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.368314115
Short name T73
Test name
Test status
Simulation time 337151970000 ps
CPU time 886.36 seconds
Started Aug 19 04:19:28 PM PDT 24
Finished Aug 19 04:55:24 PM PDT 24
Peak memory 160632 kb
Host smart-6c5221fc-279b-4383-8065-bd17bf88120e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=368314115 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.368314115
Directory /workspace/10.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.2054929094
Short name T88
Test name
Test status
Simulation time 336764830000 ps
CPU time 916.63 seconds
Started Aug 19 04:18:14 PM PDT 24
Finished Aug 19 04:56:08 PM PDT 24
Peak memory 158192 kb
Host smart-35a7d349-c1ae-43eb-afbf-7513980bef12
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2054929094 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.2054929094
Directory /workspace/11.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.796793781
Short name T81
Test name
Test status
Simulation time 337020310000 ps
CPU time 1057.04 seconds
Started Aug 19 04:18:15 PM PDT 24
Finished Aug 19 05:00:58 PM PDT 24
Peak memory 160864 kb
Host smart-a74b3831-1059-4b81-9806-920acc0681cb
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=796793781 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.796793781
Directory /workspace/12.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.4217528068
Short name T105
Test name
Test status
Simulation time 337053970000 ps
CPU time 849.73 seconds
Started Aug 19 04:18:11 PM PDT 24
Finished Aug 19 04:53:28 PM PDT 24
Peak memory 160180 kb
Host smart-083b5d42-e307-4073-ae92-1c511b1281e8
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4217528068 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.4217528068
Directory /workspace/13.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.2505361707
Short name T20
Test name
Test status
Simulation time 336660610000 ps
CPU time 1023.91 seconds
Started Aug 19 04:18:14 PM PDT 24
Finished Aug 19 05:00:52 PM PDT 24
Peak memory 160868 kb
Host smart-f2117400-68ec-4391-9f0f-dd6a3c0b3bfb
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2505361707 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.2505361707
Directory /workspace/14.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.920404052
Short name T93
Test name
Test status
Simulation time 336432430000 ps
CPU time 855.91 seconds
Started Aug 19 04:18:09 PM PDT 24
Finished Aug 19 04:54:08 PM PDT 24
Peak memory 159120 kb
Host smart-59fbc68c-e109-4abf-bd1d-119eb074c5e9
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=920404052 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.920404052
Directory /workspace/15.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.2064593520
Short name T98
Test name
Test status
Simulation time 336374010000 ps
CPU time 958.32 seconds
Started Aug 19 04:18:12 PM PDT 24
Finished Aug 19 04:57:25 PM PDT 24
Peak memory 160224 kb
Host smart-01d6579e-88b8-4509-9624-a23375e497a6
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2064593520 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.2064593520
Directory /workspace/16.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.1965972895
Short name T103
Test name
Test status
Simulation time 336358370000 ps
CPU time 985.37 seconds
Started Aug 19 04:18:10 PM PDT 24
Finished Aug 19 04:59:34 PM PDT 24
Peak memory 160156 kb
Host smart-b56721e0-16ee-4488-9a7d-bbd8b02f971d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1965972895 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.1965972895
Directory /workspace/17.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.1159483337
Short name T97
Test name
Test status
Simulation time 336927810000 ps
CPU time 986.54 seconds
Started Aug 19 04:18:09 PM PDT 24
Finished Aug 19 04:59:35 PM PDT 24
Peak memory 159040 kb
Host smart-f9352964-eb4b-4bac-8d84-0f76e6bebfff
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1159483337 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.1159483337
Directory /workspace/18.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.3657693045
Short name T87
Test name
Test status
Simulation time 336916310000 ps
CPU time 1023.81 seconds
Started Aug 19 04:18:15 PM PDT 24
Finished Aug 19 05:00:55 PM PDT 24
Peak memory 160868 kb
Host smart-b6ddd398-d55a-4b55-b27a-30b13e8bed32
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3657693045 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.3657693045
Directory /workspace/19.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.2944646897
Short name T101
Test name
Test status
Simulation time 336589430000 ps
CPU time 1023.53 seconds
Started Aug 19 04:18:15 PM PDT 24
Finished Aug 19 05:00:59 PM PDT 24
Peak memory 160860 kb
Host smart-4d3d8251-3c77-4d5e-8cea-9e683b09f098
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2944646897 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.2944646897
Directory /workspace/2.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.332230503
Short name T90
Test name
Test status
Simulation time 336994970000 ps
CPU time 888.62 seconds
Started Aug 19 04:18:04 PM PDT 24
Finished Aug 19 04:54:49 PM PDT 24
Peak memory 160696 kb
Host smart-68c8669d-806d-4699-9f4a-8cf9476be276
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=332230503 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.332230503
Directory /workspace/20.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3572417119
Short name T106
Test name
Test status
Simulation time 336476870000 ps
CPU time 881.28 seconds
Started Aug 19 04:18:48 PM PDT 24
Finished Aug 19 04:55:40 PM PDT 24
Peak memory 159344 kb
Host smart-b0717a96-6b3c-4b44-aca2-6add87d42d5e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3572417119 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.3572417119
Directory /workspace/21.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.3550744523
Short name T19
Test name
Test status
Simulation time 336731390000 ps
CPU time 994.71 seconds
Started Aug 19 04:18:06 PM PDT 24
Finished Aug 19 04:59:11 PM PDT 24
Peak memory 158704 kb
Host smart-559c400f-923d-4bff-928e-9c836e8a34ea
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3550744523 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.3550744523
Directory /workspace/22.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.973473517
Short name T94
Test name
Test status
Simulation time 336924250000 ps
CPU time 993.87 seconds
Started Aug 19 04:18:11 PM PDT 24
Finished Aug 19 04:58:30 PM PDT 24
Peak memory 160220 kb
Host smart-18eb7694-f075-4c25-82a9-78635544fed9
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=973473517 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.973473517
Directory /workspace/23.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.2849787924
Short name T89
Test name
Test status
Simulation time 336735910000 ps
CPU time 1036.99 seconds
Started Aug 19 04:18:14 PM PDT 24
Finished Aug 19 05:00:54 PM PDT 24
Peak memory 160868 kb
Host smart-5238e990-b59b-4a11-a8bc-8b26e4cbb8e2
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2849787924 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.2849787924
Directory /workspace/24.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.2430832782
Short name T99
Test name
Test status
Simulation time 336795050000 ps
CPU time 888.94 seconds
Started Aug 19 04:18:04 PM PDT 24
Finished Aug 19 04:54:48 PM PDT 24
Peak memory 160692 kb
Host smart-3eb49d63-ad1e-4be0-b818-a5a029d797ef
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2430832782 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.2430832782
Directory /workspace/25.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.341728960
Short name T100
Test name
Test status
Simulation time 336705010000 ps
CPU time 1006.76 seconds
Started Aug 19 04:18:06 PM PDT 24
Finished Aug 19 04:59:21 PM PDT 24
Peak memory 158804 kb
Host smart-2f74a627-4f92-433c-8cd8-80baafc86aeb
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=341728960 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.341728960
Directory /workspace/26.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.1075647705
Short name T80
Test name
Test status
Simulation time 336749510000 ps
CPU time 807.58 seconds
Started Aug 19 04:19:16 PM PDT 24
Finished Aug 19 04:52:32 PM PDT 24
Peak memory 160408 kb
Host smart-e76d5ee6-c36c-47b1-90ec-3f128b6ae48b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1075647705 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.1075647705
Directory /workspace/27.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.3641117221
Short name T102
Test name
Test status
Simulation time 336704730000 ps
CPU time 1001.29 seconds
Started Aug 19 04:18:10 PM PDT 24
Finished Aug 19 04:58:28 PM PDT 24
Peak memory 160220 kb
Host smart-3495a7de-1ac8-4d18-b14b-31ea8a896be4
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3641117221 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.3641117221
Directory /workspace/28.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.980147646
Short name T107
Test name
Test status
Simulation time 336740730000 ps
CPU time 884.61 seconds
Started Aug 19 04:18:04 PM PDT 24
Finished Aug 19 04:54:48 PM PDT 24
Peak memory 160696 kb
Host smart-ee417237-1cd4-4a9f-bfee-4acf2a96dfaa
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=980147646 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.980147646
Directory /workspace/29.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.3021949120
Short name T78
Test name
Test status
Simulation time 337080150000 ps
CPU time 875.81 seconds
Started Aug 19 04:18:11 PM PDT 24
Finished Aug 19 04:54:17 PM PDT 24
Peak memory 160160 kb
Host smart-16c241a4-0acb-42d6-9acb-d189e28bb50d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3021949120 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.3021949120
Directory /workspace/3.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.4010808109
Short name T21
Test name
Test status
Simulation time 336934550000 ps
CPU time 887.75 seconds
Started Aug 19 04:20:54 PM PDT 24
Finished Aug 19 04:57:14 PM PDT 24
Peak memory 160516 kb
Host smart-0dacb018-17d2-48f2-8208-4e47cb7332ff
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4010808109 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.4010808109
Directory /workspace/30.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.419437079
Short name T22
Test name
Test status
Simulation time 337035310000 ps
CPU time 740.47 seconds
Started Aug 19 04:20:53 PM PDT 24
Finished Aug 19 04:50:58 PM PDT 24
Peak memory 160588 kb
Host smart-40d35f57-470e-4b50-aa91-a46587147e1d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=419437079 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.419437079
Directory /workspace/31.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.931507414
Short name T85
Test name
Test status
Simulation time 337088770000 ps
CPU time 1003.53 seconds
Started Aug 19 04:18:06 PM PDT 24
Finished Aug 19 04:59:31 PM PDT 24
Peak memory 158592 kb
Host smart-77fe7788-6850-4603-b100-c40b09a6fe36
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=931507414 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.931507414
Directory /workspace/32.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.4090752781
Short name T72
Test name
Test status
Simulation time 336995350000 ps
CPU time 831.06 seconds
Started Aug 19 04:18:11 PM PDT 24
Finished Aug 19 04:53:30 PM PDT 24
Peak memory 160180 kb
Host smart-7b3c6c3e-812c-4fed-9605-4328180e126c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4090752781 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.4090752781
Directory /workspace/33.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.3075649551
Short name T75
Test name
Test status
Simulation time 337005390000 ps
CPU time 808.22 seconds
Started Aug 19 04:18:11 PM PDT 24
Finished Aug 19 04:52:53 PM PDT 24
Peak memory 160180 kb
Host smart-d2568866-2396-4deb-8d24-b532becb0835
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3075649551 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.3075649551
Directory /workspace/34.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.3303129182
Short name T15
Test name
Test status
Simulation time 337087770000 ps
CPU time 938.66 seconds
Started Aug 19 04:18:09 PM PDT 24
Finished Aug 19 04:59:00 PM PDT 24
Peak memory 158616 kb
Host smart-1da0443d-46f0-4121-8bb6-4ab420b88490
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3303129182 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.3303129182
Directory /workspace/35.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.354113936
Short name T110
Test name
Test status
Simulation time 336825170000 ps
CPU time 859.58 seconds
Started Aug 19 04:18:15 PM PDT 24
Finished Aug 19 04:54:41 PM PDT 24
Peak memory 160140 kb
Host smart-23107297-9d22-4578-886b-14fe24e1620b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=354113936 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.354113936
Directory /workspace/36.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.4011710637
Short name T74
Test name
Test status
Simulation time 336584190000 ps
CPU time 895.48 seconds
Started Aug 19 04:18:11 PM PDT 24
Finished Aug 19 04:54:50 PM PDT 24
Peak memory 160224 kb
Host smart-f699fa72-d80c-4a22-bfe2-c1be54cfbb59
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4011710637 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.4011710637
Directory /workspace/37.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.607651497
Short name T17
Test name
Test status
Simulation time 336590110000 ps
CPU time 623.67 seconds
Started Aug 19 04:23:47 PM PDT 24
Finished Aug 19 04:49:07 PM PDT 24
Peak memory 159744 kb
Host smart-e0a8309c-2f4a-4ddf-9236-5badf09e45fc
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=607651497 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.607651497
Directory /workspace/38.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.1992722421
Short name T96
Test name
Test status
Simulation time 336579710000 ps
CPU time 897.99 seconds
Started Aug 19 04:18:48 PM PDT 24
Finished Aug 19 04:55:59 PM PDT 24
Peak memory 159248 kb
Host smart-b797be30-9c4f-437a-8db5-ca6e99b2ffa3
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1992722421 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.1992722421
Directory /workspace/39.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.2988075725
Short name T76
Test name
Test status
Simulation time 336501510000 ps
CPU time 892.29 seconds
Started Aug 19 04:18:48 PM PDT 24
Finished Aug 19 04:55:52 PM PDT 24
Peak memory 160180 kb
Host smart-e0381ffa-656e-40f7-aab7-3d8b0f7b7fb4
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2988075725 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.2988075725
Directory /workspace/4.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.4189209443
Short name T23
Test name
Test status
Simulation time 336770110000 ps
CPU time 884.24 seconds
Started Aug 19 04:18:49 PM PDT 24
Finished Aug 19 04:55:46 PM PDT 24
Peak memory 160324 kb
Host smart-4e3d9f8c-c225-4cdc-a536-6aa82349497e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4189209443 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.4189209443
Directory /workspace/40.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.4264323507
Short name T104
Test name
Test status
Simulation time 336397450000 ps
CPU time 908.9 seconds
Started Aug 19 04:18:14 PM PDT 24
Finished Aug 19 04:56:12 PM PDT 24
Peak memory 158724 kb
Host smart-984b221e-b136-49e3-8322-0efcd8a7899f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4264323507 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.4264323507
Directory /workspace/41.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.1756858924
Short name T84
Test name
Test status
Simulation time 336565370000 ps
CPU time 937.17 seconds
Started Aug 19 04:18:09 PM PDT 24
Finished Aug 19 04:58:53 PM PDT 24
Peak memory 158652 kb
Host smart-11fceffd-398b-4112-a9d2-9aec2383f008
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1756858924 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.1756858924
Directory /workspace/42.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.3526002220
Short name T79
Test name
Test status
Simulation time 336825650000 ps
CPU time 866.27 seconds
Started Aug 19 04:18:09 PM PDT 24
Finished Aug 19 04:54:17 PM PDT 24
Peak memory 159140 kb
Host smart-5a9627e9-a232-4282-b375-79b7c67e555f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3526002220 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.3526002220
Directory /workspace/43.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.165844727
Short name T71
Test name
Test status
Simulation time 336798110000 ps
CPU time 840.66 seconds
Started Aug 19 04:19:58 PM PDT 24
Finished Aug 19 04:56:00 PM PDT 24
Peak memory 160484 kb
Host smart-b84c283c-6252-449f-897d-db19942f1ab9
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=165844727 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.165844727
Directory /workspace/44.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.899295554
Short name T91
Test name
Test status
Simulation time 336843870000 ps
CPU time 1039.27 seconds
Started Aug 19 04:18:14 PM PDT 24
Finished Aug 19 05:00:57 PM PDT 24
Peak memory 160864 kb
Host smart-e0e94c1c-9b8e-40d4-8e0b-c39844ce85fb
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=899295554 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.899295554
Directory /workspace/45.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.2042409893
Short name T77
Test name
Test status
Simulation time 336527890000 ps
CPU time 892.37 seconds
Started Aug 19 04:18:04 PM PDT 24
Finished Aug 19 04:54:54 PM PDT 24
Peak memory 160656 kb
Host smart-f63b76ec-4239-4033-b2d0-bb643365ed68
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2042409893 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.2042409893
Directory /workspace/46.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.4066699654
Short name T83
Test name
Test status
Simulation time 336623370000 ps
CPU time 887.43 seconds
Started Aug 19 04:18:49 PM PDT 24
Finished Aug 19 04:55:53 PM PDT 24
Peak memory 160324 kb
Host smart-b9acad5b-d039-4f6f-9a00-b655e31a7d91
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4066699654 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.4066699654
Directory /workspace/47.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.4186335340
Short name T82
Test name
Test status
Simulation time 336808450000 ps
CPU time 1040.01 seconds
Started Aug 19 04:18:15 PM PDT 24
Finished Aug 19 05:00:59 PM PDT 24
Peak memory 160868 kb
Host smart-8eca7c50-8a78-4c05-b80d-47183aba2dae
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4186335340 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.4186335340
Directory /workspace/48.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.2100532693
Short name T92
Test name
Test status
Simulation time 336416130000 ps
CPU time 980.52 seconds
Started Aug 19 04:18:11 PM PDT 24
Finished Aug 19 04:58:12 PM PDT 24
Peak memory 160224 kb
Host smart-f057016f-b43d-4de5-a7a3-377d894102d7
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2100532693 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.2100532693
Directory /workspace/49.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.2109154100
Short name T86
Test name
Test status
Simulation time 336750830000 ps
CPU time 864.5 seconds
Started Aug 19 04:18:09 PM PDT 24
Finished Aug 19 04:54:23 PM PDT 24
Peak memory 159120 kb
Host smart-c91c27e4-ccbe-45df-b68b-4c9812333bb9
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2109154100 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.2109154100
Directory /workspace/5.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.278790113
Short name T108
Test name
Test status
Simulation time 337045630000 ps
CPU time 892.97 seconds
Started Aug 19 04:18:04 PM PDT 24
Finished Aug 19 04:55:00 PM PDT 24
Peak memory 160632 kb
Host smart-0d1590f9-46c0-4497-887e-35b5b60475ee
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=278790113 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.278790113
Directory /workspace/6.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.3556380057
Short name T16
Test name
Test status
Simulation time 337077110000 ps
CPU time 932.65 seconds
Started Aug 19 04:18:09 PM PDT 24
Finished Aug 19 04:58:47 PM PDT 24
Peak memory 158592 kb
Host smart-72b8fe3d-9994-4812-ad1e-488f2eba246d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3556380057 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.3556380057
Directory /workspace/7.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.1240749075
Short name T14
Test name
Test status
Simulation time 336507690000 ps
CPU time 887.66 seconds
Started Aug 19 04:18:49 PM PDT 24
Finished Aug 19 04:55:30 PM PDT 24
Peak memory 160280 kb
Host smart-f14450a1-09e1-4cce-9e2d-c1278de8d850
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1240749075 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.1240749075
Directory /workspace/8.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.1408366882
Short name T95
Test name
Test status
Simulation time 336629550000 ps
CPU time 915.06 seconds
Started Aug 19 04:18:49 PM PDT 24
Finished Aug 19 04:56:35 PM PDT 24
Peak memory 160260 kb
Host smart-3686fea5-6fac-4082-865e-71987f662b41
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1408366882 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.1408366882
Directory /workspace/9.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.1056497485
Short name T192
Test name
Test status
Simulation time 1561350000 ps
CPU time 4.78 seconds
Started Aug 19 04:18:48 PM PDT 24
Finished Aug 19 04:18:59 PM PDT 24
Peak memory 163292 kb
Host smart-8b25afe8-c82a-4411-bca4-d20f81669ae4
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1056497485 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.1056497485
Directory /workspace/0.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.665803122
Short name T176
Test name
Test status
Simulation time 1566750000 ps
CPU time 4.05 seconds
Started Aug 19 04:22:57 PM PDT 24
Finished Aug 19 04:23:06 PM PDT 24
Peak memory 166076 kb
Host smart-70fe00ce-419d-4d41-abae-c7549c3c8d43
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=665803122 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.665803122
Directory /workspace/1.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.1309006471
Short name T181
Test name
Test status
Simulation time 1501450000 ps
CPU time 3.18 seconds
Started Aug 19 04:22:54 PM PDT 24
Finished Aug 19 04:23:01 PM PDT 24
Peak memory 164100 kb
Host smart-53fe8a0a-a6bf-4d78-bc23-caec112331cf
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1309006471 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.1309006471
Directory /workspace/10.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.3296503365
Short name T187
Test name
Test status
Simulation time 1455570000 ps
CPU time 4.45 seconds
Started Aug 19 04:23:13 PM PDT 24
Finished Aug 19 04:23:22 PM PDT 24
Peak memory 164468 kb
Host smart-e743f5e2-a5d7-4fa0-a449-7aa97eef4bf3
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3296503365 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.3296503365
Directory /workspace/11.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.3467584762
Short name T160
Test name
Test status
Simulation time 1385110000 ps
CPU time 5.16 seconds
Started Aug 19 04:20:43 PM PDT 24
Finished Aug 19 04:20:54 PM PDT 24
Peak memory 164748 kb
Host smart-947296f6-bca0-41fb-ac52-a6c6b5965a24
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3467584762 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.3467584762
Directory /workspace/12.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.780473550
Short name T189
Test name
Test status
Simulation time 1497050000 ps
CPU time 3.74 seconds
Started Aug 19 04:23:24 PM PDT 24
Finished Aug 19 04:23:32 PM PDT 24
Peak memory 164016 kb
Host smart-7598fae3-fbb7-4913-a591-eca5d090b888
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=780473550 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.780473550
Directory /workspace/13.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.4175354307
Short name T157
Test name
Test status
Simulation time 1354970000 ps
CPU time 3.58 seconds
Started Aug 19 04:20:04 PM PDT 24
Finished Aug 19 04:20:12 PM PDT 24
Peak memory 164668 kb
Host smart-095f2941-450f-4121-aed9-e0b47955544e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4175354307 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.4175354307
Directory /workspace/14.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.4208357197
Short name T151
Test name
Test status
Simulation time 1381310000 ps
CPU time 3.45 seconds
Started Aug 19 04:22:58 PM PDT 24
Finished Aug 19 04:23:06 PM PDT 24
Peak memory 163824 kb
Host smart-2b300dd6-02fd-477c-aef8-0bd21320195f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4208357197 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.4208357197
Directory /workspace/15.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.3868706775
Short name T164
Test name
Test status
Simulation time 1554050000 ps
CPU time 2.92 seconds
Started Aug 19 04:23:35 PM PDT 24
Finished Aug 19 04:23:42 PM PDT 24
Peak memory 164564 kb
Host smart-2e305266-f0e7-4e60-adf7-48a2f231a772
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3868706775 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.3868706775
Directory /workspace/16.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.1347971545
Short name T183
Test name
Test status
Simulation time 1223350000 ps
CPU time 3.49 seconds
Started Aug 19 04:20:05 PM PDT 24
Finished Aug 19 04:20:13 PM PDT 24
Peak memory 164632 kb
Host smart-b71bf57d-3a81-468d-8eb4-eab7c20ed488
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1347971545 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.1347971545
Directory /workspace/17.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.2272565783
Short name T179
Test name
Test status
Simulation time 1569410000 ps
CPU time 3.16 seconds
Started Aug 19 04:23:21 PM PDT 24
Finished Aug 19 04:23:28 PM PDT 24
Peak memory 164360 kb
Host smart-062931a0-5566-4063-b185-3ef717ffa478
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2272565783 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.2272565783
Directory /workspace/18.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.1322627789
Short name T159
Test name
Test status
Simulation time 1528750000 ps
CPU time 3.69 seconds
Started Aug 19 04:23:13 PM PDT 24
Finished Aug 19 04:23:21 PM PDT 24
Peak memory 164476 kb
Host smart-8828987e-e6c6-4e3e-b000-ceb0886b425b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1322627789 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.1322627789
Directory /workspace/19.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.4177364974
Short name T182
Test name
Test status
Simulation time 1398170000 ps
CPU time 5.26 seconds
Started Aug 19 04:21:52 PM PDT 24
Finished Aug 19 04:22:03 PM PDT 24
Peak memory 164764 kb
Host smart-cc3d54b3-1e1c-4275-8046-ff652e5b9d26
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4177364974 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.4177364974
Directory /workspace/2.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.4169485075
Short name T196
Test name
Test status
Simulation time 1559070000 ps
CPU time 5.36 seconds
Started Aug 19 04:23:33 PM PDT 24
Finished Aug 19 04:23:45 PM PDT 24
Peak memory 163760 kb
Host smart-40935f2d-b97e-45aa-83e8-9853e4dba37b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4169485075 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.4169485075
Directory /workspace/20.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3537038944
Short name T156
Test name
Test status
Simulation time 1543390000 ps
CPU time 3.28 seconds
Started Aug 19 04:23:16 PM PDT 24
Finished Aug 19 04:23:24 PM PDT 24
Peak memory 163684 kb
Host smart-d8039f96-fdc2-4760-ac78-6ed22d8c9dbc
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3537038944 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.3537038944
Directory /workspace/21.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.2527823043
Short name T165
Test name
Test status
Simulation time 1291770000 ps
CPU time 4.45 seconds
Started Aug 19 04:20:53 PM PDT 24
Finished Aug 19 04:21:03 PM PDT 24
Peak memory 164744 kb
Host smart-6841d87b-4273-4c03-9dee-9ba1fcbd2ca3
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2527823043 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.2527823043
Directory /workspace/22.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.4158580388
Short name T177
Test name
Test status
Simulation time 1309610000 ps
CPU time 2.78 seconds
Started Aug 19 04:19:30 PM PDT 24
Finished Aug 19 04:19:36 PM PDT 24
Peak memory 165056 kb
Host smart-edbe60f3-a80e-458b-bd22-b2c56b6d6505
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4158580388 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.4158580388
Directory /workspace/23.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.2004045197
Short name T180
Test name
Test status
Simulation time 1592730000 ps
CPU time 5.75 seconds
Started Aug 19 04:21:59 PM PDT 24
Finished Aug 19 04:22:11 PM PDT 24
Peak memory 164500 kb
Host smart-fd13a865-e6d8-4a06-8deb-5853d5aaa482
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2004045197 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.2004045197
Directory /workspace/24.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.1781993507
Short name T184
Test name
Test status
Simulation time 1195230000 ps
CPU time 2.88 seconds
Started Aug 19 04:23:10 PM PDT 24
Finished Aug 19 04:23:17 PM PDT 24
Peak memory 164556 kb
Host smart-4ac977aa-15f6-4318-8e42-7d9bfe0b44b4
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1781993507 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.1781993507
Directory /workspace/25.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2491307948
Short name T178
Test name
Test status
Simulation time 1281570000 ps
CPU time 4.17 seconds
Started Aug 19 04:22:57 PM PDT 24
Finished Aug 19 04:23:06 PM PDT 24
Peak memory 163800 kb
Host smart-5cc3a4fa-a23d-43c9-87c1-d383649ff0da
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2491307948 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.2491307948
Directory /workspace/26.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.1362082435
Short name T162
Test name
Test status
Simulation time 1551990000 ps
CPU time 3.51 seconds
Started Aug 19 04:23:04 PM PDT 24
Finished Aug 19 04:23:12 PM PDT 24
Peak memory 163084 kb
Host smart-b3a60495-ecae-49b3-8a7c-d9bacc8aa3ef
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1362082435 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.1362082435
Directory /workspace/27.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.2131228009
Short name T188
Test name
Test status
Simulation time 1458790000 ps
CPU time 3.19 seconds
Started Aug 19 04:23:04 PM PDT 24
Finished Aug 19 04:23:11 PM PDT 24
Peak memory 163820 kb
Host smart-7d5b75b0-8b75-4b31-91f7-dc110fdc8b32
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2131228009 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.2131228009
Directory /workspace/28.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.3223000439
Short name T191
Test name
Test status
Simulation time 1518410000 ps
CPU time 4.72 seconds
Started Aug 19 04:21:48 PM PDT 24
Finished Aug 19 04:21:59 PM PDT 24
Peak memory 164656 kb
Host smart-550ffa91-8578-4889-a5da-412a15db7edf
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3223000439 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.3223000439
Directory /workspace/29.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.3844382904
Short name T186
Test name
Test status
Simulation time 1481970000 ps
CPU time 3.61 seconds
Started Aug 19 04:23:06 PM PDT 24
Finished Aug 19 04:23:14 PM PDT 24
Peak memory 164384 kb
Host smart-be6efe6a-df96-4e57-9a83-11c2788b28d7
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3844382904 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.3844382904
Directory /workspace/3.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.196307127
Short name T170
Test name
Test status
Simulation time 1488430000 ps
CPU time 3.21 seconds
Started Aug 19 04:18:05 PM PDT 24
Finished Aug 19 04:18:12 PM PDT 24
Peak memory 165056 kb
Host smart-34b1b375-d5a4-4de2-9bd8-e7da3483389b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=196307127 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.196307127
Directory /workspace/30.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.4131086093
Short name T175
Test name
Test status
Simulation time 1499150000 ps
CPU time 3.86 seconds
Started Aug 19 04:19:16 PM PDT 24
Finished Aug 19 04:19:24 PM PDT 24
Peak memory 162912 kb
Host smart-da6f6091-3f0e-4158-a4d7-aeb5d1867917
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4131086093 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.4131086093
Directory /workspace/31.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.2074172124
Short name T197
Test name
Test status
Simulation time 1469990000 ps
CPU time 3.8 seconds
Started Aug 19 04:18:13 PM PDT 24
Finished Aug 19 04:18:22 PM PDT 24
Peak memory 164908 kb
Host smart-c0a25ad3-868e-4f84-93ab-1d0168366114
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2074172124 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.2074172124
Directory /workspace/32.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.4140721191
Short name T172
Test name
Test status
Simulation time 1370450000 ps
CPU time 3.58 seconds
Started Aug 19 04:18:13 PM PDT 24
Finished Aug 19 04:18:21 PM PDT 24
Peak memory 164764 kb
Host smart-c500d288-f38a-4610-99c5-a66befae8919
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4140721191 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.4140721191
Directory /workspace/33.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.1820517452
Short name T152
Test name
Test status
Simulation time 1505950000 ps
CPU time 3.81 seconds
Started Aug 19 04:19:30 PM PDT 24
Finished Aug 19 04:19:38 PM PDT 24
Peak memory 164668 kb
Host smart-716578d6-0e03-4c2f-afea-a59e8ac08337
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1820517452 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.1820517452
Directory /workspace/34.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.2785862781
Short name T158
Test name
Test status
Simulation time 1511250000 ps
CPU time 4.29 seconds
Started Aug 19 04:18:20 PM PDT 24
Finished Aug 19 04:18:29 PM PDT 24
Peak memory 164924 kb
Host smart-53145f9a-92ca-4ff9-b2a8-c2a90c00da55
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2785862781 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.2785862781
Directory /workspace/35.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.2581093041
Short name T168
Test name
Test status
Simulation time 1500390000 ps
CPU time 4.06 seconds
Started Aug 19 04:18:17 PM PDT 24
Finished Aug 19 04:18:26 PM PDT 24
Peak memory 164924 kb
Host smart-993445ee-4866-4892-944f-8a0ca00dab99
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2581093041 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.2581093041
Directory /workspace/36.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.866760243
Short name T161
Test name
Test status
Simulation time 1600710000 ps
CPU time 4.16 seconds
Started Aug 19 04:19:15 PM PDT 24
Finished Aug 19 04:19:25 PM PDT 24
Peak memory 164300 kb
Host smart-19612073-6f7d-4650-9d1d-025085e0cdf7
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=866760243 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.866760243
Directory /workspace/37.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.111660451
Short name T154
Test name
Test status
Simulation time 1336710000 ps
CPU time 3.64 seconds
Started Aug 19 04:19:15 PM PDT 24
Finished Aug 19 04:19:23 PM PDT 24
Peak memory 163048 kb
Host smart-44a86e68-7cdd-472b-b970-5e582adeae5b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=111660451 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.111660451
Directory /workspace/38.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.3770352446
Short name T167
Test name
Test status
Simulation time 1463110000 ps
CPU time 4.04 seconds
Started Aug 19 04:19:16 PM PDT 24
Finished Aug 19 04:19:24 PM PDT 24
Peak memory 163968 kb
Host smart-b2fb75cb-52d6-46e0-a2c5-7960066f7d41
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3770352446 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.3770352446
Directory /workspace/39.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3175881612
Short name T174
Test name
Test status
Simulation time 1242370000 ps
CPU time 3.95 seconds
Started Aug 19 04:22:57 PM PDT 24
Finished Aug 19 04:23:06 PM PDT 24
Peak memory 162644 kb
Host smart-3825fb83-9521-4986-9032-d33836b9a50a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3175881612 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.3175881612
Directory /workspace/4.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.4012155874
Short name T169
Test name
Test status
Simulation time 1476050000 ps
CPU time 5.18 seconds
Started Aug 19 04:22:03 PM PDT 24
Finished Aug 19 04:22:15 PM PDT 24
Peak memory 164540 kb
Host smart-c0c4ddf1-26ef-4604-a136-f62bd8bb074e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4012155874 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.4012155874
Directory /workspace/40.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.4057247802
Short name T190
Test name
Test status
Simulation time 1608330000 ps
CPU time 4.13 seconds
Started Aug 19 04:19:16 PM PDT 24
Finished Aug 19 04:19:26 PM PDT 24
Peak memory 163912 kb
Host smart-846b0978-217b-47d6-b569-745fcde5b26a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4057247802 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.4057247802
Directory /workspace/41.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.2684900428
Short name T195
Test name
Test status
Simulation time 1235510000 ps
CPU time 4.37 seconds
Started Aug 19 04:21:08 PM PDT 24
Finished Aug 19 04:21:18 PM PDT 24
Peak memory 164632 kb
Host smart-ce1eb549-6ad3-4480-9494-a084d113a6e1
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2684900428 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.2684900428
Directory /workspace/42.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.3068049391
Short name T193
Test name
Test status
Simulation time 1199190000 ps
CPU time 3.62 seconds
Started Aug 19 04:19:15 PM PDT 24
Finished Aug 19 04:19:23 PM PDT 24
Peak memory 163208 kb
Host smart-1e643521-6d0f-4c59-9542-06982ab3a668
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3068049391 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.3068049391
Directory /workspace/43.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.93734373
Short name T166
Test name
Test status
Simulation time 1065630000 ps
CPU time 2.86 seconds
Started Aug 19 04:22:43 PM PDT 24
Finished Aug 19 04:22:50 PM PDT 24
Peak memory 162552 kb
Host smart-22355750-4439-435c-a42a-01211253b482
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=93734373 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.93734373
Directory /workspace/44.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.362546855
Short name T163
Test name
Test status
Simulation time 1492450000 ps
CPU time 4.71 seconds
Started Aug 19 04:19:29 PM PDT 24
Finished Aug 19 04:19:40 PM PDT 24
Peak memory 164692 kb
Host smart-47e2343e-765f-41fe-b84f-2436c3b4ad9b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=362546855 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.362546855
Directory /workspace/45.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.3356048830
Short name T200
Test name
Test status
Simulation time 1434250000 ps
CPU time 3.78 seconds
Started Aug 19 04:19:16 PM PDT 24
Finished Aug 19 04:19:25 PM PDT 24
Peak memory 163792 kb
Host smart-f2fd38f1-edda-4acb-8b0f-3c3bd4734fec
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3356048830 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.3356048830
Directory /workspace/46.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.2881158663
Short name T171
Test name
Test status
Simulation time 1380710000 ps
CPU time 4.1 seconds
Started Aug 19 04:19:17 PM PDT 24
Finished Aug 19 04:19:26 PM PDT 24
Peak memory 164360 kb
Host smart-3f9f0d43-7308-4fd4-b5b2-6981621e3715
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2881158663 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.2881158663
Directory /workspace/47.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.2666070868
Short name T198
Test name
Test status
Simulation time 1359670000 ps
CPU time 3.23 seconds
Started Aug 19 04:19:15 PM PDT 24
Finished Aug 19 04:19:22 PM PDT 24
Peak memory 163076 kb
Host smart-18ab4d77-8b96-4541-8390-07c7dfb08767
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2666070868 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.2666070868
Directory /workspace/48.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.1148004879
Short name T153
Test name
Test status
Simulation time 1361790000 ps
CPU time 3.05 seconds
Started Aug 19 04:19:15 PM PDT 24
Finished Aug 19 04:19:22 PM PDT 24
Peak memory 164152 kb
Host smart-086611f0-91f2-4911-a267-748d7d388352
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1148004879 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.1148004879
Directory /workspace/49.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.2367978715
Short name T185
Test name
Test status
Simulation time 1258430000 ps
CPU time 4.05 seconds
Started Aug 19 04:23:12 PM PDT 24
Finished Aug 19 04:23:21 PM PDT 24
Peak memory 164684 kb
Host smart-d14d310d-c83f-4e63-8497-b1b187618385
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2367978715 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.2367978715
Directory /workspace/5.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.1719839463
Short name T194
Test name
Test status
Simulation time 1118870000 ps
CPU time 3.44 seconds
Started Aug 19 04:23:06 PM PDT 24
Finished Aug 19 04:23:14 PM PDT 24
Peak memory 164096 kb
Host smart-8e877ac2-3bf8-489a-804a-752fd9dd3e7d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1719839463 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.1719839463
Directory /workspace/6.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.2358603273
Short name T155
Test name
Test status
Simulation time 1380510000 ps
CPU time 4.03 seconds
Started Aug 19 04:19:54 PM PDT 24
Finished Aug 19 04:20:02 PM PDT 24
Peak memory 164868 kb
Host smart-cbd2cae6-8fdd-404a-9e70-a3e760784017
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2358603273 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.2358603273
Directory /workspace/7.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1372598556
Short name T199
Test name
Test status
Simulation time 1443910000 ps
CPU time 3.23 seconds
Started Aug 19 04:22:59 PM PDT 24
Finished Aug 19 04:23:07 PM PDT 24
Peak memory 164324 kb
Host smart-761b82d5-d188-447d-a289-b0dfbd5a2e2d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1372598556 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.1372598556
Directory /workspace/8.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2270359252
Short name T173
Test name
Test status
Simulation time 1634030000 ps
CPU time 4.36 seconds
Started Aug 19 04:20:08 PM PDT 24
Finished Aug 19 04:20:18 PM PDT 24
Peak memory 163804 kb
Host smart-4f175a7a-4b3f-476a-89b0-007a4b7744ec
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2270359252 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.2270359252
Directory /workspace/9.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.2350218957
Short name T70
Test name
Test status
Simulation time 1333670000 ps
CPU time 3.66 seconds
Started Aug 19 04:22:58 PM PDT 24
Finished Aug 19 04:23:06 PM PDT 24
Peak memory 164324 kb
Host smart-1c433593-570b-45a8-b3f8-c50eee004f7c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2350218957 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.2350218957
Directory /workspace/0.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.4255039161
Short name T68
Test name
Test status
Simulation time 1486770000 ps
CPU time 3.88 seconds
Started Aug 19 04:22:59 PM PDT 24
Finished Aug 19 04:23:07 PM PDT 24
Peak memory 164192 kb
Host smart-9f3354d4-5e15-4202-8b5c-12b1576b4486
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4255039161 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.4255039161
Directory /workspace/1.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.81803029
Short name T51
Test name
Test status
Simulation time 1484910000 ps
CPU time 5.19 seconds
Started Aug 19 04:18:15 PM PDT 24
Finished Aug 19 04:18:26 PM PDT 24
Peak memory 163908 kb
Host smart-0a47c368-29c2-43fc-97e3-b82811ddfa17
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=81803029 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.81803029
Directory /workspace/11.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.565613155
Short name T3
Test name
Test status
Simulation time 1529990000 ps
CPU time 5.64 seconds
Started Aug 19 04:18:15 PM PDT 24
Finished Aug 19 04:18:28 PM PDT 24
Peak memory 164348 kb
Host smart-b50b4224-0acb-4ffb-bde1-c5b265a2dc53
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=565613155 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.565613155
Directory /workspace/12.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.77657439
Short name T58
Test name
Test status
Simulation time 1631490000 ps
CPU time 5.58 seconds
Started Aug 19 04:18:15 PM PDT 24
Finished Aug 19 04:18:28 PM PDT 24
Peak memory 164300 kb
Host smart-46d484ad-c9bf-4e75-b4c4-5da93b0ef8bd
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=77657439 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.77657439
Directory /workspace/13.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.2591997879
Short name T53
Test name
Test status
Simulation time 1446830000 ps
CPU time 4.28 seconds
Started Aug 19 04:18:20 PM PDT 24
Finished Aug 19 04:18:29 PM PDT 24
Peak memory 164924 kb
Host smart-7fbf411d-928e-48f8-aadb-dd6ff8635e84
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2591997879 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.2591997879
Directory /workspace/14.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.3648935995
Short name T44
Test name
Test status
Simulation time 1469970000 ps
CPU time 4.15 seconds
Started Aug 19 04:18:05 PM PDT 24
Finished Aug 19 04:18:14 PM PDT 24
Peak memory 163808 kb
Host smart-77fd322f-c2d5-4700-959c-090165462b07
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3648935995 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.3648935995
Directory /workspace/15.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.605372593
Short name T66
Test name
Test status
Simulation time 1368290000 ps
CPU time 5.11 seconds
Started Aug 19 04:18:14 PM PDT 24
Finished Aug 19 04:18:26 PM PDT 24
Peak memory 162992 kb
Host smart-316f1df8-b244-4ddd-9bd3-f2379c9426f7
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=605372593 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.605372593
Directory /workspace/16.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.855611419
Short name T41
Test name
Test status
Simulation time 1371270000 ps
CPU time 4.53 seconds
Started Aug 19 04:18:15 PM PDT 24
Finished Aug 19 04:18:25 PM PDT 24
Peak memory 164948 kb
Host smart-817592f3-7c95-431f-a4d8-fe65ca50a2ca
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=855611419 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.855611419
Directory /workspace/17.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.3564824162
Short name T65
Test name
Test status
Simulation time 1538290000 ps
CPU time 5.67 seconds
Started Aug 19 04:21:08 PM PDT 24
Finished Aug 19 04:21:21 PM PDT 24
Peak memory 164740 kb
Host smart-68f79f8f-2174-4af9-bf59-98f002a08393
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3564824162 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.3564824162
Directory /workspace/18.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.2984045021
Short name T64
Test name
Test status
Simulation time 1470830000 ps
CPU time 3.8 seconds
Started Aug 19 04:20:50 PM PDT 24
Finished Aug 19 04:20:58 PM PDT 24
Peak memory 164772 kb
Host smart-7f3d27bb-b4d1-44e3-a155-8a6da0d21ab1
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2984045021 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.2984045021
Directory /workspace/19.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.3157339251
Short name T39
Test name
Test status
Simulation time 1437610000 ps
CPU time 4.36 seconds
Started Aug 19 04:23:34 PM PDT 24
Finished Aug 19 04:23:44 PM PDT 24
Peak memory 164536 kb
Host smart-81b4f072-6599-4d6b-8c68-3df9b6822c55
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3157339251 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.3157339251
Directory /workspace/2.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.2246660392
Short name T11
Test name
Test status
Simulation time 1475930000 ps
CPU time 4.21 seconds
Started Aug 19 04:19:15 PM PDT 24
Finished Aug 19 04:19:24 PM PDT 24
Peak memory 163164 kb
Host smart-effd69dd-3b1b-42db-a124-5f0d1a15bfb4
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2246660392 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.2246660392
Directory /workspace/20.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.1006826184
Short name T47
Test name
Test status
Simulation time 1332530000 ps
CPU time 3.02 seconds
Started Aug 19 04:20:53 PM PDT 24
Finished Aug 19 04:21:00 PM PDT 24
Peak memory 164668 kb
Host smart-27716251-9fc8-49be-824b-6bb66503eca5
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1006826184 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.1006826184
Directory /workspace/21.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.3790148158
Short name T57
Test name
Test status
Simulation time 1599370000 ps
CPU time 4.39 seconds
Started Aug 19 04:22:58 PM PDT 24
Finished Aug 19 04:23:08 PM PDT 24
Peak memory 164716 kb
Host smart-40a9111e-6fdb-43e9-ae9b-85053f11e5e9
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3790148158 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.3790148158
Directory /workspace/22.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.86257081
Short name T32
Test name
Test status
Simulation time 1330510000 ps
CPU time 3.8 seconds
Started Aug 19 04:23:00 PM PDT 24
Finished Aug 19 04:23:08 PM PDT 24
Peak memory 164656 kb
Host smart-0f501eff-8098-4a67-a49e-00036e473e4b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=86257081 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.86257081
Directory /workspace/23.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.597897036
Short name T38
Test name
Test status
Simulation time 1401550000 ps
CPU time 3.48 seconds
Started Aug 19 04:22:44 PM PDT 24
Finished Aug 19 04:22:52 PM PDT 24
Peak memory 164648 kb
Host smart-ec80e5df-2135-4641-bea1-57b26452f025
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=597897036 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.597897036
Directory /workspace/24.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.2730988565
Short name T55
Test name
Test status
Simulation time 1571090000 ps
CPU time 3.65 seconds
Started Aug 19 04:22:43 PM PDT 24
Finished Aug 19 04:22:52 PM PDT 24
Peak memory 162988 kb
Host smart-fb0a9158-f622-4dd5-8643-71762d008bbe
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2730988565 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.2730988565
Directory /workspace/25.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.454705966
Short name T45
Test name
Test status
Simulation time 1422870000 ps
CPU time 4.05 seconds
Started Aug 19 04:19:16 PM PDT 24
Finished Aug 19 04:19:25 PM PDT 24
Peak memory 163448 kb
Host smart-2b4722cd-34d1-4e70-9c17-ec46096570cb
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=454705966 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.454705966
Directory /workspace/26.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.3055245235
Short name T2
Test name
Test status
Simulation time 1453850000 ps
CPU time 3.92 seconds
Started Aug 19 04:19:17 PM PDT 24
Finished Aug 19 04:19:26 PM PDT 24
Peak memory 164284 kb
Host smart-3dc2b578-4613-49e6-86f8-3eefa3f17453
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3055245235 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.3055245235
Directory /workspace/27.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.2772134794
Short name T67
Test name
Test status
Simulation time 1439470000 ps
CPU time 4.12 seconds
Started Aug 19 04:20:04 PM PDT 24
Finished Aug 19 04:20:13 PM PDT 24
Peak memory 164668 kb
Host smart-d7f2bf30-71a4-41ed-a4e7-b5bbbbe04696
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2772134794 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.2772134794
Directory /workspace/28.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.2676291912
Short name T63
Test name
Test status
Simulation time 1620390000 ps
CPU time 3.17 seconds
Started Aug 19 04:23:44 PM PDT 24
Finished Aug 19 04:23:51 PM PDT 24
Peak memory 164392 kb
Host smart-9644e5df-cfc8-4df8-869d-ff0b0d1b94ce
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2676291912 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.2676291912
Directory /workspace/29.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.1435797521
Short name T50
Test name
Test status
Simulation time 1503250000 ps
CPU time 3.51 seconds
Started Aug 19 04:23:10 PM PDT 24
Finished Aug 19 04:23:18 PM PDT 24
Peak memory 164548 kb
Host smart-61310b29-8e99-4c9e-9c9f-e12b41b6a4e7
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1435797521 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.1435797521
Directory /workspace/3.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.2125478139
Short name T12
Test name
Test status
Simulation time 1457650000 ps
CPU time 3.83 seconds
Started Aug 19 04:22:57 PM PDT 24
Finished Aug 19 04:23:05 PM PDT 24
Peak memory 164376 kb
Host smart-81099366-43ba-4b31-9bd7-e2f1663288f2
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2125478139 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.2125478139
Directory /workspace/30.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.2071882312
Short name T33
Test name
Test status
Simulation time 1351250000 ps
CPU time 3.39 seconds
Started Aug 19 04:22:56 PM PDT 24
Finished Aug 19 04:23:04 PM PDT 24
Peak memory 163904 kb
Host smart-9f2c4539-ce7f-4439-82d7-dbba88eaac7f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2071882312 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.2071882312
Directory /workspace/31.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.1071374057
Short name T31
Test name
Test status
Simulation time 1493990000 ps
CPU time 4.83 seconds
Started Aug 19 04:19:36 PM PDT 24
Finished Aug 19 04:19:47 PM PDT 24
Peak memory 164748 kb
Host smart-d998796d-afca-45c4-bebe-618905713276
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1071374057 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.1071374057
Directory /workspace/32.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.1660618333
Short name T34
Test name
Test status
Simulation time 1354690000 ps
CPU time 4.2 seconds
Started Aug 19 04:22:57 PM PDT 24
Finished Aug 19 04:23:06 PM PDT 24
Peak memory 162896 kb
Host smart-7d1908a5-d6e3-43bf-b82c-b10896a0cf24
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1660618333 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.1660618333
Directory /workspace/33.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.675139981
Short name T52
Test name
Test status
Simulation time 1451510000 ps
CPU time 4.43 seconds
Started Aug 19 04:20:02 PM PDT 24
Finished Aug 19 04:20:11 PM PDT 24
Peak memory 164716 kb
Host smart-800155b2-350b-4a46-b6b4-df0c8254b39e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=675139981 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.675139981
Directory /workspace/34.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.174461118
Short name T40
Test name
Test status
Simulation time 1322270000 ps
CPU time 3.91 seconds
Started Aug 19 04:21:40 PM PDT 24
Finished Aug 19 04:21:48 PM PDT 24
Peak memory 164660 kb
Host smart-f6c8305d-d023-41e1-bfb9-c1fa8faeb239
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=174461118 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.174461118
Directory /workspace/35.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.3569368787
Short name T62
Test name
Test status
Simulation time 1548450000 ps
CPU time 3.67 seconds
Started Aug 19 04:23:06 PM PDT 24
Finished Aug 19 04:23:15 PM PDT 24
Peak memory 164244 kb
Host smart-71992a33-fad2-461a-925b-9a391f326dd8
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3569368787 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.3569368787
Directory /workspace/36.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.3682604744
Short name T43
Test name
Test status
Simulation time 1442650000 ps
CPU time 4.1 seconds
Started Aug 19 04:20:51 PM PDT 24
Finished Aug 19 04:21:00 PM PDT 24
Peak memory 164932 kb
Host smart-485aa7be-5f4e-4884-bb56-c7efa26c88fd
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3682604744 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.3682604744
Directory /workspace/37.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.510027588
Short name T42
Test name
Test status
Simulation time 1461270000 ps
CPU time 4.64 seconds
Started Aug 19 04:21:03 PM PDT 24
Finished Aug 19 04:21:13 PM PDT 24
Peak memory 164716 kb
Host smart-b65acc85-3709-47dd-a14e-60d0c40a1ab9
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=510027588 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.510027588
Directory /workspace/38.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.2323806359
Short name T35
Test name
Test status
Simulation time 1603350000 ps
CPU time 3.8 seconds
Started Aug 19 04:23:20 PM PDT 24
Finished Aug 19 04:23:28 PM PDT 24
Peak memory 164592 kb
Host smart-a022ada5-a278-4deb-ad7a-59d5cf220923
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2323806359 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.2323806359
Directory /workspace/39.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.3984507514
Short name T61
Test name
Test status
Simulation time 1498990000 ps
CPU time 2.99 seconds
Started Aug 19 04:23:15 PM PDT 24
Finished Aug 19 04:23:22 PM PDT 24
Peak memory 164396 kb
Host smart-4955a4f5-cc8d-4cf2-a769-112d7ec8dc28
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3984507514 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.3984507514
Directory /workspace/4.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.614212165
Short name T49
Test name
Test status
Simulation time 1440690000 ps
CPU time 4.28 seconds
Started Aug 19 04:23:13 PM PDT 24
Finished Aug 19 04:23:22 PM PDT 24
Peak memory 164476 kb
Host smart-61eb7b4a-e72a-47e0-8ab6-746c11ef0d2e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=614212165 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.614212165
Directory /workspace/40.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.131070279
Short name T60
Test name
Test status
Simulation time 1426990000 ps
CPU time 4.3 seconds
Started Aug 19 04:23:12 PM PDT 24
Finished Aug 19 04:23:22 PM PDT 24
Peak memory 164448 kb
Host smart-f8a9dd55-fca1-4c78-a83a-4a7b4b9e3b7e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=131070279 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.131070279
Directory /workspace/41.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.10188442
Short name T46
Test name
Test status
Simulation time 1513810000 ps
CPU time 3.77 seconds
Started Aug 19 04:22:58 PM PDT 24
Finished Aug 19 04:23:06 PM PDT 24
Peak memory 163088 kb
Host smart-c9f8cc9a-05c4-4cee-b6fb-34d72cc58265
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=10188442 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.10188442
Directory /workspace/42.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.851952365
Short name T1
Test name
Test status
Simulation time 1394010000 ps
CPU time 3.87 seconds
Started Aug 19 04:23:38 PM PDT 24
Finished Aug 19 04:23:47 PM PDT 24
Peak memory 163688 kb
Host smart-a8c63084-3f5b-4420-bb3b-a1d6a61b7944
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=851952365 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.851952365
Directory /workspace/43.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.4113288677
Short name T36
Test name
Test status
Simulation time 1527330000 ps
CPU time 4.87 seconds
Started Aug 19 04:23:14 PM PDT 24
Finished Aug 19 04:23:25 PM PDT 24
Peak memory 164424 kb
Host smart-1b50ee67-63a0-4bdd-9a45-7ef47cbb3455
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4113288677 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.4113288677
Directory /workspace/44.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.805874000
Short name T54
Test name
Test status
Simulation time 1541810000 ps
CPU time 4.71 seconds
Started Aug 19 04:20:24 PM PDT 24
Finished Aug 19 04:20:34 PM PDT 24
Peak memory 164692 kb
Host smart-c862c577-ddcb-4d29-a23b-b3ef13f9b4ee
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=805874000 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.805874000
Directory /workspace/45.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.1214462579
Short name T9
Test name
Test status
Simulation time 1440430000 ps
CPU time 4.47 seconds
Started Aug 19 04:23:14 PM PDT 24
Finished Aug 19 04:23:24 PM PDT 24
Peak memory 164424 kb
Host smart-641f6be3-049c-4542-ae4d-8378c06ee0a7
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1214462579 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.1214462579
Directory /workspace/46.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.2812302846
Short name T8
Test name
Test status
Simulation time 1496850000 ps
CPU time 4.11 seconds
Started Aug 19 04:23:38 PM PDT 24
Finished Aug 19 04:23:47 PM PDT 24
Peak memory 163204 kb
Host smart-a5426767-3d9f-4416-8034-790a3e01efb2
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2812302846 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.2812302846
Directory /workspace/47.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.17220291
Short name T56
Test name
Test status
Simulation time 1559510000 ps
CPU time 4.06 seconds
Started Aug 19 04:23:38 PM PDT 24
Finished Aug 19 04:23:48 PM PDT 24
Peak memory 163252 kb
Host smart-805c7398-39c0-4eab-b211-ea79c80f0c6a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=17220291 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.17220291
Directory /workspace/48.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.3428154273
Short name T69
Test name
Test status
Simulation time 1338970000 ps
CPU time 3.63 seconds
Started Aug 19 04:22:59 PM PDT 24
Finished Aug 19 04:23:06 PM PDT 24
Peak memory 165648 kb
Host smart-6af92e6d-9408-44b9-90a0-81d3ec25e9aa
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3428154273 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.3428154273
Directory /workspace/49.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.372738403
Short name T48
Test name
Test status
Simulation time 1560010000 ps
CPU time 4.1 seconds
Started Aug 19 04:22:57 PM PDT 24
Finished Aug 19 04:23:06 PM PDT 24
Peak memory 163068 kb
Host smart-47d42438-3f35-4852-9422-ea019f3084a9
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=372738403 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.372738403
Directory /workspace/5.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.1260333058
Short name T13
Test name
Test status
Simulation time 1482590000 ps
CPU time 2.98 seconds
Started Aug 19 04:24:31 PM PDT 24
Finished Aug 19 04:24:38 PM PDT 24
Peak memory 164312 kb
Host smart-0858aac5-4788-4457-ab18-8c01922d10d6
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1260333058 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.1260333058
Directory /workspace/6.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.3182280484
Short name T59
Test name
Test status
Simulation time 1489630000 ps
CPU time 4.38 seconds
Started Aug 19 04:23:50 PM PDT 24
Finished Aug 19 04:24:00 PM PDT 24
Peak memory 163844 kb
Host smart-2a9651cf-52d4-4f96-9dab-0ab351bda32d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3182280484 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.3182280484
Directory /workspace/7.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.791472356
Short name T37
Test name
Test status
Simulation time 1565270000 ps
CPU time 4.44 seconds
Started Aug 19 04:23:50 PM PDT 24
Finished Aug 19 04:24:00 PM PDT 24
Peak memory 164820 kb
Host smart-8ff1a47a-01b3-4fe6-a8c0-30aa3efd989c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=791472356 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.791472356
Directory /workspace/8.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.1784318519
Short name T4
Test name
Test status
Simulation time 1474830000 ps
CPU time 4.19 seconds
Started Aug 19 04:20:05 PM PDT 24
Finished Aug 19 04:20:15 PM PDT 24
Peak memory 164764 kb
Host smart-9752ea63-ad8b-490a-ac86-c5c6ff366e20
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1784318519 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.1784318519
Directory /workspace/9.prim_lfsr_gal_smoke/latest
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