Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.31 100.00 96.55 100.00 100.00 95.00


Total tests in report: 200
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
87.31 87.31 100.00 100.00 96.55 96.55 100.00 100.00 100.00 100.00 40.00 40.00 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.117395397
96.81 9.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 87.50 47.50 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.1873995600
98.31 1.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 95.00 7.50 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.1377575811

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.1880546652
/workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.2656325593
/workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.863966551
/workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.925515819
/workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.3576979302
/workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.3723081144
/workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.1817587748
/workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.2456869145
/workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.2766648864
/workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.3526182027
/workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2379314935
/workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.1980290650
/workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.1944287486
/workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.3613684612
/workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.1952615802
/workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.3941967132
/workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.3397351792
/workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.3652861418
/workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.189054010
/workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.3082799997
/workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.1582330944
/workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.2709049384
/workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.3456348283
/workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3526475397
/workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.1619158711
/workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.2581433865
/workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.2867802828
/workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.985534207
/workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.2038434057
/workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.3768444120
/workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.212885128
/workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.2493888611
/workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.3365550261
/workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.4287985619
/workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.1378411208
/workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.680578105
/workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.2172596546
/workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.1356218523
/workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.4025995239
/workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.259943046
/workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.982917898
/workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.1594954569
/workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.577683070
/workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.2073548436
/workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.2782151910
/workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.316613169
/workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.2175555801
/workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.368391642
/workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.3596321198
/workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.198575860
/workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.2960703883
/workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.3578996653
/workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.3542711191
/workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.657001827
/workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.1707663524
/workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.3796195314
/workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.1565506326
/workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.605571
/workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.2764029590
/workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.1571334282
/workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.2563583555
/workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.1743309053
/workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.2226597855
/workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.2943573390
/workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.3549007750
/workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.1401170779
/workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.515180072
/workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.2396967493
/workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.2499085749
/workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.2402006224
/workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.4257926012
/workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.2117873945
/workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.296483878
/workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.744210509
/workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.2966718941
/workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.1021316361
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/workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.2471230279
/workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.1949377197
/workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.1153960429
/workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.754722109
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/workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.129911151
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/workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.1550476362
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Total test records in report: 200
tests.html | tests1.html | tests2.html | tests3.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.2412252236 Aug 23 05:51:04 PM UTC 24 Aug 23 05:51:14 PM UTC 24 1352830000 ps
T2 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.117395397 Aug 23 05:51:04 PM UTC 24 Aug 23 05:51:15 PM UTC 24 1452370000 ps
T3 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.1755710901 Aug 23 05:51:06 PM UTC 24 Aug 23 05:51:15 PM UTC 24 1347670000 ps
T4 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.3837057809 Aug 23 05:51:06 PM UTC 24 Aug 23 05:51:15 PM UTC 24 1381590000 ps
T8 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.514741202 Aug 23 05:51:05 PM UTC 24 Aug 23 05:51:16 PM UTC 24 1449390000 ps
T9 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.3549600110 Aug 23 05:51:06 PM UTC 24 Aug 23 05:51:16 PM UTC 24 1440770000 ps
T10 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.2443539274 Aug 23 05:51:06 PM UTC 24 Aug 23 05:51:16 PM UTC 24 1480910000 ps
T11 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.4089246811 Aug 23 05:51:06 PM UTC 24 Aug 23 05:51:16 PM UTC 24 1463650000 ps
T12 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.2281931559 Aug 23 05:51:05 PM UTC 24 Aug 23 05:51:16 PM UTC 24 1517830000 ps
T13 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.3738484435 Aug 23 05:51:06 PM UTC 24 Aug 23 05:51:16 PM UTC 24 1542010000 ps
T31 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.2356880202 Aug 23 05:51:06 PM UTC 24 Aug 23 05:51:17 PM UTC 24 1585350000 ps
T32 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.2144473911 Aug 23 05:51:07 PM UTC 24 Aug 23 05:51:17 PM UTC 24 1213550000 ps
T33 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.2605389508 Aug 23 05:51:06 PM UTC 24 Aug 23 05:51:17 PM UTC 24 1635530000 ps
T34 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.397518662 Aug 23 05:51:07 PM UTC 24 Aug 23 05:51:17 PM UTC 24 1289970000 ps
T35 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.4168252481 Aug 23 05:51:07 PM UTC 24 Aug 23 05:51:18 PM UTC 24 1396370000 ps
T36 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.1266447744 Aug 23 05:51:07 PM UTC 24 Aug 23 05:51:18 PM UTC 24 1489970000 ps
T37 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.1710057105 Aug 23 05:51:07 PM UTC 24 Aug 23 05:51:18 PM UTC 24 1547330000 ps
T38 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.3956850772 Aug 23 05:51:07 PM UTC 24 Aug 23 05:51:19 PM UTC 24 1559550000 ps
T39 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.3152471891 Aug 23 05:51:07 PM UTC 24 Aug 23 05:51:19 PM UTC 24 1617230000 ps
T40 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.746668876 Aug 23 05:51:07 PM UTC 24 Aug 23 05:51:20 PM UTC 24 1478910000 ps
T41 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.1534630588 Aug 23 05:51:15 PM UTC 24 Aug 23 05:51:25 PM UTC 24 1443290000 ps
T42 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.469700525 Aug 23 05:51:15 PM UTC 24 Aug 23 05:51:26 PM UTC 24 1532790000 ps
T43 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.1331160157 Aug 23 05:51:16 PM UTC 24 Aug 23 05:51:26 PM UTC 24 1361250000 ps
T44 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.4012902956 Aug 23 05:51:16 PM UTC 24 Aug 23 05:51:26 PM UTC 24 1392710000 ps
T45 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.4173454475 Aug 23 05:51:16 PM UTC 24 Aug 23 05:51:26 PM UTC 24 1378130000 ps
T46 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.1178884796 Aug 23 05:51:16 PM UTC 24 Aug 23 05:51:26 PM UTC 24 1403290000 ps
T47 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.2206563954 Aug 23 05:51:16 PM UTC 24 Aug 23 05:51:26 PM UTC 24 1422010000 ps
T48 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.2063155417 Aug 23 05:51:17 PM UTC 24 Aug 23 05:51:26 PM UTC 24 1255270000 ps
T49 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.830644662 Aug 23 05:51:17 PM UTC 24 Aug 23 05:51:27 PM UTC 24 1364870000 ps
T50 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.2487821589 Aug 23 05:51:19 PM UTC 24 Aug 23 05:51:27 PM UTC 24 1199910000 ps
T51 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.2701714459 Aug 23 05:51:17 PM UTC 24 Aug 23 05:51:27 PM UTC 24 1418710000 ps
T52 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.3897161424 Aug 23 05:51:17 PM UTC 24 Aug 23 05:51:28 PM UTC 24 1465270000 ps
T53 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.3576883491 Aug 23 05:51:19 PM UTC 24 Aug 23 05:51:28 PM UTC 24 1329790000 ps
T54 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.3875546754 Aug 23 05:51:20 PM UTC 24 Aug 23 05:51:28 PM UTC 24 1193130000 ps
T55 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.219039820 Aug 23 05:51:17 PM UTC 24 Aug 23 05:51:28 PM UTC 24 1594130000 ps
T56 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.22868772 Aug 23 05:51:19 PM UTC 24 Aug 23 05:51:29 PM UTC 24 1439070000 ps
T57 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.3460915468 Aug 23 05:51:19 PM UTC 24 Aug 23 05:51:29 PM UTC 24 1570210000 ps
T58 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.2529069576 Aug 23 05:51:20 PM UTC 24 Aug 23 05:51:30 PM UTC 24 1479170000 ps
T59 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.4255055348 Aug 23 05:51:20 PM UTC 24 Aug 23 05:51:30 PM UTC 24 1512870000 ps
T60 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.3231904998 Aug 23 05:51:21 PM UTC 24 Aug 23 05:51:30 PM UTC 24 1408090000 ps
T61 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.3952563866 Aug 23 05:51:26 PM UTC 24 Aug 23 05:51:35 PM UTC 24 1462730000 ps
T62 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.1683179402 Aug 23 05:51:27 PM UTC 24 Aug 23 05:51:36 PM UTC 24 1304590000 ps
T63 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.3431431204 Aug 23 05:51:27 PM UTC 24 Aug 23 05:51:36 PM UTC 24 1390010000 ps
T64 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.2376252778 Aug 23 05:51:27 PM UTC 24 Aug 23 05:51:37 PM UTC 24 1498130000 ps
T65 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.1984466313 Aug 23 05:51:27 PM UTC 24 Aug 23 05:51:37 PM UTC 24 1506690000 ps
T66 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.3752454133 Aug 23 05:51:27 PM UTC 24 Aug 23 05:51:37 PM UTC 24 1583010000 ps
T67 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.3918953683 Aug 23 05:51:27 PM UTC 24 Aug 23 05:51:37 PM UTC 24 1585230000 ps
T68 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.2831632754 Aug 23 05:51:27 PM UTC 24 Aug 23 05:51:37 PM UTC 24 1627730000 ps
T69 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.3682474740 Aug 23 05:51:28 PM UTC 24 Aug 23 05:51:37 PM UTC 24 1452470000 ps
T70 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.3807599932 Aug 23 05:51:28 PM UTC 24 Aug 23 05:51:38 PM UTC 24 1539450000 ps
T5 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.2782151910 Aug 23 05:52:22 PM UTC 24 Aug 23 06:27:24 PM UTC 24 336396710000 ps
T6 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.1873995600 Aug 23 05:52:22 PM UTC 24 Aug 23 06:27:25 PM UTC 24 336612810000 ps
T7 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.925515819 Aug 23 05:52:24 PM UTC 24 Aug 23 06:27:25 PM UTC 24 336425990000 ps
T14 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.368391642 Aug 23 05:52:24 PM UTC 24 Aug 23 06:27:26 PM UTC 24 336454690000 ps
T15 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.1980290650 Aug 23 05:52:22 PM UTC 24 Aug 23 06:27:26 PM UTC 24 336697250000 ps
T16 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.2656325593 Aug 23 05:52:24 PM UTC 24 Aug 23 06:27:26 PM UTC 24 336477270000 ps
T17 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.3456348283 Aug 23 05:52:22 PM UTC 24 Aug 23 06:27:26 PM UTC 24 336749370000 ps
T18 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.4287985619 Aug 23 05:52:22 PM UTC 24 Aug 23 06:27:26 PM UTC 24 336609690000 ps
T19 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.2175555801 Aug 23 05:52:23 PM UTC 24 Aug 23 06:27:26 PM UTC 24 336704750000 ps
T20 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.3723081144 Aug 23 05:52:24 PM UTC 24 Aug 23 06:27:26 PM UTC 24 336384510000 ps
T71 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.1817587748 Aug 23 05:52:24 PM UTC 24 Aug 23 06:27:26 PM UTC 24 336483450000 ps
T72 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.3576979302 Aug 23 05:52:24 PM UTC 24 Aug 23 06:27:26 PM UTC 24 336549250000 ps
T73 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.863966551 Aug 23 05:52:24 PM UTC 24 Aug 23 06:27:26 PM UTC 24 336572990000 ps
T74 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.3596321198 Aug 23 05:52:24 PM UTC 24 Aug 23 06:27:26 PM UTC 24 336664530000 ps
T75 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.3526182027 Aug 23 05:52:25 PM UTC 24 Aug 23 06:27:26 PM UTC 24 336426490000 ps
T76 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.2456869145 Aug 23 05:52:25 PM UTC 24 Aug 23 06:27:27 PM UTC 24 336438450000 ps
T77 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.316613169 Aug 23 05:52:23 PM UTC 24 Aug 23 06:27:27 PM UTC 24 336941590000 ps
T78 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.2766648864 Aug 23 05:52:25 PM UTC 24 Aug 23 06:27:27 PM UTC 24 336472370000 ps
T79 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.1880546652 Aug 23 05:52:22 PM UTC 24 Aug 23 06:27:28 PM UTC 24 337028150000 ps
T80 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2379314935 Aug 23 05:52:28 PM UTC 24 Aug 23 06:27:31 PM UTC 24 337046090000 ps
T81 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.1944287486 Aug 23 06:27:25 PM UTC 24 Aug 23 07:02:30 PM UTC 24 336446030000 ps
T82 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.2867802828 Aug 23 06:27:27 PM UTC 24 Aug 23 07:02:32 PM UTC 24 336361310000 ps
T83 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.3652861418 Aug 23 06:27:27 PM UTC 24 Aug 23 07:02:33 PM UTC 24 336444170000 ps
T84 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.2581433865 Aug 23 06:27:27 PM UTC 24 Aug 23 07:02:33 PM UTC 24 336393190000 ps
T85 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.189054010 Aug 23 06:27:27 PM UTC 24 Aug 23 07:02:33 PM UTC 24 336505270000 ps
T86 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.3613684612 Aug 23 06:27:26 PM UTC 24 Aug 23 07:02:34 PM UTC 24 336923390000 ps
T87 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3526475397 Aug 23 06:27:27 PM UTC 24 Aug 23 07:02:34 PM UTC 24 336588470000 ps
T88 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.985534207 Aug 23 06:27:27 PM UTC 24 Aug 23 07:02:34 PM UTC 24 336616870000 ps
T89 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.1619158711 Aug 23 06:27:27 PM UTC 24 Aug 23 07:02:35 PM UTC 24 336640790000 ps
T90 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.1952615802 Aug 23 06:27:26 PM UTC 24 Aug 23 07:02:35 PM UTC 24 336944130000 ps
T91 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.1582330944 Aug 23 06:27:27 PM UTC 24 Aug 23 07:02:35 PM UTC 24 336821910000 ps
T92 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.3082799997 Aug 23 06:27:27 PM UTC 24 Aug 23 07:02:35 PM UTC 24 336843670000 ps
T93 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.2493888611 Aug 23 06:27:28 PM UTC 24 Aug 23 07:02:35 PM UTC 24 336657570000 ps
T94 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.3768444120 Aug 23 06:27:28 PM UTC 24 Aug 23 07:02:35 PM UTC 24 336726770000 ps
T95 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.2709049384 Aug 23 06:27:27 PM UTC 24 Aug 23 07:02:35 PM UTC 24 337145290000 ps
T96 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.3397351792 Aug 23 06:27:27 PM UTC 24 Aug 23 07:02:36 PM UTC 24 337047330000 ps
T97 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.212885128 Aug 23 06:27:28 PM UTC 24 Aug 23 07:02:36 PM UTC 24 336882250000 ps
T98 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.3941967132 Aug 23 06:27:27 PM UTC 24 Aug 23 07:02:36 PM UTC 24 337106330000 ps
T99 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.2038434057 Aug 23 06:27:28 PM UTC 24 Aug 23 07:02:36 PM UTC 24 337005150000 ps
T100 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.3365550261 Aug 23 06:27:32 PM UTC 24 Aug 23 07:02:38 PM UTC 24 336738510000 ps
T101 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.1378411208 Aug 23 07:02:31 PM UTC 24 Aug 23 07:34:26 PM UTC 24 336979590000 ps
T102 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.982917898 Aug 23 07:02:35 PM UTC 24 Aug 23 07:34:27 PM UTC 24 336487070000 ps
T103 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.680578105 Aug 23 07:02:33 PM UTC 24 Aug 23 07:34:27 PM UTC 24 336890370000 ps
T104 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.4025995239 Aug 23 07:02:34 PM UTC 24 Aug 23 07:34:27 PM UTC 24 336674650000 ps
T105 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.1594954569 Aug 23 07:02:35 PM UTC 24 Aug 23 07:34:28 PM UTC 24 336577150000 ps
T106 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.1356218523 Aug 23 07:02:34 PM UTC 24 Aug 23 07:34:28 PM UTC 24 336787650000 ps
T107 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.2172596546 Aug 23 07:02:34 PM UTC 24 Aug 23 07:34:28 PM UTC 24 336883550000 ps
T108 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.2073548436 Aug 23 07:02:36 PM UTC 24 Aug 23 07:34:28 PM UTC 24 336595750000 ps
T109 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.259943046 Aug 23 07:02:35 PM UTC 24 Aug 23 07:34:29 PM UTC 24 336844110000 ps
T110 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.577683070 Aug 23 07:02:35 PM UTC 24 Aug 23 07:34:29 PM UTC 24 336778010000 ps
T111 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.3284863112 Aug 23 07:34:04 PM UTC 24 Aug 23 07:34:14 PM UTC 24 1305890000 ps
T112 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.2321943660 Aug 23 07:34:04 PM UTC 24 Aug 23 07:34:14 PM UTC 24 1335270000 ps
T113 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.1324857029 Aug 23 07:34:04 PM UTC 24 Aug 23 07:34:14 PM UTC 24 1425290000 ps
T114 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.4248650861 Aug 23 07:34:04 PM UTC 24 Aug 23 07:34:15 PM UTC 24 1447730000 ps
T115 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.3219842069 Aug 23 07:34:04 PM UTC 24 Aug 23 07:34:15 PM UTC 24 1451970000 ps
T116 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.4191681035 Aug 23 07:34:04 PM UTC 24 Aug 23 07:34:15 PM UTC 24 1532270000 ps
T117 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.1766497149 Aug 23 07:34:05 PM UTC 24 Aug 23 07:34:16 PM UTC 24 1454490000 ps
T118 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.3888720299 Aug 23 07:34:06 PM UTC 24 Aug 23 07:34:16 PM UTC 24 1403330000 ps
T119 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.515900397 Aug 23 07:34:06 PM UTC 24 Aug 23 07:34:17 PM UTC 24 1511710000 ps
T120 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.517659806 Aug 23 07:34:14 PM UTC 24 Aug 23 07:34:25 PM UTC 24 1437890000 ps
T121 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.1017244961 Aug 23 07:34:16 PM UTC 24 Aug 23 07:34:26 PM UTC 24 1270710000 ps
T122 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.2044964296 Aug 23 07:34:15 PM UTC 24 Aug 23 07:34:26 PM UTC 24 1455490000 ps
T123 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.1755871780 Aug 23 07:34:15 PM UTC 24 Aug 23 07:34:26 PM UTC 24 1473310000 ps
T124 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.3169260790 Aug 23 07:34:15 PM UTC 24 Aug 23 07:34:26 PM UTC 24 1496550000 ps
T125 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.1383104571 Aug 23 07:34:15 PM UTC 24 Aug 23 07:34:26 PM UTC 24 1531990000 ps
T126 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.3485495469 Aug 23 07:34:16 PM UTC 24 Aug 23 07:34:27 PM UTC 24 1565210000 ps
T127 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.4163378905 Aug 23 07:34:17 PM UTC 24 Aug 23 07:34:28 PM UTC 24 1496610000 ps
T128 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.866457392 Aug 23 07:34:17 PM UTC 24 Aug 23 07:34:28 PM UTC 24 1516270000 ps
T129 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.1558188372 Aug 23 07:34:25 PM UTC 24 Aug 23 07:34:34 PM UTC 24 1403870000 ps
T130 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.3624102832 Aug 23 07:34:26 PM UTC 24 Aug 23 07:34:36 PM UTC 24 1514750000 ps
T131 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.4000808039 Aug 23 07:34:27 PM UTC 24 Aug 23 07:34:36 PM UTC 24 1319230000 ps
T132 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.181419706 Aug 23 07:34:27 PM UTC 24 Aug 23 07:34:36 PM UTC 24 1364850000 ps
T133 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.2457388109 Aug 23 07:34:27 PM UTC 24 Aug 23 07:34:37 PM UTC 24 1400730000 ps
T134 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.392381925 Aug 23 07:34:27 PM UTC 24 Aug 23 07:34:37 PM UTC 24 1402010000 ps
T135 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.3417477351 Aug 23 07:34:27 PM UTC 24 Aug 23 07:34:37 PM UTC 24 1400450000 ps
T136 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.323873117 Aug 23 07:34:27 PM UTC 24 Aug 23 07:34:37 PM UTC 24 1461450000 ps
T137 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.889346851 Aug 23 07:34:28 PM UTC 24 Aug 23 07:34:37 PM UTC 24 1298330000 ps
T138 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.58028166 Aug 23 07:34:28 PM UTC 24 Aug 23 07:34:38 PM UTC 24 1426050000 ps
T139 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.3259277994 Aug 23 07:34:28 PM UTC 24 Aug 23 07:34:38 PM UTC 24 1432550000 ps
T140 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.211469043 Aug 23 07:34:28 PM UTC 24 Aug 23 07:34:39 PM UTC 24 1555370000 ps
T141 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.985849852 Aug 23 07:34:29 PM UTC 24 Aug 23 07:34:39 PM UTC 24 1444370000 ps
T142 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.795869750 Aug 23 07:34:29 PM UTC 24 Aug 23 07:34:39 PM UTC 24 1443410000 ps
T143 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.3765796610 Aug 23 07:34:29 PM UTC 24 Aug 23 07:34:40 PM UTC 24 1549610000 ps
T144 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.2483581716 Aug 23 07:34:29 PM UTC 24 Aug 23 07:34:40 PM UTC 24 1540650000 ps
T145 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.1559624981 Aug 23 07:34:29 PM UTC 24 Aug 23 07:34:40 PM UTC 24 1567050000 ps
T146 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.3325576985 Aug 23 07:34:29 PM UTC 24 Aug 23 07:34:40 PM UTC 24 1601990000 ps
T147 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.2004727652 Aug 23 07:34:30 PM UTC 24 Aug 23 07:34:41 PM UTC 24 1480610000 ps
T148 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1052048306 Aug 23 07:34:30 PM UTC 24 Aug 23 07:34:41 PM UTC 24 1507050000 ps
T149 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.2918346485 Aug 23 07:34:35 PM UTC 24 Aug 23 07:34:45 PM UTC 24 1386450000 ps
T150 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.2500645078 Aug 23 07:34:37 PM UTC 24 Aug 23 07:34:46 PM UTC 24 1069070000 ps
T151 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.1577691629 Aug 23 07:34:37 PM UTC 24 Aug 23 07:34:47 PM UTC 24 1306110000 ps
T152 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.1155403651 Aug 23 07:34:37 PM UTC 24 Aug 23 07:34:47 PM UTC 24 1433650000 ps
T153 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.801958392 Aug 23 07:34:37 PM UTC 24 Aug 23 07:34:48 PM UTC 24 1441310000 ps
T154 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.566259113 Aug 23 07:34:37 PM UTC 24 Aug 23 07:34:48 PM UTC 24 1472330000 ps
T155 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.1957337572 Aug 23 07:34:37 PM UTC 24 Aug 23 07:34:48 PM UTC 24 1515190000 ps
T156 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.3025766544 Aug 23 07:34:38 PM UTC 24 Aug 23 07:34:49 PM UTC 24 1466450000 ps
T157 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.2961162157 Aug 23 07:34:38 PM UTC 24 Aug 23 07:34:49 PM UTC 24 1518910000 ps
T158 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.3791374622 Aug 23 07:34:39 PM UTC 24 Aug 23 07:34:49 PM UTC 24 1407010000 ps
T159 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.4270814127 Aug 23 07:34:39 PM UTC 24 Aug 23 07:34:49 PM UTC 24 1445970000 ps
T160 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.3584572405 Aug 23 07:34:39 PM UTC 24 Aug 23 07:34:50 PM UTC 24 1486330000 ps
T21 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.2597663330 Aug 23 07:35:31 PM UTC 24 Aug 23 08:10:40 PM UTC 24 336411170000 ps
T22 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.657001827 Aug 23 07:35:32 PM UTC 24 Aug 23 08:10:42 PM UTC 24 336402850000 ps
T23 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.2849748170 Aug 23 07:35:32 PM UTC 24 Aug 23 08:10:42 PM UTC 24 336399390000 ps
T24 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.129911151 Aug 23 07:35:31 PM UTC 24 Aug 23 08:10:42 PM UTC 24 336547830000 ps
T25 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.3578996653 Aug 23 07:35:32 PM UTC 24 Aug 23 08:10:43 PM UTC 24 336487670000 ps
T26 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.1377575811 Aug 23 07:35:31 PM UTC 24 Aug 23 08:10:43 PM UTC 24 336777830000 ps
T27 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.3796195314 Aug 23 07:35:33 PM UTC 24 Aug 23 08:10:43 PM UTC 24 336409450000 ps
T28 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.2117873945 Aug 23 07:35:31 PM UTC 24 Aug 23 08:10:43 PM UTC 24 336841110000 ps
T29 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.2563583555 Aug 23 07:35:31 PM UTC 24 Aug 23 08:10:43 PM UTC 24 336785050000 ps
T30 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.1550476362 Aug 23 07:35:32 PM UTC 24 Aug 23 08:10:43 PM UTC 24 336639610000 ps
T161 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.2960703883 Aug 23 07:35:32 PM UTC 24 Aug 23 08:10:44 PM UTC 24 336700730000 ps
T162 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.2006755288 Aug 23 07:35:32 PM UTC 24 Aug 23 08:10:44 PM UTC 24 336712530000 ps
T163 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.198575860 Aug 23 07:35:31 PM UTC 24 Aug 23 08:10:44 PM UTC 24 337034290000 ps
T164 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.1153960429 Aug 23 07:35:31 PM UTC 24 Aug 23 08:10:45 PM UTC 24 337005170000 ps
T165 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.3542711191 Aug 23 07:35:32 PM UTC 24 Aug 23 08:10:45 PM UTC 24 336961950000 ps
T166 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.605571 Aug 23 07:35:33 PM UTC 24 Aug 23 08:10:45 PM UTC 24 336755450000 ps
T167 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.1707663524 Aug 23 07:35:33 PM UTC 24 Aug 23 08:10:45 PM UTC 24 336840790000 ps
T168 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.1565506326 Aug 23 07:35:33 PM UTC 24 Aug 23 08:10:46 PM UTC 24 336952050000 ps
T169 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.2764029590 Aug 23 07:35:39 PM UTC 24 Aug 23 08:10:50 PM UTC 24 337011710000 ps
T170 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.1571334282 Aug 23 07:35:46 PM UTC 24 Aug 23 08:10:52 PM UTC 24 336315250000 ps
T171 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.1743309053 Aug 23 07:53:32 PM UTC 24 Aug 23 08:28:11 PM UTC 24 337013370000 ps
T172 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.2226597855 Aug 23 08:10:41 PM UTC 24 Aug 23 08:46:01 PM UTC 24 336915350000 ps
T173 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.3549007750 Aug 23 08:10:43 PM UTC 24 Aug 23 08:46:01 PM UTC 24 336518410000 ps
T174 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.2396967493 Aug 23 08:10:44 PM UTC 24 Aug 23 08:46:03 PM UTC 24 336390790000 ps
T175 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.2943573390 Aug 23 08:10:43 PM UTC 24 Aug 23 08:46:03 PM UTC 24 336739910000 ps
T176 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.2499085749 Aug 23 08:10:44 PM UTC 24 Aug 23 08:46:03 PM UTC 24 336598670000 ps
T177 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.2116145652 Aug 23 08:10:45 PM UTC 24 Aug 23 08:46:04 PM UTC 24 336343430000 ps
T178 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.1401170779 Aug 23 08:10:43 PM UTC 24 Aug 23 08:46:04 PM UTC 24 336921810000 ps
T179 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.744210509 Aug 23 08:10:44 PM UTC 24 Aug 23 08:46:04 PM UTC 24 336665690000 ps
T180 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.2966718941 Aug 23 08:10:44 PM UTC 24 Aug 23 08:46:04 PM UTC 24 336837450000 ps
T181 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.2402006224 Aug 23 08:10:44 PM UTC 24 Aug 23 08:46:04 PM UTC 24 336714770000 ps
T182 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.3409732894 Aug 23 08:10:47 PM UTC 24 Aug 23 08:46:04 PM UTC 24 336380550000 ps
T183 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.515180072 Aug 23 08:10:43 PM UTC 24 Aug 23 08:46:04 PM UTC 24 336926870000 ps
T184 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.296483878 Aug 23 08:10:44 PM UTC 24 Aug 23 08:46:05 PM UTC 24 336871970000 ps
T185 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.2979202499 Aug 23 08:10:46 PM UTC 24 Aug 23 08:46:05 PM UTC 24 336782570000 ps
T186 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.4257926012 Aug 23 08:10:44 PM UTC 24 Aug 23 08:46:05 PM UTC 24 336960150000 ps
T187 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.1142996106 Aug 23 08:10:45 PM UTC 24 Aug 23 08:46:06 PM UTC 24 336975530000 ps
T188 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.1021316361 Aug 23 08:10:45 PM UTC 24 Aug 23 08:46:07 PM UTC 24 336945250000 ps
T189 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.2471230279 Aug 23 08:10:47 PM UTC 24 Aug 23 08:46:08 PM UTC 24 336974290000 ps
T190 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.1949377197 Aug 23 08:10:51 PM UTC 24 Aug 23 08:46:10 PM UTC 24 336705650000 ps
T191 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.754722109 Aug 23 08:10:53 PM UTC 24 Aug 23 08:46:10 PM UTC 24 336429730000 ps
T192 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.1901471505 Aug 23 08:23:05 PM UTC 24 Aug 23 08:56:39 PM UTC 24 336597790000 ps
T193 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.193570445 Aug 23 08:28:13 PM UTC 24 Aug 23 09:01:01 PM UTC 24 336908310000 ps
T194 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.368550401 Aug 23 08:45:54 PM UTC 24 Aug 23 09:15:30 PM UTC 24 336697570000 ps
T195 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.3419685545 Aug 23 08:46:04 PM UTC 24 Aug 23 09:15:38 PM UTC 24 336493390000 ps
T196 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.954882017 Aug 23 08:46:02 PM UTC 24 Aug 23 09:15:39 PM UTC 24 336910610000 ps
T197 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.3582849447 Aug 23 08:46:02 PM UTC 24 Aug 23 09:15:39 PM UTC 24 336993710000 ps
T198 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.1762243483 Aug 23 08:46:04 PM UTC 24 Aug 23 09:15:39 PM UTC 24 336587990000 ps
T199 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.2826369091 Aug 23 08:46:04 PM UTC 24 Aug 23 09:15:39 PM UTC 24 336679750000 ps
T200 /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.816010767 Aug 23 08:46:04 PM UTC 24 Aug 23 09:15:42 PM UTC 24 337067430000 ps

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.117395397
Short name T2
Test name
Test status
Simulation time 1452370000 ps
CPU time 1.49 seconds
Started Aug 23 05:51:04 PM UTC 24
Finished Aug 23 05:51:15 PM UTC 24
Peak memory 177588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=117395397 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g
al.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.117395397
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/0.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.1873995600
Short name T6
Test name
Test status
Simulation time 336612810000 ps
CPU time 200.67 seconds
Started Aug 23 05:52:22 PM UTC 24
Finished Aug 23 06:27:25 PM UTC 24
Peak memory 176664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1873995600 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.1873995600
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/0.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.1377575811
Short name T26
Test name
Test status
Simulation time 336777830000 ps
CPU time 202.13 seconds
Started Aug 23 07:35:31 PM UTC 24
Finished Aug 23 08:10:43 PM UTC 24
Peak memory 176664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1377575811 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.1377575811
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/1.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.1880546652
Short name T79
Test name
Test status
Simulation time 337028150000 ps
CPU time 200.76 seconds
Started Aug 23 05:52:22 PM UTC 24
Finished Aug 23 06:27:28 PM UTC 24
Peak memory 176156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1880546652 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.1880546652
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/1.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.2656325593
Short name T16
Test name
Test status
Simulation time 336477270000 ps
CPU time 203.93 seconds
Started Aug 23 05:52:24 PM UTC 24
Finished Aug 23 06:27:26 PM UTC 24
Peak memory 176656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2656325593 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.2656325593
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/10.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.863966551
Short name T73
Test name
Test status
Simulation time 336572990000 ps
CPU time 201.12 seconds
Started Aug 23 05:52:24 PM UTC 24
Finished Aug 23 06:27:26 PM UTC 24
Peak memory 176656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=863966551 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.863966551
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/11.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.925515819
Short name T7
Test name
Test status
Simulation time 336425990000 ps
CPU time 201.08 seconds
Started Aug 23 05:52:24 PM UTC 24
Finished Aug 23 06:27:25 PM UTC 24
Peak memory 175128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=925515819 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.925515819
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/12.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.3576979302
Short name T72
Test name
Test status
Simulation time 336549250000 ps
CPU time 200.54 seconds
Started Aug 23 05:52:24 PM UTC 24
Finished Aug 23 06:27:26 PM UTC 24
Peak memory 176656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3576979302 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.3576979302
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/13.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.3723081144
Short name T20
Test name
Test status
Simulation time 336384510000 ps
CPU time 202.68 seconds
Started Aug 23 05:52:24 PM UTC 24
Finished Aug 23 06:27:26 PM UTC 24
Peak memory 176656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3723081144 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.3723081144
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/14.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.1817587748
Short name T71
Test name
Test status
Simulation time 336483450000 ps
CPU time 199.32 seconds
Started Aug 23 05:52:24 PM UTC 24
Finished Aug 23 06:27:26 PM UTC 24
Peak memory 176656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1817587748 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.1817587748
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/15.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.2456869145
Short name T76
Test name
Test status
Simulation time 336438450000 ps
CPU time 203.47 seconds
Started Aug 23 05:52:25 PM UTC 24
Finished Aug 23 06:27:27 PM UTC 24
Peak memory 176448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2456869145 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.2456869145
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/16.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.2766648864
Short name T78
Test name
Test status
Simulation time 336472370000 ps
CPU time 203.2 seconds
Started Aug 23 05:52:25 PM UTC 24
Finished Aug 23 06:27:27 PM UTC 24
Peak memory 176656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2766648864 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.2766648864
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/17.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.3526182027
Short name T75
Test name
Test status
Simulation time 336426490000 ps
CPU time 203.27 seconds
Started Aug 23 05:52:25 PM UTC 24
Finished Aug 23 06:27:26 PM UTC 24
Peak memory 176656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3526182027 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.3526182027
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/18.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2379314935
Short name T80
Test name
Test status
Simulation time 337046090000 ps
CPU time 202.49 seconds
Started Aug 23 05:52:28 PM UTC 24
Finished Aug 23 06:27:31 PM UTC 24
Peak memory 176656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2379314935 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.2379314935
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/19.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.1980290650
Short name T15
Test name
Test status
Simulation time 336697250000 ps
CPU time 201.12 seconds
Started Aug 23 05:52:22 PM UTC 24
Finished Aug 23 06:27:26 PM UTC 24
Peak memory 176656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1980290650 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.1980290650
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/2.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.1944287486
Short name T81
Test name
Test status
Simulation time 336446030000 ps
CPU time 197.39 seconds
Started Aug 23 06:27:25 PM UTC 24
Finished Aug 23 07:02:30 PM UTC 24
Peak memory 175124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1944287486 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.1944287486
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/20.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.3613684612
Short name T86
Test name
Test status
Simulation time 336923390000 ps
CPU time 199.63 seconds
Started Aug 23 06:27:26 PM UTC 24
Finished Aug 23 07:02:34 PM UTC 24
Peak memory 175116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3613684612 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.3613684612
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/21.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.1952615802
Short name T90
Test name
Test status
Simulation time 336944130000 ps
CPU time 201.77 seconds
Started Aug 23 06:27:26 PM UTC 24
Finished Aug 23 07:02:35 PM UTC 24
Peak memory 175124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1952615802 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.1952615802
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/22.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.3941967132
Short name T98
Test name
Test status
Simulation time 337106330000 ps
CPU time 201.37 seconds
Started Aug 23 06:27:27 PM UTC 24
Finished Aug 23 07:02:36 PM UTC 24
Peak memory 174648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3941967132 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.3941967132
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/23.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.3397351792
Short name T96
Test name
Test status
Simulation time 337047330000 ps
CPU time 199.18 seconds
Started Aug 23 06:27:27 PM UTC 24
Finished Aug 23 07:02:36 PM UTC 24
Peak memory 175124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3397351792 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.3397351792
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/24.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.3652861418
Short name T83
Test name
Test status
Simulation time 336444170000 ps
CPU time 197.61 seconds
Started Aug 23 06:27:27 PM UTC 24
Finished Aug 23 07:02:33 PM UTC 24
Peak memory 175124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3652861418 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.3652861418
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/25.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.189054010
Short name T85
Test name
Test status
Simulation time 336505270000 ps
CPU time 199.09 seconds
Started Aug 23 06:27:27 PM UTC 24
Finished Aug 23 07:02:33 PM UTC 24
Peak memory 174616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=189054010 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.189054010
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/26.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.3082799997
Short name T92
Test name
Test status
Simulation time 336843670000 ps
CPU time 201.92 seconds
Started Aug 23 06:27:27 PM UTC 24
Finished Aug 23 07:02:35 PM UTC 24
Peak memory 175116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3082799997 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.3082799997
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/27.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.1582330944
Short name T91
Test name
Test status
Simulation time 336821910000 ps
CPU time 199.41 seconds
Started Aug 23 06:27:27 PM UTC 24
Finished Aug 23 07:02:35 PM UTC 24
Peak memory 174780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1582330944 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.1582330944
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/28.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.2709049384
Short name T95
Test name
Test status
Simulation time 337145290000 ps
CPU time 199.76 seconds
Started Aug 23 06:27:27 PM UTC 24
Finished Aug 23 07:02:35 PM UTC 24
Peak memory 175124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2709049384 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.2709049384
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/29.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.3456348283
Short name T17
Test name
Test status
Simulation time 336749370000 ps
CPU time 201.73 seconds
Started Aug 23 05:52:22 PM UTC 24
Finished Aug 23 06:27:26 PM UTC 24
Peak memory 176664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3456348283 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.3456348283
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/3.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3526475397
Short name T87
Test name
Test status
Simulation time 336588470000 ps
CPU time 199.75 seconds
Started Aug 23 06:27:27 PM UTC 24
Finished Aug 23 07:02:34 PM UTC 24
Peak memory 175124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3526475397 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.3526475397
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/30.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.1619158711
Short name T89
Test name
Test status
Simulation time 336640790000 ps
CPU time 200.95 seconds
Started Aug 23 06:27:27 PM UTC 24
Finished Aug 23 07:02:35 PM UTC 24
Peak memory 175124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1619158711 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.1619158711
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/31.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.2581433865
Short name T84
Test name
Test status
Simulation time 336393190000 ps
CPU time 201.21 seconds
Started Aug 23 06:27:27 PM UTC 24
Finished Aug 23 07:02:33 PM UTC 24
Peak memory 175124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2581433865 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.2581433865
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/32.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.2867802828
Short name T82
Test name
Test status
Simulation time 336361310000 ps
CPU time 203.51 seconds
Started Aug 23 06:27:27 PM UTC 24
Finished Aug 23 07:02:32 PM UTC 24
Peak memory 175124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2867802828 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.2867802828
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/33.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.985534207
Short name T88
Test name
Test status
Simulation time 336616870000 ps
CPU time 198.33 seconds
Started Aug 23 06:27:27 PM UTC 24
Finished Aug 23 07:02:34 PM UTC 24
Peak memory 175124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=985534207 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.985534207
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/34.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.2038434057
Short name T99
Test name
Test status
Simulation time 337005150000 ps
CPU time 198.63 seconds
Started Aug 23 06:27:28 PM UTC 24
Finished Aug 23 07:02:36 PM UTC 24
Peak memory 174672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2038434057 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.2038434057
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/35.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.3768444120
Short name T94
Test name
Test status
Simulation time 336726770000 ps
CPU time 200.95 seconds
Started Aug 23 06:27:28 PM UTC 24
Finished Aug 23 07:02:35 PM UTC 24
Peak memory 174832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3768444120 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.3768444120
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/36.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.212885128
Short name T97
Test name
Test status
Simulation time 336882250000 ps
CPU time 200.25 seconds
Started Aug 23 06:27:28 PM UTC 24
Finished Aug 23 07:02:36 PM UTC 24
Peak memory 175124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=212885128 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.212885128
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/37.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.2493888611
Short name T93
Test name
Test status
Simulation time 336657570000 ps
CPU time 203.25 seconds
Started Aug 23 06:27:28 PM UTC 24
Finished Aug 23 07:02:35 PM UTC 24
Peak memory 175124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2493888611 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.2493888611
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/38.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.3365550261
Short name T100
Test name
Test status
Simulation time 336738510000 ps
CPU time 201.29 seconds
Started Aug 23 06:27:32 PM UTC 24
Finished Aug 23 07:02:38 PM UTC 24
Peak memory 175124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3365550261 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.3365550261
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/39.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.4287985619
Short name T18
Test name
Test status
Simulation time 336609690000 ps
CPU time 206.24 seconds
Started Aug 23 05:52:22 PM UTC 24
Finished Aug 23 06:27:26 PM UTC 24
Peak memory 176664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4287985619 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.4287985619
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/4.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.1378411208
Short name T101
Test name
Test status
Simulation time 336979590000 ps
CPU time 200.36 seconds
Started Aug 23 07:02:31 PM UTC 24
Finished Aug 23 07:34:26 PM UTC 24
Peak memory 175128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1378411208 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.1378411208
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/40.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.680578105
Short name T103
Test name
Test status
Simulation time 336890370000 ps
CPU time 196.25 seconds
Started Aug 23 07:02:33 PM UTC 24
Finished Aug 23 07:34:27 PM UTC 24
Peak memory 176656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=680578105 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.680578105
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/41.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.2172596546
Short name T107
Test name
Test status
Simulation time 336883550000 ps
CPU time 196.51 seconds
Started Aug 23 07:02:34 PM UTC 24
Finished Aug 23 07:34:28 PM UTC 24
Peak memory 176656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2172596546 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.2172596546
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/42.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.1356218523
Short name T106
Test name
Test status
Simulation time 336787650000 ps
CPU time 197.18 seconds
Started Aug 23 07:02:34 PM UTC 24
Finished Aug 23 07:34:28 PM UTC 24
Peak memory 175128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1356218523 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.1356218523
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/43.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.4025995239
Short name T104
Test name
Test status
Simulation time 336674650000 ps
CPU time 196.01 seconds
Started Aug 23 07:02:34 PM UTC 24
Finished Aug 23 07:34:27 PM UTC 24
Peak memory 176656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4025995239 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.4025995239
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/44.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.259943046
Short name T109
Test name
Test status
Simulation time 336844110000 ps
CPU time 194.38 seconds
Started Aug 23 07:02:35 PM UTC 24
Finished Aug 23 07:34:29 PM UTC 24
Peak memory 175128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=259943046 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.259943046
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/45.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.982917898
Short name T102
Test name
Test status
Simulation time 336487070000 ps
CPU time 193.51 seconds
Started Aug 23 07:02:35 PM UTC 24
Finished Aug 23 07:34:27 PM UTC 24
Peak memory 176656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=982917898 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.982917898
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/46.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.1594954569
Short name T105
Test name
Test status
Simulation time 336577150000 ps
CPU time 200.34 seconds
Started Aug 23 07:02:35 PM UTC 24
Finished Aug 23 07:34:28 PM UTC 24
Peak memory 176656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1594954569 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.1594954569
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/47.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.577683070
Short name T110
Test name
Test status
Simulation time 336778010000 ps
CPU time 190.78 seconds
Started Aug 23 07:02:35 PM UTC 24
Finished Aug 23 07:34:29 PM UTC 24
Peak memory 176648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577683070 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.577683070
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/48.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.2073548436
Short name T108
Test name
Test status
Simulation time 336595750000 ps
CPU time 192.47 seconds
Started Aug 23 07:02:36 PM UTC 24
Finished Aug 23 07:34:28 PM UTC 24
Peak memory 176656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2073548436 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.2073548436
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/49.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.2782151910
Short name T5
Test name
Test status
Simulation time 336396710000 ps
CPU time 200.68 seconds
Started Aug 23 05:52:22 PM UTC 24
Finished Aug 23 06:27:24 PM UTC 24
Peak memory 175200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2782151910 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.2782151910
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/5.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.316613169
Short name T77
Test name
Test status
Simulation time 336941590000 ps
CPU time 200.78 seconds
Started Aug 23 05:52:23 PM UTC 24
Finished Aug 23 06:27:27 PM UTC 24
Peak memory 176652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=316613169 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.316613169
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/6.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.2175555801
Short name T19
Test name
Test status
Simulation time 336704750000 ps
CPU time 205.09 seconds
Started Aug 23 05:52:23 PM UTC 24
Finished Aug 23 06:27:26 PM UTC 24
Peak memory 175136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2175555801 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.2175555801
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/7.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.368391642
Short name T14
Test name
Test status
Simulation time 336454690000 ps
CPU time 201.29 seconds
Started Aug 23 05:52:24 PM UTC 24
Finished Aug 23 06:27:26 PM UTC 24
Peak memory 176652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=368391642 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.368391642
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/8.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.3596321198
Short name T74
Test name
Test status
Simulation time 336664530000 ps
CPU time 202.36 seconds
Started Aug 23 05:52:24 PM UTC 24
Finished Aug 23 06:27:26 PM UTC 24
Peak memory 175136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3596321198 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.3596321198
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/9.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.198575860
Short name T163
Test name
Test status
Simulation time 337034290000 ps
CPU time 199.55 seconds
Started Aug 23 07:35:31 PM UTC 24
Finished Aug 23 08:10:44 PM UTC 24
Peak memory 175124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=198575860 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.198575860
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/0.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.2960703883
Short name T161
Test name
Test status
Simulation time 336700730000 ps
CPU time 201.25 seconds
Started Aug 23 07:35:32 PM UTC 24
Finished Aug 23 08:10:44 PM UTC 24
Peak memory 176656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2960703883 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.2960703883
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/10.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.3578996653
Short name T25
Test name
Test status
Simulation time 336487670000 ps
CPU time 201.08 seconds
Started Aug 23 07:35:32 PM UTC 24
Finished Aug 23 08:10:43 PM UTC 24
Peak memory 176616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3578996653 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.3578996653
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/11.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.3542711191
Short name T165
Test name
Test status
Simulation time 336961950000 ps
CPU time 202.84 seconds
Started Aug 23 07:35:32 PM UTC 24
Finished Aug 23 08:10:45 PM UTC 24
Peak memory 176656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3542711191 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.3542711191
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/12.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.657001827
Short name T22
Test name
Test status
Simulation time 336402850000 ps
CPU time 201.19 seconds
Started Aug 23 07:35:32 PM UTC 24
Finished Aug 23 08:10:42 PM UTC 24
Peak memory 176656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=657001827 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.657001827
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/13.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.1707663524
Short name T167
Test name
Test status
Simulation time 336840790000 ps
CPU time 199.25 seconds
Started Aug 23 07:35:33 PM UTC 24
Finished Aug 23 08:10:45 PM UTC 24
Peak memory 176656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1707663524 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.1707663524
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/14.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.3796195314
Short name T27
Test name
Test status
Simulation time 336409450000 ps
CPU time 203.14 seconds
Started Aug 23 07:35:33 PM UTC 24
Finished Aug 23 08:10:43 PM UTC 24
Peak memory 176648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3796195314 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.3796195314
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/15.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.1565506326
Short name T168
Test name
Test status
Simulation time 336952050000 ps
CPU time 199.91 seconds
Started Aug 23 07:35:33 PM UTC 24
Finished Aug 23 08:10:46 PM UTC 24
Peak memory 176656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1565506326 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.1565506326
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/16.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.605571
Short name T166
Test name
Test status
Simulation time 336755450000 ps
CPU time 198.8 seconds
Started Aug 23 07:35:33 PM UTC 24
Finished Aug 23 08:10:45 PM UTC 24
Peak memory 175164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=605571 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_ga
l.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.605571
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/17.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.2764029590
Short name T169
Test name
Test status
Simulation time 337011710000 ps
CPU time 200.91 seconds
Started Aug 23 07:35:39 PM UTC 24
Finished Aug 23 08:10:50 PM UTC 24
Peak memory 175128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2764029590 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.2764029590
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/18.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.1571334282
Short name T170
Test name
Test status
Simulation time 336315250000 ps
CPU time 198.62 seconds
Started Aug 23 07:35:46 PM UTC 24
Finished Aug 23 08:10:52 PM UTC 24
Peak memory 176656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571334282 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.1571334282
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/19.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.2563583555
Short name T29
Test name
Test status
Simulation time 336785050000 ps
CPU time 197.6 seconds
Started Aug 23 07:35:31 PM UTC 24
Finished Aug 23 08:10:43 PM UTC 24
Peak memory 175136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2563583555 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.2563583555
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/2.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.1743309053
Short name T171
Test name
Test status
Simulation time 337013370000 ps
CPU time 206.44 seconds
Started Aug 23 07:53:32 PM UTC 24
Finished Aug 23 08:28:11 PM UTC 24
Peak memory 175124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1743309053 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.1743309053
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/20.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.2226597855
Short name T172
Test name
Test status
Simulation time 336915350000 ps
CPU time 205.82 seconds
Started Aug 23 08:10:41 PM UTC 24
Finished Aug 23 08:46:01 PM UTC 24
Peak memory 175124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226597855 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.2226597855
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/21.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.2943573390
Short name T175
Test name
Test status
Simulation time 336739910000 ps
CPU time 206.38 seconds
Started Aug 23 08:10:43 PM UTC 24
Finished Aug 23 08:46:03 PM UTC 24
Peak memory 174668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2943573390 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.2943573390
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/22.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.3549007750
Short name T173
Test name
Test status
Simulation time 336518410000 ps
CPU time 206.08 seconds
Started Aug 23 08:10:43 PM UTC 24
Finished Aug 23 08:46:01 PM UTC 24
Peak memory 174704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3549007750 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.3549007750
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/23.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.1401170779
Short name T178
Test name
Test status
Simulation time 336921810000 ps
CPU time 208.27 seconds
Started Aug 23 08:10:43 PM UTC 24
Finished Aug 23 08:46:04 PM UTC 24
Peak memory 175124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401170779 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.1401170779
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/24.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.515180072
Short name T183
Test name
Test status
Simulation time 336926870000 ps
CPU time 208.39 seconds
Started Aug 23 08:10:43 PM UTC 24
Finished Aug 23 08:46:04 PM UTC 24
Peak memory 175124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=515180072 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.515180072
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/25.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.2396967493
Short name T174
Test name
Test status
Simulation time 336390790000 ps
CPU time 206.59 seconds
Started Aug 23 08:10:44 PM UTC 24
Finished Aug 23 08:46:03 PM UTC 24
Peak memory 175124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2396967493 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.2396967493
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/26.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.2499085749
Short name T176
Test name
Test status
Simulation time 336598670000 ps
CPU time 206.32 seconds
Started Aug 23 08:10:44 PM UTC 24
Finished Aug 23 08:46:03 PM UTC 24
Peak memory 175124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2499085749 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.2499085749
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/27.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.2402006224
Short name T181
Test name
Test status
Simulation time 336714770000 ps
CPU time 208.3 seconds
Started Aug 23 08:10:44 PM UTC 24
Finished Aug 23 08:46:04 PM UTC 24
Peak memory 175124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2402006224 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.2402006224
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/28.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.4257926012
Short name T186
Test name
Test status
Simulation time 336960150000 ps
CPU time 208.14 seconds
Started Aug 23 08:10:44 PM UTC 24
Finished Aug 23 08:46:05 PM UTC 24
Peak memory 175124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4257926012 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.4257926012
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/29.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.2117873945
Short name T28
Test name
Test status
Simulation time 336841110000 ps
CPU time 199.06 seconds
Started Aug 23 07:35:31 PM UTC 24
Finished Aug 23 08:10:43 PM UTC 24
Peak memory 175136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2117873945 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.2117873945
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/3.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.296483878
Short name T184
Test name
Test status
Simulation time 336871970000 ps
CPU time 205.99 seconds
Started Aug 23 08:10:44 PM UTC 24
Finished Aug 23 08:46:05 PM UTC 24
Peak memory 175124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=296483878 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.296483878
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/30.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.744210509
Short name T179
Test name
Test status
Simulation time 336665690000 ps
CPU time 205.36 seconds
Started Aug 23 08:10:44 PM UTC 24
Finished Aug 23 08:46:04 PM UTC 24
Peak memory 175124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=744210509 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.744210509
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/31.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.2966718941
Short name T180
Test name
Test status
Simulation time 336837450000 ps
CPU time 207.14 seconds
Started Aug 23 08:10:44 PM UTC 24
Finished Aug 23 08:46:04 PM UTC 24
Peak memory 175124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2966718941 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.2966718941
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/32.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.1021316361
Short name T188
Test name
Test status
Simulation time 336945250000 ps
CPU time 207.85 seconds
Started Aug 23 08:10:45 PM UTC 24
Finished Aug 23 08:46:07 PM UTC 24
Peak memory 175124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1021316361 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.1021316361
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/33.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.1142996106
Short name T187
Test name
Test status
Simulation time 336975530000 ps
CPU time 205.28 seconds
Started Aug 23 08:10:45 PM UTC 24
Finished Aug 23 08:46:06 PM UTC 24
Peak memory 175124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1142996106 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.1142996106
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/34.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.2116145652
Short name T177
Test name
Test status
Simulation time 336343430000 ps
CPU time 206.42 seconds
Started Aug 23 08:10:45 PM UTC 24
Finished Aug 23 08:46:04 PM UTC 24
Peak memory 175124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2116145652 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.2116145652
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/35.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.2979202499
Short name T185
Test name
Test status
Simulation time 336782570000 ps
CPU time 205.49 seconds
Started Aug 23 08:10:46 PM UTC 24
Finished Aug 23 08:46:05 PM UTC 24
Peak memory 175124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2979202499 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.2979202499
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/36.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.3409732894
Short name T182
Test name
Test status
Simulation time 336380550000 ps
CPU time 205.18 seconds
Started Aug 23 08:10:47 PM UTC 24
Finished Aug 23 08:46:04 PM UTC 24
Peak memory 175124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3409732894 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.3409732894
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/37.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.2471230279
Short name T189
Test name
Test status
Simulation time 336974290000 ps
CPU time 206.74 seconds
Started Aug 23 08:10:47 PM UTC 24
Finished Aug 23 08:46:08 PM UTC 24
Peak memory 175124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2471230279 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.2471230279
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/38.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.1949377197
Short name T190
Test name
Test status
Simulation time 336705650000 ps
CPU time 209.19 seconds
Started Aug 23 08:10:51 PM UTC 24
Finished Aug 23 08:46:10 PM UTC 24
Peak memory 175124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1949377197 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.1949377197
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/39.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.1153960429
Short name T164
Test name
Test status
Simulation time 337005170000 ps
CPU time 197.06 seconds
Started Aug 23 07:35:31 PM UTC 24
Finished Aug 23 08:10:45 PM UTC 24
Peak memory 176604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1153960429 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.1153960429
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/4.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.754722109
Short name T191
Test name
Test status
Simulation time 336429730000 ps
CPU time 205.69 seconds
Started Aug 23 08:10:53 PM UTC 24
Finished Aug 23 08:46:10 PM UTC 24
Peak memory 175124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=754722109 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.754722109
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/40.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.1901471505
Short name T192
Test name
Test status
Simulation time 336597790000 ps
CPU time 195.57 seconds
Started Aug 23 08:23:05 PM UTC 24
Finished Aug 23 08:56:39 PM UTC 24
Peak memory 175124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1901471505 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.1901471505
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/41.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.193570445
Short name T193
Test name
Test status
Simulation time 336908310000 ps
CPU time 195.68 seconds
Started Aug 23 08:28:13 PM UTC 24
Finished Aug 23 09:01:01 PM UTC 24
Peak memory 175124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=193570445 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.193570445
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/42.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.368550401
Short name T194
Test name
Test status
Simulation time 336697570000 ps
CPU time 194.69 seconds
Started Aug 23 08:45:54 PM UTC 24
Finished Aug 23 09:15:30 PM UTC 24
Peak memory 175128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=368550401 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.368550401
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/43.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.954882017
Short name T196
Test name
Test status
Simulation time 336910610000 ps
CPU time 190.32 seconds
Started Aug 23 08:46:02 PM UTC 24
Finished Aug 23 09:15:39 PM UTC 24
Peak memory 176288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=954882017 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.954882017
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/44.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.3582849447
Short name T197
Test name
Test status
Simulation time 336993710000 ps
CPU time 187.69 seconds
Started Aug 23 08:46:02 PM UTC 24
Finished Aug 23 09:15:39 PM UTC 24
Peak memory 176420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3582849447 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.3582849447
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/45.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.1762243483
Short name T198
Test name
Test status
Simulation time 336587990000 ps
CPU time 195.44 seconds
Started Aug 23 08:46:04 PM UTC 24
Finished Aug 23 09:15:39 PM UTC 24
Peak memory 176656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1762243483 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.1762243483
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/46.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.816010767
Short name T200
Test name
Test status
Simulation time 337067430000 ps
CPU time 194.13 seconds
Started Aug 23 08:46:04 PM UTC 24
Finished Aug 23 09:15:42 PM UTC 24
Peak memory 175128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=816010767 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.816010767
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/47.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.2826369091
Short name T199
Test name
Test status
Simulation time 336679750000 ps
CPU time 190.64 seconds
Started Aug 23 08:46:04 PM UTC 24
Finished Aug 23 09:15:39 PM UTC 24
Peak memory 176656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2826369091 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.2826369091
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/48.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.3419685545
Short name T195
Test name
Test status
Simulation time 336493390000 ps
CPU time 193.71 seconds
Started Aug 23 08:46:04 PM UTC 24
Finished Aug 23 09:15:38 PM UTC 24
Peak memory 176656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3419685545 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.3419685545
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/49.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.2597663330
Short name T21
Test name
Test status
Simulation time 336411170000 ps
CPU time 198.35 seconds
Started Aug 23 07:35:31 PM UTC 24
Finished Aug 23 08:10:40 PM UTC 24
Peak memory 176728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2597663330 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.2597663330
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/5.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.129911151
Short name T24
Test name
Test status
Simulation time 336547830000 ps
CPU time 200.94 seconds
Started Aug 23 07:35:31 PM UTC 24
Finished Aug 23 08:10:42 PM UTC 24
Peak memory 176652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=129911151 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.129911151
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/6.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.2849748170
Short name T23
Test name
Test status
Simulation time 336399390000 ps
CPU time 198.36 seconds
Started Aug 23 07:35:32 PM UTC 24
Finished Aug 23 08:10:42 PM UTC 24
Peak memory 176664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2849748170 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.2849748170
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/7.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.2006755288
Short name T162
Test name
Test status
Simulation time 336712530000 ps
CPU time 202.75 seconds
Started Aug 23 07:35:32 PM UTC 24
Finished Aug 23 08:10:44 PM UTC 24
Peak memory 175136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2006755288 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.2006755288
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/8.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.1550476362
Short name T30
Test name
Test status
Simulation time 336639610000 ps
CPU time 200.41 seconds
Started Aug 23 07:35:32 PM UTC 24
Finished Aug 23 08:10:43 PM UTC 24
Peak memory 176664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1550476362 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.1550476362
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/9.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.4191681035
Short name T116
Test name
Test status
Simulation time 1532270000 ps
CPU time 1.41 seconds
Started Aug 23 07:34:04 PM UTC 24
Finished Aug 23 07:34:15 PM UTC 24
Peak memory 177772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191681035 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.4191681035
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/0.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.4248650861
Short name T114
Test name
Test status
Simulation time 1447730000 ps
CPU time 1.51 seconds
Started Aug 23 07:34:04 PM UTC 24
Finished Aug 23 07:34:15 PM UTC 24
Peak memory 177772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4248650861 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.4248650861
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/1.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.1383104571
Short name T125
Test name
Test status
Simulation time 1531990000 ps
CPU time 1.44 seconds
Started Aug 23 07:34:15 PM UTC 24
Finished Aug 23 07:34:26 PM UTC 24
Peak memory 177624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1383104571 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.1383104571
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/10.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.2044964296
Short name T122
Test name
Test status
Simulation time 1455490000 ps
CPU time 1.64 seconds
Started Aug 23 07:34:15 PM UTC 24
Finished Aug 23 07:34:26 PM UTC 24
Peak memory 177776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2044964296 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.2044964296
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/11.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.1755871780
Short name T123
Test name
Test status
Simulation time 1473310000 ps
CPU time 1.49 seconds
Started Aug 23 07:34:15 PM UTC 24
Finished Aug 23 07:34:26 PM UTC 24
Peak memory 177580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1755871780 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.1755871780
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/12.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.3169260790
Short name T124
Test name
Test status
Simulation time 1496550000 ps
CPU time 1.63 seconds
Started Aug 23 07:34:15 PM UTC 24
Finished Aug 23 07:34:26 PM UTC 24
Peak memory 177776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3169260790 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.3169260790
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/13.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.3485495469
Short name T126
Test name
Test status
Simulation time 1565210000 ps
CPU time 1.51 seconds
Started Aug 23 07:34:16 PM UTC 24
Finished Aug 23 07:34:27 PM UTC 24
Peak memory 177776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3485495469 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.3485495469
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/14.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.1017244961
Short name T121
Test name
Test status
Simulation time 1270710000 ps
CPU time 1.39 seconds
Started Aug 23 07:34:16 PM UTC 24
Finished Aug 23 07:34:26 PM UTC 24
Peak memory 177772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1017244961 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.1017244961
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/15.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.4163378905
Short name T127
Test name
Test status
Simulation time 1496610000 ps
CPU time 1.51 seconds
Started Aug 23 07:34:17 PM UTC 24
Finished Aug 23 07:34:28 PM UTC 24
Peak memory 177776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4163378905 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.4163378905
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/16.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.866457392
Short name T128
Test name
Test status
Simulation time 1516270000 ps
CPU time 1.39 seconds
Started Aug 23 07:34:17 PM UTC 24
Finished Aug 23 07:34:28 PM UTC 24
Peak memory 177772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=866457392 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f
ib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.866457392
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/17.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.1558188372
Short name T129
Test name
Test status
Simulation time 1403870000 ps
CPU time 1.38 seconds
Started Aug 23 07:34:25 PM UTC 24
Finished Aug 23 07:34:34 PM UTC 24
Peak memory 177780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1558188372 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.1558188372
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/18.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.3624102832
Short name T130
Test name
Test status
Simulation time 1514750000 ps
CPU time 1.34 seconds
Started Aug 23 07:34:26 PM UTC 24
Finished Aug 23 07:34:36 PM UTC 24
Peak memory 177776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3624102832 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.3624102832
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/19.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.3284863112
Short name T111
Test name
Test status
Simulation time 1305890000 ps
CPU time 1.32 seconds
Started Aug 23 07:34:04 PM UTC 24
Finished Aug 23 07:34:14 PM UTC 24
Peak memory 177840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3284863112 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.3284863112
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/2.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.4000808039
Short name T131
Test name
Test status
Simulation time 1319230000 ps
CPU time 1.29 seconds
Started Aug 23 07:34:27 PM UTC 24
Finished Aug 23 07:34:36 PM UTC 24
Peak memory 177732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4000808039 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.4000808039
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/20.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.2457388109
Short name T133
Test name
Test status
Simulation time 1400730000 ps
CPU time 1.45 seconds
Started Aug 23 07:34:27 PM UTC 24
Finished Aug 23 07:34:37 PM UTC 24
Peak memory 177708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2457388109 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.2457388109
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/21.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.181419706
Short name T132
Test name
Test status
Simulation time 1364850000 ps
CPU time 1.34 seconds
Started Aug 23 07:34:27 PM UTC 24
Finished Aug 23 07:34:36 PM UTC 24
Peak memory 177772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=181419706 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f
ib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.181419706
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/22.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.392381925
Short name T134
Test name
Test status
Simulation time 1402010000 ps
CPU time 1.42 seconds
Started Aug 23 07:34:27 PM UTC 24
Finished Aug 23 07:34:37 PM UTC 24
Peak memory 177772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=392381925 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f
ib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.392381925
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/23.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.3417477351
Short name T135
Test name
Test status
Simulation time 1400450000 ps
CPU time 1.53 seconds
Started Aug 23 07:34:27 PM UTC 24
Finished Aug 23 07:34:37 PM UTC 24
Peak memory 177776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3417477351 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.3417477351
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/24.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.323873117
Short name T136
Test name
Test status
Simulation time 1461450000 ps
CPU time 1.39 seconds
Started Aug 23 07:34:27 PM UTC 24
Finished Aug 23 07:34:37 PM UTC 24
Peak memory 177772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=323873117 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f
ib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.323873117
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/25.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.211469043
Short name T140
Test name
Test status
Simulation time 1555370000 ps
CPU time 1.42 seconds
Started Aug 23 07:34:28 PM UTC 24
Finished Aug 23 07:34:39 PM UTC 24
Peak memory 177772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211469043 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f
ib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.211469043
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/26.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.889346851
Short name T137
Test name
Test status
Simulation time 1298330000 ps
CPU time 1.22 seconds
Started Aug 23 07:34:28 PM UTC 24
Finished Aug 23 07:34:37 PM UTC 24
Peak memory 177772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=889346851 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f
ib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.889346851
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/27.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.58028166
Short name T138
Test name
Test status
Simulation time 1426050000 ps
CPU time 1.32 seconds
Started Aug 23 07:34:28 PM UTC 24
Finished Aug 23 07:34:38 PM UTC 24
Peak memory 177648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=58028166 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fi
b.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.58028166
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/28.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.3259277994
Short name T139
Test name
Test status
Simulation time 1432550000 ps
CPU time 1.36 seconds
Started Aug 23 07:34:28 PM UTC 24
Finished Aug 23 07:34:38 PM UTC 24
Peak memory 177776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3259277994 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.3259277994
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/29.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.1324857029
Short name T113
Test name
Test status
Simulation time 1425290000 ps
CPU time 1.41 seconds
Started Aug 23 07:34:04 PM UTC 24
Finished Aug 23 07:34:14 PM UTC 24
Peak memory 177772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1324857029 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.1324857029
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/3.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.985849852
Short name T141
Test name
Test status
Simulation time 1444370000 ps
CPU time 1.41 seconds
Started Aug 23 07:34:29 PM UTC 24
Finished Aug 23 07:34:39 PM UTC 24
Peak memory 177772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=985849852 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f
ib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.985849852
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/30.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.795869750
Short name T142
Test name
Test status
Simulation time 1443410000 ps
CPU time 1.34 seconds
Started Aug 23 07:34:29 PM UTC 24
Finished Aug 23 07:34:39 PM UTC 24
Peak memory 177772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=795869750 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f
ib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.795869750
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/31.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.3325576985
Short name T146
Test name
Test status
Simulation time 1601990000 ps
CPU time 1.34 seconds
Started Aug 23 07:34:29 PM UTC 24
Finished Aug 23 07:34:40 PM UTC 24
Peak memory 177776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3325576985 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.3325576985
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/32.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.3765796610
Short name T143
Test name
Test status
Simulation time 1549610000 ps
CPU time 1.67 seconds
Started Aug 23 07:34:29 PM UTC 24
Finished Aug 23 07:34:40 PM UTC 24
Peak memory 177776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3765796610 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.3765796610
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/33.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.2483581716
Short name T144
Test name
Test status
Simulation time 1540650000 ps
CPU time 1.32 seconds
Started Aug 23 07:34:29 PM UTC 24
Finished Aug 23 07:34:40 PM UTC 24
Peak memory 177776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2483581716 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.2483581716
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/34.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.1559624981
Short name T145
Test name
Test status
Simulation time 1567050000 ps
CPU time 1.38 seconds
Started Aug 23 07:34:29 PM UTC 24
Finished Aug 23 07:34:40 PM UTC 24
Peak memory 177776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1559624981 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.1559624981
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/35.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.2004727652
Short name T147
Test name
Test status
Simulation time 1480610000 ps
CPU time 1.46 seconds
Started Aug 23 07:34:30 PM UTC 24
Finished Aug 23 07:34:41 PM UTC 24
Peak memory 177384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2004727652 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.2004727652
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/36.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1052048306
Short name T148
Test name
Test status
Simulation time 1507050000 ps
CPU time 1.32 seconds
Started Aug 23 07:34:30 PM UTC 24
Finished Aug 23 07:34:41 PM UTC 24
Peak memory 177328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052048306 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.1052048306
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/37.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.2918346485
Short name T149
Test name
Test status
Simulation time 1386450000 ps
CPU time 1.23 seconds
Started Aug 23 07:34:35 PM UTC 24
Finished Aug 23 07:34:45 PM UTC 24
Peak memory 177780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2918346485 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.2918346485
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/38.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.566259113
Short name T154
Test name
Test status
Simulation time 1472330000 ps
CPU time 1.49 seconds
Started Aug 23 07:34:37 PM UTC 24
Finished Aug 23 07:34:48 PM UTC 24
Peak memory 177744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=566259113 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f
ib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.566259113
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/39.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.2321943660
Short name T112
Test name
Test status
Simulation time 1335270000 ps
CPU time 1.27 seconds
Started Aug 23 07:34:04 PM UTC 24
Finished Aug 23 07:34:14 PM UTC 24
Peak memory 177772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2321943660 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.2321943660
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/4.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.1155403651
Short name T152
Test name
Test status
Simulation time 1433650000 ps
CPU time 1.32 seconds
Started Aug 23 07:34:37 PM UTC 24
Finished Aug 23 07:34:47 PM UTC 24
Peak memory 177776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1155403651 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.1155403651
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/40.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.1957337572
Short name T155
Test name
Test status
Simulation time 1515190000 ps
CPU time 1.41 seconds
Started Aug 23 07:34:37 PM UTC 24
Finished Aug 23 07:34:48 PM UTC 24
Peak memory 177720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1957337572 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.1957337572
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/41.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.801958392
Short name T153
Test name
Test status
Simulation time 1441310000 ps
CPU time 1.44 seconds
Started Aug 23 07:34:37 PM UTC 24
Finished Aug 23 07:34:48 PM UTC 24
Peak memory 177768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=801958392 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f
ib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.801958392
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/42.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.2500645078
Short name T150
Test name
Test status
Simulation time 1069070000 ps
CPU time 1.05 seconds
Started Aug 23 07:34:37 PM UTC 24
Finished Aug 23 07:34:46 PM UTC 24
Peak memory 177776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2500645078 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.2500645078
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/43.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.1577691629
Short name T151
Test name
Test status
Simulation time 1306110000 ps
CPU time 1.29 seconds
Started Aug 23 07:34:37 PM UTC 24
Finished Aug 23 07:34:47 PM UTC 24
Peak memory 177776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1577691629 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.1577691629
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/44.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.3025766544
Short name T156
Test name
Test status
Simulation time 1466450000 ps
CPU time 1.41 seconds
Started Aug 23 07:34:38 PM UTC 24
Finished Aug 23 07:34:49 PM UTC 24
Peak memory 177776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3025766544 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.3025766544
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/45.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.2961162157
Short name T157
Test name
Test status
Simulation time 1518910000 ps
CPU time 1.57 seconds
Started Aug 23 07:34:38 PM UTC 24
Finished Aug 23 07:34:49 PM UTC 24
Peak memory 177776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2961162157 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.2961162157
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/46.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.3584572405
Short name T160
Test name
Test status
Simulation time 1486330000 ps
CPU time 1.33 seconds
Started Aug 23 07:34:39 PM UTC 24
Finished Aug 23 07:34:50 PM UTC 24
Peak memory 177776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3584572405 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.3584572405
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/47.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.4270814127
Short name T159
Test name
Test status
Simulation time 1445970000 ps
CPU time 1.2 seconds
Started Aug 23 07:34:39 PM UTC 24
Finished Aug 23 07:34:49 PM UTC 24
Peak memory 177776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4270814127 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.4270814127
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/48.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.3791374622
Short name T158
Test name
Test status
Simulation time 1407010000 ps
CPU time 1.3 seconds
Started Aug 23 07:34:39 PM UTC 24
Finished Aug 23 07:34:49 PM UTC 24
Peak memory 177776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3791374622 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.3791374622
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/49.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.3219842069
Short name T115
Test name
Test status
Simulation time 1451970000 ps
CPU time 1.4 seconds
Started Aug 23 07:34:04 PM UTC 24
Finished Aug 23 07:34:15 PM UTC 24
Peak memory 177772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3219842069 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.3219842069
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/5.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.1766497149
Short name T117
Test name
Test status
Simulation time 1454490000 ps
CPU time 1.61 seconds
Started Aug 23 07:34:05 PM UTC 24
Finished Aug 23 07:34:16 PM UTC 24
Peak memory 177768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1766497149 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.1766497149
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/6.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.3888720299
Short name T118
Test name
Test status
Simulation time 1403330000 ps
CPU time 1.42 seconds
Started Aug 23 07:34:06 PM UTC 24
Finished Aug 23 07:34:16 PM UTC 24
Peak memory 177772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3888720299 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.3888720299
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/7.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.515900397
Short name T119
Test name
Test status
Simulation time 1511710000 ps
CPU time 1.8 seconds
Started Aug 23 07:34:06 PM UTC 24
Finished Aug 23 07:34:17 PM UTC 24
Peak memory 177768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=515900397 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f
ib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.515900397
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/8.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.517659806
Short name T120
Test name
Test status
Simulation time 1437890000 ps
CPU time 1.37 seconds
Started Aug 23 07:34:14 PM UTC 24
Finished Aug 23 07:34:25 PM UTC 24
Peak memory 177768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=517659806 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f
ib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.517659806
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/9.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.2412252236
Short name T1
Test name
Test status
Simulation time 1352830000 ps
CPU time 1.33 seconds
Started Aug 23 05:51:04 PM UTC 24
Finished Aug 23 05:51:14 PM UTC 24
Peak memory 177840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2412252236 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.2412252236
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/1.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.3837057809
Short name T4
Test name
Test status
Simulation time 1381590000 ps
CPU time 1.45 seconds
Started Aug 23 05:51:06 PM UTC 24
Finished Aug 23 05:51:15 PM UTC 24
Peak memory 177776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3837057809 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.3837057809
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/10.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.2605389508
Short name T33
Test name
Test status
Simulation time 1635530000 ps
CPU time 1.61 seconds
Started Aug 23 05:51:06 PM UTC 24
Finished Aug 23 05:51:17 PM UTC 24
Peak memory 177776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2605389508 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.2605389508
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/11.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.1266447744
Short name T36
Test name
Test status
Simulation time 1489970000 ps
CPU time 1.46 seconds
Started Aug 23 05:51:07 PM UTC 24
Finished Aug 23 05:51:18 PM UTC 24
Peak memory 177776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1266447744 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.1266447744
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/12.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.746668876
Short name T40
Test name
Test status
Simulation time 1478910000 ps
CPU time 1.38 seconds
Started Aug 23 05:51:07 PM UTC 24
Finished Aug 23 05:51:20 PM UTC 24
Peak memory 177772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=746668876 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g
al.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.746668876
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/13.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.1710057105
Short name T37
Test name
Test status
Simulation time 1547330000 ps
CPU time 1.47 seconds
Started Aug 23 05:51:07 PM UTC 24
Finished Aug 23 05:51:18 PM UTC 24
Peak memory 177776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1710057105 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.1710057105
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/14.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.3956850772
Short name T38
Test name
Test status
Simulation time 1559550000 ps
CPU time 1.69 seconds
Started Aug 23 05:51:07 PM UTC 24
Finished Aug 23 05:51:19 PM UTC 24
Peak memory 177776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3956850772 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.3956850772
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/15.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.397518662
Short name T34
Test name
Test status
Simulation time 1289970000 ps
CPU time 1.47 seconds
Started Aug 23 05:51:07 PM UTC 24
Finished Aug 23 05:51:17 PM UTC 24
Peak memory 177772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=397518662 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g
al.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.397518662
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/16.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.2144473911
Short name T32
Test name
Test status
Simulation time 1213550000 ps
CPU time 1.34 seconds
Started Aug 23 05:51:07 PM UTC 24
Finished Aug 23 05:51:17 PM UTC 24
Peak memory 177776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2144473911 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.2144473911
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/17.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.4168252481
Short name T35
Test name
Test status
Simulation time 1396370000 ps
CPU time 1.35 seconds
Started Aug 23 05:51:07 PM UTC 24
Finished Aug 23 05:51:18 PM UTC 24
Peak memory 177776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4168252481 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.4168252481
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/18.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.3152471891
Short name T39
Test name
Test status
Simulation time 1617230000 ps
CPU time 1.39 seconds
Started Aug 23 05:51:07 PM UTC 24
Finished Aug 23 05:51:19 PM UTC 24
Peak memory 177776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3152471891 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.3152471891
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/19.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.2281931559
Short name T12
Test name
Test status
Simulation time 1517830000 ps
CPU time 1.36 seconds
Started Aug 23 05:51:05 PM UTC 24
Finished Aug 23 05:51:16 PM UTC 24
Peak memory 177772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2281931559 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.2281931559
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/2.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.469700525
Short name T42
Test name
Test status
Simulation time 1532790000 ps
CPU time 1.46 seconds
Started Aug 23 05:51:15 PM UTC 24
Finished Aug 23 05:51:26 PM UTC 24
Peak memory 177772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=469700525 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g
al.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.469700525
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/20.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.1534630588
Short name T41
Test name
Test status
Simulation time 1443290000 ps
CPU time 1.33 seconds
Started Aug 23 05:51:15 PM UTC 24
Finished Aug 23 05:51:25 PM UTC 24
Peak memory 177776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1534630588 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.1534630588
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/21.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.1178884796
Short name T46
Test name
Test status
Simulation time 1403290000 ps
CPU time 1.35 seconds
Started Aug 23 05:51:16 PM UTC 24
Finished Aug 23 05:51:26 PM UTC 24
Peak memory 177776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1178884796 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.1178884796
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/22.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.4012902956
Short name T44
Test name
Test status
Simulation time 1392710000 ps
CPU time 1.43 seconds
Started Aug 23 05:51:16 PM UTC 24
Finished Aug 23 05:51:26 PM UTC 24
Peak memory 177376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4012902956 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.4012902956
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/23.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.1331160157
Short name T43
Test name
Test status
Simulation time 1361250000 ps
CPU time 1.37 seconds
Started Aug 23 05:51:16 PM UTC 24
Finished Aug 23 05:51:26 PM UTC 24
Peak memory 177776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1331160157 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.1331160157
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/24.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.4173454475
Short name T45
Test name
Test status
Simulation time 1378130000 ps
CPU time 1.59 seconds
Started Aug 23 05:51:16 PM UTC 24
Finished Aug 23 05:51:26 PM UTC 24
Peak memory 177472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4173454475 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.4173454475
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/25.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.2206563954
Short name T47
Test name
Test status
Simulation time 1422010000 ps
CPU time 1.42 seconds
Started Aug 23 05:51:16 PM UTC 24
Finished Aug 23 05:51:26 PM UTC 24
Peak memory 177428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2206563954 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.2206563954
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/26.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.2063155417
Short name T48
Test name
Test status
Simulation time 1255270000 ps
CPU time 1.23 seconds
Started Aug 23 05:51:17 PM UTC 24
Finished Aug 23 05:51:26 PM UTC 24
Peak memory 177776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2063155417 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.2063155417
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/27.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.2701714459
Short name T51
Test name
Test status
Simulation time 1418710000 ps
CPU time 1.34 seconds
Started Aug 23 05:51:17 PM UTC 24
Finished Aug 23 05:51:27 PM UTC 24
Peak memory 177776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2701714459 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.2701714459
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/28.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.3897161424
Short name T52
Test name
Test status
Simulation time 1465270000 ps
CPU time 1.42 seconds
Started Aug 23 05:51:17 PM UTC 24
Finished Aug 23 05:51:28 PM UTC 24
Peak memory 177776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3897161424 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.3897161424
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/29.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.514741202
Short name T8
Test name
Test status
Simulation time 1449390000 ps
CPU time 1.38 seconds
Started Aug 23 05:51:05 PM UTC 24
Finished Aug 23 05:51:16 PM UTC 24
Peak memory 177768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=514741202 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g
al.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.514741202
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/3.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.830644662
Short name T49
Test name
Test status
Simulation time 1364870000 ps
CPU time 1.38 seconds
Started Aug 23 05:51:17 PM UTC 24
Finished Aug 23 05:51:27 PM UTC 24
Peak memory 177772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=830644662 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g
al.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.830644662
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/30.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.219039820
Short name T55
Test name
Test status
Simulation time 1594130000 ps
CPU time 1.46 seconds
Started Aug 23 05:51:17 PM UTC 24
Finished Aug 23 05:51:28 PM UTC 24
Peak memory 177772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=219039820 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g
al.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.219039820
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/31.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.3576883491
Short name T53
Test name
Test status
Simulation time 1329790000 ps
CPU time 1.45 seconds
Started Aug 23 05:51:19 PM UTC 24
Finished Aug 23 05:51:28 PM UTC 24
Peak memory 177776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3576883491 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.3576883491
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/32.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.2487821589
Short name T50
Test name
Test status
Simulation time 1199910000 ps
CPU time 1.42 seconds
Started Aug 23 05:51:19 PM UTC 24
Finished Aug 23 05:51:27 PM UTC 24
Peak memory 177776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2487821589 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.2487821589
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/33.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.3460915468
Short name T57
Test name
Test status
Simulation time 1570210000 ps
CPU time 1.41 seconds
Started Aug 23 05:51:19 PM UTC 24
Finished Aug 23 05:51:29 PM UTC 24
Peak memory 177776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3460915468 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.3460915468
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/34.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.22868772
Short name T56
Test name
Test status
Simulation time 1439070000 ps
CPU time 1.43 seconds
Started Aug 23 05:51:19 PM UTC 24
Finished Aug 23 05:51:29 PM UTC 24
Peak memory 177772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22868772 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ga
l.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.22868772
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/35.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.2529069576
Short name T58
Test name
Test status
Simulation time 1479170000 ps
CPU time 1.43 seconds
Started Aug 23 05:51:20 PM UTC 24
Finished Aug 23 05:51:30 PM UTC 24
Peak memory 177776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2529069576 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.2529069576
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/36.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.4255055348
Short name T59
Test name
Test status
Simulation time 1512870000 ps
CPU time 1.48 seconds
Started Aug 23 05:51:20 PM UTC 24
Finished Aug 23 05:51:30 PM UTC 24
Peak memory 177776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4255055348 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.4255055348
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/37.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.3875546754
Short name T54
Test name
Test status
Simulation time 1193130000 ps
CPU time 1.35 seconds
Started Aug 23 05:51:20 PM UTC 24
Finished Aug 23 05:51:28 PM UTC 24
Peak memory 177776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3875546754 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.3875546754
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/38.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.3231904998
Short name T60
Test name
Test status
Simulation time 1408090000 ps
CPU time 1.3 seconds
Started Aug 23 05:51:21 PM UTC 24
Finished Aug 23 05:51:30 PM UTC 24
Peak memory 177776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3231904998 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.3231904998
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/39.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.1755710901
Short name T3
Test name
Test status
Simulation time 1347670000 ps
CPU time 1.3 seconds
Started Aug 23 05:51:06 PM UTC 24
Finished Aug 23 05:51:15 PM UTC 24
Peak memory 177772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1755710901 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.1755710901
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/4.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.3952563866
Short name T61
Test name
Test status
Simulation time 1462730000 ps
CPU time 1.29 seconds
Started Aug 23 05:51:26 PM UTC 24
Finished Aug 23 05:51:35 PM UTC 24
Peak memory 177776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3952563866 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.3952563866
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/40.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.3752454133
Short name T66
Test name
Test status
Simulation time 1583010000 ps
CPU time 1.36 seconds
Started Aug 23 05:51:27 PM UTC 24
Finished Aug 23 05:51:37 PM UTC 24
Peak memory 177776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3752454133 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.3752454133
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/41.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.3918953683
Short name T67
Test name
Test status
Simulation time 1585230000 ps
CPU time 1.37 seconds
Started Aug 23 05:51:27 PM UTC 24
Finished Aug 23 05:51:37 PM UTC 24
Peak memory 177776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3918953683 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.3918953683
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/42.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.2831632754
Short name T68
Test name
Test status
Simulation time 1627730000 ps
CPU time 1.6 seconds
Started Aug 23 05:51:27 PM UTC 24
Finished Aug 23 05:51:37 PM UTC 24
Peak memory 177776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2831632754 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.2831632754
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/43.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.1683179402
Short name T62
Test name
Test status
Simulation time 1304590000 ps
CPU time 1.31 seconds
Started Aug 23 05:51:27 PM UTC 24
Finished Aug 23 05:51:36 PM UTC 24
Peak memory 177776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1683179402 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.1683179402
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/44.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.2376252778
Short name T64
Test name
Test status
Simulation time 1498130000 ps
CPU time 1.55 seconds
Started Aug 23 05:51:27 PM UTC 24
Finished Aug 23 05:51:37 PM UTC 24
Peak memory 177776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2376252778 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.2376252778
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/45.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.3431431204
Short name T63
Test name
Test status
Simulation time 1390010000 ps
CPU time 1.37 seconds
Started Aug 23 05:51:27 PM UTC 24
Finished Aug 23 05:51:36 PM UTC 24
Peak memory 177776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3431431204 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.3431431204
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/46.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.1984466313
Short name T65
Test name
Test status
Simulation time 1506690000 ps
CPU time 1.41 seconds
Started Aug 23 05:51:27 PM UTC 24
Finished Aug 23 05:51:37 PM UTC 24
Peak memory 177768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1984466313 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.1984466313
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/47.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.3682474740
Short name T69
Test name
Test status
Simulation time 1452470000 ps
CPU time 1.43 seconds
Started Aug 23 05:51:28 PM UTC 24
Finished Aug 23 05:51:37 PM UTC 24
Peak memory 177776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3682474740 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.3682474740
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/48.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.3807599932
Short name T70
Test name
Test status
Simulation time 1539450000 ps
CPU time 1.43 seconds
Started Aug 23 05:51:28 PM UTC 24
Finished Aug 23 05:51:38 PM UTC 24
Peak memory 177776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3807599932 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.3807599932
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/49.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.2356880202
Short name T31
Test name
Test status
Simulation time 1585350000 ps
CPU time 1.5 seconds
Started Aug 23 05:51:06 PM UTC 24
Finished Aug 23 05:51:17 PM UTC 24
Peak memory 177768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2356880202 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.2356880202
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/5.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.3549600110
Short name T9
Test name
Test status
Simulation time 1440770000 ps
CPU time 1.39 seconds
Started Aug 23 05:51:06 PM UTC 24
Finished Aug 23 05:51:16 PM UTC 24
Peak memory 177772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3549600110 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.3549600110
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/6.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.2443539274
Short name T10
Test name
Test status
Simulation time 1480910000 ps
CPU time 1.36 seconds
Started Aug 23 05:51:06 PM UTC 24
Finished Aug 23 05:51:16 PM UTC 24
Peak memory 177772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2443539274 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.2443539274
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/7.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.3738484435
Short name T13
Test name
Test status
Simulation time 1542010000 ps
CPU time 1.43 seconds
Started Aug 23 05:51:06 PM UTC 24
Finished Aug 23 05:51:16 PM UTC 24
Peak memory 177432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3738484435 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.3738484435
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/8.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.4089246811
Short name T11
Test name
Test status
Simulation time 1463650000 ps
CPU time 1.4 seconds
Started Aug 23 05:51:06 PM UTC 24
Finished Aug 23 05:51:16 PM UTC 24
Peak memory 177404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4089246811 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.4089246811
Directory /workspaces/repo/scratch/os_regression_2024_08_22/prim_lfsr-sim-vcs/9.prim_lfsr_gal_smoke/latest
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