Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.31 100.00 96.55 100.00 100.00 95.00


Total tests in report: 200
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
87.31 87.31 100.00 100.00 96.55 96.55 100.00 100.00 100.00 100.00 40.00 40.00 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.3941204177
95.31 8.00 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 80.00 40.00 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.2668321459
96.81 1.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 87.50 7.50 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.2455208773
98.31 1.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 95.00 7.50 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.2202458283

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.1608333704
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.2167392567
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.2442186721
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.2140546394
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.980309320
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.3427442694
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.2396322547
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.831271705
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.656281372
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.2759721176
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.884012951
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.4075088680
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.4133095037
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.4031967917
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.3787999831
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.4102528966
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.3107674391
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.907698591
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.224192242
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.745583920
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.1091208910
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.943768352
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.2536227314
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.1659232562
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.155437997
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.1995271654
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.621528179
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.1662325674
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.2670472955
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.2151974304
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.3176782886
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.1231812458
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.1431324733
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.3973464851
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.3407940453
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.842126455
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.717633999
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.2996386128
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.2608175620
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.2459321699
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.218030319
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.62494489
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.4261654011
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.725111244
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.853321236
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.617279518
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.1789299795
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1806602572
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.477002673
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.3842657337
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.1336237884
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.3049938348
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.92813232
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.3262811369
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.1734104723
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.1337164075
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.873500291
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.3951110603
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.2040946391
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.3679388705
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.162792205
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.1444027479
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.2454665751
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.3088755034
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.2528740651
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.143725242
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.755510627
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.2730657786
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.1430771107
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.959493052
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.3982837103
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.1221980993
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.2296271155
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.2024954892
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.137949097
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.2486606326
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.1901330440
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.2429178849
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.1971938972
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.1175572394
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3729836255
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.2587640427
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.2337453360
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.2657403716
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.1190066073
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.4278755766
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.654572303
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/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.2884940853
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.1181713625
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1027552591
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.112262206
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.949841143
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.1534915795
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/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.4078564995
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.1044946108
/workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.1763453098
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Total test records in report: 200
tests.html | tests1.html | tests2.html | tests3.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.3655478788 Aug 27 12:03:06 AM UTC 24 Aug 27 12:03:16 AM UTC 24 1303110000 ps
T2 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.1931940404 Aug 27 12:03:06 AM UTC 24 Aug 27 12:03:17 AM UTC 24 1423810000 ps
T3 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.908732591 Aug 27 12:03:06 AM UTC 24 Aug 27 12:03:17 AM UTC 24 1442330000 ps
T9 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.2512189011 Aug 27 12:03:06 AM UTC 24 Aug 27 12:03:17 AM UTC 24 1428950000 ps
T4 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.1673165859 Aug 27 12:03:06 AM UTC 24 Aug 27 12:03:17 AM UTC 24 1467730000 ps
T5 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.3941204177 Aug 27 12:03:06 AM UTC 24 Aug 27 12:03:17 AM UTC 24 1545450000 ps
T10 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.3238174615 Aug 27 12:03:06 AM UTC 24 Aug 27 12:03:18 AM UTC 24 1506170000 ps
T11 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.3668575770 Aug 27 12:03:06 AM UTC 24 Aug 27 12:03:18 AM UTC 24 1559670000 ps
T12 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.94787269 Aug 27 12:03:06 AM UTC 24 Aug 27 12:03:18 AM UTC 24 1556430000 ps
T13 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.3876904273 Aug 27 12:03:06 AM UTC 24 Aug 27 12:03:18 AM UTC 24 1556930000 ps
T41 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.1268729450 Aug 27 12:03:08 AM UTC 24 Aug 27 12:03:19 AM UTC 24 1380270000 ps
T42 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.3240981684 Aug 27 12:03:09 AM UTC 24 Aug 27 12:03:20 AM UTC 24 1209730000 ps
T43 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.495941504 Aug 27 12:03:10 AM UTC 24 Aug 27 12:03:20 AM UTC 24 1121390000 ps
T44 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.1903325437 Aug 27 12:03:10 AM UTC 24 Aug 27 12:03:20 AM UTC 24 1178750000 ps
T45 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.3227711224 Aug 27 12:03:10 AM UTC 24 Aug 27 12:03:20 AM UTC 24 1253490000 ps
T46 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.1766602397 Aug 27 12:03:08 AM UTC 24 Aug 27 12:03:21 AM UTC 24 1592990000 ps
T47 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.1973360255 Aug 27 12:03:10 AM UTC 24 Aug 27 12:03:21 AM UTC 24 1338690000 ps
T48 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.1404688146 Aug 27 12:03:09 AM UTC 24 Aug 27 12:03:21 AM UTC 24 1380970000 ps
T49 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.692275807 Aug 27 12:03:10 AM UTC 24 Aug 27 12:03:21 AM UTC 24 1416050000 ps
T50 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.379235433 Aug 27 12:03:10 AM UTC 24 Aug 27 12:03:21 AM UTC 24 1440390000 ps
T51 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.3754019942 Aug 27 12:03:10 AM UTC 24 Aug 27 12:03:21 AM UTC 24 1474530000 ps
T52 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.3908768937 Aug 27 12:03:10 AM UTC 24 Aug 27 12:03:21 AM UTC 24 1464790000 ps
T53 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.401429532 Aug 27 12:03:10 AM UTC 24 Aug 27 12:03:21 AM UTC 24 1463770000 ps
T54 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.3740324524 Aug 27 12:03:10 AM UTC 24 Aug 27 12:03:22 AM UTC 24 1403850000 ps
T55 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.2751897356 Aug 27 12:03:10 AM UTC 24 Aug 27 12:03:22 AM UTC 24 1448310000 ps
T56 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.2401948967 Aug 27 12:03:10 AM UTC 24 Aug 27 12:03:22 AM UTC 24 1413250000 ps
T57 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.3027506448 Aug 27 12:03:10 AM UTC 24 Aug 27 12:03:22 AM UTC 24 1467610000 ps
T58 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.2731789141 Aug 27 12:03:10 AM UTC 24 Aug 27 12:03:22 AM UTC 24 1485830000 ps
T59 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.89785593 Aug 27 12:03:10 AM UTC 24 Aug 27 12:03:22 AM UTC 24 1502170000 ps
T60 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.3921841220 Aug 27 12:03:11 AM UTC 24 Aug 27 12:03:22 AM UTC 24 1339390000 ps
T61 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.3130513453 Aug 27 12:03:10 AM UTC 24 Aug 27 12:03:22 AM UTC 24 1555190000 ps
T62 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.540003890 Aug 27 12:03:10 AM UTC 24 Aug 27 12:03:22 AM UTC 24 1534850000 ps
T63 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.430359479 Aug 27 12:03:09 AM UTC 24 Aug 27 12:03:22 AM UTC 24 1604910000 ps
T64 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.2696172109 Aug 27 12:03:11 AM UTC 24 Aug 27 12:03:22 AM UTC 24 1393290000 ps
T65 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.3245420462 Aug 27 12:03:11 AM UTC 24 Aug 27 12:03:23 AM UTC 24 1496890000 ps
T66 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.3413880649 Aug 27 12:03:11 AM UTC 24 Aug 27 12:03:23 AM UTC 24 1487030000 ps
T67 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.431372730 Aug 27 12:03:11 AM UTC 24 Aug 27 12:03:23 AM UTC 24 1514630000 ps
T68 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.37107627 Aug 27 12:03:11 AM UTC 24 Aug 27 12:03:23 AM UTC 24 1559990000 ps
T69 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.1088677089 Aug 27 12:03:11 AM UTC 24 Aug 27 12:03:23 AM UTC 24 1562550000 ps
T70 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.3000062389 Aug 27 12:03:11 AM UTC 24 Aug 27 12:03:24 AM UTC 24 1571210000 ps
T71 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.3508373459 Aug 27 12:03:15 AM UTC 24 Aug 27 12:03:25 AM UTC 24 1156510000 ps
T72 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.3655119317 Aug 27 12:03:18 AM UTC 24 Aug 27 12:03:26 AM UTC 24 1098310000 ps
T73 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.1012361175 Aug 27 12:03:18 AM UTC 24 Aug 27 12:03:26 AM UTC 24 1123290000 ps
T74 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.1075218451 Aug 27 12:03:17 AM UTC 24 Aug 27 12:03:27 AM UTC 24 1441250000 ps
T75 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.2226851301 Aug 27 12:03:18 AM UTC 24 Aug 27 12:03:27 AM UTC 24 1322370000 ps
T76 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.2877367277 Aug 27 12:03:18 AM UTC 24 Aug 27 12:03:27 AM UTC 24 1345410000 ps
T77 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.930096269 Aug 27 12:03:18 AM UTC 24 Aug 27 12:03:28 AM UTC 24 1467950000 ps
T78 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.2753143004 Aug 27 12:03:19 AM UTC 24 Aug 27 12:03:29 AM UTC 24 1446710000 ps
T79 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.368710348 Aug 27 12:03:19 AM UTC 24 Aug 27 12:03:29 AM UTC 24 1527070000 ps
T80 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.3695220008 Aug 27 12:03:19 AM UTC 24 Aug 27 12:03:29 AM UTC 24 1549090000 ps
T14 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.2668321459 Aug 27 12:04:12 AM UTC 24 Aug 27 12:36:44 AM UTC 24 337000490000 ps
T15 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.162792205 Aug 27 12:04:15 AM UTC 24 Aug 27 12:36:47 AM UTC 24 336941350000 ps
T16 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.1221980993 Aug 27 12:04:17 AM UTC 24 Aug 27 12:36:48 AM UTC 24 336481890000 ps
T17 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.3842657337 Aug 27 12:04:15 AM UTC 24 Aug 27 12:36:48 AM UTC 24 336877550000 ps
T18 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.949841143 Aug 27 12:04:19 AM UTC 24 Aug 27 12:36:49 AM UTC 24 336451230000 ps
T19 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.2337453360 Aug 27 12:04:18 AM UTC 24 Aug 27 12:36:49 AM UTC 24 336926630000 ps
T20 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.1534915795 Aug 27 12:04:22 AM UTC 24 Aug 27 12:36:53 AM UTC 24 336662470000 ps
T21 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.1044946108 Aug 27 12:04:26 AM UTC 24 Aug 27 12:36:55 AM UTC 24 336429050000 ps
T22 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.4193071804 Aug 27 12:04:24 AM UTC 24 Aug 27 12:36:56 AM UTC 24 336450650000 ps
T23 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.3049938348 Aug 27 12:04:27 AM UTC 24 Aug 27 12:36:56 AM UTC 24 336642850000 ps
T81 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.4078564995 Aug 27 12:04:26 AM UTC 24 Aug 27 12:36:58 AM UTC 24 336978570000 ps
T82 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.1336237884 Aug 27 12:04:27 AM UTC 24 Aug 27 12:36:59 AM UTC 24 336919090000 ps
T83 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.92813232 Aug 27 12:04:28 AM UTC 24 Aug 27 12:36:59 AM UTC 24 336623550000 ps
T84 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.3262811369 Aug 27 12:04:29 AM UTC 24 Aug 27 12:37:00 AM UTC 24 336586930000 ps
T85 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.1337164075 Aug 27 12:04:30 AM UTC 24 Aug 27 12:37:02 AM UTC 24 336731970000 ps
T86 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.1734104723 Aug 27 12:04:30 AM UTC 24 Aug 27 12:37:04 AM UTC 24 337092850000 ps
T87 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.873500291 Aug 27 12:04:31 AM UTC 24 Aug 27 12:37:04 AM UTC 24 336978490000 ps
T88 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.2040946391 Aug 27 12:04:34 AM UTC 24 Aug 27 12:37:05 AM UTC 24 336649670000 ps
T89 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.3951110603 Aug 27 12:04:33 AM UTC 24 Aug 27 12:37:05 AM UTC 24 336670810000 ps
T90 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.1444027479 Aug 27 12:04:37 AM UTC 24 Aug 27 12:37:08 AM UTC 24 336899130000 ps
T91 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.3679388705 Aug 27 12:04:37 AM UTC 24 Aug 27 12:37:09 AM UTC 24 336771710000 ps
T92 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.2454665751 Aug 27 12:04:39 AM UTC 24 Aug 27 12:37:09 AM UTC 24 336614090000 ps
T93 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.755510627 Aug 27 12:04:43 AM UTC 24 Aug 27 12:37:11 AM UTC 24 336285950000 ps
T94 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.3088755034 Aug 27 12:04:41 AM UTC 24 Aug 27 12:37:12 AM UTC 24 336839550000 ps
T95 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.2528740651 Aug 27 12:04:42 AM UTC 24 Aug 27 12:37:12 AM UTC 24 336708150000 ps
T96 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.959493052 Aug 27 12:04:47 AM UTC 24 Aug 27 12:37:14 AM UTC 24 336383810000 ps
T97 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.2730657786 Aug 27 12:04:43 AM UTC 24 Aug 27 12:37:15 AM UTC 24 336831890000 ps
T98 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.1430771107 Aug 27 12:04:46 AM UTC 24 Aug 27 12:37:15 AM UTC 24 336534630000 ps
T99 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.143725242 Aug 27 12:04:43 AM UTC 24 Aug 27 12:37:15 AM UTC 24 337069850000 ps
T100 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.3982837103 Aug 27 12:04:50 AM UTC 24 Aug 27 12:37:18 AM UTC 24 336364910000 ps
T101 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.2296271155 Aug 27 12:04:53 AM UTC 24 Aug 27 12:37:22 AM UTC 24 336870970000 ps
T102 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.2024954892 Aug 27 12:04:55 AM UTC 24 Aug 27 12:37:23 AM UTC 24 336683210000 ps
T103 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.137949097 Aug 27 12:04:56 AM UTC 24 Aug 27 12:37:25 AM UTC 24 336989730000 ps
T104 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.2486606326 Aug 27 12:04:59 AM UTC 24 Aug 27 12:37:27 AM UTC 24 337048610000 ps
T105 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.1901330440 Aug 27 12:05:01 AM UTC 24 Aug 27 12:37:28 AM UTC 24 336622850000 ps
T106 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.2429178849 Aug 27 12:05:02 AM UTC 24 Aug 27 12:37:29 AM UTC 24 336596390000 ps
T107 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.1175572394 Aug 27 12:05:02 AM UTC 24 Aug 27 12:37:30 AM UTC 24 336885050000 ps
T108 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.1971938972 Aug 27 12:05:02 AM UTC 24 Aug 27 12:37:31 AM UTC 24 336853150000 ps
T109 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3729836255 Aug 27 12:05:03 AM UTC 24 Aug 27 12:37:32 AM UTC 24 336952610000 ps
T110 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.2587640427 Aug 27 12:05:07 AM UTC 24 Aug 27 12:37:35 AM UTC 24 336862210000 ps
T111 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.1190066073 Aug 27 12:05:10 AM UTC 24 Aug 27 12:37:36 AM UTC 24 336828470000 ps
T112 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.2657403716 Aug 27 12:05:08 AM UTC 24 Aug 27 12:37:36 AM UTC 24 336903350000 ps
T113 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.4278755766 Aug 27 12:05:12 AM UTC 24 Aug 27 12:37:37 AM UTC 24 336751970000 ps
T114 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.654572303 Aug 27 12:05:17 AM UTC 24 Aug 27 12:37:41 AM UTC 24 336755970000 ps
T115 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.2616385391 Aug 27 12:05:24 AM UTC 24 Aug 27 12:37:48 AM UTC 24 336902010000 ps
T116 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.3586912991 Aug 27 12:05:42 AM UTC 24 Aug 27 12:37:58 AM UTC 24 336453290000 ps
T117 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.2884940853 Aug 27 12:06:03 AM UTC 24 Aug 27 12:38:14 AM UTC 24 337096530000 ps
T118 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.1181713625 Aug 27 12:06:29 AM UTC 24 Aug 27 12:38:31 AM UTC 24 336943810000 ps
T119 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1027552591 Aug 27 12:06:37 AM UTC 24 Aug 27 12:38:36 AM UTC 24 336788910000 ps
T120 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.112262206 Aug 27 12:07:26 AM UTC 24 Aug 27 12:39:12 AM UTC 24 336769250000 ps
T6 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3839456994 Aug 27 12:02:45 AM UTC 24 Aug 27 12:02:54 AM UTC 24 1119150000 ps
T7 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.2202458283 Aug 27 12:02:43 AM UTC 24 Aug 27 12:02:54 AM UTC 24 1406230000 ps
T8 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2104293250 Aug 27 12:02:45 AM UTC 24 Aug 27 12:02:55 AM UTC 24 1200590000 ps
T24 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.395547306 Aug 27 12:02:44 AM UTC 24 Aug 27 12:02:55 AM UTC 24 1384470000 ps
T25 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.1763453098 Aug 27 12:02:44 AM UTC 24 Aug 27 12:02:56 AM UTC 24 1473390000 ps
T26 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.377146501 Aug 27 12:02:45 AM UTC 24 Aug 27 12:02:56 AM UTC 24 1416670000 ps
T27 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.2369977594 Aug 27 12:02:45 AM UTC 24 Aug 27 12:02:56 AM UTC 24 1433210000 ps
T28 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.4223240542 Aug 27 12:02:45 AM UTC 24 Aug 27 12:02:56 AM UTC 24 1429630000 ps
T29 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.2803636511 Aug 27 12:02:45 AM UTC 24 Aug 27 12:02:56 AM UTC 24 1501450000 ps
T30 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.1948195154 Aug 27 12:02:45 AM UTC 24 Aug 27 12:02:56 AM UTC 24 1522470000 ps
T121 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.3149278258 Aug 27 12:02:45 AM UTC 24 Aug 27 12:02:57 AM UTC 24 1492430000 ps
T122 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.356269598 Aug 27 12:02:45 AM UTC 24 Aug 27 12:02:57 AM UTC 24 1526990000 ps
T123 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.1516971071 Aug 27 12:02:45 AM UTC 24 Aug 27 12:02:57 AM UTC 24 1550870000 ps
T124 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.1860393473 Aug 27 12:02:44 AM UTC 24 Aug 27 12:02:57 AM UTC 24 1594070000 ps
T125 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.3614065761 Aug 27 12:02:47 AM UTC 24 Aug 27 12:02:57 AM UTC 24 1192310000 ps
T126 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.2492783212 Aug 27 12:02:46 AM UTC 24 Aug 27 12:02:58 AM UTC 24 1427830000 ps
T127 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.2649495543 Aug 27 12:02:46 AM UTC 24 Aug 27 12:02:58 AM UTC 24 1500770000 ps
T128 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.4074309109 Aug 27 12:02:46 AM UTC 24 Aug 27 12:02:58 AM UTC 24 1444170000 ps
T129 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.3187142726 Aug 27 12:02:46 AM UTC 24 Aug 27 12:02:58 AM UTC 24 1514810000 ps
T130 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.128525160 Aug 27 12:02:46 AM UTC 24 Aug 27 12:02:58 AM UTC 24 1503810000 ps
T131 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.1671738641 Aug 27 12:02:46 AM UTC 24 Aug 27 12:02:58 AM UTC 24 1518650000 ps
T132 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.2826622243 Aug 27 12:02:46 AM UTC 24 Aug 27 12:02:58 AM UTC 24 1529470000 ps
T133 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.1429793912 Aug 27 12:02:46 AM UTC 24 Aug 27 12:02:58 AM UTC 24 1533870000 ps
T134 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.3937693953 Aug 27 12:02:46 AM UTC 24 Aug 27 12:02:58 AM UTC 24 1511810000 ps
T135 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.3997734305 Aug 27 12:02:46 AM UTC 24 Aug 27 12:02:58 AM UTC 24 1576310000 ps
T136 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.255147027 Aug 27 12:02:48 AM UTC 24 Aug 27 12:02:59 AM UTC 24 1375210000 ps
T137 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.3523009336 Aug 27 12:02:46 AM UTC 24 Aug 27 12:02:59 AM UTC 24 1528190000 ps
T138 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2241466431 Aug 27 12:02:47 AM UTC 24 Aug 27 12:02:59 AM UTC 24 1421230000 ps
T139 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.2988829472 Aug 27 12:02:46 AM UTC 24 Aug 27 12:02:59 AM UTC 24 1564630000 ps
T140 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.880301590 Aug 27 12:02:47 AM UTC 24 Aug 27 12:02:59 AM UTC 24 1439870000 ps
T141 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.4090896206 Aug 27 12:02:49 AM UTC 24 Aug 27 12:03:01 AM UTC 24 1507330000 ps
T142 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.2662745579 Aug 27 12:02:50 AM UTC 24 Aug 27 12:03:02 AM UTC 24 1534970000 ps
T143 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.1079858160 Aug 27 12:02:50 AM UTC 24 Aug 27 12:03:02 AM UTC 24 1545850000 ps
T144 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.1877404579 Aug 27 12:02:50 AM UTC 24 Aug 27 12:03:02 AM UTC 24 1532130000 ps
T145 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.935720015 Aug 27 12:02:50 AM UTC 24 Aug 27 12:03:02 AM UTC 24 1548790000 ps
T146 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.2961889950 Aug 27 12:02:50 AM UTC 24 Aug 27 12:03:02 AM UTC 24 1578030000 ps
T147 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.845304793 Aug 27 12:02:50 AM UTC 24 Aug 27 12:03:02 AM UTC 24 1570210000 ps
T148 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.915436544 Aug 27 12:02:55 AM UTC 24 Aug 27 12:03:04 AM UTC 24 1081690000 ps
T149 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.1301859674 Aug 27 12:02:56 AM UTC 24 Aug 27 12:03:06 AM UTC 24 1254550000 ps
T150 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.589922869 Aug 27 12:02:54 AM UTC 24 Aug 27 12:03:06 AM UTC 24 1539550000 ps
T151 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.3225532320 Aug 27 12:02:55 AM UTC 24 Aug 27 12:03:06 AM UTC 24 1432030000 ps
T152 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.1997215547 Aug 27 12:02:57 AM UTC 24 Aug 27 12:03:07 AM UTC 24 1279710000 ps
T153 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.980171511 Aug 27 12:02:57 AM UTC 24 Aug 27 12:03:07 AM UTC 24 1314950000 ps
T154 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.2043839636 Aug 27 12:02:57 AM UTC 24 Aug 27 12:03:07 AM UTC 24 1310730000 ps
T155 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.2689454420 Aug 27 12:02:57 AM UTC 24 Aug 27 12:03:07 AM UTC 24 1330650000 ps
T156 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.779967729 Aug 27 12:02:58 AM UTC 24 Aug 27 12:03:07 AM UTC 24 1361250000 ps
T157 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.2469932300 Aug 27 12:02:57 AM UTC 24 Aug 27 12:03:08 AM UTC 24 1382690000 ps
T158 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1569717457 Aug 27 12:02:57 AM UTC 24 Aug 27 12:03:08 AM UTC 24 1461630000 ps
T159 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.1140188272 Aug 27 12:02:57 AM UTC 24 Aug 27 12:03:08 AM UTC 24 1459990000 ps
T160 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.3682678270 Aug 27 12:02:57 AM UTC 24 Aug 27 12:03:08 AM UTC 24 1535190000 ps
T31 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.2455208773 Aug 27 12:07:45 AM UTC 24 Aug 27 12:39:26 AM UTC 24 336478830000 ps
T32 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.1608333704 Aug 27 12:08:01 AM UTC 24 Aug 27 12:39:39 AM UTC 24 336389590000 ps
T33 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.4075088680 Aug 27 12:08:55 AM UTC 24 Aug 27 12:40:26 AM UTC 24 336695750000 ps
T34 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.2536227314 Aug 27 12:10:31 AM UTC 24 Aug 27 12:41:45 AM UTC 24 336331130000 ps
T35 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.3973464851 Aug 27 12:13:44 AM UTC 24 Aug 27 12:44:37 AM UTC 24 336930350000 ps
T36 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.853321236 Aug 27 12:32:29 AM UTC 24 Aug 27 01:01:16 AM UTC 24 336691990000 ps
T37 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.617279518 Aug 27 12:32:33 AM UTC 24 Aug 27 01:01:18 AM UTC 24 336425390000 ps
T38 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.1789299795 Aug 27 12:34:00 AM UTC 24 Aug 27 01:02:41 AM UTC 24 337036170000 ps
T39 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1806602572 Aug 27 12:34:18 AM UTC 24 Aug 27 01:02:56 AM UTC 24 336638390000 ps
T40 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.477002673 Aug 27 12:36:45 AM UTC 24 Aug 27 01:05:29 AM UTC 24 336773250000 ps
T161 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.2140546394 Aug 27 12:36:49 AM UTC 24 Aug 27 01:05:33 AM UTC 24 336657430000 ps
T162 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.2167392567 Aug 27 12:36:48 AM UTC 24 Aug 27 01:05:33 AM UTC 24 336695870000 ps
T163 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.980309320 Aug 27 12:36:50 AM UTC 24 Aug 27 01:05:35 AM UTC 24 336552610000 ps
T164 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.2442186721 Aug 27 12:36:49 AM UTC 24 Aug 27 01:05:36 AM UTC 24 337049930000 ps
T165 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.3427442694 Aug 27 12:36:50 AM UTC 24 Aug 27 01:05:37 AM UTC 24 336829050000 ps
T166 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.2396322547 Aug 27 12:36:53 AM UTC 24 Aug 27 01:05:38 AM UTC 24 336532970000 ps
T167 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.831271705 Aug 27 12:36:55 AM UTC 24 Aug 27 01:05:41 AM UTC 24 336702810000 ps
T168 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.884012951 Aug 27 12:36:58 AM UTC 24 Aug 27 01:05:43 AM UTC 24 336491070000 ps
T169 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.2759721176 Aug 27 12:36:57 AM UTC 24 Aug 27 01:05:43 AM UTC 24 336557010000 ps
T170 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.656281372 Aug 27 12:36:56 AM UTC 24 Aug 27 01:05:44 AM UTC 24 336797970000 ps
T171 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.4031967917 Aug 27 12:37:00 AM UTC 24 Aug 27 01:05:45 AM UTC 24 336465270000 ps
T172 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.4133095037 Aug 27 12:36:59 AM UTC 24 Aug 27 01:05:47 AM UTC 24 336623490000 ps
T173 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.3787999831 Aug 27 12:37:01 AM UTC 24 Aug 27 01:05:48 AM UTC 24 336853450000 ps
T174 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.4102528966 Aug 27 12:37:03 AM UTC 24 Aug 27 01:05:53 AM UTC 24 336904270000 ps
T175 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.3107674391 Aug 27 12:37:05 AM UTC 24 Aug 27 01:05:53 AM UTC 24 336549850000 ps
T176 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.907698591 Aug 27 12:37:05 AM UTC 24 Aug 27 01:05:54 AM UTC 24 336623650000 ps
T177 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.745583920 Aug 27 12:37:06 AM UTC 24 Aug 27 01:05:56 AM UTC 24 336582410000 ps
T178 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.224192242 Aug 27 12:37:06 AM UTC 24 Aug 27 01:05:57 AM UTC 24 336950310000 ps
T179 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.943768352 Aug 27 12:37:10 AM UTC 24 Aug 27 01:06:01 AM UTC 24 336446070000 ps
T180 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.1659232562 Aug 27 12:37:10 AM UTC 24 Aug 27 01:06:02 AM UTC 24 336452810000 ps
T181 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.1091208910 Aug 27 12:37:09 AM UTC 24 Aug 27 01:06:03 AM UTC 24 336955230000 ps
T182 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.1995271654 Aug 27 12:37:13 AM UTC 24 Aug 27 01:06:07 AM UTC 24 336776150000 ps
T183 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.155437997 Aug 27 12:37:12 AM UTC 24 Aug 27 01:06:07 AM UTC 24 336961390000 ps
T184 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.621528179 Aug 27 12:37:13 AM UTC 24 Aug 27 01:06:07 AM UTC 24 336843430000 ps
T185 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.2151974304 Aug 27 12:37:15 AM UTC 24 Aug 27 01:06:08 AM UTC 24 336548870000 ps
T186 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.1662325674 Aug 27 12:37:15 AM UTC 24 Aug 27 01:06:10 AM UTC 24 336828550000 ps
T187 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.2670472955 Aug 27 12:37:15 AM UTC 24 Aug 27 01:06:10 AM UTC 24 336880950000 ps
T188 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.3176782886 Aug 27 12:37:16 AM UTC 24 Aug 27 01:06:13 AM UTC 24 336997030000 ps
T189 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.1231812458 Aug 27 12:37:18 AM UTC 24 Aug 27 01:06:14 AM UTC 24 336677490000 ps
T190 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.3407940453 Aug 27 12:37:23 AM UTC 24 Aug 27 01:06:23 AM UTC 24 336788910000 ps
T191 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.1431324733 Aug 27 12:37:22 AM UTC 24 Aug 27 01:06:23 AM UTC 24 337097010000 ps
T192 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.842126455 Aug 27 12:37:27 AM UTC 24 Aug 27 01:06:28 AM UTC 24 337111830000 ps
T193 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.717633999 Aug 27 12:37:28 AM UTC 24 Aug 27 01:06:30 AM UTC 24 336835390000 ps
T194 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.2996386128 Aug 27 12:37:29 AM UTC 24 Aug 27 01:06:30 AM UTC 24 336819170000 ps
T195 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.2459321699 Aug 27 12:37:31 AM UTC 24 Aug 27 01:06:31 AM UTC 24 336576750000 ps
T196 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.2608175620 Aug 27 12:37:31 AM UTC 24 Aug 27 01:06:31 AM UTC 24 336464110000 ps
T197 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.218030319 Aug 27 12:37:32 AM UTC 24 Aug 27 01:06:33 AM UTC 24 336677330000 ps
T198 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.62494489 Aug 27 12:37:33 AM UTC 24 Aug 27 01:06:34 AM UTC 24 336421010000 ps
T199 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.4261654011 Aug 27 12:37:36 AM UTC 24 Aug 27 01:06:37 AM UTC 24 336441690000 ps
T200 /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.725111244 Aug 27 12:37:36 AM UTC 24 Aug 27 01:06:40 AM UTC 24 336850710000 ps

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.3941204177
Short name T5
Test name
Test status
Simulation time 1545450000 ps
CPU time 1.96 seconds
Started Aug 27 12:03:06 AM UTC 24
Finished Aug 27 12:03:17 AM UTC 24
Peak memory 177772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3941204177 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.3941204177
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/0.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.2668321459
Short name T14
Test name
Test status
Simulation time 337000490000 ps
CPU time 229.97 seconds
Started Aug 27 12:04:12 AM UTC 24
Finished Aug 27 12:36:44 AM UTC 24
Peak memory 175188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2668321459 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.2668321459
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/0.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.2455208773
Short name T31
Test name
Test status
Simulation time 336478830000 ps
CPU time 227.09 seconds
Started Aug 27 12:07:45 AM UTC 24
Finished Aug 27 12:39:26 AM UTC 24
Peak memory 175192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2455208773 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.2455208773
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/0.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.2202458283
Short name T7
Test name
Test status
Simulation time 1406230000 ps
CPU time 1.74 seconds
Started Aug 27 12:02:43 AM UTC 24
Finished Aug 27 12:02:54 AM UTC 24
Peak memory 177772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2202458283 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.2202458283
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/0.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.1608333704
Short name T32
Test name
Test status
Simulation time 336389590000 ps
CPU time 226.4 seconds
Started Aug 27 12:08:01 AM UTC 24
Finished Aug 27 12:39:39 AM UTC 24
Peak memory 175128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1608333704 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.1608333704
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/1.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.2167392567
Short name T162
Test name
Test status
Simulation time 336695870000 ps
CPU time 220.18 seconds
Started Aug 27 12:36:48 AM UTC 24
Finished Aug 27 01:05:33 AM UTC 24
Peak memory 176656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2167392567 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.2167392567
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/10.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.2442186721
Short name T164
Test name
Test status
Simulation time 337049930000 ps
CPU time 224.26 seconds
Started Aug 27 12:36:49 AM UTC 24
Finished Aug 27 01:05:36 AM UTC 24
Peak memory 176656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2442186721 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.2442186721
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/11.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.2140546394
Short name T161
Test name
Test status
Simulation time 336657430000 ps
CPU time 220.62 seconds
Started Aug 27 12:36:49 AM UTC 24
Finished Aug 27 01:05:33 AM UTC 24
Peak memory 176656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2140546394 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.2140546394
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/12.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.980309320
Short name T163
Test name
Test status
Simulation time 336552610000 ps
CPU time 220.66 seconds
Started Aug 27 12:36:50 AM UTC 24
Finished Aug 27 01:05:35 AM UTC 24
Peak memory 176660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=980309320 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.980309320
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/13.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.3427442694
Short name T165
Test name
Test status
Simulation time 336829050000 ps
CPU time 220.85 seconds
Started Aug 27 12:36:50 AM UTC 24
Finished Aug 27 01:05:37 AM UTC 24
Peak memory 175128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3427442694 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.3427442694
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/14.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.2396322547
Short name T166
Test name
Test status
Simulation time 336532970000 ps
CPU time 223.01 seconds
Started Aug 27 12:36:53 AM UTC 24
Finished Aug 27 01:05:38 AM UTC 24
Peak memory 176656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2396322547 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.2396322547
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/15.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.831271705
Short name T167
Test name
Test status
Simulation time 336702810000 ps
CPU time 222.17 seconds
Started Aug 27 12:36:55 AM UTC 24
Finished Aug 27 01:05:41 AM UTC 24
Peak memory 176656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=831271705 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.831271705
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/16.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.656281372
Short name T170
Test name
Test status
Simulation time 336797970000 ps
CPU time 223.01 seconds
Started Aug 27 12:36:56 AM UTC 24
Finished Aug 27 01:05:44 AM UTC 24
Peak memory 176660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=656281372 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.656281372
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/17.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.2759721176
Short name T169
Test name
Test status
Simulation time 336557010000 ps
CPU time 223.24 seconds
Started Aug 27 12:36:57 AM UTC 24
Finished Aug 27 01:05:43 AM UTC 24
Peak memory 176656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2759721176 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.2759721176
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/18.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.884012951
Short name T168
Test name
Test status
Simulation time 336491070000 ps
CPU time 223 seconds
Started Aug 27 12:36:58 AM UTC 24
Finished Aug 27 01:05:43 AM UTC 24
Peak memory 175132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=884012951 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.884012951
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/19.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.4075088680
Short name T33
Test name
Test status
Simulation time 336695750000 ps
CPU time 230.48 seconds
Started Aug 27 12:08:55 AM UTC 24
Finished Aug 27 12:40:26 AM UTC 24
Peak memory 176660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4075088680 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.4075088680
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/2.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.4133095037
Short name T172
Test name
Test status
Simulation time 336623490000 ps
CPU time 220.12 seconds
Started Aug 27 12:36:59 AM UTC 24
Finished Aug 27 01:05:47 AM UTC 24
Peak memory 176656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4133095037 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.4133095037
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/20.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.4031967917
Short name T171
Test name
Test status
Simulation time 336465270000 ps
CPU time 221.09 seconds
Started Aug 27 12:37:00 AM UTC 24
Finished Aug 27 01:05:45 AM UTC 24
Peak memory 175128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4031967917 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.4031967917
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/21.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.3787999831
Short name T173
Test name
Test status
Simulation time 336853450000 ps
CPU time 222.58 seconds
Started Aug 27 12:37:01 AM UTC 24
Finished Aug 27 01:05:48 AM UTC 24
Peak memory 176656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3787999831 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.3787999831
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/22.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.4102528966
Short name T174
Test name
Test status
Simulation time 336904270000 ps
CPU time 222.43 seconds
Started Aug 27 12:37:03 AM UTC 24
Finished Aug 27 01:05:53 AM UTC 24
Peak memory 176656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4102528966 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.4102528966
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/23.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.3107674391
Short name T175
Test name
Test status
Simulation time 336549850000 ps
CPU time 222.6 seconds
Started Aug 27 12:37:05 AM UTC 24
Finished Aug 27 01:05:53 AM UTC 24
Peak memory 175128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3107674391 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.3107674391
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/24.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.907698591
Short name T176
Test name
Test status
Simulation time 336623650000 ps
CPU time 219.63 seconds
Started Aug 27 12:37:05 AM UTC 24
Finished Aug 27 01:05:54 AM UTC 24
Peak memory 176660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=907698591 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.907698591
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/25.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.224192242
Short name T178
Test name
Test status
Simulation time 336950310000 ps
CPU time 222.47 seconds
Started Aug 27 12:37:06 AM UTC 24
Finished Aug 27 01:05:57 AM UTC 24
Peak memory 175132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=224192242 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.224192242
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/26.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.745583920
Short name T177
Test name
Test status
Simulation time 336582410000 ps
CPU time 220.56 seconds
Started Aug 27 12:37:06 AM UTC 24
Finished Aug 27 01:05:56 AM UTC 24
Peak memory 176660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=745583920 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.745583920
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/27.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.1091208910
Short name T181
Test name
Test status
Simulation time 336955230000 ps
CPU time 221.62 seconds
Started Aug 27 12:37:09 AM UTC 24
Finished Aug 27 01:06:03 AM UTC 24
Peak memory 175128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1091208910 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.1091208910
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/28.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.943768352
Short name T179
Test name
Test status
Simulation time 336446070000 ps
CPU time 223.9 seconds
Started Aug 27 12:37:10 AM UTC 24
Finished Aug 27 01:06:01 AM UTC 24
Peak memory 176660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=943768352 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.943768352
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/29.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.2536227314
Short name T34
Test name
Test status
Simulation time 336331130000 ps
CPU time 226.53 seconds
Started Aug 27 12:10:31 AM UTC 24
Finished Aug 27 12:41:45 AM UTC 24
Peak memory 175124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2536227314 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.2536227314
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/3.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.1659232562
Short name T180
Test name
Test status
Simulation time 336452810000 ps
CPU time 220.69 seconds
Started Aug 27 12:37:10 AM UTC 24
Finished Aug 27 01:06:02 AM UTC 24
Peak memory 175128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1659232562 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.1659232562
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/30.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.155437997
Short name T183
Test name
Test status
Simulation time 336961390000 ps
CPU time 221.87 seconds
Started Aug 27 12:37:12 AM UTC 24
Finished Aug 27 01:06:07 AM UTC 24
Peak memory 175128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=155437997 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.155437997
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/31.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.1995271654
Short name T182
Test name
Test status
Simulation time 336776150000 ps
CPU time 220.33 seconds
Started Aug 27 12:37:13 AM UTC 24
Finished Aug 27 01:06:07 AM UTC 24
Peak memory 175112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1995271654 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.1995271654
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/32.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.621528179
Short name T184
Test name
Test status
Simulation time 336843430000 ps
CPU time 221.9 seconds
Started Aug 27 12:37:13 AM UTC 24
Finished Aug 27 01:06:07 AM UTC 24
Peak memory 176656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=621528179 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.621528179
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/33.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.1662325674
Short name T186
Test name
Test status
Simulation time 336828550000 ps
CPU time 223.68 seconds
Started Aug 27 12:37:15 AM UTC 24
Finished Aug 27 01:06:10 AM UTC 24
Peak memory 176656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1662325674 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.1662325674
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/34.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.2670472955
Short name T187
Test name
Test status
Simulation time 336880950000 ps
CPU time 224.29 seconds
Started Aug 27 12:37:15 AM UTC 24
Finished Aug 27 01:06:10 AM UTC 24
Peak memory 175128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2670472955 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.2670472955
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/35.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.2151974304
Short name T185
Test name
Test status
Simulation time 336548870000 ps
CPU time 223.68 seconds
Started Aug 27 12:37:15 AM UTC 24
Finished Aug 27 01:06:08 AM UTC 24
Peak memory 176652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2151974304 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.2151974304
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/36.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.3176782886
Short name T188
Test name
Test status
Simulation time 336997030000 ps
CPU time 224.13 seconds
Started Aug 27 12:37:16 AM UTC 24
Finished Aug 27 01:06:13 AM UTC 24
Peak memory 176656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3176782886 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.3176782886
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/37.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.1231812458
Short name T189
Test name
Test status
Simulation time 336677490000 ps
CPU time 220.39 seconds
Started Aug 27 12:37:18 AM UTC 24
Finished Aug 27 01:06:14 AM UTC 24
Peak memory 175128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1231812458 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.1231812458
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/38.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.1431324733
Short name T191
Test name
Test status
Simulation time 337097010000 ps
CPU time 221.48 seconds
Started Aug 27 12:37:22 AM UTC 24
Finished Aug 27 01:06:23 AM UTC 24
Peak memory 175128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1431324733 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.1431324733
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/39.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.3973464851
Short name T35
Test name
Test status
Simulation time 336930350000 ps
CPU time 225.85 seconds
Started Aug 27 12:13:44 AM UTC 24
Finished Aug 27 12:44:37 AM UTC 24
Peak memory 176652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3973464851 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.3973464851
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/4.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.3407940453
Short name T190
Test name
Test status
Simulation time 336788910000 ps
CPU time 222.85 seconds
Started Aug 27 12:37:23 AM UTC 24
Finished Aug 27 01:06:23 AM UTC 24
Peak memory 176656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3407940453 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.3407940453
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/40.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.842126455
Short name T192
Test name
Test status
Simulation time 337111830000 ps
CPU time 220.95 seconds
Started Aug 27 12:37:27 AM UTC 24
Finished Aug 27 01:06:28 AM UTC 24
Peak memory 176660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=842126455 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.842126455
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/41.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.717633999
Short name T193
Test name
Test status
Simulation time 336835390000 ps
CPU time 221.17 seconds
Started Aug 27 12:37:28 AM UTC 24
Finished Aug 27 01:06:30 AM UTC 24
Peak memory 176656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=717633999 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.717633999
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/42.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.2996386128
Short name T194
Test name
Test status
Simulation time 336819170000 ps
CPU time 224.46 seconds
Started Aug 27 12:37:29 AM UTC 24
Finished Aug 27 01:06:30 AM UTC 24
Peak memory 175128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2996386128 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.2996386128
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/43.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.2608175620
Short name T196
Test name
Test status
Simulation time 336464110000 ps
CPU time 221.42 seconds
Started Aug 27 12:37:31 AM UTC 24
Finished Aug 27 01:06:31 AM UTC 24
Peak memory 175128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2608175620 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.2608175620
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/44.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.2459321699
Short name T195
Test name
Test status
Simulation time 336576750000 ps
CPU time 223.42 seconds
Started Aug 27 12:37:31 AM UTC 24
Finished Aug 27 01:06:31 AM UTC 24
Peak memory 175128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2459321699 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.2459321699
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/45.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.218030319
Short name T197
Test name
Test status
Simulation time 336677330000 ps
CPU time 220.74 seconds
Started Aug 27 12:37:32 AM UTC 24
Finished Aug 27 01:06:33 AM UTC 24
Peak memory 176660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=218030319 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.218030319
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/46.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.62494489
Short name T198
Test name
Test status
Simulation time 336421010000 ps
CPU time 222.22 seconds
Started Aug 27 12:37:33 AM UTC 24
Finished Aug 27 01:06:34 AM UTC 24
Peak memory 175124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=62494489 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_
fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.62494489
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/47.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.4261654011
Short name T199
Test name
Test status
Simulation time 336441690000 ps
CPU time 220.16 seconds
Started Aug 27 12:37:36 AM UTC 24
Finished Aug 27 01:06:37 AM UTC 24
Peak memory 176656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4261654011 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.4261654011
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/48.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.725111244
Short name T200
Test name
Test status
Simulation time 336850710000 ps
CPU time 220.3 seconds
Started Aug 27 12:37:36 AM UTC 24
Finished Aug 27 01:06:40 AM UTC 24
Peak memory 176644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=725111244 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.725111244
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/49.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.853321236
Short name T36
Test name
Test status
Simulation time 336691990000 ps
CPU time 223.15 seconds
Started Aug 27 12:32:29 AM UTC 24
Finished Aug 27 01:01:16 AM UTC 24
Peak memory 175124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=853321236 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.853321236
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/5.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.617279518
Short name T37
Test name
Test status
Simulation time 336425390000 ps
CPU time 221.37 seconds
Started Aug 27 12:32:33 AM UTC 24
Finished Aug 27 01:01:18 AM UTC 24
Peak memory 175124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=617279518 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.617279518
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/6.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.1789299795
Short name T38
Test name
Test status
Simulation time 337036170000 ps
CPU time 221.61 seconds
Started Aug 27 12:34:00 AM UTC 24
Finished Aug 27 01:02:41 AM UTC 24
Peak memory 175124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1789299795 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.1789299795
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/7.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1806602572
Short name T39
Test name
Test status
Simulation time 336638390000 ps
CPU time 223 seconds
Started Aug 27 12:34:18 AM UTC 24
Finished Aug 27 01:02:56 AM UTC 24
Peak memory 175120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1806602572 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.1806602572
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/8.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.477002673
Short name T40
Test name
Test status
Simulation time 336773250000 ps
CPU time 223.14 seconds
Started Aug 27 12:36:45 AM UTC 24
Finished Aug 27 01:05:29 AM UTC 24
Peak memory 176656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=477002673 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.477002673
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/9.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.3842657337
Short name T17
Test name
Test status
Simulation time 336877550000 ps
CPU time 228.19 seconds
Started Aug 27 12:04:15 AM UTC 24
Finished Aug 27 12:36:48 AM UTC 24
Peak memory 175124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3842657337 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.3842657337
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/1.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.1336237884
Short name T82
Test name
Test status
Simulation time 336919090000 ps
CPU time 229.87 seconds
Started Aug 27 12:04:27 AM UTC 24
Finished Aug 27 12:36:59 AM UTC 24
Peak memory 176656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1336237884 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.1336237884
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/10.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.3049938348
Short name T23
Test name
Test status
Simulation time 336642850000 ps
CPU time 227.6 seconds
Started Aug 27 12:04:27 AM UTC 24
Finished Aug 27 12:36:56 AM UTC 24
Peak memory 175128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3049938348 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.3049938348
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/11.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.92813232
Short name T83
Test name
Test status
Simulation time 336623550000 ps
CPU time 229.09 seconds
Started Aug 27 12:04:28 AM UTC 24
Finished Aug 27 12:36:59 AM UTC 24
Peak memory 175124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92813232 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_
gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.92813232
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/12.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.3262811369
Short name T84
Test name
Test status
Simulation time 336586930000 ps
CPU time 229.83 seconds
Started Aug 27 12:04:29 AM UTC 24
Finished Aug 27 12:37:00 AM UTC 24
Peak memory 176656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3262811369 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.3262811369
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/13.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.1734104723
Short name T86
Test name
Test status
Simulation time 337092850000 ps
CPU time 228 seconds
Started Aug 27 12:04:30 AM UTC 24
Finished Aug 27 12:37:04 AM UTC 24
Peak memory 176656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1734104723 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.1734104723
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/14.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.1337164075
Short name T85
Test name
Test status
Simulation time 336731970000 ps
CPU time 226.54 seconds
Started Aug 27 12:04:30 AM UTC 24
Finished Aug 27 12:37:02 AM UTC 24
Peak memory 175128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1337164075 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.1337164075
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/15.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.873500291
Short name T87
Test name
Test status
Simulation time 336978490000 ps
CPU time 230.49 seconds
Started Aug 27 12:04:31 AM UTC 24
Finished Aug 27 12:37:04 AM UTC 24
Peak memory 175132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=873500291 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.873500291
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/16.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.3951110603
Short name T89
Test name
Test status
Simulation time 336670810000 ps
CPU time 225.23 seconds
Started Aug 27 12:04:33 AM UTC 24
Finished Aug 27 12:37:05 AM UTC 24
Peak memory 176656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3951110603 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.3951110603
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/17.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.2040946391
Short name T88
Test name
Test status
Simulation time 336649670000 ps
CPU time 229.59 seconds
Started Aug 27 12:04:34 AM UTC 24
Finished Aug 27 12:37:05 AM UTC 24
Peak memory 175128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2040946391 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.2040946391
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/18.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.3679388705
Short name T91
Test name
Test status
Simulation time 336771710000 ps
CPU time 227.71 seconds
Started Aug 27 12:04:37 AM UTC 24
Finished Aug 27 12:37:09 AM UTC 24
Peak memory 175128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3679388705 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.3679388705
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/19.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.162792205
Short name T15
Test name
Test status
Simulation time 336941350000 ps
CPU time 227.47 seconds
Started Aug 27 12:04:15 AM UTC 24
Finished Aug 27 12:36:47 AM UTC 24
Peak memory 175128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162792205 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.162792205
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/2.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.1444027479
Short name T90
Test name
Test status
Simulation time 336899130000 ps
CPU time 227.37 seconds
Started Aug 27 12:04:37 AM UTC 24
Finished Aug 27 12:37:08 AM UTC 24
Peak memory 176656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1444027479 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.1444027479
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/20.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.2454665751
Short name T92
Test name
Test status
Simulation time 336614090000 ps
CPU time 225.06 seconds
Started Aug 27 12:04:39 AM UTC 24
Finished Aug 27 12:37:09 AM UTC 24
Peak memory 175116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2454665751 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.2454665751
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/21.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.3088755034
Short name T94
Test name
Test status
Simulation time 336839550000 ps
CPU time 227.54 seconds
Started Aug 27 12:04:41 AM UTC 24
Finished Aug 27 12:37:12 AM UTC 24
Peak memory 175128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3088755034 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.3088755034
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/22.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.2528740651
Short name T95
Test name
Test status
Simulation time 336708150000 ps
CPU time 226.29 seconds
Started Aug 27 12:04:42 AM UTC 24
Finished Aug 27 12:37:12 AM UTC 24
Peak memory 175128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2528740651 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.2528740651
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/23.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.143725242
Short name T99
Test name
Test status
Simulation time 337069850000 ps
CPU time 225.31 seconds
Started Aug 27 12:04:43 AM UTC 24
Finished Aug 27 12:37:15 AM UTC 24
Peak memory 175132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=143725242 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.143725242
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/24.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.755510627
Short name T93
Test name
Test status
Simulation time 336285950000 ps
CPU time 226.56 seconds
Started Aug 27 12:04:43 AM UTC 24
Finished Aug 27 12:37:11 AM UTC 24
Peak memory 176656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=755510627 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.755510627
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/25.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.2730657786
Short name T97
Test name
Test status
Simulation time 336831890000 ps
CPU time 226.2 seconds
Started Aug 27 12:04:43 AM UTC 24
Finished Aug 27 12:37:15 AM UTC 24
Peak memory 176656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2730657786 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.2730657786
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/26.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.1430771107
Short name T98
Test name
Test status
Simulation time 336534630000 ps
CPU time 225.83 seconds
Started Aug 27 12:04:46 AM UTC 24
Finished Aug 27 12:37:15 AM UTC 24
Peak memory 175128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1430771107 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.1430771107
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/27.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.959493052
Short name T96
Test name
Test status
Simulation time 336383810000 ps
CPU time 227.75 seconds
Started Aug 27 12:04:47 AM UTC 24
Finished Aug 27 12:37:14 AM UTC 24
Peak memory 175132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=959493052 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.959493052
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/28.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.3982837103
Short name T100
Test name
Test status
Simulation time 336364910000 ps
CPU time 225.85 seconds
Started Aug 27 12:04:50 AM UTC 24
Finished Aug 27 12:37:18 AM UTC 24
Peak memory 175124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3982837103 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.3982837103
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/29.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.1221980993
Short name T16
Test name
Test status
Simulation time 336481890000 ps
CPU time 229.88 seconds
Started Aug 27 12:04:17 AM UTC 24
Finished Aug 27 12:36:48 AM UTC 24
Peak memory 176644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1221980993 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.1221980993
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/3.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.2296271155
Short name T101
Test name
Test status
Simulation time 336870970000 ps
CPU time 228.83 seconds
Started Aug 27 12:04:53 AM UTC 24
Finished Aug 27 12:37:22 AM UTC 24
Peak memory 175124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2296271155 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.2296271155
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/30.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.2024954892
Short name T102
Test name
Test status
Simulation time 336683210000 ps
CPU time 229.43 seconds
Started Aug 27 12:04:55 AM UTC 24
Finished Aug 27 12:37:23 AM UTC 24
Peak memory 175124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2024954892 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.2024954892
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/31.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.137949097
Short name T103
Test name
Test status
Simulation time 336989730000 ps
CPU time 224.34 seconds
Started Aug 27 12:04:56 AM UTC 24
Finished Aug 27 12:37:25 AM UTC 24
Peak memory 175132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=137949097 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.137949097
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/32.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.2486606326
Short name T104
Test name
Test status
Simulation time 337048610000 ps
CPU time 226.52 seconds
Started Aug 27 12:04:59 AM UTC 24
Finished Aug 27 12:37:27 AM UTC 24
Peak memory 175128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2486606326 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.2486606326
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/33.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.1901330440
Short name T105
Test name
Test status
Simulation time 336622850000 ps
CPU time 228.4 seconds
Started Aug 27 12:05:01 AM UTC 24
Finished Aug 27 12:37:28 AM UTC 24
Peak memory 175128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1901330440 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.1901330440
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/34.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.2429178849
Short name T106
Test name
Test status
Simulation time 336596390000 ps
CPU time 225.99 seconds
Started Aug 27 12:05:02 AM UTC 24
Finished Aug 27 12:37:29 AM UTC 24
Peak memory 175128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2429178849 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.2429178849
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/35.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.1971938972
Short name T108
Test name
Test status
Simulation time 336853150000 ps
CPU time 225.75 seconds
Started Aug 27 12:05:02 AM UTC 24
Finished Aug 27 12:37:31 AM UTC 24
Peak memory 176464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1971938972 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.1971938972
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/36.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.1175572394
Short name T107
Test name
Test status
Simulation time 336885050000 ps
CPU time 227.32 seconds
Started Aug 27 12:05:02 AM UTC 24
Finished Aug 27 12:37:30 AM UTC 24
Peak memory 175124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1175572394 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.1175572394
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/37.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3729836255
Short name T109
Test name
Test status
Simulation time 336952610000 ps
CPU time 225.85 seconds
Started Aug 27 12:05:03 AM UTC 24
Finished Aug 27 12:37:32 AM UTC 24
Peak memory 175124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3729836255 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.3729836255
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/38.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.2587640427
Short name T110
Test name
Test status
Simulation time 336862210000 ps
CPU time 226.58 seconds
Started Aug 27 12:05:07 AM UTC 24
Finished Aug 27 12:37:35 AM UTC 24
Peak memory 175128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2587640427 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.2587640427
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/39.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.2337453360
Short name T19
Test name
Test status
Simulation time 336926630000 ps
CPU time 228.66 seconds
Started Aug 27 12:04:18 AM UTC 24
Finished Aug 27 12:36:49 AM UTC 24
Peak memory 176652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2337453360 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.2337453360
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/4.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.2657403716
Short name T112
Test name
Test status
Simulation time 336903350000 ps
CPU time 226.37 seconds
Started Aug 27 12:05:08 AM UTC 24
Finished Aug 27 12:37:36 AM UTC 24
Peak memory 175128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2657403716 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.2657403716
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/40.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.1190066073
Short name T111
Test name
Test status
Simulation time 336828470000 ps
CPU time 227.61 seconds
Started Aug 27 12:05:10 AM UTC 24
Finished Aug 27 12:37:36 AM UTC 24
Peak memory 175124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1190066073 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.1190066073
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/41.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.4278755766
Short name T113
Test name
Test status
Simulation time 336751970000 ps
CPU time 228.58 seconds
Started Aug 27 12:05:12 AM UTC 24
Finished Aug 27 12:37:37 AM UTC 24
Peak memory 175124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4278755766 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.4278755766
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/42.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.654572303
Short name T114
Test name
Test status
Simulation time 336755970000 ps
CPU time 227.01 seconds
Started Aug 27 12:05:17 AM UTC 24
Finished Aug 27 12:37:41 AM UTC 24
Peak memory 175128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=654572303 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.654572303
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/43.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.2616385391
Short name T115
Test name
Test status
Simulation time 336902010000 ps
CPU time 227.16 seconds
Started Aug 27 12:05:24 AM UTC 24
Finished Aug 27 12:37:48 AM UTC 24
Peak memory 175128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2616385391 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.2616385391
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/44.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.3586912991
Short name T116
Test name
Test status
Simulation time 336453290000 ps
CPU time 224.22 seconds
Started Aug 27 12:05:42 AM UTC 24
Finished Aug 27 12:37:58 AM UTC 24
Peak memory 175128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3586912991 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.3586912991
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/45.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.2884940853
Short name T117
Test name
Test status
Simulation time 337096530000 ps
CPU time 224.35 seconds
Started Aug 27 12:06:03 AM UTC 24
Finished Aug 27 12:38:14 AM UTC 24
Peak memory 175128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2884940853 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.2884940853
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/46.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.1181713625
Short name T118
Test name
Test status
Simulation time 336943810000 ps
CPU time 225.32 seconds
Started Aug 27 12:06:29 AM UTC 24
Finished Aug 27 12:38:31 AM UTC 24
Peak memory 176648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1181713625 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.1181713625
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/47.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1027552591
Short name T119
Test name
Test status
Simulation time 336788910000 ps
CPU time 225.6 seconds
Started Aug 27 12:06:37 AM UTC 24
Finished Aug 27 12:38:36 AM UTC 24
Peak memory 175128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1027552591 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.1027552591
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/48.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.112262206
Short name T120
Test name
Test status
Simulation time 336769250000 ps
CPU time 223 seconds
Started Aug 27 12:07:26 AM UTC 24
Finished Aug 27 12:39:12 AM UTC 24
Peak memory 175132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=112262206 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.112262206
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/49.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.949841143
Short name T18
Test name
Test status
Simulation time 336451230000 ps
CPU time 229.27 seconds
Started Aug 27 12:04:19 AM UTC 24
Finished Aug 27 12:36:49 AM UTC 24
Peak memory 175124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=949841143 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.949841143
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/5.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.1534915795
Short name T20
Test name
Test status
Simulation time 336662470000 ps
CPU time 227.66 seconds
Started Aug 27 12:04:22 AM UTC 24
Finished Aug 27 12:36:53 AM UTC 24
Peak memory 175124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1534915795 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.1534915795
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/6.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.4193071804
Short name T22
Test name
Test status
Simulation time 336450650000 ps
CPU time 226.89 seconds
Started Aug 27 12:04:24 AM UTC 24
Finished Aug 27 12:36:56 AM UTC 24
Peak memory 176652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4193071804 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.4193071804
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/7.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.4078564995
Short name T81
Test name
Test status
Simulation time 336978570000 ps
CPU time 229.44 seconds
Started Aug 27 12:04:26 AM UTC 24
Finished Aug 27 12:36:58 AM UTC 24
Peak memory 176652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4078564995 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.4078564995
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/8.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.1044946108
Short name T21
Test name
Test status
Simulation time 336429050000 ps
CPU time 227.14 seconds
Started Aug 27 12:04:26 AM UTC 24
Finished Aug 27 12:36:55 AM UTC 24
Peak memory 175124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1044946108 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.1044946108
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/9.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.1763453098
Short name T25
Test name
Test status
Simulation time 1473390000 ps
CPU time 1.93 seconds
Started Aug 27 12:02:44 AM UTC 24
Finished Aug 27 12:02:56 AM UTC 24
Peak memory 177772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1763453098 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.1763453098
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/1.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.1516971071
Short name T123
Test name
Test status
Simulation time 1550870000 ps
CPU time 1.79 seconds
Started Aug 27 12:02:45 AM UTC 24
Finished Aug 27 12:02:57 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1516971071 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.1516971071
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/10.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.3149278258
Short name T121
Test name
Test status
Simulation time 1492430000 ps
CPU time 1.91 seconds
Started Aug 27 12:02:45 AM UTC 24
Finished Aug 27 12:02:57 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3149278258 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.3149278258
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/11.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.377146501
Short name T26
Test name
Test status
Simulation time 1416670000 ps
CPU time 1.9 seconds
Started Aug 27 12:02:45 AM UTC 24
Finished Aug 27 12:02:56 AM UTC 24
Peak memory 177768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=377146501 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f
ib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.377146501
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/12.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.4223240542
Short name T28
Test name
Test status
Simulation time 1429630000 ps
CPU time 1.92 seconds
Started Aug 27 12:02:45 AM UTC 24
Finished Aug 27 12:02:56 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4223240542 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.4223240542
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/13.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.2649495543
Short name T127
Test name
Test status
Simulation time 1500770000 ps
CPU time 1.96 seconds
Started Aug 27 12:02:46 AM UTC 24
Finished Aug 27 12:02:58 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649495543 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.2649495543
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/14.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.3187142726
Short name T129
Test name
Test status
Simulation time 1514810000 ps
CPU time 1.97 seconds
Started Aug 27 12:02:46 AM UTC 24
Finished Aug 27 12:02:58 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3187142726 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.3187142726
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/15.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.1671738641
Short name T131
Test name
Test status
Simulation time 1518650000 ps
CPU time 2.11 seconds
Started Aug 27 12:02:46 AM UTC 24
Finished Aug 27 12:02:58 AM UTC 24
Peak memory 177764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1671738641 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.1671738641
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/16.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.3997734305
Short name T135
Test name
Test status
Simulation time 1576310000 ps
CPU time 2.12 seconds
Started Aug 27 12:02:46 AM UTC 24
Finished Aug 27 12:02:58 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3997734305 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.3997734305
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/17.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.128525160
Short name T130
Test name
Test status
Simulation time 1503810000 ps
CPU time 2.06 seconds
Started Aug 27 12:02:46 AM UTC 24
Finished Aug 27 12:02:58 AM UTC 24
Peak memory 177708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=128525160 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f
ib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.128525160
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/18.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.1429793912
Short name T133
Test name
Test status
Simulation time 1533870000 ps
CPU time 2.09 seconds
Started Aug 27 12:02:46 AM UTC 24
Finished Aug 27 12:02:58 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1429793912 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.1429793912
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/19.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.395547306
Short name T24
Test name
Test status
Simulation time 1384470000 ps
CPU time 1.94 seconds
Started Aug 27 12:02:44 AM UTC 24
Finished Aug 27 12:02:55 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=395547306 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f
ib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.395547306
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/2.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.2826622243
Short name T132
Test name
Test status
Simulation time 1529470000 ps
CPU time 2.06 seconds
Started Aug 27 12:02:46 AM UTC 24
Finished Aug 27 12:02:58 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2826622243 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.2826622243
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/20.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.2492783212
Short name T126
Test name
Test status
Simulation time 1427830000 ps
CPU time 1.91 seconds
Started Aug 27 12:02:46 AM UTC 24
Finished Aug 27 12:02:58 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2492783212 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.2492783212
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/21.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.4074309109
Short name T128
Test name
Test status
Simulation time 1444170000 ps
CPU time 2.01 seconds
Started Aug 27 12:02:46 AM UTC 24
Finished Aug 27 12:02:58 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4074309109 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.4074309109
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/22.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.3937693953
Short name T134
Test name
Test status
Simulation time 1511810000 ps
CPU time 2.13 seconds
Started Aug 27 12:02:46 AM UTC 24
Finished Aug 27 12:02:58 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3937693953 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.3937693953
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/23.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.2988829472
Short name T139
Test name
Test status
Simulation time 1564630000 ps
CPU time 2.02 seconds
Started Aug 27 12:02:46 AM UTC 24
Finished Aug 27 12:02:59 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2988829472 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.2988829472
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/24.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.3523009336
Short name T137
Test name
Test status
Simulation time 1528190000 ps
CPU time 2.01 seconds
Started Aug 27 12:02:46 AM UTC 24
Finished Aug 27 12:02:59 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3523009336 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.3523009336
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/25.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2241466431
Short name T138
Test name
Test status
Simulation time 1421230000 ps
CPU time 2.02 seconds
Started Aug 27 12:02:47 AM UTC 24
Finished Aug 27 12:02:59 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2241466431 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.2241466431
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/26.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.880301590
Short name T140
Test name
Test status
Simulation time 1439870000 ps
CPU time 2 seconds
Started Aug 27 12:02:47 AM UTC 24
Finished Aug 27 12:02:59 AM UTC 24
Peak memory 177768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=880301590 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f
ib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.880301590
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/27.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.3614065761
Short name T125
Test name
Test status
Simulation time 1192310000 ps
CPU time 1.81 seconds
Started Aug 27 12:02:47 AM UTC 24
Finished Aug 27 12:02:57 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3614065761 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.3614065761
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/28.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.255147027
Short name T136
Test name
Test status
Simulation time 1375210000 ps
CPU time 1.95 seconds
Started Aug 27 12:02:48 AM UTC 24
Finished Aug 27 12:02:59 AM UTC 24
Peak memory 177768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=255147027 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f
ib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.255147027
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/29.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.1860393473
Short name T124
Test name
Test status
Simulation time 1594070000 ps
CPU time 1.88 seconds
Started Aug 27 12:02:44 AM UTC 24
Finished Aug 27 12:02:57 AM UTC 24
Peak memory 177772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1860393473 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.1860393473
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/3.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.4090896206
Short name T141
Test name
Test status
Simulation time 1507330000 ps
CPU time 2.08 seconds
Started Aug 27 12:02:49 AM UTC 24
Finished Aug 27 12:03:01 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4090896206 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.4090896206
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/30.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.1079858160
Short name T143
Test name
Test status
Simulation time 1545850000 ps
CPU time 2.11 seconds
Started Aug 27 12:02:50 AM UTC 24
Finished Aug 27 12:03:02 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1079858160 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.1079858160
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/31.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.2662745579
Short name T142
Test name
Test status
Simulation time 1534970000 ps
CPU time 2.19 seconds
Started Aug 27 12:02:50 AM UTC 24
Finished Aug 27 12:03:02 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2662745579 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.2662745579
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/32.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.935720015
Short name T145
Test name
Test status
Simulation time 1548790000 ps
CPU time 2.03 seconds
Started Aug 27 12:02:50 AM UTC 24
Finished Aug 27 12:03:02 AM UTC 24
Peak memory 177768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=935720015 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f
ib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.935720015
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/33.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.2961889950
Short name T146
Test name
Test status
Simulation time 1578030000 ps
CPU time 2.24 seconds
Started Aug 27 12:02:50 AM UTC 24
Finished Aug 27 12:03:02 AM UTC 24
Peak memory 177800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2961889950 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.2961889950
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/34.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.1877404579
Short name T144
Test name
Test status
Simulation time 1532130000 ps
CPU time 1.96 seconds
Started Aug 27 12:02:50 AM UTC 24
Finished Aug 27 12:03:02 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1877404579 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.1877404579
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/35.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.845304793
Short name T147
Test name
Test status
Simulation time 1570210000 ps
CPU time 2.05 seconds
Started Aug 27 12:02:50 AM UTC 24
Finished Aug 27 12:03:02 AM UTC 24
Peak memory 177768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=845304793 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f
ib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.845304793
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/36.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.589922869
Short name T150
Test name
Test status
Simulation time 1539550000 ps
CPU time 1.9 seconds
Started Aug 27 12:02:54 AM UTC 24
Finished Aug 27 12:03:06 AM UTC 24
Peak memory 177768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=589922869 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f
ib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.589922869
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/37.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.3225532320
Short name T151
Test name
Test status
Simulation time 1432030000 ps
CPU time 1.83 seconds
Started Aug 27 12:02:55 AM UTC 24
Finished Aug 27 12:03:06 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3225532320 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.3225532320
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/38.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.915436544
Short name T148
Test name
Test status
Simulation time 1081690000 ps
CPU time 1.82 seconds
Started Aug 27 12:02:55 AM UTC 24
Finished Aug 27 12:03:04 AM UTC 24
Peak memory 177768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=915436544 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f
ib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.915436544
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/39.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3839456994
Short name T6
Test name
Test status
Simulation time 1119150000 ps
CPU time 1.6 seconds
Started Aug 27 12:02:45 AM UTC 24
Finished Aug 27 12:02:54 AM UTC 24
Peak memory 177840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3839456994 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.3839456994
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/4.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.1301859674
Short name T149
Test name
Test status
Simulation time 1254550000 ps
CPU time 1.79 seconds
Started Aug 27 12:02:56 AM UTC 24
Finished Aug 27 12:03:06 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1301859674 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.1301859674
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/40.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.3682678270
Short name T160
Test name
Test status
Simulation time 1535190000 ps
CPU time 1.91 seconds
Started Aug 27 12:02:57 AM UTC 24
Finished Aug 27 12:03:08 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3682678270 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.3682678270
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/41.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.980171511
Short name T153
Test name
Test status
Simulation time 1314950000 ps
CPU time 1.77 seconds
Started Aug 27 12:02:57 AM UTC 24
Finished Aug 27 12:03:07 AM UTC 24
Peak memory 177768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=980171511 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f
ib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.980171511
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/42.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1569717457
Short name T158
Test name
Test status
Simulation time 1461630000 ps
CPU time 1.93 seconds
Started Aug 27 12:02:57 AM UTC 24
Finished Aug 27 12:03:08 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1569717457 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.1569717457
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/43.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.2689454420
Short name T155
Test name
Test status
Simulation time 1330650000 ps
CPU time 1.79 seconds
Started Aug 27 12:02:57 AM UTC 24
Finished Aug 27 12:03:07 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2689454420 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.2689454420
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/44.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.2469932300
Short name T157
Test name
Test status
Simulation time 1382690000 ps
CPU time 1.78 seconds
Started Aug 27 12:02:57 AM UTC 24
Finished Aug 27 12:03:08 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2469932300 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.2469932300
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/45.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.1140188272
Short name T159
Test name
Test status
Simulation time 1459990000 ps
CPU time 1.97 seconds
Started Aug 27 12:02:57 AM UTC 24
Finished Aug 27 12:03:08 AM UTC 24
Peak memory 177788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1140188272 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.1140188272
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/46.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.2043839636
Short name T154
Test name
Test status
Simulation time 1310730000 ps
CPU time 1.63 seconds
Started Aug 27 12:02:57 AM UTC 24
Finished Aug 27 12:03:07 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2043839636 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.2043839636
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/47.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.1997215547
Short name T152
Test name
Test status
Simulation time 1279710000 ps
CPU time 1.71 seconds
Started Aug 27 12:02:57 AM UTC 24
Finished Aug 27 12:03:07 AM UTC 24
Peak memory 177760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1997215547 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.1997215547
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/48.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.779967729
Short name T156
Test name
Test status
Simulation time 1361250000 ps
CPU time 1.85 seconds
Started Aug 27 12:02:58 AM UTC 24
Finished Aug 27 12:03:07 AM UTC 24
Peak memory 177768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779967729 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f
ib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.779967729
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/49.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.356269598
Short name T122
Test name
Test status
Simulation time 1526990000 ps
CPU time 1.99 seconds
Started Aug 27 12:02:45 AM UTC 24
Finished Aug 27 12:02:57 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=356269598 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f
ib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.356269598
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/5.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.2369977594
Short name T27
Test name
Test status
Simulation time 1433210000 ps
CPU time 1.95 seconds
Started Aug 27 12:02:45 AM UTC 24
Finished Aug 27 12:02:56 AM UTC 24
Peak memory 177772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2369977594 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.2369977594
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/6.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.1948195154
Short name T30
Test name
Test status
Simulation time 1522470000 ps
CPU time 2.01 seconds
Started Aug 27 12:02:45 AM UTC 24
Finished Aug 27 12:02:56 AM UTC 24
Peak memory 177772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1948195154 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.1948195154
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/7.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.2803636511
Short name T29
Test name
Test status
Simulation time 1501450000 ps
CPU time 1.95 seconds
Started Aug 27 12:02:45 AM UTC 24
Finished Aug 27 12:02:56 AM UTC 24
Peak memory 177772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2803636511 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.2803636511
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/8.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2104293250
Short name T8
Test name
Test status
Simulation time 1200590000 ps
CPU time 1.7 seconds
Started Aug 27 12:02:45 AM UTC 24
Finished Aug 27 12:02:55 AM UTC 24
Peak memory 177772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2104293250 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.2104293250
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/9.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.908732591
Short name T3
Test name
Test status
Simulation time 1442330000 ps
CPU time 1.83 seconds
Started Aug 27 12:03:06 AM UTC 24
Finished Aug 27 12:03:17 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=908732591 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g
al.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.908732591
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/1.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.1268729450
Short name T41
Test name
Test status
Simulation time 1380270000 ps
CPU time 1.88 seconds
Started Aug 27 12:03:08 AM UTC 24
Finished Aug 27 12:03:19 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1268729450 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.1268729450
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/10.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.1766602397
Short name T46
Test name
Test status
Simulation time 1592990000 ps
CPU time 1.94 seconds
Started Aug 27 12:03:08 AM UTC 24
Finished Aug 27 12:03:21 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1766602397 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.1766602397
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/11.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.3240981684
Short name T42
Test name
Test status
Simulation time 1209730000 ps
CPU time 1.68 seconds
Started Aug 27 12:03:09 AM UTC 24
Finished Aug 27 12:03:20 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3240981684 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.3240981684
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/12.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.430359479
Short name T63
Test name
Test status
Simulation time 1604910000 ps
CPU time 1.95 seconds
Started Aug 27 12:03:09 AM UTC 24
Finished Aug 27 12:03:22 AM UTC 24
Peak memory 177768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=430359479 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g
al.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.430359479
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/13.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.1404688146
Short name T48
Test name
Test status
Simulation time 1380970000 ps
CPU time 1.83 seconds
Started Aug 27 12:03:09 AM UTC 24
Finished Aug 27 12:03:21 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1404688146 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.1404688146
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/14.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.3754019942
Short name T51
Test name
Test status
Simulation time 1474530000 ps
CPU time 1.81 seconds
Started Aug 27 12:03:10 AM UTC 24
Finished Aug 27 12:03:21 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3754019942 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.3754019942
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/15.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.3130513453
Short name T61
Test name
Test status
Simulation time 1555190000 ps
CPU time 2.07 seconds
Started Aug 27 12:03:10 AM UTC 24
Finished Aug 27 12:03:22 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3130513453 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.3130513453
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/16.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.379235433
Short name T50
Test name
Test status
Simulation time 1440390000 ps
CPU time 1.78 seconds
Started Aug 27 12:03:10 AM UTC 24
Finished Aug 27 12:03:21 AM UTC 24
Peak memory 177768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=379235433 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g
al.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.379235433
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/17.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.692275807
Short name T49
Test name
Test status
Simulation time 1416050000 ps
CPU time 1.81 seconds
Started Aug 27 12:03:10 AM UTC 24
Finished Aug 27 12:03:21 AM UTC 24
Peak memory 177768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=692275807 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g
al.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.692275807
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/18.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.3908768937
Short name T52
Test name
Test status
Simulation time 1464790000 ps
CPU time 1.73 seconds
Started Aug 27 12:03:10 AM UTC 24
Finished Aug 27 12:03:21 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3908768937 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.3908768937
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/19.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.1931940404
Short name T2
Test name
Test status
Simulation time 1423810000 ps
CPU time 1.81 seconds
Started Aug 27 12:03:06 AM UTC 24
Finished Aug 27 12:03:17 AM UTC 24
Peak memory 177772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1931940404 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.1931940404
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/2.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.1973360255
Short name T47
Test name
Test status
Simulation time 1338690000 ps
CPU time 1.81 seconds
Started Aug 27 12:03:10 AM UTC 24
Finished Aug 27 12:03:21 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1973360255 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.1973360255
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/20.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.89785593
Short name T59
Test name
Test status
Simulation time 1502170000 ps
CPU time 1.8 seconds
Started Aug 27 12:03:10 AM UTC 24
Finished Aug 27 12:03:22 AM UTC 24
Peak memory 177772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=89785593 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ga
l.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.89785593
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/21.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.3027506448
Short name T57
Test name
Test status
Simulation time 1467610000 ps
CPU time 1.93 seconds
Started Aug 27 12:03:10 AM UTC 24
Finished Aug 27 12:03:22 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3027506448 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.3027506448
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/22.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.401429532
Short name T53
Test name
Test status
Simulation time 1463770000 ps
CPU time 1.79 seconds
Started Aug 27 12:03:10 AM UTC 24
Finished Aug 27 12:03:21 AM UTC 24
Peak memory 177768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=401429532 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g
al.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.401429532
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/23.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.2731789141
Short name T58
Test name
Test status
Simulation time 1485830000 ps
CPU time 1.83 seconds
Started Aug 27 12:03:10 AM UTC 24
Finished Aug 27 12:03:22 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2731789141 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.2731789141
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/24.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.2751897356
Short name T55
Test name
Test status
Simulation time 1448310000 ps
CPU time 1.83 seconds
Started Aug 27 12:03:10 AM UTC 24
Finished Aug 27 12:03:22 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2751897356 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.2751897356
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/25.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.2401948967
Short name T56
Test name
Test status
Simulation time 1413250000 ps
CPU time 1.8 seconds
Started Aug 27 12:03:10 AM UTC 24
Finished Aug 27 12:03:22 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2401948967 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.2401948967
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/26.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.3740324524
Short name T54
Test name
Test status
Simulation time 1403850000 ps
CPU time 1.91 seconds
Started Aug 27 12:03:10 AM UTC 24
Finished Aug 27 12:03:22 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3740324524 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.3740324524
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/27.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.3227711224
Short name T45
Test name
Test status
Simulation time 1253490000 ps
CPU time 1.78 seconds
Started Aug 27 12:03:10 AM UTC 24
Finished Aug 27 12:03:20 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3227711224 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.3227711224
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/28.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.540003890
Short name T62
Test name
Test status
Simulation time 1534850000 ps
CPU time 1.76 seconds
Started Aug 27 12:03:10 AM UTC 24
Finished Aug 27 12:03:22 AM UTC 24
Peak memory 177768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=540003890 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g
al.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.540003890
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/29.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.3238174615
Short name T10
Test name
Test status
Simulation time 1506170000 ps
CPU time 1.83 seconds
Started Aug 27 12:03:06 AM UTC 24
Finished Aug 27 12:03:18 AM UTC 24
Peak memory 177772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3238174615 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.3238174615
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/3.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.495941504
Short name T43
Test name
Test status
Simulation time 1121390000 ps
CPU time 1.62 seconds
Started Aug 27 12:03:10 AM UTC 24
Finished Aug 27 12:03:20 AM UTC 24
Peak memory 177768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=495941504 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g
al.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.495941504
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/30.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.1903325437
Short name T44
Test name
Test status
Simulation time 1178750000 ps
CPU time 1.68 seconds
Started Aug 27 12:03:10 AM UTC 24
Finished Aug 27 12:03:20 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1903325437 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.1903325437
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/31.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.431372730
Short name T67
Test name
Test status
Simulation time 1514630000 ps
CPU time 2.02 seconds
Started Aug 27 12:03:11 AM UTC 24
Finished Aug 27 12:03:23 AM UTC 24
Peak memory 177768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=431372730 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g
al.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.431372730
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/32.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.3245420462
Short name T65
Test name
Test status
Simulation time 1496890000 ps
CPU time 2.01 seconds
Started Aug 27 12:03:11 AM UTC 24
Finished Aug 27 12:03:23 AM UTC 24
Peak memory 178516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3245420462 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.3245420462
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/33.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.3413880649
Short name T66
Test name
Test status
Simulation time 1487030000 ps
CPU time 1.89 seconds
Started Aug 27 12:03:11 AM UTC 24
Finished Aug 27 12:03:23 AM UTC 24
Peak memory 178832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3413880649 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.3413880649
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/34.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.37107627
Short name T68
Test name
Test status
Simulation time 1559990000 ps
CPU time 1.84 seconds
Started Aug 27 12:03:11 AM UTC 24
Finished Aug 27 12:03:23 AM UTC 24
Peak memory 177772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37107627 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ga
l.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.37107627
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/35.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.1088677089
Short name T69
Test name
Test status
Simulation time 1562550000 ps
CPU time 1.99 seconds
Started Aug 27 12:03:11 AM UTC 24
Finished Aug 27 12:03:23 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1088677089 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.1088677089
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/36.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.3000062389
Short name T70
Test name
Test status
Simulation time 1571210000 ps
CPU time 1.95 seconds
Started Aug 27 12:03:11 AM UTC 24
Finished Aug 27 12:03:24 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3000062389 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.3000062389
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/37.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.3921841220
Short name T60
Test name
Test status
Simulation time 1339390000 ps
CPU time 1.7 seconds
Started Aug 27 12:03:11 AM UTC 24
Finished Aug 27 12:03:22 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3921841220 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.3921841220
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/38.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.2696172109
Short name T64
Test name
Test status
Simulation time 1393290000 ps
CPU time 1.83 seconds
Started Aug 27 12:03:11 AM UTC 24
Finished Aug 27 12:03:22 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2696172109 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.2696172109
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/39.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.3668575770
Short name T11
Test name
Test status
Simulation time 1559670000 ps
CPU time 2 seconds
Started Aug 27 12:03:06 AM UTC 24
Finished Aug 27 12:03:18 AM UTC 24
Peak memory 177772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3668575770 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.3668575770
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/4.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.3508373459
Short name T71
Test name
Test status
Simulation time 1156510000 ps
CPU time 1.77 seconds
Started Aug 27 12:03:15 AM UTC 24
Finished Aug 27 12:03:25 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3508373459 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.3508373459
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/40.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.1075218451
Short name T74
Test name
Test status
Simulation time 1441250000 ps
CPU time 1.95 seconds
Started Aug 27 12:03:17 AM UTC 24
Finished Aug 27 12:03:27 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1075218451 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.1075218451
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/41.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.1012361175
Short name T73
Test name
Test status
Simulation time 1123290000 ps
CPU time 1.72 seconds
Started Aug 27 12:03:18 AM UTC 24
Finished Aug 27 12:03:26 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1012361175 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.1012361175
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/42.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.2877367277
Short name T76
Test name
Test status
Simulation time 1345410000 ps
CPU time 1.81 seconds
Started Aug 27 12:03:18 AM UTC 24
Finished Aug 27 12:03:27 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2877367277 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.2877367277
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/43.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.930096269
Short name T77
Test name
Test status
Simulation time 1467950000 ps
CPU time 1.82 seconds
Started Aug 27 12:03:18 AM UTC 24
Finished Aug 27 12:03:28 AM UTC 24
Peak memory 177768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=930096269 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g
al.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.930096269
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/44.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.3655119317
Short name T72
Test name
Test status
Simulation time 1098310000 ps
CPU time 1.61 seconds
Started Aug 27 12:03:18 AM UTC 24
Finished Aug 27 12:03:26 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3655119317 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.3655119317
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/45.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.2226851301
Short name T75
Test name
Test status
Simulation time 1322370000 ps
CPU time 1.77 seconds
Started Aug 27 12:03:18 AM UTC 24
Finished Aug 27 12:03:27 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226851301 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.2226851301
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/46.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.2753143004
Short name T78
Test name
Test status
Simulation time 1446710000 ps
CPU time 1.82 seconds
Started Aug 27 12:03:19 AM UTC 24
Finished Aug 27 12:03:29 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2753143004 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.2753143004
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/47.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.3695220008
Short name T80
Test name
Test status
Simulation time 1549090000 ps
CPU time 1.81 seconds
Started Aug 27 12:03:19 AM UTC 24
Finished Aug 27 12:03:29 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3695220008 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.3695220008
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/48.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.368710348
Short name T79
Test name
Test status
Simulation time 1527070000 ps
CPU time 1.92 seconds
Started Aug 27 12:03:19 AM UTC 24
Finished Aug 27 12:03:29 AM UTC 24
Peak memory 177768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=368710348 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g
al.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.368710348
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/49.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.3655478788
Short name T1
Test name
Test status
Simulation time 1303110000 ps
CPU time 1.6 seconds
Started Aug 27 12:03:06 AM UTC 24
Finished Aug 27 12:03:16 AM UTC 24
Peak memory 177756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3655478788 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.3655478788
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/5.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.94787269
Short name T12
Test name
Test status
Simulation time 1556430000 ps
CPU time 2.01 seconds
Started Aug 27 12:03:06 AM UTC 24
Finished Aug 27 12:03:18 AM UTC 24
Peak memory 177700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=94787269 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ga
l.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.94787269
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/6.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.3876904273
Short name T13
Test name
Test status
Simulation time 1556930000 ps
CPU time 1.75 seconds
Started Aug 27 12:03:06 AM UTC 24
Finished Aug 27 12:03:18 AM UTC 24
Peak memory 177772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3876904273 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.3876904273
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/7.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.1673165859
Short name T4
Test name
Test status
Simulation time 1467730000 ps
CPU time 1.9 seconds
Started Aug 27 12:03:06 AM UTC 24
Finished Aug 27 12:03:17 AM UTC 24
Peak memory 177772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1673165859 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.1673165859
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/8.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.2512189011
Short name T9
Test name
Test status
Simulation time 1428950000 ps
CPU time 1.77 seconds
Started Aug 27 12:03:06 AM UTC 24
Finished Aug 27 12:03:17 AM UTC 24
Peak memory 177772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2512189011 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.2512189011
Directory /workspaces/repo/scratch/os_regression_2024_08_26/prim_lfsr-sim-vcs/9.prim_lfsr_gal_smoke/latest
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