Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.31 100.00 96.55 100.00 100.00 95.00


Total tests in report: 200
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
87.31 87.31 100.00 100.00 96.55 96.55 100.00 100.00 100.00 100.00 40.00 40.00 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.3097838205
95.31 8.00 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 80.00 40.00 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.875939969
96.81 1.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 87.50 7.50 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.2617345179
98.31 1.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 95.00 7.50 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.3848111113


Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.3503313546
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.73736719
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.1017145923
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.2114776802
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.4198803736
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.891110257
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.2607960612
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.904675238
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.1967307082
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.1481980243
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2793881353
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.694802309
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.2188354149
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.3729920146
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.787320031
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.720402264
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.1457597257
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.3574259697
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1798352814
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.178627153
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.3750133669
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.934370619
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.4046899283
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3718585209
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.2516201155
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.2832866311
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.367395030
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.830239633
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.3637690838
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.2911973483
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.3355087979
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.4107897845
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.3942781103
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.2870608597
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.1550595759
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.340601700
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.565398903
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.3785007852
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.3923663393
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.2781642926
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.3350518222
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.1439138211
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.3772202969
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.1911698234
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.263204173
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.4057187442
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.2839199579
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.2663748137
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.2986427147
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.237285187
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.2694076741
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.3258774823
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.1181332594
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.1700265504
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.43326567
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.879556490
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.4266742793
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.97516848
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.1017011111
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.1408196546
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.1288983033
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.2371517832
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.4031526978
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.2391331935
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.1922635109
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.4291251239
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.1881795032
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.179298834
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.357684860
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.3169342428
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.2398469349
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.305219234
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.2158577565
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.3459749390
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.3643183578
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.2759120558
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.2092201269
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.405333766
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.673086863
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.606514730
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.2281210254
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.1757770662
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.4033150542
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.1878227490
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.2358648542
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.2294835642
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.2144896777
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.2225932262
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.1785016045
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.1129210737
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.1964695950
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.3706273355
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.1261110027
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.3965343892
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.2228825039
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.2389661000
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.904161381
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.297086531
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.623110563
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/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.1291085778
/workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.2416320179




Total test records in report: 200
tests.html | tests1.html | tests2.html | tests3.html

TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.3097838205 Sep 04 08:38:41 AM UTC 24 Sep 04 08:38:52 AM UTC 24 1349990000 ps
T2 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.3143929909 Sep 04 08:38:41 AM UTC 24 Sep 04 08:38:52 AM UTC 24 1462390000 ps
T3 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.4235469520 Sep 04 08:38:41 AM UTC 24 Sep 04 08:38:53 AM UTC 24 1566810000 ps
T7 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.1291085778 Sep 04 08:38:42 AM UTC 24 Sep 04 08:38:53 AM UTC 24 1355970000 ps
T8 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.1596554360 Sep 04 08:38:42 AM UTC 24 Sep 04 08:38:53 AM UTC 24 1412050000 ps
T9 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.3495571122 Sep 04 08:38:42 AM UTC 24 Sep 04 08:38:53 AM UTC 24 1390250000 ps
T10 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.2416320179 Sep 04 08:38:42 AM UTC 24 Sep 04 08:38:54 AM UTC 24 1472110000 ps
T11 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.1815826901 Sep 04 08:38:42 AM UTC 24 Sep 04 08:38:54 AM UTC 24 1531770000 ps
T12 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.150458493 Sep 04 08:38:42 AM UTC 24 Sep 04 08:38:54 AM UTC 24 1553490000 ps
T13 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.2790316008 Sep 04 08:38:42 AM UTC 24 Sep 04 08:38:55 AM UTC 24 1568590000 ps
T41 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.1579068642 Sep 04 08:38:43 AM UTC 24 Sep 04 08:38:55 AM UTC 24 1352890000 ps
T42 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.3287868150 Sep 04 08:38:43 AM UTC 24 Sep 04 08:38:55 AM UTC 24 1364450000 ps
T43 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.166745138 Sep 04 08:38:42 AM UTC 24 Sep 04 08:38:55 AM UTC 24 1556050000 ps
T44 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.2309939044 Sep 04 08:38:45 AM UTC 24 Sep 04 08:38:55 AM UTC 24 1262830000 ps
T45 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.410394062 Sep 04 08:38:45 AM UTC 24 Sep 04 08:38:55 AM UTC 24 1269250000 ps
T46 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.268280347 Sep 04 08:38:43 AM UTC 24 Sep 04 08:38:55 AM UTC 24 1503730000 ps
T47 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.3713327150 Sep 04 08:38:43 AM UTC 24 Sep 04 08:38:55 AM UTC 24 1492110000 ps
T48 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.3898283510 Sep 04 08:38:43 AM UTC 24 Sep 04 08:38:56 AM UTC 24 1492890000 ps
T49 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.98369619 Sep 04 08:38:43 AM UTC 24 Sep 04 08:38:56 AM UTC 24 1544150000 ps
T50 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.3072374425 Sep 04 08:38:44 AM UTC 24 Sep 04 08:38:56 AM UTC 24 1545970000 ps
T51 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.1048894062 Sep 04 08:38:45 AM UTC 24 Sep 04 08:38:56 AM UTC 24 1400050000 ps
T52 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.2389126513 Sep 04 08:38:45 AM UTC 24 Sep 04 08:38:56 AM UTC 24 1485430000 ps
T53 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.1786779087 Sep 04 08:38:45 AM UTC 24 Sep 04 08:38:57 AM UTC 24 1483990000 ps
T54 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.106829597 Sep 04 08:38:46 AM UTC 24 Sep 04 08:38:58 AM UTC 24 1542350000 ps
T55 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.3857766089 Sep 04 08:38:51 AM UTC 24 Sep 04 08:39:00 AM UTC 24 1080130000 ps
T56 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.3085449656 Sep 04 08:38:48 AM UTC 24 Sep 04 08:39:00 AM UTC 24 1597570000 ps
T57 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.1748120042 Sep 04 08:38:50 AM UTC 24 Sep 04 08:39:03 AM UTC 24 1615570000 ps
T58 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.1398307543 Sep 04 08:38:52 AM UTC 24 Sep 04 08:39:03 AM UTC 24 1391750000 ps
T59 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.1626015840 Sep 04 08:38:52 AM UTC 24 Sep 04 08:39:04 AM UTC 24 1567650000 ps
T60 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.3593286864 Sep 04 08:38:53 AM UTC 24 Sep 04 08:39:05 AM UTC 24 1472230000 ps
T61 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.3124992998 Sep 04 08:38:54 AM UTC 24 Sep 04 08:39:05 AM UTC 24 1387910000 ps
T62 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.1828489035 Sep 04 08:38:54 AM UTC 24 Sep 04 08:39:06 AM UTC 24 1448190000 ps
T63 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.3079378057 Sep 04 08:38:54 AM UTC 24 Sep 04 08:39:07 AM UTC 24 1544950000 ps
T64 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.3908352988 Sep 04 08:38:54 AM UTC 24 Sep 04 08:39:07 AM UTC 24 1559310000 ps
T65 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.605032063 Sep 04 08:38:54 AM UTC 24 Sep 04 08:39:07 AM UTC 24 1560730000 ps
T66 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.1602947297 Sep 04 08:38:55 AM UTC 24 Sep 04 08:39:07 AM UTC 24 1442950000 ps
T67 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.2592236338 Sep 04 08:38:56 AM UTC 24 Sep 04 08:39:07 AM UTC 24 1428490000 ps
T68 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.3969530125 Sep 04 08:38:56 AM UTC 24 Sep 04 08:39:07 AM UTC 24 1431310000 ps
T69 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.3856122035 Sep 04 08:38:55 AM UTC 24 Sep 04 08:39:07 AM UTC 24 1463650000 ps
T70 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.4026544375 Sep 04 08:38:56 AM UTC 24 Sep 04 08:39:07 AM UTC 24 1439390000 ps
T71 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.4046722586 Sep 04 08:38:56 AM UTC 24 Sep 04 08:39:08 AM UTC 24 1530170000 ps
T72 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.2310268012 Sep 04 08:38:56 AM UTC 24 Sep 04 08:39:08 AM UTC 24 1527830000 ps
T73 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.1621062527 Sep 04 08:38:56 AM UTC 24 Sep 04 08:39:08 AM UTC 24 1535850000 ps
T74 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.3297690010 Sep 04 08:38:55 AM UTC 24 Sep 04 08:39:08 AM UTC 24 1571950000 ps
T75 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.515585626 Sep 04 08:38:57 AM UTC 24 Sep 04 08:39:09 AM UTC 24 1498570000 ps
T76 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.1793113814 Sep 04 08:38:57 AM UTC 24 Sep 04 08:39:09 AM UTC 24 1484330000 ps
T77 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.1441212124 Sep 04 08:38:57 AM UTC 24 Sep 04 08:39:09 AM UTC 24 1507770000 ps
T78 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.1565417415 Sep 04 08:38:57 AM UTC 24 Sep 04 08:39:09 AM UTC 24 1529830000 ps
T79 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.3609001569 Sep 04 08:38:57 AM UTC 24 Sep 04 08:39:09 AM UTC 24 1548690000 ps
T80 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.3331238435 Sep 04 08:38:57 AM UTC 24 Sep 04 08:39:09 AM UTC 24 1555850000 ps
T14 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.1288983033 Sep 04 11:02:43 AM UTC 24 Sep 04 11:36:20 AM UTC 24 336534230000 ps
T15 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.2228825039 Sep 04 11:02:43 AM UTC 24 Sep 04 11:36:20 AM UTC 24 336378470000 ps
T16 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.297086531 Sep 04 11:02:43 AM UTC 24 Sep 04 11:36:21 AM UTC 24 336773690000 ps
T17 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.4033150542 Sep 04 11:02:43 AM UTC 24 Sep 04 11:36:21 AM UTC 24 336562850000 ps
T18 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.305219234 Sep 04 11:02:43 AM UTC 24 Sep 04 11:36:21 AM UTC 24 336496190000 ps
T19 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.904161381 Sep 04 11:02:43 AM UTC 24 Sep 04 11:36:21 AM UTC 24 336501370000 ps
T20 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.875939969 Sep 04 11:02:43 AM UTC 24 Sep 04 11:36:21 AM UTC 24 336776310000 ps
T21 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.1181332594 Sep 04 11:02:44 AM UTC 24 Sep 04 11:36:22 AM UTC 24 336453250000 ps
T22 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.2694076741 Sep 04 11:02:43 AM UTC 24 Sep 04 11:36:22 AM UTC 24 336714410000 ps
T23 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.2389661000 Sep 04 11:02:43 AM UTC 24 Sep 04 11:36:22 AM UTC 24 336751570000 ps
T81 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.879556490 Sep 04 11:02:45 AM UTC 24 Sep 04 11:36:22 AM UTC 24 336492370000 ps
T82 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.3965343892 Sep 04 11:02:43 AM UTC 24 Sep 04 11:36:23 AM UTC 24 336786330000 ps
T83 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.1700265504 Sep 04 11:02:45 AM UTC 24 Sep 04 11:36:23 AM UTC 24 336750630000 ps
T84 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.4266742793 Sep 04 11:02:46 AM UTC 24 Sep 04 11:36:23 AM UTC 24 336737750000 ps
T85 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.3258774823 Sep 04 11:02:43 AM UTC 24 Sep 04 11:36:23 AM UTC 24 337007250000 ps
T86 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.237285187 Sep 04 11:02:43 AM UTC 24 Sep 04 11:36:24 AM UTC 24 337111370000 ps
T87 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.43326567 Sep 04 11:02:45 AM UTC 24 Sep 04 11:36:25 AM UTC 24 336998930000 ps
T88 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.1017011111 Sep 04 11:02:53 AM UTC 24 Sep 04 11:36:32 AM UTC 24 336602950000 ps
T89 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.97516848 Sep 04 11:02:52 AM UTC 24 Sep 04 11:36:33 AM UTC 24 336728010000 ps
T90 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.4031526978 Sep 04 11:02:55 AM UTC 24 Sep 04 11:36:35 AM UTC 24 336552610000 ps
T91 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.2371517832 Sep 04 11:02:55 AM UTC 24 Sep 04 11:36:35 AM UTC 24 336611270000 ps
T92 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.2391331935 Sep 04 11:02:55 AM UTC 24 Sep 04 11:36:36 AM UTC 24 336697010000 ps
T93 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.1408196546 Sep 04 11:02:55 AM UTC 24 Sep 04 11:36:37 AM UTC 24 336899810000 ps
T94 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.4291251239 Sep 04 11:03:04 AM UTC 24 Sep 04 11:36:49 AM UTC 24 336682990000 ps
T95 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.179298834 Sep 04 11:03:04 AM UTC 24 Sep 04 11:36:49 AM UTC 24 336447030000 ps
T96 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.2158577565 Sep 04 11:03:05 AM UTC 24 Sep 04 11:36:50 AM UTC 24 336663350000 ps
T97 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.1922635109 Sep 04 11:03:04 AM UTC 24 Sep 04 11:36:50 AM UTC 24 336693970000 ps
T98 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.3459749390 Sep 04 11:03:05 AM UTC 24 Sep 04 11:36:51 AM UTC 24 336361050000 ps
T99 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.2759120558 Sep 04 11:03:07 AM UTC 24 Sep 04 11:36:51 AM UTC 24 336312470000 ps
T100 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.3643183578 Sep 04 11:03:05 AM UTC 24 Sep 04 11:36:51 AM UTC 24 336614530000 ps
T101 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.673086863 Sep 04 11:03:07 AM UTC 24 Sep 04 11:36:51 AM UTC 24 336591430000 ps
T102 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.2398469349 Sep 04 11:03:05 AM UTC 24 Sep 04 11:36:52 AM UTC 24 336804170000 ps
T103 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.2281210254 Sep 04 11:03:07 AM UTC 24 Sep 04 11:36:52 AM UTC 24 336580270000 ps
T104 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.1881795032 Sep 04 11:03:04 AM UTC 24 Sep 04 11:36:53 AM UTC 24 337009850000 ps
T105 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.405333766 Sep 04 11:03:07 AM UTC 24 Sep 04 11:36:53 AM UTC 24 336674650000 ps
T106 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.3169342428 Sep 04 11:03:05 AM UTC 24 Sep 04 11:36:53 AM UTC 24 336942970000 ps
T107 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.1757770662 Sep 04 11:03:07 AM UTC 24 Sep 04 11:36:53 AM UTC 24 336892970000 ps
T108 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.606514730 Sep 04 11:03:07 AM UTC 24 Sep 04 11:36:53 AM UTC 24 336598090000 ps
T109 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.1261110027 Sep 04 11:03:08 AM UTC 24 Sep 04 11:36:53 AM UTC 24 336573130000 ps
T110 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.2294835642 Sep 04 11:03:08 AM UTC 24 Sep 04 11:36:54 AM UTC 24 336423050000 ps
T111 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.1878227490 Sep 04 11:03:07 AM UTC 24 Sep 04 11:36:54 AM UTC 24 336908830000 ps
T112 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.357684860 Sep 04 11:03:05 AM UTC 24 Sep 04 11:36:54 AM UTC 24 337035870000 ps
T113 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.2358648542 Sep 04 11:03:07 AM UTC 24 Sep 04 11:36:54 AM UTC 24 336878630000 ps
T114 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.2092201269 Sep 04 11:03:07 AM UTC 24 Sep 04 11:36:55 AM UTC 24 336837190000 ps
T115 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.1785016045 Sep 04 11:03:08 AM UTC 24 Sep 04 11:36:55 AM UTC 24 336611610000 ps
T116 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.2144896777 Sep 04 11:03:08 AM UTC 24 Sep 04 11:36:56 AM UTC 24 336993030000 ps
T117 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.1964695950 Sep 04 11:03:08 AM UTC 24 Sep 04 11:36:57 AM UTC 24 336783210000 ps
T118 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.2225932262 Sep 04 11:03:08 AM UTC 24 Sep 04 11:36:57 AM UTC 24 336667570000 ps
T119 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.1129210737 Sep 04 11:03:08 AM UTC 24 Sep 04 11:36:57 AM UTC 24 337062750000 ps
T120 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.3706273355 Sep 04 11:03:08 AM UTC 24 Sep 04 11:36:57 AM UTC 24 336964550000 ps
T4 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3414752325 Sep 04 10:05:40 AM UTC 24 Sep 04 10:05:49 AM UTC 24 1182450000 ps
T5 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.3848111113 Sep 04 10:05:39 AM UTC 24 Sep 04 10:05:50 AM UTC 24 1484870000 ps
T6 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.623110563 Sep 04 10:05:40 AM UTC 24 Sep 04 10:05:50 AM UTC 24 1371770000 ps
T24 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.2827104646 Sep 04 10:05:40 AM UTC 24 Sep 04 10:05:51 AM UTC 24 1425130000 ps
T25 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.3249062509 Sep 04 10:05:40 AM UTC 24 Sep 04 10:05:52 AM UTC 24 1564070000 ps
T26 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.1702424689 Sep 04 10:05:40 AM UTC 24 Sep 04 10:05:52 AM UTC 24 1579710000 ps
T27 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.1774940483 Sep 04 10:05:41 AM UTC 24 Sep 04 10:05:52 AM UTC 24 1398230000 ps
T28 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.1130263312 Sep 04 10:05:41 AM UTC 24 Sep 04 10:05:52 AM UTC 24 1458170000 ps
T29 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2586371464 Sep 04 10:05:42 AM UTC 24 Sep 04 10:05:53 AM UTC 24 1559330000 ps
T30 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.561296386 Sep 04 10:05:43 AM UTC 24 Sep 04 10:05:54 AM UTC 24 1438470000 ps
T121 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.3797894301 Sep 04 10:05:42 AM UTC 24 Sep 04 10:05:54 AM UTC 24 1673990000 ps
T122 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.894195251 Sep 04 10:05:43 AM UTC 24 Sep 04 10:05:54 AM UTC 24 1514390000 ps
T123 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.1089540917 Sep 04 10:05:44 AM UTC 24 Sep 04 10:05:55 AM UTC 24 1465890000 ps
T124 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.3223174051 Sep 04 10:05:45 AM UTC 24 Sep 04 10:05:56 AM UTC 24 1493270000 ps
T125 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.2579130211 Sep 04 10:05:45 AM UTC 24 Sep 04 10:05:57 AM UTC 24 1583710000 ps
T126 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.87698763 Sep 04 10:05:46 AM UTC 24 Sep 04 10:05:57 AM UTC 24 1540010000 ps
T127 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.1483638383 Sep 04 10:05:47 AM UTC 24 Sep 04 10:05:57 AM UTC 24 1341310000 ps
T128 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.4272671334 Sep 04 10:05:47 AM UTC 24 Sep 04 10:05:58 AM UTC 24 1495310000 ps
T129 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.417462962 Sep 04 10:05:48 AM UTC 24 Sep 04 10:06:00 AM UTC 24 1506850000 ps
T130 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.2457999366 Sep 04 10:05:49 AM UTC 24 Sep 04 10:06:00 AM UTC 24 1500190000 ps
T131 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.3807627591 Sep 04 10:05:48 AM UTC 24 Sep 04 10:06:00 AM UTC 24 1525910000 ps
T132 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.2794861583 Sep 04 10:05:50 AM UTC 24 Sep 04 10:06:00 AM UTC 24 1404730000 ps
T133 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3539871290 Sep 04 10:05:50 AM UTC 24 Sep 04 10:06:01 AM UTC 24 1506970000 ps
T134 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.1922552310 Sep 04 10:05:50 AM UTC 24 Sep 04 10:06:01 AM UTC 24 1496850000 ps
T135 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.2322890055 Sep 04 10:05:51 AM UTC 24 Sep 04 10:06:01 AM UTC 24 1350310000 ps
T136 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.929949223 Sep 04 10:05:51 AM UTC 24 Sep 04 10:06:01 AM UTC 24 1400770000 ps
T137 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.4251912726 Sep 04 10:05:51 AM UTC 24 Sep 04 10:06:02 AM UTC 24 1452850000 ps
T138 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.2687772180 Sep 04 10:05:51 AM UTC 24 Sep 04 10:06:02 AM UTC 24 1537970000 ps
T139 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.2637576123 Sep 04 10:05:52 AM UTC 24 Sep 04 10:06:02 AM UTC 24 1394010000 ps
T140 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.2275847900 Sep 04 10:05:52 AM UTC 24 Sep 04 10:06:02 AM UTC 24 1386610000 ps
T141 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.970630674 Sep 04 10:05:52 AM UTC 24 Sep 04 10:06:03 AM UTC 24 1382330000 ps
T142 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.745615217 Sep 04 10:05:52 AM UTC 24 Sep 04 10:06:03 AM UTC 24 1424310000 ps
T143 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.888081297 Sep 04 10:05:52 AM UTC 24 Sep 04 10:06:03 AM UTC 24 1511570000 ps
T144 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.2701288496 Sep 04 10:05:52 AM UTC 24 Sep 04 10:06:03 AM UTC 24 1512370000 ps
T145 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1256889400 Sep 04 10:05:53 AM UTC 24 Sep 04 10:06:04 AM UTC 24 1448430000 ps
T146 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.1526017189 Sep 04 10:05:53 AM UTC 24 Sep 04 10:06:04 AM UTC 24 1478510000 ps
T147 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.2548760668 Sep 04 10:05:53 AM UTC 24 Sep 04 10:06:04 AM UTC 24 1501910000 ps
T148 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.3575421457 Sep 04 10:05:53 AM UTC 24 Sep 04 10:06:05 AM UTC 24 1505190000 ps
T149 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.906772949 Sep 04 10:05:53 AM UTC 24 Sep 04 10:06:05 AM UTC 24 1535950000 ps
T150 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.1330244302 Sep 04 10:05:55 AM UTC 24 Sep 04 10:06:05 AM UTC 24 1452970000 ps
T151 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.3554826890 Sep 04 10:05:55 AM UTC 24 Sep 04 10:06:05 AM UTC 24 1469670000 ps
T152 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.2311577690 Sep 04 10:05:55 AM UTC 24 Sep 04 10:06:05 AM UTC 24 1472850000 ps
T153 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.17040902 Sep 04 10:05:55 AM UTC 24 Sep 04 10:06:05 AM UTC 24 1487610000 ps
T154 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1483834442 Sep 04 10:05:56 AM UTC 24 Sep 04 10:06:06 AM UTC 24 1360370000 ps
T155 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.2451151895 Sep 04 10:05:57 AM UTC 24 Sep 04 10:06:07 AM UTC 24 1445530000 ps
T156 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.354302124 Sep 04 10:05:58 AM UTC 24 Sep 04 10:06:08 AM UTC 24 1372030000 ps
T157 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.1900665619 Sep 04 10:05:58 AM UTC 24 Sep 04 10:06:08 AM UTC 24 1459650000 ps
T158 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.3296652213 Sep 04 10:05:58 AM UTC 24 Sep 04 10:06:09 AM UTC 24 1550210000 ps
T159 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.1326594647 Sep 04 10:05:58 AM UTC 24 Sep 04 10:06:09 AM UTC 24 1552750000 ps
T160 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.1204657018 Sep 04 10:05:58 AM UTC 24 Sep 04 10:06:09 AM UTC 24 1575650000 ps
T31 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.2617345179 Sep 04 11:56:52 AM UTC 24 Sep 04 12:32:31 PM UTC 24 336569170000 ps
T32 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.3503313546 Sep 04 11:56:55 AM UTC 24 Sep 04 12:32:32 PM UTC 24 336569770000 ps
T33 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.263204173 Sep 04 11:57:15 AM UTC 24 Sep 04 12:32:43 PM UTC 24 336357870000 ps
T34 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.694802309 Sep 04 11:57:12 AM UTC 24 Sep 04 12:32:44 PM UTC 24 336713010000 ps
T35 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.4057187442 Sep 04 11:57:15 AM UTC 24 Sep 04 12:32:46 PM UTC 24 336839090000 ps
T36 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.4046899283 Sep 04 11:57:14 AM UTC 24 Sep 04 12:32:46 PM UTC 24 336947730000 ps
T37 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.2870608597 Sep 04 11:57:15 AM UTC 24 Sep 04 12:32:46 PM UTC 24 336932270000 ps
T38 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.2839199579 Sep 04 11:57:30 AM UTC 24 Sep 04 12:32:56 PM UTC 24 336509410000 ps
T39 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.2663748137 Sep 04 11:57:37 AM UTC 24 Sep 04 12:33:00 PM UTC 24 336421350000 ps
T40 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.2986427147 Sep 04 11:57:50 AM UTC 24 Sep 04 12:33:12 PM UTC 24 337091490000 ps
T161 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.73736719 Sep 04 11:57:53 AM UTC 24 Sep 04 12:33:13 PM UTC 24 336929110000 ps
T162 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.1017145923 Sep 04 11:58:25 AM UTC 24 Sep 04 12:33:40 PM UTC 24 337137950000 ps
T163 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.2114776802 Sep 04 11:58:25 AM UTC 24 Sep 04 12:33:40 PM UTC 24 337010030000 ps
T164 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.4198803736 Sep 04 11:58:27 AM UTC 24 Sep 04 12:33:41 PM UTC 24 336824970000 ps
T165 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.2607960612 Sep 04 11:58:40 AM UTC 24 Sep 04 12:33:50 PM UTC 24 336535110000 ps
T166 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.891110257 Sep 04 11:58:40 AM UTC 24 Sep 04 12:33:52 PM UTC 24 336761230000 ps
T167 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.904675238 Sep 04 11:58:51 AM UTC 24 Sep 04 12:34:01 PM UTC 24 336686010000 ps
T168 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.1967307082 Sep 04 11:58:58 AM UTC 24 Sep 04 12:34:10 PM UTC 24 336797150000 ps
T169 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.1481980243 Sep 04 11:59:07 AM UTC 24 Sep 04 12:34:16 PM UTC 24 336622470000 ps
T170 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2793881353 Sep 04 11:59:22 AM UTC 24 Sep 04 12:34:32 PM UTC 24 336959850000 ps
T171 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.2188354149 Sep 04 11:59:26 AM UTC 24 Sep 04 12:34:35 PM UTC 24 336782170000 ps
T172 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.3729920146 Sep 04 12:00:42 PM UTC 24 Sep 04 12:35:38 PM UTC 24 336734590000 ps
T173 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.787320031 Sep 04 12:01:09 PM UTC 24 Sep 04 12:36:03 PM UTC 24 336784050000 ps
T174 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.1457597257 Sep 04 12:01:16 PM UTC 24 Sep 04 12:36:07 PM UTC 24 336586410000 ps
T175 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.720402264 Sep 04 12:01:16 PM UTC 24 Sep 04 12:36:09 PM UTC 24 336966310000 ps
T176 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.3574259697 Sep 04 12:02:00 PM UTC 24 Sep 04 12:36:49 PM UTC 24 337088190000 ps
T177 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1798352814 Sep 04 12:02:12 PM UTC 24 Sep 04 12:36:56 PM UTC 24 336728130000 ps
T178 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.178627153 Sep 04 12:02:53 PM UTC 24 Sep 04 12:37:27 PM UTC 24 336406030000 ps
T179 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.3750133669 Sep 04 12:04:38 PM UTC 24 Sep 04 12:38:51 PM UTC 24 336396910000 ps
T180 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.934370619 Sep 04 12:04:40 PM UTC 24 Sep 04 12:38:54 PM UTC 24 336663950000 ps
T181 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3718585209 Sep 04 12:04:45 PM UTC 24 Sep 04 12:38:59 PM UTC 24 336818310000 ps
T182 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.2832866311 Sep 04 12:07:11 PM UTC 24 Sep 04 12:40:59 PM UTC 24 336401910000 ps
T183 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.2516201155 Sep 04 12:07:08 PM UTC 24 Sep 04 12:41:01 PM UTC 24 336872790000 ps
T184 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.367395030 Sep 04 12:07:17 PM UTC 24 Sep 04 12:41:07 PM UTC 24 336533970000 ps
T185 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.830239633 Sep 04 12:07:27 PM UTC 24 Sep 04 12:41:18 PM UTC 24 336711330000 ps
T186 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.3637690838 Sep 04 12:08:09 PM UTC 24 Sep 04 12:41:58 PM UTC 24 336577530000 ps
T187 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.2911973483 Sep 04 12:08:12 PM UTC 24 Sep 04 12:42:02 PM UTC 24 336667470000 ps
T188 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.3355087979 Sep 04 12:08:16 PM UTC 24 Sep 04 12:42:07 PM UTC 24 336966970000 ps
T189 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.4107897845 Sep 04 12:08:20 PM UTC 24 Sep 04 12:42:10 PM UTC 24 336535070000 ps
T190 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.3942781103 Sep 04 12:08:39 PM UTC 24 Sep 04 12:42:32 PM UTC 24 336599570000 ps
T191 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.1550595759 Sep 04 12:09:11 PM UTC 24 Sep 04 12:43:11 PM UTC 24 336897010000 ps
T192 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.340601700 Sep 04 12:11:56 PM UTC 24 Sep 04 12:46:11 PM UTC 24 336628390000 ps
T193 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.565398903 Sep 04 12:11:56 PM UTC 24 Sep 04 12:46:11 PM UTC 24 336587690000 ps
T194 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.3785007852 Sep 04 12:12:51 PM UTC 24 Sep 04 12:47:18 PM UTC 24 336810490000 ps
T195 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.3923663393 Sep 04 12:13:31 PM UTC 24 Sep 04 12:48:04 PM UTC 24 336609670000 ps
T196 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.2781642926 Sep 04 12:14:17 PM UTC 24 Sep 04 12:49:02 PM UTC 24 336873370000 ps
T197 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.3350518222 Sep 04 12:15:59 PM UTC 24 Sep 04 12:51:04 PM UTC 24 336357330000 ps
T198 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.1439138211 Sep 04 12:16:21 PM UTC 24 Sep 04 12:51:34 PM UTC 24 336863270000 ps
T199 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.3772202969 Sep 04 12:17:36 PM UTC 24 Sep 04 12:53:17 PM UTC 24 337053350000 ps
T200 /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.1911698234 Sep 04 12:19:32 PM UTC 24 Sep 04 12:55:44 PM UTC 24 336885390000 ps


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.3097838205
Short name T1
Test name
Test status
Simulation time 1349990000 ps
CPU time 1.98 seconds
Started Sep 04 08:38:41 AM UTC 24
Finished Sep 04 08:38:52 AM UTC 24
Peak memory 177796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097838205 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.3097838205
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/0.prim_lfsr_gal_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.875939969
Short name T20
Test name
Test status
Simulation time 336776310000 ps
CPU time 237.42 seconds
Started Sep 04 11:02:43 AM UTC 24
Finished Sep 04 11:36:21 AM UTC 24
Peak memory 176652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=875939969 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.875939969
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/1.prim_lfsr_gal_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.2617345179
Short name T31
Test name
Test status
Simulation time 336569170000 ps
CPU time 266.27 seconds
Started Sep 04 11:56:52 AM UTC 24
Finished Sep 04 12:32:31 PM UTC 24
Peak memory 175184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2617345179 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.2617345179
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/0.prim_lfsr_fib_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.3848111113
Short name T5
Test name
Test status
Simulation time 1484870000 ps
CPU time 2.11 seconds
Started Sep 04 10:05:39 AM UTC 24
Finished Sep 04 10:05:50 AM UTC 24
Peak memory 177772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3848111113 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.3848111113
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/0.prim_lfsr_fib_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.3503313546
Short name T32
Test name
Test status
Simulation time 336569770000 ps
CPU time 265.31 seconds
Started Sep 04 11:56:55 AM UTC 24
Finished Sep 04 12:32:32 PM UTC 24
Peak memory 175120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3503313546 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.3503313546
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/1.prim_lfsr_fib_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.73736719
Short name T161
Test name
Test status
Simulation time 336929110000 ps
CPU time 264.08 seconds
Started Sep 04 11:57:53 AM UTC 24
Finished Sep 04 12:33:13 PM UTC 24
Peak memory 175120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=73736719 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_
fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.73736719
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/10.prim_lfsr_fib_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.1017145923
Short name T162
Test name
Test status
Simulation time 337137950000 ps
CPU time 261.41 seconds
Started Sep 04 11:58:25 AM UTC 24
Finished Sep 04 12:33:40 PM UTC 24
Peak memory 175124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1017145923 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.1017145923
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/11.prim_lfsr_fib_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.2114776802
Short name T163
Test name
Test status
Simulation time 337010030000 ps
CPU time 264.29 seconds
Started Sep 04 11:58:25 AM UTC 24
Finished Sep 04 12:33:40 PM UTC 24
Peak memory 175124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2114776802 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.2114776802
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/12.prim_lfsr_fib_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.4198803736
Short name T164
Test name
Test status
Simulation time 336824970000 ps
CPU time 262.81 seconds
Started Sep 04 11:58:27 AM UTC 24
Finished Sep 04 12:33:41 PM UTC 24
Peak memory 175124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4198803736 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.4198803736
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/13.prim_lfsr_fib_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.891110257
Short name T166
Test name
Test status
Simulation time 336761230000 ps
CPU time 261.02 seconds
Started Sep 04 11:58:40 AM UTC 24
Finished Sep 04 12:33:52 PM UTC 24
Peak memory 175128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=891110257 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.891110257
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/14.prim_lfsr_fib_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.2607960612
Short name T165
Test name
Test status
Simulation time 336535110000 ps
CPU time 258.65 seconds
Started Sep 04 11:58:40 AM UTC 24
Finished Sep 04 12:33:50 PM UTC 24
Peak memory 175124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2607960612 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.2607960612
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/15.prim_lfsr_fib_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.904675238
Short name T167
Test name
Test status
Simulation time 336686010000 ps
CPU time 259.43 seconds
Started Sep 04 11:58:51 AM UTC 24
Finished Sep 04 12:34:01 PM UTC 24
Peak memory 175124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=904675238 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.904675238
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/16.prim_lfsr_fib_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.1967307082
Short name T168
Test name
Test status
Simulation time 336797150000 ps
CPU time 260.96 seconds
Started Sep 04 11:58:58 AM UTC 24
Finished Sep 04 12:34:10 PM UTC 24
Peak memory 175124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1967307082 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.1967307082
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/17.prim_lfsr_fib_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.1481980243
Short name T169
Test name
Test status
Simulation time 336622470000 ps
CPU time 262.17 seconds
Started Sep 04 11:59:07 AM UTC 24
Finished Sep 04 12:34:16 PM UTC 24
Peak memory 175124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1481980243 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.1481980243
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/18.prim_lfsr_fib_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2793881353
Short name T170
Test name
Test status
Simulation time 336959850000 ps
CPU time 260.36 seconds
Started Sep 04 11:59:22 AM UTC 24
Finished Sep 04 12:34:32 PM UTC 24
Peak memory 175124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2793881353 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.2793881353
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/19.prim_lfsr_fib_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.694802309
Short name T34
Test name
Test status
Simulation time 336713010000 ps
CPU time 266.17 seconds
Started Sep 04 11:57:12 AM UTC 24
Finished Sep 04 12:32:44 PM UTC 24
Peak memory 175120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=694802309 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.694802309
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/2.prim_lfsr_fib_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.2188354149
Short name T171
Test name
Test status
Simulation time 336782170000 ps
CPU time 262.18 seconds
Started Sep 04 11:59:26 AM UTC 24
Finished Sep 04 12:34:35 PM UTC 24
Peak memory 175124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2188354149 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.2188354149
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/20.prim_lfsr_fib_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.3729920146
Short name T172
Test name
Test status
Simulation time 336734590000 ps
CPU time 260.16 seconds
Started Sep 04 12:00:42 PM UTC 24
Finished Sep 04 12:35:38 PM UTC 24
Peak memory 175124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3729920146 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.3729920146
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/21.prim_lfsr_fib_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.787320031
Short name T173
Test name
Test status
Simulation time 336784050000 ps
CPU time 260.37 seconds
Started Sep 04 12:01:09 PM UTC 24
Finished Sep 04 12:36:03 PM UTC 24
Peak memory 175128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=787320031 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.787320031
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/22.prim_lfsr_fib_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.720402264
Short name T175
Test name
Test status
Simulation time 336966310000 ps
CPU time 258.99 seconds
Started Sep 04 12:01:16 PM UTC 24
Finished Sep 04 12:36:09 PM UTC 24
Peak memory 175124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=720402264 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.720402264
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/23.prim_lfsr_fib_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.1457597257
Short name T174
Test name
Test status
Simulation time 336586410000 ps
CPU time 260.29 seconds
Started Sep 04 12:01:16 PM UTC 24
Finished Sep 04 12:36:07 PM UTC 24
Peak memory 175124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1457597257 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.1457597257
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/24.prim_lfsr_fib_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.3574259697
Short name T176
Test name
Test status
Simulation time 337088190000 ps
CPU time 256.57 seconds
Started Sep 04 12:02:00 PM UTC 24
Finished Sep 04 12:36:49 PM UTC 24
Peak memory 175124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3574259697 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.3574259697
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/25.prim_lfsr_fib_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1798352814
Short name T177
Test name
Test status
Simulation time 336728130000 ps
CPU time 258.88 seconds
Started Sep 04 12:02:12 PM UTC 24
Finished Sep 04 12:36:56 PM UTC 24
Peak memory 175124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1798352814 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.1798352814
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/26.prim_lfsr_fib_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.178627153
Short name T178
Test name
Test status
Simulation time 336406030000 ps
CPU time 255.91 seconds
Started Sep 04 12:02:53 PM UTC 24
Finished Sep 04 12:37:27 PM UTC 24
Peak memory 175128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=178627153 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.178627153
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/27.prim_lfsr_fib_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.3750133669
Short name T179
Test name
Test status
Simulation time 336396910000 ps
CPU time 253.13 seconds
Started Sep 04 12:04:38 PM UTC 24
Finished Sep 04 12:38:51 PM UTC 24
Peak memory 175124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3750133669 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.3750133669
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/28.prim_lfsr_fib_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.934370619
Short name T180
Test name
Test status
Simulation time 336663950000 ps
CPU time 252.35 seconds
Started Sep 04 12:04:40 PM UTC 24
Finished Sep 04 12:38:54 PM UTC 24
Peak memory 175128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=934370619 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.934370619
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/29.prim_lfsr_fib_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.4046899283
Short name T36
Test name
Test status
Simulation time 336947730000 ps
CPU time 266.48 seconds
Started Sep 04 11:57:14 AM UTC 24
Finished Sep 04 12:32:46 PM UTC 24
Peak memory 175120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4046899283 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.4046899283
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/3.prim_lfsr_fib_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3718585209
Short name T181
Test name
Test status
Simulation time 336818310000 ps
CPU time 253.69 seconds
Started Sep 04 12:04:45 PM UTC 24
Finished Sep 04 12:38:59 PM UTC 24
Peak memory 175124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3718585209 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.3718585209
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/30.prim_lfsr_fib_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.2516201155
Short name T183
Test name
Test status
Simulation time 336872790000 ps
CPU time 250.49 seconds
Started Sep 04 12:07:08 PM UTC 24
Finished Sep 04 12:41:01 PM UTC 24
Peak memory 175124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2516201155 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.2516201155
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/31.prim_lfsr_fib_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.2832866311
Short name T182
Test name
Test status
Simulation time 336401910000 ps
CPU time 248.53 seconds
Started Sep 04 12:07:11 PM UTC 24
Finished Sep 04 12:40:59 PM UTC 24
Peak memory 175124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2832866311 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.2832866311
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/32.prim_lfsr_fib_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.367395030
Short name T184
Test name
Test status
Simulation time 336533970000 ps
CPU time 248.71 seconds
Started Sep 04 12:07:17 PM UTC 24
Finished Sep 04 12:41:07 PM UTC 24
Peak memory 175128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=367395030 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.367395030
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/33.prim_lfsr_fib_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.830239633
Short name T185
Test name
Test status
Simulation time 336711330000 ps
CPU time 248.05 seconds
Started Sep 04 12:07:27 PM UTC 24
Finished Sep 04 12:41:18 PM UTC 24
Peak memory 175128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=830239633 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.830239633
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/34.prim_lfsr_fib_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.3637690838
Short name T186
Test name
Test status
Simulation time 336577530000 ps
CPU time 248.3 seconds
Started Sep 04 12:08:09 PM UTC 24
Finished Sep 04 12:41:58 PM UTC 24
Peak memory 175124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3637690838 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.3637690838
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/35.prim_lfsr_fib_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.2911973483
Short name T187
Test name
Test status
Simulation time 336667470000 ps
CPU time 246.91 seconds
Started Sep 04 12:08:12 PM UTC 24
Finished Sep 04 12:42:02 PM UTC 24
Peak memory 175124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2911973483 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.2911973483
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/36.prim_lfsr_fib_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.3355087979
Short name T188
Test name
Test status
Simulation time 336966970000 ps
CPU time 247.43 seconds
Started Sep 04 12:08:16 PM UTC 24
Finished Sep 04 12:42:07 PM UTC 24
Peak memory 175124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3355087979 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.3355087979
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/37.prim_lfsr_fib_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.4107897845
Short name T189
Test name
Test status
Simulation time 336535070000 ps
CPU time 247.98 seconds
Started Sep 04 12:08:20 PM UTC 24
Finished Sep 04 12:42:10 PM UTC 24
Peak memory 175124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4107897845 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.4107897845
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/38.prim_lfsr_fib_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.3942781103
Short name T190
Test name
Test status
Simulation time 336599570000 ps
CPU time 249.7 seconds
Started Sep 04 12:08:39 PM UTC 24
Finished Sep 04 12:42:32 PM UTC 24
Peak memory 175124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3942781103 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.3942781103
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/39.prim_lfsr_fib_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.2870608597
Short name T37
Test name
Test status
Simulation time 336932270000 ps
CPU time 265.72 seconds
Started Sep 04 11:57:15 AM UTC 24
Finished Sep 04 12:32:46 PM UTC 24
Peak memory 175128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2870608597 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.2870608597
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/4.prim_lfsr_fib_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.1550595759
Short name T191
Test name
Test status
Simulation time 336897010000 ps
CPU time 250.69 seconds
Started Sep 04 12:09:11 PM UTC 24
Finished Sep 04 12:43:11 PM UTC 24
Peak memory 175124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1550595759 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.1550595759
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/40.prim_lfsr_fib_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.340601700
Short name T192
Test name
Test status
Simulation time 336628390000 ps
CPU time 249.53 seconds
Started Sep 04 12:11:56 PM UTC 24
Finished Sep 04 12:46:11 PM UTC 24
Peak memory 175128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=340601700 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.340601700
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/41.prim_lfsr_fib_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.565398903
Short name T193
Test name
Test status
Simulation time 336587690000 ps
CPU time 251.04 seconds
Started Sep 04 12:11:56 PM UTC 24
Finished Sep 04 12:46:11 PM UTC 24
Peak memory 175128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=565398903 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.565398903
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/42.prim_lfsr_fib_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.3785007852
Short name T194
Test name
Test status
Simulation time 336810490000 ps
CPU time 249.38 seconds
Started Sep 04 12:12:51 PM UTC 24
Finished Sep 04 12:47:18 PM UTC 24
Peak memory 175124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3785007852 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.3785007852
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/43.prim_lfsr_fib_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.3923663393
Short name T195
Test name
Test status
Simulation time 336609670000 ps
CPU time 252.29 seconds
Started Sep 04 12:13:31 PM UTC 24
Finished Sep 04 12:48:04 PM UTC 24
Peak memory 175124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3923663393 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.3923663393
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/44.prim_lfsr_fib_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.2781642926
Short name T196
Test name
Test status
Simulation time 336873370000 ps
CPU time 250.46 seconds
Started Sep 04 12:14:17 PM UTC 24
Finished Sep 04 12:49:02 PM UTC 24
Peak memory 175124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2781642926 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.2781642926
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/45.prim_lfsr_fib_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.3350518222
Short name T197
Test name
Test status
Simulation time 336357330000 ps
CPU time 253.06 seconds
Started Sep 04 12:15:59 PM UTC 24
Finished Sep 04 12:51:04 PM UTC 24
Peak memory 175124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350518222 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.3350518222
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/46.prim_lfsr_fib_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.1439138211
Short name T198
Test name
Test status
Simulation time 336863270000 ps
CPU time 251.35 seconds
Started Sep 04 12:16:21 PM UTC 24
Finished Sep 04 12:51:34 PM UTC 24
Peak memory 175124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1439138211 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.1439138211
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/47.prim_lfsr_fib_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.3772202969
Short name T199
Test name
Test status
Simulation time 337053350000 ps
CPU time 253.73 seconds
Started Sep 04 12:17:36 PM UTC 24
Finished Sep 04 12:53:17 PM UTC 24
Peak memory 175124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3772202969 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.3772202969
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/48.prim_lfsr_fib_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.1911698234
Short name T200
Test name
Test status
Simulation time 336885390000 ps
CPU time 257.38 seconds
Started Sep 04 12:19:32 PM UTC 24
Finished Sep 04 12:55:44 PM UTC 24
Peak memory 175128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1911698234 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.1911698234
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/49.prim_lfsr_fib_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.263204173
Short name T33
Test name
Test status
Simulation time 336357870000 ps
CPU time 265.98 seconds
Started Sep 04 11:57:15 AM UTC 24
Finished Sep 04 12:32:43 PM UTC 24
Peak memory 175124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=263204173 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.263204173
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/5.prim_lfsr_fib_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.4057187442
Short name T35
Test name
Test status
Simulation time 336839090000 ps
CPU time 266.22 seconds
Started Sep 04 11:57:15 AM UTC 24
Finished Sep 04 12:32:46 PM UTC 24
Peak memory 175120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4057187442 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.4057187442
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/6.prim_lfsr_fib_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.2839199579
Short name T38
Test name
Test status
Simulation time 336509410000 ps
CPU time 263.91 seconds
Started Sep 04 11:57:30 AM UTC 24
Finished Sep 04 12:32:56 PM UTC 24
Peak memory 175120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2839199579 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.2839199579
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/7.prim_lfsr_fib_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.2663748137
Short name T39
Test name
Test status
Simulation time 336421350000 ps
CPU time 264.14 seconds
Started Sep 04 11:57:37 AM UTC 24
Finished Sep 04 12:33:00 PM UTC 24
Peak memory 175128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2663748137 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.2663748137
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/8.prim_lfsr_fib_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.2986427147
Short name T40
Test name
Test status
Simulation time 337091490000 ps
CPU time 264.07 seconds
Started Sep 04 11:57:50 AM UTC 24
Finished Sep 04 12:33:12 PM UTC 24
Peak memory 175120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2986427147 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.2986427147
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/9.prim_lfsr_fib_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.237285187
Short name T86
Test name
Test status
Simulation time 337111370000 ps
CPU time 241.16 seconds
Started Sep 04 11:02:43 AM UTC 24
Finished Sep 04 11:36:24 AM UTC 24
Peak memory 176652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=237285187 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.237285187
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/0.prim_lfsr_gal_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.2694076741
Short name T22
Test name
Test status
Simulation time 336714410000 ps
CPU time 239.65 seconds
Started Sep 04 11:02:43 AM UTC 24
Finished Sep 04 11:36:22 AM UTC 24
Peak memory 175128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694076741 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.2694076741
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/10.prim_lfsr_gal_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.3258774823
Short name T85
Test name
Test status
Simulation time 337007250000 ps
CPU time 242.29 seconds
Started Sep 04 11:02:43 AM UTC 24
Finished Sep 04 11:36:23 AM UTC 24
Peak memory 175128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3258774823 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.3258774823
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/11.prim_lfsr_gal_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.1181332594
Short name T21
Test name
Test status
Simulation time 336453250000 ps
CPU time 240.12 seconds
Started Sep 04 11:02:44 AM UTC 24
Finished Sep 04 11:36:22 AM UTC 24
Peak memory 175128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1181332594 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.1181332594
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/12.prim_lfsr_gal_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.1700265504
Short name T83
Test name
Test status
Simulation time 336750630000 ps
CPU time 239.09 seconds
Started Sep 04 11:02:45 AM UTC 24
Finished Sep 04 11:36:23 AM UTC 24
Peak memory 176656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1700265504 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.1700265504
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/13.prim_lfsr_gal_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.43326567
Short name T87
Test name
Test status
Simulation time 336998930000 ps
CPU time 239.86 seconds
Started Sep 04 11:02:45 AM UTC 24
Finished Sep 04 11:36:25 AM UTC 24
Peak memory 176572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=43326567 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_
gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.43326567
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/14.prim_lfsr_gal_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.879556490
Short name T81
Test name
Test status
Simulation time 336492370000 ps
CPU time 240.73 seconds
Started Sep 04 11:02:45 AM UTC 24
Finished Sep 04 11:36:22 AM UTC 24
Peak memory 175132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=879556490 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.879556490
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/15.prim_lfsr_gal_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.4266742793
Short name T84
Test name
Test status
Simulation time 336737750000 ps
CPU time 237.04 seconds
Started Sep 04 11:02:46 AM UTC 24
Finished Sep 04 11:36:23 AM UTC 24
Peak memory 176656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4266742793 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.4266742793
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/16.prim_lfsr_gal_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.97516848
Short name T89
Test name
Test status
Simulation time 336728010000 ps
CPU time 242.39 seconds
Started Sep 04 11:02:52 AM UTC 24
Finished Sep 04 11:36:33 AM UTC 24
Peak memory 176652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=97516848 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_
gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.97516848
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/17.prim_lfsr_gal_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.1017011111
Short name T88
Test name
Test status
Simulation time 336602950000 ps
CPU time 238.61 seconds
Started Sep 04 11:02:53 AM UTC 24
Finished Sep 04 11:36:32 AM UTC 24
Peak memory 175128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1017011111 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.1017011111
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/18.prim_lfsr_gal_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.1408196546
Short name T93
Test name
Test status
Simulation time 336899810000 ps
CPU time 238.83 seconds
Started Sep 04 11:02:55 AM UTC 24
Finished Sep 04 11:36:37 AM UTC 24
Peak memory 176656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1408196546 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.1408196546
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/19.prim_lfsr_gal_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.1288983033
Short name T14
Test name
Test status
Simulation time 336534230000 ps
CPU time 238.07 seconds
Started Sep 04 11:02:43 AM UTC 24
Finished Sep 04 11:36:20 AM UTC 24
Peak memory 176772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1288983033 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.1288983033
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/2.prim_lfsr_gal_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.2371517832
Short name T91
Test name
Test status
Simulation time 336611270000 ps
CPU time 237.53 seconds
Started Sep 04 11:02:55 AM UTC 24
Finished Sep 04 11:36:35 AM UTC 24
Peak memory 176656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2371517832 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.2371517832
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/20.prim_lfsr_gal_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.4031526978
Short name T90
Test name
Test status
Simulation time 336552610000 ps
CPU time 240.42 seconds
Started Sep 04 11:02:55 AM UTC 24
Finished Sep 04 11:36:35 AM UTC 24
Peak memory 176656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4031526978 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.4031526978
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/21.prim_lfsr_gal_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.2391331935
Short name T92
Test name
Test status
Simulation time 336697010000 ps
CPU time 238.91 seconds
Started Sep 04 11:02:55 AM UTC 24
Finished Sep 04 11:36:36 AM UTC 24
Peak memory 175128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2391331935 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.2391331935
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/22.prim_lfsr_gal_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.1922635109
Short name T97
Test name
Test status
Simulation time 336693970000 ps
CPU time 240.2 seconds
Started Sep 04 11:03:04 AM UTC 24
Finished Sep 04 11:36:50 AM UTC 24
Peak memory 176656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1922635109 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.1922635109
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/23.prim_lfsr_gal_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.4291251239
Short name T94
Test name
Test status
Simulation time 336682990000 ps
CPU time 240.52 seconds
Started Sep 04 11:03:04 AM UTC 24
Finished Sep 04 11:36:49 AM UTC 24
Peak memory 175128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4291251239 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.4291251239
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/24.prim_lfsr_gal_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.1881795032
Short name T104
Test name
Test status
Simulation time 337009850000 ps
CPU time 243.95 seconds
Started Sep 04 11:03:04 AM UTC 24
Finished Sep 04 11:36:53 AM UTC 24
Peak memory 176656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1881795032 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.1881795032
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/25.prim_lfsr_gal_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.179298834
Short name T95
Test name
Test status
Simulation time 336447030000 ps
CPU time 241.68 seconds
Started Sep 04 11:03:04 AM UTC 24
Finished Sep 04 11:36:49 AM UTC 24
Peak memory 176660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=179298834 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.179298834
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/26.prim_lfsr_gal_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.357684860
Short name T112
Test name
Test status
Simulation time 337035870000 ps
CPU time 243.36 seconds
Started Sep 04 11:03:05 AM UTC 24
Finished Sep 04 11:36:54 AM UTC 24
Peak memory 176660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=357684860 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.357684860
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/27.prim_lfsr_gal_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.3169342428
Short name T106
Test name
Test status
Simulation time 336942970000 ps
CPU time 240.77 seconds
Started Sep 04 11:03:05 AM UTC 24
Finished Sep 04 11:36:53 AM UTC 24
Peak memory 176632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3169342428 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.3169342428
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/28.prim_lfsr_gal_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.2398469349
Short name T102
Test name
Test status
Simulation time 336804170000 ps
CPU time 241.58 seconds
Started Sep 04 11:03:05 AM UTC 24
Finished Sep 04 11:36:52 AM UTC 24
Peak memory 176648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2398469349 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.2398469349
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/29.prim_lfsr_gal_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.305219234
Short name T18
Test name
Test status
Simulation time 336496190000 ps
CPU time 241.23 seconds
Started Sep 04 11:02:43 AM UTC 24
Finished Sep 04 11:36:21 AM UTC 24
Peak memory 176656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=305219234 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.305219234
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/3.prim_lfsr_gal_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.2158577565
Short name T96
Test name
Test status
Simulation time 336663350000 ps
CPU time 239.15 seconds
Started Sep 04 11:03:05 AM UTC 24
Finished Sep 04 11:36:50 AM UTC 24
Peak memory 175128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2158577565 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.2158577565
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/30.prim_lfsr_gal_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.3459749390
Short name T98
Test name
Test status
Simulation time 336361050000 ps
CPU time 243.15 seconds
Started Sep 04 11:03:05 AM UTC 24
Finished Sep 04 11:36:51 AM UTC 24
Peak memory 176656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3459749390 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.3459749390
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/31.prim_lfsr_gal_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.3643183578
Short name T100
Test name
Test status
Simulation time 336614530000 ps
CPU time 242.53 seconds
Started Sep 04 11:03:05 AM UTC 24
Finished Sep 04 11:36:51 AM UTC 24
Peak memory 175128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3643183578 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.3643183578
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/32.prim_lfsr_gal_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.2759120558
Short name T99
Test name
Test status
Simulation time 336312470000 ps
CPU time 240.8 seconds
Started Sep 04 11:03:07 AM UTC 24
Finished Sep 04 11:36:51 AM UTC 24
Peak memory 176656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2759120558 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.2759120558
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/33.prim_lfsr_gal_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.2092201269
Short name T114
Test name
Test status
Simulation time 336837190000 ps
CPU time 242.86 seconds
Started Sep 04 11:03:07 AM UTC 24
Finished Sep 04 11:36:55 AM UTC 24
Peak memory 175128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2092201269 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.2092201269
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/34.prim_lfsr_gal_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.405333766
Short name T105
Test name
Test status
Simulation time 336674650000 ps
CPU time 240.28 seconds
Started Sep 04 11:03:07 AM UTC 24
Finished Sep 04 11:36:53 AM UTC 24
Peak memory 176660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=405333766 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.405333766
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/35.prim_lfsr_gal_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.673086863
Short name T101
Test name
Test status
Simulation time 336591430000 ps
CPU time 240.18 seconds
Started Sep 04 11:03:07 AM UTC 24
Finished Sep 04 11:36:51 AM UTC 24
Peak memory 176660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=673086863 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.673086863
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/36.prim_lfsr_gal_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.606514730
Short name T108
Test name
Test status
Simulation time 336598090000 ps
CPU time 242.41 seconds
Started Sep 04 11:03:07 AM UTC 24
Finished Sep 04 11:36:53 AM UTC 24
Peak memory 176660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=606514730 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.606514730
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/37.prim_lfsr_gal_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.2281210254
Short name T103
Test name
Test status
Simulation time 336580270000 ps
CPU time 239.52 seconds
Started Sep 04 11:03:07 AM UTC 24
Finished Sep 04 11:36:52 AM UTC 24
Peak memory 175128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2281210254 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.2281210254
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/38.prim_lfsr_gal_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.1757770662
Short name T107
Test name
Test status
Simulation time 336892970000 ps
CPU time 238.83 seconds
Started Sep 04 11:03:07 AM UTC 24
Finished Sep 04 11:36:53 AM UTC 24
Peak memory 176656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1757770662 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.1757770662
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/39.prim_lfsr_gal_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.4033150542
Short name T17
Test name
Test status
Simulation time 336562850000 ps
CPU time 238.47 seconds
Started Sep 04 11:02:43 AM UTC 24
Finished Sep 04 11:36:21 AM UTC 24
Peak memory 176708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4033150542 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.4033150542
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/4.prim_lfsr_gal_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.1878227490
Short name T111
Test name
Test status
Simulation time 336908830000 ps
CPU time 238.9 seconds
Started Sep 04 11:03:07 AM UTC 24
Finished Sep 04 11:36:54 AM UTC 24
Peak memory 176656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1878227490 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.1878227490
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/40.prim_lfsr_gal_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.2358648542
Short name T113
Test name
Test status
Simulation time 336878630000 ps
CPU time 241.3 seconds
Started Sep 04 11:03:07 AM UTC 24
Finished Sep 04 11:36:54 AM UTC 24
Peak memory 176656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2358648542 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.2358648542
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/41.prim_lfsr_gal_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.2294835642
Short name T110
Test name
Test status
Simulation time 336423050000 ps
CPU time 241.46 seconds
Started Sep 04 11:03:08 AM UTC 24
Finished Sep 04 11:36:54 AM UTC 24
Peak memory 175064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2294835642 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.2294835642
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/42.prim_lfsr_gal_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.2144896777
Short name T116
Test name
Test status
Simulation time 336993030000 ps
CPU time 239.67 seconds
Started Sep 04 11:03:08 AM UTC 24
Finished Sep 04 11:36:56 AM UTC 24
Peak memory 176656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2144896777 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.2144896777
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/43.prim_lfsr_gal_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.2225932262
Short name T118
Test name
Test status
Simulation time 336667570000 ps
CPU time 245.72 seconds
Started Sep 04 11:03:08 AM UTC 24
Finished Sep 04 11:36:57 AM UTC 24
Peak memory 176656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2225932262 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.2225932262
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/44.prim_lfsr_gal_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.1785016045
Short name T115
Test name
Test status
Simulation time 336611610000 ps
CPU time 243.22 seconds
Started Sep 04 11:03:08 AM UTC 24
Finished Sep 04 11:36:55 AM UTC 24
Peak memory 175128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1785016045 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.1785016045
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/45.prim_lfsr_gal_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.1129210737
Short name T119
Test name
Test status
Simulation time 337062750000 ps
CPU time 239.95 seconds
Started Sep 04 11:03:08 AM UTC 24
Finished Sep 04 11:36:57 AM UTC 24
Peak memory 176656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1129210737 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.1129210737
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/46.prim_lfsr_gal_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.1964695950
Short name T117
Test name
Test status
Simulation time 336783210000 ps
CPU time 242.37 seconds
Started Sep 04 11:03:08 AM UTC 24
Finished Sep 04 11:36:57 AM UTC 24
Peak memory 176656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1964695950 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.1964695950
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/47.prim_lfsr_gal_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.3706273355
Short name T120
Test name
Test status
Simulation time 336964550000 ps
CPU time 242.58 seconds
Started Sep 04 11:03:08 AM UTC 24
Finished Sep 04 11:36:57 AM UTC 24
Peak memory 175128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3706273355 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.3706273355
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/48.prim_lfsr_gal_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.1261110027
Short name T109
Test name
Test status
Simulation time 336573130000 ps
CPU time 237.88 seconds
Started Sep 04 11:03:08 AM UTC 24
Finished Sep 04 11:36:53 AM UTC 24
Peak memory 176656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1261110027 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.1261110027
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/49.prim_lfsr_gal_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.3965343892
Short name T82
Test name
Test status
Simulation time 336786330000 ps
CPU time 241.2 seconds
Started Sep 04 11:02:43 AM UTC 24
Finished Sep 04 11:36:23 AM UTC 24
Peak memory 176660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3965343892 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.3965343892
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/5.prim_lfsr_gal_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.2228825039
Short name T15
Test name
Test status
Simulation time 336378470000 ps
CPU time 239.11 seconds
Started Sep 04 11:02:43 AM UTC 24
Finished Sep 04 11:36:20 AM UTC 24
Peak memory 176652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2228825039 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.2228825039
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/6.prim_lfsr_gal_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.2389661000
Short name T23
Test name
Test status
Simulation time 336751570000 ps
CPU time 240.85 seconds
Started Sep 04 11:02:43 AM UTC 24
Finished Sep 04 11:36:22 AM UTC 24
Peak memory 176652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2389661000 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.2389661000
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/7.prim_lfsr_gal_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.904161381
Short name T19
Test name
Test status
Simulation time 336501370000 ps
CPU time 241.3 seconds
Started Sep 04 11:02:43 AM UTC 24
Finished Sep 04 11:36:21 AM UTC 24
Peak memory 176652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=904161381 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.904161381
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/8.prim_lfsr_gal_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.297086531
Short name T16
Test name
Test status
Simulation time 336773690000 ps
CPU time 236.38 seconds
Started Sep 04 11:02:43 AM UTC 24
Finished Sep 04 11:36:21 AM UTC 24
Peak memory 176644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=297086531 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.297086531
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/9.prim_lfsr_gal_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.623110563
Short name T6
Test name
Test status
Simulation time 1371770000 ps
CPU time 2.02 seconds
Started Sep 04 10:05:40 AM UTC 24
Finished Sep 04 10:05:50 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=623110563 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f
ib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.623110563
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/1.prim_lfsr_fib_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.561296386
Short name T30
Test name
Test status
Simulation time 1438470000 ps
CPU time 2.21 seconds
Started Sep 04 10:05:43 AM UTC 24
Finished Sep 04 10:05:54 AM UTC 24
Peak memory 177424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=561296386 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f
ib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.561296386
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/10.prim_lfsr_fib_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.894195251
Short name T122
Test name
Test status
Simulation time 1514390000 ps
CPU time 2.25 seconds
Started Sep 04 10:05:43 AM UTC 24
Finished Sep 04 10:05:54 AM UTC 24
Peak memory 177400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=894195251 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f
ib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.894195251
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/11.prim_lfsr_fib_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.1089540917
Short name T123
Test name
Test status
Simulation time 1465890000 ps
CPU time 2.1 seconds
Started Sep 04 10:05:44 AM UTC 24
Finished Sep 04 10:05:55 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1089540917 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.1089540917
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/12.prim_lfsr_fib_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.2579130211
Short name T125
Test name
Test status
Simulation time 1583710000 ps
CPU time 2.12 seconds
Started Sep 04 10:05:45 AM UTC 24
Finished Sep 04 10:05:57 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2579130211 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.2579130211
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/13.prim_lfsr_fib_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.3223174051
Short name T124
Test name
Test status
Simulation time 1493270000 ps
CPU time 2.05 seconds
Started Sep 04 10:05:45 AM UTC 24
Finished Sep 04 10:05:56 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3223174051 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.3223174051
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/14.prim_lfsr_fib_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.87698763
Short name T126
Test name
Test status
Simulation time 1540010000 ps
CPU time 2.11 seconds
Started Sep 04 10:05:46 AM UTC 24
Finished Sep 04 10:05:57 AM UTC 24
Peak memory 177772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87698763 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fi
b.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.87698763
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/15.prim_lfsr_fib_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.4272671334
Short name T128
Test name
Test status
Simulation time 1495310000 ps
CPU time 2.11 seconds
Started Sep 04 10:05:47 AM UTC 24
Finished Sep 04 10:05:58 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4272671334 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.4272671334
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/16.prim_lfsr_fib_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.1483638383
Short name T127
Test name
Test status
Simulation time 1341310000 ps
CPU time 2.03 seconds
Started Sep 04 10:05:47 AM UTC 24
Finished Sep 04 10:05:57 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1483638383 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.1483638383
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/17.prim_lfsr_fib_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.417462962
Short name T129
Test name
Test status
Simulation time 1506850000 ps
CPU time 1.94 seconds
Started Sep 04 10:05:48 AM UTC 24
Finished Sep 04 10:06:00 AM UTC 24
Peak memory 177468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=417462962 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f
ib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.417462962
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/18.prim_lfsr_fib_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.3807627591
Short name T131
Test name
Test status
Simulation time 1525910000 ps
CPU time 2.13 seconds
Started Sep 04 10:05:48 AM UTC 24
Finished Sep 04 10:06:00 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3807627591 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.3807627591
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/19.prim_lfsr_fib_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.3249062509
Short name T25
Test name
Test status
Simulation time 1564070000 ps
CPU time 2.29 seconds
Started Sep 04 10:05:40 AM UTC 24
Finished Sep 04 10:05:52 AM UTC 24
Peak memory 177772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3249062509 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.3249062509
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/2.prim_lfsr_fib_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.2457999366
Short name T130
Test name
Test status
Simulation time 1500190000 ps
CPU time 1.95 seconds
Started Sep 04 10:05:49 AM UTC 24
Finished Sep 04 10:06:00 AM UTC 24
Peak memory 177460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2457999366 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.2457999366
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/20.prim_lfsr_fib_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3539871290
Short name T133
Test name
Test status
Simulation time 1506970000 ps
CPU time 1.98 seconds
Started Sep 04 10:05:50 AM UTC 24
Finished Sep 04 10:06:01 AM UTC 24
Peak memory 177800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3539871290 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.3539871290
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/21.prim_lfsr_fib_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.1922552310
Short name T134
Test name
Test status
Simulation time 1496850000 ps
CPU time 2.02 seconds
Started Sep 04 10:05:50 AM UTC 24
Finished Sep 04 10:06:01 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1922552310 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.1922552310
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/22.prim_lfsr_fib_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.2794861583
Short name T132
Test name
Test status
Simulation time 1404730000 ps
CPU time 1.99 seconds
Started Sep 04 10:05:50 AM UTC 24
Finished Sep 04 10:06:00 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2794861583 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.2794861583
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/23.prim_lfsr_fib_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.929949223
Short name T136
Test name
Test status
Simulation time 1400770000 ps
CPU time 1.74 seconds
Started Sep 04 10:05:51 AM UTC 24
Finished Sep 04 10:06:01 AM UTC 24
Peak memory 177768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=929949223 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f
ib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.929949223
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/24.prim_lfsr_fib_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.2322890055
Short name T135
Test name
Test status
Simulation time 1350310000 ps
CPU time 1.96 seconds
Started Sep 04 10:05:51 AM UTC 24
Finished Sep 04 10:06:01 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2322890055 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.2322890055
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/25.prim_lfsr_fib_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.4251912726
Short name T137
Test name
Test status
Simulation time 1452850000 ps
CPU time 1.94 seconds
Started Sep 04 10:05:51 AM UTC 24
Finished Sep 04 10:06:02 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4251912726 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.4251912726
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/26.prim_lfsr_fib_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.2687772180
Short name T138
Test name
Test status
Simulation time 1537970000 ps
CPU time 2.04 seconds
Started Sep 04 10:05:51 AM UTC 24
Finished Sep 04 10:06:02 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2687772180 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.2687772180
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/27.prim_lfsr_fib_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.2637576123
Short name T139
Test name
Test status
Simulation time 1394010000 ps
CPU time 1.84 seconds
Started Sep 04 10:05:52 AM UTC 24
Finished Sep 04 10:06:02 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2637576123 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.2637576123
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/28.prim_lfsr_fib_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.2275847900
Short name T140
Test name
Test status
Simulation time 1386610000 ps
CPU time 2.01 seconds
Started Sep 04 10:05:52 AM UTC 24
Finished Sep 04 10:06:02 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2275847900 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.2275847900
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/29.prim_lfsr_fib_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.1702424689
Short name T26
Test name
Test status
Simulation time 1579710000 ps
CPU time 2.16 seconds
Started Sep 04 10:05:40 AM UTC 24
Finished Sep 04 10:05:52 AM UTC 24
Peak memory 177772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1702424689 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.1702424689
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/3.prim_lfsr_fib_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.888081297
Short name T143
Test name
Test status
Simulation time 1511570000 ps
CPU time 1.93 seconds
Started Sep 04 10:05:52 AM UTC 24
Finished Sep 04 10:06:03 AM UTC 24
Peak memory 177768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=888081297 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f
ib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.888081297
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/30.prim_lfsr_fib_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.2701288496
Short name T144
Test name
Test status
Simulation time 1512370000 ps
CPU time 1.86 seconds
Started Sep 04 10:05:52 AM UTC 24
Finished Sep 04 10:06:03 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2701288496 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.2701288496
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/31.prim_lfsr_fib_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.745615217
Short name T142
Test name
Test status
Simulation time 1424310000 ps
CPU time 2 seconds
Started Sep 04 10:05:52 AM UTC 24
Finished Sep 04 10:06:03 AM UTC 24
Peak memory 177772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=745615217 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f
ib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.745615217
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/32.prim_lfsr_fib_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.970630674
Short name T141
Test name
Test status
Simulation time 1382330000 ps
CPU time 1.97 seconds
Started Sep 04 10:05:52 AM UTC 24
Finished Sep 04 10:06:03 AM UTC 24
Peak memory 177772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=970630674 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f
ib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.970630674
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/33.prim_lfsr_fib_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.2548760668
Short name T147
Test name
Test status
Simulation time 1501910000 ps
CPU time 1.87 seconds
Started Sep 04 10:05:53 AM UTC 24
Finished Sep 04 10:06:04 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2548760668 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.2548760668
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/34.prim_lfsr_fib_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.906772949
Short name T149
Test name
Test status
Simulation time 1535950000 ps
CPU time 1.93 seconds
Started Sep 04 10:05:53 AM UTC 24
Finished Sep 04 10:06:05 AM UTC 24
Peak memory 177768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=906772949 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f
ib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.906772949
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/35.prim_lfsr_fib_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.1526017189
Short name T146
Test name
Test status
Simulation time 1478510000 ps
CPU time 2.04 seconds
Started Sep 04 10:05:53 AM UTC 24
Finished Sep 04 10:06:04 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1526017189 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.1526017189
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/36.prim_lfsr_fib_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1256889400
Short name T145
Test name
Test status
Simulation time 1448430000 ps
CPU time 1.98 seconds
Started Sep 04 10:05:53 AM UTC 24
Finished Sep 04 10:06:04 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1256889400 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.1256889400
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/37.prim_lfsr_fib_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.3575421457
Short name T148
Test name
Test status
Simulation time 1505190000 ps
CPU time 2.1 seconds
Started Sep 04 10:05:53 AM UTC 24
Finished Sep 04 10:06:05 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3575421457 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.3575421457
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/38.prim_lfsr_fib_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.3554826890
Short name T151
Test name
Test status
Simulation time 1469670000 ps
CPU time 1.98 seconds
Started Sep 04 10:05:55 AM UTC 24
Finished Sep 04 10:06:05 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3554826890 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.3554826890
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/39.prim_lfsr_fib_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3414752325
Short name T4
Test name
Test status
Simulation time 1182450000 ps
CPU time 1.84 seconds
Started Sep 04 10:05:40 AM UTC 24
Finished Sep 04 10:05:49 AM UTC 24
Peak memory 177840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3414752325 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.3414752325
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/4.prim_lfsr_fib_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.17040902
Short name T153
Test name
Test status
Simulation time 1487610000 ps
CPU time 2.02 seconds
Started Sep 04 10:05:55 AM UTC 24
Finished Sep 04 10:06:05 AM UTC 24
Peak memory 177772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17040902 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fi
b.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.17040902
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/40.prim_lfsr_fib_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.2311577690
Short name T152
Test name
Test status
Simulation time 1472850000 ps
CPU time 1.9 seconds
Started Sep 04 10:05:55 AM UTC 24
Finished Sep 04 10:06:05 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2311577690 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.2311577690
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/41.prim_lfsr_fib_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.1330244302
Short name T150
Test name
Test status
Simulation time 1452970000 ps
CPU time 1.82 seconds
Started Sep 04 10:05:55 AM UTC 24
Finished Sep 04 10:06:05 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1330244302 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.1330244302
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/42.prim_lfsr_fib_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1483834442
Short name T154
Test name
Test status
Simulation time 1360370000 ps
CPU time 1.69 seconds
Started Sep 04 10:05:56 AM UTC 24
Finished Sep 04 10:06:06 AM UTC 24
Peak memory 177800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1483834442 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.1483834442
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/43.prim_lfsr_fib_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.2451151895
Short name T155
Test name
Test status
Simulation time 1445530000 ps
CPU time 1.74 seconds
Started Sep 04 10:05:57 AM UTC 24
Finished Sep 04 10:06:07 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2451151895 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.2451151895
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/44.prim_lfsr_fib_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.3296652213
Short name T158
Test name
Test status
Simulation time 1550210000 ps
CPU time 1.9 seconds
Started Sep 04 10:05:58 AM UTC 24
Finished Sep 04 10:06:09 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3296652213 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.3296652213
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/45.prim_lfsr_fib_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.1900665619
Short name T157
Test name
Test status
Simulation time 1459650000 ps
CPU time 1.92 seconds
Started Sep 04 10:05:58 AM UTC 24
Finished Sep 04 10:06:08 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1900665619 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.1900665619
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/46.prim_lfsr_fib_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.354302124
Short name T156
Test name
Test status
Simulation time 1372030000 ps
CPU time 1.78 seconds
Started Sep 04 10:05:58 AM UTC 24
Finished Sep 04 10:06:08 AM UTC 24
Peak memory 177768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=354302124 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f
ib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.354302124
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/47.prim_lfsr_fib_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.1326594647
Short name T159
Test name
Test status
Simulation time 1552750000 ps
CPU time 2.08 seconds
Started Sep 04 10:05:58 AM UTC 24
Finished Sep 04 10:06:09 AM UTC 24
Peak memory 177408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1326594647 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.1326594647
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/48.prim_lfsr_fib_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.1204657018
Short name T160
Test name
Test status
Simulation time 1575650000 ps
CPU time 2.08 seconds
Started Sep 04 10:05:58 AM UTC 24
Finished Sep 04 10:06:09 AM UTC 24
Peak memory 177504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1204657018 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.1204657018
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/49.prim_lfsr_fib_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.2827104646
Short name T24
Test name
Test status
Simulation time 1425130000 ps
CPU time 2.14 seconds
Started Sep 04 10:05:40 AM UTC 24
Finished Sep 04 10:05:51 AM UTC 24
Peak memory 177772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2827104646 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.2827104646
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/5.prim_lfsr_fib_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.1774940483
Short name T27
Test name
Test status
Simulation time 1398230000 ps
CPU time 1.96 seconds
Started Sep 04 10:05:41 AM UTC 24
Finished Sep 04 10:05:52 AM UTC 24
Peak memory 177772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1774940483 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.1774940483
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/6.prim_lfsr_fib_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.1130263312
Short name T28
Test name
Test status
Simulation time 1458170000 ps
CPU time 1.95 seconds
Started Sep 04 10:05:41 AM UTC 24
Finished Sep 04 10:05:52 AM UTC 24
Peak memory 177772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1130263312 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.1130263312
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/7.prim_lfsr_fib_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.3797894301
Short name T121
Test name
Test status
Simulation time 1673990000 ps
CPU time 2.24 seconds
Started Sep 04 10:05:42 AM UTC 24
Finished Sep 04 10:05:54 AM UTC 24
Peak memory 177772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3797894301 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.3797894301
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/8.prim_lfsr_fib_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2586371464
Short name T29
Test name
Test status
Simulation time 1559330000 ps
CPU time 2.36 seconds
Started Sep 04 10:05:42 AM UTC 24
Finished Sep 04 10:05:53 AM UTC 24
Peak memory 177772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2586371464 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.2586371464
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/9.prim_lfsr_fib_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.3143929909
Short name T2
Test name
Test status
Simulation time 1462390000 ps
CPU time 1.95 seconds
Started Sep 04 08:38:41 AM UTC 24
Finished Sep 04 08:38:52 AM UTC 24
Peak memory 177772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3143929909 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.3143929909
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/1.prim_lfsr_gal_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.166745138
Short name T43
Test name
Test status
Simulation time 1556050000 ps
CPU time 2.18 seconds
Started Sep 04 08:38:42 AM UTC 24
Finished Sep 04 08:38:55 AM UTC 24
Peak memory 177768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=166745138 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g
al.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.166745138
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/10.prim_lfsr_gal_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.98369619
Short name T49
Test name
Test status
Simulation time 1544150000 ps
CPU time 2.32 seconds
Started Sep 04 08:38:43 AM UTC 24
Finished Sep 04 08:38:56 AM UTC 24
Peak memory 177772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=98369619 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ga
l.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.98369619
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/11.prim_lfsr_gal_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.268280347
Short name T46
Test name
Test status
Simulation time 1503730000 ps
CPU time 2.25 seconds
Started Sep 04 08:38:43 AM UTC 24
Finished Sep 04 08:38:55 AM UTC 24
Peak memory 177768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=268280347 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g
al.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.268280347
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/12.prim_lfsr_gal_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.3287868150
Short name T42
Test name
Test status
Simulation time 1364450000 ps
CPU time 2.13 seconds
Started Sep 04 08:38:43 AM UTC 24
Finished Sep 04 08:38:55 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3287868150 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.3287868150
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/13.prim_lfsr_gal_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.3713327150
Short name T47
Test name
Test status
Simulation time 1492110000 ps
CPU time 2.32 seconds
Started Sep 04 08:38:43 AM UTC 24
Finished Sep 04 08:38:55 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3713327150 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.3713327150
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/14.prim_lfsr_gal_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.1579068642
Short name T41
Test name
Test status
Simulation time 1352890000 ps
CPU time 1.99 seconds
Started Sep 04 08:38:43 AM UTC 24
Finished Sep 04 08:38:55 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1579068642 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.1579068642
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/15.prim_lfsr_gal_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.3898283510
Short name T48
Test name
Test status
Simulation time 1492890000 ps
CPU time 1.98 seconds
Started Sep 04 08:38:43 AM UTC 24
Finished Sep 04 08:38:56 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3898283510 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.3898283510
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/16.prim_lfsr_gal_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.3072374425
Short name T50
Test name
Test status
Simulation time 1545970000 ps
CPU time 2.25 seconds
Started Sep 04 08:38:44 AM UTC 24
Finished Sep 04 08:38:56 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3072374425 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.3072374425
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/17.prim_lfsr_gal_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.2309939044
Short name T44
Test name
Test status
Simulation time 1262830000 ps
CPU time 2.03 seconds
Started Sep 04 08:38:45 AM UTC 24
Finished Sep 04 08:38:55 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2309939044 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.2309939044
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/18.prim_lfsr_gal_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.1048894062
Short name T51
Test name
Test status
Simulation time 1400050000 ps
CPU time 2.12 seconds
Started Sep 04 08:38:45 AM UTC 24
Finished Sep 04 08:38:56 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1048894062 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.1048894062
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/19.prim_lfsr_gal_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.4235469520
Short name T3
Test name
Test status
Simulation time 1566810000 ps
CPU time 2.29 seconds
Started Sep 04 08:38:41 AM UTC 24
Finished Sep 04 08:38:53 AM UTC 24
Peak memory 177772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4235469520 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.4235469520
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/2.prim_lfsr_gal_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.2389126513
Short name T52
Test name
Test status
Simulation time 1485430000 ps
CPU time 2.07 seconds
Started Sep 04 08:38:45 AM UTC 24
Finished Sep 04 08:38:56 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2389126513 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.2389126513
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/20.prim_lfsr_gal_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.1786779087
Short name T53
Test name
Test status
Simulation time 1483990000 ps
CPU time 2.09 seconds
Started Sep 04 08:38:45 AM UTC 24
Finished Sep 04 08:38:57 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1786779087 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.1786779087
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/21.prim_lfsr_gal_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.410394062
Short name T45
Test name
Test status
Simulation time 1269250000 ps
CPU time 2 seconds
Started Sep 04 08:38:45 AM UTC 24
Finished Sep 04 08:38:55 AM UTC 24
Peak memory 177768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=410394062 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g
al.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.410394062
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/22.prim_lfsr_gal_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.106829597
Short name T54
Test name
Test status
Simulation time 1542350000 ps
CPU time 2.21 seconds
Started Sep 04 08:38:46 AM UTC 24
Finished Sep 04 08:38:58 AM UTC 24
Peak memory 177768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=106829597 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g
al.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.106829597
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/23.prim_lfsr_gal_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.3085449656
Short name T56
Test name
Test status
Simulation time 1597570000 ps
CPU time 2.3 seconds
Started Sep 04 08:38:48 AM UTC 24
Finished Sep 04 08:39:00 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3085449656 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.3085449656
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/24.prim_lfsr_gal_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.1748120042
Short name T57
Test name
Test status
Simulation time 1615570000 ps
CPU time 2.34 seconds
Started Sep 04 08:38:50 AM UTC 24
Finished Sep 04 08:39:03 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1748120042 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.1748120042
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/25.prim_lfsr_gal_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.3857766089
Short name T55
Test name
Test status
Simulation time 1080130000 ps
CPU time 1.72 seconds
Started Sep 04 08:38:51 AM UTC 24
Finished Sep 04 08:39:00 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3857766089 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.3857766089
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/26.prim_lfsr_gal_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.1626015840
Short name T59
Test name
Test status
Simulation time 1567650000 ps
CPU time 2.06 seconds
Started Sep 04 08:38:52 AM UTC 24
Finished Sep 04 08:39:04 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1626015840 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.1626015840
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/27.prim_lfsr_gal_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.1398307543
Short name T58
Test name
Test status
Simulation time 1391750000 ps
CPU time 2.05 seconds
Started Sep 04 08:38:52 AM UTC 24
Finished Sep 04 08:39:03 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1398307543 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.1398307543
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/28.prim_lfsr_gal_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.3593286864
Short name T60
Test name
Test status
Simulation time 1472230000 ps
CPU time 2.26 seconds
Started Sep 04 08:38:53 AM UTC 24
Finished Sep 04 08:39:05 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3593286864 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.3593286864
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/29.prim_lfsr_gal_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.1596554360
Short name T8
Test name
Test status
Simulation time 1412050000 ps
CPU time 2.19 seconds
Started Sep 04 08:38:42 AM UTC 24
Finished Sep 04 08:38:53 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1596554360 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.1596554360
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/3.prim_lfsr_gal_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.3124992998
Short name T61
Test name
Test status
Simulation time 1387910000 ps
CPU time 2.11 seconds
Started Sep 04 08:38:54 AM UTC 24
Finished Sep 04 08:39:05 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3124992998 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.3124992998
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/30.prim_lfsr_gal_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.3908352988
Short name T64
Test name
Test status
Simulation time 1559310000 ps
CPU time 2.17 seconds
Started Sep 04 08:38:54 AM UTC 24
Finished Sep 04 08:39:07 AM UTC 24
Peak memory 177776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3908352988 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.3908352988
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/31.prim_lfsr_gal_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.1828489035
Short name T62
Test name
Test status
Simulation time 1448190000 ps
CPU time 2 seconds
Started Sep 04 08:38:54 AM UTC 24
Finished Sep 04 08:39:06 AM UTC 24
Peak memory 177668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1828489035 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.1828489035
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/32.prim_lfsr_gal_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.605032063
Short name T65
Test name
Test status
Simulation time 1560730000 ps
CPU time 2.18 seconds
Started Sep 04 08:38:54 AM UTC 24
Finished Sep 04 08:39:07 AM UTC 24
Peak memory 177768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=605032063 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g
al.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.605032063
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/33.prim_lfsr_gal_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.3079378057
Short name T63
Test name
Test status
Simulation time 1544950000 ps
CPU time 2.04 seconds
Started Sep 04 08:38:54 AM UTC 24
Finished Sep 04 08:39:07 AM UTC 24
Peak memory 177724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3079378057 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.3079378057
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/34.prim_lfsr_gal_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.1602947297
Short name T66
Test name
Test status
Simulation time 1442950000 ps
CPU time 2.06 seconds
Started Sep 04 08:38:55 AM UTC 24
Finished Sep 04 08:39:07 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1602947297 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.1602947297
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/35.prim_lfsr_gal_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.3856122035
Short name T69
Test name
Test status
Simulation time 1463650000 ps
CPU time 2.02 seconds
Started Sep 04 08:38:55 AM UTC 24
Finished Sep 04 08:39:07 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3856122035 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.3856122035
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/36.prim_lfsr_gal_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.3297690010
Short name T74
Test name
Test status
Simulation time 1571950000 ps
CPU time 2.34 seconds
Started Sep 04 08:38:55 AM UTC 24
Finished Sep 04 08:39:08 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3297690010 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.3297690010
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/37.prim_lfsr_gal_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.2592236338
Short name T67
Test name
Test status
Simulation time 1428490000 ps
CPU time 1.96 seconds
Started Sep 04 08:38:56 AM UTC 24
Finished Sep 04 08:39:07 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2592236338 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.2592236338
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/38.prim_lfsr_gal_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.3969530125
Short name T68
Test name
Test status
Simulation time 1431310000 ps
CPU time 2.15 seconds
Started Sep 04 08:38:56 AM UTC 24
Finished Sep 04 08:39:07 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3969530125 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.3969530125
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/39.prim_lfsr_gal_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.2790316008
Short name T13
Test name
Test status
Simulation time 1568590000 ps
CPU time 2.36 seconds
Started Sep 04 08:38:42 AM UTC 24
Finished Sep 04 08:38:55 AM UTC 24
Peak memory 177772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2790316008 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.2790316008
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/4.prim_lfsr_gal_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.2310268012
Short name T72
Test name
Test status
Simulation time 1527830000 ps
CPU time 2.2 seconds
Started Sep 04 08:38:56 AM UTC 24
Finished Sep 04 08:39:08 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2310268012 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.2310268012
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/40.prim_lfsr_gal_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.1621062527
Short name T73
Test name
Test status
Simulation time 1535850000 ps
CPU time 2.17 seconds
Started Sep 04 08:38:56 AM UTC 24
Finished Sep 04 08:39:08 AM UTC 24
Peak memory 177800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1621062527 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.1621062527
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/41.prim_lfsr_gal_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.4046722586
Short name T71
Test name
Test status
Simulation time 1530170000 ps
CPU time 2.01 seconds
Started Sep 04 08:38:56 AM UTC 24
Finished Sep 04 08:39:08 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4046722586 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.4046722586
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/42.prim_lfsr_gal_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.4026544375
Short name T70
Test name
Test status
Simulation time 1439390000 ps
CPU time 2.15 seconds
Started Sep 04 08:38:56 AM UTC 24
Finished Sep 04 08:39:07 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4026544375 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.4026544375
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/43.prim_lfsr_gal_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.515585626
Short name T75
Test name
Test status
Simulation time 1498570000 ps
CPU time 2.22 seconds
Started Sep 04 08:38:57 AM UTC 24
Finished Sep 04 08:39:09 AM UTC 24
Peak memory 177768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=515585626 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g
al.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.515585626
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/44.prim_lfsr_gal_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.3609001569
Short name T79
Test name
Test status
Simulation time 1548690000 ps
CPU time 2.14 seconds
Started Sep 04 08:38:57 AM UTC 24
Finished Sep 04 08:39:09 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3609001569 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.3609001569
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/45.prim_lfsr_gal_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.1565417415
Short name T78
Test name
Test status
Simulation time 1529830000 ps
CPU time 2.24 seconds
Started Sep 04 08:38:57 AM UTC 24
Finished Sep 04 08:39:09 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1565417415 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.1565417415
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/46.prim_lfsr_gal_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.1793113814
Short name T76
Test name
Test status
Simulation time 1484330000 ps
CPU time 2.11 seconds
Started Sep 04 08:38:57 AM UTC 24
Finished Sep 04 08:39:09 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1793113814 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.1793113814
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/47.prim_lfsr_gal_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.3331238435
Short name T80
Test name
Test status
Simulation time 1555850000 ps
CPU time 2.11 seconds
Started Sep 04 08:38:57 AM UTC 24
Finished Sep 04 08:39:09 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3331238435 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.3331238435
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/48.prim_lfsr_gal_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.1441212124
Short name T77
Test name
Test status
Simulation time 1507770000 ps
CPU time 2.06 seconds
Started Sep 04 08:38:57 AM UTC 24
Finished Sep 04 08:39:09 AM UTC 24
Peak memory 179144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1441212124 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.1441212124
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/49.prim_lfsr_gal_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.1815826901
Short name T11
Test name
Test status
Simulation time 1531770000 ps
CPU time 2.24 seconds
Started Sep 04 08:38:42 AM UTC 24
Finished Sep 04 08:38:54 AM UTC 24
Peak memory 177772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1815826901 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.1815826901
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/5.prim_lfsr_gal_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.150458493
Short name T12
Test name
Test status
Simulation time 1553490000 ps
CPU time 2.14 seconds
Started Sep 04 08:38:42 AM UTC 24
Finished Sep 04 08:38:54 AM UTC 24
Peak memory 177804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=150458493 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g
al.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.150458493
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/6.prim_lfsr_gal_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.3495571122
Short name T9
Test name
Test status
Simulation time 1390250000 ps
CPU time 2.08 seconds
Started Sep 04 08:38:42 AM UTC 24
Finished Sep 04 08:38:53 AM UTC 24
Peak memory 177772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3495571122 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.3495571122
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/7.prim_lfsr_gal_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.1291085778
Short name T7
Test name
Test status
Simulation time 1355970000 ps
CPU time 2.04 seconds
Started Sep 04 08:38:42 AM UTC 24
Finished Sep 04 08:38:53 AM UTC 24
Peak memory 177772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1291085778 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.1291085778
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/8.prim_lfsr_gal_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.2416320179
Short name T10
Test name
Test status
Simulation time 1472110000 ps
CPU time 2.05 seconds
Started Sep 04 08:38:42 AM UTC 24
Finished Sep 04 08:38:54 AM UTC 24
Peak memory 177772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2416320179 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.2416320179
Directory /workspaces/repo/scratch/os_regression_2024_09_03/prim_lfsr-sim-vcs/9.prim_lfsr_gal_smoke/latest
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