SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
98.31 | 100.00 | 96.55 | 100.00 | 100.00 | 95.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
87.31 | 87.31 | 100.00 | 100.00 | 96.55 | 96.55 | 100.00 | 100.00 | 100.00 | 100.00 | 40.00 | 40.00 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.2785315121 | ||
95.31 | 8.00 | 100.00 | 0.00 | 96.55 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 80.00 | 40.00 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.623192632 | ||
96.81 | 1.50 | 100.00 | 0.00 | 96.55 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 87.50 | 7.50 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.2777809942 | ||
98.31 | 1.50 | 100.00 | 0.00 | 96.55 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 95.00 | 7.50 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.3294286297 |
Name |
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/workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.4284793102 |
/workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.1643155810 |
/workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.3897564715 |
/workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.1251137582 |
/workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.574877064 |
/workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.392760008 |
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/workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.3870997949 |
/workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.3012511765 |
/workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2964415499 |
/workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.788290062 |
/workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.3261854080 |
/workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.3321151776 |
/workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.3098334234 |
/workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.4082703242 |
/workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.530888424 |
/workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.1567361795 |
/workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.637884515 |
/workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.2690861938 |
/workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.2663628018 |
/workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.1019300553 |
/workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.511652220 |
/workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.2921830834 |
/workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.925566904 |
/workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.2045653569 |
/workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.2611272571 |
/workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.1006458084 |
/workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.3792537644 |
/workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.926087840 |
/workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.2117523817 |
/workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.362533629 |
/workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.1472360812 |
/workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.2726746635 |
/workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.1556292276 |
/workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.3918622206 |
/workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.3197115074 |
/workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.3480950035 |
/workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.695627368 |
/workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.2092746588 |
/workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.3990337700 |
/workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.1207566524 |
/workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.1185185592 |
/workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.405866562 |
/workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.2340577676 |
/workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.4120686747 |
/workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.344800314 |
/workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.3548523154 |
/workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.234840467 |
/workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.795490176 |
/workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.2655681260 |
/workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.1363949063 |
/workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.436101585 |
/workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.2036912841 |
/workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.670192386 |
/workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.3897778920 |
/workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.1816651332 |
/workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.4044178213 |
/workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.3178351946 |
/workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.1512146471 |
/workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.2267891804 |
/workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.743010257 |
/workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.1540426948 |
/workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.365760757 |
/workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.320952240 |
/workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.1609812457 |
/workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.2982703833 |
/workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.1965646247 |
/workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.154799047 |
/workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.2768949365 |
/workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.2943844557 |
/workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.3667325185 |
/workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.2161884585 |
/workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.3325173626 |
/workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.757543971 |
/workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.4006136773 |
/workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.4227577413 |
/workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.1154173279 |
/workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.675388050 |
/workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.1117031478 |
/workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.1850258763 |
/workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.323551148 |
/workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.2588769515 |
/workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.2361934341 |
/workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.3833864006 |
/workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.4095435352 |
/workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.3900393285 |
/workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.3822296903 |
/workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.1433069273 |
/workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.1660350093 |
TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
---|---|---|---|---|---|---|
T1 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.2785315121 | Sep 09 02:54:55 AM UTC 24 | Sep 09 02:55:06 AM UTC 24 | 1224170000 ps | ||
T2 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.1660350093 | Sep 09 02:54:57 AM UTC 24 | Sep 09 02:55:08 AM UTC 24 | 1244350000 ps | ||
T3 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.436101585 | Sep 09 02:54:56 AM UTC 24 | Sep 09 02:55:09 AM UTC 24 | 1436890000 ps | ||
T7 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.3900393285 | Sep 09 02:54:56 AM UTC 24 | Sep 09 02:55:09 AM UTC 24 | 1408730000 ps | ||
T8 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.365760757 | Sep 09 02:54:56 AM UTC 24 | Sep 09 02:55:09 AM UTC 24 | 1511330000 ps | ||
T9 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.1207566524 | Sep 09 02:54:56 AM UTC 24 | Sep 09 02:55:10 AM UTC 24 | 1569010000 ps | ||
T10 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.1433069273 | Sep 09 02:54:57 AM UTC 24 | Sep 09 02:55:10 AM UTC 24 | 1430930000 ps | ||
T11 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.757543971 | Sep 09 02:54:56 AM UTC 24 | Sep 09 02:55:10 AM UTC 24 | 1586770000 ps | ||
T12 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.344800314 | Sep 09 02:55:00 AM UTC 24 | Sep 09 02:55:10 AM UTC 24 | 1114690000 ps | ||
T13 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.4095435352 | Sep 09 02:54:56 AM UTC 24 | Sep 09 02:55:10 AM UTC 24 | 1603130000 ps | ||
T41 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.2340577676 | Sep 09 02:54:57 AM UTC 24 | Sep 09 02:55:10 AM UTC 24 | 1436490000 ps | ||
T42 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.3822296903 | Sep 09 02:54:57 AM UTC 24 | Sep 09 02:55:11 AM UTC 24 | 1544470000 ps | ||
T43 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.1185185592 | Sep 09 02:54:57 AM UTC 24 | Sep 09 02:55:11 AM UTC 24 | 1577230000 ps | ||
T44 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.405866562 | Sep 09 02:54:57 AM UTC 24 | Sep 09 02:55:11 AM UTC 24 | 1605850000 ps | ||
T45 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.4120686747 | Sep 09 02:54:59 AM UTC 24 | Sep 09 02:55:12 AM UTC 24 | 1526270000 ps | ||
T46 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.234840467 | Sep 09 02:55:01 AM UTC 24 | Sep 09 02:55:12 AM UTC 24 | 1237150000 ps | ||
T47 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.3548523154 | Sep 09 02:55:00 AM UTC 24 | Sep 09 02:55:13 AM UTC 24 | 1592230000 ps | ||
T48 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.795490176 | Sep 09 02:55:04 AM UTC 24 | Sep 09 02:55:14 AM UTC 24 | 1107530000 ps | ||
T49 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.2655681260 | Sep 09 02:55:05 AM UTC 24 | Sep 09 02:55:17 AM UTC 24 | 1491710000 ps | ||
T50 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.1363949063 | Sep 09 02:55:07 AM UTC 24 | Sep 09 02:55:20 AM UTC 24 | 1605370000 ps | ||
T51 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.2036912841 | Sep 09 02:55:09 AM UTC 24 | Sep 09 02:55:21 AM UTC 24 | 1420970000 ps | ||
T52 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.670192386 | Sep 09 02:55:09 AM UTC 24 | Sep 09 02:55:21 AM UTC 24 | 1485110000 ps | ||
T53 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.320952240 | Sep 09 02:55:12 AM UTC 24 | Sep 09 02:55:22 AM UTC 24 | 1158350000 ps | ||
T54 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.3897778920 | Sep 09 02:55:09 AM UTC 24 | Sep 09 02:55:22 AM UTC 24 | 1553950000 ps | ||
T55 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.2267891804 | Sep 09 02:55:10 AM UTC 24 | Sep 09 02:55:23 AM UTC 24 | 1461130000 ps | ||
T56 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.1512146471 | Sep 09 02:55:10 AM UTC 24 | Sep 09 02:55:23 AM UTC 24 | 1459150000 ps | ||
T57 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.3178351946 | Sep 09 02:55:10 AM UTC 24 | Sep 09 02:55:23 AM UTC 24 | 1510150000 ps | ||
T58 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.1816651332 | Sep 09 02:55:10 AM UTC 24 | Sep 09 02:55:23 AM UTC 24 | 1572250000 ps | ||
T59 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.4044178213 | Sep 09 02:55:10 AM UTC 24 | Sep 09 02:55:23 AM UTC 24 | 1572130000 ps | ||
T60 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.1540426948 | Sep 09 02:55:12 AM UTC 24 | Sep 09 02:55:24 AM UTC 24 | 1447730000 ps | ||
T61 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.743010257 | Sep 09 02:55:12 AM UTC 24 | Sep 09 02:55:24 AM UTC 24 | 1465090000 ps | ||
T62 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.1609812457 | Sep 09 02:55:12 AM UTC 24 | Sep 09 02:55:24 AM UTC 24 | 1536270000 ps | ||
T63 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.1965646247 | Sep 09 02:55:13 AM UTC 24 | Sep 09 02:55:25 AM UTC 24 | 1432430000 ps | ||
T64 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.2982703833 | Sep 09 02:55:12 AM UTC 24 | Sep 09 02:55:25 AM UTC 24 | 1596810000 ps | ||
T65 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.154799047 | Sep 09 02:55:13 AM UTC 24 | Sep 09 02:55:25 AM UTC 24 | 1534890000 ps | ||
T66 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.2768949365 | Sep 09 02:55:14 AM UTC 24 | Sep 09 02:55:26 AM UTC 24 | 1538090000 ps | ||
T67 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.2943844557 | Sep 09 02:55:14 AM UTC 24 | Sep 09 02:55:26 AM UTC 24 | 1541610000 ps | ||
T68 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.3667325185 | Sep 09 02:55:15 AM UTC 24 | Sep 09 02:55:27 AM UTC 24 | 1453570000 ps | ||
T69 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.2161884585 | Sep 09 02:55:18 AM UTC 24 | Sep 09 02:55:29 AM UTC 24 | 1370790000 ps | ||
T70 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.1154173279 | Sep 09 02:55:22 AM UTC 24 | Sep 09 02:55:32 AM UTC 24 | 1249350000 ps | ||
T71 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.3325173626 | Sep 09 02:55:21 AM UTC 24 | Sep 09 02:55:33 AM UTC 24 | 1471390000 ps | ||
T72 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.675388050 | Sep 09 02:55:22 AM UTC 24 | Sep 09 02:55:33 AM UTC 24 | 1424770000 ps | ||
T73 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.1850258763 | Sep 09 02:55:23 AM UTC 24 | Sep 09 02:55:33 AM UTC 24 | 1284070000 ps | ||
T74 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.4006136773 | Sep 09 02:55:22 AM UTC 24 | Sep 09 02:55:33 AM UTC 24 | 1452470000 ps | ||
T75 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.1117031478 | Sep 09 02:55:23 AM UTC 24 | Sep 09 02:55:34 AM UTC 24 | 1363190000 ps | ||
T76 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.323551148 | Sep 09 02:55:23 AM UTC 24 | Sep 09 02:55:34 AM UTC 24 | 1398690000 ps | ||
T77 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.2588769515 | Sep 09 02:55:23 AM UTC 24 | Sep 09 02:55:34 AM UTC 24 | 1419750000 ps | ||
T78 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.4227577413 | Sep 09 02:55:22 AM UTC 24 | Sep 09 02:55:34 AM UTC 24 | 1634950000 ps | ||
T79 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.3833864006 | Sep 09 02:55:25 AM UTC 24 | Sep 09 02:55:35 AM UTC 24 | 1299270000 ps | ||
T80 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.2361934341 | Sep 09 02:55:25 AM UTC 24 | Sep 09 02:55:36 AM UTC 24 | 1529910000 ps | ||
T14 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.623192632 | Sep 09 03:09:15 AM UTC 24 | Sep 09 03:41:05 AM UTC 24 | 336425950000 ps | ||
T15 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.4140249963 | Sep 09 03:09:15 AM UTC 24 | Sep 09 03:41:06 AM UTC 24 | 336583530000 ps | ||
T16 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.3488183777 | Sep 09 03:09:15 AM UTC 24 | Sep 09 03:41:06 AM UTC 24 | 336650970000 ps | ||
T17 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.3096779111 | Sep 09 03:09:15 AM UTC 24 | Sep 09 03:41:08 AM UTC 24 | 336617890000 ps | ||
T18 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.953028050 | Sep 09 03:09:15 AM UTC 24 | Sep 09 03:41:08 AM UTC 24 | 336478310000 ps | ||
T19 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.660004684 | Sep 09 03:09:16 AM UTC 24 | Sep 09 03:41:09 AM UTC 24 | 336624910000 ps | ||
T20 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.521181107 | Sep 09 03:09:16 AM UTC 24 | Sep 09 03:41:09 AM UTC 24 | 336742830000 ps | ||
T21 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.2692244293 | Sep 09 03:09:16 AM UTC 24 | Sep 09 03:41:09 AM UTC 24 | 336459530000 ps | ||
T22 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.700312304 | Sep 09 03:09:16 AM UTC 24 | Sep 09 03:41:09 AM UTC 24 | 336839010000 ps | ||
T23 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.146191339 | Sep 09 03:09:17 AM UTC 24 | Sep 09 03:41:10 AM UTC 24 | 336691170000 ps | ||
T81 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.677162422 | Sep 09 03:09:16 AM UTC 24 | Sep 09 03:41:11 AM UTC 24 | 336887750000 ps | ||
T82 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.1486905993 | Sep 09 03:09:18 AM UTC 24 | Sep 09 03:41:12 AM UTC 24 | 336409490000 ps | ||
T83 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.1258514324 | Sep 09 03:09:16 AM UTC 24 | Sep 09 03:41:12 AM UTC 24 | 337138030000 ps | ||
T84 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.2032942317 | Sep 09 03:09:18 AM UTC 24 | Sep 09 03:41:12 AM UTC 24 | 336503110000 ps | ||
T85 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.1761868856 | Sep 09 03:09:18 AM UTC 24 | Sep 09 03:41:13 AM UTC 24 | 336446810000 ps | ||
T86 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.340800056 | Sep 09 03:09:18 AM UTC 24 | Sep 09 03:41:13 AM UTC 24 | 336859010000 ps | ||
T87 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.1372527840 | Sep 09 03:09:19 AM UTC 24 | Sep 09 03:41:14 AM UTC 24 | 336767790000 ps | ||
T88 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.1186521816 | Sep 09 03:09:19 AM UTC 24 | Sep 09 03:41:18 AM UTC 24 | 337081570000 ps | ||
T89 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.2260750183 | Sep 09 03:09:23 AM UTC 24 | Sep 09 03:41:21 AM UTC 24 | 336812850000 ps | ||
T90 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.3306501845 | Sep 09 03:09:25 AM UTC 24 | Sep 09 03:41:23 AM UTC 24 | 336790790000 ps | ||
T91 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.340664276 | Sep 09 03:09:31 AM UTC 24 | Sep 09 03:41:30 AM UTC 24 | 336761290000 ps | ||
T92 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.279462652 | Sep 09 03:09:37 AM UTC 24 | Sep 09 03:41:34 AM UTC 24 | 336510630000 ps | ||
T93 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.496122141 | Sep 09 03:09:37 AM UTC 24 | Sep 09 03:41:35 AM UTC 24 | 336541650000 ps | ||
T94 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.431108417 | Sep 09 03:09:37 AM UTC 24 | Sep 09 03:41:38 AM UTC 24 | 336498730000 ps | ||
T95 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.2144678785 | Sep 09 03:09:37 AM UTC 24 | Sep 09 03:41:40 AM UTC 24 | 336977350000 ps | ||
T96 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.303738222 | Sep 09 03:09:45 AM UTC 24 | Sep 09 03:41:52 AM UTC 24 | 337088350000 ps | ||
T97 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.3490890947 | Sep 09 03:09:46 AM UTC 24 | Sep 09 03:41:55 AM UTC 24 | 337130810000 ps | ||
T98 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.2444443602 | Sep 09 03:09:53 AM UTC 24 | Sep 09 03:42:01 AM UTC 24 | 336572690000 ps | ||
T99 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.2009841134 | Sep 09 03:09:52 AM UTC 24 | Sep 09 03:42:02 AM UTC 24 | 337051850000 ps | ||
T100 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.2730564910 | Sep 09 03:09:53 AM UTC 24 | Sep 09 03:42:03 AM UTC 24 | 336487330000 ps | ||
T101 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.2605233545 | Sep 09 03:09:52 AM UTC 24 | Sep 09 03:42:04 AM UTC 24 | 336835410000 ps | ||
T102 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.1238731392 | Sep 09 03:09:53 AM UTC 24 | Sep 09 03:42:04 AM UTC 24 | 337057150000 ps | ||
T103 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.1167180449 | Sep 09 03:09:53 AM UTC 24 | Sep 09 03:42:05 AM UTC 24 | 336806530000 ps | ||
T104 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.3192061277 | Sep 09 03:09:53 AM UTC 24 | Sep 09 03:42:05 AM UTC 24 | 336561470000 ps | ||
T105 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.3421005286 | Sep 09 03:09:53 AM UTC 24 | Sep 09 03:42:05 AM UTC 24 | 336960910000 ps | ||
T106 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.276333353 | Sep 09 03:09:56 AM UTC 24 | Sep 09 03:42:05 AM UTC 24 | 336566290000 ps | ||
T107 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.3963747380 | Sep 09 03:09:56 AM UTC 24 | Sep 09 03:42:06 AM UTC 24 | 336509350000 ps | ||
T108 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.2557491276 | Sep 09 03:09:56 AM UTC 24 | Sep 09 03:42:06 AM UTC 24 | 336617090000 ps | ||
T109 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.755585091 | Sep 09 03:09:55 AM UTC 24 | Sep 09 03:42:07 AM UTC 24 | 336815210000 ps | ||
T110 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.1661342151 | Sep 09 03:09:53 AM UTC 24 | Sep 09 03:42:07 AM UTC 24 | 337002610000 ps | ||
T111 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.2775619790 | Sep 09 03:09:54 AM UTC 24 | Sep 09 03:42:08 AM UTC 24 | 337125010000 ps | ||
T112 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.442430376 | Sep 09 03:09:56 AM UTC 24 | Sep 09 03:42:08 AM UTC 24 | 336992670000 ps | ||
T113 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.1598887795 | Sep 09 03:09:53 AM UTC 24 | Sep 09 03:42:08 AM UTC 24 | 337057230000 ps | ||
T114 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.2984862520 | Sep 09 03:09:58 AM UTC 24 | Sep 09 03:42:08 AM UTC 24 | 336603210000 ps | ||
T115 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.2246039493 | Sep 09 03:09:55 AM UTC 24 | Sep 09 03:42:08 AM UTC 24 | 336862850000 ps | ||
T116 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.2404668831 | Sep 09 03:09:58 AM UTC 24 | Sep 09 03:42:09 AM UTC 24 | 336524330000 ps | ||
T117 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.180346909 | Sep 09 03:09:56 AM UTC 24 | Sep 09 03:42:10 AM UTC 24 | 336967270000 ps | ||
T118 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.3160622372 | Sep 09 03:09:57 AM UTC 24 | Sep 09 03:42:10 AM UTC 24 | 336684770000 ps | ||
T119 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.4185284242 | Sep 09 03:09:58 AM UTC 24 | Sep 09 03:42:13 AM UTC 24 | 337107790000 ps | ||
T120 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.190514255 | Sep 09 03:09:58 AM UTC 24 | Sep 09 03:42:14 AM UTC 24 | 336914030000 ps | ||
T4 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.2248808742 | Sep 09 07:09:06 AM UTC 24 | Sep 09 07:09:15 AM UTC 24 | 1275950000 ps | ||
T5 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.998862552 | Sep 09 07:09:06 AM UTC 24 | Sep 09 07:09:16 AM UTC 24 | 1382670000 ps | ||
T6 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.2045653569 | Sep 09 07:09:06 AM UTC 24 | Sep 09 07:09:16 AM UTC 24 | 1383250000 ps | ||
T24 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.3294286297 | Sep 09 07:09:06 AM UTC 24 | Sep 09 07:09:16 AM UTC 24 | 1506590000 ps | ||
T25 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.3098334234 | Sep 09 07:09:06 AM UTC 24 | Sep 09 07:09:17 AM UTC 24 | 1533550000 ps | ||
T26 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.3197115074 | Sep 09 07:09:06 AM UTC 24 | Sep 09 07:09:17 AM UTC 24 | 1548690000 ps | ||
T27 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.3480950035 | Sep 09 07:09:06 AM UTC 24 | Sep 09 07:09:17 AM UTC 24 | 1567750000 ps | ||
T28 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.2274144299 | Sep 09 07:09:12 AM UTC 24 | Sep 09 07:09:21 AM UTC 24 | 1110970000 ps | ||
T29 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.3870997949 | Sep 09 07:09:12 AM UTC 24 | Sep 09 07:09:21 AM UTC 24 | 1124570000 ps | ||
T30 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.3153940648 | Sep 09 07:09:12 AM UTC 24 | Sep 09 07:09:21 AM UTC 24 | 1218350000 ps | ||
T121 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.726111763 | Sep 09 07:09:12 AM UTC 24 | Sep 09 07:09:22 AM UTC 24 | 1274310000 ps | ||
T122 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.2092746588 | Sep 09 07:09:12 AM UTC 24 | Sep 09 07:09:22 AM UTC 24 | 1353650000 ps | ||
T123 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.695627368 | Sep 09 07:09:12 AM UTC 24 | Sep 09 07:09:22 AM UTC 24 | 1400550000 ps | ||
T124 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.1075636313 | Sep 09 07:09:12 AM UTC 24 | Sep 09 07:09:22 AM UTC 24 | 1367990000 ps | ||
T125 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.242305655 | Sep 09 07:09:12 AM UTC 24 | Sep 09 07:09:22 AM UTC 24 | 1376910000 ps | ||
T126 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.3834719306 | Sep 09 07:09:12 AM UTC 24 | Sep 09 07:09:23 AM UTC 24 | 1417230000 ps | ||
T127 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.2314799413 | Sep 09 07:09:12 AM UTC 24 | Sep 09 07:09:23 AM UTC 24 | 1481930000 ps | ||
T128 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.3990337700 | Sep 09 07:09:12 AM UTC 24 | Sep 09 07:09:23 AM UTC 24 | 1518910000 ps | ||
T129 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.3261854080 | Sep 09 07:09:13 AM UTC 24 | Sep 09 07:09:23 AM UTC 24 | 1419850000 ps | ||
T130 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.497096494 | Sep 09 07:09:12 AM UTC 24 | Sep 09 07:09:23 AM UTC 24 | 1504190000 ps | ||
T131 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.3012511765 | Sep 09 07:09:13 AM UTC 24 | Sep 09 07:09:23 AM UTC 24 | 1473570000 ps | ||
T132 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.2889431443 | Sep 09 07:09:12 AM UTC 24 | Sep 09 07:09:24 AM UTC 24 | 1559310000 ps | ||
T133 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.2438114793 | Sep 09 07:09:12 AM UTC 24 | Sep 09 07:09:24 AM UTC 24 | 1528350000 ps | ||
T134 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.3314046045 | Sep 09 07:09:12 AM UTC 24 | Sep 09 07:09:24 AM UTC 24 | 1529570000 ps | ||
T135 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3902648151 | Sep 09 07:09:12 AM UTC 24 | Sep 09 07:09:24 AM UTC 24 | 1555550000 ps | ||
T136 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.3058008024 | Sep 09 07:09:12 AM UTC 24 | Sep 09 07:09:24 AM UTC 24 | 1561890000 ps | ||
T137 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.29394863 | Sep 09 07:09:12 AM UTC 24 | Sep 09 07:09:24 AM UTC 24 | 1624230000 ps | ||
T138 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2964415499 | Sep 09 07:09:13 AM UTC 24 | Sep 09 07:09:24 AM UTC 24 | 1578770000 ps | ||
T139 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.788290062 | Sep 09 07:09:13 AM UTC 24 | Sep 09 07:09:24 AM UTC 24 | 1568470000 ps | ||
T140 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.530888424 | Sep 09 07:09:15 AM UTC 24 | Sep 09 07:09:25 AM UTC 24 | 1381830000 ps | ||
T141 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.4082703242 | Sep 09 07:09:15 AM UTC 24 | Sep 09 07:09:26 AM UTC 24 | 1515570000 ps | ||
T142 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.3321151776 | Sep 09 07:09:15 AM UTC 24 | Sep 09 07:09:26 AM UTC 24 | 1540210000 ps | ||
T143 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.1567361795 | Sep 09 07:09:15 AM UTC 24 | Sep 09 07:09:26 AM UTC 24 | 1591650000 ps | ||
T144 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.1019300553 | Sep 09 07:09:16 AM UTC 24 | Sep 09 07:09:27 AM UTC 24 | 1446610000 ps | ||
T145 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.2690861938 | Sep 09 07:09:16 AM UTC 24 | Sep 09 07:09:27 AM UTC 24 | 1473730000 ps | ||
T146 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.637884515 | Sep 09 07:09:16 AM UTC 24 | Sep 09 07:09:27 AM UTC 24 | 1534570000 ps | ||
T147 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.2663628018 | Sep 09 07:09:16 AM UTC 24 | Sep 09 07:09:27 AM UTC 24 | 1557890000 ps | ||
T148 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.2611272571 | Sep 09 07:09:17 AM UTC 24 | Sep 09 07:09:28 AM UTC 24 | 1416610000 ps | ||
T149 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.925566904 | Sep 09 07:09:17 AM UTC 24 | Sep 09 07:09:28 AM UTC 24 | 1452190000 ps | ||
T150 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.2921830834 | Sep 09 07:09:17 AM UTC 24 | Sep 09 07:09:28 AM UTC 24 | 1483610000 ps | ||
T151 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.511652220 | Sep 09 07:09:17 AM UTC 24 | Sep 09 07:09:28 AM UTC 24 | 1504330000 ps | ||
T152 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.1006458084 | Sep 09 07:09:21 AM UTC 24 | Sep 09 07:09:32 AM UTC 24 | 1496150000 ps | ||
T153 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.1472360812 | Sep 09 07:09:23 AM UTC 24 | Sep 09 07:09:32 AM UTC 24 | 1341510000 ps | ||
T154 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.1556292276 | Sep 09 07:09:23 AM UTC 24 | Sep 09 07:09:33 AM UTC 24 | 1346190000 ps | ||
T155 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.926087840 | Sep 09 07:09:23 AM UTC 24 | Sep 09 07:09:33 AM UTC 24 | 1437210000 ps | ||
T156 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.3792537644 | Sep 09 07:09:23 AM UTC 24 | Sep 09 07:09:33 AM UTC 24 | 1449170000 ps | ||
T157 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.3918622206 | Sep 09 07:09:23 AM UTC 24 | Sep 09 07:09:33 AM UTC 24 | 1516590000 ps | ||
T158 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.362533629 | Sep 09 07:09:23 AM UTC 24 | Sep 09 07:09:34 AM UTC 24 | 1563870000 ps | ||
T159 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.2726746635 | Sep 09 07:09:23 AM UTC 24 | Sep 09 07:09:34 AM UTC 24 | 1544150000 ps | ||
T160 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.2117523817 | Sep 09 07:09:23 AM UTC 24 | Sep 09 07:09:34 AM UTC 24 | 1586770000 ps | ||
T31 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.4270831230 | Sep 09 07:29:31 AM UTC 24 | Sep 09 08:03:42 AM UTC 24 | 336552590000 ps | ||
T32 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.2777809942 | Sep 09 07:29:31 AM UTC 24 | Sep 09 08:03:42 AM UTC 24 | 336763010000 ps | ||
T33 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.966488705 | Sep 09 07:29:31 AM UTC 24 | Sep 09 08:03:43 AM UTC 24 | 336731410000 ps | ||
T34 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.954676384 | Sep 09 07:29:31 AM UTC 24 | Sep 09 08:03:43 AM UTC 24 | 336793530000 ps | ||
T35 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.3513032043 | Sep 09 07:29:31 AM UTC 24 | Sep 09 08:03:44 AM UTC 24 | 336744210000 ps | ||
T36 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.3839530807 | Sep 09 07:29:31 AM UTC 24 | Sep 09 08:03:44 AM UTC 24 | 336888270000 ps | ||
T37 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.144955162 | Sep 09 07:29:38 AM UTC 24 | Sep 09 08:03:44 AM UTC 24 | 336790790000 ps | ||
T38 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.2385647569 | Sep 09 07:29:31 AM UTC 24 | Sep 09 08:03:44 AM UTC 24 | 336959210000 ps | ||
T39 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.3675073132 | Sep 09 07:29:31 AM UTC 24 | Sep 09 08:03:44 AM UTC 24 | 336998150000 ps | ||
T40 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.3897564715 | Sep 09 07:29:38 AM UTC 24 | Sep 09 08:03:44 AM UTC 24 | 336811050000 ps | ||
T161 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.1643155810 | Sep 09 07:29:38 AM UTC 24 | Sep 09 08:03:44 AM UTC 24 | 336835850000 ps | ||
T162 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.4284793102 | Sep 09 07:29:38 AM UTC 24 | Sep 09 08:03:45 AM UTC 24 | 337112430000 ps | ||
T163 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.4208181223 | Sep 09 07:29:31 AM UTC 24 | Sep 09 08:03:45 AM UTC 24 | 337017950000 ps | ||
T164 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.384820472 | Sep 09 07:29:39 AM UTC 24 | Sep 09 08:03:45 AM UTC 24 | 336354850000 ps | ||
T165 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.4179311104 | Sep 09 07:29:39 AM UTC 24 | Sep 09 08:03:46 AM UTC 24 | 336319530000 ps | ||
T166 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.4115103705 | Sep 09 07:29:38 AM UTC 24 | Sep 09 08:03:46 AM UTC 24 | 336485850000 ps | ||
T167 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.3771026717 | Sep 09 07:29:42 AM UTC 24 | Sep 09 08:03:46 AM UTC 24 | 336329810000 ps | ||
T168 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2593126344 | Sep 09 07:29:38 AM UTC 24 | Sep 09 08:03:46 AM UTC 24 | 336543570000 ps | ||
T169 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.4182969091 | Sep 09 07:29:39 AM UTC 24 | Sep 09 08:03:47 AM UTC 24 | 336631050000 ps | ||
T170 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.207951949 | Sep 09 07:29:38 AM UTC 24 | Sep 09 08:03:48 AM UTC 24 | 336693470000 ps | ||
T171 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.3217752881 | Sep 09 07:29:38 AM UTC 24 | Sep 09 08:03:48 AM UTC 24 | 336821350000 ps | ||
T172 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.2848148963 | Sep 09 07:29:39 AM UTC 24 | Sep 09 08:03:48 AM UTC 24 | 336600930000 ps | ||
T173 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.3690934790 | Sep 09 07:29:38 AM UTC 24 | Sep 09 08:03:48 AM UTC 24 | 336708890000 ps | ||
T174 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.1643482338 | Sep 09 07:29:38 AM UTC 24 | Sep 09 08:03:48 AM UTC 24 | 336839830000 ps | ||
T175 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.3346463565 | Sep 09 07:29:42 AM UTC 24 | Sep 09 08:03:48 AM UTC 24 | 336463010000 ps | ||
T176 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.3918090887 | Sep 09 07:29:39 AM UTC 24 | Sep 09 08:03:48 AM UTC 24 | 336752910000 ps | ||
T177 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.2746075336 | Sep 09 07:29:39 AM UTC 24 | Sep 09 08:03:49 AM UTC 24 | 336716430000 ps | ||
T178 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.572306888 | Sep 09 07:29:38 AM UTC 24 | Sep 09 08:03:49 AM UTC 24 | 336880210000 ps | ||
T179 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.2779622815 | Sep 09 07:29:43 AM UTC 24 | Sep 09 08:03:49 AM UTC 24 | 336803170000 ps | ||
T180 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.3355443372 | Sep 09 07:29:42 AM UTC 24 | Sep 09 08:03:49 AM UTC 24 | 336838770000 ps | ||
T181 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.695738960 | Sep 09 07:29:42 AM UTC 24 | Sep 09 08:03:49 AM UTC 24 | 336821550000 ps | ||
T182 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.1957136019 | Sep 09 07:29:39 AM UTC 24 | Sep 09 08:03:49 AM UTC 24 | 336875410000 ps | ||
T183 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.1074625615 | Sep 09 07:29:42 AM UTC 24 | Sep 09 08:03:49 AM UTC 24 | 336696570000 ps | ||
T184 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.342971066 | Sep 09 07:29:42 AM UTC 24 | Sep 09 08:03:50 AM UTC 24 | 336978650000 ps | ||
T185 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.2316357313 | Sep 09 07:29:45 AM UTC 24 | Sep 09 08:03:50 AM UTC 24 | 336521750000 ps | ||
T186 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.1331565522 | Sep 09 07:29:42 AM UTC 24 | Sep 09 08:03:50 AM UTC 24 | 336971290000 ps | ||
T187 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.3155838752 | Sep 09 07:29:42 AM UTC 24 | Sep 09 08:03:50 AM UTC 24 | 336786650000 ps | ||
T188 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.2251180103 | Sep 09 07:29:42 AM UTC 24 | Sep 09 08:03:50 AM UTC 24 | 336901430000 ps | ||
T189 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.1251137582 | Sep 09 07:29:38 AM UTC 24 | Sep 09 08:03:51 AM UTC 24 | 336526410000 ps | ||
T190 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.2065035476 | Sep 09 07:29:38 AM UTC 24 | Sep 09 08:03:52 AM UTC 24 | 336613730000 ps | ||
T191 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.392760008 | Sep 09 07:29:38 AM UTC 24 | Sep 09 08:03:52 AM UTC 24 | 336677150000 ps | ||
T192 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.574877064 | Sep 09 07:29:38 AM UTC 24 | Sep 09 08:03:54 AM UTC 24 | 337074290000 ps | ||
T193 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.1818261652 | Sep 09 07:29:38 AM UTC 24 | Sep 09 08:03:55 AM UTC 24 | 337017290000 ps | ||
T194 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.346850215 | Sep 09 07:29:50 AM UTC 24 | Sep 09 08:03:56 AM UTC 24 | 336468470000 ps | ||
T195 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.690484371 | Sep 09 07:29:50 AM UTC 24 | Sep 09 08:03:57 AM UTC 24 | 336498510000 ps | ||
T196 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.522604820 | Sep 09 07:29:51 AM UTC 24 | Sep 09 08:03:58 AM UTC 24 | 336431410000 ps | ||
T197 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.2927260527 | Sep 09 07:29:50 AM UTC 24 | Sep 09 08:03:59 AM UTC 24 | 336877150000 ps | ||
T198 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.1725480427 | Sep 09 07:29:51 AM UTC 24 | Sep 09 08:04:00 AM UTC 24 | 336892090000 ps | ||
T199 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.46292224 | Sep 09 07:29:50 AM UTC 24 | Sep 09 08:04:00 AM UTC 24 | 337036050000 ps | ||
T200 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.1757470110 | Sep 09 07:29:51 AM UTC 24 | Sep 09 08:04:01 AM UTC 24 | 336967370000 ps |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.2785315121 |
Short name | T1 |
Test name | |
Test status | |
Simulation time | 1224170000 ps |
CPU time | 2.01 seconds |
Started | Sep 09 02:54:55 AM UTC 24 |
Finished | Sep 09 02:55:06 AM UTC 24 |
Peak memory | 177840 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2785315121 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.2785315121 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/0.prim_lfsr_gal_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.623192632 |
Short name | T14 |
Test name | |
Test status | |
Simulation time | 336425950000 ps |
CPU time | 225.53 seconds |
Started | Sep 09 03:09:15 AM UTC 24 |
Finished | Sep 09 03:41:05 AM UTC 24 |
Peak memory | 176716 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=623192632 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.623192632 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/0.prim_lfsr_gal_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.2777809942 |
Short name | T32 |
Test name | |
Test status | |
Simulation time | 336763010000 ps |
CPU time | 231.05 seconds |
Started | Sep 09 07:29:31 AM UTC 24 |
Finished | Sep 09 08:03:42 AM UTC 24 |
Peak memory | 175128 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2777809942 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.2777809942 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/0.prim_lfsr_fib_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.3294286297 |
Short name | T24 |
Test name | |
Test status | |
Simulation time | 1506590000 ps |
CPU time | 1.82 seconds |
Started | Sep 09 07:09:06 AM UTC 24 |
Finished | Sep 09 07:09:16 AM UTC 24 |
Peak memory | 177772 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3294286297 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.3294286297 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/0.prim_lfsr_fib_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.954676384 |
Short name | T34 |
Test name | |
Test status | |
Simulation time | 336793530000 ps |
CPU time | 228.55 seconds |
Started | Sep 09 07:29:31 AM UTC 24 |
Finished | Sep 09 08:03:43 AM UTC 24 |
Peak memory | 176656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=954676384 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.954676384 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/1.prim_lfsr_fib_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.4284793102 |
Short name | T162 |
Test name | |
Test status | |
Simulation time | 337112430000 ps |
CPU time | 229.59 seconds |
Started | Sep 09 07:29:38 AM UTC 24 |
Finished | Sep 09 08:03:45 AM UTC 24 |
Peak memory | 175116 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284793102 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.4284793102 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/10.prim_lfsr_fib_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.1643155810 |
Short name | T161 |
Test name | |
Test status | |
Simulation time | 336835850000 ps |
CPU time | 231.29 seconds |
Started | Sep 09 07:29:38 AM UTC 24 |
Finished | Sep 09 08:03:44 AM UTC 24 |
Peak memory | 176656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1643155810 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.1643155810 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/11.prim_lfsr_fib_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.3897564715 |
Short name | T40 |
Test name | |
Test status | |
Simulation time | 336811050000 ps |
CPU time | 230.27 seconds |
Started | Sep 09 07:29:38 AM UTC 24 |
Finished | Sep 09 08:03:44 AM UTC 24 |
Peak memory | 175128 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3897564715 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.3897564715 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/12.prim_lfsr_fib_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.1251137582 |
Short name | T189 |
Test name | |
Test status | |
Simulation time | 336526410000 ps |
CPU time | 229.54 seconds |
Started | Sep 09 07:29:38 AM UTC 24 |
Finished | Sep 09 08:03:51 AM UTC 24 |
Peak memory | 176656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1251137582 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.1251137582 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/13.prim_lfsr_fib_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.574877064 |
Short name | T192 |
Test name | |
Test status | |
Simulation time | 337074290000 ps |
CPU time | 230.39 seconds |
Started | Sep 09 07:29:38 AM UTC 24 |
Finished | Sep 09 08:03:54 AM UTC 24 |
Peak memory | 176660 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=574877064 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.574877064 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/14.prim_lfsr_fib_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.392760008 |
Short name | T191 |
Test name | |
Test status | |
Simulation time | 336677150000 ps |
CPU time | 230.01 seconds |
Started | Sep 09 07:29:38 AM UTC 24 |
Finished | Sep 09 08:03:52 AM UTC 24 |
Peak memory | 175132 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=392760008 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.392760008 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/15.prim_lfsr_fib_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.2065035476 |
Short name | T190 |
Test name | |
Test status | |
Simulation time | 336613730000 ps |
CPU time | 230.8 seconds |
Started | Sep 09 07:29:38 AM UTC 24 |
Finished | Sep 09 08:03:52 AM UTC 24 |
Peak memory | 175128 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2065035476 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.2065035476 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/16.prim_lfsr_fib_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.1818261652 |
Short name | T193 |
Test name | |
Test status | |
Simulation time | 337017290000 ps |
CPU time | 231.64 seconds |
Started | Sep 09 07:29:38 AM UTC 24 |
Finished | Sep 09 08:03:55 AM UTC 24 |
Peak memory | 176656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1818261652 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.1818261652 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/17.prim_lfsr_fib_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.1643482338 |
Short name | T174 |
Test name | |
Test status | |
Simulation time | 336839830000 ps |
CPU time | 228.95 seconds |
Started | Sep 09 07:29:38 AM UTC 24 |
Finished | Sep 09 08:03:48 AM UTC 24 |
Peak memory | 176656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1643482338 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.1643482338 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/18.prim_lfsr_fib_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2593126344 |
Short name | T168 |
Test name | |
Test status | |
Simulation time | 336543570000 ps |
CPU time | 230.22 seconds |
Started | Sep 09 07:29:38 AM UTC 24 |
Finished | Sep 09 08:03:46 AM UTC 24 |
Peak memory | 176656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2593126344 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.2593126344 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/19.prim_lfsr_fib_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.4270831230 |
Short name | T31 |
Test name | |
Test status | |
Simulation time | 336552590000 ps |
CPU time | 229.13 seconds |
Started | Sep 09 07:29:31 AM UTC 24 |
Finished | Sep 09 08:03:42 AM UTC 24 |
Peak memory | 176716 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4270831230 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.4270831230 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/2.prim_lfsr_fib_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.572306888 |
Short name | T178 |
Test name | |
Test status | |
Simulation time | 336880210000 ps |
CPU time | 231.58 seconds |
Started | Sep 09 07:29:38 AM UTC 24 |
Finished | Sep 09 08:03:49 AM UTC 24 |
Peak memory | 176660 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=572306888 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.572306888 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/20.prim_lfsr_fib_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.3217752881 |
Short name | T171 |
Test name | |
Test status | |
Simulation time | 336821350000 ps |
CPU time | 229.27 seconds |
Started | Sep 09 07:29:38 AM UTC 24 |
Finished | Sep 09 08:03:48 AM UTC 24 |
Peak memory | 175128 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3217752881 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.3217752881 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/21.prim_lfsr_fib_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.207951949 |
Short name | T170 |
Test name | |
Test status | |
Simulation time | 336693470000 ps |
CPU time | 231.02 seconds |
Started | Sep 09 07:29:38 AM UTC 24 |
Finished | Sep 09 08:03:48 AM UTC 24 |
Peak memory | 175132 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207951949 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.207951949 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/22.prim_lfsr_fib_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.3690934790 |
Short name | T173 |
Test name | |
Test status | |
Simulation time | 336708890000 ps |
CPU time | 231.22 seconds |
Started | Sep 09 07:29:38 AM UTC 24 |
Finished | Sep 09 08:03:48 AM UTC 24 |
Peak memory | 175128 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3690934790 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.3690934790 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/23.prim_lfsr_fib_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.4115103705 |
Short name | T166 |
Test name | |
Test status | |
Simulation time | 336485850000 ps |
CPU time | 230.3 seconds |
Started | Sep 09 07:29:38 AM UTC 24 |
Finished | Sep 09 08:03:46 AM UTC 24 |
Peak memory | 175128 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4115103705 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.4115103705 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/24.prim_lfsr_fib_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.2848148963 |
Short name | T172 |
Test name | |
Test status | |
Simulation time | 336600930000 ps |
CPU time | 231.5 seconds |
Started | Sep 09 07:29:39 AM UTC 24 |
Finished | Sep 09 08:03:48 AM UTC 24 |
Peak memory | 176656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2848148963 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.2848148963 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/25.prim_lfsr_fib_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.2746075336 |
Short name | T177 |
Test name | |
Test status | |
Simulation time | 336716430000 ps |
CPU time | 232.44 seconds |
Started | Sep 09 07:29:39 AM UTC 24 |
Finished | Sep 09 08:03:49 AM UTC 24 |
Peak memory | 175120 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2746075336 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.2746075336 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/26.prim_lfsr_fib_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.3918090887 |
Short name | T176 |
Test name | |
Test status | |
Simulation time | 336752910000 ps |
CPU time | 230.02 seconds |
Started | Sep 09 07:29:39 AM UTC 24 |
Finished | Sep 09 08:03:48 AM UTC 24 |
Peak memory | 174904 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3918090887 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.3918090887 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/27.prim_lfsr_fib_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.4182969091 |
Short name | T169 |
Test name | |
Test status | |
Simulation time | 336631050000 ps |
CPU time | 229.14 seconds |
Started | Sep 09 07:29:39 AM UTC 24 |
Finished | Sep 09 08:03:47 AM UTC 24 |
Peak memory | 175128 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4182969091 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.4182969091 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/28.prim_lfsr_fib_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.1957136019 |
Short name | T182 |
Test name | |
Test status | |
Simulation time | 336875410000 ps |
CPU time | 230.81 seconds |
Started | Sep 09 07:29:39 AM UTC 24 |
Finished | Sep 09 08:03:49 AM UTC 24 |
Peak memory | 175128 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1957136019 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.1957136019 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/29.prim_lfsr_fib_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.4208181223 |
Short name | T163 |
Test name | |
Test status | |
Simulation time | 337017950000 ps |
CPU time | 231.88 seconds |
Started | Sep 09 07:29:31 AM UTC 24 |
Finished | Sep 09 08:03:45 AM UTC 24 |
Peak memory | 176644 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4208181223 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.4208181223 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/3.prim_lfsr_fib_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.384820472 |
Short name | T164 |
Test name | |
Test status | |
Simulation time | 336354850000 ps |
CPU time | 229.42 seconds |
Started | Sep 09 07:29:39 AM UTC 24 |
Finished | Sep 09 08:03:45 AM UTC 24 |
Peak memory | 175132 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=384820472 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.384820472 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/30.prim_lfsr_fib_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.4179311104 |
Short name | T165 |
Test name | |
Test status | |
Simulation time | 336319530000 ps |
CPU time | 229.1 seconds |
Started | Sep 09 07:29:39 AM UTC 24 |
Finished | Sep 09 08:03:46 AM UTC 24 |
Peak memory | 176656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4179311104 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.4179311104 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/31.prim_lfsr_fib_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.1331565522 |
Short name | T186 |
Test name | |
Test status | |
Simulation time | 336971290000 ps |
CPU time | 230.19 seconds |
Started | Sep 09 07:29:42 AM UTC 24 |
Finished | Sep 09 08:03:50 AM UTC 24 |
Peak memory | 176656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1331565522 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.1331565522 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/32.prim_lfsr_fib_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.695738960 |
Short name | T181 |
Test name | |
Test status | |
Simulation time | 336821550000 ps |
CPU time | 230.87 seconds |
Started | Sep 09 07:29:42 AM UTC 24 |
Finished | Sep 09 08:03:49 AM UTC 24 |
Peak memory | 176660 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=695738960 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.695738960 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/33.prim_lfsr_fib_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.3355443372 |
Short name | T180 |
Test name | |
Test status | |
Simulation time | 336838770000 ps |
CPU time | 229.88 seconds |
Started | Sep 09 07:29:42 AM UTC 24 |
Finished | Sep 09 08:03:49 AM UTC 24 |
Peak memory | 176656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3355443372 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.3355443372 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/34.prim_lfsr_fib_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.3346463565 |
Short name | T175 |
Test name | |
Test status | |
Simulation time | 336463010000 ps |
CPU time | 230.47 seconds |
Started | Sep 09 07:29:42 AM UTC 24 |
Finished | Sep 09 08:03:48 AM UTC 24 |
Peak memory | 175128 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346463565 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.3346463565 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/35.prim_lfsr_fib_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.342971066 |
Short name | T184 |
Test name | |
Test status | |
Simulation time | 336978650000 ps |
CPU time | 229.08 seconds |
Started | Sep 09 07:29:42 AM UTC 24 |
Finished | Sep 09 08:03:50 AM UTC 24 |
Peak memory | 176660 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=342971066 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.342971066 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/36.prim_lfsr_fib_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.3771026717 |
Short name | T167 |
Test name | |
Test status | |
Simulation time | 336329810000 ps |
CPU time | 229.87 seconds |
Started | Sep 09 07:29:42 AM UTC 24 |
Finished | Sep 09 08:03:46 AM UTC 24 |
Peak memory | 176656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3771026717 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.3771026717 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/37.prim_lfsr_fib_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.2251180103 |
Short name | T188 |
Test name | |
Test status | |
Simulation time | 336901430000 ps |
CPU time | 230.86 seconds |
Started | Sep 09 07:29:42 AM UTC 24 |
Finished | Sep 09 08:03:50 AM UTC 24 |
Peak memory | 176656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2251180103 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.2251180103 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/38.prim_lfsr_fib_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.3155838752 |
Short name | T187 |
Test name | |
Test status | |
Simulation time | 336786650000 ps |
CPU time | 231.35 seconds |
Started | Sep 09 07:29:42 AM UTC 24 |
Finished | Sep 09 08:03:50 AM UTC 24 |
Peak memory | 176648 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3155838752 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.3155838752 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/39.prim_lfsr_fib_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.3675073132 |
Short name | T39 |
Test name | |
Test status | |
Simulation time | 336998150000 ps |
CPU time | 230.33 seconds |
Started | Sep 09 07:29:31 AM UTC 24 |
Finished | Sep 09 08:03:44 AM UTC 24 |
Peak memory | 176652 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3675073132 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.3675073132 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/4.prim_lfsr_fib_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.1074625615 |
Short name | T183 |
Test name | |
Test status | |
Simulation time | 336696570000 ps |
CPU time | 231.08 seconds |
Started | Sep 09 07:29:42 AM UTC 24 |
Finished | Sep 09 08:03:49 AM UTC 24 |
Peak memory | 175128 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1074625615 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.1074625615 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/40.prim_lfsr_fib_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.2779622815 |
Short name | T179 |
Test name | |
Test status | |
Simulation time | 336803170000 ps |
CPU time | 228.07 seconds |
Started | Sep 09 07:29:43 AM UTC 24 |
Finished | Sep 09 08:03:49 AM UTC 24 |
Peak memory | 175128 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2779622815 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.2779622815 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/41.prim_lfsr_fib_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.2316357313 |
Short name | T185 |
Test name | |
Test status | |
Simulation time | 336521750000 ps |
CPU time | 230.14 seconds |
Started | Sep 09 07:29:45 AM UTC 24 |
Finished | Sep 09 08:03:50 AM UTC 24 |
Peak memory | 176656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2316357313 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.2316357313 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/42.prim_lfsr_fib_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.690484371 |
Short name | T195 |
Test name | |
Test status | |
Simulation time | 336498510000 ps |
CPU time | 229.28 seconds |
Started | Sep 09 07:29:50 AM UTC 24 |
Finished | Sep 09 08:03:57 AM UTC 24 |
Peak memory | 176660 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=690484371 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.690484371 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/43.prim_lfsr_fib_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.346850215 |
Short name | T194 |
Test name | |
Test status | |
Simulation time | 336468470000 ps |
CPU time | 229.32 seconds |
Started | Sep 09 07:29:50 AM UTC 24 |
Finished | Sep 09 08:03:56 AM UTC 24 |
Peak memory | 176612 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=346850215 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.346850215 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/44.prim_lfsr_fib_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.2927260527 |
Short name | T197 |
Test name | |
Test status | |
Simulation time | 336877150000 ps |
CPU time | 230.59 seconds |
Started | Sep 09 07:29:50 AM UTC 24 |
Finished | Sep 09 08:03:59 AM UTC 24 |
Peak memory | 175128 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2927260527 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.2927260527 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/45.prim_lfsr_fib_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.46292224 |
Short name | T199 |
Test name | |
Test status | |
Simulation time | 337036050000 ps |
CPU time | 229.77 seconds |
Started | Sep 09 07:29:50 AM UTC 24 |
Finished | Sep 09 08:04:00 AM UTC 24 |
Peak memory | 175124 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=46292224 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_ fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.46292224 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/46.prim_lfsr_fib_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.522604820 |
Short name | T196 |
Test name | |
Test status | |
Simulation time | 336431410000 ps |
CPU time | 230.81 seconds |
Started | Sep 09 07:29:51 AM UTC 24 |
Finished | Sep 09 08:03:58 AM UTC 24 |
Peak memory | 175132 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=522604820 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.522604820 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/47.prim_lfsr_fib_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.1757470110 |
Short name | T200 |
Test name | |
Test status | |
Simulation time | 336967370000 ps |
CPU time | 231.19 seconds |
Started | Sep 09 07:29:51 AM UTC 24 |
Finished | Sep 09 08:04:01 AM UTC 24 |
Peak memory | 176656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1757470110 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.1757470110 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/48.prim_lfsr_fib_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.1725480427 |
Short name | T198 |
Test name | |
Test status | |
Simulation time | 336892090000 ps |
CPU time | 231.05 seconds |
Started | Sep 09 07:29:51 AM UTC 24 |
Finished | Sep 09 08:04:00 AM UTC 24 |
Peak memory | 176656 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725480427 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.1725480427 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/49.prim_lfsr_fib_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.3513032043 |
Short name | T35 |
Test name | |
Test status | |
Simulation time | 336744210000 ps |
CPU time | 230.52 seconds |
Started | Sep 09 07:29:31 AM UTC 24 |
Finished | Sep 09 08:03:44 AM UTC 24 |
Peak memory | 176652 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3513032043 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.3513032043 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/5.prim_lfsr_fib_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.2385647569 |
Short name | T38 |
Test name | |
Test status | |
Simulation time | 336959210000 ps |
CPU time | 228.69 seconds |
Started | Sep 09 07:29:31 AM UTC 24 |
Finished | Sep 09 08:03:44 AM UTC 24 |
Peak memory | 176664 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2385647569 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.2385647569 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/6.prim_lfsr_fib_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.966488705 |
Short name | T33 |
Test name | |
Test status | |
Simulation time | 336731410000 ps |
CPU time | 228.73 seconds |
Started | Sep 09 07:29:31 AM UTC 24 |
Finished | Sep 09 08:03:43 AM UTC 24 |
Peak memory | 176652 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=966488705 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.966488705 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/7.prim_lfsr_fib_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.3839530807 |
Short name | T36 |
Test name | |
Test status | |
Simulation time | 336888270000 ps |
CPU time | 230.31 seconds |
Started | Sep 09 07:29:31 AM UTC 24 |
Finished | Sep 09 08:03:44 AM UTC 24 |
Peak memory | 176652 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3839530807 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.3839530807 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/8.prim_lfsr_fib_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.144955162 |
Short name | T37 |
Test name | |
Test status | |
Simulation time | 336790790000 ps |
CPU time | 231.36 seconds |
Started | Sep 09 07:29:38 AM UTC 24 |
Finished | Sep 09 08:03:44 AM UTC 24 |
Peak memory | 175128 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=144955162 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.144955162 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/9.prim_lfsr_fib_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.3488183777 |
Short name | T16 |
Test name | |
Test status | |
Simulation time | 336650970000 ps |
CPU time | 224.5 seconds |
Started | Sep 09 03:09:15 AM UTC 24 |
Finished | Sep 09 03:41:06 AM UTC 24 |
Peak memory | 176652 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3488183777 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.3488183777 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/1.prim_lfsr_gal_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.2692244293 |
Short name | T21 |
Test name | |
Test status | |
Simulation time | 336459530000 ps |
CPU time | 234.88 seconds |
Started | Sep 09 03:09:16 AM UTC 24 |
Finished | Sep 09 03:41:09 AM UTC 24 |
Peak memory | 175124 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2692244293 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.2692244293 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/10.prim_lfsr_gal_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.146191339 |
Short name | T23 |
Test name | |
Test status | |
Simulation time | 336691170000 ps |
CPU time | 227.17 seconds |
Started | Sep 09 03:09:17 AM UTC 24 |
Finished | Sep 09 03:41:10 AM UTC 24 |
Peak memory | 175024 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=146191339 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.146191339 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/11.prim_lfsr_gal_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.1761868856 |
Short name | T85 |
Test name | |
Test status | |
Simulation time | 336446810000 ps |
CPU time | 232.78 seconds |
Started | Sep 09 03:09:18 AM UTC 24 |
Finished | Sep 09 03:41:13 AM UTC 24 |
Peak memory | 175124 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1761868856 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.1761868856 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/12.prim_lfsr_gal_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.340800056 |
Short name | T86 |
Test name | |
Test status | |
Simulation time | 336859010000 ps |
CPU time | 227.05 seconds |
Started | Sep 09 03:09:18 AM UTC 24 |
Finished | Sep 09 03:41:13 AM UTC 24 |
Peak memory | 175128 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=340800056 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.340800056 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/13.prim_lfsr_gal_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.2032942317 |
Short name | T84 |
Test name | |
Test status | |
Simulation time | 336503110000 ps |
CPU time | 235.81 seconds |
Started | Sep 09 03:09:18 AM UTC 24 |
Finished | Sep 09 03:41:12 AM UTC 24 |
Peak memory | 175124 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2032942317 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.2032942317 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/14.prim_lfsr_gal_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.1486905993 |
Short name | T82 |
Test name | |
Test status | |
Simulation time | 336409490000 ps |
CPU time | 234.85 seconds |
Started | Sep 09 03:09:18 AM UTC 24 |
Finished | Sep 09 03:41:12 AM UTC 24 |
Peak memory | 175124 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1486905993 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.1486905993 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/15.prim_lfsr_gal_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.1372527840 |
Short name | T87 |
Test name | |
Test status | |
Simulation time | 336767790000 ps |
CPU time | 230.57 seconds |
Started | Sep 09 03:09:19 AM UTC 24 |
Finished | Sep 09 03:41:14 AM UTC 24 |
Peak memory | 175124 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1372527840 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.1372527840 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/16.prim_lfsr_gal_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.1186521816 |
Short name | T88 |
Test name | |
Test status | |
Simulation time | 337081570000 ps |
CPU time | 236.55 seconds |
Started | Sep 09 03:09:19 AM UTC 24 |
Finished | Sep 09 03:41:18 AM UTC 24 |
Peak memory | 175128 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1186521816 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.1186521816 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/17.prim_lfsr_gal_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.2260750183 |
Short name | T89 |
Test name | |
Test status | |
Simulation time | 336812850000 ps |
CPU time | 237.2 seconds |
Started | Sep 09 03:09:23 AM UTC 24 |
Finished | Sep 09 03:41:21 AM UTC 24 |
Peak memory | 175128 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2260750183 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.2260750183 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/18.prim_lfsr_gal_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.3306501845 |
Short name | T90 |
Test name | |
Test status | |
Simulation time | 336790790000 ps |
CPU time | 236.09 seconds |
Started | Sep 09 03:09:25 AM UTC 24 |
Finished | Sep 09 03:41:23 AM UTC 24 |
Peak memory | 175124 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3306501845 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.3306501845 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/19.prim_lfsr_gal_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.4140249963 |
Short name | T15 |
Test name | |
Test status | |
Simulation time | 336583530000 ps |
CPU time | 227.45 seconds |
Started | Sep 09 03:09:15 AM UTC 24 |
Finished | Sep 09 03:41:06 AM UTC 24 |
Peak memory | 176652 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4140249963 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.4140249963 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/2.prim_lfsr_gal_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.340664276 |
Short name | T91 |
Test name | |
Test status | |
Simulation time | 336761290000 ps |
CPU time | 234.44 seconds |
Started | Sep 09 03:09:31 AM UTC 24 |
Finished | Sep 09 03:41:30 AM UTC 24 |
Peak memory | 175132 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=340664276 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.340664276 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/20.prim_lfsr_gal_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.496122141 |
Short name | T93 |
Test name | |
Test status | |
Simulation time | 336541650000 ps |
CPU time | 226.99 seconds |
Started | Sep 09 03:09:37 AM UTC 24 |
Finished | Sep 09 03:41:35 AM UTC 24 |
Peak memory | 175128 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=496122141 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.496122141 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/21.prim_lfsr_gal_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.279462652 |
Short name | T92 |
Test name | |
Test status | |
Simulation time | 336510630000 ps |
CPU time | 225.89 seconds |
Started | Sep 09 03:09:37 AM UTC 24 |
Finished | Sep 09 03:41:34 AM UTC 24 |
Peak memory | 175128 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=279462652 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.279462652 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/22.prim_lfsr_gal_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.2144678785 |
Short name | T95 |
Test name | |
Test status | |
Simulation time | 336977350000 ps |
CPU time | 229.06 seconds |
Started | Sep 09 03:09:37 AM UTC 24 |
Finished | Sep 09 03:41:40 AM UTC 24 |
Peak memory | 175128 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2144678785 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.2144678785 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/23.prim_lfsr_gal_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.431108417 |
Short name | T94 |
Test name | |
Test status | |
Simulation time | 336498730000 ps |
CPU time | 234.03 seconds |
Started | Sep 09 03:09:37 AM UTC 24 |
Finished | Sep 09 03:41:38 AM UTC 24 |
Peak memory | 175128 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=431108417 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.431108417 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/24.prim_lfsr_gal_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.303738222 |
Short name | T96 |
Test name | |
Test status | |
Simulation time | 337088350000 ps |
CPU time | 228.52 seconds |
Started | Sep 09 03:09:45 AM UTC 24 |
Finished | Sep 09 03:41:52 AM UTC 24 |
Peak memory | 175132 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=303738222 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.303738222 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/25.prim_lfsr_gal_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.3490890947 |
Short name | T97 |
Test name | |
Test status | |
Simulation time | 337130810000 ps |
CPU time | 237.74 seconds |
Started | Sep 09 03:09:46 AM UTC 24 |
Finished | Sep 09 03:41:55 AM UTC 24 |
Peak memory | 175124 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3490890947 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.3490890947 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/26.prim_lfsr_gal_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.2605233545 |
Short name | T101 |
Test name | |
Test status | |
Simulation time | 336835410000 ps |
CPU time | 239.84 seconds |
Started | Sep 09 03:09:52 AM UTC 24 |
Finished | Sep 09 03:42:04 AM UTC 24 |
Peak memory | 175128 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2605233545 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.2605233545 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/27.prim_lfsr_gal_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.2009841134 |
Short name | T99 |
Test name | |
Test status | |
Simulation time | 337051850000 ps |
CPU time | 227.72 seconds |
Started | Sep 09 03:09:52 AM UTC 24 |
Finished | Sep 09 03:42:02 AM UTC 24 |
Peak memory | 175128 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2009841134 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.2009841134 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/28.prim_lfsr_gal_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.1238731392 |
Short name | T102 |
Test name | |
Test status | |
Simulation time | 337057150000 ps |
CPU time | 232.3 seconds |
Started | Sep 09 03:09:53 AM UTC 24 |
Finished | Sep 09 03:42:04 AM UTC 24 |
Peak memory | 175124 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1238731392 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.1238731392 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/29.prim_lfsr_gal_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.953028050 |
Short name | T18 |
Test name | |
Test status | |
Simulation time | 336478310000 ps |
CPU time | 230.71 seconds |
Started | Sep 09 03:09:15 AM UTC 24 |
Finished | Sep 09 03:41:08 AM UTC 24 |
Peak memory | 174852 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=953028050 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.953028050 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/3.prim_lfsr_gal_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.1661342151 |
Short name | T110 |
Test name | |
Test status | |
Simulation time | 337002610000 ps |
CPU time | 238.82 seconds |
Started | Sep 09 03:09:53 AM UTC 24 |
Finished | Sep 09 03:42:07 AM UTC 24 |
Peak memory | 175124 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1661342151 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.1661342151 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/30.prim_lfsr_gal_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.2730564910 |
Short name | T100 |
Test name | |
Test status | |
Simulation time | 336487330000 ps |
CPU time | 237.44 seconds |
Started | Sep 09 03:09:53 AM UTC 24 |
Finished | Sep 09 03:42:03 AM UTC 24 |
Peak memory | 175124 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2730564910 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.2730564910 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/31.prim_lfsr_gal_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.3421005286 |
Short name | T105 |
Test name | |
Test status | |
Simulation time | 336960910000 ps |
CPU time | 228.24 seconds |
Started | Sep 09 03:09:53 AM UTC 24 |
Finished | Sep 09 03:42:05 AM UTC 24 |
Peak memory | 175112 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3421005286 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.3421005286 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/32.prim_lfsr_gal_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.1167180449 |
Short name | T103 |
Test name | |
Test status | |
Simulation time | 336806530000 ps |
CPU time | 235.74 seconds |
Started | Sep 09 03:09:53 AM UTC 24 |
Finished | Sep 09 03:42:05 AM UTC 24 |
Peak memory | 175120 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1167180449 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.1167180449 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/33.prim_lfsr_gal_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.2444443602 |
Short name | T98 |
Test name | |
Test status | |
Simulation time | 336572690000 ps |
CPU time | 229.57 seconds |
Started | Sep 09 03:09:53 AM UTC 24 |
Finished | Sep 09 03:42:01 AM UTC 24 |
Peak memory | 175124 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2444443602 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.2444443602 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/34.prim_lfsr_gal_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.1598887795 |
Short name | T113 |
Test name | |
Test status | |
Simulation time | 337057230000 ps |
CPU time | 238.19 seconds |
Started | Sep 09 03:09:53 AM UTC 24 |
Finished | Sep 09 03:42:08 AM UTC 24 |
Peak memory | 175124 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1598887795 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.1598887795 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/35.prim_lfsr_gal_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.3192061277 |
Short name | T104 |
Test name | |
Test status | |
Simulation time | 336561470000 ps |
CPU time | 239.96 seconds |
Started | Sep 09 03:09:53 AM UTC 24 |
Finished | Sep 09 03:42:05 AM UTC 24 |
Peak memory | 175024 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3192061277 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.3192061277 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/36.prim_lfsr_gal_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.2775619790 |
Short name | T111 |
Test name | |
Test status | |
Simulation time | 337125010000 ps |
CPU time | 232.3 seconds |
Started | Sep 09 03:09:54 AM UTC 24 |
Finished | Sep 09 03:42:08 AM UTC 24 |
Peak memory | 175124 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2775619790 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.2775619790 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/37.prim_lfsr_gal_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.2246039493 |
Short name | T115 |
Test name | |
Test status | |
Simulation time | 336862850000 ps |
CPU time | 237.42 seconds |
Started | Sep 09 03:09:55 AM UTC 24 |
Finished | Sep 09 03:42:08 AM UTC 24 |
Peak memory | 175120 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2246039493 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.2246039493 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/38.prim_lfsr_gal_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.755585091 |
Short name | T109 |
Test name | |
Test status | |
Simulation time | 336815210000 ps |
CPU time | 232.58 seconds |
Started | Sep 09 03:09:55 AM UTC 24 |
Finished | Sep 09 03:42:07 AM UTC 24 |
Peak memory | 175128 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=755585091 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.755585091 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/39.prim_lfsr_gal_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.3096779111 |
Short name | T17 |
Test name | |
Test status | |
Simulation time | 336617890000 ps |
CPU time | 226.08 seconds |
Started | Sep 09 03:09:15 AM UTC 24 |
Finished | Sep 09 03:41:08 AM UTC 24 |
Peak memory | 175124 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3096779111 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.3096779111 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/4.prim_lfsr_gal_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.2557491276 |
Short name | T108 |
Test name | |
Test status | |
Simulation time | 336617090000 ps |
CPU time | 232.48 seconds |
Started | Sep 09 03:09:56 AM UTC 24 |
Finished | Sep 09 03:42:06 AM UTC 24 |
Peak memory | 175124 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2557491276 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.2557491276 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/40.prim_lfsr_gal_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.276333353 |
Short name | T106 |
Test name | |
Test status | |
Simulation time | 336566290000 ps |
CPU time | 228.19 seconds |
Started | Sep 09 03:09:56 AM UTC 24 |
Finished | Sep 09 03:42:05 AM UTC 24 |
Peak memory | 173744 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276333353 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.276333353 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/41.prim_lfsr_gal_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.3963747380 |
Short name | T107 |
Test name | |
Test status | |
Simulation time | 336509350000 ps |
CPU time | 231.85 seconds |
Started | Sep 09 03:09:56 AM UTC 24 |
Finished | Sep 09 03:42:06 AM UTC 24 |
Peak memory | 175124 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963747380 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.3963747380 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/42.prim_lfsr_gal_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.442430376 |
Short name | T112 |
Test name | |
Test status | |
Simulation time | 336992670000 ps |
CPU time | 232.84 seconds |
Started | Sep 09 03:09:56 AM UTC 24 |
Finished | Sep 09 03:42:08 AM UTC 24 |
Peak memory | 175128 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=442430376 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.442430376 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/43.prim_lfsr_gal_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.180346909 |
Short name | T117 |
Test name | |
Test status | |
Simulation time | 336967270000 ps |
CPU time | 235.53 seconds |
Started | Sep 09 03:09:56 AM UTC 24 |
Finished | Sep 09 03:42:10 AM UTC 24 |
Peak memory | 175132 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=180346909 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.180346909 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/44.prim_lfsr_gal_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.3160622372 |
Short name | T118 |
Test name | |
Test status | |
Simulation time | 336684770000 ps |
CPU time | 238.57 seconds |
Started | Sep 09 03:09:57 AM UTC 24 |
Finished | Sep 09 03:42:10 AM UTC 24 |
Peak memory | 175120 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3160622372 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.3160622372 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/45.prim_lfsr_gal_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.2404668831 |
Short name | T116 |
Test name | |
Test status | |
Simulation time | 336524330000 ps |
CPU time | 230.3 seconds |
Started | Sep 09 03:09:58 AM UTC 24 |
Finished | Sep 09 03:42:09 AM UTC 24 |
Peak memory | 175124 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2404668831 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.2404668831 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/46.prim_lfsr_gal_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.2984862520 |
Short name | T114 |
Test name | |
Test status | |
Simulation time | 336603210000 ps |
CPU time | 228.07 seconds |
Started | Sep 09 03:09:58 AM UTC 24 |
Finished | Sep 09 03:42:08 AM UTC 24 |
Peak memory | 175124 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2984862520 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.2984862520 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/47.prim_lfsr_gal_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.190514255 |
Short name | T120 |
Test name | |
Test status | |
Simulation time | 336914030000 ps |
CPU time | 238.07 seconds |
Started | Sep 09 03:09:58 AM UTC 24 |
Finished | Sep 09 03:42:14 AM UTC 24 |
Peak memory | 175120 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=190514255 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.190514255 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/48.prim_lfsr_gal_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.4185284242 |
Short name | T119 |
Test name | |
Test status | |
Simulation time | 337107790000 ps |
CPU time | 233.24 seconds |
Started | Sep 09 03:09:58 AM UTC 24 |
Finished | Sep 09 03:42:13 AM UTC 24 |
Peak memory | 175120 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4185284242 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.4185284242 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/49.prim_lfsr_gal_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.521181107 |
Short name | T20 |
Test name | |
Test status | |
Simulation time | 336742830000 ps |
CPU time | 228.62 seconds |
Started | Sep 09 03:09:16 AM UTC 24 |
Finished | Sep 09 03:41:09 AM UTC 24 |
Peak memory | 176652 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=521181107 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.521181107 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/5.prim_lfsr_gal_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.677162422 |
Short name | T81 |
Test name | |
Test status | |
Simulation time | 336887750000 ps |
CPU time | 231.8 seconds |
Started | Sep 09 03:09:16 AM UTC 24 |
Finished | Sep 09 03:41:11 AM UTC 24 |
Peak memory | 176652 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=677162422 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.677162422 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/6.prim_lfsr_gal_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.660004684 |
Short name | T19 |
Test name | |
Test status | |
Simulation time | 336624910000 ps |
CPU time | 229.18 seconds |
Started | Sep 09 03:09:16 AM UTC 24 |
Finished | Sep 09 03:41:09 AM UTC 24 |
Peak memory | 175124 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=660004684 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.660004684 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/7.prim_lfsr_gal_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.1258514324 |
Short name | T83 |
Test name | |
Test status | |
Simulation time | 337138030000 ps |
CPU time | 226.73 seconds |
Started | Sep 09 03:09:16 AM UTC 24 |
Finished | Sep 09 03:41:12 AM UTC 24 |
Peak memory | 175124 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1258514324 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.1258514324 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/8.prim_lfsr_gal_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.700312304 |
Short name | T22 |
Test name | |
Test status | |
Simulation time | 336839010000 ps |
CPU time | 227.16 seconds |
Started | Sep 09 03:09:16 AM UTC 24 |
Finished | Sep 09 03:41:09 AM UTC 24 |
Peak memory | 175120 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=700312304 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.700312304 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/9.prim_lfsr_gal_test/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.998862552 |
Short name | T5 |
Test name | |
Test status | |
Simulation time | 1382670000 ps |
CPU time | 1.83 seconds |
Started | Sep 09 07:09:06 AM UTC 24 |
Finished | Sep 09 07:09:16 AM UTC 24 |
Peak memory | 177804 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=998862552 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f ib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.998862552 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/1.prim_lfsr_fib_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.1075636313 |
Short name | T124 |
Test name | |
Test status | |
Simulation time | 1367990000 ps |
CPU time | 1.85 seconds |
Started | Sep 09 07:09:12 AM UTC 24 |
Finished | Sep 09 07:09:22 AM UTC 24 |
Peak memory | 177804 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1075636313 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.1075636313 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/10.prim_lfsr_fib_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.2314799413 |
Short name | T127 |
Test name | |
Test status | |
Simulation time | 1481930000 ps |
CPU time | 2.01 seconds |
Started | Sep 09 07:09:12 AM UTC 24 |
Finished | Sep 09 07:09:23 AM UTC 24 |
Peak memory | 177748 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2314799413 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.2314799413 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/11.prim_lfsr_fib_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.497096494 |
Short name | T130 |
Test name | |
Test status | |
Simulation time | 1504190000 ps |
CPU time | 1.88 seconds |
Started | Sep 09 07:09:12 AM UTC 24 |
Finished | Sep 09 07:09:23 AM UTC 24 |
Peak memory | 177768 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=497096494 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f ib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.497096494 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/12.prim_lfsr_fib_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.3153940648 |
Short name | T30 |
Test name | |
Test status | |
Simulation time | 1218350000 ps |
CPU time | 1.63 seconds |
Started | Sep 09 07:09:12 AM UTC 24 |
Finished | Sep 09 07:09:21 AM UTC 24 |
Peak memory | 177804 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3153940648 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.3153940648 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/13.prim_lfsr_fib_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.242305655 |
Short name | T125 |
Test name | |
Test status | |
Simulation time | 1376910000 ps |
CPU time | 1.83 seconds |
Started | Sep 09 07:09:12 AM UTC 24 |
Finished | Sep 09 07:09:22 AM UTC 24 |
Peak memory | 177704 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=242305655 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f ib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.242305655 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/14.prim_lfsr_fib_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.3314046045 |
Short name | T134 |
Test name | |
Test status | |
Simulation time | 1529570000 ps |
CPU time | 2.09 seconds |
Started | Sep 09 07:09:12 AM UTC 24 |
Finished | Sep 09 07:09:24 AM UTC 24 |
Peak memory | 177804 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3314046045 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.3314046045 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/15.prim_lfsr_fib_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.2889431443 |
Short name | T132 |
Test name | |
Test status | |
Simulation time | 1559310000 ps |
CPU time | 2.03 seconds |
Started | Sep 09 07:09:12 AM UTC 24 |
Finished | Sep 09 07:09:24 AM UTC 24 |
Peak memory | 177804 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2889431443 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.2889431443 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/16.prim_lfsr_fib_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.29394863 |
Short name | T137 |
Test name | |
Test status | |
Simulation time | 1624230000 ps |
CPU time | 1.91 seconds |
Started | Sep 09 07:09:12 AM UTC 24 |
Finished | Sep 09 07:09:24 AM UTC 24 |
Peak memory | 177772 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29394863 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fi b.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.29394863 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/17.prim_lfsr_fib_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.2438114793 |
Short name | T133 |
Test name | |
Test status | |
Simulation time | 1528350000 ps |
CPU time | 2.05 seconds |
Started | Sep 09 07:09:12 AM UTC 24 |
Finished | Sep 09 07:09:24 AM UTC 24 |
Peak memory | 177804 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2438114793 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.2438114793 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/18.prim_lfsr_fib_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.2274144299 |
Short name | T28 |
Test name | |
Test status | |
Simulation time | 1110970000 ps |
CPU time | 1.67 seconds |
Started | Sep 09 07:09:12 AM UTC 24 |
Finished | Sep 09 07:09:21 AM UTC 24 |
Peak memory | 177804 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2274144299 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.2274144299 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/19.prim_lfsr_fib_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.2248808742 |
Short name | T4 |
Test name | |
Test status | |
Simulation time | 1275950000 ps |
CPU time | 1.67 seconds |
Started | Sep 09 07:09:06 AM UTC 24 |
Finished | Sep 09 07:09:15 AM UTC 24 |
Peak memory | 177840 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2248808742 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.2248808742 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/2.prim_lfsr_fib_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.726111763 |
Short name | T121 |
Test name | |
Test status | |
Simulation time | 1274310000 ps |
CPU time | 1.65 seconds |
Started | Sep 09 07:09:12 AM UTC 24 |
Finished | Sep 09 07:09:22 AM UTC 24 |
Peak memory | 177772 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=726111763 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f ib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.726111763 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/20.prim_lfsr_fib_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3902648151 |
Short name | T135 |
Test name | |
Test status | |
Simulation time | 1555550000 ps |
CPU time | 1.97 seconds |
Started | Sep 09 07:09:12 AM UTC 24 |
Finished | Sep 09 07:09:24 AM UTC 24 |
Peak memory | 177420 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3902648151 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.3902648151 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/21.prim_lfsr_fib_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.3834719306 |
Short name | T126 |
Test name | |
Test status | |
Simulation time | 1417230000 ps |
CPU time | 1.85 seconds |
Started | Sep 09 07:09:12 AM UTC 24 |
Finished | Sep 09 07:09:23 AM UTC 24 |
Peak memory | 177436 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3834719306 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.3834719306 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/22.prim_lfsr_fib_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.3058008024 |
Short name | T136 |
Test name | |
Test status | |
Simulation time | 1561890000 ps |
CPU time | 1.97 seconds |
Started | Sep 09 07:09:12 AM UTC 24 |
Finished | Sep 09 07:09:24 AM UTC 24 |
Peak memory | 177804 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3058008024 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.3058008024 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/23.prim_lfsr_fib_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.3870997949 |
Short name | T29 |
Test name | |
Test status | |
Simulation time | 1124570000 ps |
CPU time | 1.58 seconds |
Started | Sep 09 07:09:12 AM UTC 24 |
Finished | Sep 09 07:09:21 AM UTC 24 |
Peak memory | 177804 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3870997949 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.3870997949 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/24.prim_lfsr_fib_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.3012511765 |
Short name | T131 |
Test name | |
Test status | |
Simulation time | 1473570000 ps |
CPU time | 1.98 seconds |
Started | Sep 09 07:09:13 AM UTC 24 |
Finished | Sep 09 07:09:23 AM UTC 24 |
Peak memory | 177804 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3012511765 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.3012511765 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/25.prim_lfsr_fib_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2964415499 |
Short name | T138 |
Test name | |
Test status | |
Simulation time | 1578770000 ps |
CPU time | 1.99 seconds |
Started | Sep 09 07:09:13 AM UTC 24 |
Finished | Sep 09 07:09:24 AM UTC 24 |
Peak memory | 177804 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2964415499 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.2964415499 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/26.prim_lfsr_fib_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.788290062 |
Short name | T139 |
Test name | |
Test status | |
Simulation time | 1568470000 ps |
CPU time | 2.11 seconds |
Started | Sep 09 07:09:13 AM UTC 24 |
Finished | Sep 09 07:09:24 AM UTC 24 |
Peak memory | 177768 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=788290062 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f ib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.788290062 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/27.prim_lfsr_fib_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.3261854080 |
Short name | T129 |
Test name | |
Test status | |
Simulation time | 1419850000 ps |
CPU time | 1.96 seconds |
Started | Sep 09 07:09:13 AM UTC 24 |
Finished | Sep 09 07:09:23 AM UTC 24 |
Peak memory | 177804 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3261854080 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.3261854080 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/28.prim_lfsr_fib_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.3321151776 |
Short name | T142 |
Test name | |
Test status | |
Simulation time | 1540210000 ps |
CPU time | 2.18 seconds |
Started | Sep 09 07:09:15 AM UTC 24 |
Finished | Sep 09 07:09:26 AM UTC 24 |
Peak memory | 177804 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3321151776 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.3321151776 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/29.prim_lfsr_fib_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.3098334234 |
Short name | T25 |
Test name | |
Test status | |
Simulation time | 1533550000 ps |
CPU time | 1.9 seconds |
Started | Sep 09 07:09:06 AM UTC 24 |
Finished | Sep 09 07:09:17 AM UTC 24 |
Peak memory | 177772 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3098334234 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.3098334234 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/3.prim_lfsr_fib_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.4082703242 |
Short name | T141 |
Test name | |
Test status | |
Simulation time | 1515570000 ps |
CPU time | 1.94 seconds |
Started | Sep 09 07:09:15 AM UTC 24 |
Finished | Sep 09 07:09:26 AM UTC 24 |
Peak memory | 177804 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4082703242 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.4082703242 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/30.prim_lfsr_fib_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.530888424 |
Short name | T140 |
Test name | |
Test status | |
Simulation time | 1381830000 ps |
CPU time | 1.79 seconds |
Started | Sep 09 07:09:15 AM UTC 24 |
Finished | Sep 09 07:09:25 AM UTC 24 |
Peak memory | 177768 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=530888424 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f ib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.530888424 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/31.prim_lfsr_fib_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.1567361795 |
Short name | T143 |
Test name | |
Test status | |
Simulation time | 1591650000 ps |
CPU time | 2.04 seconds |
Started | Sep 09 07:09:15 AM UTC 24 |
Finished | Sep 09 07:09:26 AM UTC 24 |
Peak memory | 177804 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1567361795 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.1567361795 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/32.prim_lfsr_fib_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.637884515 |
Short name | T146 |
Test name | |
Test status | |
Simulation time | 1534570000 ps |
CPU time | 1.86 seconds |
Started | Sep 09 07:09:16 AM UTC 24 |
Finished | Sep 09 07:09:27 AM UTC 24 |
Peak memory | 177768 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=637884515 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f ib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.637884515 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/33.prim_lfsr_fib_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.2690861938 |
Short name | T145 |
Test name | |
Test status | |
Simulation time | 1473730000 ps |
CPU time | 1.88 seconds |
Started | Sep 09 07:09:16 AM UTC 24 |
Finished | Sep 09 07:09:27 AM UTC 24 |
Peak memory | 177804 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2690861938 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.2690861938 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/34.prim_lfsr_fib_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.2663628018 |
Short name | T147 |
Test name | |
Test status | |
Simulation time | 1557890000 ps |
CPU time | 1.94 seconds |
Started | Sep 09 07:09:16 AM UTC 24 |
Finished | Sep 09 07:09:27 AM UTC 24 |
Peak memory | 177804 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2663628018 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.2663628018 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/35.prim_lfsr_fib_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.1019300553 |
Short name | T144 |
Test name | |
Test status | |
Simulation time | 1446610000 ps |
CPU time | 1.87 seconds |
Started | Sep 09 07:09:16 AM UTC 24 |
Finished | Sep 09 07:09:27 AM UTC 24 |
Peak memory | 177804 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1019300553 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.1019300553 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/36.prim_lfsr_fib_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.511652220 |
Short name | T151 |
Test name | |
Test status | |
Simulation time | 1504330000 ps |
CPU time | 1.92 seconds |
Started | Sep 09 07:09:17 AM UTC 24 |
Finished | Sep 09 07:09:28 AM UTC 24 |
Peak memory | 177768 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=511652220 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f ib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.511652220 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/37.prim_lfsr_fib_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.2921830834 |
Short name | T150 |
Test name | |
Test status | |
Simulation time | 1483610000 ps |
CPU time | 1.99 seconds |
Started | Sep 09 07:09:17 AM UTC 24 |
Finished | Sep 09 07:09:28 AM UTC 24 |
Peak memory | 177804 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2921830834 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.2921830834 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/38.prim_lfsr_fib_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.925566904 |
Short name | T149 |
Test name | |
Test status | |
Simulation time | 1452190000 ps |
CPU time | 2.08 seconds |
Started | Sep 09 07:09:17 AM UTC 24 |
Finished | Sep 09 07:09:28 AM UTC 24 |
Peak memory | 177768 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=925566904 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f ib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.925566904 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/39.prim_lfsr_fib_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.2045653569 |
Short name | T6 |
Test name | |
Test status | |
Simulation time | 1383250000 ps |
CPU time | 1.8 seconds |
Started | Sep 09 07:09:06 AM UTC 24 |
Finished | Sep 09 07:09:16 AM UTC 24 |
Peak memory | 177772 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2045653569 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.2045653569 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/4.prim_lfsr_fib_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.2611272571 |
Short name | T148 |
Test name | |
Test status | |
Simulation time | 1416610000 ps |
CPU time | 1.97 seconds |
Started | Sep 09 07:09:17 AM UTC 24 |
Finished | Sep 09 07:09:28 AM UTC 24 |
Peak memory | 177804 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2611272571 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.2611272571 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/40.prim_lfsr_fib_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.1006458084 |
Short name | T152 |
Test name | |
Test status | |
Simulation time | 1496150000 ps |
CPU time | 1.8 seconds |
Started | Sep 09 07:09:21 AM UTC 24 |
Finished | Sep 09 07:09:32 AM UTC 24 |
Peak memory | 177804 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1006458084 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.1006458084 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/41.prim_lfsr_fib_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.3792537644 |
Short name | T156 |
Test name | |
Test status | |
Simulation time | 1449170000 ps |
CPU time | 2.06 seconds |
Started | Sep 09 07:09:23 AM UTC 24 |
Finished | Sep 09 07:09:33 AM UTC 24 |
Peak memory | 177804 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3792537644 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.3792537644 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/42.prim_lfsr_fib_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.926087840 |
Short name | T155 |
Test name | |
Test status | |
Simulation time | 1437210000 ps |
CPU time | 1.85 seconds |
Started | Sep 09 07:09:23 AM UTC 24 |
Finished | Sep 09 07:09:33 AM UTC 24 |
Peak memory | 177768 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=926087840 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f ib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.926087840 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/43.prim_lfsr_fib_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.2117523817 |
Short name | T160 |
Test name | |
Test status | |
Simulation time | 1586770000 ps |
CPU time | 2.06 seconds |
Started | Sep 09 07:09:23 AM UTC 24 |
Finished | Sep 09 07:09:34 AM UTC 24 |
Peak memory | 177804 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2117523817 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.2117523817 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/44.prim_lfsr_fib_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.362533629 |
Short name | T158 |
Test name | |
Test status | |
Simulation time | 1563870000 ps |
CPU time | 1.99 seconds |
Started | Sep 09 07:09:23 AM UTC 24 |
Finished | Sep 09 07:09:34 AM UTC 24 |
Peak memory | 177768 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362533629 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f ib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.362533629 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/45.prim_lfsr_fib_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.1472360812 |
Short name | T153 |
Test name | |
Test status | |
Simulation time | 1341510000 ps |
CPU time | 1.67 seconds |
Started | Sep 09 07:09:23 AM UTC 24 |
Finished | Sep 09 07:09:32 AM UTC 24 |
Peak memory | 177804 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1472360812 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.1472360812 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/46.prim_lfsr_fib_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.2726746635 |
Short name | T159 |
Test name | |
Test status | |
Simulation time | 1544150000 ps |
CPU time | 2.04 seconds |
Started | Sep 09 07:09:23 AM UTC 24 |
Finished | Sep 09 07:09:34 AM UTC 24 |
Peak memory | 177804 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2726746635 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.2726746635 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/47.prim_lfsr_fib_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.1556292276 |
Short name | T154 |
Test name | |
Test status | |
Simulation time | 1346190000 ps |
CPU time | 1.83 seconds |
Started | Sep 09 07:09:23 AM UTC 24 |
Finished | Sep 09 07:09:33 AM UTC 24 |
Peak memory | 177804 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1556292276 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.1556292276 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/48.prim_lfsr_fib_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.3918622206 |
Short name | T157 |
Test name | |
Test status | |
Simulation time | 1516590000 ps |
CPU time | 1.89 seconds |
Started | Sep 09 07:09:23 AM UTC 24 |
Finished | Sep 09 07:09:33 AM UTC 24 |
Peak memory | 177804 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3918622206 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.3918622206 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/49.prim_lfsr_fib_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.3197115074 |
Short name | T26 |
Test name | |
Test status | |
Simulation time | 1548690000 ps |
CPU time | 1.94 seconds |
Started | Sep 09 07:09:06 AM UTC 24 |
Finished | Sep 09 07:09:17 AM UTC 24 |
Peak memory | 177772 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3197115074 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.3197115074 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/5.prim_lfsr_fib_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.3480950035 |
Short name | T27 |
Test name | |
Test status | |
Simulation time | 1567750000 ps |
CPU time | 1.89 seconds |
Started | Sep 09 07:09:06 AM UTC 24 |
Finished | Sep 09 07:09:17 AM UTC 24 |
Peak memory | 177772 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3480950035 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.3480950035 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/6.prim_lfsr_fib_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.695627368 |
Short name | T123 |
Test name | |
Test status | |
Simulation time | 1400550000 ps |
CPU time | 1.77 seconds |
Started | Sep 09 07:09:12 AM UTC 24 |
Finished | Sep 09 07:09:22 AM UTC 24 |
Peak memory | 177596 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=695627368 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f ib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.695627368 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/7.prim_lfsr_fib_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.2092746588 |
Short name | T122 |
Test name | |
Test status | |
Simulation time | 1353650000 ps |
CPU time | 1.59 seconds |
Started | Sep 09 07:09:12 AM UTC 24 |
Finished | Sep 09 07:09:22 AM UTC 24 |
Peak memory | 177772 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2092746588 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.2092746588 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/8.prim_lfsr_fib_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.3990337700 |
Short name | T128 |
Test name | |
Test status | |
Simulation time | 1518910000 ps |
CPU time | 2.05 seconds |
Started | Sep 09 07:09:12 AM UTC 24 |
Finished | Sep 09 07:09:23 AM UTC 24 |
Peak memory | 177772 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3990337700 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.3990337700 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/9.prim_lfsr_fib_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.1207566524 |
Short name | T9 |
Test name | |
Test status | |
Simulation time | 1569010000 ps |
CPU time | 2.55 seconds |
Started | Sep 09 02:54:56 AM UTC 24 |
Finished | Sep 09 02:55:10 AM UTC 24 |
Peak memory | 177544 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1207566524 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.1207566524 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/1.prim_lfsr_gal_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.1185185592 |
Short name | T43 |
Test name | |
Test status | |
Simulation time | 1577230000 ps |
CPU time | 2.55 seconds |
Started | Sep 09 02:54:57 AM UTC 24 |
Finished | Sep 09 02:55:11 AM UTC 24 |
Peak memory | 177804 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1185185592 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.1185185592 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/10.prim_lfsr_gal_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.405866562 |
Short name | T44 |
Test name | |
Test status | |
Simulation time | 1605850000 ps |
CPU time | 2.61 seconds |
Started | Sep 09 02:54:57 AM UTC 24 |
Finished | Sep 09 02:55:11 AM UTC 24 |
Peak memory | 177768 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=405866562 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g al.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.405866562 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/11.prim_lfsr_gal_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.2340577676 |
Short name | T41 |
Test name | |
Test status | |
Simulation time | 1436490000 ps |
CPU time | 2.67 seconds |
Started | Sep 09 02:54:57 AM UTC 24 |
Finished | Sep 09 02:55:10 AM UTC 24 |
Peak memory | 177804 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2340577676 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.2340577676 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/12.prim_lfsr_gal_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.4120686747 |
Short name | T45 |
Test name | |
Test status | |
Simulation time | 1526270000 ps |
CPU time | 2.55 seconds |
Started | Sep 09 02:54:59 AM UTC 24 |
Finished | Sep 09 02:55:12 AM UTC 24 |
Peak memory | 177804 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4120686747 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.4120686747 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/13.prim_lfsr_gal_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.344800314 |
Short name | T12 |
Test name | |
Test status | |
Simulation time | 1114690000 ps |
CPU time | 2.21 seconds |
Started | Sep 09 02:55:00 AM UTC 24 |
Finished | Sep 09 02:55:10 AM UTC 24 |
Peak memory | 177768 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=344800314 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g al.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.344800314 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/14.prim_lfsr_gal_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.3548523154 |
Short name | T47 |
Test name | |
Test status | |
Simulation time | 1592230000 ps |
CPU time | 2.63 seconds |
Started | Sep 09 02:55:00 AM UTC 24 |
Finished | Sep 09 02:55:13 AM UTC 24 |
Peak memory | 177804 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3548523154 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.3548523154 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/15.prim_lfsr_gal_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.234840467 |
Short name | T46 |
Test name | |
Test status | |
Simulation time | 1237150000 ps |
CPU time | 2.33 seconds |
Started | Sep 09 02:55:01 AM UTC 24 |
Finished | Sep 09 02:55:12 AM UTC 24 |
Peak memory | 177768 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=234840467 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g al.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.234840467 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/16.prim_lfsr_gal_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.795490176 |
Short name | T48 |
Test name | |
Test status | |
Simulation time | 1107530000 ps |
CPU time | 2.05 seconds |
Started | Sep 09 02:55:04 AM UTC 24 |
Finished | Sep 09 02:55:14 AM UTC 24 |
Peak memory | 177768 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=795490176 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g al.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.795490176 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/17.prim_lfsr_gal_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.2655681260 |
Short name | T49 |
Test name | |
Test status | |
Simulation time | 1491710000 ps |
CPU time | 2.61 seconds |
Started | Sep 09 02:55:05 AM UTC 24 |
Finished | Sep 09 02:55:17 AM UTC 24 |
Peak memory | 177804 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2655681260 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.2655681260 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/18.prim_lfsr_gal_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.1363949063 |
Short name | T50 |
Test name | |
Test status | |
Simulation time | 1605370000 ps |
CPU time | 2.7 seconds |
Started | Sep 09 02:55:07 AM UTC 24 |
Finished | Sep 09 02:55:20 AM UTC 24 |
Peak memory | 177804 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1363949063 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.1363949063 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/19.prim_lfsr_gal_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.436101585 |
Short name | T3 |
Test name | |
Test status | |
Simulation time | 1436890000 ps |
CPU time | 2.52 seconds |
Started | Sep 09 02:54:56 AM UTC 24 |
Finished | Sep 09 02:55:09 AM UTC 24 |
Peak memory | 177628 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=436101585 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g al.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.436101585 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/2.prim_lfsr_gal_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.2036912841 |
Short name | T51 |
Test name | |
Test status | |
Simulation time | 1420970000 ps |
CPU time | 2.28 seconds |
Started | Sep 09 02:55:09 AM UTC 24 |
Finished | Sep 09 02:55:21 AM UTC 24 |
Peak memory | 177804 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2036912841 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.2036912841 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/20.prim_lfsr_gal_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.670192386 |
Short name | T52 |
Test name | |
Test status | |
Simulation time | 1485110000 ps |
CPU time | 2.23 seconds |
Started | Sep 09 02:55:09 AM UTC 24 |
Finished | Sep 09 02:55:21 AM UTC 24 |
Peak memory | 177768 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=670192386 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g al.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.670192386 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/21.prim_lfsr_gal_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.3897778920 |
Short name | T54 |
Test name | |
Test status | |
Simulation time | 1553950000 ps |
CPU time | 2.56 seconds |
Started | Sep 09 02:55:09 AM UTC 24 |
Finished | Sep 09 02:55:22 AM UTC 24 |
Peak memory | 177804 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3897778920 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.3897778920 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/22.prim_lfsr_gal_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.1816651332 |
Short name | T58 |
Test name | |
Test status | |
Simulation time | 1572250000 ps |
CPU time | 2.33 seconds |
Started | Sep 09 02:55:10 AM UTC 24 |
Finished | Sep 09 02:55:23 AM UTC 24 |
Peak memory | 177792 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1816651332 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.1816651332 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/23.prim_lfsr_gal_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.4044178213 |
Short name | T59 |
Test name | |
Test status | |
Simulation time | 1572130000 ps |
CPU time | 2.47 seconds |
Started | Sep 09 02:55:10 AM UTC 24 |
Finished | Sep 09 02:55:23 AM UTC 24 |
Peak memory | 177804 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4044178213 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.4044178213 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/24.prim_lfsr_gal_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.3178351946 |
Short name | T57 |
Test name | |
Test status | |
Simulation time | 1510150000 ps |
CPU time | 2.48 seconds |
Started | Sep 09 02:55:10 AM UTC 24 |
Finished | Sep 09 02:55:23 AM UTC 24 |
Peak memory | 177804 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3178351946 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.3178351946 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/25.prim_lfsr_gal_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.1512146471 |
Short name | T56 |
Test name | |
Test status | |
Simulation time | 1459150000 ps |
CPU time | 2.32 seconds |
Started | Sep 09 02:55:10 AM UTC 24 |
Finished | Sep 09 02:55:23 AM UTC 24 |
Peak memory | 177804 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1512146471 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.1512146471 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/26.prim_lfsr_gal_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.2267891804 |
Short name | T55 |
Test name | |
Test status | |
Simulation time | 1461130000 ps |
CPU time | 2.46 seconds |
Started | Sep 09 02:55:10 AM UTC 24 |
Finished | Sep 09 02:55:23 AM UTC 24 |
Peak memory | 177804 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2267891804 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.2267891804 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/27.prim_lfsr_gal_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.743010257 |
Short name | T61 |
Test name | |
Test status | |
Simulation time | 1465090000 ps |
CPU time | 2.48 seconds |
Started | Sep 09 02:55:12 AM UTC 24 |
Finished | Sep 09 02:55:24 AM UTC 24 |
Peak memory | 177768 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=743010257 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g al.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.743010257 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/28.prim_lfsr_gal_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.1540426948 |
Short name | T60 |
Test name | |
Test status | |
Simulation time | 1447730000 ps |
CPU time | 2.38 seconds |
Started | Sep 09 02:55:12 AM UTC 24 |
Finished | Sep 09 02:55:24 AM UTC 24 |
Peak memory | 177804 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1540426948 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.1540426948 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/29.prim_lfsr_gal_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.365760757 |
Short name | T8 |
Test name | |
Test status | |
Simulation time | 1511330000 ps |
CPU time | 2.85 seconds |
Started | Sep 09 02:54:56 AM UTC 24 |
Finished | Sep 09 02:55:09 AM UTC 24 |
Peak memory | 177804 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=365760757 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g al.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.365760757 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/3.prim_lfsr_gal_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.320952240 |
Short name | T53 |
Test name | |
Test status | |
Simulation time | 1158350000 ps |
CPU time | 2.17 seconds |
Started | Sep 09 02:55:12 AM UTC 24 |
Finished | Sep 09 02:55:22 AM UTC 24 |
Peak memory | 177768 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=320952240 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g al.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.320952240 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/30.prim_lfsr_gal_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.1609812457 |
Short name | T62 |
Test name | |
Test status | |
Simulation time | 1536270000 ps |
CPU time | 2.49 seconds |
Started | Sep 09 02:55:12 AM UTC 24 |
Finished | Sep 09 02:55:24 AM UTC 24 |
Peak memory | 177804 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1609812457 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.1609812457 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/31.prim_lfsr_gal_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.2982703833 |
Short name | T64 |
Test name | |
Test status | |
Simulation time | 1596810000 ps |
CPU time | 2.38 seconds |
Started | Sep 09 02:55:12 AM UTC 24 |
Finished | Sep 09 02:55:25 AM UTC 24 |
Peak memory | 177804 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2982703833 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.2982703833 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/32.prim_lfsr_gal_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.1965646247 |
Short name | T63 |
Test name | |
Test status | |
Simulation time | 1432430000 ps |
CPU time | 2.37 seconds |
Started | Sep 09 02:55:13 AM UTC 24 |
Finished | Sep 09 02:55:25 AM UTC 24 |
Peak memory | 177804 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1965646247 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.1965646247 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/33.prim_lfsr_gal_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.154799047 |
Short name | T65 |
Test name | |
Test status | |
Simulation time | 1534890000 ps |
CPU time | 2.22 seconds |
Started | Sep 09 02:55:13 AM UTC 24 |
Finished | Sep 09 02:55:25 AM UTC 24 |
Peak memory | 177768 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=154799047 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g al.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.154799047 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/34.prim_lfsr_gal_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.2768949365 |
Short name | T66 |
Test name | |
Test status | |
Simulation time | 1538090000 ps |
CPU time | 2.64 seconds |
Started | Sep 09 02:55:14 AM UTC 24 |
Finished | Sep 09 02:55:26 AM UTC 24 |
Peak memory | 177804 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2768949365 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.2768949365 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/35.prim_lfsr_gal_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.2943844557 |
Short name | T67 |
Test name | |
Test status | |
Simulation time | 1541610000 ps |
CPU time | 2.66 seconds |
Started | Sep 09 02:55:14 AM UTC 24 |
Finished | Sep 09 02:55:26 AM UTC 24 |
Peak memory | 177804 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2943844557 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.2943844557 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/36.prim_lfsr_gal_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.3667325185 |
Short name | T68 |
Test name | |
Test status | |
Simulation time | 1453570000 ps |
CPU time | 2.11 seconds |
Started | Sep 09 02:55:15 AM UTC 24 |
Finished | Sep 09 02:55:27 AM UTC 24 |
Peak memory | 177804 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3667325185 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.3667325185 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/37.prim_lfsr_gal_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.2161884585 |
Short name | T69 |
Test name | |
Test status | |
Simulation time | 1370790000 ps |
CPU time | 2.2 seconds |
Started | Sep 09 02:55:18 AM UTC 24 |
Finished | Sep 09 02:55:29 AM UTC 24 |
Peak memory | 177804 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2161884585 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.2161884585 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/38.prim_lfsr_gal_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.3325173626 |
Short name | T71 |
Test name | |
Test status | |
Simulation time | 1471390000 ps |
CPU time | 2.26 seconds |
Started | Sep 09 02:55:21 AM UTC 24 |
Finished | Sep 09 02:55:33 AM UTC 24 |
Peak memory | 177804 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3325173626 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.3325173626 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/39.prim_lfsr_gal_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.757543971 |
Short name | T11 |
Test name | |
Test status | |
Simulation time | 1586770000 ps |
CPU time | 2.71 seconds |
Started | Sep 09 02:54:56 AM UTC 24 |
Finished | Sep 09 02:55:10 AM UTC 24 |
Peak memory | 177804 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=757543971 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g al.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.757543971 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/4.prim_lfsr_gal_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.4006136773 |
Short name | T74 |
Test name | |
Test status | |
Simulation time | 1452470000 ps |
CPU time | 2.34 seconds |
Started | Sep 09 02:55:22 AM UTC 24 |
Finished | Sep 09 02:55:33 AM UTC 24 |
Peak memory | 177472 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4006136773 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.4006136773 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/40.prim_lfsr_gal_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.4227577413 |
Short name | T78 |
Test name | |
Test status | |
Simulation time | 1634950000 ps |
CPU time | 2.6 seconds |
Started | Sep 09 02:55:22 AM UTC 24 |
Finished | Sep 09 02:55:34 AM UTC 24 |
Peak memory | 177760 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4227577413 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.4227577413 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/41.prim_lfsr_gal_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.1154173279 |
Short name | T70 |
Test name | |
Test status | |
Simulation time | 1249350000 ps |
CPU time | 2.14 seconds |
Started | Sep 09 02:55:22 AM UTC 24 |
Finished | Sep 09 02:55:32 AM UTC 24 |
Peak memory | 177748 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1154173279 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.1154173279 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/42.prim_lfsr_gal_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.675388050 |
Short name | T72 |
Test name | |
Test status | |
Simulation time | 1424770000 ps |
CPU time | 2.27 seconds |
Started | Sep 09 02:55:22 AM UTC 24 |
Finished | Sep 09 02:55:33 AM UTC 24 |
Peak memory | 177772 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=675388050 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g al.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.675388050 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/43.prim_lfsr_gal_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.1117031478 |
Short name | T75 |
Test name | |
Test status | |
Simulation time | 1363190000 ps |
CPU time | 2.16 seconds |
Started | Sep 09 02:55:23 AM UTC 24 |
Finished | Sep 09 02:55:34 AM UTC 24 |
Peak memory | 177804 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1117031478 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.1117031478 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/44.prim_lfsr_gal_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.1850258763 |
Short name | T73 |
Test name | |
Test status | |
Simulation time | 1284070000 ps |
CPU time | 2.19 seconds |
Started | Sep 09 02:55:23 AM UTC 24 |
Finished | Sep 09 02:55:33 AM UTC 24 |
Peak memory | 177804 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1850258763 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.1850258763 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/45.prim_lfsr_gal_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.323551148 |
Short name | T76 |
Test name | |
Test status | |
Simulation time | 1398690000 ps |
CPU time | 2.27 seconds |
Started | Sep 09 02:55:23 AM UTC 24 |
Finished | Sep 09 02:55:34 AM UTC 24 |
Peak memory | 177772 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=323551148 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g al.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.323551148 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/46.prim_lfsr_gal_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.2588769515 |
Short name | T77 |
Test name | |
Test status | |
Simulation time | 1419750000 ps |
CPU time | 2.2 seconds |
Started | Sep 09 02:55:23 AM UTC 24 |
Finished | Sep 09 02:55:34 AM UTC 24 |
Peak memory | 177804 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2588769515 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.2588769515 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/47.prim_lfsr_gal_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.2361934341 |
Short name | T80 |
Test name | |
Test status | |
Simulation time | 1529910000 ps |
CPU time | 2.32 seconds |
Started | Sep 09 02:55:25 AM UTC 24 |
Finished | Sep 09 02:55:36 AM UTC 24 |
Peak memory | 177804 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2361934341 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.2361934341 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/48.prim_lfsr_gal_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.3833864006 |
Short name | T79 |
Test name | |
Test status | |
Simulation time | 1299270000 ps |
CPU time | 2.24 seconds |
Started | Sep 09 02:55:25 AM UTC 24 |
Finished | Sep 09 02:55:35 AM UTC 24 |
Peak memory | 177804 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3833864006 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.3833864006 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/49.prim_lfsr_gal_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.4095435352 |
Short name | T13 |
Test name | |
Test status | |
Simulation time | 1603130000 ps |
CPU time | 2.64 seconds |
Started | Sep 09 02:54:56 AM UTC 24 |
Finished | Sep 09 02:55:10 AM UTC 24 |
Peak memory | 177772 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4095435352 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.4095435352 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/5.prim_lfsr_gal_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.3900393285 |
Short name | T7 |
Test name | |
Test status | |
Simulation time | 1408730000 ps |
CPU time | 2.34 seconds |
Started | Sep 09 02:54:56 AM UTC 24 |
Finished | Sep 09 02:55:09 AM UTC 24 |
Peak memory | 177772 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3900393285 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.3900393285 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/6.prim_lfsr_gal_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.3822296903 |
Short name | T42 |
Test name | |
Test status | |
Simulation time | 1544470000 ps |
CPU time | 2.6 seconds |
Started | Sep 09 02:54:57 AM UTC 24 |
Finished | Sep 09 02:55:11 AM UTC 24 |
Peak memory | 177772 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3822296903 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.3822296903 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/7.prim_lfsr_gal_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.1433069273 |
Short name | T10 |
Test name | |
Test status | |
Simulation time | 1430930000 ps |
CPU time | 2.47 seconds |
Started | Sep 09 02:54:57 AM UTC 24 |
Finished | Sep 09 02:55:10 AM UTC 24 |
Peak memory | 177772 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1433069273 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.1433069273 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/8.prim_lfsr_gal_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.1660350093 |
Short name | T2 |
Test name | |
Test status | |
Simulation time | 1244350000 ps |
CPU time | 2.2 seconds |
Started | Sep 09 02:54:57 AM UTC 24 |
Finished | Sep 09 02:55:08 AM UTC 24 |
Peak memory | 177772 kb |
Host | riverbear.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1660350093 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.1660350093 |
Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_lfsr-sim-vcs/9.prim_lfsr_gal_smoke/latest |
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