| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 98.31 | 100.00 | 96.55 | 100.00 | 100.00 | 95.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 87.31 | 87.31 | 100.00 | 100.00 | 96.55 | 96.55 | 100.00 | 100.00 | 100.00 | 100.00 | 40.00 | 40.00 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.347633169 | ||
| 95.31 | 8.00 | 100.00 | 0.00 | 96.55 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 80.00 | 40.00 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.2995598282 | ||
| 96.81 | 1.50 | 100.00 | 0.00 | 96.55 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 87.50 | 7.50 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.3064634428 | ||
| 98.31 | 1.50 | 100.00 | 0.00 | 96.55 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 95.00 | 7.50 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.138135528 | ||
| Name |
|---|
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.1034188183 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.510743357 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.1922098505 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.885903307 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.4222665992 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.1833903350 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.2756220588 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.1989175030 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.616282246 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.374743119 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.3456298188 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.4257371447 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.1711593900 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.3469096241 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.1253875002 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.1914840378 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.2857768256 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.2396239032 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1190809138 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.1697030493 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.3233609023 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.3359054900 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.2705154593 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.1006462491 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.2923055912 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.3581450112 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.2114408292 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.641815226 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.3891549045 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.821264005 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.2230953305 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.2370803540 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.2939634791 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.357566792 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.1442177470 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.525088018 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.2934384659 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.2176049292 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.376717206 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.3934094910 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.90984208 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.363961245 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.26067794 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.1748127171 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.778687082 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.2901264680 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.1225788873 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.2956311704 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.512070886 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.1657164683 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.474264477 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.1241914004 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.2415420796 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.741903727 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.2583266242 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.3847330924 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.1558768432 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.3648424828 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.1552673681 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.3170773862 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.3350858096 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.4135435255 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3105744960 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.888783922 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.2389350270 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.90735103 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.2190399872 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.3501763332 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.3559300437 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.963165961 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.1933864138 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.340785928 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.654603710 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.1543264810 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.2067882466 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.154445644 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.708261368 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.3701453305 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.2322402780 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.2451732687 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.1990161599 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.2953641802 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.353055147 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.1219036674 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.2115503893 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.3541749125 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.1585244061 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.1854959608 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.1649544153 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.793967415 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.1195992324 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.516407928 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.3520005023 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.2276205838 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.2221982650 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.3858807574 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.3856094407 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.392394339 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.2846484381 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.2964659368 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.2256181944 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.2103610593 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.2981758107 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.107207818 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.134844411 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.3691128760 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.2940232364 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.742622281 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.422740091 |
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| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.2847807293 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.2058473399 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.4104546655 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.3943702726 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.263375583 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.330693849 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.3629090210 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.2038539910 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.2970145617 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.4258446547 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.3622262603 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.1599422613 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.3702146788 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.3708123284 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.728480328 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.2433256370 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.3348187814 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.3938938797 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.669498978 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.4240898728 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.1351633582 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3667456411 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.3631056144 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.3578210733 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.3035077146 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.302937233 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.1750057233 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.4285308049 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.937678016 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.3416984405 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.3550296110 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.3343747205 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.1277489102 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.928462653 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.3525523096 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.388683207 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.123276230 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.3281136112 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.2942760638 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.3781185793 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.212495478 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.1324551443 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.2608226809 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.2824921048 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.2530857886 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.631821782 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.1917384801 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.4097024882 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.2557289835 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.1289889156 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.3902124305 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.70017696 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.2397392393 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.4196409251 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.301947000 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.3086898862 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.2168252195 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.807836940 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.3319953260 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.3262289827 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.1834992161 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.767464995 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.1282585629 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.3090883438 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.2006970327 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.1040270850 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.2010536021 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.4053516034 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.673273248 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.1879167241 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.3371899107 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.1532098462 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.3021041685 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.3833784977 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.4229983206 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.1361620378 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.3382817015 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.1858476486 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.4174194650 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.1152709400 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.2053250186 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.1790758088 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.1914192154 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.1297835545 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.3212694520 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.2932971745 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.2557289835 | Sep 18 01:18:57 AM UTC 24 | Sep 18 01:19:09 AM UTC 24 | 1238430000 ps | ||
| T2 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.347633169 | Sep 18 01:18:56 AM UTC 24 | Sep 18 01:19:09 AM UTC 24 | 1378830000 ps | ||
| T3 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.3281136112 | Sep 18 01:18:56 AM UTC 24 | Sep 18 01:19:10 AM UTC 24 | 1549650000 ps | ||
| T7 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.3262289827 | Sep 18 01:18:57 AM UTC 24 | Sep 18 01:19:10 AM UTC 24 | 1429030000 ps | ||
| T8 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.1790758088 | Sep 18 01:18:57 AM UTC 24 | Sep 18 01:19:11 AM UTC 24 | 1485530000 ps | ||
| T9 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.3371899107 | Sep 18 01:18:57 AM UTC 24 | Sep 18 01:19:12 AM UTC 24 | 1596970000 ps | ||
| T10 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.1914192154 | Sep 18 01:18:58 AM UTC 24 | Sep 18 01:19:12 AM UTC 24 | 1536730000 ps | ||
| T11 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.1297835545 | Sep 18 01:18:59 AM UTC 24 | Sep 18 01:19:14 AM UTC 24 | 1594990000 ps | ||
| T12 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.2932971745 | Sep 18 01:19:01 AM UTC 24 | Sep 18 01:19:14 AM UTC 24 | 1501210000 ps | ||
| T13 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.3212694520 | Sep 18 01:19:00 AM UTC 24 | Sep 18 01:19:15 AM UTC 24 | 1571410000 ps | ||
| T41 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.2942760638 | Sep 18 01:19:01 AM UTC 24 | Sep 18 01:19:15 AM UTC 24 | 1606590000 ps | ||
| T42 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.212495478 | Sep 18 01:19:03 AM UTC 24 | Sep 18 01:19:15 AM UTC 24 | 1395890000 ps | ||
| T43 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.3781185793 | Sep 18 01:19:02 AM UTC 24 | Sep 18 01:19:16 AM UTC 24 | 1547890000 ps | ||
| T44 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.2530857886 | Sep 18 01:19:06 AM UTC 24 | Sep 18 01:19:16 AM UTC 24 | 1033530000 ps | ||
| T45 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.2824921048 | Sep 18 01:19:05 AM UTC 24 | Sep 18 01:19:18 AM UTC 24 | 1380290000 ps | ||
| T46 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.2608226809 | Sep 18 01:19:05 AM UTC 24 | Sep 18 01:19:18 AM UTC 24 | 1473190000 ps | ||
| T47 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.1324551443 | Sep 18 01:19:05 AM UTC 24 | Sep 18 01:19:18 AM UTC 24 | 1503110000 ps | ||
| T48 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.1917384801 | Sep 18 01:19:06 AM UTC 24 | Sep 18 01:19:19 AM UTC 24 | 1462390000 ps | ||
| T49 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.631821782 | Sep 18 01:19:06 AM UTC 24 | Sep 18 01:19:20 AM UTC 24 | 1529890000 ps | ||
| T50 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.4097024882 | Sep 18 01:19:07 AM UTC 24 | Sep 18 01:19:20 AM UTC 24 | 1419870000 ps | ||
| T51 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.2397392393 | Sep 18 01:19:10 AM UTC 24 | Sep 18 01:19:21 AM UTC 24 | 1166890000 ps | ||
| T52 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.1289889156 | Sep 18 01:19:09 AM UTC 24 | Sep 18 01:19:21 AM UTC 24 | 1222250000 ps | ||
| T53 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.3902124305 | Sep 18 01:19:09 AM UTC 24 | Sep 18 01:19:22 AM UTC 24 | 1283370000 ps | ||
| T54 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.70017696 | Sep 18 01:19:10 AM UTC 24 | Sep 18 01:19:22 AM UTC 24 | 1360090000 ps | ||
| T55 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.807836940 | Sep 18 01:19:12 AM UTC 24 | Sep 18 01:19:22 AM UTC 24 | 1150290000 ps | ||
| T56 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.4196409251 | Sep 18 01:19:11 AM UTC 24 | Sep 18 01:19:23 AM UTC 24 | 1386170000 ps | ||
| T57 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.301947000 | Sep 18 01:19:11 AM UTC 24 | Sep 18 01:19:24 AM UTC 24 | 1442370000 ps | ||
| T58 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.3086898862 | Sep 18 01:19:11 AM UTC 24 | Sep 18 01:19:25 AM UTC 24 | 1579450000 ps | ||
| T59 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.2168252195 | Sep 18 01:19:12 AM UTC 24 | Sep 18 01:19:25 AM UTC 24 | 1473710000 ps | ||
| T60 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.3319953260 | Sep 18 01:19:13 AM UTC 24 | Sep 18 01:19:26 AM UTC 24 | 1402570000 ps | ||
| T61 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.1834992161 | Sep 18 01:19:13 AM UTC 24 | Sep 18 01:19:27 AM UTC 24 | 1608810000 ps | ||
| T62 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.1879167241 | Sep 18 01:19:17 AM UTC 24 | Sep 18 01:19:28 AM UTC 24 | 1270410000 ps | ||
| T63 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.3090883438 | Sep 18 01:19:15 AM UTC 24 | Sep 18 01:19:29 AM UTC 24 | 1505830000 ps | ||
| T64 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.767464995 | Sep 18 01:19:15 AM UTC 24 | Sep 18 01:19:29 AM UTC 24 | 1514450000 ps | ||
| T65 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.673273248 | Sep 18 01:19:17 AM UTC 24 | Sep 18 01:19:29 AM UTC 24 | 1348970000 ps | ||
| T66 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.1040270850 | Sep 18 01:19:15 AM UTC 24 | Sep 18 01:19:29 AM UTC 24 | 1512310000 ps | ||
| T67 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.1282585629 | Sep 18 01:19:15 AM UTC 24 | Sep 18 01:19:29 AM UTC 24 | 1535230000 ps | ||
| T68 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.2006970327 | Sep 18 01:19:15 AM UTC 24 | Sep 18 01:19:29 AM UTC 24 | 1573650000 ps | ||
| T69 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.2010536021 | Sep 18 01:19:15 AM UTC 24 | Sep 18 01:19:30 AM UTC 24 | 1591550000 ps | ||
| T70 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.4053516034 | Sep 18 01:19:16 AM UTC 24 | Sep 18 01:19:30 AM UTC 24 | 1541750000 ps | ||
| T71 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.1532098462 | Sep 18 01:19:17 AM UTC 24 | Sep 18 01:19:30 AM UTC 24 | 1542710000 ps | ||
| T72 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.3021041685 | Sep 18 01:19:17 AM UTC 24 | Sep 18 01:19:31 AM UTC 24 | 1556750000 ps | ||
| T73 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.3833784977 | Sep 18 01:19:19 AM UTC 24 | Sep 18 01:19:32 AM UTC 24 | 1503690000 ps | ||
| T74 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.1361620378 | Sep 18 01:19:19 AM UTC 24 | Sep 18 01:19:33 AM UTC 24 | 1495650000 ps | ||
| T75 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.4229983206 | Sep 18 01:19:19 AM UTC 24 | Sep 18 01:19:33 AM UTC 24 | 1559050000 ps | ||
| T76 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.3382817015 | Sep 18 01:19:20 AM UTC 24 | Sep 18 01:19:33 AM UTC 24 | 1459030000 ps | ||
| T77 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.1858476486 | Sep 18 01:19:21 AM UTC 24 | Sep 18 01:19:34 AM UTC 24 | 1458490000 ps | ||
| T78 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.4174194650 | Sep 18 01:19:21 AM UTC 24 | Sep 18 01:19:35 AM UTC 24 | 1512570000 ps | ||
| T79 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.1152709400 | Sep 18 01:19:22 AM UTC 24 | Sep 18 01:19:35 AM UTC 24 | 1358710000 ps | ||
| T80 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.2053250186 | Sep 18 01:19:22 AM UTC 24 | Sep 18 01:19:36 AM UTC 24 | 1499850000 ps | ||
| T14 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.1657164683 | Sep 18 03:36:15 AM UTC 24 | Sep 18 04:08:57 AM UTC 24 | 336450310000 ps | ||
| T15 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.3350858096 | Sep 18 03:36:15 AM UTC 24 | Sep 18 04:08:59 AM UTC 24 | 336944170000 ps | ||
| T16 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.340785928 | Sep 18 03:36:15 AM UTC 24 | Sep 18 04:09:03 AM UTC 24 | 337039710000 ps | ||
| T17 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.2276205838 | Sep 18 03:36:28 AM UTC 24 | Sep 18 04:09:12 AM UTC 24 | 336681690000 ps | ||
| T18 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.474264477 | Sep 18 03:36:33 AM UTC 24 | Sep 18 04:09:14 AM UTC 24 | 336424150000 ps | ||
| T19 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.3847330924 | Sep 18 03:36:36 AM UTC 24 | Sep 18 04:09:20 AM UTC 24 | 336398690000 ps | ||
| T20 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.2221982650 | Sep 18 03:36:28 AM UTC 24 | Sep 18 04:09:21 AM UTC 24 | 337073610000 ps | ||
| T21 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.353055147 | Sep 18 03:36:17 AM UTC 24 | Sep 18 04:09:22 AM UTC 24 | 336361490000 ps | ||
| T22 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.1558768432 | Sep 18 03:36:36 AM UTC 24 | Sep 18 04:09:25 AM UTC 24 | 336982750000 ps | ||
| T23 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.2995598282 | Sep 18 03:36:15 AM UTC 24 | Sep 18 04:09:27 AM UTC 24 | 336990430000 ps | ||
| T81 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.3856094407 | Sep 18 03:36:32 AM UTC 24 | Sep 18 04:09:32 AM UTC 24 | 336647070000 ps | ||
| T82 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.3170773862 | Sep 18 03:36:44 AM UTC 24 | Sep 18 04:09:32 AM UTC 24 | 336715050000 ps | ||
| T83 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.1241914004 | Sep 18 03:36:34 AM UTC 24 | Sep 18 04:09:38 AM UTC 24 | 336707170000 ps | ||
| T84 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.2415420796 | Sep 18 03:36:34 AM UTC 24 | Sep 18 04:09:41 AM UTC 24 | 336370510000 ps | ||
| T85 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.741903727 | Sep 18 03:36:36 AM UTC 24 | Sep 18 04:09:43 AM UTC 24 | 337029010000 ps | ||
| T86 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.3501763332 | Sep 18 03:37:01 AM UTC 24 | Sep 18 04:09:43 AM UTC 24 | 336503690000 ps | ||
| T87 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.4135435255 | Sep 18 03:36:48 AM UTC 24 | Sep 18 04:09:43 AM UTC 24 | 336867850000 ps | ||
| T88 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.2389350270 | Sep 18 03:36:54 AM UTC 24 | Sep 18 04:09:43 AM UTC 24 | 336432110000 ps | ||
| T89 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.3858807574 | Sep 18 03:36:31 AM UTC 24 | Sep 18 04:09:44 AM UTC 24 | 336352910000 ps | ||
| T90 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.3559300437 | Sep 18 03:37:01 AM UTC 24 | Sep 18 04:09:44 AM UTC 24 | 336833990000 ps | ||
| T91 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.392394339 | Sep 18 03:36:33 AM UTC 24 | Sep 18 04:09:46 AM UTC 24 | 336588170000 ps | ||
| T92 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.888783922 | Sep 18 03:36:50 AM UTC 24 | Sep 18 04:09:46 AM UTC 24 | 337113130000 ps | ||
| T93 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.3648424828 | Sep 18 03:36:42 AM UTC 24 | Sep 18 04:09:49 AM UTC 24 | 336925310000 ps | ||
| T94 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.2583266242 | Sep 18 03:36:36 AM UTC 24 | Sep 18 04:09:53 AM UTC 24 | 337045790000 ps | ||
| T95 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3105744960 | Sep 18 03:36:50 AM UTC 24 | Sep 18 04:09:55 AM UTC 24 | 336889310000 ps | ||
| T96 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.963165961 | Sep 18 03:37:05 AM UTC 24 | Sep 18 04:09:57 AM UTC 24 | 336833750000 ps | ||
| T97 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.3701453305 | Sep 18 03:37:20 AM UTC 24 | Sep 18 04:09:59 AM UTC 24 | 336486030000 ps | ||
| T98 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.1552673681 | Sep 18 03:36:42 AM UTC 24 | Sep 18 04:10:01 AM UTC 24 | 336539150000 ps | ||
| T99 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.2190399872 | Sep 18 03:36:57 AM UTC 24 | Sep 18 04:10:01 AM UTC 24 | 336981490000 ps | ||
| T100 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.1933864138 | Sep 18 03:37:12 AM UTC 24 | Sep 18 04:10:03 AM UTC 24 | 337076530000 ps | ||
| T101 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.654603710 | Sep 18 03:37:12 AM UTC 24 | Sep 18 04:10:08 AM UTC 24 | 336718590000 ps | ||
| T102 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.1543264810 | Sep 18 03:37:13 AM UTC 24 | Sep 18 04:10:09 AM UTC 24 | 336451570000 ps | ||
| T103 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.2451732687 | Sep 18 03:37:24 AM UTC 24 | Sep 18 04:10:09 AM UTC 24 | 336774750000 ps | ||
| T104 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.3541749125 | Sep 18 03:37:28 AM UTC 24 | Sep 18 04:10:11 AM UTC 24 | 336725490000 ps | ||
| T105 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.1649544153 | Sep 18 03:37:31 AM UTC 24 | Sep 18 04:10:12 AM UTC 24 | 336429410000 ps | ||
| T106 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.90735103 | Sep 18 03:36:57 AM UTC 24 | Sep 18 04:10:12 AM UTC 24 | 336661630000 ps | ||
| T107 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.154445644 | Sep 18 03:37:16 AM UTC 24 | Sep 18 04:10:13 AM UTC 24 | 336376010000 ps | ||
| T108 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.1219036674 | Sep 18 03:37:27 AM UTC 24 | Sep 18 04:10:19 AM UTC 24 | 336912470000 ps | ||
| T109 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.2067882466 | Sep 18 03:37:14 AM UTC 24 | Sep 18 04:10:19 AM UTC 24 | 336691150000 ps | ||
| T110 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.2322402780 | Sep 18 03:37:22 AM UTC 24 | Sep 18 04:10:23 AM UTC 24 | 336724570000 ps | ||
| T111 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.708261368 | Sep 18 03:37:19 AM UTC 24 | Sep 18 04:10:24 AM UTC 24 | 336420170000 ps | ||
| T112 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.1585244061 | Sep 18 03:37:29 AM UTC 24 | Sep 18 04:10:25 AM UTC 24 | 336499950000 ps | ||
| T113 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.1854959608 | Sep 18 03:37:31 AM UTC 24 | Sep 18 04:10:27 AM UTC 24 | 336908890000 ps | ||
| T114 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.2115503893 | Sep 18 03:37:27 AM UTC 24 | Sep 18 04:10:27 AM UTC 24 | 336540070000 ps | ||
| T115 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.516407928 | Sep 18 03:37:32 AM UTC 24 | Sep 18 04:10:29 AM UTC 24 | 336637090000 ps | ||
| T116 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.3520005023 | Sep 18 03:37:33 AM UTC 24 | Sep 18 04:10:30 AM UTC 24 | 336525670000 ps | ||
| T117 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.793967415 | Sep 18 03:37:31 AM UTC 24 | Sep 18 04:10:31 AM UTC 24 | 336724070000 ps | ||
| T118 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.2953641802 | Sep 18 03:37:27 AM UTC 24 | Sep 18 04:10:40 AM UTC 24 | 336942110000 ps | ||
| T119 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.1990161599 | Sep 18 03:37:25 AM UTC 24 | Sep 18 04:10:42 AM UTC 24 | 336554710000 ps | ||
| T120 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.1195992324 | Sep 18 03:37:32 AM UTC 24 | Sep 18 04:10:43 AM UTC 24 | 336643710000 ps | ||
| T4 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.138135528 | Sep 18 01:19:22 AM UTC 24 | Sep 18 01:19:36 AM UTC 24 | 1501850000 ps | ||
| T5 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.2846484381 | Sep 18 01:19:23 AM UTC 24 | Sep 18 01:19:37 AM UTC 24 | 1496250000 ps | ||
| T6 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.4271255291 | Sep 18 01:19:23 AM UTC 24 | Sep 18 01:19:38 AM UTC 24 | 1550690000 ps | ||
| T24 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3667456411 | Sep 18 01:19:25 AM UTC 24 | Sep 18 01:19:38 AM UTC 24 | 1523650000 ps | ||
| T25 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.928462653 | Sep 18 01:19:26 AM UTC 24 | Sep 18 01:19:39 AM UTC 24 | 1461910000 ps | ||
| T26 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.3525523096 | Sep 18 01:19:26 AM UTC 24 | Sep 18 01:19:39 AM UTC 24 | 1467850000 ps | ||
| T27 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.1277489102 | Sep 18 01:19:26 AM UTC 24 | Sep 18 01:19:39 AM UTC 24 | 1508210000 ps | ||
| T28 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.3622262603 | Sep 18 01:19:25 AM UTC 24 | Sep 18 01:19:39 AM UTC 24 | 1629390000 ps | ||
| T29 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.2256181944 | Sep 18 01:19:29 AM UTC 24 | Sep 18 01:19:41 AM UTC 24 | 1280890000 ps | ||
| T30 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.2964659368 | Sep 18 01:19:29 AM UTC 24 | Sep 18 01:19:41 AM UTC 24 | 1342030000 ps | ||
| T121 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.388683207 | Sep 18 01:19:27 AM UTC 24 | Sep 18 01:19:41 AM UTC 24 | 1600230000 ps | ||
| T122 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.123276230 | Sep 18 01:19:28 AM UTC 24 | Sep 18 01:19:42 AM UTC 24 | 1533070000 ps | ||
| T123 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.134844411 | Sep 18 01:19:30 AM UTC 24 | Sep 18 01:19:42 AM UTC 24 | 1289130000 ps | ||
| T124 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.2981758107 | Sep 18 01:19:30 AM UTC 24 | Sep 18 01:19:42 AM UTC 24 | 1345070000 ps | ||
| T125 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.3691128760 | Sep 18 01:19:30 AM UTC 24 | Sep 18 01:19:43 AM UTC 24 | 1406310000 ps | ||
| T126 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.107207818 | Sep 18 01:19:30 AM UTC 24 | Sep 18 01:19:43 AM UTC 24 | 1451710000 ps | ||
| T127 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.2940232364 | Sep 18 01:19:30 AM UTC 24 | Sep 18 01:19:43 AM UTC 24 | 1441310000 ps | ||
| T128 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.2103610593 | Sep 18 01:19:30 AM UTC 24 | Sep 18 01:19:44 AM UTC 24 | 1542670000 ps | ||
| T129 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.742622281 | Sep 18 01:19:30 AM UTC 24 | Sep 18 01:19:44 AM UTC 24 | 1533210000 ps | ||
| T130 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.422740091 | Sep 18 01:19:31 AM UTC 24 | Sep 18 01:19:45 AM UTC 24 | 1495970000 ps | ||
| T131 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.2058473399 | Sep 18 01:19:32 AM UTC 24 | Sep 18 01:19:45 AM UTC 24 | 1503390000 ps | ||
| T132 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.2038539910 | Sep 18 01:19:36 AM UTC 24 | Sep 18 01:19:45 AM UTC 24 | 1024310000 ps | ||
| T133 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.2847807293 | Sep 18 01:19:31 AM UTC 24 | Sep 18 01:19:45 AM UTC 24 | 1588290000 ps | ||
| T134 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.4104546655 | Sep 18 01:19:34 AM UTC 24 | Sep 18 01:19:47 AM UTC 24 | 1439430000 ps | ||
| T135 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.263375583 | Sep 18 01:19:34 AM UTC 24 | Sep 18 01:19:47 AM UTC 24 | 1448610000 ps | ||
| T136 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.330693849 | Sep 18 01:19:34 AM UTC 24 | Sep 18 01:19:47 AM UTC 24 | 1484330000 ps | ||
| T137 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.3943702726 | Sep 18 01:19:34 AM UTC 24 | Sep 18 01:19:47 AM UTC 24 | 1528110000 ps | ||
| T138 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.1599422613 | Sep 18 01:19:37 AM UTC 24 | Sep 18 01:19:48 AM UTC 24 | 1212070000 ps | ||
| T139 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.3629090210 | Sep 18 01:19:35 AM UTC 24 | Sep 18 01:19:48 AM UTC 24 | 1517610000 ps | ||
| T140 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.4258446547 | Sep 18 01:19:36 AM UTC 24 | Sep 18 01:19:49 AM UTC 24 | 1503390000 ps | ||
| T141 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.2970145617 | Sep 18 01:19:36 AM UTC 24 | Sep 18 01:19:49 AM UTC 24 | 1519890000 ps | ||
| T142 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.3702146788 | Sep 18 01:19:37 AM UTC 24 | Sep 18 01:19:51 AM UTC 24 | 1536010000 ps | ||
| T143 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.669498978 | Sep 18 01:19:40 AM UTC 24 | Sep 18 01:19:51 AM UTC 24 | 1165070000 ps | ||
| T144 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.3708123284 | Sep 18 01:19:38 AM UTC 24 | Sep 18 01:19:51 AM UTC 24 | 1501290000 ps | ||
| T145 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.728480328 | Sep 18 01:19:38 AM UTC 24 | Sep 18 01:19:52 AM UTC 24 | 1518150000 ps | ||
| T146 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.3938938797 | Sep 18 01:19:40 AM UTC 24 | Sep 18 01:19:52 AM UTC 24 | 1258570000 ps | ||
| T147 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.3348187814 | Sep 18 01:19:39 AM UTC 24 | Sep 18 01:19:52 AM UTC 24 | 1409530000 ps | ||
| T148 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.4240898728 | Sep 18 01:19:40 AM UTC 24 | Sep 18 01:19:52 AM UTC 24 | 1292910000 ps | ||
| T149 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.1351633582 | Sep 18 01:19:42 AM UTC 24 | Sep 18 01:19:52 AM UTC 24 | 1200110000 ps | ||
| T150 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.2433256370 | Sep 18 01:19:39 AM UTC 24 | Sep 18 01:19:52 AM UTC 24 | 1519350000 ps | ||
| T151 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.1750057233 | Sep 18 01:19:43 AM UTC 24 | Sep 18 01:19:54 AM UTC 24 | 1284650000 ps | ||
| T152 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.3035077146 | Sep 18 01:19:43 AM UTC 24 | Sep 18 01:19:54 AM UTC 24 | 1299670000 ps | ||
| T153 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.3631056144 | Sep 18 01:19:42 AM UTC 24 | Sep 18 01:19:54 AM UTC 24 | 1488430000 ps | ||
| T154 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.302937233 | Sep 18 01:19:43 AM UTC 24 | Sep 18 01:19:54 AM UTC 24 | 1411270000 ps | ||
| T155 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.4285308049 | Sep 18 01:19:44 AM UTC 24 | Sep 18 01:19:55 AM UTC 24 | 1347470000 ps | ||
| T156 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.3578210733 | Sep 18 01:19:43 AM UTC 24 | Sep 18 01:19:55 AM UTC 24 | 1502510000 ps | ||
| T157 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.3416984405 | Sep 18 01:19:44 AM UTC 24 | Sep 18 01:19:55 AM UTC 24 | 1343690000 ps | ||
| T158 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.937678016 | Sep 18 01:19:44 AM UTC 24 | Sep 18 01:19:55 AM UTC 24 | 1396250000 ps | ||
| T159 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.3343747205 | Sep 18 01:19:45 AM UTC 24 | Sep 18 01:19:57 AM UTC 24 | 1531330000 ps | ||
| T160 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.3550296110 | Sep 18 01:19:45 AM UTC 24 | Sep 18 01:19:57 AM UTC 24 | 1573170000 ps | ||
| T31 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.357566792 | Sep 18 03:37:38 AM UTC 24 | Sep 18 04:10:23 AM UTC 24 | 336820950000 ps | ||
| T32 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.1034188183 | Sep 18 03:37:35 AM UTC 24 | Sep 18 04:10:35 AM UTC 24 | 336629290000 ps | ||
| T33 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.2705154593 | Sep 18 03:37:36 AM UTC 24 | Sep 18 04:10:37 AM UTC 24 | 336990530000 ps | ||
| T34 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.1922098505 | Sep 18 03:37:50 AM UTC 24 | Sep 18 04:10:37 AM UTC 24 | 336846370000 ps | ||
| T35 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.3064634428 | Sep 18 03:37:35 AM UTC 24 | Sep 18 04:10:43 AM UTC 24 | 336981210000 ps | ||
| T36 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.1225788873 | Sep 18 03:37:45 AM UTC 24 | Sep 18 04:10:45 AM UTC 24 | 336814550000 ps | ||
| T37 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.885903307 | Sep 18 03:37:54 AM UTC 24 | Sep 18 04:10:47 AM UTC 24 | 336545130000 ps | ||
| T38 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.510743357 | Sep 18 03:37:49 AM UTC 24 | Sep 18 04:10:49 AM UTC 24 | 336323390000 ps | ||
| T39 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.778687082 | Sep 18 03:37:44 AM UTC 24 | Sep 18 04:10:50 AM UTC 24 | 336424870000 ps | ||
| T40 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.4257371447 | Sep 18 03:37:36 AM UTC 24 | Sep 18 04:10:54 AM UTC 24 | 336936330000 ps | ||
| T161 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.2901264680 | Sep 18 03:37:45 AM UTC 24 | Sep 18 04:10:54 AM UTC 24 | 336987210000 ps | ||
| T162 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.2956311704 | Sep 18 03:37:46 AM UTC 24 | Sep 18 04:10:54 AM UTC 24 | 336801130000 ps | ||
| T163 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.512070886 | Sep 18 03:37:47 AM UTC 24 | Sep 18 04:10:56 AM UTC 24 | 336323250000 ps | ||
| T164 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.4222665992 | Sep 18 03:38:07 AM UTC 24 | Sep 18 04:11:08 AM UTC 24 | 336451910000 ps | ||
| T165 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.1989175030 | Sep 18 04:09:04 AM UTC 24 | Sep 18 04:46:14 AM UTC 24 | 336627750000 ps | ||
| T166 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.2756220588 | Sep 18 04:09:00 AM UTC 24 | Sep 18 04:46:16 AM UTC 24 | 336785470000 ps | ||
| T167 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.1833903350 | Sep 18 04:08:58 AM UTC 24 | Sep 18 04:46:21 AM UTC 24 | 336477710000 ps | ||
| T168 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.616282246 | Sep 18 04:09:13 AM UTC 24 | Sep 18 04:46:26 AM UTC 24 | 336989310000 ps | ||
| T169 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.1711593900 | Sep 18 04:09:22 AM UTC 24 | Sep 18 04:46:34 AM UTC 24 | 336629090000 ps | ||
| T170 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.374743119 | Sep 18 04:09:15 AM UTC 24 | Sep 18 04:46:35 AM UTC 24 | 336391110000 ps | ||
| T171 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.3469096241 | Sep 18 04:09:22 AM UTC 24 | Sep 18 04:46:39 AM UTC 24 | 336534210000 ps | ||
| T172 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.1253875002 | Sep 18 04:09:26 AM UTC 24 | Sep 18 04:46:39 AM UTC 24 | 336928390000 ps | ||
| T173 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.3456298188 | Sep 18 04:09:21 AM UTC 24 | Sep 18 04:46:43 AM UTC 24 | 337002750000 ps | ||
| T174 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.2857768256 | Sep 18 04:09:32 AM UTC 24 | Sep 18 04:46:50 AM UTC 24 | 336989050000 ps | ||
| T175 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.1914840378 | Sep 18 04:09:27 AM UTC 24 | Sep 18 04:46:53 AM UTC 24 | 336370670000 ps | ||
| T176 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.2396239032 | Sep 18 04:09:33 AM UTC 24 | Sep 18 04:47:00 AM UTC 24 | 336706290000 ps | ||
| T177 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.1697030493 | Sep 18 04:09:42 AM UTC 24 | Sep 18 04:47:00 AM UTC 24 | 336463610000 ps | ||
| T178 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.2114408292 | Sep 18 04:09:45 AM UTC 24 | Sep 18 04:47:04 AM UTC 24 | 336707090000 ps | ||
| T179 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.641815226 | Sep 18 04:09:46 AM UTC 24 | Sep 18 04:47:08 AM UTC 24 | 336919090000 ps | ||
| T180 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.3233609023 | Sep 18 04:09:44 AM UTC 24 | Sep 18 04:47:09 AM UTC 24 | 336886750000 ps | ||
| T181 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1190809138 | Sep 18 04:09:38 AM UTC 24 | Sep 18 04:47:09 AM UTC 24 | 336468750000 ps | ||
| T182 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.3891549045 | Sep 18 04:09:47 AM UTC 24 | Sep 18 04:47:10 AM UTC 24 | 336880030000 ps | ||
| T183 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.3359054900 | Sep 18 04:09:44 AM UTC 24 | Sep 18 04:47:14 AM UTC 24 | 336698210000 ps | ||
| T184 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.2923055912 | Sep 18 04:09:44 AM UTC 24 | Sep 18 04:47:15 AM UTC 24 | 336664430000 ps | ||
| T185 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.3581450112 | Sep 18 04:09:45 AM UTC 24 | Sep 18 04:47:16 AM UTC 24 | 336434330000 ps | ||
| T186 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.1006462491 | Sep 18 04:09:44 AM UTC 24 | Sep 18 04:47:17 AM UTC 24 | 336831590000 ps | ||
| T187 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.2230953305 | Sep 18 04:09:54 AM UTC 24 | Sep 18 04:47:18 AM UTC 24 | 336764290000 ps | ||
| T188 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.2939634791 | Sep 18 04:09:58 AM UTC 24 | Sep 18 04:47:20 AM UTC 24 | 336414130000 ps | ||
| T189 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.525088018 | Sep 18 04:10:02 AM UTC 24 | Sep 18 04:47:24 AM UTC 24 | 336297750000 ps | ||
| T190 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.821264005 | Sep 18 04:09:49 AM UTC 24 | Sep 18 04:47:28 AM UTC 24 | 337004670000 ps | ||
| T191 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.2176049292 | Sep 18 04:10:04 AM UTC 24 | Sep 18 04:47:31 AM UTC 24 | 336682330000 ps | ||
| T192 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.2370803540 | Sep 18 04:09:55 AM UTC 24 | Sep 18 04:47:32 AM UTC 24 | 336566990000 ps | ||
| T193 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.376717206 | Sep 18 04:10:08 AM UTC 24 | Sep 18 04:47:34 AM UTC 24 | 336412970000 ps | ||
| T194 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.1442177470 | Sep 18 04:10:00 AM UTC 24 | Sep 18 04:47:34 AM UTC 24 | 336465210000 ps | ||
| T195 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.3934094910 | Sep 18 04:10:09 AM UTC 24 | Sep 18 04:47:36 AM UTC 24 | 336540730000 ps | ||
| T196 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.90984208 | Sep 18 04:10:10 AM UTC 24 | Sep 18 04:47:40 AM UTC 24 | 336771010000 ps | ||
| T197 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.1748127171 | Sep 18 04:10:13 AM UTC 24 | Sep 18 04:47:41 AM UTC 24 | 336643610000 ps | ||
| T198 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.363961245 | Sep 18 04:10:13 AM UTC 24 | Sep 18 04:47:41 AM UTC 24 | 336722850000 ps | ||
| T199 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.26067794 | Sep 18 04:10:13 AM UTC 24 | Sep 18 04:47:42 AM UTC 24 | 336367650000 ps | ||
| T200 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.2934384659 | Sep 18 04:10:02 AM UTC 24 | Sep 18 04:47:45 AM UTC 24 | 336821630000 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.347633169 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 1378830000 ps |
| CPU time | 2.23 seconds |
| Started | Sep 18 01:18:56 AM UTC 24 |
| Finished | Sep 18 01:19:09 AM UTC 24 |
| Peak memory | 175240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=347633169 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g al.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.347633169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/0.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.2995598282 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 336990430000 ps |
| CPU time | 228.29 seconds |
| Started | Sep 18 03:36:15 AM UTC 24 |
| Finished | Sep 18 04:09:27 AM UTC 24 |
| Peak memory | 175096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2995598282 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.2995598282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/0.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.3064634428 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 336981210000 ps |
| CPU time | 233.78 seconds |
| Started | Sep 18 03:37:35 AM UTC 24 |
| Finished | Sep 18 04:10:43 AM UTC 24 |
| Peak memory | 176648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3064634428 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.3064634428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/0.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.138135528 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 1501850000 ps |
| CPU time | 2.07 seconds |
| Started | Sep 18 01:19:22 AM UTC 24 |
| Finished | Sep 18 01:19:36 AM UTC 24 |
| Peak memory | 177832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=138135528 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f ib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.138135528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/0.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.1034188183 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 336629290000 ps |
| CPU time | 232.71 seconds |
| Started | Sep 18 03:37:35 AM UTC 24 |
| Finished | Sep 18 04:10:35 AM UTC 24 |
| Peak memory | 175128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1034188183 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.1034188183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/1.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.510743357 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 336323390000 ps |
| CPU time | 232.06 seconds |
| Started | Sep 18 03:37:49 AM UTC 24 |
| Finished | Sep 18 04:10:49 AM UTC 24 |
| Peak memory | 176660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=510743357 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.510743357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/10.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.1922098505 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 336846370000 ps |
| CPU time | 232.36 seconds |
| Started | Sep 18 03:37:50 AM UTC 24 |
| Finished | Sep 18 04:10:37 AM UTC 24 |
| Peak memory | 176656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1922098505 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.1922098505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/11.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.885903307 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 336545130000 ps |
| CPU time | 232.81 seconds |
| Started | Sep 18 03:37:54 AM UTC 24 |
| Finished | Sep 18 04:10:47 AM UTC 24 |
| Peak memory | 175124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=885903307 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.885903307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/12.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.4222665992 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 336451910000 ps |
| CPU time | 231.89 seconds |
| Started | Sep 18 03:38:07 AM UTC 24 |
| Finished | Sep 18 04:11:08 AM UTC 24 |
| Peak memory | 175124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4222665992 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.4222665992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/13.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.1833903350 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 336477710000 ps |
| CPU time | 268.38 seconds |
| Started | Sep 18 04:08:58 AM UTC 24 |
| Finished | Sep 18 04:46:21 AM UTC 24 |
| Peak memory | 175120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1833903350 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.1833903350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/14.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.2756220588 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 336785470000 ps |
| CPU time | 266.75 seconds |
| Started | Sep 18 04:09:00 AM UTC 24 |
| Finished | Sep 18 04:46:16 AM UTC 24 |
| Peak memory | 175120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2756220588 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.2756220588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/15.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.1989175030 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 336627750000 ps |
| CPU time | 260.97 seconds |
| Started | Sep 18 04:09:04 AM UTC 24 |
| Finished | Sep 18 04:46:14 AM UTC 24 |
| Peak memory | 175120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1989175030 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.1989175030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/16.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.616282246 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 336989310000 ps |
| CPU time | 250.99 seconds |
| Started | Sep 18 04:09:13 AM UTC 24 |
| Finished | Sep 18 04:46:26 AM UTC 24 |
| Peak memory | 175116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=616282246 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.616282246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/17.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.374743119 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 336391110000 ps |
| CPU time | 269.12 seconds |
| Started | Sep 18 04:09:15 AM UTC 24 |
| Finished | Sep 18 04:46:35 AM UTC 24 |
| Peak memory | 175120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=374743119 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.374743119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/18.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.3456298188 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 337002750000 ps |
| CPU time | 264.2 seconds |
| Started | Sep 18 04:09:21 AM UTC 24 |
| Finished | Sep 18 04:46:43 AM UTC 24 |
| Peak memory | 175120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3456298188 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.3456298188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/19.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.4257371447 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 336936330000 ps |
| CPU time | 234.3 seconds |
| Started | Sep 18 03:37:36 AM UTC 24 |
| Finished | Sep 18 04:10:54 AM UTC 24 |
| Peak memory | 175128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4257371447 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.4257371447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/2.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.1711593900 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 336629090000 ps |
| CPU time | 251.67 seconds |
| Started | Sep 18 04:09:22 AM UTC 24 |
| Finished | Sep 18 04:46:34 AM UTC 24 |
| Peak memory | 175120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1711593900 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.1711593900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/20.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.3469096241 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 336534210000 ps |
| CPU time | 263.77 seconds |
| Started | Sep 18 04:09:22 AM UTC 24 |
| Finished | Sep 18 04:46:39 AM UTC 24 |
| Peak memory | 175116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3469096241 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.3469096241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/21.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.1253875002 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 336928390000 ps |
| CPU time | 251.08 seconds |
| Started | Sep 18 04:09:26 AM UTC 24 |
| Finished | Sep 18 04:46:39 AM UTC 24 |
| Peak memory | 175120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1253875002 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.1253875002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/22.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.1914840378 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 336370670000 ps |
| CPU time | 273.27 seconds |
| Started | Sep 18 04:09:27 AM UTC 24 |
| Finished | Sep 18 04:46:53 AM UTC 24 |
| Peak memory | 175120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1914840378 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.1914840378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/23.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.2857768256 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 336989050000 ps |
| CPU time | 252.5 seconds |
| Started | Sep 18 04:09:32 AM UTC 24 |
| Finished | Sep 18 04:46:50 AM UTC 24 |
| Peak memory | 175120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2857768256 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.2857768256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/24.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.2396239032 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 336706290000 ps |
| CPU time | 269.07 seconds |
| Started | Sep 18 04:09:33 AM UTC 24 |
| Finished | Sep 18 04:47:00 AM UTC 24 |
| Peak memory | 175120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2396239032 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.2396239032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/25.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1190809138 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 336468750000 ps |
| CPU time | 274 seconds |
| Started | Sep 18 04:09:38 AM UTC 24 |
| Finished | Sep 18 04:47:09 AM UTC 24 |
| Peak memory | 175120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1190809138 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.1190809138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/26.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.1697030493 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 336463610000 ps |
| CPU time | 259.09 seconds |
| Started | Sep 18 04:09:42 AM UTC 24 |
| Finished | Sep 18 04:47:00 AM UTC 24 |
| Peak memory | 175112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1697030493 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.1697030493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/27.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.3233609023 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 336886750000 ps |
| CPU time | 264.44 seconds |
| Started | Sep 18 04:09:44 AM UTC 24 |
| Finished | Sep 18 04:47:09 AM UTC 24 |
| Peak memory | 175052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3233609023 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.3233609023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/28.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.3359054900 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 336698210000 ps |
| CPU time | 265.79 seconds |
| Started | Sep 18 04:09:44 AM UTC 24 |
| Finished | Sep 18 04:47:14 AM UTC 24 |
| Peak memory | 175120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3359054900 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.3359054900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/29.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.2705154593 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 336990530000 ps |
| CPU time | 233.6 seconds |
| Started | Sep 18 03:37:36 AM UTC 24 |
| Finished | Sep 18 04:10:37 AM UTC 24 |
| Peak memory | 176660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2705154593 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.2705154593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/3.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.1006462491 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 336831590000 ps |
| CPU time | 267.16 seconds |
| Started | Sep 18 04:09:44 AM UTC 24 |
| Finished | Sep 18 04:47:17 AM UTC 24 |
| Peak memory | 175028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1006462491 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.1006462491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/30.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.2923055912 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 336664430000 ps |
| CPU time | 266.6 seconds |
| Started | Sep 18 04:09:44 AM UTC 24 |
| Finished | Sep 18 04:47:15 AM UTC 24 |
| Peak memory | 175120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2923055912 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.2923055912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/31.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.3581450112 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 336434330000 ps |
| CPU time | 269.35 seconds |
| Started | Sep 18 04:09:45 AM UTC 24 |
| Finished | Sep 18 04:47:16 AM UTC 24 |
| Peak memory | 175008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3581450112 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.3581450112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/32.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.2114408292 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 336707090000 ps |
| CPU time | 252.26 seconds |
| Started | Sep 18 04:09:45 AM UTC 24 |
| Finished | Sep 18 04:47:04 AM UTC 24 |
| Peak memory | 174980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2114408292 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.2114408292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/33.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.641815226 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 336919090000 ps |
| CPU time | 254.01 seconds |
| Started | Sep 18 04:09:46 AM UTC 24 |
| Finished | Sep 18 04:47:08 AM UTC 24 |
| Peak memory | 175120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=641815226 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.641815226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/34.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.3891549045 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 336880030000 ps |
| CPU time | 258.07 seconds |
| Started | Sep 18 04:09:47 AM UTC 24 |
| Finished | Sep 18 04:47:10 AM UTC 24 |
| Peak memory | 175120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3891549045 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.3891549045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/35.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.821264005 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 337004670000 ps |
| CPU time | 273.28 seconds |
| Started | Sep 18 04:09:49 AM UTC 24 |
| Finished | Sep 18 04:47:28 AM UTC 24 |
| Peak memory | 175120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=821264005 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.821264005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/36.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.2230953305 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 336764290000 ps |
| CPU time | 252.36 seconds |
| Started | Sep 18 04:09:54 AM UTC 24 |
| Finished | Sep 18 04:47:18 AM UTC 24 |
| Peak memory | 175120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2230953305 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.2230953305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/37.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.2370803540 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 336566990000 ps |
| CPU time | 269.07 seconds |
| Started | Sep 18 04:09:55 AM UTC 24 |
| Finished | Sep 18 04:47:32 AM UTC 24 |
| Peak memory | 175120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2370803540 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.2370803540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/38.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.2939634791 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 336414130000 ps |
| CPU time | 257.24 seconds |
| Started | Sep 18 04:09:58 AM UTC 24 |
| Finished | Sep 18 04:47:20 AM UTC 24 |
| Peak memory | 175120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2939634791 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.2939634791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/39.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.357566792 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 336820950000 ps |
| CPU time | 232.26 seconds |
| Started | Sep 18 03:37:38 AM UTC 24 |
| Finished | Sep 18 04:10:23 AM UTC 24 |
| Peak memory | 176720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=357566792 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.357566792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/4.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.1442177470 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 336465210000 ps |
| CPU time | 268.19 seconds |
| Started | Sep 18 04:10:00 AM UTC 24 |
| Finished | Sep 18 04:47:34 AM UTC 24 |
| Peak memory | 175120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1442177470 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.1442177470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/40.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.525088018 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 336297750000 ps |
| CPU time | 251.86 seconds |
| Started | Sep 18 04:10:02 AM UTC 24 |
| Finished | Sep 18 04:47:24 AM UTC 24 |
| Peak memory | 175124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=525088018 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.525088018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/41.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.2934384659 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 336821630000 ps |
| CPU time | 274.38 seconds |
| Started | Sep 18 04:10:02 AM UTC 24 |
| Finished | Sep 18 04:47:45 AM UTC 24 |
| Peak memory | 175120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2934384659 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.2934384659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/42.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.2176049292 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 336682330000 ps |
| CPU time | 251.93 seconds |
| Started | Sep 18 04:10:04 AM UTC 24 |
| Finished | Sep 18 04:47:31 AM UTC 24 |
| Peak memory | 175120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2176049292 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.2176049292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/43.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.376717206 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 336412970000 ps |
| CPU time | 251.48 seconds |
| Started | Sep 18 04:10:08 AM UTC 24 |
| Finished | Sep 18 04:47:34 AM UTC 24 |
| Peak memory | 175120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=376717206 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.376717206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/44.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.3934094910 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 336540730000 ps |
| CPU time | 253.82 seconds |
| Started | Sep 18 04:10:09 AM UTC 24 |
| Finished | Sep 18 04:47:36 AM UTC 24 |
| Peak memory | 175120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934094910 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.3934094910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/45.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.90984208 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 336771010000 ps |
| CPU time | 256.16 seconds |
| Started | Sep 18 04:10:10 AM UTC 24 |
| Finished | Sep 18 04:47:40 AM UTC 24 |
| Peak memory | 175116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=90984208 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_ fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.90984208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/46.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.363961245 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 336722850000 ps |
| CPU time | 252.13 seconds |
| Started | Sep 18 04:10:13 AM UTC 24 |
| Finished | Sep 18 04:47:41 AM UTC 24 |
| Peak memory | 175120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=363961245 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.363961245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/47.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.26067794 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 336367650000 ps |
| CPU time | 260.33 seconds |
| Started | Sep 18 04:10:13 AM UTC 24 |
| Finished | Sep 18 04:47:42 AM UTC 24 |
| Peak memory | 175120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26067794 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_ fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.26067794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/48.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.1748127171 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 336643610000 ps |
| CPU time | 252.02 seconds |
| Started | Sep 18 04:10:13 AM UTC 24 |
| Finished | Sep 18 04:47:41 AM UTC 24 |
| Peak memory | 175120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1748127171 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.1748127171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/49.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.778687082 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 336424870000 ps |
| CPU time | 233.21 seconds |
| Started | Sep 18 03:37:44 AM UTC 24 |
| Finished | Sep 18 04:10:50 AM UTC 24 |
| Peak memory | 175124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=778687082 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.778687082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/5.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.2901264680 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 336987210000 ps |
| CPU time | 233.56 seconds |
| Started | Sep 18 03:37:45 AM UTC 24 |
| Finished | Sep 18 04:10:54 AM UTC 24 |
| Peak memory | 175100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2901264680 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.2901264680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/6.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.1225788873 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 336814550000 ps |
| CPU time | 233.73 seconds |
| Started | Sep 18 03:37:45 AM UTC 24 |
| Finished | Sep 18 04:10:45 AM UTC 24 |
| Peak memory | 176620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1225788873 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.1225788873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/7.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.2956311704 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 336801130000 ps |
| CPU time | 233.97 seconds |
| Started | Sep 18 03:37:46 AM UTC 24 |
| Finished | Sep 18 04:10:54 AM UTC 24 |
| Peak memory | 175128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2956311704 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.2956311704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/8.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.512070886 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 336323250000 ps |
| CPU time | 233.38 seconds |
| Started | Sep 18 03:37:47 AM UTC 24 |
| Finished | Sep 18 04:10:56 AM UTC 24 |
| Peak memory | 176656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=512070886 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.512070886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/9.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.1657164683 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 336450310000 ps |
| CPU time | 226.31 seconds |
| Started | Sep 18 03:36:15 AM UTC 24 |
| Finished | Sep 18 04:08:57 AM UTC 24 |
| Peak memory | 174992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1657164683 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.1657164683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/1.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.474264477 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 336424150000 ps |
| CPU time | 226.68 seconds |
| Started | Sep 18 03:36:33 AM UTC 24 |
| Finished | Sep 18 04:09:14 AM UTC 24 |
| Peak memory | 176656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=474264477 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.474264477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/10.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.1241914004 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 336707170000 ps |
| CPU time | 227.75 seconds |
| Started | Sep 18 03:36:34 AM UTC 24 |
| Finished | Sep 18 04:09:38 AM UTC 24 |
| Peak memory | 176656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1241914004 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.1241914004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/11.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.2415420796 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 336370510000 ps |
| CPU time | 228.46 seconds |
| Started | Sep 18 03:36:34 AM UTC 24 |
| Finished | Sep 18 04:09:41 AM UTC 24 |
| Peak memory | 176656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2415420796 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.2415420796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/12.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.741903727 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 337029010000 ps |
| CPU time | 228.01 seconds |
| Started | Sep 18 03:36:36 AM UTC 24 |
| Finished | Sep 18 04:09:43 AM UTC 24 |
| Peak memory | 176648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=741903727 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.741903727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/13.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.2583266242 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 337045790000 ps |
| CPU time | 229.22 seconds |
| Started | Sep 18 03:36:36 AM UTC 24 |
| Finished | Sep 18 04:09:53 AM UTC 24 |
| Peak memory | 175124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2583266242 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.2583266242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/14.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.3847330924 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 336398690000 ps |
| CPU time | 227.38 seconds |
| Started | Sep 18 03:36:36 AM UTC 24 |
| Finished | Sep 18 04:09:20 AM UTC 24 |
| Peak memory | 176656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3847330924 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.3847330924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/15.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.1558768432 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 336982750000 ps |
| CPU time | 226.88 seconds |
| Started | Sep 18 03:36:36 AM UTC 24 |
| Finished | Sep 18 04:09:25 AM UTC 24 |
| Peak memory | 176656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1558768432 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.1558768432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/16.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.3648424828 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 336925310000 ps |
| CPU time | 228.63 seconds |
| Started | Sep 18 03:36:42 AM UTC 24 |
| Finished | Sep 18 04:09:49 AM UTC 24 |
| Peak memory | 175080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3648424828 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.3648424828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/17.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.1552673681 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 336539150000 ps |
| CPU time | 230.12 seconds |
| Started | Sep 18 03:36:42 AM UTC 24 |
| Finished | Sep 18 04:10:01 AM UTC 24 |
| Peak memory | 175068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1552673681 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.1552673681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/18.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.3170773862 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 336715050000 ps |
| CPU time | 226.2 seconds |
| Started | Sep 18 03:36:44 AM UTC 24 |
| Finished | Sep 18 04:09:32 AM UTC 24 |
| Peak memory | 176656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3170773862 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.3170773862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/19.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.3350858096 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 336944170000 ps |
| CPU time | 226.49 seconds |
| Started | Sep 18 03:36:15 AM UTC 24 |
| Finished | Sep 18 04:08:59 AM UTC 24 |
| Peak memory | 175128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350858096 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.3350858096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/2.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.4135435255 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 336867850000 ps |
| CPU time | 228.3 seconds |
| Started | Sep 18 03:36:48 AM UTC 24 |
| Finished | Sep 18 04:09:43 AM UTC 24 |
| Peak memory | 176656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4135435255 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.4135435255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/20.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3105744960 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 336889310000 ps |
| CPU time | 228.13 seconds |
| Started | Sep 18 03:36:50 AM UTC 24 |
| Finished | Sep 18 04:09:55 AM UTC 24 |
| Peak memory | 175116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3105744960 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.3105744960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/21.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.888783922 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 337113130000 ps |
| CPU time | 228.05 seconds |
| Started | Sep 18 03:36:50 AM UTC 24 |
| Finished | Sep 18 04:09:46 AM UTC 24 |
| Peak memory | 176648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=888783922 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.888783922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/22.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.2389350270 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 336432110000 ps |
| CPU time | 227.09 seconds |
| Started | Sep 18 03:36:54 AM UTC 24 |
| Finished | Sep 18 04:09:43 AM UTC 24 |
| Peak memory | 176652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2389350270 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.2389350270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/23.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.90735103 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 336661630000 ps |
| CPU time | 229.6 seconds |
| Started | Sep 18 03:36:57 AM UTC 24 |
| Finished | Sep 18 04:10:12 AM UTC 24 |
| Peak memory | 175132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=90735103 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_ gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.90735103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/24.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.2190399872 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 336981490000 ps |
| CPU time | 228.02 seconds |
| Started | Sep 18 03:36:57 AM UTC 24 |
| Finished | Sep 18 04:10:01 AM UTC 24 |
| Peak memory | 176656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2190399872 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.2190399872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/25.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.3501763332 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 336503690000 ps |
| CPU time | 226.51 seconds |
| Started | Sep 18 03:37:01 AM UTC 24 |
| Finished | Sep 18 04:09:43 AM UTC 24 |
| Peak memory | 176656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3501763332 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.3501763332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/26.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.3559300437 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 336833990000 ps |
| CPU time | 225.64 seconds |
| Started | Sep 18 03:37:01 AM UTC 24 |
| Finished | Sep 18 04:09:44 AM UTC 24 |
| Peak memory | 176656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3559300437 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.3559300437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/27.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.963165961 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 336833750000 ps |
| CPU time | 226.98 seconds |
| Started | Sep 18 03:37:05 AM UTC 24 |
| Finished | Sep 18 04:09:57 AM UTC 24 |
| Peak memory | 176660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=963165961 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.963165961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/28.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.1933864138 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 337076530000 ps |
| CPU time | 227.22 seconds |
| Started | Sep 18 03:37:12 AM UTC 24 |
| Finished | Sep 18 04:10:03 AM UTC 24 |
| Peak memory | 175124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1933864138 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.1933864138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/29.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.340785928 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 337039710000 ps |
| CPU time | 227.6 seconds |
| Started | Sep 18 03:36:15 AM UTC 24 |
| Finished | Sep 18 04:09:03 AM UTC 24 |
| Peak memory | 175124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=340785928 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.340785928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/3.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.654603710 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 336718590000 ps |
| CPU time | 227 seconds |
| Started | Sep 18 03:37:12 AM UTC 24 |
| Finished | Sep 18 04:10:08 AM UTC 24 |
| Peak memory | 175128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=654603710 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.654603710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/30.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.1543264810 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 336451570000 ps |
| CPU time | 227 seconds |
| Started | Sep 18 03:37:13 AM UTC 24 |
| Finished | Sep 18 04:10:09 AM UTC 24 |
| Peak memory | 176656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1543264810 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.1543264810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/31.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.2067882466 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 336691150000 ps |
| CPU time | 228.6 seconds |
| Started | Sep 18 03:37:14 AM UTC 24 |
| Finished | Sep 18 04:10:19 AM UTC 24 |
| Peak memory | 176656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2067882466 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.2067882466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/32.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.154445644 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 336376010000 ps |
| CPU time | 227.43 seconds |
| Started | Sep 18 03:37:16 AM UTC 24 |
| Finished | Sep 18 04:10:13 AM UTC 24 |
| Peak memory | 175128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=154445644 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.154445644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/33.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.708261368 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 336420170000 ps |
| CPU time | 228.09 seconds |
| Started | Sep 18 03:37:19 AM UTC 24 |
| Finished | Sep 18 04:10:24 AM UTC 24 |
| Peak memory | 176656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=708261368 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.708261368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/34.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.3701453305 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 336486030000 ps |
| CPU time | 225.7 seconds |
| Started | Sep 18 03:37:20 AM UTC 24 |
| Finished | Sep 18 04:09:59 AM UTC 24 |
| Peak memory | 176656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3701453305 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.3701453305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/35.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.2322402780 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 336724570000 ps |
| CPU time | 228.24 seconds |
| Started | Sep 18 03:37:22 AM UTC 24 |
| Finished | Sep 18 04:10:23 AM UTC 24 |
| Peak memory | 176656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2322402780 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.2322402780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/36.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.2451732687 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 336774750000 ps |
| CPU time | 225.98 seconds |
| Started | Sep 18 03:37:24 AM UTC 24 |
| Finished | Sep 18 04:10:09 AM UTC 24 |
| Peak memory | 175124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2451732687 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.2451732687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/37.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.1990161599 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 336554710000 ps |
| CPU time | 229.12 seconds |
| Started | Sep 18 03:37:25 AM UTC 24 |
| Finished | Sep 18 04:10:42 AM UTC 24 |
| Peak memory | 175124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1990161599 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.1990161599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/38.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.2953641802 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 336942110000 ps |
| CPU time | 228.7 seconds |
| Started | Sep 18 03:37:27 AM UTC 24 |
| Finished | Sep 18 04:10:40 AM UTC 24 |
| Peak memory | 176656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2953641802 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.2953641802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/39.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.353055147 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 336361490000 ps |
| CPU time | 227.67 seconds |
| Started | Sep 18 03:36:17 AM UTC 24 |
| Finished | Sep 18 04:09:22 AM UTC 24 |
| Peak memory | 176656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=353055147 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.353055147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/4.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.1219036674 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 336912470000 ps |
| CPU time | 227.14 seconds |
| Started | Sep 18 03:37:27 AM UTC 24 |
| Finished | Sep 18 04:10:19 AM UTC 24 |
| Peak memory | 174908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1219036674 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.1219036674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/40.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.2115503893 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 336540070000 ps |
| CPU time | 227.13 seconds |
| Started | Sep 18 03:37:27 AM UTC 24 |
| Finished | Sep 18 04:10:27 AM UTC 24 |
| Peak memory | 175124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2115503893 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.2115503893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/41.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.3541749125 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 336725490000 ps |
| CPU time | 226.32 seconds |
| Started | Sep 18 03:37:28 AM UTC 24 |
| Finished | Sep 18 04:10:11 AM UTC 24 |
| Peak memory | 176656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3541749125 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.3541749125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/42.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.1585244061 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 336499950000 ps |
| CPU time | 227.08 seconds |
| Started | Sep 18 03:37:29 AM UTC 24 |
| Finished | Sep 18 04:10:25 AM UTC 24 |
| Peak memory | 175124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1585244061 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.1585244061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/43.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.1854959608 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 336908890000 ps |
| CPU time | 227.33 seconds |
| Started | Sep 18 03:37:31 AM UTC 24 |
| Finished | Sep 18 04:10:27 AM UTC 24 |
| Peak memory | 175124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1854959608 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.1854959608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/44.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.1649544153 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 336429410000 ps |
| CPU time | 226.77 seconds |
| Started | Sep 18 03:37:31 AM UTC 24 |
| Finished | Sep 18 04:10:12 AM UTC 24 |
| Peak memory | 175124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1649544153 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.1649544153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/45.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.793967415 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 336724070000 ps |
| CPU time | 226.86 seconds |
| Started | Sep 18 03:37:31 AM UTC 24 |
| Finished | Sep 18 04:10:31 AM UTC 24 |
| Peak memory | 175164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=793967415 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.793967415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/46.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.1195992324 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 336643710000 ps |
| CPU time | 228.4 seconds |
| Started | Sep 18 03:37:32 AM UTC 24 |
| Finished | Sep 18 04:10:43 AM UTC 24 |
| Peak memory | 175124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1195992324 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.1195992324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/47.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.516407928 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 336637090000 ps |
| CPU time | 227.86 seconds |
| Started | Sep 18 03:37:32 AM UTC 24 |
| Finished | Sep 18 04:10:29 AM UTC 24 |
| Peak memory | 176652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=516407928 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.516407928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/48.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.3520005023 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 336525670000 ps |
| CPU time | 227.21 seconds |
| Started | Sep 18 03:37:33 AM UTC 24 |
| Finished | Sep 18 04:10:30 AM UTC 24 |
| Peak memory | 176656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3520005023 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.3520005023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/49.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.2276205838 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 336681690000 ps |
| CPU time | 227.92 seconds |
| Started | Sep 18 03:36:28 AM UTC 24 |
| Finished | Sep 18 04:09:12 AM UTC 24 |
| Peak memory | 175128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2276205838 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.2276205838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/5.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.2221982650 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 337073610000 ps |
| CPU time | 227.44 seconds |
| Started | Sep 18 03:36:28 AM UTC 24 |
| Finished | Sep 18 04:09:21 AM UTC 24 |
| Peak memory | 176652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2221982650 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.2221982650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/6.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.3858807574 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 336352910000 ps |
| CPU time | 229.27 seconds |
| Started | Sep 18 03:36:31 AM UTC 24 |
| Finished | Sep 18 04:09:44 AM UTC 24 |
| Peak memory | 176652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3858807574 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.3858807574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/7.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.3856094407 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 336647070000 ps |
| CPU time | 227.85 seconds |
| Started | Sep 18 03:36:32 AM UTC 24 |
| Finished | Sep 18 04:09:32 AM UTC 24 |
| Peak memory | 176660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3856094407 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.3856094407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/8.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.392394339 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 336588170000 ps |
| CPU time | 229.1 seconds |
| Started | Sep 18 03:36:33 AM UTC 24 |
| Finished | Sep 18 04:09:46 AM UTC 24 |
| Peak memory | 175124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=392394339 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.392394339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/9.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.2846484381 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 1496250000 ps |
| CPU time | 2.17 seconds |
| Started | Sep 18 01:19:23 AM UTC 24 |
| Finished | Sep 18 01:19:37 AM UTC 24 |
| Peak memory | 177764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2846484381 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.2846484381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/1.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.2964659368 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 1342030000 ps |
| CPU time | 1.93 seconds |
| Started | Sep 18 01:19:29 AM UTC 24 |
| Finished | Sep 18 01:19:41 AM UTC 24 |
| Peak memory | 177772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2964659368 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.2964659368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/10.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.2256181944 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 1280890000 ps |
| CPU time | 1.93 seconds |
| Started | Sep 18 01:19:29 AM UTC 24 |
| Finished | Sep 18 01:19:41 AM UTC 24 |
| Peak memory | 177772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2256181944 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.2256181944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/11.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.2103610593 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 1542670000 ps |
| CPU time | 2.18 seconds |
| Started | Sep 18 01:19:30 AM UTC 24 |
| Finished | Sep 18 01:19:44 AM UTC 24 |
| Peak memory | 177772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2103610593 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.2103610593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/12.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.2981758107 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 1345070000 ps |
| CPU time | 1.92 seconds |
| Started | Sep 18 01:19:30 AM UTC 24 |
| Finished | Sep 18 01:19:42 AM UTC 24 |
| Peak memory | 177772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2981758107 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.2981758107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/13.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.107207818 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 1451710000 ps |
| CPU time | 1.97 seconds |
| Started | Sep 18 01:19:30 AM UTC 24 |
| Finished | Sep 18 01:19:43 AM UTC 24 |
| Peak memory | 177760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=107207818 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f ib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.107207818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/14.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.134844411 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 1289130000 ps |
| CPU time | 2.02 seconds |
| Started | Sep 18 01:19:30 AM UTC 24 |
| Finished | Sep 18 01:19:42 AM UTC 24 |
| Peak memory | 177760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=134844411 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f ib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.134844411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/15.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.3691128760 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 1406310000 ps |
| CPU time | 1.98 seconds |
| Started | Sep 18 01:19:30 AM UTC 24 |
| Finished | Sep 18 01:19:43 AM UTC 24 |
| Peak memory | 177760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3691128760 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.3691128760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/16.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.2940232364 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 1441310000 ps |
| CPU time | 2.07 seconds |
| Started | Sep 18 01:19:30 AM UTC 24 |
| Finished | Sep 18 01:19:43 AM UTC 24 |
| Peak memory | 177772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2940232364 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.2940232364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/17.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.742622281 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 1533210000 ps |
| CPU time | 2.28 seconds |
| Started | Sep 18 01:19:30 AM UTC 24 |
| Finished | Sep 18 01:19:44 AM UTC 24 |
| Peak memory | 177760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=742622281 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f ib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.742622281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/18.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.422740091 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 1495970000 ps |
| CPU time | 2.21 seconds |
| Started | Sep 18 01:19:31 AM UTC 24 |
| Finished | Sep 18 01:19:45 AM UTC 24 |
| Peak memory | 177760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=422740091 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f ib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.422740091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/19.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.4271255291 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 1550690000 ps |
| CPU time | 2.35 seconds |
| Started | Sep 18 01:19:23 AM UTC 24 |
| Finished | Sep 18 01:19:38 AM UTC 24 |
| Peak memory | 177744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4271255291 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.4271255291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/2.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.2847807293 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 1588290000 ps |
| CPU time | 2.17 seconds |
| Started | Sep 18 01:19:31 AM UTC 24 |
| Finished | Sep 18 01:19:45 AM UTC 24 |
| Peak memory | 177772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2847807293 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.2847807293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/20.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.2058473399 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 1503390000 ps |
| CPU time | 2.15 seconds |
| Started | Sep 18 01:19:32 AM UTC 24 |
| Finished | Sep 18 01:19:45 AM UTC 24 |
| Peak memory | 177772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2058473399 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.2058473399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/21.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.4104546655 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 1439430000 ps |
| CPU time | 2.16 seconds |
| Started | Sep 18 01:19:34 AM UTC 24 |
| Finished | Sep 18 01:19:47 AM UTC 24 |
| Peak memory | 177772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4104546655 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.4104546655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/22.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.3943702726 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 1528110000 ps |
| CPU time | 2.23 seconds |
| Started | Sep 18 01:19:34 AM UTC 24 |
| Finished | Sep 18 01:19:47 AM UTC 24 |
| Peak memory | 177772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3943702726 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.3943702726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/23.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.263375583 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 1448610000 ps |
| CPU time | 2.17 seconds |
| Started | Sep 18 01:19:34 AM UTC 24 |
| Finished | Sep 18 01:19:47 AM UTC 24 |
| Peak memory | 177760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=263375583 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f ib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.263375583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/24.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.330693849 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 1484330000 ps |
| CPU time | 2.25 seconds |
| Started | Sep 18 01:19:34 AM UTC 24 |
| Finished | Sep 18 01:19:47 AM UTC 24 |
| Peak memory | 177760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=330693849 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f ib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.330693849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/25.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.3629090210 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 1517610000 ps |
| CPU time | 2.11 seconds |
| Started | Sep 18 01:19:35 AM UTC 24 |
| Finished | Sep 18 01:19:48 AM UTC 24 |
| Peak memory | 177772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3629090210 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.3629090210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/26.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.2038539910 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 1024310000 ps |
| CPU time | 1.71 seconds |
| Started | Sep 18 01:19:36 AM UTC 24 |
| Finished | Sep 18 01:19:45 AM UTC 24 |
| Peak memory | 177772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2038539910 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.2038539910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/27.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.2970145617 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 1519890000 ps |
| CPU time | 2.12 seconds |
| Started | Sep 18 01:19:36 AM UTC 24 |
| Finished | Sep 18 01:19:49 AM UTC 24 |
| Peak memory | 177704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2970145617 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.2970145617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/28.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.4258446547 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 1503390000 ps |
| CPU time | 2.16 seconds |
| Started | Sep 18 01:19:36 AM UTC 24 |
| Finished | Sep 18 01:19:49 AM UTC 24 |
| Peak memory | 177772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4258446547 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.4258446547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/29.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.3622262603 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 1629390000 ps |
| CPU time | 2.23 seconds |
| Started | Sep 18 01:19:25 AM UTC 24 |
| Finished | Sep 18 01:19:39 AM UTC 24 |
| Peak memory | 177764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3622262603 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.3622262603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/3.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.1599422613 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 1212070000 ps |
| CPU time | 1.97 seconds |
| Started | Sep 18 01:19:37 AM UTC 24 |
| Finished | Sep 18 01:19:48 AM UTC 24 |
| Peak memory | 177772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1599422613 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.1599422613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/30.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.3702146788 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 1536010000 ps |
| CPU time | 2.16 seconds |
| Started | Sep 18 01:19:37 AM UTC 24 |
| Finished | Sep 18 01:19:51 AM UTC 24 |
| Peak memory | 177772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3702146788 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.3702146788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/31.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.3708123284 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 1501290000 ps |
| CPU time | 2.15 seconds |
| Started | Sep 18 01:19:38 AM UTC 24 |
| Finished | Sep 18 01:19:51 AM UTC 24 |
| Peak memory | 177772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3708123284 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.3708123284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/32.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.728480328 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 1518150000 ps |
| CPU time | 2.03 seconds |
| Started | Sep 18 01:19:38 AM UTC 24 |
| Finished | Sep 18 01:19:52 AM UTC 24 |
| Peak memory | 177760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=728480328 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f ib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.728480328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/33.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.2433256370 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 1519350000 ps |
| CPU time | 2.11 seconds |
| Started | Sep 18 01:19:39 AM UTC 24 |
| Finished | Sep 18 01:19:52 AM UTC 24 |
| Peak memory | 177772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2433256370 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.2433256370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/34.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.3348187814 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 1409530000 ps |
| CPU time | 2.13 seconds |
| Started | Sep 18 01:19:39 AM UTC 24 |
| Finished | Sep 18 01:19:52 AM UTC 24 |
| Peak memory | 177772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3348187814 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.3348187814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/35.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.3938938797 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 1258570000 ps |
| CPU time | 1.92 seconds |
| Started | Sep 18 01:19:40 AM UTC 24 |
| Finished | Sep 18 01:19:52 AM UTC 24 |
| Peak memory | 177772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3938938797 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.3938938797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/36.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.669498978 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 1165070000 ps |
| CPU time | 1.82 seconds |
| Started | Sep 18 01:19:40 AM UTC 24 |
| Finished | Sep 18 01:19:51 AM UTC 24 |
| Peak memory | 177760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=669498978 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f ib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.669498978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/37.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.4240898728 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 1292910000 ps |
| CPU time | 2.03 seconds |
| Started | Sep 18 01:19:40 AM UTC 24 |
| Finished | Sep 18 01:19:52 AM UTC 24 |
| Peak memory | 177772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4240898728 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.4240898728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/38.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.1351633582 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 1200110000 ps |
| CPU time | 1.9 seconds |
| Started | Sep 18 01:19:42 AM UTC 24 |
| Finished | Sep 18 01:19:52 AM UTC 24 |
| Peak memory | 177772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1351633582 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.1351633582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/39.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3667456411 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 1523650000 ps |
| CPU time | 2.31 seconds |
| Started | Sep 18 01:19:25 AM UTC 24 |
| Finished | Sep 18 01:19:38 AM UTC 24 |
| Peak memory | 177764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3667456411 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.3667456411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/4.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.3631056144 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 1488430000 ps |
| CPU time | 2.06 seconds |
| Started | Sep 18 01:19:42 AM UTC 24 |
| Finished | Sep 18 01:19:54 AM UTC 24 |
| Peak memory | 177760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3631056144 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.3631056144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/40.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.3578210733 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 1502510000 ps |
| CPU time | 2.16 seconds |
| Started | Sep 18 01:19:43 AM UTC 24 |
| Finished | Sep 18 01:19:55 AM UTC 24 |
| Peak memory | 177772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3578210733 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.3578210733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/41.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.3035077146 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 1299670000 ps |
| CPU time | 1.96 seconds |
| Started | Sep 18 01:19:43 AM UTC 24 |
| Finished | Sep 18 01:19:54 AM UTC 24 |
| Peak memory | 177772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3035077146 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.3035077146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/42.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.302937233 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 1411270000 ps |
| CPU time | 2.03 seconds |
| Started | Sep 18 01:19:43 AM UTC 24 |
| Finished | Sep 18 01:19:54 AM UTC 24 |
| Peak memory | 177480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=302937233 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f ib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.302937233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/43.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.1750057233 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 1284650000 ps |
| CPU time | 1.96 seconds |
| Started | Sep 18 01:19:43 AM UTC 24 |
| Finished | Sep 18 01:19:54 AM UTC 24 |
| Peak memory | 177772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1750057233 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.1750057233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/44.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.4285308049 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 1347470000 ps |
| CPU time | 1.96 seconds |
| Started | Sep 18 01:19:44 AM UTC 24 |
| Finished | Sep 18 01:19:55 AM UTC 24 |
| Peak memory | 177768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4285308049 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.4285308049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/45.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.937678016 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 1396250000 ps |
| CPU time | 1.92 seconds |
| Started | Sep 18 01:19:44 AM UTC 24 |
| Finished | Sep 18 01:19:55 AM UTC 24 |
| Peak memory | 177760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=937678016 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f ib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.937678016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/46.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.3416984405 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 1343690000 ps |
| CPU time | 2.14 seconds |
| Started | Sep 18 01:19:44 AM UTC 24 |
| Finished | Sep 18 01:19:55 AM UTC 24 |
| Peak memory | 177768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3416984405 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.3416984405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/47.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.3550296110 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 1573170000 ps |
| CPU time | 2.1 seconds |
| Started | Sep 18 01:19:45 AM UTC 24 |
| Finished | Sep 18 01:19:57 AM UTC 24 |
| Peak memory | 177772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3550296110 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.3550296110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/48.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.3343747205 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 1531330000 ps |
| CPU time | 2.19 seconds |
| Started | Sep 18 01:19:45 AM UTC 24 |
| Finished | Sep 18 01:19:57 AM UTC 24 |
| Peak memory | 177772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3343747205 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.3343747205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/49.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.1277489102 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 1508210000 ps |
| CPU time | 2.22 seconds |
| Started | Sep 18 01:19:26 AM UTC 24 |
| Finished | Sep 18 01:19:39 AM UTC 24 |
| Peak memory | 177764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1277489102 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.1277489102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/5.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.928462653 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 1461910000 ps |
| CPU time | 2.18 seconds |
| Started | Sep 18 01:19:26 AM UTC 24 |
| Finished | Sep 18 01:19:39 AM UTC 24 |
| Peak memory | 177764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=928462653 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f ib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.928462653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/6.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.3525523096 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 1467850000 ps |
| CPU time | 2.04 seconds |
| Started | Sep 18 01:19:26 AM UTC 24 |
| Finished | Sep 18 01:19:39 AM UTC 24 |
| Peak memory | 177764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3525523096 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.3525523096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/7.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.388683207 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 1600230000 ps |
| CPU time | 2.12 seconds |
| Started | Sep 18 01:19:27 AM UTC 24 |
| Finished | Sep 18 01:19:41 AM UTC 24 |
| Peak memory | 177764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=388683207 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f ib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.388683207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/8.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.123276230 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 1533070000 ps |
| CPU time | 2.28 seconds |
| Started | Sep 18 01:19:28 AM UTC 24 |
| Finished | Sep 18 01:19:42 AM UTC 24 |
| Peak memory | 177764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=123276230 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f ib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.123276230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/9.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.3281136112 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 1549650000 ps |
| CPU time | 2.36 seconds |
| Started | Sep 18 01:18:56 AM UTC 24 |
| Finished | Sep 18 01:19:10 AM UTC 24 |
| Peak memory | 175212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3281136112 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.3281136112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/1.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.2942760638 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 1606590000 ps |
| CPU time | 2.48 seconds |
| Started | Sep 18 01:19:01 AM UTC 24 |
| Finished | Sep 18 01:19:15 AM UTC 24 |
| Peak memory | 177772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2942760638 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.2942760638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/10.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.3781185793 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 1547890000 ps |
| CPU time | 2.34 seconds |
| Started | Sep 18 01:19:02 AM UTC 24 |
| Finished | Sep 18 01:19:16 AM UTC 24 |
| Peak memory | 177772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3781185793 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.3781185793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/11.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.212495478 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 1395890000 ps |
| CPU time | 2.27 seconds |
| Started | Sep 18 01:19:03 AM UTC 24 |
| Finished | Sep 18 01:19:15 AM UTC 24 |
| Peak memory | 177760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=212495478 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g al.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.212495478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/12.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.1324551443 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 1503110000 ps |
| CPU time | 2.29 seconds |
| Started | Sep 18 01:19:05 AM UTC 24 |
| Finished | Sep 18 01:19:18 AM UTC 24 |
| Peak memory | 177772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1324551443 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.1324551443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/13.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.2608226809 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 1473190000 ps |
| CPU time | 2.26 seconds |
| Started | Sep 18 01:19:05 AM UTC 24 |
| Finished | Sep 18 01:19:18 AM UTC 24 |
| Peak memory | 177772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2608226809 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.2608226809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/14.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.2824921048 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 1380290000 ps |
| CPU time | 2.23 seconds |
| Started | Sep 18 01:19:05 AM UTC 24 |
| Finished | Sep 18 01:19:18 AM UTC 24 |
| Peak memory | 177772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2824921048 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.2824921048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/15.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.2530857886 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 1033530000 ps |
| CPU time | 1.8 seconds |
| Started | Sep 18 01:19:06 AM UTC 24 |
| Finished | Sep 18 01:19:16 AM UTC 24 |
| Peak memory | 177772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2530857886 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.2530857886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/16.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.631821782 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 1529890000 ps |
| CPU time | 2.36 seconds |
| Started | Sep 18 01:19:06 AM UTC 24 |
| Finished | Sep 18 01:19:20 AM UTC 24 |
| Peak memory | 177760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=631821782 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g al.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.631821782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/17.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.1917384801 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 1462390000 ps |
| CPU time | 2.3 seconds |
| Started | Sep 18 01:19:06 AM UTC 24 |
| Finished | Sep 18 01:19:19 AM UTC 24 |
| Peak memory | 177772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1917384801 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.1917384801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/18.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.4097024882 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 1419870000 ps |
| CPU time | 2.25 seconds |
| Started | Sep 18 01:19:07 AM UTC 24 |
| Finished | Sep 18 01:19:20 AM UTC 24 |
| Peak memory | 177772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4097024882 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.4097024882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/19.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.2557289835 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 1238430000 ps |
| CPU time | 2.11 seconds |
| Started | Sep 18 01:18:57 AM UTC 24 |
| Finished | Sep 18 01:19:09 AM UTC 24 |
| Peak memory | 177828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2557289835 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.2557289835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/2.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.1289889156 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 1222250000 ps |
| CPU time | 1.95 seconds |
| Started | Sep 18 01:19:09 AM UTC 24 |
| Finished | Sep 18 01:19:21 AM UTC 24 |
| Peak memory | 177772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1289889156 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.1289889156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/20.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.3902124305 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 1283370000 ps |
| CPU time | 1.89 seconds |
| Started | Sep 18 01:19:09 AM UTC 24 |
| Finished | Sep 18 01:19:22 AM UTC 24 |
| Peak memory | 177772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3902124305 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.3902124305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/21.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.70017696 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 1360090000 ps |
| CPU time | 2.05 seconds |
| Started | Sep 18 01:19:10 AM UTC 24 |
| Finished | Sep 18 01:19:22 AM UTC 24 |
| Peak memory | 177760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=70017696 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ga l.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.70017696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/22.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.2397392393 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 1166890000 ps |
| CPU time | 1.81 seconds |
| Started | Sep 18 01:19:10 AM UTC 24 |
| Finished | Sep 18 01:19:21 AM UTC 24 |
| Peak memory | 177772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2397392393 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.2397392393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/23.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.4196409251 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 1386170000 ps |
| CPU time | 2.04 seconds |
| Started | Sep 18 01:19:11 AM UTC 24 |
| Finished | Sep 18 01:19:23 AM UTC 24 |
| Peak memory | 177764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4196409251 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.4196409251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/24.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.301947000 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 1442370000 ps |
| CPU time | 2.12 seconds |
| Started | Sep 18 01:19:11 AM UTC 24 |
| Finished | Sep 18 01:19:24 AM UTC 24 |
| Peak memory | 177760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=301947000 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g al.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.301947000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/25.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.3086898862 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 1579450000 ps |
| CPU time | 2.09 seconds |
| Started | Sep 18 01:19:11 AM UTC 24 |
| Finished | Sep 18 01:19:25 AM UTC 24 |
| Peak memory | 177772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3086898862 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.3086898862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/26.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.2168252195 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 1473710000 ps |
| CPU time | 2.25 seconds |
| Started | Sep 18 01:19:12 AM UTC 24 |
| Finished | Sep 18 01:19:25 AM UTC 24 |
| Peak memory | 177772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2168252195 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.2168252195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/27.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.807836940 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 1150290000 ps |
| CPU time | 1.94 seconds |
| Started | Sep 18 01:19:12 AM UTC 24 |
| Finished | Sep 18 01:19:22 AM UTC 24 |
| Peak memory | 177760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=807836940 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g al.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.807836940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/28.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.3319953260 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 1402570000 ps |
| CPU time | 2.24 seconds |
| Started | Sep 18 01:19:13 AM UTC 24 |
| Finished | Sep 18 01:19:26 AM UTC 24 |
| Peak memory | 177772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3319953260 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.3319953260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/29.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.3262289827 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 1429030000 ps |
| CPU time | 2.37 seconds |
| Started | Sep 18 01:18:57 AM UTC 24 |
| Finished | Sep 18 01:19:10 AM UTC 24 |
| Peak memory | 177764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3262289827 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.3262289827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/3.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.1834992161 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 1608810000 ps |
| CPU time | 2.3 seconds |
| Started | Sep 18 01:19:13 AM UTC 24 |
| Finished | Sep 18 01:19:27 AM UTC 24 |
| Peak memory | 177772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1834992161 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.1834992161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/30.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.767464995 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 1514450000 ps |
| CPU time | 2.08 seconds |
| Started | Sep 18 01:19:15 AM UTC 24 |
| Finished | Sep 18 01:19:29 AM UTC 24 |
| Peak memory | 177760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=767464995 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g al.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.767464995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/31.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.1282585629 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 1535230000 ps |
| CPU time | 2.24 seconds |
| Started | Sep 18 01:19:15 AM UTC 24 |
| Finished | Sep 18 01:19:29 AM UTC 24 |
| Peak memory | 177772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1282585629 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.1282585629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/32.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.3090883438 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 1505830000 ps |
| CPU time | 2.05 seconds |
| Started | Sep 18 01:19:15 AM UTC 24 |
| Finished | Sep 18 01:19:29 AM UTC 24 |
| Peak memory | 177772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3090883438 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.3090883438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/33.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.2006970327 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 1573650000 ps |
| CPU time | 2.24 seconds |
| Started | Sep 18 01:19:15 AM UTC 24 |
| Finished | Sep 18 01:19:29 AM UTC 24 |
| Peak memory | 177772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2006970327 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.2006970327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/34.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.1040270850 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 1512310000 ps |
| CPU time | 2.26 seconds |
| Started | Sep 18 01:19:15 AM UTC 24 |
| Finished | Sep 18 01:19:29 AM UTC 24 |
| Peak memory | 177772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1040270850 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.1040270850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/35.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.2010536021 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 1591550000 ps |
| CPU time | 2.41 seconds |
| Started | Sep 18 01:19:15 AM UTC 24 |
| Finished | Sep 18 01:19:30 AM UTC 24 |
| Peak memory | 177772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2010536021 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.2010536021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/36.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.4053516034 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 1541750000 ps |
| CPU time | 2.26 seconds |
| Started | Sep 18 01:19:16 AM UTC 24 |
| Finished | Sep 18 01:19:30 AM UTC 24 |
| Peak memory | 177772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4053516034 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.4053516034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/37.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.673273248 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 1348970000 ps |
| CPU time | 2.17 seconds |
| Started | Sep 18 01:19:17 AM UTC 24 |
| Finished | Sep 18 01:19:29 AM UTC 24 |
| Peak memory | 177760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=673273248 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g al.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.673273248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/38.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.1879167241 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 1270410000 ps |
| CPU time | 1.96 seconds |
| Started | Sep 18 01:19:17 AM UTC 24 |
| Finished | Sep 18 01:19:28 AM UTC 24 |
| Peak memory | 177772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1879167241 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.1879167241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/39.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.3371899107 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 1596970000 ps |
| CPU time | 2.33 seconds |
| Started | Sep 18 01:18:57 AM UTC 24 |
| Finished | Sep 18 01:19:12 AM UTC 24 |
| Peak memory | 177408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3371899107 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.3371899107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/4.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.1532098462 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 1542710000 ps |
| CPU time | 2.09 seconds |
| Started | Sep 18 01:19:17 AM UTC 24 |
| Finished | Sep 18 01:19:30 AM UTC 24 |
| Peak memory | 177772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1532098462 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.1532098462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/40.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.3021041685 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 1556750000 ps |
| CPU time | 2.3 seconds |
| Started | Sep 18 01:19:17 AM UTC 24 |
| Finished | Sep 18 01:19:31 AM UTC 24 |
| Peak memory | 177772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3021041685 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.3021041685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/41.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.3833784977 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 1503690000 ps |
| CPU time | 2.16 seconds |
| Started | Sep 18 01:19:19 AM UTC 24 |
| Finished | Sep 18 01:19:32 AM UTC 24 |
| Peak memory | 177720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3833784977 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.3833784977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/42.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.4229983206 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 1559050000 ps |
| CPU time | 2.26 seconds |
| Started | Sep 18 01:19:19 AM UTC 24 |
| Finished | Sep 18 01:19:33 AM UTC 24 |
| Peak memory | 177724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4229983206 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.4229983206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/43.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.1361620378 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 1495650000 ps |
| CPU time | 2.17 seconds |
| Started | Sep 18 01:19:19 AM UTC 24 |
| Finished | Sep 18 01:19:33 AM UTC 24 |
| Peak memory | 177772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1361620378 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.1361620378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/44.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.3382817015 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 1459030000 ps |
| CPU time | 2.12 seconds |
| Started | Sep 18 01:19:20 AM UTC 24 |
| Finished | Sep 18 01:19:33 AM UTC 24 |
| Peak memory | 177772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3382817015 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.3382817015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/45.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.1858476486 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 1458490000 ps |
| CPU time | 2.08 seconds |
| Started | Sep 18 01:19:21 AM UTC 24 |
| Finished | Sep 18 01:19:34 AM UTC 24 |
| Peak memory | 177772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1858476486 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.1858476486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/46.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.4174194650 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 1512570000 ps |
| CPU time | 2.28 seconds |
| Started | Sep 18 01:19:21 AM UTC 24 |
| Finished | Sep 18 01:19:35 AM UTC 24 |
| Peak memory | 177772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4174194650 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.4174194650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/47.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.1152709400 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 1358710000 ps |
| CPU time | 2.11 seconds |
| Started | Sep 18 01:19:22 AM UTC 24 |
| Finished | Sep 18 01:19:35 AM UTC 24 |
| Peak memory | 177768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1152709400 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.1152709400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/48.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.2053250186 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 1499850000 ps |
| CPU time | 2.03 seconds |
| Started | Sep 18 01:19:22 AM UTC 24 |
| Finished | Sep 18 01:19:36 AM UTC 24 |
| Peak memory | 177772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2053250186 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.2053250186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/49.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.1790758088 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 1485530000 ps |
| CPU time | 2.29 seconds |
| Started | Sep 18 01:18:57 AM UTC 24 |
| Finished | Sep 18 01:19:11 AM UTC 24 |
| Peak memory | 177372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1790758088 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.1790758088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/5.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.1914192154 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 1536730000 ps |
| CPU time | 2.5 seconds |
| Started | Sep 18 01:18:58 AM UTC 24 |
| Finished | Sep 18 01:19:12 AM UTC 24 |
| Peak memory | 177764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1914192154 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.1914192154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/6.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.1297835545 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 1594990000 ps |
| CPU time | 2.47 seconds |
| Started | Sep 18 01:18:59 AM UTC 24 |
| Finished | Sep 18 01:19:14 AM UTC 24 |
| Peak memory | 177764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1297835545 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.1297835545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/7.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.3212694520 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 1571410000 ps |
| CPU time | 2.52 seconds |
| Started | Sep 18 01:19:00 AM UTC 24 |
| Finished | Sep 18 01:19:15 AM UTC 24 |
| Peak memory | 177764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3212694520 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.3212694520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/8.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.2932971745 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 1501210000 ps |
| CPU time | 2.36 seconds |
| Started | Sep 18 01:19:01 AM UTC 24 |
| Finished | Sep 18 01:19:14 AM UTC 24 |
| Peak memory | 177764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2932971745 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.2932971745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_lfsr-sim-vcs/9.prim_lfsr_gal_smoke/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |