Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.31 100.00 96.55 100.00 100.00 95.00


Total tests in report: 200
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
87.31 87.31 100.00 100.00 96.55 96.55 100.00 100.00 100.00 100.00 40.00 40.00 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.2924386025
95.31 8.00 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 80.00 40.00 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.2357666336
96.81 1.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 87.50 7.50 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.88735600
98.31 1.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 95.00 7.50 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.494863598

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.2622024885
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.1134072224
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.3786553605
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.4163931183
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.3351554856
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.1380240190
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.45095470
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.4059888913
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.1497764406
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.3693577703
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.1388084356
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.3076553336
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.1753834707
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.2789340245
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.1052516191
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.3942099433
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.1084981181
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.3589639955
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.3286737053
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.2268285085
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.4007914294
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.2662576189
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.3026169405
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3653963803
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.1218035967
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.2440721107
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.1902784856
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.1918667578
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.1119040199
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.3142300678
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.2832664013
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.3526020520
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.1644454339
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.930364600
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.2224046860
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.3789861476
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.2278044069
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.3676463892
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.3428092087
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.3277938120
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.2014933477
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.3336123267
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.519736638
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.2075206159
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.567197531
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.32756542
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.1282569447
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1629355774
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.2802678902
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.2093327010
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.3293181164
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.1326606760
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.3574691526
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.3399234029
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.3901630268
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.2809841855
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.944459840
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.3767092715
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.1400049530
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.4148401501
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.2844364571
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.576890025
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.745632900
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.4269867403
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.955170481
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.1910830061
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.1733158852
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.2417097831
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.2413248193
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.2129305545
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.648609003
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.3380228238
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.3941614454
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.826019395
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.1073141419
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.2622199082
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.3590308086
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.1464376294
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.2493741558
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.1885149610
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3138661560
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.289767686
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.641471043
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.1881639946
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.2234684208
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.3503528674
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.3727897984
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.1556861443
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.1706969079
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.2523132098
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.2602068446
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1349070022
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.2639716037
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.1089893346
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.1076639009
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.451720716
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.2400998725
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.3946645077
/workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.2756236067
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Total test records in report: 200
tests.html | tests1.html | tests2.html | tests3.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.2924386025 Sep 24 01:50:57 AM UTC 24 Sep 24 01:51:08 AM UTC 24 1281030000 ps
T2 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.3982083334 Sep 24 01:50:59 AM UTC 24 Sep 24 01:51:08 AM UTC 24 1147870000 ps
T3 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.11702040 Sep 24 01:50:57 AM UTC 24 Sep 24 01:51:09 AM UTC 24 1342590000 ps
T7 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.586519918 Sep 24 01:50:57 AM UTC 24 Sep 24 01:51:09 AM UTC 24 1365730000 ps
T8 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.896891360 Sep 24 01:50:57 AM UTC 24 Sep 24 01:51:09 AM UTC 24 1388870000 ps
T9 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.3141889702 Sep 24 01:50:57 AM UTC 24 Sep 24 01:51:09 AM UTC 24 1435470000 ps
T10 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.1046668328 Sep 24 01:50:59 AM UTC 24 Sep 24 01:51:09 AM UTC 24 1304430000 ps
T11 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.4271414185 Sep 24 01:50:57 AM UTC 24 Sep 24 01:51:09 AM UTC 24 1485990000 ps
T12 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.2294342776 Sep 24 01:50:59 AM UTC 24 Sep 24 01:51:10 AM UTC 24 1299550000 ps
T13 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.3382581160 Sep 24 01:50:57 AM UTC 24 Sep 24 01:51:10 AM UTC 24 1545090000 ps
T41 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.1213886561 Sep 24 01:50:57 AM UTC 24 Sep 24 01:51:10 AM UTC 24 1565110000 ps
T42 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.2113123409 Sep 24 01:50:59 AM UTC 24 Sep 24 01:51:10 AM UTC 24 1356470000 ps
T43 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.76657330 Sep 24 01:50:59 AM UTC 24 Sep 24 01:51:10 AM UTC 24 1345910000 ps
T44 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.2388185874 Sep 24 01:50:59 AM UTC 24 Sep 24 01:51:10 AM UTC 24 1411850000 ps
T45 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.392230988 Sep 24 01:50:59 AM UTC 24 Sep 24 01:51:10 AM UTC 24 1474990000 ps
T46 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.3715855531 Sep 24 01:50:59 AM UTC 24 Sep 24 01:51:11 AM UTC 24 1440270000 ps
T47 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.83868866 Sep 24 01:50:59 AM UTC 24 Sep 24 01:51:11 AM UTC 24 1516850000 ps
T48 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.2297788047 Sep 24 01:50:59 AM UTC 24 Sep 24 01:51:11 AM UTC 24 1528870000 ps
T49 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.684972614 Sep 24 01:50:59 AM UTC 24 Sep 24 01:51:11 AM UTC 24 1528310000 ps
T50 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.1761639131 Sep 24 01:50:59 AM UTC 24 Sep 24 01:51:11 AM UTC 24 1509890000 ps
T51 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.356466958 Sep 24 01:50:59 AM UTC 24 Sep 24 01:51:11 AM UTC 24 1533150000 ps
T52 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.1133163706 Sep 24 01:51:00 AM UTC 24 Sep 24 01:51:11 AM UTC 24 1392450000 ps
T53 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.3999121265 Sep 24 01:50:59 AM UTC 24 Sep 24 01:51:12 AM UTC 24 1543590000 ps
T54 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.3288304187 Sep 24 01:51:01 AM UTC 24 Sep 24 01:51:12 AM UTC 24 1323810000 ps
T55 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.655726307 Sep 24 01:51:01 AM UTC 24 Sep 24 01:51:13 AM UTC 24 1400870000 ps
T56 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.1935644124 Sep 24 01:51:01 AM UTC 24 Sep 24 01:51:13 AM UTC 24 1413890000 ps
T57 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.2813780224 Sep 24 01:51:02 AM UTC 24 Sep 24 01:51:13 AM UTC 24 1302210000 ps
T58 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.911028488 Sep 24 01:51:01 AM UTC 24 Sep 24 01:51:14 AM UTC 24 1454430000 ps
T59 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.4082879431 Sep 24 01:51:01 AM UTC 24 Sep 24 01:51:14 AM UTC 24 1500290000 ps
T60 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.3596995728 Sep 24 01:51:03 AM UTC 24 Sep 24 01:51:14 AM UTC 24 1343170000 ps
T61 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.66641724 Sep 24 01:51:03 AM UTC 24 Sep 24 01:51:14 AM UTC 24 1337690000 ps
T62 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.308342396 Sep 24 01:51:01 AM UTC 24 Sep 24 01:51:14 AM UTC 24 1568530000 ps
T63 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.3109318077 Sep 24 01:51:03 AM UTC 24 Sep 24 01:51:14 AM UTC 24 1447310000 ps
T64 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.1107733217 Sep 24 01:51:01 AM UTC 24 Sep 24 01:51:15 AM UTC 24 1648250000 ps
T65 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.2629386948 Sep 24 01:51:03 AM UTC 24 Sep 24 01:51:15 AM UTC 24 1494590000 ps
T66 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.3381547236 Sep 24 01:51:03 AM UTC 24 Sep 24 01:51:15 AM UTC 24 1547830000 ps
T67 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.585704528 Sep 24 01:51:05 AM UTC 24 Sep 24 01:51:15 AM UTC 24 1302210000 ps
T68 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.4101453497 Sep 24 01:51:03 AM UTC 24 Sep 24 01:51:16 AM UTC 24 1629250000 ps
T69 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.80906231 Sep 24 01:51:05 AM UTC 24 Sep 24 01:51:16 AM UTC 24 1419150000 ps
T70 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.2190995638 Sep 24 01:51:05 AM UTC 24 Sep 24 01:51:17 AM UTC 24 1547090000 ps
T71 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.3387425393 Sep 24 01:51:09 AM UTC 24 Sep 24 01:51:20 AM UTC 24 1262030000 ps
T72 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.3647505361 Sep 24 01:51:07 AM UTC 24 Sep 24 01:51:20 AM UTC 24 1572330000 ps
T73 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.3949830560 Sep 24 01:51:09 AM UTC 24 Sep 24 01:51:21 AM UTC 24 1482410000 ps
T74 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.3958558285 Sep 24 01:51:09 AM UTC 24 Sep 24 01:51:21 AM UTC 24 1536290000 ps
T75 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.355213624 Sep 24 01:51:09 AM UTC 24 Sep 24 01:51:21 AM UTC 24 1532750000 ps
T76 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.1223451706 Sep 24 01:51:10 AM UTC 24 Sep 24 01:51:22 AM UTC 24 1357570000 ps
T77 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.4054630344 Sep 24 01:51:09 AM UTC 24 Sep 24 01:51:22 AM UTC 24 1579590000 ps
T78 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.724267309 Sep 24 01:51:10 AM UTC 24 Sep 24 01:51:22 AM UTC 24 1395310000 ps
T79 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.3317126569 Sep 24 01:51:10 AM UTC 24 Sep 24 01:51:22 AM UTC 24 1453170000 ps
T80 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.688521768 Sep 24 01:51:10 AM UTC 24 Sep 24 01:51:23 AM UTC 24 1501330000 ps
T14 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.2093327010 Sep 24 03:49:10 AM UTC 24 Sep 24 04:22:51 AM UTC 24 336436410000 ps
T15 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.2357666336 Sep 24 03:49:06 AM UTC 24 Sep 24 04:22:51 AM UTC 24 336703670000 ps
T16 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.3380228238 Sep 24 03:49:12 AM UTC 24 Sep 24 04:22:53 AM UTC 24 337035910000 ps
T17 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.1089893346 Sep 24 03:49:14 AM UTC 24 Sep 24 04:22:56 AM UTC 24 336728590000 ps
T18 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.641471043 Sep 24 03:49:12 AM UTC 24 Sep 24 04:22:56 AM UTC 24 336413210000 ps
T19 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.1076639009 Sep 24 03:49:14 AM UTC 24 Sep 24 04:22:56 AM UTC 24 336963430000 ps
T20 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.3293181164 Sep 24 03:49:20 AM UTC 24 Sep 24 04:23:01 AM UTC 24 337103610000 ps
T21 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.2844364571 Sep 24 03:49:10 AM UTC 24 Sep 24 04:23:02 AM UTC 24 337140110000 ps
T22 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.944459840 Sep 24 03:49:26 AM UTC 24 Sep 24 04:23:04 AM UTC 24 336450390000 ps
T23 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.2809841855 Sep 24 03:49:26 AM UTC 24 Sep 24 04:23:04 AM UTC 24 336448430000 ps
T81 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.3946645077 Sep 24 03:49:19 AM UTC 24 Sep 24 04:23:05 AM UTC 24 336813830000 ps
T82 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.451720716 Sep 24 03:49:14 AM UTC 24 Sep 24 04:23:08 AM UTC 24 336781590000 ps
T83 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.1326606760 Sep 24 03:49:22 AM UTC 24 Sep 24 04:23:09 AM UTC 24 336747750000 ps
T84 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.2400998725 Sep 24 03:49:16 AM UTC 24 Sep 24 04:23:11 AM UTC 24 336726130000 ps
T85 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.3574691526 Sep 24 03:49:22 AM UTC 24 Sep 24 04:23:15 AM UTC 24 336466510000 ps
T86 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.4148401501 Sep 24 03:49:31 AM UTC 24 Sep 24 04:23:16 AM UTC 24 337125390000 ps
T87 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.3399234029 Sep 24 03:49:22 AM UTC 24 Sep 24 04:23:18 AM UTC 24 337015830000 ps
T88 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.1400049530 Sep 24 03:49:30 AM UTC 24 Sep 24 04:23:19 AM UTC 24 336463450000 ps
T89 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.3767092715 Sep 24 03:49:30 AM UTC 24 Sep 24 04:23:19 AM UTC 24 336901730000 ps
T90 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.745632900 Sep 24 03:49:37 AM UTC 24 Sep 24 04:23:20 AM UTC 24 337096390000 ps
T91 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.3901630268 Sep 24 03:49:22 AM UTC 24 Sep 24 04:23:21 AM UTC 24 336937970000 ps
T92 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.576890025 Sep 24 03:49:36 AM UTC 24 Sep 24 04:23:21 AM UTC 24 336773730000 ps
T93 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.4269867403 Sep 24 03:49:37 AM UTC 24 Sep 24 04:23:22 AM UTC 24 336763730000 ps
T94 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.955170481 Sep 24 03:49:42 AM UTC 24 Sep 24 04:23:28 AM UTC 24 336840770000 ps
T95 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.2417097831 Sep 24 03:49:43 AM UTC 24 Sep 24 04:23:37 AM UTC 24 336668470000 ps
T96 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.1733158852 Sep 24 03:49:43 AM UTC 24 Sep 24 04:23:38 AM UTC 24 337080610000 ps
T97 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.2129305545 Sep 24 03:49:54 AM UTC 24 Sep 24 04:23:40 AM UTC 24 336918530000 ps
T98 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.1910830061 Sep 24 03:49:43 AM UTC 24 Sep 24 04:23:42 AM UTC 24 337022530000 ps
T99 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.648609003 Sep 24 03:49:55 AM UTC 24 Sep 24 04:23:44 AM UTC 24 336590970000 ps
T100 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.1073141419 Sep 24 03:49:59 AM UTC 24 Sep 24 04:23:44 AM UTC 24 336862990000 ps
T101 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.2413248193 Sep 24 03:49:54 AM UTC 24 Sep 24 04:23:47 AM UTC 24 337033870000 ps
T102 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.3590308086 Sep 24 03:50:05 AM UTC 24 Sep 24 04:23:49 AM UTC 24 336995050000 ps
T103 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.2622199082 Sep 24 03:50:02 AM UTC 24 Sep 24 04:23:49 AM UTC 24 336990450000 ps
T104 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.1885149610 Sep 24 03:50:06 AM UTC 24 Sep 24 04:23:50 AM UTC 24 336713130000 ps
T105 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.2493741558 Sep 24 03:50:06 AM UTC 24 Sep 24 04:23:52 AM UTC 24 336480770000 ps
T106 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.1464376294 Sep 24 03:50:06 AM UTC 24 Sep 24 04:23:55 AM UTC 24 336536690000 ps
T107 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.3503528674 Sep 24 03:50:16 AM UTC 24 Sep 24 04:23:56 AM UTC 24 336304890000 ps
T108 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.3941614454 Sep 24 03:49:56 AM UTC 24 Sep 24 04:23:57 AM UTC 24 337152470000 ps
T109 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.826019395 Sep 24 03:49:57 AM UTC 24 Sep 24 04:23:58 AM UTC 24 336659230000 ps
T110 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.2234684208 Sep 24 03:50:16 AM UTC 24 Sep 24 04:24:01 AM UTC 24 337019710000 ps
T111 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.2523132098 Sep 24 03:50:21 AM UTC 24 Sep 24 04:24:03 AM UTC 24 336442410000 ps
T112 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.3727897984 Sep 24 03:50:20 AM UTC 24 Sep 24 04:24:05 AM UTC 24 336939490000 ps
T113 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3138661560 Sep 24 03:50:09 AM UTC 24 Sep 24 04:24:07 AM UTC 24 336599150000 ps
T114 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.1881639946 Sep 24 03:50:15 AM UTC 24 Sep 24 04:24:07 AM UTC 24 336751610000 ps
T115 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.289767686 Sep 24 03:50:12 AM UTC 24 Sep 24 04:24:08 AM UTC 24 336348690000 ps
T116 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1349070022 Sep 24 03:50:23 AM UTC 24 Sep 24 04:24:10 AM UTC 24 336393170000 ps
T117 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.1706969079 Sep 24 03:50:21 AM UTC 24 Sep 24 04:24:12 AM UTC 24 336757230000 ps
T118 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.1556861443 Sep 24 03:50:20 AM UTC 24 Sep 24 04:24:16 AM UTC 24 336395230000 ps
T119 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.2639716037 Sep 24 03:50:24 AM UTC 24 Sep 24 04:24:19 AM UTC 24 336975130000 ps
T120 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.2602068446 Sep 24 03:50:23 AM UTC 24 Sep 24 04:24:21 AM UTC 24 336999430000 ps
T4 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3419762817 Sep 24 01:51:12 AM UTC 24 Sep 24 01:51:22 AM UTC 24 1286070000 ps
T5 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.1714892720 Sep 24 01:51:12 AM UTC 24 Sep 24 01:51:22 AM UTC 24 1271970000 ps
T6 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.494863598 Sep 24 01:51:11 AM UTC 24 Sep 24 01:51:22 AM UTC 24 1461670000 ps
T24 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.1557373859 Sep 24 01:51:13 AM UTC 24 Sep 24 01:51:23 AM UTC 24 1160110000 ps
T25 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1117823809 Sep 24 01:51:12 AM UTC 24 Sep 24 01:51:23 AM UTC 24 1362950000 ps
T26 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.3263952628 Sep 24 01:51:12 AM UTC 24 Sep 24 01:51:23 AM UTC 24 1394030000 ps
T27 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.2756236067 Sep 24 01:51:12 AM UTC 24 Sep 24 01:51:23 AM UTC 24 1461090000 ps
T28 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.465530337 Sep 24 01:51:12 AM UTC 24 Sep 24 01:51:24 AM UTC 24 1491130000 ps
T29 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.3044911637 Sep 24 01:51:13 AM UTC 24 Sep 24 01:51:24 AM UTC 24 1316970000 ps
T30 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.2805303371 Sep 24 01:51:12 AM UTC 24 Sep 24 01:51:24 AM UTC 24 1526170000 ps
T121 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.3040539303 Sep 24 01:51:12 AM UTC 24 Sep 24 01:51:24 AM UTC 24 1499330000 ps
T122 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.3860545341 Sep 24 01:51:12 AM UTC 24 Sep 24 01:51:24 AM UTC 24 1546290000 ps
T123 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.84684383 Sep 24 01:51:12 AM UTC 24 Sep 24 01:51:24 AM UTC 24 1532890000 ps
T124 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.1304768569 Sep 24 01:51:12 AM UTC 24 Sep 24 01:51:25 AM UTC 24 1631670000 ps
T125 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.623229270 Sep 24 01:51:13 AM UTC 24 Sep 24 01:51:25 AM UTC 24 1516870000 ps
T126 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.4233348739 Sep 24 01:51:14 AM UTC 24 Sep 24 01:51:25 AM UTC 24 1377270000 ps
T127 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.98960165 Sep 24 01:51:14 AM UTC 24 Sep 24 01:51:25 AM UTC 24 1386010000 ps
T128 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.1306343310 Sep 24 01:51:14 AM UTC 24 Sep 24 01:51:25 AM UTC 24 1380010000 ps
T129 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.41270218 Sep 24 01:51:14 AM UTC 24 Sep 24 01:51:25 AM UTC 24 1421930000 ps
T130 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.2089223513 Sep 24 01:51:14 AM UTC 24 Sep 24 01:51:25 AM UTC 24 1394530000 ps
T131 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.1613220409 Sep 24 01:51:14 AM UTC 24 Sep 24 01:51:26 AM UTC 24 1464950000 ps
T132 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.587982054 Sep 24 01:51:14 AM UTC 24 Sep 24 01:51:26 AM UTC 24 1548770000 ps
T133 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.4106913403 Sep 24 01:51:17 AM UTC 24 Sep 24 01:51:27 AM UTC 24 1376890000 ps
T134 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.3872642348 Sep 24 01:51:17 AM UTC 24 Sep 24 01:51:27 AM UTC 24 1415970000 ps
T135 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.1756031193 Sep 24 01:51:17 AM UTC 24 Sep 24 01:51:27 AM UTC 24 1411250000 ps
T136 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2636041926 Sep 24 01:51:17 AM UTC 24 Sep 24 01:51:28 AM UTC 24 1445010000 ps
T137 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.962516437 Sep 24 01:51:17 AM UTC 24 Sep 24 01:51:28 AM UTC 24 1452830000 ps
T138 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.1561600610 Sep 24 01:51:17 AM UTC 24 Sep 24 01:51:28 AM UTC 24 1548350000 ps
T139 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.1149948364 Sep 24 01:51:17 AM UTC 24 Sep 24 01:51:28 AM UTC 24 1533710000 ps
T140 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.1831132280 Sep 24 01:51:18 AM UTC 24 Sep 24 01:51:28 AM UTC 24 1346090000 ps
T141 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.2799262132 Sep 24 01:51:18 AM UTC 24 Sep 24 01:51:29 AM UTC 24 1427690000 ps
T142 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.1231239061 Sep 24 01:51:18 AM UTC 24 Sep 24 01:51:29 AM UTC 24 1474890000 ps
T143 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.4150176439 Sep 24 01:51:18 AM UTC 24 Sep 24 01:51:29 AM UTC 24 1515970000 ps
T144 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.3939213359 Sep 24 01:51:19 AM UTC 24 Sep 24 01:51:29 AM UTC 24 1302790000 ps
T145 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.362393938 Sep 24 01:51:18 AM UTC 24 Sep 24 01:51:29 AM UTC 24 1535390000 ps
T146 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.3897849190 Sep 24 01:51:18 AM UTC 24 Sep 24 01:51:30 AM UTC 24 1595530000 ps
T147 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.3883435500 Sep 24 01:51:19 AM UTC 24 Sep 24 01:51:30 AM UTC 24 1530250000 ps
T148 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.938963122 Sep 24 01:51:21 AM UTC 24 Sep 24 01:51:31 AM UTC 24 1309630000 ps
T149 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.676680378 Sep 24 01:51:21 AM UTC 24 Sep 24 01:51:31 AM UTC 24 1336510000 ps
T150 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.1554375748 Sep 24 01:51:21 AM UTC 24 Sep 24 01:51:31 AM UTC 24 1381610000 ps
T151 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1607959284 Sep 24 01:51:21 AM UTC 24 Sep 24 01:51:32 AM UTC 24 1434630000 ps
T152 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.112340012 Sep 24 01:51:21 AM UTC 24 Sep 24 01:51:32 AM UTC 24 1458350000 ps
T153 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1223709978 Sep 24 01:51:21 AM UTC 24 Sep 24 01:51:32 AM UTC 24 1532550000 ps
T154 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.1046825673 Sep 24 01:51:21 AM UTC 24 Sep 24 01:51:32 AM UTC 24 1564470000 ps
T155 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.3258054949 Sep 24 01:51:23 AM UTC 24 Sep 24 01:51:33 AM UTC 24 1384410000 ps
T156 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.3170119308 Sep 24 01:51:23 AM UTC 24 Sep 24 01:51:33 AM UTC 24 1351530000 ps
T157 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.1094109494 Sep 24 01:51:22 AM UTC 24 Sep 24 01:51:33 AM UTC 24 1397770000 ps
T158 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.1797096300 Sep 24 01:51:23 AM UTC 24 Sep 24 01:51:33 AM UTC 24 1363630000 ps
T159 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.1299551367 Sep 24 01:51:23 AM UTC 24 Sep 24 01:51:34 AM UTC 24 1546770000 ps
T160 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.99120555 Sep 24 01:51:23 AM UTC 24 Sep 24 01:51:34 AM UTC 24 1592750000 ps
T31 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.88735600 Sep 24 03:50:26 AM UTC 24 Sep 24 04:24:12 AM UTC 24 336849690000 ps
T32 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.3076553336 Sep 24 03:50:36 AM UTC 24 Sep 24 04:24:26 AM UTC 24 336985210000 ps
T33 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.2622024885 Sep 24 03:50:29 AM UTC 24 Sep 24 04:24:30 AM UTC 24 336381850000 ps
T34 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.3026169405 Sep 24 03:50:47 AM UTC 24 Sep 24 04:24:38 AM UTC 24 336634870000 ps
T35 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.930364600 Sep 24 03:50:56 AM UTC 24 Sep 24 04:24:40 AM UTC 24 337075970000 ps
T36 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.567197531 Sep 24 03:50:57 AM UTC 24 Sep 24 04:24:54 AM UTC 24 337121370000 ps
T37 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.32756542 Sep 24 03:51:16 AM UTC 24 Sep 24 04:25:10 AM UTC 24 336507190000 ps
T38 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.1282569447 Sep 24 03:51:19 AM UTC 24 Sep 24 04:25:12 AM UTC 24 336597770000 ps
T39 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1629355774 Sep 24 03:51:28 AM UTC 24 Sep 24 04:25:18 AM UTC 24 336674910000 ps
T40 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.1134072224 Sep 24 03:51:43 AM UTC 24 Sep 24 04:25:26 AM UTC 24 336768130000 ps
T161 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.2802678902 Sep 24 03:51:32 AM UTC 24 Sep 24 04:25:26 AM UTC 24 336321650000 ps
T162 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.3786553605 Sep 24 03:52:10 AM UTC 24 Sep 24 04:25:49 AM UTC 24 336426930000 ps
T163 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.4163931183 Sep 24 03:54:15 AM UTC 24 Sep 24 04:27:45 AM UTC 24 336554710000 ps
T164 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.3351554856 Sep 24 03:55:11 AM UTC 24 Sep 24 04:28:37 AM UTC 24 336838750000 ps
T165 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.1380240190 Sep 24 04:22:51 AM UTC 24 Sep 24 04:57:38 AM UTC 24 336338310000 ps
T166 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.45095470 Sep 24 04:22:52 AM UTC 24 Sep 24 04:57:41 AM UTC 24 336798930000 ps
T167 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.4059888913 Sep 24 04:22:54 AM UTC 24 Sep 24 04:57:42 AM UTC 24 336543970000 ps
T168 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.1497764406 Sep 24 04:22:57 AM UTC 24 Sep 24 04:57:46 AM UTC 24 336600990000 ps
T169 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.1388084356 Sep 24 04:22:57 AM UTC 24 Sep 24 04:57:47 AM UTC 24 336687070000 ps
T170 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.3693577703 Sep 24 04:22:57 AM UTC 24 Sep 24 04:57:50 AM UTC 24 336765330000 ps
T171 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.2789340245 Sep 24 04:23:03 AM UTC 24 Sep 24 04:57:53 AM UTC 24 336568910000 ps
T172 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.3942099433 Sep 24 04:23:05 AM UTC 24 Sep 24 04:57:56 AM UTC 24 336540170000 ps
T173 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.1753834707 Sep 24 04:23:02 AM UTC 24 Sep 24 04:57:56 AM UTC 24 336549610000 ps
T174 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.1084981181 Sep 24 04:23:06 AM UTC 24 Sep 24 04:57:58 AM UTC 24 336389830000 ps
T175 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.1052516191 Sep 24 04:23:05 AM UTC 24 Sep 24 04:58:03 AM UTC 24 336830470000 ps
T176 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.3589639955 Sep 24 04:23:09 AM UTC 24 Sep 24 04:58:07 AM UTC 24 336721590000 ps
T177 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.2268285085 Sep 24 04:23:11 AM UTC 24 Sep 24 04:58:09 AM UTC 24 336696970000 ps
T178 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.3286737053 Sep 24 04:23:10 AM UTC 24 Sep 24 04:58:10 AM UTC 24 336895710000 ps
T179 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.4007914294 Sep 24 04:23:15 AM UTC 24 Sep 24 04:58:12 AM UTC 24 336813930000 ps
T180 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.2440721107 Sep 24 04:23:20 AM UTC 24 Sep 24 04:58:19 AM UTC 24 336335310000 ps
T181 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.1218035967 Sep 24 04:23:20 AM UTC 24 Sep 24 04:58:19 AM UTC 24 336387970000 ps
T182 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.2662576189 Sep 24 04:23:17 AM UTC 24 Sep 24 04:58:20 AM UTC 24 336742370000 ps
T183 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.1902784856 Sep 24 04:23:20 AM UTC 24 Sep 24 04:58:21 AM UTC 24 336878070000 ps
T184 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3653963803 Sep 24 04:23:19 AM UTC 24 Sep 24 04:58:21 AM UTC 24 336611350000 ps
T185 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.3142300678 Sep 24 04:23:23 AM UTC 24 Sep 24 04:58:25 AM UTC 24 336419410000 ps
T186 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.1918667578 Sep 24 04:23:22 AM UTC 24 Sep 24 04:58:25 AM UTC 24 336700730000 ps
T187 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.1119040199 Sep 24 04:23:22 AM UTC 24 Sep 24 04:58:28 AM UTC 24 337047070000 ps
T188 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.2832664013 Sep 24 04:23:29 AM UTC 24 Sep 24 04:58:33 AM UTC 24 336507350000 ps
T189 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.2224046860 Sep 24 04:23:41 AM UTC 24 Sep 24 04:58:48 AM UTC 24 336412530000 ps
T190 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.1644454339 Sep 24 04:23:39 AM UTC 24 Sep 24 04:58:50 AM UTC 24 336545890000 ps
T191 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.3526020520 Sep 24 04:23:38 AM UTC 24 Sep 24 04:58:52 AM UTC 24 336992470000 ps
T192 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.3789861476 Sep 24 04:23:42 AM UTC 24 Sep 24 04:58:52 AM UTC 24 336432370000 ps
T193 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.2278044069 Sep 24 04:23:45 AM UTC 24 Sep 24 04:58:54 AM UTC 24 336439670000 ps
T194 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.3676463892 Sep 24 04:23:45 AM UTC 24 Sep 24 04:58:58 AM UTC 24 336437590000 ps
T195 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.3428092087 Sep 24 04:23:47 AM UTC 24 Sep 24 04:59:01 AM UTC 24 336905150000 ps
T196 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.3277938120 Sep 24 04:23:49 AM UTC 24 Sep 24 04:59:04 AM UTC 24 336508530000 ps
T197 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.3336123267 Sep 24 04:23:51 AM UTC 24 Sep 24 04:59:04 AM UTC 24 336410530000 ps
T198 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.2014933477 Sep 24 04:23:50 AM UTC 24 Sep 24 04:59:06 AM UTC 24 336732970000 ps
T199 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.519736638 Sep 24 04:23:52 AM UTC 24 Sep 24 04:59:11 AM UTC 24 337051510000 ps
T200 /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.2075206159 Sep 24 04:23:55 AM UTC 24 Sep 24 04:59:11 AM UTC 24 336412930000 ps

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.2924386025
Short name T1
Test name
Test status
Simulation time 1281030000 ps
CPU time 1.48 seconds
Started Sep 24 01:50:57 AM UTC 24
Finished Sep 24 01:51:08 AM UTC 24
Peak memory 177792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2924386025 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.2924386025
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/0.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.2357666336
Short name T15
Test name
Test status
Simulation time 336703670000 ps
CPU time 242.89 seconds
Started Sep 24 03:49:06 AM UTC 24
Finished Sep 24 04:22:51 AM UTC 24
Peak memory 174988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2357666336 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.2357666336
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/0.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.88735600
Short name T31
Test name
Test status
Simulation time 336849690000 ps
CPU time 242.12 seconds
Started Sep 24 03:50:26 AM UTC 24
Finished Sep 24 04:24:12 AM UTC 24
Peak memory 176592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=88735600 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_
fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.88735600
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/0.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.494863598
Short name T6
Test name
Test status
Simulation time 1461670000 ps
CPU time 1.95 seconds
Started Sep 24 01:51:11 AM UTC 24
Finished Sep 24 01:51:22 AM UTC 24
Peak memory 177768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=494863598 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f
ib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.494863598
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/0.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.2622024885
Short name T33
Test name
Test status
Simulation time 336381850000 ps
CPU time 240.94 seconds
Started Sep 24 03:50:29 AM UTC 24
Finished Sep 24 04:24:30 AM UTC 24
Peak memory 176528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2622024885 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.2622024885
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/1.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.1134072224
Short name T40
Test name
Test status
Simulation time 336768130000 ps
CPU time 242.99 seconds
Started Sep 24 03:51:43 AM UTC 24
Finished Sep 24 04:25:26 AM UTC 24
Peak memory 174996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1134072224 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.1134072224
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/10.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.3786553605
Short name T162
Test name
Test status
Simulation time 336426930000 ps
CPU time 246.32 seconds
Started Sep 24 03:52:10 AM UTC 24
Finished Sep 24 04:25:49 AM UTC 24
Peak memory 174996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3786553605 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.3786553605
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/11.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.4163931183
Short name T163
Test name
Test status
Simulation time 336554710000 ps
CPU time 240.35 seconds
Started Sep 24 03:54:15 AM UTC 24
Finished Sep 24 04:27:45 AM UTC 24
Peak memory 176536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4163931183 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.4163931183
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/12.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.3351554856
Short name T164
Test name
Test status
Simulation time 336838750000 ps
CPU time 247.96 seconds
Started Sep 24 03:55:11 AM UTC 24
Finished Sep 24 04:28:37 AM UTC 24
Peak memory 174996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3351554856 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.3351554856
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/13.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.1380240190
Short name T165
Test name
Test status
Simulation time 336338310000 ps
CPU time 258.51 seconds
Started Sep 24 04:22:51 AM UTC 24
Finished Sep 24 04:57:38 AM UTC 24
Peak memory 174992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1380240190 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.1380240190
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/14.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.45095470
Short name T166
Test name
Test status
Simulation time 336798930000 ps
CPU time 250.05 seconds
Started Sep 24 04:22:52 AM UTC 24
Finished Sep 24 04:57:41 AM UTC 24
Peak memory 174980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=45095470 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_
fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.45095470
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/15.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.4059888913
Short name T167
Test name
Test status
Simulation time 336543970000 ps
CPU time 251.26 seconds
Started Sep 24 04:22:54 AM UTC 24
Finished Sep 24 04:57:42 AM UTC 24
Peak memory 174992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4059888913 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.4059888913
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/16.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.1497764406
Short name T168
Test name
Test status
Simulation time 336600990000 ps
CPU time 254.3 seconds
Started Sep 24 04:22:57 AM UTC 24
Finished Sep 24 04:57:46 AM UTC 24
Peak memory 174992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1497764406 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.1497764406
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/17.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.3693577703
Short name T170
Test name
Test status
Simulation time 336765330000 ps
CPU time 258.73 seconds
Started Sep 24 04:22:57 AM UTC 24
Finished Sep 24 04:57:50 AM UTC 24
Peak memory 174992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3693577703 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.3693577703
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/18.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.1388084356
Short name T169
Test name
Test status
Simulation time 336687070000 ps
CPU time 258.59 seconds
Started Sep 24 04:22:57 AM UTC 24
Finished Sep 24 04:57:47 AM UTC 24
Peak memory 174992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1388084356 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.1388084356
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/19.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.3076553336
Short name T32
Test name
Test status
Simulation time 336985210000 ps
CPU time 246.33 seconds
Started Sep 24 03:50:36 AM UTC 24
Finished Sep 24 04:24:26 AM UTC 24
Peak memory 174988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3076553336 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.3076553336
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/2.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.1753834707
Short name T173
Test name
Test status
Simulation time 336549610000 ps
CPU time 267.17 seconds
Started Sep 24 04:23:02 AM UTC 24
Finished Sep 24 04:57:56 AM UTC 24
Peak memory 174992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1753834707 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.1753834707
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/20.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.2789340245
Short name T171
Test name
Test status
Simulation time 336568910000 ps
CPU time 261.6 seconds
Started Sep 24 04:23:03 AM UTC 24
Finished Sep 24 04:57:53 AM UTC 24
Peak memory 174992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2789340245 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.2789340245
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/21.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.1052516191
Short name T175
Test name
Test status
Simulation time 336830470000 ps
CPU time 267.88 seconds
Started Sep 24 04:23:05 AM UTC 24
Finished Sep 24 04:58:03 AM UTC 24
Peak memory 174992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052516191 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.1052516191
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/22.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.3942099433
Short name T172
Test name
Test status
Simulation time 336540170000 ps
CPU time 254.02 seconds
Started Sep 24 04:23:05 AM UTC 24
Finished Sep 24 04:57:56 AM UTC 24
Peak memory 174992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3942099433 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.3942099433
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/23.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.1084981181
Short name T174
Test name
Test status
Simulation time 336389830000 ps
CPU time 262.99 seconds
Started Sep 24 04:23:06 AM UTC 24
Finished Sep 24 04:57:58 AM UTC 24
Peak memory 174992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1084981181 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.1084981181
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/24.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.3589639955
Short name T176
Test name
Test status
Simulation time 336721590000 ps
CPU time 260.4 seconds
Started Sep 24 04:23:09 AM UTC 24
Finished Sep 24 04:58:07 AM UTC 24
Peak memory 174992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589639955 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.3589639955
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/25.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.3286737053
Short name T178
Test name
Test status
Simulation time 336895710000 ps
CPU time 264.26 seconds
Started Sep 24 04:23:10 AM UTC 24
Finished Sep 24 04:58:10 AM UTC 24
Peak memory 174992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3286737053 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.3286737053
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/26.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.2268285085
Short name T177
Test name
Test status
Simulation time 336696970000 ps
CPU time 258.9 seconds
Started Sep 24 04:23:11 AM UTC 24
Finished Sep 24 04:58:09 AM UTC 24
Peak memory 174992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2268285085 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.2268285085
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/27.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.4007914294
Short name T179
Test name
Test status
Simulation time 336813930000 ps
CPU time 249.63 seconds
Started Sep 24 04:23:15 AM UTC 24
Finished Sep 24 04:58:12 AM UTC 24
Peak memory 174992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4007914294 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.4007914294
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/28.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.2662576189
Short name T182
Test name
Test status
Simulation time 336742370000 ps
CPU time 269.4 seconds
Started Sep 24 04:23:17 AM UTC 24
Finished Sep 24 04:58:20 AM UTC 24
Peak memory 174992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2662576189 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.2662576189
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/29.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.3026169405
Short name T34
Test name
Test status
Simulation time 336634870000 ps
CPU time 246.78 seconds
Started Sep 24 03:50:47 AM UTC 24
Finished Sep 24 04:24:38 AM UTC 24
Peak memory 174988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3026169405 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.3026169405
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/3.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3653963803
Short name T184
Test name
Test status
Simulation time 336611350000 ps
CPU time 266.2 seconds
Started Sep 24 04:23:19 AM UTC 24
Finished Sep 24 04:58:21 AM UTC 24
Peak memory 174992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3653963803 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.3653963803
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/30.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.1218035967
Short name T181
Test name
Test status
Simulation time 336387970000 ps
CPU time 261.94 seconds
Started Sep 24 04:23:20 AM UTC 24
Finished Sep 24 04:58:19 AM UTC 24
Peak memory 174992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1218035967 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.1218035967
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/31.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.2440721107
Short name T180
Test name
Test status
Simulation time 336335310000 ps
CPU time 259.62 seconds
Started Sep 24 04:23:20 AM UTC 24
Finished Sep 24 04:58:19 AM UTC 24
Peak memory 174992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2440721107 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.2440721107
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/32.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.1902784856
Short name T183
Test name
Test status
Simulation time 336878070000 ps
CPU time 258.28 seconds
Started Sep 24 04:23:20 AM UTC 24
Finished Sep 24 04:58:21 AM UTC 24
Peak memory 174992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1902784856 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.1902784856
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/33.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.1918667578
Short name T186
Test name
Test status
Simulation time 336700730000 ps
CPU time 266.39 seconds
Started Sep 24 04:23:22 AM UTC 24
Finished Sep 24 04:58:25 AM UTC 24
Peak memory 174984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1918667578 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.1918667578
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/34.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.1119040199
Short name T187
Test name
Test status
Simulation time 337047070000 ps
CPU time 262.98 seconds
Started Sep 24 04:23:22 AM UTC 24
Finished Sep 24 04:58:28 AM UTC 24
Peak memory 174992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1119040199 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.1119040199
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/35.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.3142300678
Short name T185
Test name
Test status
Simulation time 336419410000 ps
CPU time 267.98 seconds
Started Sep 24 04:23:23 AM UTC 24
Finished Sep 24 04:58:25 AM UTC 24
Peak memory 174992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3142300678 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.3142300678
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/36.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.2832664013
Short name T188
Test name
Test status
Simulation time 336507350000 ps
CPU time 259.2 seconds
Started Sep 24 04:23:29 AM UTC 24
Finished Sep 24 04:58:33 AM UTC 24
Peak memory 174992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2832664013 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.2832664013
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/37.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.3526020520
Short name T191
Test name
Test status
Simulation time 336992470000 ps
CPU time 267.48 seconds
Started Sep 24 04:23:38 AM UTC 24
Finished Sep 24 04:58:52 AM UTC 24
Peak memory 174992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3526020520 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.3526020520
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/38.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.1644454339
Short name T190
Test name
Test status
Simulation time 336545890000 ps
CPU time 267.09 seconds
Started Sep 24 04:23:39 AM UTC 24
Finished Sep 24 04:58:50 AM UTC 24
Peak memory 174992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1644454339 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.1644454339
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/39.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.930364600
Short name T35
Test name
Test status
Simulation time 337075970000 ps
CPU time 244.73 seconds
Started Sep 24 03:50:56 AM UTC 24
Finished Sep 24 04:24:40 AM UTC 24
Peak memory 176532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=930364600 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.930364600
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/4.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.2224046860
Short name T189
Test name
Test status
Simulation time 336412530000 ps
CPU time 261.12 seconds
Started Sep 24 04:23:41 AM UTC 24
Finished Sep 24 04:58:48 AM UTC 24
Peak memory 174992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2224046860 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.2224046860
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/40.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.3789861476
Short name T192
Test name
Test status
Simulation time 336432370000 ps
CPU time 266.81 seconds
Started Sep 24 04:23:42 AM UTC 24
Finished Sep 24 04:58:52 AM UTC 24
Peak memory 174988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3789861476 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.3789861476
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/41.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.2278044069
Short name T193
Test name
Test status
Simulation time 336439670000 ps
CPU time 256.72 seconds
Started Sep 24 04:23:45 AM UTC 24
Finished Sep 24 04:58:54 AM UTC 24
Peak memory 174992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2278044069 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.2278044069
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/42.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.3676463892
Short name T194
Test name
Test status
Simulation time 336437590000 ps
CPU time 266.03 seconds
Started Sep 24 04:23:45 AM UTC 24
Finished Sep 24 04:58:58 AM UTC 24
Peak memory 174992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3676463892 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.3676463892
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/43.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.3428092087
Short name T195
Test name
Test status
Simulation time 336905150000 ps
CPU time 259.11 seconds
Started Sep 24 04:23:47 AM UTC 24
Finished Sep 24 04:59:01 AM UTC 24
Peak memory 174992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3428092087 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.3428092087
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/44.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.3277938120
Short name T196
Test name
Test status
Simulation time 336508530000 ps
CPU time 265.45 seconds
Started Sep 24 04:23:49 AM UTC 24
Finished Sep 24 04:59:04 AM UTC 24
Peak memory 174992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3277938120 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.3277938120
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/45.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.2014933477
Short name T198
Test name
Test status
Simulation time 336732970000 ps
CPU time 264 seconds
Started Sep 24 04:23:50 AM UTC 24
Finished Sep 24 04:59:06 AM UTC 24
Peak memory 174992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2014933477 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.2014933477
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/46.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.3336123267
Short name T197
Test name
Test status
Simulation time 336410530000 ps
CPU time 262.83 seconds
Started Sep 24 04:23:51 AM UTC 24
Finished Sep 24 04:59:04 AM UTC 24
Peak memory 174992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3336123267 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.3336123267
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/47.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.519736638
Short name T199
Test name
Test status
Simulation time 337051510000 ps
CPU time 257.97 seconds
Started Sep 24 04:23:52 AM UTC 24
Finished Sep 24 04:59:11 AM UTC 24
Peak memory 174992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=519736638 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.519736638
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/48.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.2075206159
Short name T200
Test name
Test status
Simulation time 336412930000 ps
CPU time 262.05 seconds
Started Sep 24 04:23:55 AM UTC 24
Finished Sep 24 04:59:11 AM UTC 24
Peak memory 174992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2075206159 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.2075206159
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/49.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.567197531
Short name T36
Test name
Test status
Simulation time 337121370000 ps
CPU time 246.68 seconds
Started Sep 24 03:50:57 AM UTC 24
Finished Sep 24 04:24:54 AM UTC 24
Peak memory 176532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=567197531 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.567197531
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/5.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.32756542
Short name T37
Test name
Test status
Simulation time 336507190000 ps
CPU time 242.05 seconds
Started Sep 24 03:51:16 AM UTC 24
Finished Sep 24 04:25:10 AM UTC 24
Peak memory 174988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32756542 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_
fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.32756542
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/6.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.1282569447
Short name T38
Test name
Test status
Simulation time 336597770000 ps
CPU time 245.3 seconds
Started Sep 24 03:51:19 AM UTC 24
Finished Sep 24 04:25:12 AM UTC 24
Peak memory 174976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1282569447 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.1282569447
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/7.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1629355774
Short name T39
Test name
Test status
Simulation time 336674910000 ps
CPU time 245.47 seconds
Started Sep 24 03:51:28 AM UTC 24
Finished Sep 24 04:25:18 AM UTC 24
Peak memory 176528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1629355774 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.1629355774
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/8.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.2802678902
Short name T161
Test name
Test status
Simulation time 336321650000 ps
CPU time 241.44 seconds
Started Sep 24 03:51:32 AM UTC 24
Finished Sep 24 04:25:26 AM UTC 24
Peak memory 176528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2802678902 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.2802678902
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/9.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.2093327010
Short name T14
Test name
Test status
Simulation time 336436410000 ps
CPU time 238.36 seconds
Started Sep 24 03:49:10 AM UTC 24
Finished Sep 24 04:22:51 AM UTC 24
Peak memory 176592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2093327010 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.2093327010
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/1.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.3293181164
Short name T20
Test name
Test status
Simulation time 337103610000 ps
CPU time 243.42 seconds
Started Sep 24 03:49:20 AM UTC 24
Finished Sep 24 04:23:01 AM UTC 24
Peak memory 174996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3293181164 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.3293181164
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/10.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.1326606760
Short name T83
Test name
Test status
Simulation time 336747750000 ps
CPU time 240.45 seconds
Started Sep 24 03:49:22 AM UTC 24
Finished Sep 24 04:23:09 AM UTC 24
Peak memory 176536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1326606760 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.1326606760
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/11.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.3574691526
Short name T85
Test name
Test status
Simulation time 336466510000 ps
CPU time 238.25 seconds
Started Sep 24 03:49:22 AM UTC 24
Finished Sep 24 04:23:15 AM UTC 24
Peak memory 174996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3574691526 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.3574691526
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/12.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.3399234029
Short name T87
Test name
Test status
Simulation time 337015830000 ps
CPU time 242.43 seconds
Started Sep 24 03:49:22 AM UTC 24
Finished Sep 24 04:23:18 AM UTC 24
Peak memory 176532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3399234029 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.3399234029
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/13.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.3901630268
Short name T91
Test name
Test status
Simulation time 336937970000 ps
CPU time 242.79 seconds
Started Sep 24 03:49:22 AM UTC 24
Finished Sep 24 04:23:21 AM UTC 24
Peak memory 176536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3901630268 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.3901630268
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/14.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.2809841855
Short name T23
Test name
Test status
Simulation time 336448430000 ps
CPU time 242.85 seconds
Started Sep 24 03:49:26 AM UTC 24
Finished Sep 24 04:23:04 AM UTC 24
Peak memory 174992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2809841855 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.2809841855
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/15.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.944459840
Short name T22
Test name
Test status
Simulation time 336450390000 ps
CPU time 239.78 seconds
Started Sep 24 03:49:26 AM UTC 24
Finished Sep 24 04:23:04 AM UTC 24
Peak memory 176532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=944459840 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.944459840
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/16.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.3767092715
Short name T89
Test name
Test status
Simulation time 336901730000 ps
CPU time 241.51 seconds
Started Sep 24 03:49:30 AM UTC 24
Finished Sep 24 04:23:19 AM UTC 24
Peak memory 176536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3767092715 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.3767092715
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/17.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.1400049530
Short name T88
Test name
Test status
Simulation time 336463450000 ps
CPU time 243.06 seconds
Started Sep 24 03:49:30 AM UTC 24
Finished Sep 24 04:23:19 AM UTC 24
Peak memory 176536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1400049530 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.1400049530
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/18.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.4148401501
Short name T86
Test name
Test status
Simulation time 337125390000 ps
CPU time 241.45 seconds
Started Sep 24 03:49:31 AM UTC 24
Finished Sep 24 04:23:16 AM UTC 24
Peak memory 176536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4148401501 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.4148401501
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/19.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.2844364571
Short name T21
Test name
Test status
Simulation time 337140110000 ps
CPU time 239.96 seconds
Started Sep 24 03:49:10 AM UTC 24
Finished Sep 24 04:23:02 AM UTC 24
Peak memory 176528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2844364571 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.2844364571
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/2.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.576890025
Short name T92
Test name
Test status
Simulation time 336773730000 ps
CPU time 237.96 seconds
Started Sep 24 03:49:36 AM UTC 24
Finished Sep 24 04:23:21 AM UTC 24
Peak memory 174996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=576890025 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.576890025
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/20.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.745632900
Short name T90
Test name
Test status
Simulation time 337096390000 ps
CPU time 242.03 seconds
Started Sep 24 03:49:37 AM UTC 24
Finished Sep 24 04:23:20 AM UTC 24
Peak memory 174904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=745632900 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.745632900
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/21.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.4269867403
Short name T93
Test name
Test status
Simulation time 336763730000 ps
CPU time 237.02 seconds
Started Sep 24 03:49:37 AM UTC 24
Finished Sep 24 04:23:22 AM UTC 24
Peak memory 176476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4269867403 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.4269867403
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/22.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.955170481
Short name T94
Test name
Test status
Simulation time 336840770000 ps
CPU time 243.65 seconds
Started Sep 24 03:49:42 AM UTC 24
Finished Sep 24 04:23:28 AM UTC 24
Peak memory 174996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=955170481 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.955170481
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/23.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.1910830061
Short name T98
Test name
Test status
Simulation time 337022530000 ps
CPU time 242.58 seconds
Started Sep 24 03:49:43 AM UTC 24
Finished Sep 24 04:23:42 AM UTC 24
Peak memory 174996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1910830061 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.1910830061
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/24.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.1733158852
Short name T96
Test name
Test status
Simulation time 337080610000 ps
CPU time 241.17 seconds
Started Sep 24 03:49:43 AM UTC 24
Finished Sep 24 04:23:38 AM UTC 24
Peak memory 174996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1733158852 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.1733158852
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/25.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.2417097831
Short name T95
Test name
Test status
Simulation time 336668470000 ps
CPU time 242.92 seconds
Started Sep 24 03:49:43 AM UTC 24
Finished Sep 24 04:23:37 AM UTC 24
Peak memory 174996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2417097831 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.2417097831
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/26.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.2413248193
Short name T101
Test name
Test status
Simulation time 337033870000 ps
CPU time 239.81 seconds
Started Sep 24 03:49:54 AM UTC 24
Finished Sep 24 04:23:47 AM UTC 24
Peak memory 176536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2413248193 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.2413248193
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/27.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.2129305545
Short name T97
Test name
Test status
Simulation time 336918530000 ps
CPU time 242.57 seconds
Started Sep 24 03:49:54 AM UTC 24
Finished Sep 24 04:23:40 AM UTC 24
Peak memory 176484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2129305545 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.2129305545
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/28.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.648609003
Short name T99
Test name
Test status
Simulation time 336590970000 ps
CPU time 242.3 seconds
Started Sep 24 03:49:55 AM UTC 24
Finished Sep 24 04:23:44 AM UTC 24
Peak memory 176536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=648609003 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.648609003
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/29.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.3380228238
Short name T16
Test name
Test status
Simulation time 337035910000 ps
CPU time 240.65 seconds
Started Sep 24 03:49:12 AM UTC 24
Finished Sep 24 04:22:53 AM UTC 24
Peak memory 176524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3380228238 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.3380228238
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/3.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.3941614454
Short name T108
Test name
Test status
Simulation time 337152470000 ps
CPU time 240.5 seconds
Started Sep 24 03:49:56 AM UTC 24
Finished Sep 24 04:23:57 AM UTC 24
Peak memory 176536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3941614454 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.3941614454
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/30.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.826019395
Short name T109
Test name
Test status
Simulation time 336659230000 ps
CPU time 236.92 seconds
Started Sep 24 03:49:57 AM UTC 24
Finished Sep 24 04:23:58 AM UTC 24
Peak memory 176536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=826019395 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.826019395
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/31.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.1073141419
Short name T100
Test name
Test status
Simulation time 336862990000 ps
CPU time 239.15 seconds
Started Sep 24 03:49:59 AM UTC 24
Finished Sep 24 04:23:44 AM UTC 24
Peak memory 174996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1073141419 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.1073141419
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/32.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.2622199082
Short name T103
Test name
Test status
Simulation time 336990450000 ps
CPU time 242.31 seconds
Started Sep 24 03:50:02 AM UTC 24
Finished Sep 24 04:23:49 AM UTC 24
Peak memory 176536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2622199082 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.2622199082
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/33.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.3590308086
Short name T102
Test name
Test status
Simulation time 336995050000 ps
CPU time 242 seconds
Started Sep 24 03:50:05 AM UTC 24
Finished Sep 24 04:23:49 AM UTC 24
Peak memory 174996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3590308086 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.3590308086
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/34.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.1464376294
Short name T106
Test name
Test status
Simulation time 336536690000 ps
CPU time 240.07 seconds
Started Sep 24 03:50:06 AM UTC 24
Finished Sep 24 04:23:55 AM UTC 24
Peak memory 176536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1464376294 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.1464376294
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/35.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.2493741558
Short name T105
Test name
Test status
Simulation time 336480770000 ps
CPU time 242.1 seconds
Started Sep 24 03:50:06 AM UTC 24
Finished Sep 24 04:23:52 AM UTC 24
Peak memory 176536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2493741558 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.2493741558
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/36.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.1885149610
Short name T104
Test name
Test status
Simulation time 336713130000 ps
CPU time 239.5 seconds
Started Sep 24 03:50:06 AM UTC 24
Finished Sep 24 04:23:50 AM UTC 24
Peak memory 176588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1885149610 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.1885149610
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/37.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3138661560
Short name T113
Test name
Test status
Simulation time 336599150000 ps
CPU time 241.69 seconds
Started Sep 24 03:50:09 AM UTC 24
Finished Sep 24 04:24:07 AM UTC 24
Peak memory 175048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3138661560 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.3138661560
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/38.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.289767686
Short name T115
Test name
Test status
Simulation time 336348690000 ps
CPU time 241.6 seconds
Started Sep 24 03:50:12 AM UTC 24
Finished Sep 24 04:24:08 AM UTC 24
Peak memory 176536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=289767686 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.289767686
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/39.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.641471043
Short name T18
Test name
Test status
Simulation time 336413210000 ps
CPU time 242.26 seconds
Started Sep 24 03:49:12 AM UTC 24
Finished Sep 24 04:22:56 AM UTC 24
Peak memory 176532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=641471043 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.641471043
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/4.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.1881639946
Short name T114
Test name
Test status
Simulation time 336751610000 ps
CPU time 242.78 seconds
Started Sep 24 03:50:15 AM UTC 24
Finished Sep 24 04:24:07 AM UTC 24
Peak memory 174996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1881639946 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.1881639946
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/40.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.2234684208
Short name T110
Test name
Test status
Simulation time 337019710000 ps
CPU time 242.13 seconds
Started Sep 24 03:50:16 AM UTC 24
Finished Sep 24 04:24:01 AM UTC 24
Peak memory 174992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2234684208 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.2234684208
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/41.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.3503528674
Short name T107
Test name
Test status
Simulation time 336304890000 ps
CPU time 241.95 seconds
Started Sep 24 03:50:16 AM UTC 24
Finished Sep 24 04:23:56 AM UTC 24
Peak memory 174996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3503528674 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.3503528674
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/42.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.3727897984
Short name T112
Test name
Test status
Simulation time 336939490000 ps
CPU time 242.79 seconds
Started Sep 24 03:50:20 AM UTC 24
Finished Sep 24 04:24:05 AM UTC 24
Peak memory 174996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3727897984 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.3727897984
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/43.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.1556861443
Short name T118
Test name
Test status
Simulation time 336395230000 ps
CPU time 241.01 seconds
Started Sep 24 03:50:20 AM UTC 24
Finished Sep 24 04:24:16 AM UTC 24
Peak memory 174996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1556861443 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.1556861443
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/44.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.1706969079
Short name T117
Test name
Test status
Simulation time 336757230000 ps
CPU time 242.22 seconds
Started Sep 24 03:50:21 AM UTC 24
Finished Sep 24 04:24:12 AM UTC 24
Peak memory 176532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1706969079 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.1706969079
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/45.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.2523132098
Short name T111
Test name
Test status
Simulation time 336442410000 ps
CPU time 242.02 seconds
Started Sep 24 03:50:21 AM UTC 24
Finished Sep 24 04:24:03 AM UTC 24
Peak memory 174996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2523132098 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.2523132098
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/46.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.2602068446
Short name T120
Test name
Test status
Simulation time 336999430000 ps
CPU time 239.89 seconds
Started Sep 24 03:50:23 AM UTC 24
Finished Sep 24 04:24:21 AM UTC 24
Peak memory 174724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2602068446 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.2602068446
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/47.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1349070022
Short name T116
Test name
Test status
Simulation time 336393170000 ps
CPU time 238.37 seconds
Started Sep 24 03:50:23 AM UTC 24
Finished Sep 24 04:24:10 AM UTC 24
Peak memory 174628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1349070022 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.1349070022
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/48.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.2639716037
Short name T119
Test name
Test status
Simulation time 336975130000 ps
CPU time 239.83 seconds
Started Sep 24 03:50:24 AM UTC 24
Finished Sep 24 04:24:19 AM UTC 24
Peak memory 176536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2639716037 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.2639716037
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/49.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.1089893346
Short name T17
Test name
Test status
Simulation time 336728590000 ps
CPU time 243.73 seconds
Started Sep 24 03:49:14 AM UTC 24
Finished Sep 24 04:22:56 AM UTC 24
Peak memory 174988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1089893346 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.1089893346
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/5.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.1076639009
Short name T19
Test name
Test status
Simulation time 336963430000 ps
CPU time 243.07 seconds
Started Sep 24 03:49:14 AM UTC 24
Finished Sep 24 04:22:56 AM UTC 24
Peak memory 174988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1076639009 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.1076639009
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/6.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.451720716
Short name T82
Test name
Test status
Simulation time 336781590000 ps
CPU time 242.08 seconds
Started Sep 24 03:49:14 AM UTC 24
Finished Sep 24 04:23:08 AM UTC 24
Peak memory 176532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=451720716 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.451720716
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/7.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.2400998725
Short name T84
Test name
Test status
Simulation time 336726130000 ps
CPU time 239.58 seconds
Started Sep 24 03:49:16 AM UTC 24
Finished Sep 24 04:23:11 AM UTC 24
Peak memory 174988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2400998725 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.2400998725
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/8.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.3946645077
Short name T81
Test name
Test status
Simulation time 336813830000 ps
CPU time 243.63 seconds
Started Sep 24 03:49:19 AM UTC 24
Finished Sep 24 04:23:05 AM UTC 24
Peak memory 174988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3946645077 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.3946645077
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/9.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.2756236067
Short name T27
Test name
Test status
Simulation time 1461090000 ps
CPU time 1.8 seconds
Started Sep 24 01:51:12 AM UTC 24
Finished Sep 24 01:51:23 AM UTC 24
Peak memory 177764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2756236067 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.2756236067
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/1.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.3263952628
Short name T26
Test name
Test status
Simulation time 1394030000 ps
CPU time 1.88 seconds
Started Sep 24 01:51:12 AM UTC 24
Finished Sep 24 01:51:23 AM UTC 24
Peak memory 177764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3263952628 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.3263952628
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/10.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.3040539303
Short name T121
Test name
Test status
Simulation time 1499330000 ps
CPU time 1.88 seconds
Started Sep 24 01:51:12 AM UTC 24
Finished Sep 24 01:51:24 AM UTC 24
Peak memory 177764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3040539303 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.3040539303
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/11.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.623229270
Short name T125
Test name
Test status
Simulation time 1516870000 ps
CPU time 1.94 seconds
Started Sep 24 01:51:13 AM UTC 24
Finished Sep 24 01:51:25 AM UTC 24
Peak memory 177760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=623229270 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f
ib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.623229270
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/12.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.1557373859
Short name T24
Test name
Test status
Simulation time 1160110000 ps
CPU time 1.62 seconds
Started Sep 24 01:51:13 AM UTC 24
Finished Sep 24 01:51:23 AM UTC 24
Peak memory 177764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1557373859 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.1557373859
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/13.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.3044911637
Short name T29
Test name
Test status
Simulation time 1316970000 ps
CPU time 1.77 seconds
Started Sep 24 01:51:13 AM UTC 24
Finished Sep 24 01:51:24 AM UTC 24
Peak memory 177764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3044911637 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.3044911637
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/14.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.4233348739
Short name T126
Test name
Test status
Simulation time 1377270000 ps
CPU time 1.86 seconds
Started Sep 24 01:51:14 AM UTC 24
Finished Sep 24 01:51:25 AM UTC 24
Peak memory 177764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4233348739 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.4233348739
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/15.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.2089223513
Short name T130
Test name
Test status
Simulation time 1394530000 ps
CPU time 1.85 seconds
Started Sep 24 01:51:14 AM UTC 24
Finished Sep 24 01:51:25 AM UTC 24
Peak memory 177764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2089223513 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.2089223513
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/16.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.98960165
Short name T127
Test name
Test status
Simulation time 1386010000 ps
CPU time 1.88 seconds
Started Sep 24 01:51:14 AM UTC 24
Finished Sep 24 01:51:25 AM UTC 24
Peak memory 177764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=98960165 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fi
b.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.98960165
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/17.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.41270218
Short name T129
Test name
Test status
Simulation time 1421930000 ps
CPU time 1.8 seconds
Started Sep 24 01:51:14 AM UTC 24
Finished Sep 24 01:51:25 AM UTC 24
Peak memory 177764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41270218 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fi
b.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.41270218
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/18.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.1306343310
Short name T128
Test name
Test status
Simulation time 1380010000 ps
CPU time 1.78 seconds
Started Sep 24 01:51:14 AM UTC 24
Finished Sep 24 01:51:25 AM UTC 24
Peak memory 177764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1306343310 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.1306343310
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/19.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.3860545341
Short name T122
Test name
Test status
Simulation time 1546290000 ps
CPU time 2 seconds
Started Sep 24 01:51:12 AM UTC 24
Finished Sep 24 01:51:24 AM UTC 24
Peak memory 177764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3860545341 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.3860545341
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/2.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.1613220409
Short name T131
Test name
Test status
Simulation time 1464950000 ps
CPU time 1.93 seconds
Started Sep 24 01:51:14 AM UTC 24
Finished Sep 24 01:51:26 AM UTC 24
Peak memory 177764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1613220409 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.1613220409
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/20.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.587982054
Short name T132
Test name
Test status
Simulation time 1548770000 ps
CPU time 1.9 seconds
Started Sep 24 01:51:14 AM UTC 24
Finished Sep 24 01:51:26 AM UTC 24
Peak memory 177760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=587982054 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f
ib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.587982054
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/21.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.3872642348
Short name T134
Test name
Test status
Simulation time 1415970000 ps
CPU time 1.79 seconds
Started Sep 24 01:51:17 AM UTC 24
Finished Sep 24 01:51:27 AM UTC 24
Peak memory 177764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3872642348 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.3872642348
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/22.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.1756031193
Short name T135
Test name
Test status
Simulation time 1411250000 ps
CPU time 1.88 seconds
Started Sep 24 01:51:17 AM UTC 24
Finished Sep 24 01:51:27 AM UTC 24
Peak memory 177764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1756031193 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.1756031193
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/23.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.1561600610
Short name T138
Test name
Test status
Simulation time 1548350000 ps
CPU time 1.98 seconds
Started Sep 24 01:51:17 AM UTC 24
Finished Sep 24 01:51:28 AM UTC 24
Peak memory 177764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1561600610 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.1561600610
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/24.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.4106913403
Short name T133
Test name
Test status
Simulation time 1376890000 ps
CPU time 1.87 seconds
Started Sep 24 01:51:17 AM UTC 24
Finished Sep 24 01:51:27 AM UTC 24
Peak memory 177764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4106913403 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.4106913403
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/25.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2636041926
Short name T136
Test name
Test status
Simulation time 1445010000 ps
CPU time 1.92 seconds
Started Sep 24 01:51:17 AM UTC 24
Finished Sep 24 01:51:28 AM UTC 24
Peak memory 177764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2636041926 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.2636041926
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/26.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.962516437
Short name T137
Test name
Test status
Simulation time 1452830000 ps
CPU time 1.87 seconds
Started Sep 24 01:51:17 AM UTC 24
Finished Sep 24 01:51:28 AM UTC 24
Peak memory 177760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=962516437 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f
ib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.962516437
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/27.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.1149948364
Short name T139
Test name
Test status
Simulation time 1533710000 ps
CPU time 1.78 seconds
Started Sep 24 01:51:17 AM UTC 24
Finished Sep 24 01:51:28 AM UTC 24
Peak memory 177764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1149948364 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.1149948364
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/28.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.4150176439
Short name T143
Test name
Test status
Simulation time 1515970000 ps
CPU time 1.89 seconds
Started Sep 24 01:51:18 AM UTC 24
Finished Sep 24 01:51:29 AM UTC 24
Peak memory 177764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4150176439 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.4150176439
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/29.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.2805303371
Short name T30
Test name
Test status
Simulation time 1526170000 ps
CPU time 1.88 seconds
Started Sep 24 01:51:12 AM UTC 24
Finished Sep 24 01:51:24 AM UTC 24
Peak memory 177764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2805303371 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.2805303371
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/3.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.1231239061
Short name T142
Test name
Test status
Simulation time 1474890000 ps
CPU time 1.89 seconds
Started Sep 24 01:51:18 AM UTC 24
Finished Sep 24 01:51:29 AM UTC 24
Peak memory 177764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1231239061 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.1231239061
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/30.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.2799262132
Short name T141
Test name
Test status
Simulation time 1427690000 ps
CPU time 1.83 seconds
Started Sep 24 01:51:18 AM UTC 24
Finished Sep 24 01:51:29 AM UTC 24
Peak memory 177764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2799262132 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.2799262132
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/31.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.362393938
Short name T145
Test name
Test status
Simulation time 1535390000 ps
CPU time 1.92 seconds
Started Sep 24 01:51:18 AM UTC 24
Finished Sep 24 01:51:29 AM UTC 24
Peak memory 177760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362393938 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f
ib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.362393938
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/32.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.3897849190
Short name T146
Test name
Test status
Simulation time 1595530000 ps
CPU time 2.07 seconds
Started Sep 24 01:51:18 AM UTC 24
Finished Sep 24 01:51:30 AM UTC 24
Peak memory 177764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3897849190 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.3897849190
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/33.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.1831132280
Short name T140
Test name
Test status
Simulation time 1346090000 ps
CPU time 1.82 seconds
Started Sep 24 01:51:18 AM UTC 24
Finished Sep 24 01:51:28 AM UTC 24
Peak memory 177764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1831132280 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.1831132280
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/34.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.3939213359
Short name T144
Test name
Test status
Simulation time 1302790000 ps
CPU time 1.75 seconds
Started Sep 24 01:51:19 AM UTC 24
Finished Sep 24 01:51:29 AM UTC 24
Peak memory 177764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3939213359 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.3939213359
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/35.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.3883435500
Short name T147
Test name
Test status
Simulation time 1530250000 ps
CPU time 1.78 seconds
Started Sep 24 01:51:19 AM UTC 24
Finished Sep 24 01:51:30 AM UTC 24
Peak memory 177764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3883435500 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.3883435500
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/36.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1223709978
Short name T153
Test name
Test status
Simulation time 1532550000 ps
CPU time 2.01 seconds
Started Sep 24 01:51:21 AM UTC 24
Finished Sep 24 01:51:32 AM UTC 24
Peak memory 177764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1223709978 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.1223709978
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/37.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.1046825673
Short name T154
Test name
Test status
Simulation time 1564470000 ps
CPU time 2.02 seconds
Started Sep 24 01:51:21 AM UTC 24
Finished Sep 24 01:51:32 AM UTC 24
Peak memory 177764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1046825673 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.1046825673
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/38.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.676680378
Short name T149
Test name
Test status
Simulation time 1336510000 ps
CPU time 1.72 seconds
Started Sep 24 01:51:21 AM UTC 24
Finished Sep 24 01:51:31 AM UTC 24
Peak memory 177760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=676680378 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f
ib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.676680378
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/39.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3419762817
Short name T4
Test name
Test status
Simulation time 1286070000 ps
CPU time 1.79 seconds
Started Sep 24 01:51:12 AM UTC 24
Finished Sep 24 01:51:22 AM UTC 24
Peak memory 177832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3419762817 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.3419762817
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/4.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.938963122
Short name T148
Test name
Test status
Simulation time 1309630000 ps
CPU time 1.71 seconds
Started Sep 24 01:51:21 AM UTC 24
Finished Sep 24 01:51:31 AM UTC 24
Peak memory 177760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=938963122 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f
ib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.938963122
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/40.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.1554375748
Short name T150
Test name
Test status
Simulation time 1381610000 ps
CPU time 1.9 seconds
Started Sep 24 01:51:21 AM UTC 24
Finished Sep 24 01:51:31 AM UTC 24
Peak memory 177764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1554375748 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.1554375748
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/41.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.112340012
Short name T152
Test name
Test status
Simulation time 1458350000 ps
CPU time 2.01 seconds
Started Sep 24 01:51:21 AM UTC 24
Finished Sep 24 01:51:32 AM UTC 24
Peak memory 177760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=112340012 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f
ib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.112340012
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/42.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1607959284
Short name T151
Test name
Test status
Simulation time 1434630000 ps
CPU time 1.84 seconds
Started Sep 24 01:51:21 AM UTC 24
Finished Sep 24 01:51:32 AM UTC 24
Peak memory 177764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1607959284 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.1607959284
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/43.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.1094109494
Short name T157
Test name
Test status
Simulation time 1397770000 ps
CPU time 1.78 seconds
Started Sep 24 01:51:22 AM UTC 24
Finished Sep 24 01:51:33 AM UTC 24
Peak memory 177764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1094109494 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.1094109494
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/44.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.3258054949
Short name T155
Test name
Test status
Simulation time 1384410000 ps
CPU time 1.94 seconds
Started Sep 24 01:51:23 AM UTC 24
Finished Sep 24 01:51:33 AM UTC 24
Peak memory 177764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3258054949 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.3258054949
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/45.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.1299551367
Short name T159
Test name
Test status
Simulation time 1546770000 ps
CPU time 2.1 seconds
Started Sep 24 01:51:23 AM UTC 24
Finished Sep 24 01:51:34 AM UTC 24
Peak memory 177756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1299551367 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.1299551367
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/46.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.3170119308
Short name T156
Test name
Test status
Simulation time 1351530000 ps
CPU time 1.81 seconds
Started Sep 24 01:51:23 AM UTC 24
Finished Sep 24 01:51:33 AM UTC 24
Peak memory 177764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3170119308 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.3170119308
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/47.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.1797096300
Short name T158
Test name
Test status
Simulation time 1363630000 ps
CPU time 1.82 seconds
Started Sep 24 01:51:23 AM UTC 24
Finished Sep 24 01:51:33 AM UTC 24
Peak memory 177764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1797096300 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.1797096300
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/48.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.99120555
Short name T160
Test name
Test status
Simulation time 1592750000 ps
CPU time 1.95 seconds
Started Sep 24 01:51:23 AM UTC 24
Finished Sep 24 01:51:34 AM UTC 24
Peak memory 177764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=99120555 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fi
b.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.99120555
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/49.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.1714892720
Short name T5
Test name
Test status
Simulation time 1271970000 ps
CPU time 1.82 seconds
Started Sep 24 01:51:12 AM UTC 24
Finished Sep 24 01:51:22 AM UTC 24
Peak memory 177764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1714892720 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.1714892720
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/5.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.1304768569
Short name T124
Test name
Test status
Simulation time 1631670000 ps
CPU time 2.11 seconds
Started Sep 24 01:51:12 AM UTC 24
Finished Sep 24 01:51:25 AM UTC 24
Peak memory 177764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1304768569 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.1304768569
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/6.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.465530337
Short name T28
Test name
Test status
Simulation time 1491130000 ps
CPU time 1.8 seconds
Started Sep 24 01:51:12 AM UTC 24
Finished Sep 24 01:51:24 AM UTC 24
Peak memory 177760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=465530337 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f
ib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.465530337
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/7.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1117823809
Short name T25
Test name
Test status
Simulation time 1362950000 ps
CPU time 1.83 seconds
Started Sep 24 01:51:12 AM UTC 24
Finished Sep 24 01:51:23 AM UTC 24
Peak memory 177764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1117823809 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.1117823809
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/8.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.84684383
Short name T123
Test name
Test status
Simulation time 1532890000 ps
CPU time 1.93 seconds
Started Sep 24 01:51:12 AM UTC 24
Finished Sep 24 01:51:24 AM UTC 24
Peak memory 177756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=84684383 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fi
b.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.84684383
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/9.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.586519918
Short name T7
Test name
Test status
Simulation time 1365730000 ps
CPU time 1.61 seconds
Started Sep 24 01:50:57 AM UTC 24
Finished Sep 24 01:51:09 AM UTC 24
Peak memory 177732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=586519918 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g
al.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.586519918
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/1.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.1046668328
Short name T10
Test name
Test status
Simulation time 1304430000 ps
CPU time 1.75 seconds
Started Sep 24 01:50:59 AM UTC 24
Finished Sep 24 01:51:09 AM UTC 24
Peak memory 177728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1046668328 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.1046668328
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/10.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.684972614
Short name T49
Test name
Test status
Simulation time 1528310000 ps
CPU time 1.75 seconds
Started Sep 24 01:50:59 AM UTC 24
Finished Sep 24 01:51:11 AM UTC 24
Peak memory 177724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=684972614 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g
al.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.684972614
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/11.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.83868866
Short name T47
Test name
Test status
Simulation time 1516850000 ps
CPU time 1.78 seconds
Started Sep 24 01:50:59 AM UTC 24
Finished Sep 24 01:51:11 AM UTC 24
Peak memory 177728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=83868866 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ga
l.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.83868866
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/12.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.2294342776
Short name T12
Test name
Test status
Simulation time 1299550000 ps
CPU time 1.57 seconds
Started Sep 24 01:50:59 AM UTC 24
Finished Sep 24 01:51:10 AM UTC 24
Peak memory 177728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2294342776 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.2294342776
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/13.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.2297788047
Short name T48
Test name
Test status
Simulation time 1528870000 ps
CPU time 1.82 seconds
Started Sep 24 01:50:59 AM UTC 24
Finished Sep 24 01:51:11 AM UTC 24
Peak memory 177728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2297788047 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.2297788047
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/14.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.356466958
Short name T51
Test name
Test status
Simulation time 1533150000 ps
CPU time 1.82 seconds
Started Sep 24 01:50:59 AM UTC 24
Finished Sep 24 01:51:11 AM UTC 24
Peak memory 177724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=356466958 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g
al.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.356466958
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/15.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.2388185874
Short name T44
Test name
Test status
Simulation time 1411850000 ps
CPU time 1.71 seconds
Started Sep 24 01:50:59 AM UTC 24
Finished Sep 24 01:51:10 AM UTC 24
Peak memory 177728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2388185874 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.2388185874
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/16.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.1761639131
Short name T50
Test name
Test status
Simulation time 1509890000 ps
CPU time 1.86 seconds
Started Sep 24 01:50:59 AM UTC 24
Finished Sep 24 01:51:11 AM UTC 24
Peak memory 177728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1761639131 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.1761639131
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/17.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.2113123409
Short name T42
Test name
Test status
Simulation time 1356470000 ps
CPU time 1.66 seconds
Started Sep 24 01:50:59 AM UTC 24
Finished Sep 24 01:51:10 AM UTC 24
Peak memory 177728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2113123409 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.2113123409
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/18.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.3715855531
Short name T46
Test name
Test status
Simulation time 1440270000 ps
CPU time 1.73 seconds
Started Sep 24 01:50:59 AM UTC 24
Finished Sep 24 01:51:11 AM UTC 24
Peak memory 177728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3715855531 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.3715855531
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/19.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.896891360
Short name T8
Test name
Test status
Simulation time 1388870000 ps
CPU time 1.64 seconds
Started Sep 24 01:50:57 AM UTC 24
Finished Sep 24 01:51:09 AM UTC 24
Peak memory 177760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=896891360 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g
al.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.896891360
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/2.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.3999121265
Short name T53
Test name
Test status
Simulation time 1543590000 ps
CPU time 1.87 seconds
Started Sep 24 01:50:59 AM UTC 24
Finished Sep 24 01:51:12 AM UTC 24
Peak memory 177728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3999121265 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.3999121265
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/20.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.76657330
Short name T43
Test name
Test status
Simulation time 1345910000 ps
CPU time 1.75 seconds
Started Sep 24 01:50:59 AM UTC 24
Finished Sep 24 01:51:10 AM UTC 24
Peak memory 177728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=76657330 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ga
l.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.76657330
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/21.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.1133163706
Short name T52
Test name
Test status
Simulation time 1392450000 ps
CPU time 1.74 seconds
Started Sep 24 01:51:00 AM UTC 24
Finished Sep 24 01:51:11 AM UTC 24
Peak memory 177728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1133163706 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.1133163706
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/22.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.1935644124
Short name T56
Test name
Test status
Simulation time 1413890000 ps
CPU time 1.9 seconds
Started Sep 24 01:51:01 AM UTC 24
Finished Sep 24 01:51:13 AM UTC 24
Peak memory 177728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1935644124 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.1935644124
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/23.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.4082879431
Short name T59
Test name
Test status
Simulation time 1500290000 ps
CPU time 1.81 seconds
Started Sep 24 01:51:01 AM UTC 24
Finished Sep 24 01:51:14 AM UTC 24
Peak memory 177728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4082879431 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.4082879431
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/24.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.655726307
Short name T55
Test name
Test status
Simulation time 1400870000 ps
CPU time 1.78 seconds
Started Sep 24 01:51:01 AM UTC 24
Finished Sep 24 01:51:13 AM UTC 24
Peak memory 177720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=655726307 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g
al.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.655726307
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/25.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.1107733217
Short name T64
Test name
Test status
Simulation time 1648250000 ps
CPU time 2.05 seconds
Started Sep 24 01:51:01 AM UTC 24
Finished Sep 24 01:51:15 AM UTC 24
Peak memory 177728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1107733217 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.1107733217
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/26.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.3288304187
Short name T54
Test name
Test status
Simulation time 1323810000 ps
CPU time 1.75 seconds
Started Sep 24 01:51:01 AM UTC 24
Finished Sep 24 01:51:12 AM UTC 24
Peak memory 177728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3288304187 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.3288304187
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/27.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.308342396
Short name T62
Test name
Test status
Simulation time 1568530000 ps
CPU time 1.87 seconds
Started Sep 24 01:51:01 AM UTC 24
Finished Sep 24 01:51:14 AM UTC 24
Peak memory 177724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308342396 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g
al.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.308342396
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/28.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.911028488
Short name T58
Test name
Test status
Simulation time 1454430000 ps
CPU time 1.79 seconds
Started Sep 24 01:51:01 AM UTC 24
Finished Sep 24 01:51:14 AM UTC 24
Peak memory 177704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=911028488 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g
al.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.911028488
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/29.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.11702040
Short name T3
Test name
Test status
Simulation time 1342590000 ps
CPU time 1.61 seconds
Started Sep 24 01:50:57 AM UTC 24
Finished Sep 24 01:51:09 AM UTC 24
Peak memory 177728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11702040 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ga
l.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.11702040
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/3.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.2813780224
Short name T57
Test name
Test status
Simulation time 1302210000 ps
CPU time 1.73 seconds
Started Sep 24 01:51:02 AM UTC 24
Finished Sep 24 01:51:13 AM UTC 24
Peak memory 177672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2813780224 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.2813780224
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/30.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.3109318077
Short name T63
Test name
Test status
Simulation time 1447310000 ps
CPU time 1.74 seconds
Started Sep 24 01:51:03 AM UTC 24
Finished Sep 24 01:51:14 AM UTC 24
Peak memory 177680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3109318077 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.3109318077
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/31.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.2629386948
Short name T65
Test name
Test status
Simulation time 1494590000 ps
CPU time 1.91 seconds
Started Sep 24 01:51:03 AM UTC 24
Finished Sep 24 01:51:15 AM UTC 24
Peak memory 177724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2629386948 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.2629386948
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/32.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.66641724
Short name T61
Test name
Test status
Simulation time 1337690000 ps
CPU time 1.77 seconds
Started Sep 24 01:51:03 AM UTC 24
Finished Sep 24 01:51:14 AM UTC 24
Peak memory 177728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=66641724 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ga
l.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.66641724
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/33.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.3596995728
Short name T60
Test name
Test status
Simulation time 1343170000 ps
CPU time 1.69 seconds
Started Sep 24 01:51:03 AM UTC 24
Finished Sep 24 01:51:14 AM UTC 24
Peak memory 177728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3596995728 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.3596995728
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/34.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.3381547236
Short name T66
Test name
Test status
Simulation time 1547830000 ps
CPU time 1.83 seconds
Started Sep 24 01:51:03 AM UTC 24
Finished Sep 24 01:51:15 AM UTC 24
Peak memory 177728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3381547236 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.3381547236
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/35.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.4101453497
Short name T68
Test name
Test status
Simulation time 1629250000 ps
CPU time 1.96 seconds
Started Sep 24 01:51:03 AM UTC 24
Finished Sep 24 01:51:16 AM UTC 24
Peak memory 177728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4101453497 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.4101453497
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/36.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.80906231
Short name T69
Test name
Test status
Simulation time 1419150000 ps
CPU time 1.83 seconds
Started Sep 24 01:51:05 AM UTC 24
Finished Sep 24 01:51:16 AM UTC 24
Peak memory 177528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=80906231 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ga
l.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.80906231
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/37.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.2190995638
Short name T70
Test name
Test status
Simulation time 1547090000 ps
CPU time 1.9 seconds
Started Sep 24 01:51:05 AM UTC 24
Finished Sep 24 01:51:17 AM UTC 24
Peak memory 177516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2190995638 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.2190995638
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/38.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.585704528
Short name T67
Test name
Test status
Simulation time 1302210000 ps
CPU time 1.65 seconds
Started Sep 24 01:51:05 AM UTC 24
Finished Sep 24 01:51:15 AM UTC 24
Peak memory 177724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=585704528 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g
al.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.585704528
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/39.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.4271414185
Short name T11
Test name
Test status
Simulation time 1485990000 ps
CPU time 1.73 seconds
Started Sep 24 01:50:57 AM UTC 24
Finished Sep 24 01:51:09 AM UTC 24
Peak memory 177728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4271414185 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.4271414185
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/4.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.3647505361
Short name T72
Test name
Test status
Simulation time 1572330000 ps
CPU time 1.96 seconds
Started Sep 24 01:51:07 AM UTC 24
Finished Sep 24 01:51:20 AM UTC 24
Peak memory 177728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3647505361 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.3647505361
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/40.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.3387425393
Short name T71
Test name
Test status
Simulation time 1262030000 ps
CPU time 1.67 seconds
Started Sep 24 01:51:09 AM UTC 24
Finished Sep 24 01:51:20 AM UTC 24
Peak memory 177728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3387425393 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.3387425393
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/41.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.3958558285
Short name T74
Test name
Test status
Simulation time 1536290000 ps
CPU time 1.91 seconds
Started Sep 24 01:51:09 AM UTC 24
Finished Sep 24 01:51:21 AM UTC 24
Peak memory 177728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3958558285 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.3958558285
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/42.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.4054630344
Short name T77
Test name
Test status
Simulation time 1579590000 ps
CPU time 2.03 seconds
Started Sep 24 01:51:09 AM UTC 24
Finished Sep 24 01:51:22 AM UTC 24
Peak memory 177728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4054630344 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.4054630344
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/43.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.355213624
Short name T75
Test name
Test status
Simulation time 1532750000 ps
CPU time 1.89 seconds
Started Sep 24 01:51:09 AM UTC 24
Finished Sep 24 01:51:21 AM UTC 24
Peak memory 177724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=355213624 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g
al.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.355213624
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/44.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.3949830560
Short name T73
Test name
Test status
Simulation time 1482410000 ps
CPU time 1.87 seconds
Started Sep 24 01:51:09 AM UTC 24
Finished Sep 24 01:51:21 AM UTC 24
Peak memory 177728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3949830560 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.3949830560
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/45.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.688521768
Short name T80
Test name
Test status
Simulation time 1501330000 ps
CPU time 1.97 seconds
Started Sep 24 01:51:10 AM UTC 24
Finished Sep 24 01:51:23 AM UTC 24
Peak memory 177572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=688521768 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g
al.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.688521768
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/46.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.3317126569
Short name T79
Test name
Test status
Simulation time 1453170000 ps
CPU time 1.97 seconds
Started Sep 24 01:51:10 AM UTC 24
Finished Sep 24 01:51:22 AM UTC 24
Peak memory 177728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3317126569 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.3317126569
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/47.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.724267309
Short name T78
Test name
Test status
Simulation time 1395310000 ps
CPU time 1.86 seconds
Started Sep 24 01:51:10 AM UTC 24
Finished Sep 24 01:51:22 AM UTC 24
Peak memory 177724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=724267309 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g
al.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.724267309
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/48.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.1223451706
Short name T76
Test name
Test status
Simulation time 1357570000 ps
CPU time 1.85 seconds
Started Sep 24 01:51:10 AM UTC 24
Finished Sep 24 01:51:22 AM UTC 24
Peak memory 177728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1223451706 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.1223451706
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/49.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.3141889702
Short name T9
Test name
Test status
Simulation time 1435470000 ps
CPU time 1.8 seconds
Started Sep 24 01:50:57 AM UTC 24
Finished Sep 24 01:51:09 AM UTC 24
Peak memory 177728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3141889702 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.3141889702
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/5.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.3382581160
Short name T13
Test name
Test status
Simulation time 1545090000 ps
CPU time 1.82 seconds
Started Sep 24 01:50:57 AM UTC 24
Finished Sep 24 01:51:10 AM UTC 24
Peak memory 177728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3382581160 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.3382581160
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/6.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.1213886561
Short name T41
Test name
Test status
Simulation time 1565110000 ps
CPU time 1.77 seconds
Started Sep 24 01:50:57 AM UTC 24
Finished Sep 24 01:51:10 AM UTC 24
Peak memory 177728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1213886561 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.1213886561
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/7.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.392230988
Short name T45
Test name
Test status
Simulation time 1474990000 ps
CPU time 1.69 seconds
Started Sep 24 01:50:59 AM UTC 24
Finished Sep 24 01:51:10 AM UTC 24
Peak memory 177760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=392230988 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g
al.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.392230988
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/8.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.3982083334
Short name T2
Test name
Test status
Simulation time 1147870000 ps
CPU time 1.57 seconds
Started Sep 24 01:50:59 AM UTC 24
Finished Sep 24 01:51:08 AM UTC 24
Peak memory 177640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3982083334 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.3982083334
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_lfsr-sim-vcs/9.prim_lfsr_gal_smoke/latest
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