| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 98.31 | 100.00 | 96.55 | 100.00 | 100.00 | 95.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 87.31 | 87.31 | 100.00 | 100.00 | 96.55 | 96.55 | 100.00 | 100.00 | 100.00 | 100.00 | 40.00 | 40.00 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.3099281572 | ||
| 95.31 | 8.00 | 100.00 | 0.00 | 96.55 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 80.00 | 40.00 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.2849184720 | ||
| 96.81 | 1.50 | 100.00 | 0.00 | 96.55 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 87.50 | 7.50 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.1177966755 | ||
| 98.31 | 1.50 | 100.00 | 0.00 | 96.55 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 95.00 | 7.50 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.2620211950 | ||
| Name |
|---|
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.1697674292 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.1121204319 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.2496622872 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.2172153153 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.1116846666 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.2740854204 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.3029448887 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.3178704052 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.2559167854 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.1209049240 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.3602853628 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.3525993127 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.2551339918 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.3385738043 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.555492761 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.4026162063 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.3515507796 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.553278081 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1358918015 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.3942073010 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.2181134022 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.1329220213 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.1258329170 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.265313665 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.2295331053 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.4114069980 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.556688552 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.1471860102 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.2951054293 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.1277361717 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.84079414 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.3319796393 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.3075424530 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.766546021 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.3921541078 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.3021723962 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.64237164 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.4018525795 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.3581966160 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.175652958 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.2918295240 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.2045294010 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.2986044786 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.846015080 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.341107566 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.1229231737 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.3908143024 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.350910364 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.655759485 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.157711591 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.2606826241 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.474040679 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.4061645659 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.3767477325 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.3288286290 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.36773150 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.1649968091 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.932723399 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.844411968 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.3113410987 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.2117039023 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.40609166 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3825847335 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.2594561352 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.2428613359 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.1521693364 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.3602966146 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.3274505794 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.2463379272 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.3995179455 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.4265397741 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.2505959978 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.972561901 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.3095491522 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.1173800149 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.2884102185 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.730335475 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.410875144 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.2023955360 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.1521435453 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3979338959 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.3477293876 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.2708427471 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.3003235001 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.3978592232 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.3056960553 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.257208374 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.640849621 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.3858502203 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.2206183745 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.331612151 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1044145186 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.1474439662 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.718563580 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.205685043 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.748621634 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.2924180945 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.1547282051 |
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| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.2538237496 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.4175493845 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.2482490372 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.3247025514 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.319804764 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.396095797 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.3575470599 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.502461732 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.3539635607 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.3676318845 |
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| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.3510935810 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.721112406 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.4253325184 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.411090681 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.3380621 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.3529895568 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2750751290 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.2323414206 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.2288847206 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.4137032145 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.1980088735 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.153593251 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.2768253842 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.1239133769 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.4093103796 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.3742841362 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.1742385030 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.1464420838 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1148680543 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.3059103011 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.2018703370 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.938490400 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.1099047457 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.808421945 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.37827886 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1930966987 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.3876394147 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.2171469971 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.1034480759 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.1377974294 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.2620085473 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.3557850927 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.3494653248 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.563781107 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.1441607481 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1541306534 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.3953057478 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.736962181 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.692754187 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.3378769599 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.271511286 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.306992642 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.2169697865 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.574305682 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.3626727716 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.842755507 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.941205425 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.2064166305 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.3021913172 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.1979927647 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.3128157362 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.2072745777 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.4289072092 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.4151691805 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.174208466 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.1442832243 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.5385834 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.327554245 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.2807661634 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.2294611031 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.1732290715 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.2645568295 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.3080859432 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.587635135 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.627306447 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.70014465 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.732454404 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.1629168020 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.540642193 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.1915342872 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.581760665 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.882537062 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.4011562650 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.3907367257 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.3274497241 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.1489893302 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.2583292668 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.1401877821 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.926294278 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.2268478600 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.4233975369 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.363503029 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.673761770 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.1379526591 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.1249213263 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.3829184864 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.736962181 | Oct 03 06:28:01 AM UTC 24 | Oct 03 06:28:16 AM UTC 24 | 1238950000 ps | ||
| T2 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.3099281572 | Oct 03 06:28:00 AM UTC 24 | Oct 03 06:28:16 AM UTC 24 | 1336090000 ps | ||
| T3 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.673761770 | Oct 03 06:28:03 AM UTC 24 | Oct 03 06:28:17 AM UTC 24 | 1272330000 ps | ||
| T7 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.3021913172 | Oct 03 06:28:02 AM UTC 24 | Oct 03 06:28:18 AM UTC 24 | 1522990000 ps | ||
| T8 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.2294611031 | Oct 03 06:28:02 AM UTC 24 | Oct 03 06:28:19 AM UTC 24 | 1540850000 ps | ||
| T9 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.363503029 | Oct 03 06:28:03 AM UTC 24 | Oct 03 06:28:19 AM UTC 24 | 1484990000 ps | ||
| T10 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.581760665 | Oct 03 06:28:03 AM UTC 24 | Oct 03 06:28:19 AM UTC 24 | 1497990000 ps | ||
| T11 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.3829184864 | Oct 03 06:28:04 AM UTC 24 | Oct 03 06:28:19 AM UTC 24 | 1345910000 ps | ||
| T12 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.3378769599 | Oct 03 06:28:05 AM UTC 24 | Oct 03 06:28:20 AM UTC 24 | 1307030000 ps | ||
| T13 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.1249213263 | Oct 03 06:28:04 AM UTC 24 | Oct 03 06:28:20 AM UTC 24 | 1412930000 ps | ||
| T41 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.1379526591 | Oct 03 06:28:04 AM UTC 24 | Oct 03 06:28:21 AM UTC 24 | 1546810000 ps | ||
| T42 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.271511286 | Oct 03 06:28:05 AM UTC 24 | Oct 03 06:28:21 AM UTC 24 | 1438330000 ps | ||
| T43 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.692754187 | Oct 03 06:28:05 AM UTC 24 | Oct 03 06:28:22 AM UTC 24 | 1548910000 ps | ||
| T44 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.306992642 | Oct 03 06:28:05 AM UTC 24 | Oct 03 06:28:22 AM UTC 24 | 1539950000 ps | ||
| T45 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.2169697865 | Oct 03 06:28:16 AM UTC 24 | Oct 03 06:28:32 AM UTC 24 | 1416210000 ps | ||
| T46 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.574305682 | Oct 03 06:28:16 AM UTC 24 | Oct 03 06:28:33 AM UTC 24 | 1511410000 ps | ||
| T47 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.2072745777 | Oct 03 06:28:21 AM UTC 24 | Oct 03 06:28:34 AM UTC 24 | 1180770000 ps | ||
| T48 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.3626727716 | Oct 03 06:28:19 AM UTC 24 | Oct 03 06:28:36 AM UTC 24 | 1620270000 ps | ||
| T49 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.2064166305 | Oct 03 06:28:20 AM UTC 24 | Oct 03 06:28:36 AM UTC 24 | 1517010000 ps | ||
| T50 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.842755507 | Oct 03 06:28:20 AM UTC 24 | Oct 03 06:28:37 AM UTC 24 | 1575230000 ps | ||
| T51 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.941205425 | Oct 03 06:28:20 AM UTC 24 | Oct 03 06:28:37 AM UTC 24 | 1576870000 ps | ||
| T52 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.4289072092 | Oct 03 06:28:21 AM UTC 24 | Oct 03 06:28:37 AM UTC 24 | 1438770000 ps | ||
| T53 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.174208466 | Oct 03 06:28:22 AM UTC 24 | Oct 03 06:28:37 AM UTC 24 | 1336530000 ps | ||
| T54 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.1979927647 | Oct 03 06:28:21 AM UTC 24 | Oct 03 06:28:38 AM UTC 24 | 1548610000 ps | ||
| T55 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.1442832243 | Oct 03 06:28:23 AM UTC 24 | Oct 03 06:28:38 AM UTC 24 | 1306870000 ps | ||
| T56 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.4151691805 | Oct 03 06:28:22 AM UTC 24 | Oct 03 06:28:38 AM UTC 24 | 1420950000 ps | ||
| T57 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.3128157362 | Oct 03 06:28:21 AM UTC 24 | Oct 03 06:28:38 AM UTC 24 | 1580810000 ps | ||
| T58 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.5385834 | Oct 03 06:28:23 AM UTC 24 | Oct 03 06:28:40 AM UTC 24 | 1554690000 ps | ||
| T59 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.327554245 | Oct 03 06:28:27 AM UTC 24 | Oct 03 06:28:42 AM UTC 24 | 1445510000 ps | ||
| T60 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.2807661634 | Oct 03 06:28:29 AM UTC 24 | Oct 03 06:28:43 AM UTC 24 | 1334770000 ps | ||
| T61 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.1732290715 | Oct 03 06:28:32 AM UTC 24 | Oct 03 06:28:48 AM UTC 24 | 1439950000 ps | ||
| T62 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.2645568295 | Oct 03 06:28:33 AM UTC 24 | Oct 03 06:28:48 AM UTC 24 | 1320030000 ps | ||
| T63 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.3080859432 | Oct 03 06:28:36 AM UTC 24 | Oct 03 06:28:51 AM UTC 24 | 1435150000 ps | ||
| T64 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.587635135 | Oct 03 06:28:37 AM UTC 24 | Oct 03 06:28:53 AM UTC 24 | 1511610000 ps | ||
| T65 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.1915342872 | Oct 03 06:28:39 AM UTC 24 | Oct 03 06:28:53 AM UTC 24 | 1297370000 ps | ||
| T66 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.70014465 | Oct 03 06:28:38 AM UTC 24 | Oct 03 06:28:54 AM UTC 24 | 1354510000 ps | ||
| T67 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.882537062 | Oct 03 06:28:39 AM UTC 24 | Oct 03 06:28:54 AM UTC 24 | 1334950000 ps | ||
| T68 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.732454404 | Oct 03 06:28:38 AM UTC 24 | Oct 03 06:28:54 AM UTC 24 | 1390190000 ps | ||
| T69 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.1629168020 | Oct 03 06:28:38 AM UTC 24 | Oct 03 06:28:54 AM UTC 24 | 1399750000 ps | ||
| T70 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.627306447 | Oct 03 06:28:37 AM UTC 24 | Oct 03 06:28:54 AM UTC 24 | 1618970000 ps | ||
| T71 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.1489893302 | Oct 03 06:28:41 AM UTC 24 | Oct 03 06:28:54 AM UTC 24 | 1181250000 ps | ||
| T72 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.3907367257 | Oct 03 06:28:39 AM UTC 24 | Oct 03 06:28:55 AM UTC 24 | 1415270000 ps | ||
| T73 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.540642193 | Oct 03 06:28:38 AM UTC 24 | Oct 03 06:28:55 AM UTC 24 | 1483070000 ps | ||
| T74 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.4011562650 | Oct 03 06:28:39 AM UTC 24 | Oct 03 06:28:55 AM UTC 24 | 1491850000 ps | ||
| T75 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.3274497241 | Oct 03 06:28:39 AM UTC 24 | Oct 03 06:28:56 AM UTC 24 | 1537690000 ps | ||
| T76 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.2583292668 | Oct 03 06:28:43 AM UTC 24 | Oct 03 06:28:58 AM UTC 24 | 1430470000 ps | ||
| T77 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.1401877821 | Oct 03 06:28:44 AM UTC 24 | Oct 03 06:29:00 AM UTC 24 | 1520770000 ps | ||
| T78 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.2268478600 | Oct 03 06:28:48 AM UTC 24 | Oct 03 06:29:02 AM UTC 24 | 1354050000 ps | ||
| T79 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.926294278 | Oct 03 06:28:48 AM UTC 24 | Oct 03 06:29:03 AM UTC 24 | 1467030000 ps | ||
| T80 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.4233975369 | Oct 03 06:28:52 AM UTC 24 | Oct 03 06:29:07 AM UTC 24 | 1588390000 ps | ||
| T14 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.157711591 | Oct 03 07:01:26 AM UTC 24 | Oct 03 07:38:40 AM UTC 24 | 336409290000 ps | ||
| T15 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.2505959978 | Oct 03 07:01:26 AM UTC 24 | Oct 03 07:38:43 AM UTC 24 | 336778370000 ps | ||
| T16 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.718563580 | Oct 03 07:01:28 AM UTC 24 | Oct 03 07:38:45 AM UTC 24 | 336686870000 ps | ||
| T17 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.2708427471 | Oct 03 07:01:28 AM UTC 24 | Oct 03 07:38:45 AM UTC 24 | 336826930000 ps | ||
| T18 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.205685043 | Oct 03 07:01:28 AM UTC 24 | Oct 03 07:38:46 AM UTC 24 | 337054790000 ps | ||
| T19 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.2849184720 | Oct 03 07:01:23 AM UTC 24 | Oct 03 07:38:49 AM UTC 24 | 336889230000 ps | ||
| T20 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.2117039023 | Oct 03 07:01:26 AM UTC 24 | Oct 03 07:38:50 AM UTC 24 | 336543890000 ps | ||
| T21 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.2924180945 | Oct 03 07:01:32 AM UTC 24 | Oct 03 07:38:51 AM UTC 24 | 337026630000 ps | ||
| T22 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.4061645659 | Oct 03 07:01:36 AM UTC 24 | Oct 03 07:38:51 AM UTC 24 | 336404810000 ps | ||
| T23 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.748621634 | Oct 03 07:01:30 AM UTC 24 | Oct 03 07:38:53 AM UTC 24 | 337045730000 ps | ||
| T81 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.474040679 | Oct 03 07:01:36 AM UTC 24 | Oct 03 07:38:53 AM UTC 24 | 336398430000 ps | ||
| T82 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.2606826241 | Oct 03 07:01:34 AM UTC 24 | Oct 03 07:38:56 AM UTC 24 | 336465010000 ps | ||
| T83 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.3288286290 | Oct 03 07:01:42 AM UTC 24 | Oct 03 07:38:58 AM UTC 24 | 336723930000 ps | ||
| T84 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.1547282051 | Oct 03 07:01:32 AM UTC 24 | Oct 03 07:39:00 AM UTC 24 | 336973270000 ps | ||
| T85 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.36773150 | Oct 03 07:01:44 AM UTC 24 | Oct 03 07:39:01 AM UTC 24 | 336790030000 ps | ||
| T86 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.3767477325 | Oct 03 07:01:40 AM UTC 24 | Oct 03 07:39:04 AM UTC 24 | 336650910000 ps | ||
| T87 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3825847335 | Oct 03 07:01:51 AM UTC 24 | Oct 03 07:39:06 AM UTC 24 | 336328810000 ps | ||
| T88 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.3113410987 | Oct 03 07:01:46 AM UTC 24 | Oct 03 07:39:06 AM UTC 24 | 337151890000 ps | ||
| T89 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.932723399 | Oct 03 07:01:45 AM UTC 24 | Oct 03 07:39:09 AM UTC 24 | 336575650000 ps | ||
| T90 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.2594561352 | Oct 03 07:01:52 AM UTC 24 | Oct 03 07:39:09 AM UTC 24 | 336353110000 ps | ||
| T91 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.1649968091 | Oct 03 07:01:44 AM UTC 24 | Oct 03 07:39:11 AM UTC 24 | 336564070000 ps | ||
| T92 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.844411968 | Oct 03 07:01:46 AM UTC 24 | Oct 03 07:39:14 AM UTC 24 | 336725010000 ps | ||
| T93 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.40609166 | Oct 03 07:01:50 AM UTC 24 | Oct 03 07:39:18 AM UTC 24 | 336567250000 ps | ||
| T94 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.3602966146 | Oct 03 07:01:59 AM UTC 24 | Oct 03 07:39:21 AM UTC 24 | 336998850000 ps | ||
| T95 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.3274505794 | Oct 03 07:02:01 AM UTC 24 | Oct 03 07:39:22 AM UTC 24 | 336513770000 ps | ||
| T96 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.2428613359 | Oct 03 07:01:53 AM UTC 24 | Oct 03 07:39:25 AM UTC 24 | 337035690000 ps | ||
| T97 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.1521693364 | Oct 03 07:01:58 AM UTC 24 | Oct 03 07:39:26 AM UTC 24 | 337087590000 ps | ||
| T98 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.2463379272 | Oct 03 07:02:13 AM UTC 24 | Oct 03 07:39:32 AM UTC 24 | 336341590000 ps | ||
| T99 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.3995179455 | Oct 03 07:02:16 AM UTC 24 | Oct 03 07:39:38 AM UTC 24 | 336385310000 ps | ||
| T100 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.4265397741 | Oct 03 07:02:18 AM UTC 24 | Oct 03 07:39:46 AM UTC 24 | 336496230000 ps | ||
| T101 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.3095491522 | Oct 03 07:02:21 AM UTC 24 | Oct 03 07:39:47 AM UTC 24 | 336676390000 ps | ||
| T102 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.1173800149 | Oct 03 07:02:23 AM UTC 24 | Oct 03 07:39:53 AM UTC 24 | 336971030000 ps | ||
| T103 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.2884102185 | Oct 03 07:02:26 AM UTC 24 | Oct 03 07:39:57 AM UTC 24 | 337049310000 ps | ||
| T104 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.972561901 | Oct 03 07:02:21 AM UTC 24 | Oct 03 07:39:59 AM UTC 24 | 336865950000 ps | ||
| T105 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.730335475 | Oct 03 07:02:49 AM UTC 24 | Oct 03 07:40:23 AM UTC 24 | 336409450000 ps | ||
| T106 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.2023955360 | Oct 03 07:02:59 AM UTC 24 | Oct 03 07:40:40 AM UTC 24 | 336668910000 ps | ||
| T107 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.410875144 | Oct 03 07:02:55 AM UTC 24 | Oct 03 07:40:42 AM UTC 24 | 336637890000 ps | ||
| T108 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.1521435453 | Oct 03 07:03:01 AM UTC 24 | Oct 03 07:40:50 AM UTC 24 | 336547170000 ps | ||
| T109 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.3477293876 | Oct 03 07:03:10 AM UTC 24 | Oct 03 07:40:54 AM UTC 24 | 336888590000 ps | ||
| T110 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3979338959 | Oct 03 07:03:08 AM UTC 24 | Oct 03 07:40:57 AM UTC 24 | 336817470000 ps | ||
| T111 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.3003235001 | Oct 03 07:03:17 AM UTC 24 | Oct 03 07:41:16 AM UTC 24 | 337092990000 ps | ||
| T112 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.3978592232 | Oct 03 07:03:27 AM UTC 24 | Oct 03 07:41:16 AM UTC 24 | 336653390000 ps | ||
| T113 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.3056960553 | Oct 03 07:03:27 AM UTC 24 | Oct 03 07:41:18 AM UTC 24 | 336969750000 ps | ||
| T114 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.257208374 | Oct 03 07:03:32 AM UTC 24 | Oct 03 07:41:23 AM UTC 24 | 336761150000 ps | ||
| T115 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.640849621 | Oct 03 07:03:40 AM UTC 24 | Oct 03 07:41:30 AM UTC 24 | 336513310000 ps | ||
| T116 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.3858502203 | Oct 03 07:03:42 AM UTC 24 | Oct 03 07:41:40 AM UTC 24 | 336554950000 ps | ||
| T117 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.331612151 | Oct 03 07:03:46 AM UTC 24 | Oct 03 07:41:46 AM UTC 24 | 336934750000 ps | ||
| T118 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.2206183745 | Oct 03 07:03:46 AM UTC 24 | Oct 03 07:41:54 AM UTC 24 | 337000290000 ps | ||
| T119 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1044145186 | Oct 03 07:03:48 AM UTC 24 | Oct 03 07:41:54 AM UTC 24 | 336916970000 ps | ||
| T120 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.1474439662 | Oct 03 07:03:53 AM UTC 24 | Oct 03 07:42:00 AM UTC 24 | 336875190000 ps | ||
| T4 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.2620211950 | Oct 03 07:03:55 AM UTC 24 | Oct 03 07:04:05 AM UTC 24 | 1509890000 ps | ||
| T5 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.1836345215 | Oct 03 07:04:01 AM UTC 24 | Oct 03 07:04:10 AM UTC 24 | 1241010000 ps | ||
| T6 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.1980088735 | Oct 03 07:04:01 AM UTC 24 | Oct 03 07:04:10 AM UTC 24 | 1289230000 ps | ||
| T24 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.2528356852 | Oct 03 07:04:01 AM UTC 24 | Oct 03 07:04:12 AM UTC 24 | 1486990000 ps | ||
| T25 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.938490400 | Oct 03 07:04:03 AM UTC 24 | Oct 03 07:04:14 AM UTC 24 | 1563110000 ps | ||
| T26 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.3494653248 | Oct 03 07:04:07 AM UTC 24 | Oct 03 07:04:18 AM UTC 24 | 1522370000 ps | ||
| T27 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.563781107 | Oct 03 07:04:11 AM UTC 24 | Oct 03 07:04:22 AM UTC 24 | 1470070000 ps | ||
| T28 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.1441607481 | Oct 03 07:04:12 AM UTC 24 | Oct 03 07:04:23 AM UTC 24 | 1653470000 ps | ||
| T29 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1541306534 | Oct 03 07:04:14 AM UTC 24 | Oct 03 07:04:23 AM UTC 24 | 1401830000 ps | ||
| T30 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.3953057478 | Oct 03 07:04:16 AM UTC 24 | Oct 03 07:04:26 AM UTC 24 | 1482710000 ps | ||
| T121 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.2538237496 | Oct 03 07:04:20 AM UTC 24 | Oct 03 07:04:30 AM UTC 24 | 1465530000 ps | ||
| T122 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.4175493845 | Oct 03 07:04:22 AM UTC 24 | Oct 03 07:04:33 AM UTC 24 | 1481870000 ps | ||
| T123 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.396095797 | Oct 03 07:04:24 AM UTC 24 | Oct 03 07:04:33 AM UTC 24 | 1113070000 ps | ||
| T124 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.502461732 | Oct 03 07:04:24 AM UTC 24 | Oct 03 07:04:33 AM UTC 24 | 1161090000 ps | ||
| T125 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.319804764 | Oct 03 07:04:24 AM UTC 24 | Oct 03 07:04:34 AM UTC 24 | 1385490000 ps | ||
| T126 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.3575470599 | Oct 03 07:04:24 AM UTC 24 | Oct 03 07:04:34 AM UTC 24 | 1371370000 ps | ||
| T127 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.2482490372 | Oct 03 07:04:24 AM UTC 24 | Oct 03 07:04:35 AM UTC 24 | 1486410000 ps | ||
| T128 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.3247025514 | Oct 03 07:04:24 AM UTC 24 | Oct 03 07:04:35 AM UTC 24 | 1499690000 ps | ||
| T129 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.3539635607 | Oct 03 07:04:28 AM UTC 24 | Oct 03 07:04:39 AM UTC 24 | 1524210000 ps | ||
| T130 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.3676318845 | Oct 03 07:04:30 AM UTC 24 | Oct 03 07:04:40 AM UTC 24 | 1500030000 ps | ||
| T131 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.721112406 | Oct 03 07:04:32 AM UTC 24 | Oct 03 07:04:42 AM UTC 24 | 1436070000 ps | ||
| T132 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.3510935810 | Oct 03 07:04:32 AM UTC 24 | Oct 03 07:04:42 AM UTC 24 | 1399890000 ps | ||
| T133 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.4253325184 | Oct 03 07:04:34 AM UTC 24 | Oct 03 07:04:44 AM UTC 24 | 1392390000 ps | ||
| T134 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.411090681 | Oct 03 07:04:34 AM UTC 24 | Oct 03 07:04:44 AM UTC 24 | 1419610000 ps | ||
| T135 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.3380621 | Oct 03 07:04:34 AM UTC 24 | Oct 03 07:04:44 AM UTC 24 | 1486390000 ps | ||
| T136 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.3529895568 | Oct 03 07:04:36 AM UTC 24 | Oct 03 07:04:45 AM UTC 24 | 1250790000 ps | ||
| T137 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.2288847206 | Oct 03 07:04:36 AM UTC 24 | Oct 03 07:04:46 AM UTC 24 | 1391390000 ps | ||
| T138 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2750751290 | Oct 03 07:04:36 AM UTC 24 | Oct 03 07:04:47 AM UTC 24 | 1484630000 ps | ||
| T139 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.2323414206 | Oct 03 07:04:36 AM UTC 24 | Oct 03 07:04:47 AM UTC 24 | 1531870000 ps | ||
| T140 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.4137032145 | Oct 03 07:04:36 AM UTC 24 | Oct 03 07:04:47 AM UTC 24 | 1502190000 ps | ||
| T141 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.153593251 | Oct 03 07:04:39 AM UTC 24 | Oct 03 07:04:49 AM UTC 24 | 1302530000 ps | ||
| T142 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.2768253842 | Oct 03 07:04:39 AM UTC 24 | Oct 03 07:04:49 AM UTC 24 | 1315250000 ps | ||
| T143 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.1239133769 | Oct 03 07:04:41 AM UTC 24 | Oct 03 07:04:52 AM UTC 24 | 1452230000 ps | ||
| T144 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.3742841362 | Oct 03 07:04:43 AM UTC 24 | Oct 03 07:04:52 AM UTC 24 | 1327250000 ps | ||
| T145 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.4093103796 | Oct 03 07:04:43 AM UTC 24 | Oct 03 07:04:52 AM UTC 24 | 1382770000 ps | ||
| T146 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.1742385030 | Oct 03 07:04:45 AM UTC 24 | Oct 03 07:04:56 AM UTC 24 | 1537690000 ps | ||
| T147 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.1464420838 | Oct 03 07:04:45 AM UTC 24 | Oct 03 07:04:56 AM UTC 24 | 1570550000 ps | ||
| T148 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1148680543 | Oct 03 07:04:46 AM UTC 24 | Oct 03 07:04:56 AM UTC 24 | 1383610000 ps | ||
| T149 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.3059103011 | Oct 03 07:04:46 AM UTC 24 | Oct 03 07:04:56 AM UTC 24 | 1470750000 ps | ||
| T150 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1930966987 | Oct 03 07:04:49 AM UTC 24 | Oct 03 07:04:57 AM UTC 24 | 1078470000 ps | ||
| T151 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.2018703370 | Oct 03 07:04:47 AM UTC 24 | Oct 03 07:04:57 AM UTC 24 | 1463910000 ps | ||
| T152 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.808421945 | Oct 03 07:04:48 AM UTC 24 | Oct 03 07:04:58 AM UTC 24 | 1337850000 ps | ||
| T153 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.1099047457 | Oct 03 07:04:48 AM UTC 24 | Oct 03 07:04:58 AM UTC 24 | 1398250000 ps | ||
| T154 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.37827886 | Oct 03 07:04:48 AM UTC 24 | Oct 03 07:04:59 AM UTC 24 | 1496990000 ps | ||
| T155 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.3876394147 | Oct 03 07:04:50 AM UTC 24 | Oct 03 07:05:00 AM UTC 24 | 1337910000 ps | ||
| T156 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.2171469971 | Oct 03 07:04:52 AM UTC 24 | Oct 03 07:05:03 AM UTC 24 | 1527050000 ps | ||
| T157 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.1377974294 | Oct 03 07:04:53 AM UTC 24 | Oct 03 07:05:04 AM UTC 24 | 1439850000 ps | ||
| T158 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.1034480759 | Oct 03 07:04:53 AM UTC 24 | Oct 03 07:05:04 AM UTC 24 | 1463970000 ps | ||
| T159 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.3557850927 | Oct 03 07:04:56 AM UTC 24 | Oct 03 07:05:07 AM UTC 24 | 1448110000 ps | ||
| T160 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.2620085473 | Oct 03 07:04:56 AM UTC 24 | Oct 03 07:05:08 AM UTC 24 | 1487750000 ps | ||
| T31 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.1177966755 | Oct 03 08:56:49 AM UTC 24 | Oct 03 09:34:00 AM UTC 24 | 336498110000 ps | ||
| T32 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.341107566 | Oct 03 08:56:49 AM UTC 24 | Oct 03 09:34:01 AM UTC 24 | 336509690000 ps | ||
| T33 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.2172153153 | Oct 03 08:56:49 AM UTC 24 | Oct 03 09:34:01 AM UTC 24 | 336444010000 ps | ||
| T34 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.3178704052 | Oct 03 08:56:49 AM UTC 24 | Oct 03 09:34:02 AM UTC 24 | 336841970000 ps | ||
| T35 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.3029448887 | Oct 03 08:56:49 AM UTC 24 | Oct 03 09:34:02 AM UTC 24 | 336718990000 ps | ||
| T36 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.553278081 | Oct 03 08:56:51 AM UTC 24 | Oct 03 09:34:02 AM UTC 24 | 336484790000 ps | ||
| T37 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.1229231737 | Oct 03 08:56:49 AM UTC 24 | Oct 03 09:34:03 AM UTC 24 | 336740450000 ps | ||
| T38 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.4026162063 | Oct 03 08:56:51 AM UTC 24 | Oct 03 09:34:03 AM UTC 24 | 336336490000 ps | ||
| T39 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.655759485 | Oct 03 08:56:49 AM UTC 24 | Oct 03 09:34:04 AM UTC 24 | 337052150000 ps | ||
| T40 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.3602853628 | Oct 03 08:56:50 AM UTC 24 | Oct 03 09:34:04 AM UTC 24 | 336625230000 ps | ||
| T161 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.3525993127 | Oct 03 08:56:49 AM UTC 24 | Oct 03 09:34:05 AM UTC 24 | 336802150000 ps | ||
| T162 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.2295331053 | Oct 03 08:56:51 AM UTC 24 | Oct 03 09:34:05 AM UTC 24 | 336399590000 ps | ||
| T163 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.1121204319 | Oct 03 08:56:49 AM UTC 24 | Oct 03 09:34:05 AM UTC 24 | 336606890000 ps | ||
| T164 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.3385738043 | Oct 03 08:56:51 AM UTC 24 | Oct 03 09:34:05 AM UTC 24 | 336416570000 ps | ||
| T165 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.1329220213 | Oct 03 08:56:51 AM UTC 24 | Oct 03 09:34:05 AM UTC 24 | 336595490000 ps | ||
| T166 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.555492761 | Oct 03 08:56:51 AM UTC 24 | Oct 03 09:34:05 AM UTC 24 | 337009210000 ps | ||
| T167 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.2181134022 | Oct 03 08:56:51 AM UTC 24 | Oct 03 09:34:05 AM UTC 24 | 336917830000 ps | ||
| T168 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.350910364 | Oct 03 08:56:49 AM UTC 24 | Oct 03 09:34:05 AM UTC 24 | 336751610000 ps | ||
| T169 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.2551339918 | Oct 03 08:56:51 AM UTC 24 | Oct 03 09:34:05 AM UTC 24 | 336585110000 ps | ||
| T170 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.2740854204 | Oct 03 08:56:49 AM UTC 24 | Oct 03 09:34:05 AM UTC 24 | 336483750000 ps | ||
| T171 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.1258329170 | Oct 03 08:56:49 AM UTC 24 | Oct 03 09:34:05 AM UTC 24 | 336867190000 ps | ||
| T172 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.3515507796 | Oct 03 08:56:51 AM UTC 24 | Oct 03 09:34:06 AM UTC 24 | 337030930000 ps | ||
| T173 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.1209049240 | Oct 03 08:56:49 AM UTC 24 | Oct 03 09:34:06 AM UTC 24 | 337069770000 ps | ||
| T174 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.265313665 | Oct 03 08:56:51 AM UTC 24 | Oct 03 09:34:07 AM UTC 24 | 336470610000 ps | ||
| T175 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.556688552 | Oct 03 08:56:51 AM UTC 24 | Oct 03 09:34:07 AM UTC 24 | 336390710000 ps | ||
| T176 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.2559167854 | Oct 03 08:56:49 AM UTC 24 | Oct 03 09:34:07 AM UTC 24 | 336962390000 ps | ||
| T177 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.2045294010 | Oct 03 08:56:55 AM UTC 24 | Oct 03 09:34:08 AM UTC 24 | 336708850000 ps | ||
| T178 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.2496622872 | Oct 03 08:56:49 AM UTC 24 | Oct 03 09:34:08 AM UTC 24 | 336618770000 ps | ||
| T179 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1358918015 | Oct 03 08:56:51 AM UTC 24 | Oct 03 09:34:08 AM UTC 24 | 336917590000 ps | ||
| T180 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.3921541078 | Oct 03 08:56:52 AM UTC 24 | Oct 03 09:34:09 AM UTC 24 | 336367990000 ps | ||
| T181 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.1116846666 | Oct 03 08:56:49 AM UTC 24 | Oct 03 09:34:09 AM UTC 24 | 336989490000 ps | ||
| T182 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.4018525795 | Oct 03 08:56:52 AM UTC 24 | Oct 03 09:34:09 AM UTC 24 | 336671750000 ps | ||
| T183 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.766546021 | Oct 03 08:56:49 AM UTC 24 | Oct 03 09:34:10 AM UTC 24 | 336935990000 ps | ||
| T184 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.3908143024 | Oct 03 08:56:49 AM UTC 24 | Oct 03 09:34:10 AM UTC 24 | 336926670000 ps | ||
| T185 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.1697674292 | Oct 03 08:56:49 AM UTC 24 | Oct 03 09:34:10 AM UTC 24 | 337069930000 ps | ||
| T186 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.3319796393 | Oct 03 08:56:51 AM UTC 24 | Oct 03 09:34:11 AM UTC 24 | 336909550000 ps | ||
| T187 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.4114069980 | Oct 03 08:56:51 AM UTC 24 | Oct 03 09:34:12 AM UTC 24 | 336937650000 ps | ||
| T188 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.3021723962 | Oct 03 08:56:52 AM UTC 24 | Oct 03 09:34:12 AM UTC 24 | 336821750000 ps | ||
| T189 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.2986044786 | Oct 03 08:56:55 AM UTC 24 | Oct 03 09:34:13 AM UTC 24 | 337034350000 ps | ||
| T190 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.3942073010 | Oct 03 08:56:51 AM UTC 24 | Oct 03 09:34:13 AM UTC 24 | 336677210000 ps | ||
| T191 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.1277361717 | Oct 03 08:56:51 AM UTC 24 | Oct 03 09:34:14 AM UTC 24 | 336619790000 ps | ||
| T192 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.2918295240 | Oct 03 08:56:54 AM UTC 24 | Oct 03 09:34:14 AM UTC 24 | 337140770000 ps | ||
| T193 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.64237164 | Oct 03 08:56:52 AM UTC 24 | Oct 03 09:34:14 AM UTC 24 | 336570790000 ps | ||
| T194 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.84079414 | Oct 03 08:56:51 AM UTC 24 | Oct 03 09:34:14 AM UTC 24 | 336353710000 ps | ||
| T195 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.1471860102 | Oct 03 08:56:51 AM UTC 24 | Oct 03 09:34:15 AM UTC 24 | 337076430000 ps | ||
| T196 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.846015080 | Oct 03 08:56:57 AM UTC 24 | Oct 03 09:34:16 AM UTC 24 | 336784090000 ps | ||
| T197 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.3075424530 | Oct 03 08:56:52 AM UTC 24 | Oct 03 09:34:17 AM UTC 24 | 337031250000 ps | ||
| T198 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.175652958 | Oct 03 08:56:54 AM UTC 24 | Oct 03 09:34:17 AM UTC 24 | 337104650000 ps | ||
| T199 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.3581966160 | Oct 03 08:56:53 AM UTC 24 | Oct 03 09:34:17 AM UTC 24 | 336769770000 ps | ||
| T200 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.2951054293 | Oct 03 08:56:51 AM UTC 24 | Oct 03 09:34:19 AM UTC 24 | 336753030000 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.3099281572 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 1336090000 ps |
| CPU time | 2.26 seconds |
| Started | Oct 03 06:28:00 AM UTC 24 |
| Finished | Oct 03 06:28:16 AM UTC 24 |
| Peak memory | 177728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3099281572 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.3099281572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/0.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.2849184720 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 336889230000 ps |
| CPU time | 264.17 seconds |
| Started | Oct 03 07:01:23 AM UTC 24 |
| Finished | Oct 03 07:38:49 AM UTC 24 |
| Peak memory | 176528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2849184720 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.2849184720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/0.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.1177966755 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 336498110000 ps |
| CPU time | 259.49 seconds |
| Started | Oct 03 08:56:49 AM UTC 24 |
| Finished | Oct 03 09:34:00 AM UTC 24 |
| Peak memory | 175056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1177966755 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.1177966755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/1.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.2620211950 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 1509890000 ps |
| CPU time | 2.13 seconds |
| Started | Oct 03 07:03:55 AM UTC 24 |
| Finished | Oct 03 07:04:05 AM UTC 24 |
| Peak memory | 177820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2620211950 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.2620211950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/0.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.1697674292 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 337069930000 ps |
| CPU time | 266.43 seconds |
| Started | Oct 03 08:56:49 AM UTC 24 |
| Finished | Oct 03 09:34:10 AM UTC 24 |
| Peak memory | 174988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1697674292 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.1697674292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/0.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.1121204319 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 336606890000 ps |
| CPU time | 267.49 seconds |
| Started | Oct 03 08:56:49 AM UTC 24 |
| Finished | Oct 03 09:34:05 AM UTC 24 |
| Peak memory | 176288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1121204319 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.1121204319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/10.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.2496622872 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 336618770000 ps |
| CPU time | 259.87 seconds |
| Started | Oct 03 08:56:49 AM UTC 24 |
| Finished | Oct 03 09:34:08 AM UTC 24 |
| Peak memory | 176536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2496622872 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.2496622872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/11.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.2172153153 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 336444010000 ps |
| CPU time | 267.47 seconds |
| Started | Oct 03 08:56:49 AM UTC 24 |
| Finished | Oct 03 09:34:01 AM UTC 24 |
| Peak memory | 174996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2172153153 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.2172153153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/12.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.1116846666 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 336989490000 ps |
| CPU time | 259.73 seconds |
| Started | Oct 03 08:56:49 AM UTC 24 |
| Finished | Oct 03 09:34:09 AM UTC 24 |
| Peak memory | 174732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1116846666 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.1116846666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/13.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.2740854204 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 336483750000 ps |
| CPU time | 265.13 seconds |
| Started | Oct 03 08:56:49 AM UTC 24 |
| Finished | Oct 03 09:34:05 AM UTC 24 |
| Peak memory | 176536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2740854204 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.2740854204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/14.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.3029448887 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 336718990000 ps |
| CPU time | 259.73 seconds |
| Started | Oct 03 08:56:49 AM UTC 24 |
| Finished | Oct 03 09:34:02 AM UTC 24 |
| Peak memory | 176536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3029448887 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.3029448887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/15.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.3178704052 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 336841970000 ps |
| CPU time | 264.56 seconds |
| Started | Oct 03 08:56:49 AM UTC 24 |
| Finished | Oct 03 09:34:02 AM UTC 24 |
| Peak memory | 176536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3178704052 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.3178704052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/16.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.2559167854 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 336962390000 ps |
| CPU time | 257.65 seconds |
| Started | Oct 03 08:56:49 AM UTC 24 |
| Finished | Oct 03 09:34:07 AM UTC 24 |
| Peak memory | 174896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2559167854 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.2559167854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/17.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.1209049240 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 337069770000 ps |
| CPU time | 268.37 seconds |
| Started | Oct 03 08:56:49 AM UTC 24 |
| Finished | Oct 03 09:34:06 AM UTC 24 |
| Peak memory | 176296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1209049240 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.1209049240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/18.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.3602853628 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 336625230000 ps |
| CPU time | 267.21 seconds |
| Started | Oct 03 08:56:50 AM UTC 24 |
| Finished | Oct 03 09:34:04 AM UTC 24 |
| Peak memory | 174996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3602853628 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.3602853628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/19.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.3525993127 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 336802150000 ps |
| CPU time | 267.43 seconds |
| Started | Oct 03 08:56:49 AM UTC 24 |
| Finished | Oct 03 09:34:05 AM UTC 24 |
| Peak memory | 174988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3525993127 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.3525993127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/2.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.2551339918 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 336585110000 ps |
| CPU time | 267.92 seconds |
| Started | Oct 03 08:56:51 AM UTC 24 |
| Finished | Oct 03 09:34:05 AM UTC 24 |
| Peak memory | 174960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2551339918 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.2551339918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/20.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.3385738043 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 336416570000 ps |
| CPU time | 257.22 seconds |
| Started | Oct 03 08:56:51 AM UTC 24 |
| Finished | Oct 03 09:34:05 AM UTC 24 |
| Peak memory | 174936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3385738043 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.3385738043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/21.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.555492761 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 337009210000 ps |
| CPU time | 265.7 seconds |
| Started | Oct 03 08:56:51 AM UTC 24 |
| Finished | Oct 03 09:34:05 AM UTC 24 |
| Peak memory | 174804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=555492761 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.555492761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/22.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.4026162063 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 336336490000 ps |
| CPU time | 256.17 seconds |
| Started | Oct 03 08:56:51 AM UTC 24 |
| Finished | Oct 03 09:34:03 AM UTC 24 |
| Peak memory | 174780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4026162063 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.4026162063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/23.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.3515507796 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 337030930000 ps |
| CPU time | 259.48 seconds |
| Started | Oct 03 08:56:51 AM UTC 24 |
| Finished | Oct 03 09:34:06 AM UTC 24 |
| Peak memory | 174996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3515507796 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.3515507796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/24.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.553278081 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 336484790000 ps |
| CPU time | 264.15 seconds |
| Started | Oct 03 08:56:51 AM UTC 24 |
| Finished | Oct 03 09:34:02 AM UTC 24 |
| Peak memory | 176536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=553278081 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.553278081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/25.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1358918015 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 336917590000 ps |
| CPU time | 260.76 seconds |
| Started | Oct 03 08:56:51 AM UTC 24 |
| Finished | Oct 03 09:34:08 AM UTC 24 |
| Peak memory | 174996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1358918015 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.1358918015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/26.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.3942073010 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 336677210000 ps |
| CPU time | 266.09 seconds |
| Started | Oct 03 08:56:51 AM UTC 24 |
| Finished | Oct 03 09:34:13 AM UTC 24 |
| Peak memory | 176536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3942073010 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.3942073010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/27.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.2181134022 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 336917830000 ps |
| CPU time | 264.73 seconds |
| Started | Oct 03 08:56:51 AM UTC 24 |
| Finished | Oct 03 09:34:05 AM UTC 24 |
| Peak memory | 176536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2181134022 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.2181134022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/28.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.1329220213 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 336595490000 ps |
| CPU time | 267.09 seconds |
| Started | Oct 03 08:56:51 AM UTC 24 |
| Finished | Oct 03 09:34:05 AM UTC 24 |
| Peak memory | 174996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1329220213 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.1329220213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/29.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.1258329170 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 336867190000 ps |
| CPU time | 256.63 seconds |
| Started | Oct 03 08:56:49 AM UTC 24 |
| Finished | Oct 03 09:34:05 AM UTC 24 |
| Peak memory | 176528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1258329170 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.1258329170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/3.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.265313665 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 336470610000 ps |
| CPU time | 261.09 seconds |
| Started | Oct 03 08:56:51 AM UTC 24 |
| Finished | Oct 03 09:34:07 AM UTC 24 |
| Peak memory | 176536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=265313665 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.265313665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/30.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.2295331053 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 336399590000 ps |
| CPU time | 263.53 seconds |
| Started | Oct 03 08:56:51 AM UTC 24 |
| Finished | Oct 03 09:34:05 AM UTC 24 |
| Peak memory | 174996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2295331053 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.2295331053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/31.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.4114069980 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 336937650000 ps |
| CPU time | 264.28 seconds |
| Started | Oct 03 08:56:51 AM UTC 24 |
| Finished | Oct 03 09:34:12 AM UTC 24 |
| Peak memory | 174996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4114069980 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.4114069980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/32.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.556688552 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 336390710000 ps |
| CPU time | 267.25 seconds |
| Started | Oct 03 08:56:51 AM UTC 24 |
| Finished | Oct 03 09:34:07 AM UTC 24 |
| Peak memory | 176536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=556688552 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.556688552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/33.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.1471860102 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 337076430000 ps |
| CPU time | 260.99 seconds |
| Started | Oct 03 08:56:51 AM UTC 24 |
| Finished | Oct 03 09:34:15 AM UTC 24 |
| Peak memory | 174996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1471860102 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.1471860102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/34.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.2951054293 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 336753030000 ps |
| CPU time | 258.76 seconds |
| Started | Oct 03 08:56:51 AM UTC 24 |
| Finished | Oct 03 09:34:19 AM UTC 24 |
| Peak memory | 174996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2951054293 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.2951054293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/35.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.1277361717 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 336619790000 ps |
| CPU time | 267.29 seconds |
| Started | Oct 03 08:56:51 AM UTC 24 |
| Finished | Oct 03 09:34:14 AM UTC 24 |
| Peak memory | 174996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1277361717 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.1277361717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/36.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.84079414 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 336353710000 ps |
| CPU time | 263.32 seconds |
| Started | Oct 03 08:56:51 AM UTC 24 |
| Finished | Oct 03 09:34:14 AM UTC 24 |
| Peak memory | 176524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=84079414 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_ fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.84079414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/37.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.3319796393 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 336909550000 ps |
| CPU time | 263.29 seconds |
| Started | Oct 03 08:56:51 AM UTC 24 |
| Finished | Oct 03 09:34:11 AM UTC 24 |
| Peak memory | 174992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3319796393 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.3319796393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/38.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.3075424530 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 337031250000 ps |
| CPU time | 261.07 seconds |
| Started | Oct 03 08:56:52 AM UTC 24 |
| Finished | Oct 03 09:34:17 AM UTC 24 |
| Peak memory | 174996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3075424530 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.3075424530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/39.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.766546021 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 336935990000 ps |
| CPU time | 263.64 seconds |
| Started | Oct 03 08:56:49 AM UTC 24 |
| Finished | Oct 03 09:34:10 AM UTC 24 |
| Peak memory | 174936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=766546021 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.766546021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/4.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.3921541078 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 336367990000 ps |
| CPU time | 268.5 seconds |
| Started | Oct 03 08:56:52 AM UTC 24 |
| Finished | Oct 03 09:34:09 AM UTC 24 |
| Peak memory | 176536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3921541078 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.3921541078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/40.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.3021723962 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 336821750000 ps |
| CPU time | 269.51 seconds |
| Started | Oct 03 08:56:52 AM UTC 24 |
| Finished | Oct 03 09:34:12 AM UTC 24 |
| Peak memory | 174996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3021723962 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.3021723962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/41.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.64237164 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 336570790000 ps |
| CPU time | 259.76 seconds |
| Started | Oct 03 08:56:52 AM UTC 24 |
| Finished | Oct 03 09:34:14 AM UTC 24 |
| Peak memory | 174980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=64237164 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_ fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.64237164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/42.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.4018525795 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 336671750000 ps |
| CPU time | 264.99 seconds |
| Started | Oct 03 08:56:52 AM UTC 24 |
| Finished | Oct 03 09:34:09 AM UTC 24 |
| Peak memory | 176536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4018525795 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.4018525795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/43.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.3581966160 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 336769770000 ps |
| CPU time | 260.35 seconds |
| Started | Oct 03 08:56:53 AM UTC 24 |
| Finished | Oct 03 09:34:17 AM UTC 24 |
| Peak memory | 176536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3581966160 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.3581966160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/44.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.175652958 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 337104650000 ps |
| CPU time | 265.8 seconds |
| Started | Oct 03 08:56:54 AM UTC 24 |
| Finished | Oct 03 09:34:17 AM UTC 24 |
| Peak memory | 176536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=175652958 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.175652958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/45.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.2918295240 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 337140770000 ps |
| CPU time | 267.46 seconds |
| Started | Oct 03 08:56:54 AM UTC 24 |
| Finished | Oct 03 09:34:14 AM UTC 24 |
| Peak memory | 176536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2918295240 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.2918295240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/46.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.2045294010 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 336708850000 ps |
| CPU time | 261.55 seconds |
| Started | Oct 03 08:56:55 AM UTC 24 |
| Finished | Oct 03 09:34:08 AM UTC 24 |
| Peak memory | 176536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2045294010 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.2045294010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/47.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.2986044786 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 337034350000 ps |
| CPU time | 266.57 seconds |
| Started | Oct 03 08:56:55 AM UTC 24 |
| Finished | Oct 03 09:34:13 AM UTC 24 |
| Peak memory | 174996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2986044786 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.2986044786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/48.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.846015080 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 336784090000 ps |
| CPU time | 269.34 seconds |
| Started | Oct 03 08:56:57 AM UTC 24 |
| Finished | Oct 03 09:34:16 AM UTC 24 |
| Peak memory | 174996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=846015080 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.846015080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/49.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.341107566 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 336509690000 ps |
| CPU time | 264.81 seconds |
| Started | Oct 03 08:56:49 AM UTC 24 |
| Finished | Oct 03 09:34:01 AM UTC 24 |
| Peak memory | 176532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=341107566 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.341107566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/5.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.1229231737 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 336740450000 ps |
| CPU time | 266.98 seconds |
| Started | Oct 03 08:56:49 AM UTC 24 |
| Finished | Oct 03 09:34:03 AM UTC 24 |
| Peak memory | 174920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1229231737 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.1229231737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/6.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.3908143024 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 336926670000 ps |
| CPU time | 261.6 seconds |
| Started | Oct 03 08:56:49 AM UTC 24 |
| Finished | Oct 03 09:34:10 AM UTC 24 |
| Peak memory | 176528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3908143024 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.3908143024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/7.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.350910364 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 336751610000 ps |
| CPU time | 268.92 seconds |
| Started | Oct 03 08:56:49 AM UTC 24 |
| Finished | Oct 03 09:34:05 AM UTC 24 |
| Peak memory | 174988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=350910364 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.350910364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/8.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.655759485 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 337052150000 ps |
| CPU time | 265.89 seconds |
| Started | Oct 03 08:56:49 AM UTC 24 |
| Finished | Oct 03 09:34:04 AM UTC 24 |
| Peak memory | 174988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=655759485 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.655759485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/9.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.157711591 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 336409290000 ps |
| CPU time | 270.13 seconds |
| Started | Oct 03 07:01:26 AM UTC 24 |
| Finished | Oct 03 07:38:40 AM UTC 24 |
| Peak memory | 176592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=157711591 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.157711591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/1.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.2606826241 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 336465010000 ps |
| CPU time | 263.96 seconds |
| Started | Oct 03 07:01:34 AM UTC 24 |
| Finished | Oct 03 07:38:56 AM UTC 24 |
| Peak memory | 174996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2606826241 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.2606826241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/10.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.474040679 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 336398430000 ps |
| CPU time | 268.2 seconds |
| Started | Oct 03 07:01:36 AM UTC 24 |
| Finished | Oct 03 07:38:53 AM UTC 24 |
| Peak memory | 176536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=474040679 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.474040679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/11.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.4061645659 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 336404810000 ps |
| CPU time | 269.6 seconds |
| Started | Oct 03 07:01:36 AM UTC 24 |
| Finished | Oct 03 07:38:51 AM UTC 24 |
| Peak memory | 176536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4061645659 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.4061645659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/12.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.3767477325 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 336650910000 ps |
| CPU time | 259.79 seconds |
| Started | Oct 03 07:01:40 AM UTC 24 |
| Finished | Oct 03 07:39:04 AM UTC 24 |
| Peak memory | 174996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3767477325 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.3767477325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/13.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.3288286290 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 336723930000 ps |
| CPU time | 268.43 seconds |
| Started | Oct 03 07:01:42 AM UTC 24 |
| Finished | Oct 03 07:38:58 AM UTC 24 |
| Peak memory | 174996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3288286290 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.3288286290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/14.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.36773150 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 336790030000 ps |
| CPU time | 268.19 seconds |
| Started | Oct 03 07:01:44 AM UTC 24 |
| Finished | Oct 03 07:39:01 AM UTC 24 |
| Peak memory | 176524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36773150 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_ gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.36773150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/15.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.1649968091 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 336564070000 ps |
| CPU time | 262.77 seconds |
| Started | Oct 03 07:01:44 AM UTC 24 |
| Finished | Oct 03 07:39:11 AM UTC 24 |
| Peak memory | 176536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1649968091 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.1649968091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/16.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.932723399 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 336575650000 ps |
| CPU time | 258.66 seconds |
| Started | Oct 03 07:01:45 AM UTC 24 |
| Finished | Oct 03 07:39:09 AM UTC 24 |
| Peak memory | 174996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=932723399 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.932723399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/17.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.844411968 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 336725010000 ps |
| CPU time | 260.95 seconds |
| Started | Oct 03 07:01:46 AM UTC 24 |
| Finished | Oct 03 07:39:14 AM UTC 24 |
| Peak memory | 176532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=844411968 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.844411968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/18.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.3113410987 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 337151890000 ps |
| CPU time | 264 seconds |
| Started | Oct 03 07:01:46 AM UTC 24 |
| Finished | Oct 03 07:39:06 AM UTC 24 |
| Peak memory | 174996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3113410987 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.3113410987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/19.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.2117039023 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 336543890000 ps |
| CPU time | 265.28 seconds |
| Started | Oct 03 07:01:26 AM UTC 24 |
| Finished | Oct 03 07:38:50 AM UTC 24 |
| Peak memory | 174988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2117039023 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.2117039023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/2.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.40609166 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 336567250000 ps |
| CPU time | 265.38 seconds |
| Started | Oct 03 07:01:50 AM UTC 24 |
| Finished | Oct 03 07:39:18 AM UTC 24 |
| Peak memory | 174984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40609166 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_ gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.40609166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/20.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3825847335 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 336328810000 ps |
| CPU time | 268.8 seconds |
| Started | Oct 03 07:01:51 AM UTC 24 |
| Finished | Oct 03 07:39:06 AM UTC 24 |
| Peak memory | 176532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3825847335 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.3825847335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/21.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.2594561352 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 336353110000 ps |
| CPU time | 268.38 seconds |
| Started | Oct 03 07:01:52 AM UTC 24 |
| Finished | Oct 03 07:39:09 AM UTC 24 |
| Peak memory | 174996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2594561352 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.2594561352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/22.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.2428613359 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 337035690000 ps |
| CPU time | 263.24 seconds |
| Started | Oct 03 07:01:53 AM UTC 24 |
| Finished | Oct 03 07:39:25 AM UTC 24 |
| Peak memory | 174996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2428613359 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.2428613359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/23.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.1521693364 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 337087590000 ps |
| CPU time | 266.59 seconds |
| Started | Oct 03 07:01:58 AM UTC 24 |
| Finished | Oct 03 07:39:26 AM UTC 24 |
| Peak memory | 174996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1521693364 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.1521693364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/24.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.3602966146 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 336998850000 ps |
| CPU time | 268.91 seconds |
| Started | Oct 03 07:01:59 AM UTC 24 |
| Finished | Oct 03 07:39:21 AM UTC 24 |
| Peak memory | 176536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3602966146 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.3602966146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/25.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.3274505794 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 336513770000 ps |
| CPU time | 267.27 seconds |
| Started | Oct 03 07:02:01 AM UTC 24 |
| Finished | Oct 03 07:39:22 AM UTC 24 |
| Peak memory | 176536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3274505794 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.3274505794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/26.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.2463379272 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 336341590000 ps |
| CPU time | 264.59 seconds |
| Started | Oct 03 07:02:13 AM UTC 24 |
| Finished | Oct 03 07:39:32 AM UTC 24 |
| Peak memory | 176536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2463379272 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.2463379272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/27.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.3995179455 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 336385310000 ps |
| CPU time | 267.28 seconds |
| Started | Oct 03 07:02:16 AM UTC 24 |
| Finished | Oct 03 07:39:38 AM UTC 24 |
| Peak memory | 174996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3995179455 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.3995179455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/28.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.4265397741 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 336496230000 ps |
| CPU time | 262.32 seconds |
| Started | Oct 03 07:02:18 AM UTC 24 |
| Finished | Oct 03 07:39:46 AM UTC 24 |
| Peak memory | 176588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4265397741 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.4265397741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/29.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.2505959978 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 336778370000 ps |
| CPU time | 269.56 seconds |
| Started | Oct 03 07:01:26 AM UTC 24 |
| Finished | Oct 03 07:38:43 AM UTC 24 |
| Peak memory | 174988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2505959978 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.2505959978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/3.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.972561901 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 336865950000 ps |
| CPU time | 259.08 seconds |
| Started | Oct 03 07:02:21 AM UTC 24 |
| Finished | Oct 03 07:39:59 AM UTC 24 |
| Peak memory | 174996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=972561901 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.972561901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/30.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.3095491522 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 336676390000 ps |
| CPU time | 267.31 seconds |
| Started | Oct 03 07:02:21 AM UTC 24 |
| Finished | Oct 03 07:39:47 AM UTC 24 |
| Peak memory | 176536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3095491522 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.3095491522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/31.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.1173800149 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 336971030000 ps |
| CPU time | 269.46 seconds |
| Started | Oct 03 07:02:23 AM UTC 24 |
| Finished | Oct 03 07:39:53 AM UTC 24 |
| Peak memory | 176532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1173800149 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.1173800149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/32.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.2884102185 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 337049310000 ps |
| CPU time | 270.07 seconds |
| Started | Oct 03 07:02:26 AM UTC 24 |
| Finished | Oct 03 07:39:57 AM UTC 24 |
| Peak memory | 176536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2884102185 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.2884102185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/33.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.730335475 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 336409450000 ps |
| CPU time | 269.18 seconds |
| Started | Oct 03 07:02:49 AM UTC 24 |
| Finished | Oct 03 07:40:23 AM UTC 24 |
| Peak memory | 176536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=730335475 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.730335475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/34.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.410875144 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 336637890000 ps |
| CPU time | 261.96 seconds |
| Started | Oct 03 07:02:55 AM UTC 24 |
| Finished | Oct 03 07:40:42 AM UTC 24 |
| Peak memory | 174996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=410875144 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.410875144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/35.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.2023955360 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 336668910000 ps |
| CPU time | 268.45 seconds |
| Started | Oct 03 07:02:59 AM UTC 24 |
| Finished | Oct 03 07:40:40 AM UTC 24 |
| Peak memory | 176532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2023955360 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.2023955360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/36.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.1521435453 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 336547170000 ps |
| CPU time | 264.23 seconds |
| Started | Oct 03 07:03:01 AM UTC 24 |
| Finished | Oct 03 07:40:50 AM UTC 24 |
| Peak memory | 176536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1521435453 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.1521435453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/37.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3979338959 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 336817470000 ps |
| CPU time | 267.14 seconds |
| Started | Oct 03 07:03:08 AM UTC 24 |
| Finished | Oct 03 07:40:57 AM UTC 24 |
| Peak memory | 174996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3979338959 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.3979338959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/38.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.3477293876 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 336888590000 ps |
| CPU time | 264.72 seconds |
| Started | Oct 03 07:03:10 AM UTC 24 |
| Finished | Oct 03 07:40:54 AM UTC 24 |
| Peak memory | 176536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3477293876 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.3477293876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/39.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.2708427471 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 336826930000 ps |
| CPU time | 268 seconds |
| Started | Oct 03 07:01:28 AM UTC 24 |
| Finished | Oct 03 07:38:45 AM UTC 24 |
| Peak memory | 176528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2708427471 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.2708427471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/4.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.3003235001 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 337092990000 ps |
| CPU time | 260.72 seconds |
| Started | Oct 03 07:03:17 AM UTC 24 |
| Finished | Oct 03 07:41:16 AM UTC 24 |
| Peak memory | 176532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3003235001 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.3003235001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/40.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.3978592232 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 336653390000 ps |
| CPU time | 267.36 seconds |
| Started | Oct 03 07:03:27 AM UTC 24 |
| Finished | Oct 03 07:41:16 AM UTC 24 |
| Peak memory | 176536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3978592232 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.3978592232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/41.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.3056960553 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 336969750000 ps |
| CPU time | 265.73 seconds |
| Started | Oct 03 07:03:27 AM UTC 24 |
| Finished | Oct 03 07:41:18 AM UTC 24 |
| Peak memory | 174996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3056960553 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.3056960553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/42.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.257208374 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 336761150000 ps |
| CPU time | 268.75 seconds |
| Started | Oct 03 07:03:32 AM UTC 24 |
| Finished | Oct 03 07:41:23 AM UTC 24 |
| Peak memory | 176536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=257208374 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.257208374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/43.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.640849621 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 336513310000 ps |
| CPU time | 266.74 seconds |
| Started | Oct 03 07:03:40 AM UTC 24 |
| Finished | Oct 03 07:41:30 AM UTC 24 |
| Peak memory | 176536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=640849621 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.640849621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/44.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.3858502203 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 336554950000 ps |
| CPU time | 263.54 seconds |
| Started | Oct 03 07:03:42 AM UTC 24 |
| Finished | Oct 03 07:41:40 AM UTC 24 |
| Peak memory | 174996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3858502203 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.3858502203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/45.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.2206183745 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 337000290000 ps |
| CPU time | 261 seconds |
| Started | Oct 03 07:03:46 AM UTC 24 |
| Finished | Oct 03 07:41:54 AM UTC 24 |
| Peak memory | 176536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2206183745 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.2206183745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/46.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.331612151 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 336934750000 ps |
| CPU time | 265.24 seconds |
| Started | Oct 03 07:03:46 AM UTC 24 |
| Finished | Oct 03 07:41:46 AM UTC 24 |
| Peak memory | 174996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=331612151 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.331612151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/47.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1044145186 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 336916970000 ps |
| CPU time | 261.46 seconds |
| Started | Oct 03 07:03:48 AM UTC 24 |
| Finished | Oct 03 07:41:54 AM UTC 24 |
| Peak memory | 176536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1044145186 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.1044145186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/48.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.1474439662 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 336875190000 ps |
| CPU time | 259.45 seconds |
| Started | Oct 03 07:03:53 AM UTC 24 |
| Finished | Oct 03 07:42:00 AM UTC 24 |
| Peak memory | 176536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1474439662 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.1474439662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/49.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.718563580 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 336686870000 ps |
| CPU time | 269.52 seconds |
| Started | Oct 03 07:01:28 AM UTC 24 |
| Finished | Oct 03 07:38:45 AM UTC 24 |
| Peak memory | 174988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=718563580 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.718563580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/5.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.205685043 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 337054790000 ps |
| CPU time | 268.42 seconds |
| Started | Oct 03 07:01:28 AM UTC 24 |
| Finished | Oct 03 07:38:46 AM UTC 24 |
| Peak memory | 174988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=205685043 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.205685043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/6.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.748621634 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 337045730000 ps |
| CPU time | 265.92 seconds |
| Started | Oct 03 07:01:30 AM UTC 24 |
| Finished | Oct 03 07:38:53 AM UTC 24 |
| Peak memory | 176528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=748621634 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.748621634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/7.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.2924180945 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 337026630000 ps |
| CPU time | 269.09 seconds |
| Started | Oct 03 07:01:32 AM UTC 24 |
| Finished | Oct 03 07:38:51 AM UTC 24 |
| Peak memory | 174988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2924180945 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.2924180945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/8.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.1547282051 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 336973270000 ps |
| CPU time | 264.6 seconds |
| Started | Oct 03 07:01:32 AM UTC 24 |
| Finished | Oct 03 07:39:00 AM UTC 24 |
| Peak memory | 176524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1547282051 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.1547282051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/9.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.1836345215 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 1241010000 ps |
| CPU time | 1.8 seconds |
| Started | Oct 03 07:04:01 AM UTC 24 |
| Finished | Oct 03 07:04:10 AM UTC 24 |
| Peak memory | 177764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1836345215 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.1836345215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/1.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.2538237496 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 1465530000 ps |
| CPU time | 2.03 seconds |
| Started | Oct 03 07:04:20 AM UTC 24 |
| Finished | Oct 03 07:04:30 AM UTC 24 |
| Peak memory | 177796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2538237496 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.2538237496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/10.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.4175493845 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 1481870000 ps |
| CPU time | 1.96 seconds |
| Started | Oct 03 07:04:22 AM UTC 24 |
| Finished | Oct 03 07:04:33 AM UTC 24 |
| Peak memory | 177796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4175493845 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.4175493845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/11.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.2482490372 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 1486410000 ps |
| CPU time | 1.93 seconds |
| Started | Oct 03 07:04:24 AM UTC 24 |
| Finished | Oct 03 07:04:35 AM UTC 24 |
| Peak memory | 177796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2482490372 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.2482490372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/12.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.3247025514 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 1499690000 ps |
| CPU time | 2.01 seconds |
| Started | Oct 03 07:04:24 AM UTC 24 |
| Finished | Oct 03 07:04:35 AM UTC 24 |
| Peak memory | 177796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3247025514 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.3247025514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/13.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.319804764 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 1385490000 ps |
| CPU time | 1.87 seconds |
| Started | Oct 03 07:04:24 AM UTC 24 |
| Finished | Oct 03 07:04:34 AM UTC 24 |
| Peak memory | 177764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=319804764 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f ib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.319804764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/14.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.396095797 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 1113070000 ps |
| CPU time | 1.64 seconds |
| Started | Oct 03 07:04:24 AM UTC 24 |
| Finished | Oct 03 07:04:33 AM UTC 24 |
| Peak memory | 177740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=396095797 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f ib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.396095797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/15.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.3575470599 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 1371370000 ps |
| CPU time | 1.92 seconds |
| Started | Oct 03 07:04:24 AM UTC 24 |
| Finished | Oct 03 07:04:34 AM UTC 24 |
| Peak memory | 177796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3575470599 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.3575470599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/16.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.502461732 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 1161090000 ps |
| CPU time | 1.68 seconds |
| Started | Oct 03 07:04:24 AM UTC 24 |
| Finished | Oct 03 07:04:33 AM UTC 24 |
| Peak memory | 177764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=502461732 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f ib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.502461732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/17.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.3539635607 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 1524210000 ps |
| CPU time | 2.14 seconds |
| Started | Oct 03 07:04:28 AM UTC 24 |
| Finished | Oct 03 07:04:39 AM UTC 24 |
| Peak memory | 177796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3539635607 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.3539635607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/18.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.3676318845 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 1500030000 ps |
| CPU time | 2.07 seconds |
| Started | Oct 03 07:04:30 AM UTC 24 |
| Finished | Oct 03 07:04:40 AM UTC 24 |
| Peak memory | 177796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3676318845 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.3676318845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/19.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.2528356852 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 1486990000 ps |
| CPU time | 2.02 seconds |
| Started | Oct 03 07:04:01 AM UTC 24 |
| Finished | Oct 03 07:04:12 AM UTC 24 |
| Peak memory | 177764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2528356852 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.2528356852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/2.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.3510935810 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 1399890000 ps |
| CPU time | 2.09 seconds |
| Started | Oct 03 07:04:32 AM UTC 24 |
| Finished | Oct 03 07:04:42 AM UTC 24 |
| Peak memory | 177796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3510935810 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.3510935810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/20.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.721112406 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 1436070000 ps |
| CPU time | 1.85 seconds |
| Started | Oct 03 07:04:32 AM UTC 24 |
| Finished | Oct 03 07:04:42 AM UTC 24 |
| Peak memory | 177764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=721112406 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f ib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.721112406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/21.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.4253325184 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 1392390000 ps |
| CPU time | 1.95 seconds |
| Started | Oct 03 07:04:34 AM UTC 24 |
| Finished | Oct 03 07:04:44 AM UTC 24 |
| Peak memory | 177796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4253325184 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.4253325184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/22.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.411090681 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 1419610000 ps |
| CPU time | 1.9 seconds |
| Started | Oct 03 07:04:34 AM UTC 24 |
| Finished | Oct 03 07:04:44 AM UTC 24 |
| Peak memory | 177764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=411090681 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f ib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.411090681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/23.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.3380621 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 1486390000 ps |
| CPU time | 1.93 seconds |
| Started | Oct 03 07:04:34 AM UTC 24 |
| Finished | Oct 03 07:04:44 AM UTC 24 |
| Peak memory | 177796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3380621 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib .vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.3380621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/24.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.3529895568 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 1250790000 ps |
| CPU time | 1.74 seconds |
| Started | Oct 03 07:04:36 AM UTC 24 |
| Finished | Oct 03 07:04:45 AM UTC 24 |
| Peak memory | 177796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3529895568 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.3529895568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/25.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2750751290 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 1484630000 ps |
| CPU time | 2.05 seconds |
| Started | Oct 03 07:04:36 AM UTC 24 |
| Finished | Oct 03 07:04:47 AM UTC 24 |
| Peak memory | 177796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2750751290 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.2750751290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/26.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.2323414206 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 1531870000 ps |
| CPU time | 1.87 seconds |
| Started | Oct 03 07:04:36 AM UTC 24 |
| Finished | Oct 03 07:04:47 AM UTC 24 |
| Peak memory | 177796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2323414206 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.2323414206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/27.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.2288847206 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 1391390000 ps |
| CPU time | 1.96 seconds |
| Started | Oct 03 07:04:36 AM UTC 24 |
| Finished | Oct 03 07:04:46 AM UTC 24 |
| Peak memory | 177796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2288847206 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.2288847206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/28.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.4137032145 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 1502190000 ps |
| CPU time | 1.99 seconds |
| Started | Oct 03 07:04:36 AM UTC 24 |
| Finished | Oct 03 07:04:47 AM UTC 24 |
| Peak memory | 177796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4137032145 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.4137032145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/29.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.1980088735 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 1289230000 ps |
| CPU time | 1.84 seconds |
| Started | Oct 03 07:04:01 AM UTC 24 |
| Finished | Oct 03 07:04:10 AM UTC 24 |
| Peak memory | 177764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1980088735 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.1980088735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/3.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.153593251 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 1302530000 ps |
| CPU time | 1.77 seconds |
| Started | Oct 03 07:04:39 AM UTC 24 |
| Finished | Oct 03 07:04:49 AM UTC 24 |
| Peak memory | 177764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=153593251 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f ib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.153593251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/30.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.2768253842 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 1315250000 ps |
| CPU time | 1.78 seconds |
| Started | Oct 03 07:04:39 AM UTC 24 |
| Finished | Oct 03 07:04:49 AM UTC 24 |
| Peak memory | 177796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2768253842 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.2768253842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/31.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.1239133769 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 1452230000 ps |
| CPU time | 1.94 seconds |
| Started | Oct 03 07:04:41 AM UTC 24 |
| Finished | Oct 03 07:04:52 AM UTC 24 |
| Peak memory | 177796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1239133769 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.1239133769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/32.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.4093103796 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 1382770000 ps |
| CPU time | 1.86 seconds |
| Started | Oct 03 07:04:43 AM UTC 24 |
| Finished | Oct 03 07:04:52 AM UTC 24 |
| Peak memory | 177796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093103796 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.4093103796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/33.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.3742841362 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 1327250000 ps |
| CPU time | 1.8 seconds |
| Started | Oct 03 07:04:43 AM UTC 24 |
| Finished | Oct 03 07:04:52 AM UTC 24 |
| Peak memory | 177796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3742841362 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.3742841362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/34.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.1742385030 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 1537690000 ps |
| CPU time | 2.06 seconds |
| Started | Oct 03 07:04:45 AM UTC 24 |
| Finished | Oct 03 07:04:56 AM UTC 24 |
| Peak memory | 177496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1742385030 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.1742385030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/35.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.1464420838 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 1570550000 ps |
| CPU time | 2.08 seconds |
| Started | Oct 03 07:04:45 AM UTC 24 |
| Finished | Oct 03 07:04:56 AM UTC 24 |
| Peak memory | 177576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1464420838 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.1464420838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/36.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1148680543 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 1383610000 ps |
| CPU time | 1.93 seconds |
| Started | Oct 03 07:04:46 AM UTC 24 |
| Finished | Oct 03 07:04:56 AM UTC 24 |
| Peak memory | 177796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1148680543 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.1148680543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/37.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.3059103011 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 1470750000 ps |
| CPU time | 2.08 seconds |
| Started | Oct 03 07:04:46 AM UTC 24 |
| Finished | Oct 03 07:04:56 AM UTC 24 |
| Peak memory | 177792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3059103011 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.3059103011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/38.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.2018703370 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 1463910000 ps |
| CPU time | 1.98 seconds |
| Started | Oct 03 07:04:47 AM UTC 24 |
| Finished | Oct 03 07:04:57 AM UTC 24 |
| Peak memory | 177796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2018703370 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.2018703370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/39.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.938490400 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 1563110000 ps |
| CPU time | 2.18 seconds |
| Started | Oct 03 07:04:03 AM UTC 24 |
| Finished | Oct 03 07:04:14 AM UTC 24 |
| Peak memory | 177796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=938490400 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f ib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.938490400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/4.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.1099047457 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 1398250000 ps |
| CPU time | 1.86 seconds |
| Started | Oct 03 07:04:48 AM UTC 24 |
| Finished | Oct 03 07:04:58 AM UTC 24 |
| Peak memory | 177796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1099047457 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.1099047457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/40.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.808421945 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 1337850000 ps |
| CPU time | 1.89 seconds |
| Started | Oct 03 07:04:48 AM UTC 24 |
| Finished | Oct 03 07:04:58 AM UTC 24 |
| Peak memory | 177764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=808421945 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f ib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.808421945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/41.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.37827886 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 1496990000 ps |
| CPU time | 1.98 seconds |
| Started | Oct 03 07:04:48 AM UTC 24 |
| Finished | Oct 03 07:04:59 AM UTC 24 |
| Peak memory | 177760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37827886 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fi b.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.37827886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/42.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1930966987 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 1078470000 ps |
| CPU time | 1.64 seconds |
| Started | Oct 03 07:04:49 AM UTC 24 |
| Finished | Oct 03 07:04:57 AM UTC 24 |
| Peak memory | 177796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1930966987 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.1930966987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/43.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.3876394147 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 1337910000 ps |
| CPU time | 1.94 seconds |
| Started | Oct 03 07:04:50 AM UTC 24 |
| Finished | Oct 03 07:05:00 AM UTC 24 |
| Peak memory | 177796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3876394147 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.3876394147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/44.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.2171469971 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 1527050000 ps |
| CPU time | 2.15 seconds |
| Started | Oct 03 07:04:52 AM UTC 24 |
| Finished | Oct 03 07:05:03 AM UTC 24 |
| Peak memory | 177792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2171469971 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.2171469971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/45.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.1034480759 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 1463970000 ps |
| CPU time | 1.99 seconds |
| Started | Oct 03 07:04:53 AM UTC 24 |
| Finished | Oct 03 07:05:04 AM UTC 24 |
| Peak memory | 177796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1034480759 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.1034480759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/46.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.1377974294 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 1439850000 ps |
| CPU time | 1.83 seconds |
| Started | Oct 03 07:04:53 AM UTC 24 |
| Finished | Oct 03 07:05:04 AM UTC 24 |
| Peak memory | 177796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1377974294 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.1377974294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/47.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.2620085473 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 1487750000 ps |
| CPU time | 2.06 seconds |
| Started | Oct 03 07:04:56 AM UTC 24 |
| Finished | Oct 03 07:05:08 AM UTC 24 |
| Peak memory | 177796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2620085473 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.2620085473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/48.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.3557850927 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 1448110000 ps |
| CPU time | 1.94 seconds |
| Started | Oct 03 07:04:56 AM UTC 24 |
| Finished | Oct 03 07:05:07 AM UTC 24 |
| Peak memory | 177796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3557850927 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.3557850927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/49.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.3494653248 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 1522370000 ps |
| CPU time | 2.11 seconds |
| Started | Oct 03 07:04:07 AM UTC 24 |
| Finished | Oct 03 07:04:18 AM UTC 24 |
| Peak memory | 177764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3494653248 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.3494653248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/5.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.563781107 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 1470070000 ps |
| CPU time | 1.92 seconds |
| Started | Oct 03 07:04:11 AM UTC 24 |
| Finished | Oct 03 07:04:22 AM UTC 24 |
| Peak memory | 177760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=563781107 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f ib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.563781107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/6.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.1441607481 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 1653470000 ps |
| CPU time | 2.13 seconds |
| Started | Oct 03 07:04:12 AM UTC 24 |
| Finished | Oct 03 07:04:23 AM UTC 24 |
| Peak memory | 177764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1441607481 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.1441607481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/7.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1541306534 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 1401830000 ps |
| CPU time | 1.82 seconds |
| Started | Oct 03 07:04:14 AM UTC 24 |
| Finished | Oct 03 07:04:23 AM UTC 24 |
| Peak memory | 177764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1541306534 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.1541306534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/8.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.3953057478 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 1482710000 ps |
| CPU time | 1.96 seconds |
| Started | Oct 03 07:04:16 AM UTC 24 |
| Finished | Oct 03 07:04:26 AM UTC 24 |
| Peak memory | 177764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3953057478 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.3953057478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/9.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.736962181 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 1238950000 ps |
| CPU time | 2.27 seconds |
| Started | Oct 03 06:28:01 AM UTC 24 |
| Finished | Oct 03 06:28:16 AM UTC 24 |
| Peak memory | 177788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=736962181 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g al.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.736962181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/1.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.692754187 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 1548910000 ps |
| CPU time | 2.52 seconds |
| Started | Oct 03 06:28:05 AM UTC 24 |
| Finished | Oct 03 06:28:22 AM UTC 24 |
| Peak memory | 177724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=692754187 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g al.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.692754187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/10.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.3378769599 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 1307030000 ps |
| CPU time | 2.29 seconds |
| Started | Oct 03 06:28:05 AM UTC 24 |
| Finished | Oct 03 06:28:20 AM UTC 24 |
| Peak memory | 177760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3378769599 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.3378769599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/11.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.271511286 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 1438330000 ps |
| CPU time | 2.7 seconds |
| Started | Oct 03 06:28:05 AM UTC 24 |
| Finished | Oct 03 06:28:21 AM UTC 24 |
| Peak memory | 177728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=271511286 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g al.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.271511286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/12.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.306992642 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 1539950000 ps |
| CPU time | 2.44 seconds |
| Started | Oct 03 06:28:05 AM UTC 24 |
| Finished | Oct 03 06:28:22 AM UTC 24 |
| Peak memory | 177728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=306992642 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g al.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.306992642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/13.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.2169697865 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 1416210000 ps |
| CPU time | 2.39 seconds |
| Started | Oct 03 06:28:16 AM UTC 24 |
| Finished | Oct 03 06:28:32 AM UTC 24 |
| Peak memory | 177760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2169697865 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.2169697865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/14.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.574305682 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 1511410000 ps |
| CPU time | 2.62 seconds |
| Started | Oct 03 06:28:16 AM UTC 24 |
| Finished | Oct 03 06:28:33 AM UTC 24 |
| Peak memory | 177728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=574305682 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g al.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.574305682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/15.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.3626727716 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 1620270000 ps |
| CPU time | 2.49 seconds |
| Started | Oct 03 06:28:19 AM UTC 24 |
| Finished | Oct 03 06:28:36 AM UTC 24 |
| Peak memory | 177760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3626727716 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.3626727716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/16.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.842755507 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 1575230000 ps |
| CPU time | 2.66 seconds |
| Started | Oct 03 06:28:20 AM UTC 24 |
| Finished | Oct 03 06:28:37 AM UTC 24 |
| Peak memory | 177728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=842755507 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g al.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.842755507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/17.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.941205425 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 1576870000 ps |
| CPU time | 2.64 seconds |
| Started | Oct 03 06:28:20 AM UTC 24 |
| Finished | Oct 03 06:28:37 AM UTC 24 |
| Peak memory | 177728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=941205425 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g al.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.941205425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/18.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.2064166305 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 1517010000 ps |
| CPU time | 2.49 seconds |
| Started | Oct 03 06:28:20 AM UTC 24 |
| Finished | Oct 03 06:28:36 AM UTC 24 |
| Peak memory | 177760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2064166305 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.2064166305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/19.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.3021913172 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 1522990000 ps |
| CPU time | 2.62 seconds |
| Started | Oct 03 06:28:02 AM UTC 24 |
| Finished | Oct 03 06:28:18 AM UTC 24 |
| Peak memory | 177728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3021913172 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.3021913172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/2.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.1979927647 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 1548610000 ps |
| CPU time | 2.52 seconds |
| Started | Oct 03 06:28:21 AM UTC 24 |
| Finished | Oct 03 06:28:38 AM UTC 24 |
| Peak memory | 177760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1979927647 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.1979927647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/20.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.3128157362 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 1580810000 ps |
| CPU time | 2.56 seconds |
| Started | Oct 03 06:28:21 AM UTC 24 |
| Finished | Oct 03 06:28:38 AM UTC 24 |
| Peak memory | 177760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3128157362 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.3128157362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/21.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.2072745777 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 1180770000 ps |
| CPU time | 2.18 seconds |
| Started | Oct 03 06:28:21 AM UTC 24 |
| Finished | Oct 03 06:28:34 AM UTC 24 |
| Peak memory | 177760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2072745777 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.2072745777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/22.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.4289072092 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 1438770000 ps |
| CPU time | 2.43 seconds |
| Started | Oct 03 06:28:21 AM UTC 24 |
| Finished | Oct 03 06:28:37 AM UTC 24 |
| Peak memory | 177760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4289072092 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.4289072092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/23.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.4151691805 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 1420950000 ps |
| CPU time | 2.46 seconds |
| Started | Oct 03 06:28:22 AM UTC 24 |
| Finished | Oct 03 06:28:38 AM UTC 24 |
| Peak memory | 177760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4151691805 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.4151691805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/24.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.174208466 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 1336530000 ps |
| CPU time | 2.27 seconds |
| Started | Oct 03 06:28:22 AM UTC 24 |
| Finished | Oct 03 06:28:37 AM UTC 24 |
| Peak memory | 177728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=174208466 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g al.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.174208466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/25.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.1442832243 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 1306870000 ps |
| CPU time | 2.36 seconds |
| Started | Oct 03 06:28:23 AM UTC 24 |
| Finished | Oct 03 06:28:38 AM UTC 24 |
| Peak memory | 177760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1442832243 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.1442832243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/26.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.5385834 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 1554690000 ps |
| CPU time | 2.59 seconds |
| Started | Oct 03 06:28:23 AM UTC 24 |
| Finished | Oct 03 06:28:40 AM UTC 24 |
| Peak memory | 177760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5385834 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal .vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.5385834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/27.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.327554245 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 1445510000 ps |
| CPU time | 2.44 seconds |
| Started | Oct 03 06:28:27 AM UTC 24 |
| Finished | Oct 03 06:28:42 AM UTC 24 |
| Peak memory | 177728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=327554245 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g al.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.327554245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/28.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.2807661634 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 1334770000 ps |
| CPU time | 2.38 seconds |
| Started | Oct 03 06:28:29 AM UTC 24 |
| Finished | Oct 03 06:28:43 AM UTC 24 |
| Peak memory | 177760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2807661634 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.2807661634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/29.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.2294611031 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 1540850000 ps |
| CPU time | 2.59 seconds |
| Started | Oct 03 06:28:02 AM UTC 24 |
| Finished | Oct 03 06:28:19 AM UTC 24 |
| Peak memory | 177728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2294611031 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.2294611031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/3.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.1732290715 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 1439950000 ps |
| CPU time | 2.49 seconds |
| Started | Oct 03 06:28:32 AM UTC 24 |
| Finished | Oct 03 06:28:48 AM UTC 24 |
| Peak memory | 177760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1732290715 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.1732290715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/30.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.2645568295 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 1320030000 ps |
| CPU time | 2.32 seconds |
| Started | Oct 03 06:28:33 AM UTC 24 |
| Finished | Oct 03 06:28:48 AM UTC 24 |
| Peak memory | 177760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2645568295 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.2645568295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/31.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.3080859432 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 1435150000 ps |
| CPU time | 2.39 seconds |
| Started | Oct 03 06:28:36 AM UTC 24 |
| Finished | Oct 03 06:28:51 AM UTC 24 |
| Peak memory | 177760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3080859432 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.3080859432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/32.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.587635135 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 1511610000 ps |
| CPU time | 2.47 seconds |
| Started | Oct 03 06:28:37 AM UTC 24 |
| Finished | Oct 03 06:28:53 AM UTC 24 |
| Peak memory | 177728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=587635135 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g al.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.587635135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/33.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.627306447 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 1618970000 ps |
| CPU time | 2.5 seconds |
| Started | Oct 03 06:28:37 AM UTC 24 |
| Finished | Oct 03 06:28:54 AM UTC 24 |
| Peak memory | 177728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=627306447 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g al.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.627306447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/34.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.70014465 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 1354510000 ps |
| CPU time | 2.33 seconds |
| Started | Oct 03 06:28:38 AM UTC 24 |
| Finished | Oct 03 06:28:54 AM UTC 24 |
| Peak memory | 177728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=70014465 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ga l.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.70014465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/35.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.732454404 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 1390190000 ps |
| CPU time | 2.43 seconds |
| Started | Oct 03 06:28:38 AM UTC 24 |
| Finished | Oct 03 06:28:54 AM UTC 24 |
| Peak memory | 177728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=732454404 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g al.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.732454404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/36.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.1629168020 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 1399750000 ps |
| CPU time | 2.42 seconds |
| Started | Oct 03 06:28:38 AM UTC 24 |
| Finished | Oct 03 06:28:54 AM UTC 24 |
| Peak memory | 177760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1629168020 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.1629168020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/37.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.540642193 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 1483070000 ps |
| CPU time | 2.47 seconds |
| Started | Oct 03 06:28:38 AM UTC 24 |
| Finished | Oct 03 06:28:55 AM UTC 24 |
| Peak memory | 177728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=540642193 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g al.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.540642193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/38.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.1915342872 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 1297370000 ps |
| CPU time | 2.29 seconds |
| Started | Oct 03 06:28:39 AM UTC 24 |
| Finished | Oct 03 06:28:53 AM UTC 24 |
| Peak memory | 177760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1915342872 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.1915342872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/39.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.581760665 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 1497990000 ps |
| CPU time | 2.39 seconds |
| Started | Oct 03 06:28:03 AM UTC 24 |
| Finished | Oct 03 06:28:19 AM UTC 24 |
| Peak memory | 177724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=581760665 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g al.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.581760665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/4.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.882537062 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 1334950000 ps |
| CPU time | 2.38 seconds |
| Started | Oct 03 06:28:39 AM UTC 24 |
| Finished | Oct 03 06:28:54 AM UTC 24 |
| Peak memory | 177724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=882537062 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g al.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.882537062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/40.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.4011562650 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 1491850000 ps |
| CPU time | 2.49 seconds |
| Started | Oct 03 06:28:39 AM UTC 24 |
| Finished | Oct 03 06:28:55 AM UTC 24 |
| Peak memory | 177760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4011562650 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.4011562650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/41.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.3907367257 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 1415270000 ps |
| CPU time | 2.33 seconds |
| Started | Oct 03 06:28:39 AM UTC 24 |
| Finished | Oct 03 06:28:55 AM UTC 24 |
| Peak memory | 177760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3907367257 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.3907367257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/42.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.3274497241 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 1537690000 ps |
| CPU time | 2.49 seconds |
| Started | Oct 03 06:28:39 AM UTC 24 |
| Finished | Oct 03 06:28:56 AM UTC 24 |
| Peak memory | 177760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3274497241 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.3274497241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/43.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.1489893302 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 1181250000 ps |
| CPU time | 2.21 seconds |
| Started | Oct 03 06:28:41 AM UTC 24 |
| Finished | Oct 03 06:28:54 AM UTC 24 |
| Peak memory | 177760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1489893302 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.1489893302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/44.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.2583292668 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 1430470000 ps |
| CPU time | 2.32 seconds |
| Started | Oct 03 06:28:43 AM UTC 24 |
| Finished | Oct 03 06:28:58 AM UTC 24 |
| Peak memory | 177760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2583292668 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.2583292668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/45.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.1401877821 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 1520770000 ps |
| CPU time | 2.52 seconds |
| Started | Oct 03 06:28:44 AM UTC 24 |
| Finished | Oct 03 06:29:00 AM UTC 24 |
| Peak memory | 177760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401877821 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.1401877821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/46.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.926294278 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 1467030000 ps |
| CPU time | 2.39 seconds |
| Started | Oct 03 06:28:48 AM UTC 24 |
| Finished | Oct 03 06:29:03 AM UTC 24 |
| Peak memory | 177728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=926294278 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g al.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.926294278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/47.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.2268478600 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 1354050000 ps |
| CPU time | 2.16 seconds |
| Started | Oct 03 06:28:48 AM UTC 24 |
| Finished | Oct 03 06:29:02 AM UTC 24 |
| Peak memory | 177760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2268478600 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.2268478600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/48.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.4233975369 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 1588390000 ps |
| CPU time | 2.57 seconds |
| Started | Oct 03 06:28:52 AM UTC 24 |
| Finished | Oct 03 06:29:07 AM UTC 24 |
| Peak memory | 177760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4233975369 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.4233975369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/49.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.363503029 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 1484990000 ps |
| CPU time | 2.24 seconds |
| Started | Oct 03 06:28:03 AM UTC 24 |
| Finished | Oct 03 06:28:19 AM UTC 24 |
| Peak memory | 177724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=363503029 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g al.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.363503029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/5.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.673761770 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 1272330000 ps |
| CPU time | 2.36 seconds |
| Started | Oct 03 06:28:03 AM UTC 24 |
| Finished | Oct 03 06:28:17 AM UTC 24 |
| Peak memory | 177724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=673761770 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g al.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.673761770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/6.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.1379526591 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 1546810000 ps |
| CPU time | 2.63 seconds |
| Started | Oct 03 06:28:04 AM UTC 24 |
| Finished | Oct 03 06:28:21 AM UTC 24 |
| Peak memory | 177728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1379526591 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.1379526591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/7.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.1249213263 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 1412930000 ps |
| CPU time | 2.31 seconds |
| Started | Oct 03 06:28:04 AM UTC 24 |
| Finished | Oct 03 06:28:20 AM UTC 24 |
| Peak memory | 177728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1249213263 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.1249213263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/8.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.3829184864 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 1345910000 ps |
| CPU time | 2.4 seconds |
| Started | Oct 03 06:28:04 AM UTC 24 |
| Finished | Oct 03 06:28:19 AM UTC 24 |
| Peak memory | 177728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3829184864 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.3829184864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_lfsr-sim-vcs/9.prim_lfsr_gal_smoke/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |