Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.31 100.00 96.55 100.00 100.00 95.00


Total tests in report: 200
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
87.31 87.31 100.00 100.00 96.55 96.55 100.00 100.00 100.00 100.00 40.00 40.00 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.384499301
95.31 8.00 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 80.00 40.00 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.3509063648
98.31 3.00 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 95.00 15.00 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.492077645

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.909942635
/workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.178329753
/workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.2984858666
/workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.2088444988
/workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.4155664710
/workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.424305410
/workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.2028625187
/workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.1571566785
/workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.1559714008
/workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.2832306241
/workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2006770787
/workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.1067744964
/workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.2405595682
/workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.3703705634
/workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.2230627131
/workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.3159352861
/workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.999704855
/workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.409792566
/workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1560493699
/workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.976157636
/workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.4101412076
/workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.3849978760
/workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.3296113387
/workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3576269712
/workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.3188339967
/workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.702333626
/workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.3787220931
/workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.3598467663
/workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.1508063954
/workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.3738589115
/workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.945750827
/workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.3856452343
/workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.23084942
/workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.2468544050
/workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.2901682762
/workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.652341284
/workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.2697269546
/workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.3952890143
/workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.2495769243
/workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.3641083023
/workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.2954908416
/workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.2891179286
/workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.1200957233
/workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.2049059523
/workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.892385987
/workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.3181997916
/workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.297398082
/workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1171509490
/workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.967505486
/workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.941324646
/workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.4007533994
/workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.3073181379
/workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.810164590
/workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.2707321260
/workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.2018172458
/workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.2851862291
/workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.3894517130
/workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.3548047657
/workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.1057711410
/workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.269553281
/workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.3845868640
/workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.3047402034
/workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.2822592278
/workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.314234130
/workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.4120539458
/workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.2955957734
/workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.76550692
/workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.3957752233
/workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.284902524
/workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.3856441415
/workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.923190390
/workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.1833987962
/workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.730440048
/workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.2416931205
/workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.3056255592
/workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.4102570477
/workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.2837362406
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/workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3140167138
/workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.388067975
/workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.3155320780
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/workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.2935657819
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Total test records in report: 200
tests.html | tests1.html | tests2.html | tests3.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.2696590694 Oct 09 02:32:53 PM UTC 24 Oct 09 02:33:05 PM UTC 24 1185710000 ps
T2 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.2481205678 Oct 09 02:32:53 PM UTC 24 Oct 09 02:33:07 PM UTC 24 1354890000 ps
T3 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.685391981 Oct 09 02:32:52 PM UTC 24 Oct 09 02:33:07 PM UTC 24 1392950000 ps
T7 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.505899111 Oct 09 02:32:53 PM UTC 24 Oct 09 02:33:07 PM UTC 24 1376490000 ps
T8 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.384499301 Oct 09 02:32:52 PM UTC 24 Oct 09 02:33:08 PM UTC 24 1521370000 ps
T9 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.1544099289 Oct 09 02:32:53 PM UTC 24 Oct 09 02:33:08 PM UTC 24 1501830000 ps
T10 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.1017526263 Oct 09 02:32:53 PM UTC 24 Oct 09 02:33:08 PM UTC 24 1464750000 ps
T11 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.316754311 Oct 09 02:32:53 PM UTC 24 Oct 09 02:33:08 PM UTC 24 1510450000 ps
T12 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.2505671907 Oct 09 02:32:53 PM UTC 24 Oct 09 02:33:08 PM UTC 24 1503810000 ps
T13 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.4127785792 Oct 09 02:32:53 PM UTC 24 Oct 09 02:33:08 PM UTC 24 1568490000 ps
T31 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.2956256108 Oct 09 02:32:56 PM UTC 24 Oct 09 02:33:10 PM UTC 24 1451590000 ps
T32 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.629540926 Oct 09 02:32:58 PM UTC 24 Oct 09 02:33:13 PM UTC 24 1564890000 ps
T33 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.648036822 Oct 09 02:33:03 PM UTC 24 Oct 09 02:33:18 PM UTC 24 1553090000 ps
T34 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.1262988359 Oct 09 02:33:07 PM UTC 24 Oct 09 02:33:22 PM UTC 24 1511550000 ps
T35 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.1727118499 Oct 09 02:33:09 PM UTC 24 Oct 09 02:33:22 PM UTC 24 1263270000 ps
T36 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.937366924 Oct 09 02:33:09 PM UTC 24 Oct 09 02:33:22 PM UTC 24 1316590000 ps
T37 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.1613010984 Oct 09 02:33:09 PM UTC 24 Oct 09 02:33:23 PM UTC 24 1359950000 ps
T38 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.3718714999 Oct 09 02:33:09 PM UTC 24 Oct 09 02:33:23 PM UTC 24 1438770000 ps
T39 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.2673016097 Oct 09 02:33:09 PM UTC 24 Oct 09 02:33:24 PM UTC 24 1508870000 ps
T40 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.78810460 Oct 09 02:33:09 PM UTC 24 Oct 09 02:33:24 PM UTC 24 1545430000 ps
T41 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.3483036517 Oct 09 02:33:09 PM UTC 24 Oct 09 02:33:24 PM UTC 24 1534810000 ps
T42 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.1231643038 Oct 09 02:33:09 PM UTC 24 Oct 09 02:33:25 PM UTC 24 1592430000 ps
T43 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.3416481323 Oct 09 02:33:10 PM UTC 24 Oct 09 02:33:25 PM UTC 24 1575690000 ps
T44 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.344943178 Oct 09 02:33:12 PM UTC 24 Oct 09 02:33:26 PM UTC 24 1502870000 ps
T45 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.1034426488 Oct 09 02:33:15 PM UTC 24 Oct 09 02:33:29 PM UTC 24 1473390000 ps
T46 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.1568453986 Oct 09 02:33:19 PM UTC 24 Oct 09 02:33:33 PM UTC 24 1458170000 ps
T47 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.830361022 Oct 09 02:33:19 PM UTC 24 Oct 09 02:33:34 PM UTC 24 1483490000 ps
T48 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.3750496434 Oct 09 02:33:20 PM UTC 24 Oct 09 02:33:35 PM UTC 24 1489190000 ps
T49 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.3789349218 Oct 09 02:33:22 PM UTC 24 Oct 09 02:33:35 PM UTC 24 1323150000 ps
T50 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.3965968342 Oct 09 02:33:24 PM UTC 24 Oct 09 02:33:37 PM UTC 24 1315170000 ps
T51 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.3238393214 Oct 09 02:33:22 PM UTC 24 Oct 09 02:33:37 PM UTC 24 1528110000 ps
T52 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.1298797818 Oct 09 02:33:25 PM UTC 24 Oct 09 02:33:38 PM UTC 24 1259430000 ps
T53 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.2050512814 Oct 09 02:33:25 PM UTC 24 Oct 09 02:33:38 PM UTC 24 1353890000 ps
T54 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.1454337698 Oct 09 02:33:24 PM UTC 24 Oct 09 02:33:39 PM UTC 24 1530050000 ps
T55 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.2378637759 Oct 09 02:33:25 PM UTC 24 Oct 09 02:33:39 PM UTC 24 1438810000 ps
T56 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.740502541 Oct 09 02:33:26 PM UTC 24 Oct 09 02:33:40 PM UTC 24 1448710000 ps
T57 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.2013748464 Oct 09 02:33:27 PM UTC 24 Oct 09 02:33:41 PM UTC 24 1323210000 ps
T58 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.1662926519 Oct 09 02:33:25 PM UTC 24 Oct 09 02:33:41 PM UTC 24 1593970000 ps
T59 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.874381028 Oct 09 02:33:26 PM UTC 24 Oct 09 02:33:41 PM UTC 24 1518870000 ps
T60 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.345856898 Oct 09 02:33:29 PM UTC 24 Oct 09 02:33:44 PM UTC 24 1491690000 ps
T61 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.1775761628 Oct 09 02:33:34 PM UTC 24 Oct 09 02:33:49 PM UTC 24 1475530000 ps
T62 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.2693540427 Oct 09 02:33:34 PM UTC 24 Oct 09 02:33:50 PM UTC 24 1584410000 ps
T63 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.1354389962 Oct 09 02:33:36 PM UTC 24 Oct 09 02:33:50 PM UTC 24 1520970000 ps
T64 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.2384418090 Oct 09 02:33:37 PM UTC 24 Oct 09 02:33:52 PM UTC 24 1523150000 ps
T65 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.1864979620 Oct 09 02:33:38 PM UTC 24 Oct 09 02:33:52 PM UTC 24 1432550000 ps
T66 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.438386577 Oct 09 02:33:38 PM UTC 24 Oct 09 02:33:53 PM UTC 24 1561670000 ps
T67 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.2437966229 Oct 09 02:33:40 PM UTC 24 Oct 09 02:33:54 PM UTC 24 1329910000 ps
T68 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.3707463084 Oct 09 02:33:39 PM UTC 24 Oct 09 02:33:54 PM UTC 24 1514230000 ps
T69 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.1099188629 Oct 09 02:33:39 PM UTC 24 Oct 09 02:33:55 PM UTC 24 1588450000 ps
T70 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.49962062 Oct 09 02:33:40 PM UTC 24 Oct 09 02:33:55 PM UTC 24 1475770000 ps
T14 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.941324646 Oct 09 06:20:43 PM UTC 24 Oct 09 06:57:51 PM UTC 24 336346610000 ps
T15 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.2935657819 Oct 09 06:20:44 PM UTC 24 Oct 09 06:57:52 PM UTC 24 336536310000 ps
T16 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.1833987962 Oct 09 06:20:43 PM UTC 24 Oct 09 06:57:53 PM UTC 24 336531410000 ps
T17 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.2018172458 Oct 09 06:20:46 PM UTC 24 Oct 09 06:57:54 PM UTC 24 336668070000 ps
T18 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.3073181379 Oct 09 06:20:44 PM UTC 24 Oct 09 06:57:54 PM UTC 24 337002170000 ps
T19 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.2707321260 Oct 09 06:20:45 PM UTC 24 Oct 09 06:57:55 PM UTC 24 336370730000 ps
T20 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.1041977327 Oct 09 06:20:43 PM UTC 24 Oct 09 06:57:55 PM UTC 24 336613290000 ps
T21 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.512476439 Oct 09 06:20:44 PM UTC 24 Oct 09 06:57:56 PM UTC 24 337090950000 ps
T22 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.2907242266 Oct 09 06:20:44 PM UTC 24 Oct 09 06:57:56 PM UTC 24 336574390000 ps
T23 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.3509063648 Oct 09 06:20:43 PM UTC 24 Oct 09 06:57:56 PM UTC 24 336659050000 ps
T71 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.3845868640 Oct 09 06:20:43 PM UTC 24 Oct 09 06:57:57 PM UTC 24 336837350000 ps
T72 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.1682014193 Oct 09 06:20:43 PM UTC 24 Oct 09 06:57:57 PM UTC 24 336597430000 ps
T73 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.3155320780 Oct 09 06:20:43 PM UTC 24 Oct 09 06:57:57 PM UTC 24 336633930000 ps
T74 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.4007533994 Oct 09 06:20:44 PM UTC 24 Oct 09 06:57:58 PM UTC 24 336324250000 ps
T75 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.810164590 Oct 09 06:20:44 PM UTC 24 Oct 09 06:57:58 PM UTC 24 336565130000 ps
T76 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.2851862291 Oct 09 06:20:46 PM UTC 24 Oct 09 06:57:59 PM UTC 24 336707490000 ps
T77 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.3548047657 Oct 09 06:20:53 PM UTC 24 Oct 09 06:58:00 PM UTC 24 336374150000 ps
T78 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.3894517130 Oct 09 06:20:49 PM UTC 24 Oct 09 06:58:01 PM UTC 24 337040050000 ps
T79 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.1057711410 Oct 09 06:21:00 PM UTC 24 Oct 09 06:58:11 PM UTC 24 336978770000 ps
T80 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.269553281 Oct 09 06:22:16 PM UTC 24 Oct 09 06:58:54 PM UTC 24 336534590000 ps
T81 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.3047402034 Oct 09 06:22:18 PM UTC 24 Oct 09 06:58:59 PM UTC 24 337056350000 ps
T82 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.2822592278 Oct 09 06:23:10 PM UTC 24 Oct 09 06:59:28 PM UTC 24 337179690000 ps
T83 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.314234130 Oct 09 06:23:11 PM UTC 24 Oct 09 06:59:31 PM UTC 24 336827070000 ps
T84 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.4120539458 Oct 09 06:23:45 PM UTC 24 Oct 09 06:59:51 PM UTC 24 337033310000 ps
T85 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.2955957734 Oct 09 06:23:56 PM UTC 24 Oct 09 07:00:00 PM UTC 24 336570090000 ps
T86 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.76550692 Oct 09 06:24:05 PM UTC 24 Oct 09 07:00:06 PM UTC 24 336699070000 ps
T87 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.3957752233 Oct 09 06:24:08 PM UTC 24 Oct 09 07:00:06 PM UTC 24 336398370000 ps
T88 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.284902524 Oct 09 06:24:16 PM UTC 24 Oct 09 07:00:15 PM UTC 24 336930790000 ps
T89 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.3856441415 Oct 09 06:25:02 PM UTC 24 Oct 09 07:00:47 PM UTC 24 336638230000 ps
T90 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.923190390 Oct 09 06:25:23 PM UTC 24 Oct 09 07:01:01 PM UTC 24 336438050000 ps
T91 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.730440048 Oct 09 06:25:52 PM UTC 24 Oct 09 07:01:24 PM UTC 24 336576990000 ps
T92 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.2416931205 Oct 09 06:25:58 PM UTC 24 Oct 09 07:01:30 PM UTC 24 336760710000 ps
T93 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.3056255592 Oct 09 06:26:05 PM UTC 24 Oct 09 07:01:33 PM UTC 24 337063470000 ps
T94 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.4102570477 Oct 09 06:26:25 PM UTC 24 Oct 09 07:01:49 PM UTC 24 336745650000 ps
T95 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.2837362406 Oct 09 06:26:43 PM UTC 24 Oct 09 07:02:06 PM UTC 24 336584850000 ps
T96 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.363723044 Oct 09 06:26:55 PM UTC 24 Oct 09 07:02:15 PM UTC 24 336502530000 ps
T97 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.4145889166 Oct 09 06:27:03 PM UTC 24 Oct 09 07:02:21 PM UTC 24 336320830000 ps
T98 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.1743706241 Oct 09 06:27:12 PM UTC 24 Oct 09 07:02:33 PM UTC 24 337014330000 ps
T99 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.388067975 Oct 09 06:27:36 PM UTC 24 Oct 09 07:02:47 PM UTC 24 336384930000 ps
T100 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3140167138 Oct 09 06:27:34 PM UTC 24 Oct 09 07:02:50 PM UTC 24 336747370000 ps
T101 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.2815067215 Oct 09 06:27:59 PM UTC 24 Oct 09 07:03:09 PM UTC 24 336554090000 ps
T102 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.1473650511 Oct 09 06:28:32 PM UTC 24 Oct 09 07:03:35 PM UTC 24 336529170000 ps
T103 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.352183682 Oct 09 06:28:27 PM UTC 24 Oct 09 07:03:36 PM UTC 24 336987970000 ps
T104 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.3407660705 Oct 09 06:28:45 PM UTC 24 Oct 09 07:03:55 PM UTC 24 337024030000 ps
T105 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.1280075212 Oct 09 06:29:19 PM UTC 24 Oct 09 07:04:25 PM UTC 24 336993290000 ps
T106 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.3711957388 Oct 09 06:29:41 PM UTC 24 Oct 09 07:04:42 PM UTC 24 336662370000 ps
T107 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.2995913193 Oct 09 06:32:23 PM UTC 24 Oct 09 07:07:08 PM UTC 24 336826690000 ps
T108 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.3400908104 Oct 09 06:33:14 PM UTC 24 Oct 09 07:08:00 PM UTC 24 337020370000 ps
T109 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.859708408 Oct 09 06:33:46 PM UTC 24 Oct 09 07:08:30 PM UTC 24 336426990000 ps
T110 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.1024539014 Oct 09 06:33:53 PM UTC 24 Oct 09 07:08:37 PM UTC 24 336373130000 ps
T4 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.492077645 Oct 09 06:34:06 PM UTC 24 Oct 09 07:08:57 PM UTC 24 337077970000 ps
T5 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.909942635 Oct 09 06:34:39 PM UTC 24 Oct 09 07:09:29 PM UTC 24 336507070000 ps
T6 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.1067744964 Oct 09 06:35:05 PM UTC 24 Oct 09 07:09:53 PM UTC 24 336652170000 ps
T24 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.3296113387 Oct 09 06:36:26 PM UTC 24 Oct 09 07:11:24 PM UTC 24 336864090000 ps
T25 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.2468544050 Oct 09 06:37:08 PM UTC 24 Oct 09 07:12:10 PM UTC 24 337081210000 ps
T26 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.892385987 Oct 09 06:37:39 PM UTC 24 Oct 09 07:12:41 PM UTC 24 336764350000 ps
T27 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.3181997916 Oct 09 06:38:12 PM UTC 24 Oct 09 07:13:20 PM UTC 24 336698650000 ps
T28 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.297398082 Oct 09 06:38:26 PM UTC 24 Oct 09 07:13:32 PM UTC 24 336971710000 ps
T29 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1171509490 Oct 09 06:39:39 PM UTC 24 Oct 09 07:15:09 PM UTC 24 336721790000 ps
T30 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.967505486 Oct 09 06:40:49 PM UTC 24 Oct 09 07:16:35 PM UTC 24 336884070000 ps
T111 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.178329753 Oct 09 06:41:06 PM UTC 24 Oct 09 07:16:51 PM UTC 24 336550090000 ps
T112 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.2984858666 Oct 09 06:42:09 PM UTC 24 Oct 09 07:17:59 PM UTC 24 336523950000 ps
T113 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.2088444988 Oct 09 06:47:57 PM UTC 24 Oct 09 07:24:47 PM UTC 24 336903610000 ps
T114 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.4155664710 Oct 09 06:57:52 PM UTC 24 Oct 09 07:36:22 PM UTC 24 336549910000 ps
T115 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.424305410 Oct 09 06:57:54 PM UTC 24 Oct 09 07:36:25 PM UTC 24 336904150000 ps
T116 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.1571566785 Oct 09 06:57:55 PM UTC 24 Oct 09 07:36:25 PM UTC 24 336983350000 ps
T117 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.1559714008 Oct 09 06:57:55 PM UTC 24 Oct 09 07:36:25 PM UTC 24 336745210000 ps
T118 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.2028625187 Oct 09 06:57:54 PM UTC 24 Oct 09 07:36:26 PM UTC 24 337084970000 ps
T119 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.3159352861 Oct 09 06:57:57 PM UTC 24 Oct 09 07:36:26 PM UTC 24 336752090000 ps
T120 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.3703705634 Oct 09 06:57:57 PM UTC 24 Oct 09 07:36:27 PM UTC 24 336448610000 ps
T121 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.999704855 Oct 09 06:57:58 PM UTC 24 Oct 09 07:36:27 PM UTC 24 336375410000 ps
T122 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.2832306241 Oct 09 06:57:56 PM UTC 24 Oct 09 07:36:34 PM UTC 24 336615150000 ps
T123 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.2405595682 Oct 09 06:57:57 PM UTC 24 Oct 09 07:36:36 PM UTC 24 336489190000 ps
T124 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.3849978760 Oct 09 06:58:01 PM UTC 24 Oct 09 07:36:37 PM UTC 24 337107190000 ps
T125 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.409792566 Oct 09 06:57:58 PM UTC 24 Oct 09 07:36:38 PM UTC 24 336610030000 ps
T126 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2006770787 Oct 09 06:57:56 PM UTC 24 Oct 09 07:36:38 PM UTC 24 337025890000 ps
T127 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.2230627131 Oct 09 06:57:57 PM UTC 24 Oct 09 07:36:38 PM UTC 24 337069910000 ps
T128 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1560493699 Oct 09 06:57:58 PM UTC 24 Oct 09 07:36:40 PM UTC 24 337046550000 ps
T129 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.976157636 Oct 09 06:58:00 PM UTC 24 Oct 09 07:36:44 PM UTC 24 337061350000 ps
T130 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3576269712 Oct 09 06:58:02 PM UTC 24 Oct 09 07:36:47 PM UTC 24 337022550000 ps
T131 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.4101412076 Oct 09 06:58:01 PM UTC 24 Oct 09 07:36:47 PM UTC 24 337076890000 ps
T132 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.3188339967 Oct 09 06:58:12 PM UTC 24 Oct 09 07:37:01 PM UTC 24 336811930000 ps
T133 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.3787220931 Oct 09 06:59:00 PM UTC 24 Oct 09 07:37:58 PM UTC 24 336356810000 ps
T134 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.702333626 Oct 09 06:58:55 PM UTC 24 Oct 09 07:38:01 PM UTC 24 336608330000 ps
T135 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.1508063954 Oct 09 06:59:32 PM UTC 24 Oct 09 07:38:44 PM UTC 24 336412310000 ps
T136 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.3598467663 Oct 09 06:59:29 PM UTC 24 Oct 09 07:38:51 PM UTC 24 336672010000 ps
T137 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.3738589115 Oct 09 06:59:51 PM UTC 24 Oct 09 07:39:27 PM UTC 24 337096470000 ps
T138 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.945750827 Oct 09 07:00:00 PM UTC 24 Oct 09 07:39:35 PM UTC 24 336700730000 ps
T139 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.3856452343 Oct 09 07:00:09 PM UTC 24 Oct 09 07:39:40 PM UTC 24 336653670000 ps
T140 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.23084942 Oct 09 07:00:10 PM UTC 24 Oct 09 07:39:45 PM UTC 24 337139750000 ps
T141 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.2901682762 Oct 09 07:00:16 PM UTC 24 Oct 09 07:39:48 PM UTC 24 336367890000 ps
T142 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.652341284 Oct 09 07:00:48 PM UTC 24 Oct 09 07:40:28 PM UTC 24 336344590000 ps
T143 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.2697269546 Oct 09 07:01:02 PM UTC 24 Oct 09 07:40:50 PM UTC 24 336486350000 ps
T144 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.2495769243 Oct 09 07:01:31 PM UTC 24 Oct 09 07:41:32 PM UTC 24 336659690000 ps
T145 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.3952890143 Oct 09 07:01:25 PM UTC 24 Oct 09 07:41:33 PM UTC 24 336499170000 ps
T146 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.3641083023 Oct 09 07:01:34 PM UTC 24 Oct 09 07:41:46 PM UTC 24 336485550000 ps
T147 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.2954908416 Oct 09 07:01:50 PM UTC 24 Oct 09 07:42:05 PM UTC 24 336638150000 ps
T148 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.2891179286 Oct 09 07:02:06 PM UTC 24 Oct 09 07:42:34 PM UTC 24 336709070000 ps
T149 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.1200957233 Oct 09 07:02:15 PM UTC 24 Oct 09 07:42:45 PM UTC 24 336618730000 ps
T150 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.2049059523 Oct 09 07:02:22 PM UTC 24 Oct 09 07:42:55 PM UTC 24 336808770000 ps
T151 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.3077308977 Oct 09 07:02:35 PM UTC 24 Oct 09 07:02:44 PM UTC 24 1251450000 ps
T152 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.188443866 Oct 09 07:02:48 PM UTC 24 Oct 09 07:02:59 PM UTC 24 1484650000 ps
T153 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.2099670181 Oct 09 07:02:49 PM UTC 24 Oct 09 07:02:59 PM UTC 24 1354910000 ps
T154 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.1337568365 Oct 09 07:02:51 PM UTC 24 Oct 09 07:03:02 PM UTC 24 1489270000 ps
T155 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.2034989933 Oct 09 07:02:59 PM UTC 24 Oct 09 07:03:10 PM UTC 24 1523770000 ps
T156 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.4268807947 Oct 09 07:03:01 PM UTC 24 Oct 09 07:03:12 PM UTC 24 1499190000 ps
T157 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.2222179314 Oct 09 07:03:03 PM UTC 24 Oct 09 07:03:15 PM UTC 24 1533810000 ps
T158 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.3709717813 Oct 09 07:03:12 PM UTC 24 Oct 09 07:03:23 PM UTC 24 1581150000 ps
T159 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.2853528714 Oct 09 07:03:12 PM UTC 24 Oct 09 07:03:23 PM UTC 24 1628870000 ps
T160 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.724624983 Oct 09 07:03:14 PM UTC 24 Oct 09 07:03:24 PM UTC 24 1504450000 ps
T161 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.3068899615 Oct 09 07:03:16 PM UTC 24 Oct 09 07:03:26 PM UTC 24 1473390000 ps
T162 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.1288899230 Oct 09 07:03:24 PM UTC 24 Oct 09 07:03:34 PM UTC 24 1450010000 ps
T163 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.12865163 Oct 09 07:03:24 PM UTC 24 Oct 09 07:03:34 PM UTC 24 1463530000 ps
T164 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.714682020 Oct 09 07:03:26 PM UTC 24 Oct 09 07:03:37 PM UTC 24 1506950000 ps
T165 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.3018843726 Oct 09 07:03:28 PM UTC 24 Oct 09 07:03:38 PM UTC 24 1377990000 ps
T166 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.578850513 Oct 09 07:03:36 PM UTC 24 Oct 09 07:03:46 PM UTC 24 1427690000 ps
T167 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.2245091746 Oct 09 07:03:36 PM UTC 24 Oct 09 07:03:46 PM UTC 24 1433850000 ps
T168 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.660862486 Oct 09 07:03:36 PM UTC 24 Oct 09 07:03:47 PM UTC 24 1561590000 ps
T169 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.1205661506 Oct 09 07:03:38 PM UTC 24 Oct 09 07:03:48 PM UTC 24 1369290000 ps
T170 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.2714307506 Oct 09 07:03:38 PM UTC 24 Oct 09 07:03:49 PM UTC 24 1460850000 ps
T171 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.3351521593 Oct 09 07:03:40 PM UTC 24 Oct 09 07:03:52 PM UTC 24 1549650000 ps
T172 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.718784948 Oct 09 07:03:48 PM UTC 24 Oct 09 07:03:59 PM UTC 24 1377470000 ps
T173 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.982651073 Oct 09 07:03:48 PM UTC 24 Oct 09 07:03:59 PM UTC 24 1476450000 ps
T174 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.362701048 Oct 09 07:03:49 PM UTC 24 Oct 09 07:04:00 PM UTC 24 1595330000 ps
T175 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.1818968915 Oct 09 07:03:51 PM UTC 24 Oct 09 07:04:01 PM UTC 24 1365990000 ps
T176 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.1972344241 Oct 09 07:03:51 PM UTC 24 Oct 09 07:04:01 PM UTC 24 1469610000 ps
T177 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.450217744 Oct 09 07:03:54 PM UTC 24 Oct 09 07:04:04 PM UTC 24 1432950000 ps
T178 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.2448312585 Oct 09 07:03:56 PM UTC 24 Oct 09 07:04:06 PM UTC 24 1425170000 ps
T179 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.1478362547 Oct 09 07:04:00 PM UTC 24 Oct 09 07:04:11 PM UTC 24 1491070000 ps
T180 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.3580428952 Oct 09 07:04:00 PM UTC 24 Oct 09 07:04:11 PM UTC 24 1568910000 ps
T181 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.2687992439 Oct 09 07:04:02 PM UTC 24 Oct 09 07:04:12 PM UTC 24 1332650000 ps
T182 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.3675499227 Oct 09 07:04:02 PM UTC 24 Oct 09 07:04:13 PM UTC 24 1441970000 ps
T183 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.2866321404 Oct 09 07:04:03 PM UTC 24 Oct 09 07:04:13 PM UTC 24 1296050000 ps
T184 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.3190180364 Oct 09 07:04:02 PM UTC 24 Oct 09 07:04:13 PM UTC 24 1557990000 ps
T185 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.1719046845 Oct 09 07:04:05 PM UTC 24 Oct 09 07:04:16 PM UTC 24 1509450000 ps
T186 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.1556955090 Oct 09 07:04:07 PM UTC 24 Oct 09 07:04:19 PM UTC 24 1556810000 ps
T187 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.3790293661 Oct 09 07:04:11 PM UTC 24 Oct 09 07:04:22 PM UTC 24 1501470000 ps
T188 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.1576887033 Oct 09 07:04:13 PM UTC 24 Oct 09 07:04:22 PM UTC 24 1299970000 ps
T189 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1941363951 Oct 09 07:04:13 PM UTC 24 Oct 09 07:04:23 PM UTC 24 1392610000 ps
T190 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.2237058466 Oct 09 07:04:14 PM UTC 24 Oct 09 07:04:24 PM UTC 24 1461130000 ps
T191 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.4132617304 Oct 09 07:04:14 PM UTC 24 Oct 09 07:04:24 PM UTC 24 1492090000 ps
T192 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.1660193553 Oct 09 07:04:14 PM UTC 24 Oct 09 07:04:24 PM UTC 24 1512070000 ps
T193 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.1944419528 Oct 09 07:04:17 PM UTC 24 Oct 09 07:04:27 PM UTC 24 1359630000 ps
T194 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.219059225 Oct 09 07:04:20 PM UTC 24 Oct 09 07:04:31 PM UTC 24 1505790000 ps
T195 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.3781165480 Oct 09 07:04:23 PM UTC 24 Oct 09 07:04:34 PM UTC 24 1463090000 ps
T196 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.1510173291 Oct 09 07:04:23 PM UTC 24 Oct 09 07:04:34 PM UTC 24 1507490000 ps
T197 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.1106989872 Oct 09 07:04:23 PM UTC 24 Oct 09 07:04:35 PM UTC 24 1555850000 ps
T198 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.2216099327 Oct 09 07:04:25 PM UTC 24 Oct 09 07:04:36 PM UTC 24 1457950000 ps
T199 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.3097501804 Oct 09 07:04:25 PM UTC 24 Oct 09 07:04:36 PM UTC 24 1464990000 ps
T200 /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.2807356867 Oct 09 07:04:25 PM UTC 24 Oct 09 07:04:37 PM UTC 24 1515410000 ps

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.384499301
Short name T8
Test name
Test status
Simulation time 1521370000 ps
CPU time 2.52 seconds
Started Oct 09 02:32:52 PM UTC 24
Finished Oct 09 02:33:08 PM UTC 24
Peak memory 177732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=384499301 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g
al.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.384499301
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/0.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.3509063648
Short name T23
Test name
Test status
Simulation time 336659050000 ps
CPU time 276.78 seconds
Started Oct 09 06:20:43 PM UTC 24
Finished Oct 09 06:57:56 PM UTC 24
Peak memory 174984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3509063648 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.3509063648
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/0.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.492077645
Short name T4
Test name
Test status
Simulation time 337077970000 ps
CPU time 266.32 seconds
Started Oct 09 06:34:06 PM UTC 24
Finished Oct 09 07:08:57 PM UTC 24
Peak memory 176592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492077645 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.492077645
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/0.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.909942635
Short name T5
Test name
Test status
Simulation time 336507070000 ps
CPU time 263.31 seconds
Started Oct 09 06:34:39 PM UTC 24
Finished Oct 09 07:09:29 PM UTC 24
Peak memory 175020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=909942635 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.909942635
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/1.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.178329753
Short name T111
Test name
Test status
Simulation time 336550090000 ps
CPU time 263.42 seconds
Started Oct 09 06:41:06 PM UTC 24
Finished Oct 09 07:16:51 PM UTC 24
Peak memory 174996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=178329753 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.178329753
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/10.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.2984858666
Short name T112
Test name
Test status
Simulation time 336523950000 ps
CPU time 256.89 seconds
Started Oct 09 06:42:09 PM UTC 24
Finished Oct 09 07:17:59 PM UTC 24
Peak memory 176536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2984858666 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.2984858666
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/11.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.2088444988
Short name T113
Test name
Test status
Simulation time 336903610000 ps
CPU time 258.98 seconds
Started Oct 09 06:47:57 PM UTC 24
Finished Oct 09 07:24:47 PM UTC 24
Peak memory 174996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2088444988 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.2088444988
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/12.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.4155664710
Short name T114
Test name
Test status
Simulation time 336549910000 ps
CPU time 266.34 seconds
Started Oct 09 06:57:52 PM UTC 24
Finished Oct 09 07:36:22 PM UTC 24
Peak memory 174996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4155664710 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.4155664710
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/13.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.424305410
Short name T115
Test name
Test status
Simulation time 336904150000 ps
CPU time 258.55 seconds
Started Oct 09 06:57:54 PM UTC 24
Finished Oct 09 07:36:25 PM UTC 24
Peak memory 176536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=424305410 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.424305410
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/14.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.2028625187
Short name T118
Test name
Test status
Simulation time 337084970000 ps
CPU time 258.53 seconds
Started Oct 09 06:57:54 PM UTC 24
Finished Oct 09 07:36:26 PM UTC 24
Peak memory 176536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2028625187 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.2028625187
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/15.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.1571566785
Short name T116
Test name
Test status
Simulation time 336983350000 ps
CPU time 256.94 seconds
Started Oct 09 06:57:55 PM UTC 24
Finished Oct 09 07:36:25 PM UTC 24
Peak memory 174992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571566785 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.1571566785
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/16.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.1559714008
Short name T117
Test name
Test status
Simulation time 336745210000 ps
CPU time 258.06 seconds
Started Oct 09 06:57:55 PM UTC 24
Finished Oct 09 07:36:25 PM UTC 24
Peak memory 174996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1559714008 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.1559714008
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/17.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.2832306241
Short name T122
Test name
Test status
Simulation time 336615150000 ps
CPU time 272 seconds
Started Oct 09 06:57:56 PM UTC 24
Finished Oct 09 07:36:34 PM UTC 24
Peak memory 174996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2832306241 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.2832306241
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/18.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2006770787
Short name T126
Test name
Test status
Simulation time 337025890000 ps
CPU time 273.28 seconds
Started Oct 09 06:57:56 PM UTC 24
Finished Oct 09 07:36:38 PM UTC 24
Peak memory 174996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2006770787 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.2006770787
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/19.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.1067744964
Short name T6
Test name
Test status
Simulation time 336652170000 ps
CPU time 254.13 seconds
Started Oct 09 06:35:05 PM UTC 24
Finished Oct 09 07:09:53 PM UTC 24
Peak memory 176524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1067744964 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.1067744964
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/2.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.2405595682
Short name T123
Test name
Test status
Simulation time 336489190000 ps
CPU time 274.72 seconds
Started Oct 09 06:57:57 PM UTC 24
Finished Oct 09 07:36:36 PM UTC 24
Peak memory 176532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2405595682 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.2405595682
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/20.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.3703705634
Short name T120
Test name
Test status
Simulation time 336448610000 ps
CPU time 263.61 seconds
Started Oct 09 06:57:57 PM UTC 24
Finished Oct 09 07:36:27 PM UTC 24
Peak memory 174996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3703705634 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.3703705634
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/21.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.2230627131
Short name T127
Test name
Test status
Simulation time 337069910000 ps
CPU time 271.73 seconds
Started Oct 09 06:57:57 PM UTC 24
Finished Oct 09 07:36:38 PM UTC 24
Peak memory 174996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2230627131 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.2230627131
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/22.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.3159352861
Short name T119
Test name
Test status
Simulation time 336752090000 ps
CPU time 256.4 seconds
Started Oct 09 06:57:57 PM UTC 24
Finished Oct 09 07:36:26 PM UTC 24
Peak memory 176536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159352861 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.3159352861
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/23.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.999704855
Short name T121
Test name
Test status
Simulation time 336375410000 ps
CPU time 260.66 seconds
Started Oct 09 06:57:58 PM UTC 24
Finished Oct 09 07:36:27 PM UTC 24
Peak memory 174996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=999704855 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.999704855
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/24.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.409792566
Short name T125
Test name
Test status
Simulation time 336610030000 ps
CPU time 277.13 seconds
Started Oct 09 06:57:58 PM UTC 24
Finished Oct 09 07:36:38 PM UTC 24
Peak memory 174996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409792566 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.409792566
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/25.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1560493699
Short name T128
Test name
Test status
Simulation time 337046550000 ps
CPU time 273.34 seconds
Started Oct 09 06:57:58 PM UTC 24
Finished Oct 09 07:36:40 PM UTC 24
Peak memory 176536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1560493699 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.1560493699
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/26.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.976157636
Short name T129
Test name
Test status
Simulation time 337061350000 ps
CPU time 275.99 seconds
Started Oct 09 06:58:00 PM UTC 24
Finished Oct 09 07:36:44 PM UTC 24
Peak memory 176536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=976157636 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.976157636
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/27.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.4101412076
Short name T131
Test name
Test status
Simulation time 337076890000 ps
CPU time 276.93 seconds
Started Oct 09 06:58:01 PM UTC 24
Finished Oct 09 07:36:47 PM UTC 24
Peak memory 176536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4101412076 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.4101412076
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/28.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.3849978760
Short name T124
Test name
Test status
Simulation time 337107190000 ps
CPU time 265.48 seconds
Started Oct 09 06:58:01 PM UTC 24
Finished Oct 09 07:36:37 PM UTC 24
Peak memory 176536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3849978760 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.3849978760
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/29.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.3296113387
Short name T24
Test name
Test status
Simulation time 336864090000 ps
CPU time 260.95 seconds
Started Oct 09 06:36:26 PM UTC 24
Finished Oct 09 07:11:24 PM UTC 24
Peak memory 174988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3296113387 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.3296113387
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/3.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3576269712
Short name T130
Test name
Test status
Simulation time 337022550000 ps
CPU time 276.55 seconds
Started Oct 09 06:58:02 PM UTC 24
Finished Oct 09 07:36:47 PM UTC 24
Peak memory 174996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3576269712 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.3576269712
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/30.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.3188339967
Short name T132
Test name
Test status
Simulation time 336811930000 ps
CPU time 277.89 seconds
Started Oct 09 06:58:12 PM UTC 24
Finished Oct 09 07:37:01 PM UTC 24
Peak memory 176532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3188339967 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.3188339967
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/31.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.702333626
Short name T134
Test name
Test status
Simulation time 336608330000 ps
CPU time 273.73 seconds
Started Oct 09 06:58:55 PM UTC 24
Finished Oct 09 07:38:01 PM UTC 24
Peak memory 176536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=702333626 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.702333626
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/32.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.3787220931
Short name T133
Test name
Test status
Simulation time 336356810000 ps
CPU time 262.91 seconds
Started Oct 09 06:59:00 PM UTC 24
Finished Oct 09 07:37:58 PM UTC 24
Peak memory 176536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3787220931 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.3787220931
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/33.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.3598467663
Short name T136
Test name
Test status
Simulation time 336672010000 ps
CPU time 276.26 seconds
Started Oct 09 06:59:29 PM UTC 24
Finished Oct 09 07:38:51 PM UTC 24
Peak memory 174996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3598467663 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.3598467663
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/34.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.1508063954
Short name T135
Test name
Test status
Simulation time 336412310000 ps
CPU time 259.78 seconds
Started Oct 09 06:59:32 PM UTC 24
Finished Oct 09 07:38:44 PM UTC 24
Peak memory 176536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1508063954 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.1508063954
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/35.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.3738589115
Short name T137
Test name
Test status
Simulation time 337096470000 ps
CPU time 277.73 seconds
Started Oct 09 06:59:51 PM UTC 24
Finished Oct 09 07:39:27 PM UTC 24
Peak memory 174996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3738589115 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.3738589115
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/36.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.945750827
Short name T138
Test name
Test status
Simulation time 336700730000 ps
CPU time 271.89 seconds
Started Oct 09 07:00:00 PM UTC 24
Finished Oct 09 07:39:35 PM UTC 24
Peak memory 174996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=945750827 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.945750827
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/37.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.3856452343
Short name T139
Test name
Test status
Simulation time 336653670000 ps
CPU time 265.61 seconds
Started Oct 09 07:00:09 PM UTC 24
Finished Oct 09 07:39:40 PM UTC 24
Peak memory 174996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3856452343 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.3856452343
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/38.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.23084942
Short name T140
Test name
Test status
Simulation time 337139750000 ps
CPU time 266.12 seconds
Started Oct 09 07:00:10 PM UTC 24
Finished Oct 09 07:39:45 PM UTC 24
Peak memory 174984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23084942 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_
fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.23084942
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/39.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.2468544050
Short name T25
Test name
Test status
Simulation time 337081210000 ps
CPU time 257.05 seconds
Started Oct 09 06:37:08 PM UTC 24
Finished Oct 09 07:12:10 PM UTC 24
Peak memory 176528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2468544050 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.2468544050
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/4.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.2901682762
Short name T141
Test name
Test status
Simulation time 336367890000 ps
CPU time 263.98 seconds
Started Oct 09 07:00:16 PM UTC 24
Finished Oct 09 07:39:48 PM UTC 24
Peak memory 176536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2901682762 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.2901682762
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/40.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.652341284
Short name T142
Test name
Test status
Simulation time 336344590000 ps
CPU time 262.47 seconds
Started Oct 09 07:00:48 PM UTC 24
Finished Oct 09 07:40:28 PM UTC 24
Peak memory 174996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=652341284 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.652341284
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/41.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.2697269546
Short name T143
Test name
Test status
Simulation time 336486350000 ps
CPU time 262.74 seconds
Started Oct 09 07:01:02 PM UTC 24
Finished Oct 09 07:40:50 PM UTC 24
Peak memory 174984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697269546 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.2697269546
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/42.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.3952890143
Short name T145
Test name
Test status
Simulation time 336499170000 ps
CPU time 282.65 seconds
Started Oct 09 07:01:25 PM UTC 24
Finished Oct 09 07:41:33 PM UTC 24
Peak memory 176536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3952890143 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.3952890143
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/43.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.2495769243
Short name T144
Test name
Test status
Simulation time 336659690000 ps
CPU time 264.21 seconds
Started Oct 09 07:01:31 PM UTC 24
Finished Oct 09 07:41:32 PM UTC 24
Peak memory 176536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2495769243 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.2495769243
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/44.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.3641083023
Short name T146
Test name
Test status
Simulation time 336485550000 ps
CPU time 280.99 seconds
Started Oct 09 07:01:34 PM UTC 24
Finished Oct 09 07:41:46 PM UTC 24
Peak memory 174996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3641083023 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.3641083023
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/45.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.2954908416
Short name T147
Test name
Test status
Simulation time 336638150000 ps
CPU time 271.6 seconds
Started Oct 09 07:01:50 PM UTC 24
Finished Oct 09 07:42:05 PM UTC 24
Peak memory 174996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2954908416 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.2954908416
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/46.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.2891179286
Short name T148
Test name
Test status
Simulation time 336709070000 ps
CPU time 281.49 seconds
Started Oct 09 07:02:06 PM UTC 24
Finished Oct 09 07:42:34 PM UTC 24
Peak memory 174988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2891179286 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.2891179286
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/47.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.1200957233
Short name T149
Test name
Test status
Simulation time 336618730000 ps
CPU time 284.08 seconds
Started Oct 09 07:02:15 PM UTC 24
Finished Oct 09 07:42:45 PM UTC 24
Peak memory 174996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1200957233 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.1200957233
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/48.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.2049059523
Short name T150
Test name
Test status
Simulation time 336808770000 ps
CPU time 280.23 seconds
Started Oct 09 07:02:22 PM UTC 24
Finished Oct 09 07:42:55 PM UTC 24
Peak memory 176536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2049059523 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.2049059523
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/49.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.892385987
Short name T26
Test name
Test status
Simulation time 336764350000 ps
CPU time 256.59 seconds
Started Oct 09 06:37:39 PM UTC 24
Finished Oct 09 07:12:41 PM UTC 24
Peak memory 174992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=892385987 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.892385987
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/5.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.3181997916
Short name T27
Test name
Test status
Simulation time 336698650000 ps
CPU time 257.71 seconds
Started Oct 09 06:38:12 PM UTC 24
Finished Oct 09 07:13:20 PM UTC 24
Peak memory 176528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3181997916 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.3181997916
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/6.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.297398082
Short name T28
Test name
Test status
Simulation time 336971710000 ps
CPU time 253.31 seconds
Started Oct 09 06:38:26 PM UTC 24
Finished Oct 09 07:13:32 PM UTC 24
Peak memory 176532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=297398082 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.297398082
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/7.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1171509490
Short name T29
Test name
Test status
Simulation time 336721790000 ps
CPU time 266.13 seconds
Started Oct 09 06:39:39 PM UTC 24
Finished Oct 09 07:15:09 PM UTC 24
Peak memory 176520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1171509490 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.1171509490
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/8.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.967505486
Short name T30
Test name
Test status
Simulation time 336884070000 ps
CPU time 264.6 seconds
Started Oct 09 06:40:49 PM UTC 24
Finished Oct 09 07:16:35 PM UTC 24
Peak memory 174992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=967505486 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.967505486
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/9.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.941324646
Short name T14
Test name
Test status
Simulation time 336346610000 ps
CPU time 275.55 seconds
Started Oct 09 06:20:43 PM UTC 24
Finished Oct 09 06:57:51 PM UTC 24
Peak memory 176624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=941324646 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.941324646
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/1.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.4007533994
Short name T74
Test name
Test status
Simulation time 336324250000 ps
CPU time 276.56 seconds
Started Oct 09 06:20:44 PM UTC 24
Finished Oct 09 06:57:58 PM UTC 24
Peak memory 174996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4007533994 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.4007533994
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/10.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.3073181379
Short name T18
Test name
Test status
Simulation time 337002170000 ps
CPU time 271.88 seconds
Started Oct 09 06:20:44 PM UTC 24
Finished Oct 09 06:57:54 PM UTC 24
Peak memory 176536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3073181379 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.3073181379
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/11.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.810164590
Short name T75
Test name
Test status
Simulation time 336565130000 ps
CPU time 274.7 seconds
Started Oct 09 06:20:44 PM UTC 24
Finished Oct 09 06:57:58 PM UTC 24
Peak memory 174996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=810164590 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.810164590
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/12.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.2707321260
Short name T19
Test name
Test status
Simulation time 336370730000 ps
CPU time 276.17 seconds
Started Oct 09 06:20:45 PM UTC 24
Finished Oct 09 06:57:55 PM UTC 24
Peak memory 174996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2707321260 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.2707321260
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/13.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.2018172458
Short name T17
Test name
Test status
Simulation time 336668070000 ps
CPU time 277.08 seconds
Started Oct 09 06:20:46 PM UTC 24
Finished Oct 09 06:57:54 PM UTC 24
Peak memory 176536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2018172458 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.2018172458
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/14.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.2851862291
Short name T76
Test name
Test status
Simulation time 336707490000 ps
CPU time 277.93 seconds
Started Oct 09 06:20:46 PM UTC 24
Finished Oct 09 06:57:59 PM UTC 24
Peak memory 176536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2851862291 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.2851862291
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/15.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.3894517130
Short name T78
Test name
Test status
Simulation time 337040050000 ps
CPU time 277.98 seconds
Started Oct 09 06:20:49 PM UTC 24
Finished Oct 09 06:58:01 PM UTC 24
Peak memory 176536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3894517130 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.3894517130
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/16.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.3548047657
Short name T77
Test name
Test status
Simulation time 336374150000 ps
CPU time 272.68 seconds
Started Oct 09 06:20:53 PM UTC 24
Finished Oct 09 06:58:00 PM UTC 24
Peak memory 174996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3548047657 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.3548047657
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/17.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.1057711410
Short name T79
Test name
Test status
Simulation time 336978770000 ps
CPU time 272.76 seconds
Started Oct 09 06:21:00 PM UTC 24
Finished Oct 09 06:58:11 PM UTC 24
Peak memory 174996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1057711410 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.1057711410
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/18.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.269553281
Short name T80
Test name
Test status
Simulation time 336534590000 ps
CPU time 270.75 seconds
Started Oct 09 06:22:16 PM UTC 24
Finished Oct 09 06:58:54 PM UTC 24
Peak memory 176536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=269553281 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.269553281
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/19.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.3845868640
Short name T71
Test name
Test status
Simulation time 336837350000 ps
CPU time 275.75 seconds
Started Oct 09 06:20:43 PM UTC 24
Finished Oct 09 06:57:57 PM UTC 24
Peak memory 174984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3845868640 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.3845868640
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/2.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.3047402034
Short name T81
Test name
Test status
Simulation time 337056350000 ps
CPU time 270.38 seconds
Started Oct 09 06:22:18 PM UTC 24
Finished Oct 09 06:58:59 PM UTC 24
Peak memory 176536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3047402034 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.3047402034
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/20.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.2822592278
Short name T82
Test name
Test status
Simulation time 337179690000 ps
CPU time 273.09 seconds
Started Oct 09 06:23:10 PM UTC 24
Finished Oct 09 06:59:28 PM UTC 24
Peak memory 174992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2822592278 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.2822592278
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/21.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.314234130
Short name T83
Test name
Test status
Simulation time 336827070000 ps
CPU time 270.23 seconds
Started Oct 09 06:23:11 PM UTC 24
Finished Oct 09 06:59:31 PM UTC 24
Peak memory 176536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=314234130 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.314234130
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/22.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.4120539458
Short name T84
Test name
Test status
Simulation time 337033310000 ps
CPU time 271.25 seconds
Started Oct 09 06:23:45 PM UTC 24
Finished Oct 09 06:59:51 PM UTC 24
Peak memory 174996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4120539458 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.4120539458
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/23.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.2955957734
Short name T85
Test name
Test status
Simulation time 336570090000 ps
CPU time 263.97 seconds
Started Oct 09 06:23:56 PM UTC 24
Finished Oct 09 07:00:00 PM UTC 24
Peak memory 174996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2955957734 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.2955957734
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/24.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.76550692
Short name T86
Test name
Test status
Simulation time 336699070000 ps
CPU time 264.8 seconds
Started Oct 09 06:24:05 PM UTC 24
Finished Oct 09 07:00:06 PM UTC 24
Peak memory 174988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=76550692 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_
gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.76550692
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/25.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.3957752233
Short name T87
Test name
Test status
Simulation time 336398370000 ps
CPU time 266.17 seconds
Started Oct 09 06:24:08 PM UTC 24
Finished Oct 09 07:00:06 PM UTC 24
Peak memory 176536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3957752233 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.3957752233
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/26.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.284902524
Short name T88
Test name
Test status
Simulation time 336930790000 ps
CPU time 271.72 seconds
Started Oct 09 06:24:16 PM UTC 24
Finished Oct 09 07:00:15 PM UTC 24
Peak memory 176536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=284902524 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.284902524
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/27.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.3856441415
Short name T89
Test name
Test status
Simulation time 336638230000 ps
CPU time 271.75 seconds
Started Oct 09 06:25:02 PM UTC 24
Finished Oct 09 07:00:47 PM UTC 24
Peak memory 176536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3856441415 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.3856441415
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/28.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.923190390
Short name T90
Test name
Test status
Simulation time 336438050000 ps
CPU time 269.85 seconds
Started Oct 09 06:25:23 PM UTC 24
Finished Oct 09 07:01:01 PM UTC 24
Peak memory 176536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=923190390 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.923190390
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/29.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.1833987962
Short name T16
Test name
Test status
Simulation time 336531410000 ps
CPU time 275.25 seconds
Started Oct 09 06:20:43 PM UTC 24
Finished Oct 09 06:57:53 PM UTC 24
Peak memory 176304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1833987962 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.1833987962
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/3.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.730440048
Short name T91
Test name
Test status
Simulation time 336576990000 ps
CPU time 268.04 seconds
Started Oct 09 06:25:52 PM UTC 24
Finished Oct 09 07:01:24 PM UTC 24
Peak memory 176536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=730440048 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.730440048
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/30.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.2416931205
Short name T92
Test name
Test status
Simulation time 336760710000 ps
CPU time 260.45 seconds
Started Oct 09 06:25:58 PM UTC 24
Finished Oct 09 07:01:30 PM UTC 24
Peak memory 176536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2416931205 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.2416931205
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/31.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.3056255592
Short name T93
Test name
Test status
Simulation time 337063470000 ps
CPU time 260 seconds
Started Oct 09 06:26:05 PM UTC 24
Finished Oct 09 07:01:33 PM UTC 24
Peak memory 174996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3056255592 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.3056255592
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/32.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.4102570477
Short name T94
Test name
Test status
Simulation time 336745650000 ps
CPU time 261.09 seconds
Started Oct 09 06:26:25 PM UTC 24
Finished Oct 09 07:01:49 PM UTC 24
Peak memory 174996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4102570477 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.4102570477
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/33.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.2837362406
Short name T95
Test name
Test status
Simulation time 336584850000 ps
CPU time 267.18 seconds
Started Oct 09 06:26:43 PM UTC 24
Finished Oct 09 07:02:06 PM UTC 24
Peak memory 174996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2837362406 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.2837362406
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/34.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.363723044
Short name T96
Test name
Test status
Simulation time 336502530000 ps
CPU time 263.88 seconds
Started Oct 09 06:26:55 PM UTC 24
Finished Oct 09 07:02:15 PM UTC 24
Peak memory 174996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=363723044 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.363723044
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/35.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.4145889166
Short name T97
Test name
Test status
Simulation time 336320830000 ps
CPU time 259.29 seconds
Started Oct 09 06:27:03 PM UTC 24
Finished Oct 09 07:02:21 PM UTC 24
Peak memory 176536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4145889166 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.4145889166
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/36.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.1743706241
Short name T98
Test name
Test status
Simulation time 337014330000 ps
CPU time 260.94 seconds
Started Oct 09 06:27:12 PM UTC 24
Finished Oct 09 07:02:33 PM UTC 24
Peak memory 174996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1743706241 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.1743706241
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/37.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3140167138
Short name T100
Test name
Test status
Simulation time 336747370000 ps
CPU time 262.01 seconds
Started Oct 09 06:27:34 PM UTC 24
Finished Oct 09 07:02:50 PM UTC 24
Peak memory 174996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3140167138 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.3140167138
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/38.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.388067975
Short name T99
Test name
Test status
Simulation time 336384930000 ps
CPU time 262.69 seconds
Started Oct 09 06:27:36 PM UTC 24
Finished Oct 09 07:02:47 PM UTC 24
Peak memory 176536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=388067975 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.388067975
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/39.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.3155320780
Short name T73
Test name
Test status
Simulation time 336633930000 ps
CPU time 272.5 seconds
Started Oct 09 06:20:43 PM UTC 24
Finished Oct 09 06:57:57 PM UTC 24
Peak memory 174744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3155320780 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.3155320780
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/4.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.2815067215
Short name T101
Test name
Test status
Simulation time 336554090000 ps
CPU time 264.73 seconds
Started Oct 09 06:27:59 PM UTC 24
Finished Oct 09 07:03:09 PM UTC 24
Peak memory 174996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2815067215 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.2815067215
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/40.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.352183682
Short name T103
Test name
Test status
Simulation time 336987970000 ps
CPU time 259.48 seconds
Started Oct 09 06:28:27 PM UTC 24
Finished Oct 09 07:03:36 PM UTC 24
Peak memory 174996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=352183682 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.352183682
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/41.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.1473650511
Short name T102
Test name
Test status
Simulation time 336529170000 ps
CPU time 259.99 seconds
Started Oct 09 06:28:32 PM UTC 24
Finished Oct 09 07:03:35 PM UTC 24
Peak memory 174996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1473650511 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.1473650511
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/42.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.3407660705
Short name T104
Test name
Test status
Simulation time 337024030000 ps
CPU time 261.31 seconds
Started Oct 09 06:28:45 PM UTC 24
Finished Oct 09 07:03:55 PM UTC 24
Peak memory 174996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3407660705 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.3407660705
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/43.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.1280075212
Short name T105
Test name
Test status
Simulation time 336993290000 ps
CPU time 267.5 seconds
Started Oct 09 06:29:19 PM UTC 24
Finished Oct 09 07:04:25 PM UTC 24
Peak memory 174996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1280075212 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.1280075212
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/44.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.3711957388
Short name T106
Test name
Test status
Simulation time 336662370000 ps
CPU time 257.43 seconds
Started Oct 09 06:29:41 PM UTC 24
Finished Oct 09 07:04:42 PM UTC 24
Peak memory 174996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3711957388 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.3711957388
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/45.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.2995913193
Short name T107
Test name
Test status
Simulation time 336826690000 ps
CPU time 254.83 seconds
Started Oct 09 06:32:23 PM UTC 24
Finished Oct 09 07:07:08 PM UTC 24
Peak memory 174996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2995913193 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.2995913193
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/46.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.3400908104
Short name T108
Test name
Test status
Simulation time 337020370000 ps
CPU time 264.34 seconds
Started Oct 09 06:33:14 PM UTC 24
Finished Oct 09 07:08:00 PM UTC 24
Peak memory 176536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3400908104 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.3400908104
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/47.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.859708408
Short name T109
Test name
Test status
Simulation time 336426990000 ps
CPU time 264.74 seconds
Started Oct 09 06:33:46 PM UTC 24
Finished Oct 09 07:08:30 PM UTC 24
Peak memory 176536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=859708408 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.859708408
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/48.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.1024539014
Short name T110
Test name
Test status
Simulation time 336373130000 ps
CPU time 261.51 seconds
Started Oct 09 06:33:53 PM UTC 24
Finished Oct 09 07:08:37 PM UTC 24
Peak memory 174992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1024539014 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.1024539014
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/49.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.1041977327
Short name T20
Test name
Test status
Simulation time 336613290000 ps
CPU time 279.33 seconds
Started Oct 09 06:20:43 PM UTC 24
Finished Oct 09 06:57:55 PM UTC 24
Peak memory 176524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1041977327 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.1041977327
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/5.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.1682014193
Short name T72
Test name
Test status
Simulation time 336597430000 ps
CPU time 272.3 seconds
Started Oct 09 06:20:43 PM UTC 24
Finished Oct 09 06:57:57 PM UTC 24
Peak memory 176532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1682014193 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.1682014193
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/6.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.512476439
Short name T21
Test name
Test status
Simulation time 337090950000 ps
CPU time 273.93 seconds
Started Oct 09 06:20:44 PM UTC 24
Finished Oct 09 06:57:56 PM UTC 24
Peak memory 175020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=512476439 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.512476439
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/7.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.2907242266
Short name T22
Test name
Test status
Simulation time 336574390000 ps
CPU time 278.24 seconds
Started Oct 09 06:20:44 PM UTC 24
Finished Oct 09 06:57:56 PM UTC 24
Peak memory 176524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2907242266 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.2907242266
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/8.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.2935657819
Short name T15
Test name
Test status
Simulation time 336536310000 ps
CPU time 270.76 seconds
Started Oct 09 06:20:44 PM UTC 24
Finished Oct 09 06:57:52 PM UTC 24
Peak memory 176520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2935657819 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.2935657819
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/9.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.3077308977
Short name T151
Test name
Test status
Simulation time 1251450000 ps
CPU time 1.87 seconds
Started Oct 09 07:02:35 PM UTC 24
Finished Oct 09 07:02:44 PM UTC 24
Peak memory 177832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3077308977 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.3077308977
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/0.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.188443866
Short name T152
Test name
Test status
Simulation time 1484650000 ps
CPU time 2.06 seconds
Started Oct 09 07:02:48 PM UTC 24
Finished Oct 09 07:02:59 PM UTC 24
Peak memory 177792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=188443866 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f
ib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.188443866
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/1.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.3068899615
Short name T161
Test name
Test status
Simulation time 1473390000 ps
CPU time 1.86 seconds
Started Oct 09 07:03:16 PM UTC 24
Finished Oct 09 07:03:26 PM UTC 24
Peak memory 177764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3068899615 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.3068899615
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/10.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.1288899230
Short name T162
Test name
Test status
Simulation time 1450010000 ps
CPU time 1.84 seconds
Started Oct 09 07:03:24 PM UTC 24
Finished Oct 09 07:03:34 PM UTC 24
Peak memory 177764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1288899230 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.1288899230
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/11.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.12865163
Short name T163
Test name
Test status
Simulation time 1463530000 ps
CPU time 1.91 seconds
Started Oct 09 07:03:24 PM UTC 24
Finished Oct 09 07:03:34 PM UTC 24
Peak memory 177764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12865163 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fi
b.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.12865163
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/12.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.714682020
Short name T164
Test name
Test status
Simulation time 1506950000 ps
CPU time 2 seconds
Started Oct 09 07:03:26 PM UTC 24
Finished Oct 09 07:03:37 PM UTC 24
Peak memory 177760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=714682020 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f
ib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.714682020
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/13.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.3018843726
Short name T165
Test name
Test status
Simulation time 1377990000 ps
CPU time 1.91 seconds
Started Oct 09 07:03:28 PM UTC 24
Finished Oct 09 07:03:38 PM UTC 24
Peak memory 177748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3018843726 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.3018843726
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/14.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.660862486
Short name T168
Test name
Test status
Simulation time 1561590000 ps
CPU time 2.14 seconds
Started Oct 09 07:03:36 PM UTC 24
Finished Oct 09 07:03:47 PM UTC 24
Peak memory 177348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=660862486 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f
ib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.660862486
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/15.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.578850513
Short name T166
Test name
Test status
Simulation time 1427690000 ps
CPU time 1.94 seconds
Started Oct 09 07:03:36 PM UTC 24
Finished Oct 09 07:03:46 PM UTC 24
Peak memory 177360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=578850513 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f
ib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.578850513
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/16.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.2245091746
Short name T167
Test name
Test status
Simulation time 1433850000 ps
CPU time 1.91 seconds
Started Oct 09 07:03:36 PM UTC 24
Finished Oct 09 07:03:46 PM UTC 24
Peak memory 177764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2245091746 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.2245091746
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/17.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.1205661506
Short name T169
Test name
Test status
Simulation time 1369290000 ps
CPU time 1.87 seconds
Started Oct 09 07:03:38 PM UTC 24
Finished Oct 09 07:03:48 PM UTC 24
Peak memory 177764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1205661506 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.1205661506
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/18.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.2714307506
Short name T170
Test name
Test status
Simulation time 1460850000 ps
CPU time 2.02 seconds
Started Oct 09 07:03:38 PM UTC 24
Finished Oct 09 07:03:49 PM UTC 24
Peak memory 177764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2714307506 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.2714307506
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/19.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.2099670181
Short name T153
Test name
Test status
Simulation time 1354910000 ps
CPU time 1.95 seconds
Started Oct 09 07:02:49 PM UTC 24
Finished Oct 09 07:02:59 PM UTC 24
Peak memory 177752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2099670181 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.2099670181
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/2.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.3351521593
Short name T171
Test name
Test status
Simulation time 1549650000 ps
CPU time 2.09 seconds
Started Oct 09 07:03:40 PM UTC 24
Finished Oct 09 07:03:52 PM UTC 24
Peak memory 177764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3351521593 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.3351521593
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/20.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.982651073
Short name T173
Test name
Test status
Simulation time 1476450000 ps
CPU time 2.1 seconds
Started Oct 09 07:03:48 PM UTC 24
Finished Oct 09 07:03:59 PM UTC 24
Peak memory 177756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=982651073 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f
ib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.982651073
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/21.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.718784948
Short name T172
Test name
Test status
Simulation time 1377470000 ps
CPU time 1.88 seconds
Started Oct 09 07:03:48 PM UTC 24
Finished Oct 09 07:03:59 PM UTC 24
Peak memory 177760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=718784948 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f
ib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.718784948
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/22.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.362701048
Short name T174
Test name
Test status
Simulation time 1595330000 ps
CPU time 2.06 seconds
Started Oct 09 07:03:49 PM UTC 24
Finished Oct 09 07:04:00 PM UTC 24
Peak memory 177736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362701048 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f
ib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.362701048
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/23.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.1972344241
Short name T176
Test name
Test status
Simulation time 1469610000 ps
CPU time 1.98 seconds
Started Oct 09 07:03:51 PM UTC 24
Finished Oct 09 07:04:01 PM UTC 24
Peak memory 177764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1972344241 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.1972344241
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/24.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.1818968915
Short name T175
Test name
Test status
Simulation time 1365990000 ps
CPU time 1.84 seconds
Started Oct 09 07:03:51 PM UTC 24
Finished Oct 09 07:04:01 PM UTC 24
Peak memory 177764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1818968915 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.1818968915
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/25.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.450217744
Short name T177
Test name
Test status
Simulation time 1432950000 ps
CPU time 1.94 seconds
Started Oct 09 07:03:54 PM UTC 24
Finished Oct 09 07:04:04 PM UTC 24
Peak memory 177796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=450217744 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f
ib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.450217744
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/26.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.2448312585
Short name T178
Test name
Test status
Simulation time 1425170000 ps
CPU time 2.01 seconds
Started Oct 09 07:03:56 PM UTC 24
Finished Oct 09 07:04:06 PM UTC 24
Peak memory 177764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2448312585 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.2448312585
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/27.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.3580428952
Short name T180
Test name
Test status
Simulation time 1568910000 ps
CPU time 2.03 seconds
Started Oct 09 07:04:00 PM UTC 24
Finished Oct 09 07:04:11 PM UTC 24
Peak memory 177760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3580428952 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.3580428952
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/28.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.1478362547
Short name T179
Test name
Test status
Simulation time 1491070000 ps
CPU time 1.91 seconds
Started Oct 09 07:04:00 PM UTC 24
Finished Oct 09 07:04:11 PM UTC 24
Peak memory 177760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1478362547 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.1478362547
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/29.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.1337568365
Short name T154
Test name
Test status
Simulation time 1489270000 ps
CPU time 2.06 seconds
Started Oct 09 07:02:51 PM UTC 24
Finished Oct 09 07:03:02 PM UTC 24
Peak memory 177764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1337568365 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.1337568365
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/3.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.3190180364
Short name T184
Test name
Test status
Simulation time 1557990000 ps
CPU time 2.01 seconds
Started Oct 09 07:04:02 PM UTC 24
Finished Oct 09 07:04:13 PM UTC 24
Peak memory 177764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3190180364 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.3190180364
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/30.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.2687992439
Short name T181
Test name
Test status
Simulation time 1332650000 ps
CPU time 1.84 seconds
Started Oct 09 07:04:02 PM UTC 24
Finished Oct 09 07:04:12 PM UTC 24
Peak memory 177764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2687992439 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.2687992439
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/31.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.3675499227
Short name T182
Test name
Test status
Simulation time 1441970000 ps
CPU time 1.94 seconds
Started Oct 09 07:04:02 PM UTC 24
Finished Oct 09 07:04:13 PM UTC 24
Peak memory 177764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3675499227 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.3675499227
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/32.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.2866321404
Short name T183
Test name
Test status
Simulation time 1296050000 ps
CPU time 1.87 seconds
Started Oct 09 07:04:03 PM UTC 24
Finished Oct 09 07:04:13 PM UTC 24
Peak memory 177764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2866321404 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.2866321404
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/33.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.1719046845
Short name T185
Test name
Test status
Simulation time 1509450000 ps
CPU time 2.08 seconds
Started Oct 09 07:04:05 PM UTC 24
Finished Oct 09 07:04:16 PM UTC 24
Peak memory 177764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1719046845 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.1719046845
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/34.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.1556955090
Short name T186
Test name
Test status
Simulation time 1556810000 ps
CPU time 2.15 seconds
Started Oct 09 07:04:07 PM UTC 24
Finished Oct 09 07:04:19 PM UTC 24
Peak memory 177764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1556955090 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.1556955090
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/35.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.3790293661
Short name T187
Test name
Test status
Simulation time 1501470000 ps
CPU time 1.91 seconds
Started Oct 09 07:04:11 PM UTC 24
Finished Oct 09 07:04:22 PM UTC 24
Peak memory 177764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3790293661 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.3790293661
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/36.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1941363951
Short name T189
Test name
Test status
Simulation time 1392610000 ps
CPU time 1.89 seconds
Started Oct 09 07:04:13 PM UTC 24
Finished Oct 09 07:04:23 PM UTC 24
Peak memory 177764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1941363951 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.1941363951
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/37.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.1576887033
Short name T188
Test name
Test status
Simulation time 1299970000 ps
CPU time 1.94 seconds
Started Oct 09 07:04:13 PM UTC 24
Finished Oct 09 07:04:22 PM UTC 24
Peak memory 177764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1576887033 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.1576887033
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/38.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.1660193553
Short name T192
Test name
Test status
Simulation time 1512070000 ps
CPU time 1.96 seconds
Started Oct 09 07:04:14 PM UTC 24
Finished Oct 09 07:04:24 PM UTC 24
Peak memory 177764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1660193553 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.1660193553
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/39.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.2034989933
Short name T155
Test name
Test status
Simulation time 1523770000 ps
CPU time 2.06 seconds
Started Oct 09 07:02:59 PM UTC 24
Finished Oct 09 07:03:10 PM UTC 24
Peak memory 177760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2034989933 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.2034989933
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/4.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.2237058466
Short name T190
Test name
Test status
Simulation time 1461130000 ps
CPU time 1.9 seconds
Started Oct 09 07:04:14 PM UTC 24
Finished Oct 09 07:04:24 PM UTC 24
Peak memory 177764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2237058466 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.2237058466
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/40.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.4132617304
Short name T191
Test name
Test status
Simulation time 1492090000 ps
CPU time 1.96 seconds
Started Oct 09 07:04:14 PM UTC 24
Finished Oct 09 07:04:24 PM UTC 24
Peak memory 177764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4132617304 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.4132617304
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/41.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.1944419528
Short name T193
Test name
Test status
Simulation time 1359630000 ps
CPU time 1.9 seconds
Started Oct 09 07:04:17 PM UTC 24
Finished Oct 09 07:04:27 PM UTC 24
Peak memory 177796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1944419528 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.1944419528
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/42.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.219059225
Short name T194
Test name
Test status
Simulation time 1505790000 ps
CPU time 1.99 seconds
Started Oct 09 07:04:20 PM UTC 24
Finished Oct 09 07:04:31 PM UTC 24
Peak memory 177760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=219059225 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f
ib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.219059225
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/43.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.1106989872
Short name T197
Test name
Test status
Simulation time 1555850000 ps
CPU time 2.21 seconds
Started Oct 09 07:04:23 PM UTC 24
Finished Oct 09 07:04:35 PM UTC 24
Peak memory 177792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1106989872 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.1106989872
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/44.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.1510173291
Short name T196
Test name
Test status
Simulation time 1507490000 ps
CPU time 2.09 seconds
Started Oct 09 07:04:23 PM UTC 24
Finished Oct 09 07:04:34 PM UTC 24
Peak memory 177796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1510173291 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.1510173291
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/45.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.3781165480
Short name T195
Test name
Test status
Simulation time 1463090000 ps
CPU time 1.92 seconds
Started Oct 09 07:04:23 PM UTC 24
Finished Oct 09 07:04:34 PM UTC 24
Peak memory 177796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3781165480 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.3781165480
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/46.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.2216099327
Short name T198
Test name
Test status
Simulation time 1457950000 ps
CPU time 2.04 seconds
Started Oct 09 07:04:25 PM UTC 24
Finished Oct 09 07:04:36 PM UTC 24
Peak memory 177480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2216099327 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.2216099327
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/47.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.3097501804
Short name T199
Test name
Test status
Simulation time 1464990000 ps
CPU time 2.03 seconds
Started Oct 09 07:04:25 PM UTC 24
Finished Oct 09 07:04:36 PM UTC 24
Peak memory 177508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097501804 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.3097501804
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/48.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.2807356867
Short name T200
Test name
Test status
Simulation time 1515410000 ps
CPU time 2.03 seconds
Started Oct 09 07:04:25 PM UTC 24
Finished Oct 09 07:04:37 PM UTC 24
Peak memory 177796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2807356867 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.2807356867
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/49.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.4268807947
Short name T156
Test name
Test status
Simulation time 1499190000 ps
CPU time 1.99 seconds
Started Oct 09 07:03:01 PM UTC 24
Finished Oct 09 07:03:12 PM UTC 24
Peak memory 177764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268807947 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.4268807947
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/5.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.2222179314
Short name T157
Test name
Test status
Simulation time 1533810000 ps
CPU time 2.07 seconds
Started Oct 09 07:03:03 PM UTC 24
Finished Oct 09 07:03:15 PM UTC 24
Peak memory 177764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2222179314 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.2222179314
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/6.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.2853528714
Short name T159
Test name
Test status
Simulation time 1628870000 ps
CPU time 2.07 seconds
Started Oct 09 07:03:12 PM UTC 24
Finished Oct 09 07:03:23 PM UTC 24
Peak memory 177764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2853528714 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.2853528714
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/7.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.3709717813
Short name T158
Test name
Test status
Simulation time 1581150000 ps
CPU time 1.92 seconds
Started Oct 09 07:03:12 PM UTC 24
Finished Oct 09 07:03:23 PM UTC 24
Peak memory 177764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3709717813 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.3709717813
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/8.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.724624983
Short name T160
Test name
Test status
Simulation time 1504450000 ps
CPU time 1.95 seconds
Started Oct 09 07:03:14 PM UTC 24
Finished Oct 09 07:03:24 PM UTC 24
Peak memory 177796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=724624983 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f
ib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.724624983
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/9.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.685391981
Short name T3
Test name
Test status
Simulation time 1392950000 ps
CPU time 2.33 seconds
Started Oct 09 02:32:52 PM UTC 24
Finished Oct 09 02:33:07 PM UTC 24
Peak memory 177760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=685391981 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g
al.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.685391981
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/1.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.2956256108
Short name T31
Test name
Test status
Simulation time 1451590000 ps
CPU time 2.4 seconds
Started Oct 09 02:32:56 PM UTC 24
Finished Oct 09 02:33:10 PM UTC 24
Peak memory 177728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2956256108 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.2956256108
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/10.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.629540926
Short name T32
Test name
Test status
Simulation time 1564890000 ps
CPU time 2.43 seconds
Started Oct 09 02:32:58 PM UTC 24
Finished Oct 09 02:33:13 PM UTC 24
Peak memory 177724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=629540926 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g
al.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.629540926
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/11.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.648036822
Short name T33
Test name
Test status
Simulation time 1553090000 ps
CPU time 2.46 seconds
Started Oct 09 02:33:03 PM UTC 24
Finished Oct 09 02:33:18 PM UTC 24
Peak memory 177724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=648036822 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g
al.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.648036822
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/12.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.1262988359
Short name T34
Test name
Test status
Simulation time 1511550000 ps
CPU time 2.41 seconds
Started Oct 09 02:33:07 PM UTC 24
Finished Oct 09 02:33:22 PM UTC 24
Peak memory 177728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1262988359 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.1262988359
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/13.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.937366924
Short name T36
Test name
Test status
Simulation time 1316590000 ps
CPU time 2.26 seconds
Started Oct 09 02:33:09 PM UTC 24
Finished Oct 09 02:33:22 PM UTC 24
Peak memory 177724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=937366924 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g
al.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.937366924
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/14.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.1727118499
Short name T35
Test name
Test status
Simulation time 1263270000 ps
CPU time 2.12 seconds
Started Oct 09 02:33:09 PM UTC 24
Finished Oct 09 02:33:22 PM UTC 24
Peak memory 177728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1727118499 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.1727118499
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/15.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.78810460
Short name T40
Test name
Test status
Simulation time 1545430000 ps
CPU time 2.6 seconds
Started Oct 09 02:33:09 PM UTC 24
Finished Oct 09 02:33:24 PM UTC 24
Peak memory 177728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=78810460 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ga
l.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.78810460
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/16.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.3718714999
Short name T38
Test name
Test status
Simulation time 1438770000 ps
CPU time 2.52 seconds
Started Oct 09 02:33:09 PM UTC 24
Finished Oct 09 02:33:23 PM UTC 24
Peak memory 177728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3718714999 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.3718714999
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/17.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.1613010984
Short name T37
Test name
Test status
Simulation time 1359950000 ps
CPU time 2.37 seconds
Started Oct 09 02:33:09 PM UTC 24
Finished Oct 09 02:33:23 PM UTC 24
Peak memory 177728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1613010984 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.1613010984
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/18.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.1231643038
Short name T42
Test name
Test status
Simulation time 1592430000 ps
CPU time 2.39 seconds
Started Oct 09 02:33:09 PM UTC 24
Finished Oct 09 02:33:25 PM UTC 24
Peak memory 177588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1231643038 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.1231643038
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/19.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.1544099289
Short name T9
Test name
Test status
Simulation time 1501830000 ps
CPU time 2.44 seconds
Started Oct 09 02:32:53 PM UTC 24
Finished Oct 09 02:33:08 PM UTC 24
Peak memory 177728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1544099289 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.1544099289
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/2.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.2673016097
Short name T39
Test name
Test status
Simulation time 1508870000 ps
CPU time 2.44 seconds
Started Oct 09 02:33:09 PM UTC 24
Finished Oct 09 02:33:24 PM UTC 24
Peak memory 177608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2673016097 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.2673016097
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/20.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.3483036517
Short name T41
Test name
Test status
Simulation time 1534810000 ps
CPU time 2.47 seconds
Started Oct 09 02:33:09 PM UTC 24
Finished Oct 09 02:33:24 PM UTC 24
Peak memory 177728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3483036517 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.3483036517
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/21.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.3416481323
Short name T43
Test name
Test status
Simulation time 1575690000 ps
CPU time 2.6 seconds
Started Oct 09 02:33:10 PM UTC 24
Finished Oct 09 02:33:25 PM UTC 24
Peak memory 177728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3416481323 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.3416481323
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/22.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.344943178
Short name T44
Test name
Test status
Simulation time 1502870000 ps
CPU time 2.21 seconds
Started Oct 09 02:33:12 PM UTC 24
Finished Oct 09 02:33:26 PM UTC 24
Peak memory 177724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=344943178 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g
al.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.344943178
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/23.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.1034426488
Short name T45
Test name
Test status
Simulation time 1473390000 ps
CPU time 2.23 seconds
Started Oct 09 02:33:15 PM UTC 24
Finished Oct 09 02:33:29 PM UTC 24
Peak memory 177728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1034426488 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.1034426488
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/24.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.830361022
Short name T47
Test name
Test status
Simulation time 1483490000 ps
CPU time 2.24 seconds
Started Oct 09 02:33:19 PM UTC 24
Finished Oct 09 02:33:34 PM UTC 24
Peak memory 177724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=830361022 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g
al.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.830361022
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/25.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.1568453986
Short name T46
Test name
Test status
Simulation time 1458170000 ps
CPU time 2.41 seconds
Started Oct 09 02:33:19 PM UTC 24
Finished Oct 09 02:33:33 PM UTC 24
Peak memory 177728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1568453986 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.1568453986
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/26.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.3750496434
Short name T48
Test name
Test status
Simulation time 1489190000 ps
CPU time 2.1 seconds
Started Oct 09 02:33:20 PM UTC 24
Finished Oct 09 02:33:35 PM UTC 24
Peak memory 177728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3750496434 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.3750496434
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/27.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.3789349218
Short name T49
Test name
Test status
Simulation time 1323150000 ps
CPU time 2.08 seconds
Started Oct 09 02:33:22 PM UTC 24
Finished Oct 09 02:33:35 PM UTC 24
Peak memory 177728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3789349218 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.3789349218
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/28.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.3238393214
Short name T51
Test name
Test status
Simulation time 1528110000 ps
CPU time 2.38 seconds
Started Oct 09 02:33:22 PM UTC 24
Finished Oct 09 02:33:37 PM UTC 24
Peak memory 177728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3238393214 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.3238393214
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/29.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.316754311
Short name T11
Test name
Test status
Simulation time 1510450000 ps
CPU time 2.39 seconds
Started Oct 09 02:32:53 PM UTC 24
Finished Oct 09 02:33:08 PM UTC 24
Peak memory 177760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=316754311 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g
al.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.316754311
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/3.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.3965968342
Short name T50
Test name
Test status
Simulation time 1315170000 ps
CPU time 2.14 seconds
Started Oct 09 02:33:24 PM UTC 24
Finished Oct 09 02:33:37 PM UTC 24
Peak memory 177728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3965968342 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.3965968342
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/30.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.1454337698
Short name T54
Test name
Test status
Simulation time 1530050000 ps
CPU time 2.27 seconds
Started Oct 09 02:33:24 PM UTC 24
Finished Oct 09 02:33:39 PM UTC 24
Peak memory 177728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1454337698 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.1454337698
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/31.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.1298797818
Short name T52
Test name
Test status
Simulation time 1259430000 ps
CPU time 2.14 seconds
Started Oct 09 02:33:25 PM UTC 24
Finished Oct 09 02:33:38 PM UTC 24
Peak memory 177728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1298797818 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.1298797818
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/32.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.2378637759
Short name T55
Test name
Test status
Simulation time 1438810000 ps
CPU time 2.29 seconds
Started Oct 09 02:33:25 PM UTC 24
Finished Oct 09 02:33:39 PM UTC 24
Peak memory 177728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2378637759 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.2378637759
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/33.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.2050512814
Short name T53
Test name
Test status
Simulation time 1353890000 ps
CPU time 2.21 seconds
Started Oct 09 02:33:25 PM UTC 24
Finished Oct 09 02:33:38 PM UTC 24
Peak memory 177728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2050512814 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.2050512814
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/34.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.1662926519
Short name T58
Test name
Test status
Simulation time 1593970000 ps
CPU time 2.47 seconds
Started Oct 09 02:33:25 PM UTC 24
Finished Oct 09 02:33:41 PM UTC 24
Peak memory 177728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1662926519 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.1662926519
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/35.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.740502541
Short name T56
Test name
Test status
Simulation time 1448710000 ps
CPU time 2.41 seconds
Started Oct 09 02:33:26 PM UTC 24
Finished Oct 09 02:33:40 PM UTC 24
Peak memory 177724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=740502541 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g
al.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.740502541
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/36.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.874381028
Short name T59
Test name
Test status
Simulation time 1518870000 ps
CPU time 2.4 seconds
Started Oct 09 02:33:26 PM UTC 24
Finished Oct 09 02:33:41 PM UTC 24
Peak memory 177724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=874381028 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g
al.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.874381028
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/37.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.2013748464
Short name T57
Test name
Test status
Simulation time 1323210000 ps
CPU time 2.2 seconds
Started Oct 09 02:33:27 PM UTC 24
Finished Oct 09 02:33:41 PM UTC 24
Peak memory 177728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2013748464 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.2013748464
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/38.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.345856898
Short name T60
Test name
Test status
Simulation time 1491690000 ps
CPU time 2.45 seconds
Started Oct 09 02:33:29 PM UTC 24
Finished Oct 09 02:33:44 PM UTC 24
Peak memory 177724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=345856898 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g
al.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.345856898
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/39.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.4127785792
Short name T13
Test name
Test status
Simulation time 1568490000 ps
CPU time 2.37 seconds
Started Oct 09 02:32:53 PM UTC 24
Finished Oct 09 02:33:08 PM UTC 24
Peak memory 177728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127785792 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.4127785792
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/4.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.2693540427
Short name T62
Test name
Test status
Simulation time 1584410000 ps
CPU time 2.56 seconds
Started Oct 09 02:33:34 PM UTC 24
Finished Oct 09 02:33:50 PM UTC 24
Peak memory 177728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2693540427 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.2693540427
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/40.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.1775761628
Short name T61
Test name
Test status
Simulation time 1475530000 ps
CPU time 2.37 seconds
Started Oct 09 02:33:34 PM UTC 24
Finished Oct 09 02:33:49 PM UTC 24
Peak memory 177728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1775761628 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.1775761628
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/41.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.1354389962
Short name T63
Test name
Test status
Simulation time 1520970000 ps
CPU time 2.27 seconds
Started Oct 09 02:33:36 PM UTC 24
Finished Oct 09 02:33:50 PM UTC 24
Peak memory 177728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1354389962 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.1354389962
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/42.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.2384418090
Short name T64
Test name
Test status
Simulation time 1523150000 ps
CPU time 2.29 seconds
Started Oct 09 02:33:37 PM UTC 24
Finished Oct 09 02:33:52 PM UTC 24
Peak memory 177728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2384418090 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.2384418090
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/43.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.438386577
Short name T66
Test name
Test status
Simulation time 1561670000 ps
CPU time 2.35 seconds
Started Oct 09 02:33:38 PM UTC 24
Finished Oct 09 02:33:53 PM UTC 24
Peak memory 177724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=438386577 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g
al.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.438386577
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/44.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.1864979620
Short name T65
Test name
Test status
Simulation time 1432550000 ps
CPU time 2.27 seconds
Started Oct 09 02:33:38 PM UTC 24
Finished Oct 09 02:33:52 PM UTC 24
Peak memory 177728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1864979620 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.1864979620
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/45.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.3707463084
Short name T68
Test name
Test status
Simulation time 1514230000 ps
CPU time 2.31 seconds
Started Oct 09 02:33:39 PM UTC 24
Finished Oct 09 02:33:54 PM UTC 24
Peak memory 177728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3707463084 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.3707463084
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/46.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.1099188629
Short name T69
Test name
Test status
Simulation time 1588450000 ps
CPU time 2.43 seconds
Started Oct 09 02:33:39 PM UTC 24
Finished Oct 09 02:33:55 PM UTC 24
Peak memory 177728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1099188629 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.1099188629
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/47.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.2437966229
Short name T67
Test name
Test status
Simulation time 1329910000 ps
CPU time 2.14 seconds
Started Oct 09 02:33:40 PM UTC 24
Finished Oct 09 02:33:54 PM UTC 24
Peak memory 177728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2437966229 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.2437966229
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/48.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.49962062
Short name T70
Test name
Test status
Simulation time 1475770000 ps
CPU time 2.35 seconds
Started Oct 09 02:33:40 PM UTC 24
Finished Oct 09 02:33:55 PM UTC 24
Peak memory 177728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=49962062 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ga
l.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.49962062
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/49.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.2481205678
Short name T2
Test name
Test status
Simulation time 1354890000 ps
CPU time 2.34 seconds
Started Oct 09 02:32:53 PM UTC 24
Finished Oct 09 02:33:07 PM UTC 24
Peak memory 177728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2481205678 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.2481205678
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/5.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.2696590694
Short name T1
Test name
Test status
Simulation time 1185710000 ps
CPU time 2.08 seconds
Started Oct 09 02:32:53 PM UTC 24
Finished Oct 09 02:33:05 PM UTC 24
Peak memory 177792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2696590694 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.2696590694
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/6.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.2505671907
Short name T12
Test name
Test status
Simulation time 1503810000 ps
CPU time 2.3 seconds
Started Oct 09 02:32:53 PM UTC 24
Finished Oct 09 02:33:08 PM UTC 24
Peak memory 177728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2505671907 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.2505671907
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/7.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.505899111
Short name T7
Test name
Test status
Simulation time 1376490000 ps
CPU time 2.2 seconds
Started Oct 09 02:32:53 PM UTC 24
Finished Oct 09 02:33:07 PM UTC 24
Peak memory 177760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=505899111 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g
al.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.505899111
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/8.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.1017526263
Short name T10
Test name
Test status
Simulation time 1464750000 ps
CPU time 2.53 seconds
Started Oct 09 02:32:53 PM UTC 24
Finished Oct 09 02:33:08 PM UTC 24
Peak memory 177728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1017526263 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.1017526263
Directory /workspaces/repo/scratch/os_regression_2024_10_08/prim_lfsr-sim-vcs/9.prim_lfsr_gal_smoke/latest
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