| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 98.31 | 100.00 | 96.55 | 100.00 | 100.00 | 95.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 87.31 | 87.31 | 100.00 | 100.00 | 96.55 | 96.55 | 100.00 | 100.00 | 100.00 | 100.00 | 40.00 | 40.00 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.2421200060 | ||
| 95.31 | 8.00 | 100.00 | 0.00 | 96.55 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 80.00 | 40.00 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.1594214455 | ||
| 96.81 | 1.50 | 100.00 | 0.00 | 96.55 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 87.50 | 7.50 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.340458995 | ||
| 98.31 | 1.50 | 100.00 | 0.00 | 96.55 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 95.00 | 7.50 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.2832750253 | ||
| Name |
|---|
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.2945964247 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.2468671256 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.2449577718 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.502715397 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.948740646 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.480755949 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.379988346 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.3201180664 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.2428700432 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.964357373 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.1391584053 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.2968690924 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.1710007301 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.4243836397 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.1719155674 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.999630356 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.1936228380 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.2521463418 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.2762836236 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.2841881609 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.42577970 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.4294531907 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.1173496361 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.1448056133 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.1000322904 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.3604916093 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.1502633834 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.2077831350 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.3009393886 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.1936433440 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.2185180941 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.4017828360 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.3263086528 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.839384018 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.924150746 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.624389045 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.4141276623 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.775813260 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.3390671072 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.3262156609 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.2578743542 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.1952524564 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.614541444 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.3689158373 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.3278080359 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.1223942727 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.2205411989 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.3665197555 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.1672072182 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.1165309980 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.3492558005 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.2142300787 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.3219124549 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.4098863935 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.2738680349 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.1878281815 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.742309456 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.2914267573 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.3136638140 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.374732883 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.1119170057 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.3091213768 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.64288791 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.1662416907 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.2563898143 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.1397960809 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.2978849901 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.15476890 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.3225521529 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.2012468942 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.2092676237 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.1554602661 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.3785502542 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.1158201742 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.1922273442 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.117302843 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.1801876596 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.1455795292 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.2661949588 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.1679627548 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3931803686 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.383283825 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.2968214518 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.1381300549 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.3273870680 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.2010911345 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.1209344464 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.1762377940 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.872775597 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.3556964099 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.3299996981 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1976841655 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.1760972726 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.145143980 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.3659076036 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.40025761 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.1136743020 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.258151057 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.3235933352 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.1905347082 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.5313627 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.2211838644 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.1686764851 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.3133768004 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.3793966146 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.1995794307 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.2607823771 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.244864711 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.1849427437 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.3322878288 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.1360818868 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.4053054619 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.423557460 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.1115585264 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.2575330010 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.2918476647 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.1963285875 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.2876088663 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.3818178474 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.871063692 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.2012105211 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.1471033498 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.3815762823 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.1955255817 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.4064650210 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.2506264325 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.3808460050 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.3504911824 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1082767506 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.787275767 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.53557338 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.4237572872 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.2222682778 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.1425734109 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.1350053417 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.618584227 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.2077052667 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.3446391397 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.2451982918 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.3962597827 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.529309775 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.2500759439 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.3821454848 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.1029469334 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.1373090584 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.2607988451 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2500090111 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.3229014294 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.156321888 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.1675245228 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.3332097119 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.1679808887 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.1563067253 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.687397369 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.3080385961 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.3570857180 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.490409252 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.3101691244 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.3262043188 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.1537756549 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.1344836783 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.1662900235 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.1092318847 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.797812898 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.1964393405 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.2106372413 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.905621374 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.3460429713 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.3051451327 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.2194844167 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.3619383264 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.1638019031 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.3193797820 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.1126876448 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.1973160944 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.2104223730 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.944871101 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.2055655755 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.90253073 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.1516592570 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.4073544001 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.692654112 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.3128381048 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.180996113 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.2410999769 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.3867052227 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.4196741152 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.2459971087 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.801598765 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.350591641 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.1082957984 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.3442451201 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.1874095174 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.2384077709 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.3154975522 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.2022974333 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.2421200060 | Oct 12 11:25:28 AM UTC 24 | Oct 12 11:25:38 AM UTC 24 | 1585970000 ps | ||
| T2 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.2194844167 | Oct 12 11:25:32 AM UTC 24 | Oct 12 11:25:40 AM UTC 24 | 1151890000 ps | ||
| T3 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.3262043188 | Oct 12 11:25:31 AM UTC 24 | Oct 12 11:25:40 AM UTC 24 | 1357750000 ps | ||
| T7 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.3229014294 | Oct 12 11:25:31 AM UTC 24 | Oct 12 11:25:41 AM UTC 24 | 1483210000 ps | ||
| T8 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.4073544001 | Oct 12 11:25:33 AM UTC 24 | Oct 12 11:25:43 AM UTC 24 | 1551250000 ps | ||
| T9 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.3442451201 | Oct 12 11:25:35 AM UTC 24 | Oct 12 11:25:45 AM UTC 24 | 1503250000 ps | ||
| T10 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.2384077709 | Oct 12 11:25:39 AM UTC 24 | Oct 12 11:25:48 AM UTC 24 | 1225830000 ps | ||
| T11 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.1874095174 | Oct 12 11:25:38 AM UTC 24 | Oct 12 11:25:48 AM UTC 24 | 1419130000 ps | ||
| T12 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.2022974333 | Oct 12 11:25:41 AM UTC 24 | Oct 12 11:25:49 AM UTC 24 | 1125350000 ps | ||
| T13 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.156321888 | Oct 12 11:25:41 AM UTC 24 | Oct 12 11:25:51 AM UTC 24 | 1413230000 ps | ||
| T41 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.3154975522 | Oct 12 11:25:41 AM UTC 24 | Oct 12 11:25:51 AM UTC 24 | 1525630000 ps | ||
| T42 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.1675245228 | Oct 12 11:25:43 AM UTC 24 | Oct 12 11:25:54 AM UTC 24 | 1505870000 ps | ||
| T43 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.3332097119 | Oct 12 11:25:44 AM UTC 24 | Oct 12 11:25:54 AM UTC 24 | 1570970000 ps | ||
| T44 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.1679808887 | Oct 12 11:25:46 AM UTC 24 | Oct 12 11:25:56 AM UTC 24 | 1540830000 ps | ||
| T45 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.687397369 | Oct 12 11:25:49 AM UTC 24 | Oct 12 11:25:58 AM UTC 24 | 1315570000 ps | ||
| T46 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.3080385961 | Oct 12 11:25:49 AM UTC 24 | Oct 12 11:25:59 AM UTC 24 | 1441450000 ps | ||
| T47 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.1563067253 | Oct 12 11:25:49 AM UTC 24 | Oct 12 11:25:59 AM UTC 24 | 1533890000 ps | ||
| T48 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.3570857180 | Oct 12 11:25:50 AM UTC 24 | Oct 12 11:25:59 AM UTC 24 | 1407750000 ps | ||
| T49 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.490409252 | Oct 12 11:25:50 AM UTC 24 | Oct 12 11:26:00 AM UTC 24 | 1542050000 ps | ||
| T50 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.3101691244 | Oct 12 11:25:52 AM UTC 24 | Oct 12 11:26:01 AM UTC 24 | 1428290000 ps | ||
| T51 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.1537756549 | Oct 12 11:25:52 AM UTC 24 | Oct 12 11:26:02 AM UTC 24 | 1438550000 ps | ||
| T52 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.1344836783 | Oct 12 11:25:53 AM UTC 24 | Oct 12 11:26:03 AM UTC 24 | 1525330000 ps | ||
| T53 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.1092318847 | Oct 12 11:25:55 AM UTC 24 | Oct 12 11:26:04 AM UTC 24 | 1299750000 ps | ||
| T54 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.1662900235 | Oct 12 11:25:54 AM UTC 24 | Oct 12 11:26:05 AM UTC 24 | 1544470000 ps | ||
| T55 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.797812898 | Oct 12 11:25:56 AM UTC 24 | Oct 12 11:26:06 AM UTC 24 | 1507690000 ps | ||
| T56 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.1964393405 | Oct 12 11:25:58 AM UTC 24 | Oct 12 11:26:08 AM UTC 24 | 1256710000 ps | ||
| T57 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.3051451327 | Oct 12 11:26:00 AM UTC 24 | Oct 12 11:26:09 AM UTC 24 | 1273050000 ps | ||
| T58 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.2106372413 | Oct 12 11:25:58 AM UTC 24 | Oct 12 11:26:09 AM UTC 24 | 1567950000 ps | ||
| T59 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.3460429713 | Oct 12 11:26:00 AM UTC 24 | Oct 12 11:26:10 AM UTC 24 | 1479150000 ps | ||
| T60 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.905621374 | Oct 12 11:26:00 AM UTC 24 | Oct 12 11:26:10 AM UTC 24 | 1516310000 ps | ||
| T61 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.3619383264 | Oct 12 11:26:01 AM UTC 24 | Oct 12 11:26:11 AM UTC 24 | 1442830000 ps | ||
| T62 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.1638019031 | Oct 12 11:26:02 AM UTC 24 | Oct 12 11:26:12 AM UTC 24 | 1440530000 ps | ||
| T63 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.3193797820 | Oct 12 11:26:03 AM UTC 24 | Oct 12 11:26:13 AM UTC 24 | 1437990000 ps | ||
| T64 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.2104223730 | Oct 12 11:26:05 AM UTC 24 | Oct 12 11:26:14 AM UTC 24 | 1230950000 ps | ||
| T65 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.1126876448 | Oct 12 11:26:04 AM UTC 24 | Oct 12 11:26:14 AM UTC 24 | 1429250000 ps | ||
| T66 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.1973160944 | Oct 12 11:26:05 AM UTC 24 | Oct 12 11:26:14 AM UTC 24 | 1363690000 ps | ||
| T67 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.90253073 | Oct 12 11:26:07 AM UTC 24 | Oct 12 11:26:16 AM UTC 24 | 1311690000 ps | ||
| T68 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.1516592570 | Oct 12 11:26:07 AM UTC 24 | Oct 12 11:26:17 AM UTC 24 | 1376070000 ps | ||
| T69 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.944871101 | Oct 12 11:26:07 AM UTC 24 | Oct 12 11:26:17 AM UTC 24 | 1433190000 ps | ||
| T70 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.2055655755 | Oct 12 11:26:07 AM UTC 24 | Oct 12 11:26:17 AM UTC 24 | 1494150000 ps | ||
| T71 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.3128381048 | Oct 12 11:26:08 AM UTC 24 | Oct 12 11:26:18 AM UTC 24 | 1476210000 ps | ||
| T72 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.692654112 | Oct 12 11:26:08 AM UTC 24 | Oct 12 11:26:19 AM UTC 24 | 1614490000 ps | ||
| T73 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.180996113 | Oct 12 11:26:09 AM UTC 24 | Oct 12 11:26:19 AM UTC 24 | 1460830000 ps | ||
| T74 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.2410999769 | Oct 12 11:26:10 AM UTC 24 | Oct 12 11:26:21 AM UTC 24 | 1473690000 ps | ||
| T75 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.4196741152 | Oct 12 11:26:13 AM UTC 24 | Oct 12 11:26:22 AM UTC 24 | 1085610000 ps | ||
| T76 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.1082957984 | Oct 12 11:26:14 AM UTC 24 | Oct 12 11:26:23 AM UTC 24 | 1161950000 ps | ||
| T77 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.3867052227 | Oct 12 11:26:13 AM UTC 24 | Oct 12 11:26:24 AM UTC 24 | 1479150000 ps | ||
| T78 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.2459971087 | Oct 12 11:26:13 AM UTC 24 | Oct 12 11:26:24 AM UTC 24 | 1470530000 ps | ||
| T79 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.801598765 | Oct 12 11:26:13 AM UTC 24 | Oct 12 11:26:24 AM UTC 24 | 1474730000 ps | ||
| T80 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.350591641 | Oct 12 11:26:14 AM UTC 24 | Oct 12 11:26:24 AM UTC 24 | 1381150000 ps | ||
| T14 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.1165309980 | Oct 12 10:32:57 AM UTC 24 | Oct 12 11:15:15 AM UTC 24 | 336577130000 ps | ||
| T15 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.1594214455 | Oct 12 10:32:42 AM UTC 24 | Oct 12 11:15:23 AM UTC 24 | 336647870000 ps | ||
| T16 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.1119170057 | Oct 12 10:33:19 AM UTC 24 | Oct 12 11:15:29 AM UTC 24 | 336389210000 ps | ||
| T17 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.1554602661 | Oct 12 10:33:35 AM UTC 24 | Oct 12 11:15:39 AM UTC 24 | 336542690000 ps | ||
| T18 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.145143980 | Oct 12 10:34:46 AM UTC 24 | Oct 12 11:16:28 AM UTC 24 | 336519530000 ps | ||
| T19 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.2968214518 | Oct 12 10:34:44 AM UTC 24 | Oct 12 11:16:39 AM UTC 24 | 336313330000 ps | ||
| T20 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.3659076036 | Oct 12 10:34:52 AM UTC 24 | Oct 12 11:16:47 AM UTC 24 | 336379190000 ps | ||
| T21 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.40025761 | Oct 12 10:35:10 AM UTC 24 | Oct 12 11:17:06 AM UTC 24 | 336850470000 ps | ||
| T22 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.1136743020 | Oct 12 10:35:41 AM UTC 24 | Oct 12 11:17:29 AM UTC 24 | 336490770000 ps | ||
| T23 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.258151057 | Oct 12 10:35:45 AM UTC 24 | Oct 12 11:17:33 AM UTC 24 | 336844810000 ps | ||
| T81 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.3492558005 | Oct 12 10:36:17 AM UTC 24 | Oct 12 11:17:40 AM UTC 24 | 336804190000 ps | ||
| T82 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.2142300787 | Oct 12 10:36:17 AM UTC 24 | Oct 12 11:17:42 AM UTC 24 | 336899950000 ps | ||
| T83 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.3219124549 | Oct 12 10:36:45 AM UTC 24 | Oct 12 11:18:05 AM UTC 24 | 336425090000 ps | ||
| T84 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.4098863935 | Oct 12 10:37:22 AM UTC 24 | Oct 12 11:18:32 AM UTC 24 | 336876250000 ps | ||
| T85 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.2738680349 | Oct 12 10:37:53 AM UTC 24 | Oct 12 11:18:53 AM UTC 24 | 336397930000 ps | ||
| T86 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.1878281815 | Oct 12 10:38:41 AM UTC 24 | Oct 12 11:19:30 AM UTC 24 | 336673610000 ps | ||
| T87 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.742309456 | Oct 12 10:39:02 AM UTC 24 | Oct 12 11:20:04 AM UTC 24 | 336385650000 ps | ||
| T88 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.2914267573 | Oct 12 10:39:18 AM UTC 24 | Oct 12 11:20:05 AM UTC 24 | 337169330000 ps | ||
| T89 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.3136638140 | Oct 12 10:39:44 AM UTC 24 | Oct 12 11:20:25 AM UTC 24 | 336974510000 ps | ||
| T90 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.374732883 | Oct 12 10:39:54 AM UTC 24 | Oct 12 11:20:35 AM UTC 24 | 337035170000 ps | ||
| T91 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.3091213768 | Oct 12 10:41:42 AM UTC 24 | Oct 12 11:22:24 AM UTC 24 | 337054750000 ps | ||
| T92 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.64288791 | Oct 12 10:42:21 AM UTC 24 | Oct 12 11:22:56 AM UTC 24 | 336732830000 ps | ||
| T93 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.1662416907 | Oct 12 10:43:01 AM UTC 24 | Oct 12 11:23:27 AM UTC 24 | 336592470000 ps | ||
| T94 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.2563898143 | Oct 12 10:43:36 AM UTC 24 | Oct 12 11:23:41 AM UTC 24 | 337073910000 ps | ||
| T95 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.1397960809 | Oct 12 10:44:47 AM UTC 24 | Oct 12 11:24:21 AM UTC 24 | 336588310000 ps | ||
| T96 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.2978849901 | Oct 12 10:45:02 AM UTC 24 | Oct 12 11:24:40 AM UTC 24 | 336578870000 ps | ||
| T97 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.15476890 | Oct 12 10:46:04 AM UTC 24 | Oct 12 11:25:18 AM UTC 24 | 336549910000 ps | ||
| T98 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.3225521529 | Oct 12 10:46:23 AM UTC 24 | Oct 12 11:25:18 AM UTC 24 | 336445930000 ps | ||
| T99 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.2012468942 | Oct 12 10:46:23 AM UTC 24 | Oct 12 11:25:32 AM UTC 24 | 336682210000 ps | ||
| T100 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.2092676237 | Oct 12 10:47:19 AM UTC 24 | Oct 12 11:26:07 AM UTC 24 | 336847390000 ps | ||
| T101 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.3785502542 | Oct 12 10:48:50 AM UTC 24 | Oct 12 11:27:08 AM UTC 24 | 336410830000 ps | ||
| T102 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.1158201742 | Oct 12 10:49:05 AM UTC 24 | Oct 12 11:27:25 AM UTC 24 | 336727030000 ps | ||
| T103 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.1922273442 | Oct 12 10:50:49 AM UTC 24 | Oct 12 11:29:06 AM UTC 24 | 336951990000 ps | ||
| T104 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.117302843 | Oct 12 10:50:56 AM UTC 24 | Oct 12 11:29:34 AM UTC 24 | 336474950000 ps | ||
| T105 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.1801876596 | Oct 12 10:50:58 AM UTC 24 | Oct 12 11:29:39 AM UTC 24 | 336648890000 ps | ||
| T106 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.1455795292 | Oct 12 10:51:48 AM UTC 24 | Oct 12 11:30:13 AM UTC 24 | 337055950000 ps | ||
| T107 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.2661949588 | Oct 12 10:54:28 AM UTC 24 | Oct 12 11:32:26 AM UTC 24 | 337071170000 ps | ||
| T108 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.1679627548 | Oct 12 10:55:24 AM UTC 24 | Oct 12 11:33:24 AM UTC 24 | 336516870000 ps | ||
| T109 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3931803686 | Oct 12 10:55:40 AM UTC 24 | Oct 12 11:33:28 AM UTC 24 | 336666690000 ps | ||
| T110 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.383283825 | Oct 12 10:55:51 AM UTC 24 | Oct 12 11:33:54 AM UTC 24 | 336885270000 ps | ||
| T111 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.1381300549 | Oct 12 10:57:25 AM UTC 24 | Oct 12 11:34:57 AM UTC 24 | 336777210000 ps | ||
| T112 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.3273870680 | Oct 12 10:58:13 AM UTC 24 | Oct 12 11:35:39 AM UTC 24 | 336639110000 ps | ||
| T113 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.2010911345 | Oct 12 10:58:42 AM UTC 24 | Oct 12 11:36:11 AM UTC 24 | 336777930000 ps | ||
| T114 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.1209344464 | Oct 12 10:59:09 AM UTC 24 | Oct 12 11:36:57 AM UTC 24 | 337060630000 ps | ||
| T115 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.1762377940 | Oct 12 11:00:15 AM UTC 24 | Oct 12 11:37:45 AM UTC 24 | 336353150000 ps | ||
| T116 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.872775597 | Oct 12 11:00:35 AM UTC 24 | Oct 12 11:38:11 AM UTC 24 | 336815570000 ps | ||
| T117 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.3556964099 | Oct 12 11:01:26 AM UTC 24 | Oct 12 11:38:47 AM UTC 24 | 336970170000 ps | ||
| T118 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.3299996981 | Oct 12 11:03:15 AM UTC 24 | Oct 12 11:40:23 AM UTC 24 | 336737850000 ps | ||
| T119 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1976841655 | Oct 12 11:03:17 AM UTC 24 | Oct 12 11:40:36 AM UTC 24 | 336633570000 ps | ||
| T120 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.1760972726 | Oct 12 11:03:27 AM UTC 24 | Oct 12 11:40:42 AM UTC 24 | 336720250000 ps | ||
| T4 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.2832750253 | Oct 12 11:22:56 AM UTC 24 | Oct 12 11:23:07 AM UTC 24 | 1360230000 ps | ||
| T5 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.4237572872 | Oct 12 11:22:57 AM UTC 24 | Oct 12 11:23:08 AM UTC 24 | 1253810000 ps | ||
| T6 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.2607988451 | Oct 12 11:22:58 AM UTC 24 | Oct 12 11:23:08 AM UTC 24 | 1167610000 ps | ||
| T24 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.3821454848 | Oct 12 11:22:57 AM UTC 24 | Oct 12 11:23:09 AM UTC 24 | 1409710000 ps | ||
| T25 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.3235933352 | Oct 12 11:22:57 AM UTC 24 | Oct 12 11:23:10 AM UTC 24 | 1567830000 ps | ||
| T26 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.3322878288 | Oct 12 11:22:57 AM UTC 24 | Oct 12 11:23:10 AM UTC 24 | 1591330000 ps | ||
| T27 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.2012105211 | Oct 12 11:22:57 AM UTC 24 | Oct 12 11:23:10 AM UTC 24 | 1562770000 ps | ||
| T28 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.1373090584 | Oct 12 11:22:58 AM UTC 24 | Oct 12 11:23:11 AM UTC 24 | 1467130000 ps | ||
| T29 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.1029469334 | Oct 12 11:22:58 AM UTC 24 | Oct 12 11:23:11 AM UTC 24 | 1558850000 ps | ||
| T30 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2500090111 | Oct 12 11:22:59 AM UTC 24 | Oct 12 11:23:12 AM UTC 24 | 1448150000 ps | ||
| T121 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.1905347082 | Oct 12 11:23:01 AM UTC 24 | Oct 12 11:23:13 AM UTC 24 | 1478850000 ps | ||
| T122 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.5313627 | Oct 12 11:23:02 AM UTC 24 | Oct 12 11:23:14 AM UTC 24 | 1482250000 ps | ||
| T123 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.2211838644 | Oct 12 11:23:08 AM UTC 24 | Oct 12 11:23:20 AM UTC 24 | 1468110000 ps | ||
| T124 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.1686764851 | Oct 12 11:23:09 AM UTC 24 | Oct 12 11:23:21 AM UTC 24 | 1452210000 ps | ||
| T125 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.3133768004 | Oct 12 11:23:09 AM UTC 24 | Oct 12 11:23:21 AM UTC 24 | 1536590000 ps | ||
| T126 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.1849427437 | Oct 12 11:23:11 AM UTC 24 | Oct 12 11:23:22 AM UTC 24 | 1273430000 ps | ||
| T127 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.3793966146 | Oct 12 11:23:10 AM UTC 24 | Oct 12 11:23:22 AM UTC 24 | 1421150000 ps | ||
| T128 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.2607823771 | Oct 12 11:23:11 AM UTC 24 | Oct 12 11:23:23 AM UTC 24 | 1447790000 ps | ||
| T129 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.244864711 | Oct 12 11:23:11 AM UTC 24 | Oct 12 11:23:23 AM UTC 24 | 1476910000 ps | ||
| T130 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.4053054619 | Oct 12 11:23:12 AM UTC 24 | Oct 12 11:23:24 AM UTC 24 | 1391070000 ps | ||
| T131 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.1995794307 | Oct 12 11:23:11 AM UTC 24 | Oct 12 11:23:24 AM UTC 24 | 1572570000 ps | ||
| T132 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.1360818868 | Oct 12 11:23:12 AM UTC 24 | Oct 12 11:23:24 AM UTC 24 | 1473230000 ps | ||
| T133 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.423557460 | Oct 12 11:23:14 AM UTC 24 | Oct 12 11:23:26 AM UTC 24 | 1444050000 ps | ||
| T134 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.1115585264 | Oct 12 11:23:15 AM UTC 24 | Oct 12 11:23:28 AM UTC 24 | 1474630000 ps | ||
| T135 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.2575330010 | Oct 12 11:23:20 AM UTC 24 | Oct 12 11:23:30 AM UTC 24 | 1137650000 ps | ||
| T136 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.2918476647 | Oct 12 11:23:21 AM UTC 24 | Oct 12 11:23:33 AM UTC 24 | 1360690000 ps | ||
| T137 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.1471033498 | Oct 12 11:23:24 AM UTC 24 | Oct 12 11:23:34 AM UTC 24 | 1244050000 ps | ||
| T138 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.1963285875 | Oct 12 11:23:23 AM UTC 24 | Oct 12 11:23:35 AM UTC 24 | 1458350000 ps | ||
| T139 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.2876088663 | Oct 12 11:23:23 AM UTC 24 | Oct 12 11:23:35 AM UTC 24 | 1532810000 ps | ||
| T140 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.871063692 | Oct 12 11:23:24 AM UTC 24 | Oct 12 11:23:36 AM UTC 24 | 1440790000 ps | ||
| T141 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.3818178474 | Oct 12 11:23:23 AM UTC 24 | Oct 12 11:23:36 AM UTC 24 | 1590150000 ps | ||
| T142 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.4064650210 | Oct 12 11:23:25 AM UTC 24 | Oct 12 11:23:36 AM UTC 24 | 1385610000 ps | ||
| T143 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.2506264325 | Oct 12 11:23:25 AM UTC 24 | Oct 12 11:23:37 AM UTC 24 | 1459050000 ps | ||
| T144 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.1955255817 | Oct 12 11:23:25 AM UTC 24 | Oct 12 11:23:37 AM UTC 24 | 1478130000 ps | ||
| T145 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.3815762823 | Oct 12 11:23:24 AM UTC 24 | Oct 12 11:23:37 AM UTC 24 | 1641370000 ps | ||
| T146 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1082767506 | Oct 12 11:23:28 AM UTC 24 | Oct 12 11:23:40 AM UTC 24 | 1407610000 ps | ||
| T147 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.3808460050 | Oct 12 11:23:27 AM UTC 24 | Oct 12 11:23:40 AM UTC 24 | 1602830000 ps | ||
| T148 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.3504911824 | Oct 12 11:23:28 AM UTC 24 | Oct 12 11:23:40 AM UTC 24 | 1513570000 ps | ||
| T149 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.787275767 | Oct 12 11:23:31 AM UTC 24 | Oct 12 11:23:41 AM UTC 24 | 1110370000 ps | ||
| T150 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.2222682778 | Oct 12 11:23:35 AM UTC 24 | Oct 12 11:23:44 AM UTC 24 | 985750000 ps | ||
| T151 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.53557338 | Oct 12 11:23:33 AM UTC 24 | Oct 12 11:23:44 AM UTC 24 | 1362610000 ps | ||
| T152 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.1350053417 | Oct 12 11:23:36 AM UTC 24 | Oct 12 11:23:45 AM UTC 24 | 1220770000 ps | ||
| T153 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.618584227 | Oct 12 11:23:37 AM UTC 24 | Oct 12 11:23:47 AM UTC 24 | 1349870000 ps | ||
| T154 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.1425734109 | Oct 12 11:23:35 AM UTC 24 | Oct 12 11:23:48 AM UTC 24 | 1565090000 ps | ||
| T155 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.2077052667 | Oct 12 11:23:37 AM UTC 24 | Oct 12 11:23:48 AM UTC 24 | 1433090000 ps | ||
| T156 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.3962597827 | Oct 12 11:23:38 AM UTC 24 | Oct 12 11:23:48 AM UTC 24 | 1340770000 ps | ||
| T157 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.2451982918 | Oct 12 11:23:38 AM UTC 24 | Oct 12 11:23:49 AM UTC 24 | 1520950000 ps | ||
| T158 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.529309775 | Oct 12 11:23:38 AM UTC 24 | Oct 12 11:23:49 AM UTC 24 | 1524030000 ps | ||
| T159 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.3446391397 | Oct 12 11:23:38 AM UTC 24 | Oct 12 11:23:50 AM UTC 24 | 1586050000 ps | ||
| T160 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.2500759439 | Oct 12 11:23:41 AM UTC 24 | Oct 12 11:23:52 AM UTC 24 | 1518910000 ps | ||
| T31 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.340458995 | Oct 12 11:30:41 AM UTC 24 | Oct 12 12:06:42 PM UTC 24 | 336682950000 ps | ||
| T32 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.3278080359 | Oct 12 11:30:50 AM UTC 24 | Oct 12 12:06:42 PM UTC 24 | 336302270000 ps | ||
| T33 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.2945964247 | Oct 12 11:30:42 AM UTC 24 | Oct 12 12:06:43 PM UTC 24 | 336644810000 ps | ||
| T34 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.1173496361 | Oct 12 11:30:46 AM UTC 24 | Oct 12 12:06:46 PM UTC 24 | 337048890000 ps | ||
| T35 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.2968690924 | Oct 12 11:30:43 AM UTC 24 | Oct 12 12:06:46 PM UTC 24 | 336718950000 ps | ||
| T36 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.1223942727 | Oct 12 11:30:50 AM UTC 24 | Oct 12 12:06:48 PM UTC 24 | 337163150000 ps | ||
| T37 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.2205411989 | Oct 12 11:30:50 AM UTC 24 | Oct 12 12:06:48 PM UTC 24 | 336868990000 ps | ||
| T38 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.839384018 | Oct 12 11:30:48 AM UTC 24 | Oct 12 12:06:49 PM UTC 24 | 336728570000 ps | ||
| T39 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.2449577718 | Oct 12 11:30:55 AM UTC 24 | Oct 12 12:06:49 PM UTC 24 | 336383830000 ps | ||
| T40 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.948740646 | Oct 12 11:30:58 AM UTC 24 | Oct 12 12:06:56 PM UTC 24 | 336613230000 ps | ||
| T161 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.2428700432 | Oct 12 11:30:59 AM UTC 24 | Oct 12 12:06:56 PM UTC 24 | 336593730000 ps | ||
| T162 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.3665197555 | Oct 12 11:30:53 AM UTC 24 | Oct 12 12:06:57 PM UTC 24 | 336882370000 ps | ||
| T163 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.379988346 | Oct 12 11:30:58 AM UTC 24 | Oct 12 12:06:59 PM UTC 24 | 336902630000 ps | ||
| T164 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.1672072182 | Oct 12 11:30:55 AM UTC 24 | Oct 12 12:06:59 PM UTC 24 | 336535050000 ps | ||
| T165 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.964357373 | Oct 12 11:31:00 AM UTC 24 | Oct 12 12:06:59 PM UTC 24 | 336700530000 ps | ||
| T166 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.480755949 | Oct 12 11:30:58 AM UTC 24 | Oct 12 12:07:00 PM UTC 24 | 336694890000 ps | ||
| T167 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.2468671256 | Oct 12 11:30:55 AM UTC 24 | Oct 12 12:07:00 PM UTC 24 | 336701510000 ps | ||
| T168 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.502715397 | Oct 12 11:30:57 AM UTC 24 | Oct 12 12:07:00 PM UTC 24 | 336732410000 ps | ||
| T169 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.3201180664 | Oct 12 11:30:58 AM UTC 24 | Oct 12 12:07:01 PM UTC 24 | 336610050000 ps | ||
| T170 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.1710007301 | Oct 12 11:31:03 AM UTC 24 | Oct 12 12:07:02 PM UTC 24 | 336953670000 ps | ||
| T171 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.1719155674 | Oct 12 11:31:06 AM UTC 24 | Oct 12 12:07:06 PM UTC 24 | 336466970000 ps | ||
| T172 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.4243836397 | Oct 12 11:31:04 AM UTC 24 | Oct 12 12:07:07 PM UTC 24 | 336660510000 ps | ||
| T173 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.1391584053 | Oct 12 11:31:02 AM UTC 24 | Oct 12 12:07:09 PM UTC 24 | 336390670000 ps | ||
| T174 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.999630356 | Oct 12 11:32:27 AM UTC 24 | Oct 12 12:08:53 PM UTC 24 | 336514810000 ps | ||
| T175 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.1936228380 | Oct 12 11:33:20 AM UTC 24 | Oct 12 12:10:08 PM UTC 24 | 336474970000 ps | ||
| T176 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.2521463418 | Oct 12 11:33:24 AM UTC 24 | Oct 12 12:10:10 PM UTC 24 | 336889930000 ps | ||
| T177 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.2762836236 | Oct 12 11:33:29 AM UTC 24 | Oct 12 12:10:26 PM UTC 24 | 337165670000 ps | ||
| T178 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.2841881609 | Oct 12 11:33:54 AM UTC 24 | Oct 12 12:10:56 PM UTC 24 | 336555350000 ps | ||
| T179 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.42577970 | Oct 12 11:34:58 AM UTC 24 | Oct 12 12:12:18 PM UTC 24 | 336681630000 ps | ||
| T180 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.4294531907 | Oct 12 11:35:39 AM UTC 24 | Oct 12 12:13:14 PM UTC 24 | 337058710000 ps | ||
| T181 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.1448056133 | Oct 12 11:36:09 AM UTC 24 | Oct 12 12:13:53 PM UTC 24 | 336995430000 ps | ||
| T182 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.1000322904 | Oct 12 11:36:12 AM UTC 24 | Oct 12 12:14:05 PM UTC 24 | 336904270000 ps | ||
| T183 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.3604916093 | Oct 12 11:36:58 AM UTC 24 | Oct 12 12:15:00 PM UTC 24 | 336699250000 ps | ||
| T184 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.1502633834 | Oct 12 11:37:46 AM UTC 24 | Oct 12 12:16:07 PM UTC 24 | 336771010000 ps | ||
| T185 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.2077831350 | Oct 12 11:38:05 AM UTC 24 | Oct 12 12:16:37 PM UTC 24 | 336745110000 ps | ||
| T186 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.3009393886 | Oct 12 11:38:12 AM UTC 24 | Oct 12 12:16:40 PM UTC 24 | 336388630000 ps | ||
| T187 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.1936433440 | Oct 12 11:38:25 AM UTC 24 | Oct 12 12:17:01 PM UTC 24 | 336932510000 ps | ||
| T188 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.2185180941 | Oct 12 11:38:48 AM UTC 24 | Oct 12 12:17:34 PM UTC 24 | 336407110000 ps | ||
| T189 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.4017828360 | Oct 12 11:39:00 AM UTC 24 | Oct 12 12:17:52 PM UTC 24 | 336748090000 ps | ||
| T190 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.3263086528 | Oct 12 11:39:03 AM UTC 24 | Oct 12 12:18:01 PM UTC 24 | 336879230000 ps | ||
| T191 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.924150746 | Oct 12 11:39:09 AM UTC 24 | Oct 12 12:18:10 PM UTC 24 | 336884710000 ps | ||
| T192 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.624389045 | Oct 12 11:40:07 AM UTC 24 | Oct 12 12:19:20 PM UTC 24 | 336384150000 ps | ||
| T193 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.4141276623 | Oct 12 11:40:23 AM UTC 24 | Oct 12 12:19:44 PM UTC 24 | 336402490000 ps | ||
| T194 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.775813260 | Oct 12 11:40:33 AM UTC 24 | Oct 12 12:19:57 PM UTC 24 | 336661070000 ps | ||
| T195 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.3390671072 | Oct 12 11:40:37 AM UTC 24 | Oct 12 12:19:59 PM UTC 24 | 337011050000 ps | ||
| T196 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.3262156609 | Oct 12 11:40:43 AM UTC 24 | Oct 12 12:20:10 PM UTC 24 | 336658430000 ps | ||
| T197 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.2578743542 | Oct 12 11:40:58 AM UTC 24 | Oct 12 12:20:28 PM UTC 24 | 336759470000 ps | ||
| T198 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.1952524564 | Oct 12 11:41:25 AM UTC 24 | Oct 12 12:21:02 PM UTC 24 | 336572450000 ps | ||
| T199 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.614541444 | Oct 12 11:41:36 AM UTC 24 | Oct 12 12:21:19 PM UTC 24 | 336861030000 ps | ||
| T200 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.3689158373 | Oct 12 11:42:00 AM UTC 24 | Oct 12 12:21:49 PM UTC 24 | 336885250000 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.2421200060 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 1585970000 ps |
| CPU time | 2.09 seconds |
| Started | Oct 12 11:25:28 AM UTC 24 |
| Finished | Oct 12 11:25:38 AM UTC 24 |
| Peak memory | 177792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2421200060 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.2421200060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/0.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.1594214455 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 336647870000 ps |
| CPU time | 282.78 seconds |
| Started | Oct 12 10:32:42 AM UTC 24 |
| Finished | Oct 12 11:15:23 AM UTC 24 |
| Peak memory | 176524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1594214455 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.1594214455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/0.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.340458995 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 336682950000 ps |
| CPU time | 260.7 seconds |
| Started | Oct 12 11:30:41 AM UTC 24 |
| Finished | Oct 12 12:06:42 PM UTC 24 |
| Peak memory | 176600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=340458995 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.340458995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/0.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.2832750253 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 1360230000 ps |
| CPU time | 2.07 seconds |
| Started | Oct 12 11:22:56 AM UTC 24 |
| Finished | Oct 12 11:23:07 AM UTC 24 |
| Peak memory | 177832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2832750253 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.2832750253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/0.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.2945964247 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 336644810000 ps |
| CPU time | 261.12 seconds |
| Started | Oct 12 11:30:42 AM UTC 24 |
| Finished | Oct 12 12:06:43 PM UTC 24 |
| Peak memory | 176524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2945964247 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.2945964247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/1.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.2468671256 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 336701510000 ps |
| CPU time | 256.83 seconds |
| Started | Oct 12 11:30:55 AM UTC 24 |
| Finished | Oct 12 12:07:00 PM UTC 24 |
| Peak memory | 176536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2468671256 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.2468671256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/10.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.2449577718 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 336383830000 ps |
| CPU time | 266.85 seconds |
| Started | Oct 12 11:30:55 AM UTC 24 |
| Finished | Oct 12 12:06:49 PM UTC 24 |
| Peak memory | 174992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2449577718 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.2449577718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/11.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.502715397 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 336732410000 ps |
| CPU time | 259.32 seconds |
| Started | Oct 12 11:30:57 AM UTC 24 |
| Finished | Oct 12 12:07:00 PM UTC 24 |
| Peak memory | 174996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=502715397 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.502715397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/12.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.948740646 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 336613230000 ps |
| CPU time | 268.61 seconds |
| Started | Oct 12 11:30:58 AM UTC 24 |
| Finished | Oct 12 12:06:56 PM UTC 24 |
| Peak memory | 176368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=948740646 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.948740646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/13.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.480755949 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 336694890000 ps |
| CPU time | 257.29 seconds |
| Started | Oct 12 11:30:58 AM UTC 24 |
| Finished | Oct 12 12:07:00 PM UTC 24 |
| Peak memory | 174732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=480755949 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.480755949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/14.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.379988346 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 336902630000 ps |
| CPU time | 268.93 seconds |
| Started | Oct 12 11:30:58 AM UTC 24 |
| Finished | Oct 12 12:06:59 PM UTC 24 |
| Peak memory | 176536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=379988346 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.379988346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/15.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.3201180664 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 336610050000 ps |
| CPU time | 258.63 seconds |
| Started | Oct 12 11:30:58 AM UTC 24 |
| Finished | Oct 12 12:07:01 PM UTC 24 |
| Peak memory | 176536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3201180664 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.3201180664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/16.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.2428700432 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 336593730000 ps |
| CPU time | 268.09 seconds |
| Started | Oct 12 11:30:59 AM UTC 24 |
| Finished | Oct 12 12:06:56 PM UTC 24 |
| Peak memory | 176536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2428700432 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.2428700432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/17.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.964357373 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 336700530000 ps |
| CPU time | 262.2 seconds |
| Started | Oct 12 11:31:00 AM UTC 24 |
| Finished | Oct 12 12:06:59 PM UTC 24 |
| Peak memory | 176536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=964357373 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.964357373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/18.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.1391584053 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 336390670000 ps |
| CPU time | 261.08 seconds |
| Started | Oct 12 11:31:02 AM UTC 24 |
| Finished | Oct 12 12:07:09 PM UTC 24 |
| Peak memory | 174996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1391584053 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.1391584053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/19.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.2968690924 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 336718950000 ps |
| CPU time | 263.7 seconds |
| Started | Oct 12 11:30:43 AM UTC 24 |
| Finished | Oct 12 12:06:46 PM UTC 24 |
| Peak memory | 174984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2968690924 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.2968690924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/2.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.1710007301 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 336953670000 ps |
| CPU time | 267.47 seconds |
| Started | Oct 12 11:31:03 AM UTC 24 |
| Finished | Oct 12 12:07:02 PM UTC 24 |
| Peak memory | 174996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1710007301 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.1710007301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/20.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.4243836397 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 336660510000 ps |
| CPU time | 267.16 seconds |
| Started | Oct 12 11:31:04 AM UTC 24 |
| Finished | Oct 12 12:07:07 PM UTC 24 |
| Peak memory | 174996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4243836397 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.4243836397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/21.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.1719155674 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 336466970000 ps |
| CPU time | 262.87 seconds |
| Started | Oct 12 11:31:06 AM UTC 24 |
| Finished | Oct 12 12:07:06 PM UTC 24 |
| Peak memory | 176536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1719155674 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.1719155674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/22.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.999630356 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 336514810000 ps |
| CPU time | 268.7 seconds |
| Started | Oct 12 11:32:27 AM UTC 24 |
| Finished | Oct 12 12:08:53 PM UTC 24 |
| Peak memory | 176536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=999630356 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.999630356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/23.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.1936228380 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 336474970000 ps |
| CPU time | 266.56 seconds |
| Started | Oct 12 11:33:20 AM UTC 24 |
| Finished | Oct 12 12:10:08 PM UTC 24 |
| Peak memory | 176536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1936228380 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.1936228380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/24.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.2521463418 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 336889930000 ps |
| CPU time | 270.01 seconds |
| Started | Oct 12 11:33:24 AM UTC 24 |
| Finished | Oct 12 12:10:10 PM UTC 24 |
| Peak memory | 174996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2521463418 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.2521463418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/25.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.2762836236 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 337165670000 ps |
| CPU time | 259.35 seconds |
| Started | Oct 12 11:33:29 AM UTC 24 |
| Finished | Oct 12 12:10:26 PM UTC 24 |
| Peak memory | 176536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2762836236 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.2762836236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/26.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.2841881609 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 336555350000 ps |
| CPU time | 262.98 seconds |
| Started | Oct 12 11:33:54 AM UTC 24 |
| Finished | Oct 12 12:10:56 PM UTC 24 |
| Peak memory | 174996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2841881609 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.2841881609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/27.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.42577970 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 336681630000 ps |
| CPU time | 268.14 seconds |
| Started | Oct 12 11:34:58 AM UTC 24 |
| Finished | Oct 12 12:12:18 PM UTC 24 |
| Peak memory | 174984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42577970 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_ fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.42577970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/28.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.4294531907 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 337058710000 ps |
| CPU time | 265.84 seconds |
| Started | Oct 12 11:35:39 AM UTC 24 |
| Finished | Oct 12 12:13:14 PM UTC 24 |
| Peak memory | 174996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4294531907 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.4294531907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/29.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.1173496361 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 337048890000 ps |
| CPU time | 268.1 seconds |
| Started | Oct 12 11:30:46 AM UTC 24 |
| Finished | Oct 12 12:06:46 PM UTC 24 |
| Peak memory | 174984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1173496361 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.1173496361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/3.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.1448056133 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 336995430000 ps |
| CPU time | 269.43 seconds |
| Started | Oct 12 11:36:09 AM UTC 24 |
| Finished | Oct 12 12:13:53 PM UTC 24 |
| Peak memory | 176536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1448056133 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.1448056133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/30.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.1000322904 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 336904270000 ps |
| CPU time | 264.35 seconds |
| Started | Oct 12 11:36:12 AM UTC 24 |
| Finished | Oct 12 12:14:05 PM UTC 24 |
| Peak memory | 174996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1000322904 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.1000322904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/31.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.3604916093 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 336699250000 ps |
| CPU time | 264.19 seconds |
| Started | Oct 12 11:36:58 AM UTC 24 |
| Finished | Oct 12 12:15:00 PM UTC 24 |
| Peak memory | 176536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3604916093 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.3604916093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/32.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.1502633834 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 336771010000 ps |
| CPU time | 275.06 seconds |
| Started | Oct 12 11:37:46 AM UTC 24 |
| Finished | Oct 12 12:16:07 PM UTC 24 |
| Peak memory | 174996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1502633834 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.1502633834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/33.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.2077831350 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 336745110000 ps |
| CPU time | 267.62 seconds |
| Started | Oct 12 11:38:05 AM UTC 24 |
| Finished | Oct 12 12:16:37 PM UTC 24 |
| Peak memory | 174996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2077831350 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.2077831350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/34.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.3009393886 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 336388630000 ps |
| CPU time | 268.97 seconds |
| Started | Oct 12 11:38:12 AM UTC 24 |
| Finished | Oct 12 12:16:40 PM UTC 24 |
| Peak memory | 176536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3009393886 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.3009393886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/35.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.1936433440 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 336932510000 ps |
| CPU time | 272.26 seconds |
| Started | Oct 12 11:38:25 AM UTC 24 |
| Finished | Oct 12 12:17:01 PM UTC 24 |
| Peak memory | 174996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1936433440 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.1936433440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/36.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.2185180941 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 336407110000 ps |
| CPU time | 271.06 seconds |
| Started | Oct 12 11:38:48 AM UTC 24 |
| Finished | Oct 12 12:17:34 PM UTC 24 |
| Peak memory | 174996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2185180941 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.2185180941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/37.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.4017828360 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 336748090000 ps |
| CPU time | 269.25 seconds |
| Started | Oct 12 11:39:00 AM UTC 24 |
| Finished | Oct 12 12:17:52 PM UTC 24 |
| Peak memory | 174996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4017828360 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.4017828360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/38.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.3263086528 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 336879230000 ps |
| CPU time | 264.33 seconds |
| Started | Oct 12 11:39:03 AM UTC 24 |
| Finished | Oct 12 12:18:01 PM UTC 24 |
| Peak memory | 176536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3263086528 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.3263086528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/39.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.839384018 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 336728570000 ps |
| CPU time | 262.66 seconds |
| Started | Oct 12 11:30:48 AM UTC 24 |
| Finished | Oct 12 12:06:49 PM UTC 24 |
| Peak memory | 175020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=839384018 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.839384018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/4.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.924150746 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 336884710000 ps |
| CPU time | 266.17 seconds |
| Started | Oct 12 11:39:09 AM UTC 24 |
| Finished | Oct 12 12:18:10 PM UTC 24 |
| Peak memory | 176536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=924150746 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.924150746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/40.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.624389045 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 336384150000 ps |
| CPU time | 271.23 seconds |
| Started | Oct 12 11:40:07 AM UTC 24 |
| Finished | Oct 12 12:19:20 PM UTC 24 |
| Peak memory | 174976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=624389045 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.624389045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/41.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.4141276623 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 336402490000 ps |
| CPU time | 264.14 seconds |
| Started | Oct 12 11:40:23 AM UTC 24 |
| Finished | Oct 12 12:19:44 PM UTC 24 |
| Peak memory | 176536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4141276623 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.4141276623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/42.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.775813260 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 336661070000 ps |
| CPU time | 263.04 seconds |
| Started | Oct 12 11:40:33 AM UTC 24 |
| Finished | Oct 12 12:19:57 PM UTC 24 |
| Peak memory | 176536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=775813260 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.775813260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/43.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.3390671072 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 337011050000 ps |
| CPU time | 274.77 seconds |
| Started | Oct 12 11:40:37 AM UTC 24 |
| Finished | Oct 12 12:19:59 PM UTC 24 |
| Peak memory | 174996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3390671072 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.3390671072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/44.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.3262156609 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 336658430000 ps |
| CPU time | 264.81 seconds |
| Started | Oct 12 11:40:43 AM UTC 24 |
| Finished | Oct 12 12:20:10 PM UTC 24 |
| Peak memory | 176536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3262156609 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.3262156609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/45.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.2578743542 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 336759470000 ps |
| CPU time | 275.26 seconds |
| Started | Oct 12 11:40:58 AM UTC 24 |
| Finished | Oct 12 12:20:28 PM UTC 24 |
| Peak memory | 176536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2578743542 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.2578743542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/46.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.1952524564 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 336572450000 ps |
| CPU time | 275.83 seconds |
| Started | Oct 12 11:41:25 AM UTC 24 |
| Finished | Oct 12 12:21:02 PM UTC 24 |
| Peak memory | 176536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1952524564 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.1952524564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/47.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.614541444 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 336861030000 ps |
| CPU time | 274.8 seconds |
| Started | Oct 12 11:41:36 AM UTC 24 |
| Finished | Oct 12 12:21:19 PM UTC 24 |
| Peak memory | 176536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=614541444 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.614541444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/48.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.3689158373 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 336885250000 ps |
| CPU time | 269.99 seconds |
| Started | Oct 12 11:42:00 AM UTC 24 |
| Finished | Oct 12 12:21:49 PM UTC 24 |
| Peak memory | 174996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3689158373 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.3689158373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/49.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.3278080359 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 336302270000 ps |
| CPU time | 266.58 seconds |
| Started | Oct 12 11:30:50 AM UTC 24 |
| Finished | Oct 12 12:06:42 PM UTC 24 |
| Peak memory | 176524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3278080359 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.3278080359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/5.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.1223942727 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 337163150000 ps |
| CPU time | 263.84 seconds |
| Started | Oct 12 11:30:50 AM UTC 24 |
| Finished | Oct 12 12:06:48 PM UTC 24 |
| Peak memory | 174984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1223942727 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.1223942727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/6.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.2205411989 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 336868990000 ps |
| CPU time | 268.49 seconds |
| Started | Oct 12 11:30:50 AM UTC 24 |
| Finished | Oct 12 12:06:48 PM UTC 24 |
| Peak memory | 176524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2205411989 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.2205411989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/7.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.3665197555 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 336882370000 ps |
| CPU time | 260.29 seconds |
| Started | Oct 12 11:30:53 AM UTC 24 |
| Finished | Oct 12 12:06:57 PM UTC 24 |
| Peak memory | 176524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3665197555 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.3665197555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/8.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.1672072182 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 336535050000 ps |
| CPU time | 258.3 seconds |
| Started | Oct 12 11:30:55 AM UTC 24 |
| Finished | Oct 12 12:06:59 PM UTC 24 |
| Peak memory | 176524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672072182 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.1672072182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/9.prim_lfsr_fib_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.1165309980 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 336577130000 ps |
| CPU time | 284.38 seconds |
| Started | Oct 12 10:32:57 AM UTC 24 |
| Finished | Oct 12 11:15:15 AM UTC 24 |
| Peak memory | 176588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1165309980 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.1165309980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/1.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.3492558005 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 336804190000 ps |
| CPU time | 276.72 seconds |
| Started | Oct 12 10:36:17 AM UTC 24 |
| Finished | Oct 12 11:17:40 AM UTC 24 |
| Peak memory | 176536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3492558005 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.3492558005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/10.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.2142300787 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 336899950000 ps |
| CPU time | 277.83 seconds |
| Started | Oct 12 10:36:17 AM UTC 24 |
| Finished | Oct 12 11:17:42 AM UTC 24 |
| Peak memory | 176536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2142300787 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.2142300787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/11.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.3219124549 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 336425090000 ps |
| CPU time | 275.08 seconds |
| Started | Oct 12 10:36:45 AM UTC 24 |
| Finished | Oct 12 11:18:05 AM UTC 24 |
| Peak memory | 174996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3219124549 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.3219124549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/12.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.4098863935 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 336876250000 ps |
| CPU time | 274.98 seconds |
| Started | Oct 12 10:37:22 AM UTC 24 |
| Finished | Oct 12 11:18:32 AM UTC 24 |
| Peak memory | 176536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4098863935 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.4098863935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/13.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.2738680349 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 336397930000 ps |
| CPU time | 274.08 seconds |
| Started | Oct 12 10:37:53 AM UTC 24 |
| Finished | Oct 12 11:18:53 AM UTC 24 |
| Peak memory | 174996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2738680349 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.2738680349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/14.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.1878281815 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 336673610000 ps |
| CPU time | 271.91 seconds |
| Started | Oct 12 10:38:41 AM UTC 24 |
| Finished | Oct 12 11:19:30 AM UTC 24 |
| Peak memory | 176536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1878281815 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.1878281815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/15.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.742309456 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 336385650000 ps |
| CPU time | 273.6 seconds |
| Started | Oct 12 10:39:02 AM UTC 24 |
| Finished | Oct 12 11:20:04 AM UTC 24 |
| Peak memory | 176536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=742309456 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.742309456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/16.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.2914267573 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 337169330000 ps |
| CPU time | 274.39 seconds |
| Started | Oct 12 10:39:18 AM UTC 24 |
| Finished | Oct 12 11:20:05 AM UTC 24 |
| Peak memory | 176536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2914267573 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.2914267573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/17.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.3136638140 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 336974510000 ps |
| CPU time | 274.79 seconds |
| Started | Oct 12 10:39:44 AM UTC 24 |
| Finished | Oct 12 11:20:25 AM UTC 24 |
| Peak memory | 174996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3136638140 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.3136638140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/18.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.374732883 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 337035170000 ps |
| CPU time | 272.41 seconds |
| Started | Oct 12 10:39:54 AM UTC 24 |
| Finished | Oct 12 11:20:35 AM UTC 24 |
| Peak memory | 176532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=374732883 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.374732883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/19.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.1119170057 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 336389210000 ps |
| CPU time | 279.95 seconds |
| Started | Oct 12 10:33:19 AM UTC 24 |
| Finished | Oct 12 11:15:29 AM UTC 24 |
| Peak memory | 174984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1119170057 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.1119170057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/2.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.3091213768 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 337054750000 ps |
| CPU time | 272.73 seconds |
| Started | Oct 12 10:41:42 AM UTC 24 |
| Finished | Oct 12 11:22:24 AM UTC 24 |
| Peak memory | 174996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3091213768 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.3091213768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/20.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.64288791 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 336732830000 ps |
| CPU time | 271.46 seconds |
| Started | Oct 12 10:42:21 AM UTC 24 |
| Finished | Oct 12 11:22:56 AM UTC 24 |
| Peak memory | 174984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=64288791 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_ gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.64288791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/21.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.1662416907 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 336592470000 ps |
| CPU time | 270.78 seconds |
| Started | Oct 12 10:43:01 AM UTC 24 |
| Finished | Oct 12 11:23:27 AM UTC 24 |
| Peak memory | 176536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1662416907 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.1662416907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/22.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.2563898143 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 337073910000 ps |
| CPU time | 268.2 seconds |
| Started | Oct 12 10:43:36 AM UTC 24 |
| Finished | Oct 12 11:23:41 AM UTC 24 |
| Peak memory | 174996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2563898143 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.2563898143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/23.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.1397960809 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 336588310000 ps |
| CPU time | 267.67 seconds |
| Started | Oct 12 10:44:47 AM UTC 24 |
| Finished | Oct 12 11:24:21 AM UTC 24 |
| Peak memory | 176536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1397960809 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.1397960809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/24.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.2978849901 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 336578870000 ps |
| CPU time | 267.06 seconds |
| Started | Oct 12 10:45:02 AM UTC 24 |
| Finished | Oct 12 11:24:40 AM UTC 24 |
| Peak memory | 176536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2978849901 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.2978849901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/25.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.15476890 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 336549910000 ps |
| CPU time | 268.69 seconds |
| Started | Oct 12 10:46:04 AM UTC 24 |
| Finished | Oct 12 11:25:18 AM UTC 24 |
| Peak memory | 176524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15476890 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_ gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.15476890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/26.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.3225521529 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 336445930000 ps |
| CPU time | 268.29 seconds |
| Started | Oct 12 10:46:23 AM UTC 24 |
| Finished | Oct 12 11:25:18 AM UTC 24 |
| Peak memory | 176536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3225521529 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.3225521529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/27.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.2012468942 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 336682210000 ps |
| CPU time | 267.35 seconds |
| Started | Oct 12 10:46:23 AM UTC 24 |
| Finished | Oct 12 11:25:32 AM UTC 24 |
| Peak memory | 176536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2012468942 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.2012468942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/28.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.2092676237 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 336847390000 ps |
| CPU time | 265.89 seconds |
| Started | Oct 12 10:47:19 AM UTC 24 |
| Finished | Oct 12 11:26:07 AM UTC 24 |
| Peak memory | 174996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2092676237 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.2092676237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/29.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.1554602661 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 336542690000 ps |
| CPU time | 283.78 seconds |
| Started | Oct 12 10:33:35 AM UTC 24 |
| Finished | Oct 12 11:15:39 AM UTC 24 |
| Peak memory | 174984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1554602661 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.1554602661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/3.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.3785502542 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 336410830000 ps |
| CPU time | 262.2 seconds |
| Started | Oct 12 10:48:50 AM UTC 24 |
| Finished | Oct 12 11:27:08 AM UTC 24 |
| Peak memory | 176536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3785502542 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.3785502542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/30.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.1158201742 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 336727030000 ps |
| CPU time | 263.28 seconds |
| Started | Oct 12 10:49:05 AM UTC 24 |
| Finished | Oct 12 11:27:25 AM UTC 24 |
| Peak memory | 174996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1158201742 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.1158201742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/31.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.1922273442 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 336951990000 ps |
| CPU time | 261.88 seconds |
| Started | Oct 12 10:50:49 AM UTC 24 |
| Finished | Oct 12 11:29:06 AM UTC 24 |
| Peak memory | 174996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1922273442 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.1922273442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/32.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.117302843 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 336474950000 ps |
| CPU time | 265.7 seconds |
| Started | Oct 12 10:50:56 AM UTC 24 |
| Finished | Oct 12 11:29:34 AM UTC 24 |
| Peak memory | 174996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=117302843 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.117302843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/33.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.1801876596 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 336648890000 ps |
| CPU time | 264.92 seconds |
| Started | Oct 12 10:50:58 AM UTC 24 |
| Finished | Oct 12 11:29:39 AM UTC 24 |
| Peak memory | 176532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1801876596 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.1801876596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/34.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.1455795292 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 337055950000 ps |
| CPU time | 263.47 seconds |
| Started | Oct 12 10:51:48 AM UTC 24 |
| Finished | Oct 12 11:30:13 AM UTC 24 |
| Peak memory | 174996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1455795292 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.1455795292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/35.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.2661949588 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 337071170000 ps |
| CPU time | 259.98 seconds |
| Started | Oct 12 10:54:28 AM UTC 24 |
| Finished | Oct 12 11:32:26 AM UTC 24 |
| Peak memory | 174996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2661949588 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.2661949588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/36.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.1679627548 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 336516870000 ps |
| CPU time | 260.85 seconds |
| Started | Oct 12 10:55:24 AM UTC 24 |
| Finished | Oct 12 11:33:24 AM UTC 24 |
| Peak memory | 174996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1679627548 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.1679627548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/37.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3931803686 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 336666690000 ps |
| CPU time | 260.32 seconds |
| Started | Oct 12 10:55:40 AM UTC 24 |
| Finished | Oct 12 11:33:28 AM UTC 24 |
| Peak memory | 176536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3931803686 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.3931803686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/38.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.383283825 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 336885270000 ps |
| CPU time | 262.82 seconds |
| Started | Oct 12 10:55:51 AM UTC 24 |
| Finished | Oct 12 11:33:54 AM UTC 24 |
| Peak memory | 174996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=383283825 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.383283825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/39.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.2968214518 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 336313330000 ps |
| CPU time | 279.77 seconds |
| Started | Oct 12 10:34:44 AM UTC 24 |
| Finished | Oct 12 11:16:39 AM UTC 24 |
| Peak memory | 176524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2968214518 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.2968214518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/4.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.1381300549 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 336777210000 ps |
| CPU time | 258.81 seconds |
| Started | Oct 12 10:57:25 AM UTC 24 |
| Finished | Oct 12 11:34:57 AM UTC 24 |
| Peak memory | 176536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1381300549 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.1381300549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/40.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.3273870680 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 336639110000 ps |
| CPU time | 256.51 seconds |
| Started | Oct 12 10:58:13 AM UTC 24 |
| Finished | Oct 12 11:35:39 AM UTC 24 |
| Peak memory | 174996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3273870680 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.3273870680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/41.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.2010911345 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 336777930000 ps |
| CPU time | 259.56 seconds |
| Started | Oct 12 10:58:42 AM UTC 24 |
| Finished | Oct 12 11:36:11 AM UTC 24 |
| Peak memory | 174996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2010911345 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.2010911345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/42.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.1209344464 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 337060630000 ps |
| CPU time | 260.87 seconds |
| Started | Oct 12 10:59:09 AM UTC 24 |
| Finished | Oct 12 11:36:57 AM UTC 24 |
| Peak memory | 174996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1209344464 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.1209344464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/43.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.1762377940 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 336353150000 ps |
| CPU time | 259.8 seconds |
| Started | Oct 12 11:00:15 AM UTC 24 |
| Finished | Oct 12 11:37:45 AM UTC 24 |
| Peak memory | 176536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1762377940 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.1762377940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/44.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.872775597 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 336815570000 ps |
| CPU time | 259.62 seconds |
| Started | Oct 12 11:00:35 AM UTC 24 |
| Finished | Oct 12 11:38:11 AM UTC 24 |
| Peak memory | 176536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=872775597 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.872775597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/45.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.3556964099 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 336970170000 ps |
| CPU time | 258.87 seconds |
| Started | Oct 12 11:01:26 AM UTC 24 |
| Finished | Oct 12 11:38:47 AM UTC 24 |
| Peak memory | 176536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3556964099 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.3556964099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/46.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.3299996981 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 336737850000 ps |
| CPU time | 258.62 seconds |
| Started | Oct 12 11:03:15 AM UTC 24 |
| Finished | Oct 12 11:40:23 AM UTC 24 |
| Peak memory | 176536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3299996981 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.3299996981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/47.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1976841655 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 336633570000 ps |
| CPU time | 259.03 seconds |
| Started | Oct 12 11:03:17 AM UTC 24 |
| Finished | Oct 12 11:40:36 AM UTC 24 |
| Peak memory | 176536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1976841655 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.1976841655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/48.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.1760972726 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 336720250000 ps |
| CPU time | 258.07 seconds |
| Started | Oct 12 11:03:27 AM UTC 24 |
| Finished | Oct 12 11:40:42 AM UTC 24 |
| Peak memory | 176536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1760972726 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.1760972726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/49.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.145143980 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 336519530000 ps |
| CPU time | 277.53 seconds |
| Started | Oct 12 10:34:46 AM UTC 24 |
| Finished | Oct 12 11:16:28 AM UTC 24 |
| Peak memory | 176560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=145143980 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.145143980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/5.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.3659076036 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 336379190000 ps |
| CPU time | 280.35 seconds |
| Started | Oct 12 10:34:52 AM UTC 24 |
| Finished | Oct 12 11:16:47 AM UTC 24 |
| Peak memory | 174984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3659076036 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.3659076036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/6.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.40025761 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 336850470000 ps |
| CPU time | 280.37 seconds |
| Started | Oct 12 10:35:10 AM UTC 24 |
| Finished | Oct 12 11:17:06 AM UTC 24 |
| Peak memory | 176528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40025761 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_ gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.40025761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/7.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.1136743020 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 336490770000 ps |
| CPU time | 280.38 seconds |
| Started | Oct 12 10:35:41 AM UTC 24 |
| Finished | Oct 12 11:17:29 AM UTC 24 |
| Peak memory | 176524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1136743020 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2 4_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.1136743020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/8.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.258151057 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 336844810000 ps |
| CPU time | 279.95 seconds |
| Started | Oct 12 10:35:45 AM UTC 24 |
| Finished | Oct 12 11:17:33 AM UTC 24 |
| Peak memory | 176560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=258151057 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24 _gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.258151057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/9.prim_lfsr_gal_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.3235933352 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 1567830000 ps |
| CPU time | 2.27 seconds |
| Started | Oct 12 11:22:57 AM UTC 24 |
| Finished | Oct 12 11:23:10 AM UTC 24 |
| Peak memory | 177764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3235933352 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.3235933352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/1.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.1905347082 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 1478850000 ps |
| CPU time | 2.07 seconds |
| Started | Oct 12 11:23:01 AM UTC 24 |
| Finished | Oct 12 11:23:13 AM UTC 24 |
| Peak memory | 177796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1905347082 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.1905347082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/10.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.5313627 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 1482250000 ps |
| CPU time | 2.23 seconds |
| Started | Oct 12 11:23:02 AM UTC 24 |
| Finished | Oct 12 11:23:14 AM UTC 24 |
| Peak memory | 177796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5313627 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib .vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.5313627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/11.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.2211838644 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 1468110000 ps |
| CPU time | 2.2 seconds |
| Started | Oct 12 11:23:08 AM UTC 24 |
| Finished | Oct 12 11:23:20 AM UTC 24 |
| Peak memory | 177796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2211838644 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.2211838644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/12.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.1686764851 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 1452210000 ps |
| CPU time | 2.04 seconds |
| Started | Oct 12 11:23:09 AM UTC 24 |
| Finished | Oct 12 11:23:21 AM UTC 24 |
| Peak memory | 177796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1686764851 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.1686764851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/13.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.3133768004 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 1536590000 ps |
| CPU time | 2.04 seconds |
| Started | Oct 12 11:23:09 AM UTC 24 |
| Finished | Oct 12 11:23:21 AM UTC 24 |
| Peak memory | 177796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3133768004 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.3133768004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/14.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.3793966146 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 1421150000 ps |
| CPU time | 2.12 seconds |
| Started | Oct 12 11:23:10 AM UTC 24 |
| Finished | Oct 12 11:23:22 AM UTC 24 |
| Peak memory | 177796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3793966146 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.3793966146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/15.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.1995794307 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 1572570000 ps |
| CPU time | 2.21 seconds |
| Started | Oct 12 11:23:11 AM UTC 24 |
| Finished | Oct 12 11:23:24 AM UTC 24 |
| Peak memory | 177796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1995794307 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.1995794307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/16.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.2607823771 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 1447790000 ps |
| CPU time | 1.97 seconds |
| Started | Oct 12 11:23:11 AM UTC 24 |
| Finished | Oct 12 11:23:23 AM UTC 24 |
| Peak memory | 177796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2607823771 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.2607823771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/17.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.244864711 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 1476910000 ps |
| CPU time | 2.15 seconds |
| Started | Oct 12 11:23:11 AM UTC 24 |
| Finished | Oct 12 11:23:23 AM UTC 24 |
| Peak memory | 177760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=244864711 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f ib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.244864711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/18.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.1849427437 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 1273430000 ps |
| CPU time | 1.9 seconds |
| Started | Oct 12 11:23:11 AM UTC 24 |
| Finished | Oct 12 11:23:22 AM UTC 24 |
| Peak memory | 177796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1849427437 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.1849427437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/19.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.3322878288 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 1591330000 ps |
| CPU time | 2.18 seconds |
| Started | Oct 12 11:22:57 AM UTC 24 |
| Finished | Oct 12 11:23:10 AM UTC 24 |
| Peak memory | 177764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3322878288 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.3322878288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/2.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.1360818868 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 1473230000 ps |
| CPU time | 2.12 seconds |
| Started | Oct 12 11:23:12 AM UTC 24 |
| Finished | Oct 12 11:23:24 AM UTC 24 |
| Peak memory | 177408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1360818868 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.1360818868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/20.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.4053054619 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 1391070000 ps |
| CPU time | 2.06 seconds |
| Started | Oct 12 11:23:12 AM UTC 24 |
| Finished | Oct 12 11:23:24 AM UTC 24 |
| Peak memory | 177796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4053054619 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.4053054619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/21.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.423557460 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 1444050000 ps |
| CPU time | 2.02 seconds |
| Started | Oct 12 11:23:14 AM UTC 24 |
| Finished | Oct 12 11:23:26 AM UTC 24 |
| Peak memory | 177760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=423557460 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f ib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.423557460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/22.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.1115585264 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 1474630000 ps |
| CPU time | 2.2 seconds |
| Started | Oct 12 11:23:15 AM UTC 24 |
| Finished | Oct 12 11:23:28 AM UTC 24 |
| Peak memory | 177796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1115585264 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.1115585264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/23.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.2575330010 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 1137650000 ps |
| CPU time | 1.82 seconds |
| Started | Oct 12 11:23:20 AM UTC 24 |
| Finished | Oct 12 11:23:30 AM UTC 24 |
| Peak memory | 177796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2575330010 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.2575330010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/24.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.2918476647 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 1360690000 ps |
| CPU time | 1.97 seconds |
| Started | Oct 12 11:23:21 AM UTC 24 |
| Finished | Oct 12 11:23:33 AM UTC 24 |
| Peak memory | 177796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2918476647 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.2918476647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/25.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.1963285875 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 1458350000 ps |
| CPU time | 2.14 seconds |
| Started | Oct 12 11:23:23 AM UTC 24 |
| Finished | Oct 12 11:23:35 AM UTC 24 |
| Peak memory | 177796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1963285875 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.1963285875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/26.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.2876088663 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 1532810000 ps |
| CPU time | 2.25 seconds |
| Started | Oct 12 11:23:23 AM UTC 24 |
| Finished | Oct 12 11:23:35 AM UTC 24 |
| Peak memory | 177788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2876088663 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.2876088663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/27.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.3818178474 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 1590150000 ps |
| CPU time | 2.21 seconds |
| Started | Oct 12 11:23:23 AM UTC 24 |
| Finished | Oct 12 11:23:36 AM UTC 24 |
| Peak memory | 177796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3818178474 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.3818178474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/28.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.871063692 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 1440790000 ps |
| CPU time | 2.06 seconds |
| Started | Oct 12 11:23:24 AM UTC 24 |
| Finished | Oct 12 11:23:36 AM UTC 24 |
| Peak memory | 177760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=871063692 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f ib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.871063692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/29.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.2012105211 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 1562770000 ps |
| CPU time | 2.17 seconds |
| Started | Oct 12 11:22:57 AM UTC 24 |
| Finished | Oct 12 11:23:10 AM UTC 24 |
| Peak memory | 177764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2012105211 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.2012105211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/3.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.1471033498 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 1244050000 ps |
| CPU time | 1.89 seconds |
| Started | Oct 12 11:23:24 AM UTC 24 |
| Finished | Oct 12 11:23:34 AM UTC 24 |
| Peak memory | 177796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1471033498 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.1471033498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/30.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.3815762823 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 1641370000 ps |
| CPU time | 2.31 seconds |
| Started | Oct 12 11:23:24 AM UTC 24 |
| Finished | Oct 12 11:23:37 AM UTC 24 |
| Peak memory | 177796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3815762823 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.3815762823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/31.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.1955255817 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 1478130000 ps |
| CPU time | 2.02 seconds |
| Started | Oct 12 11:23:25 AM UTC 24 |
| Finished | Oct 12 11:23:37 AM UTC 24 |
| Peak memory | 177796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1955255817 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.1955255817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/32.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.4064650210 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 1385610000 ps |
| CPU time | 1.97 seconds |
| Started | Oct 12 11:23:25 AM UTC 24 |
| Finished | Oct 12 11:23:36 AM UTC 24 |
| Peak memory | 177796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4064650210 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.4064650210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/33.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.2506264325 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 1459050000 ps |
| CPU time | 2.08 seconds |
| Started | Oct 12 11:23:25 AM UTC 24 |
| Finished | Oct 12 11:23:37 AM UTC 24 |
| Peak memory | 177796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2506264325 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.2506264325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/34.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.3808460050 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 1602830000 ps |
| CPU time | 2.08 seconds |
| Started | Oct 12 11:23:27 AM UTC 24 |
| Finished | Oct 12 11:23:40 AM UTC 24 |
| Peak memory | 177796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3808460050 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.3808460050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/35.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.3504911824 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 1513570000 ps |
| CPU time | 1.99 seconds |
| Started | Oct 12 11:23:28 AM UTC 24 |
| Finished | Oct 12 11:23:40 AM UTC 24 |
| Peak memory | 177796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3504911824 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.3504911824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/36.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1082767506 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 1407610000 ps |
| CPU time | 2.03 seconds |
| Started | Oct 12 11:23:28 AM UTC 24 |
| Finished | Oct 12 11:23:40 AM UTC 24 |
| Peak memory | 177796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1082767506 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.1082767506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/37.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.787275767 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 1110370000 ps |
| CPU time | 1.82 seconds |
| Started | Oct 12 11:23:31 AM UTC 24 |
| Finished | Oct 12 11:23:41 AM UTC 24 |
| Peak memory | 177764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=787275767 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f ib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.787275767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/38.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.53557338 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 1362610000 ps |
| CPU time | 2.13 seconds |
| Started | Oct 12 11:23:33 AM UTC 24 |
| Finished | Oct 12 11:23:44 AM UTC 24 |
| Peak memory | 177764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=53557338 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fi b.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.53557338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/39.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.4237572872 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 1253810000 ps |
| CPU time | 1.94 seconds |
| Started | Oct 12 11:22:57 AM UTC 24 |
| Finished | Oct 12 11:23:08 AM UTC 24 |
| Peak memory | 177764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4237572872 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.4237572872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/4.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.2222682778 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 985750000 ps |
| CPU time | 1.68 seconds |
| Started | Oct 12 11:23:35 AM UTC 24 |
| Finished | Oct 12 11:23:44 AM UTC 24 |
| Peak memory | 177796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2222682778 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.2222682778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/40.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.1425734109 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 1565090000 ps |
| CPU time | 2.09 seconds |
| Started | Oct 12 11:23:35 AM UTC 24 |
| Finished | Oct 12 11:23:48 AM UTC 24 |
| Peak memory | 177796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1425734109 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.1425734109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/41.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.1350053417 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 1220770000 ps |
| CPU time | 1.87 seconds |
| Started | Oct 12 11:23:36 AM UTC 24 |
| Finished | Oct 12 11:23:45 AM UTC 24 |
| Peak memory | 177796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1350053417 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.1350053417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/42.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.618584227 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 1349870000 ps |
| CPU time | 2.01 seconds |
| Started | Oct 12 11:23:37 AM UTC 24 |
| Finished | Oct 12 11:23:47 AM UTC 24 |
| Peak memory | 177764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=618584227 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f ib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.618584227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/43.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.2077052667 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 1433090000 ps |
| CPU time | 2.13 seconds |
| Started | Oct 12 11:23:37 AM UTC 24 |
| Finished | Oct 12 11:23:48 AM UTC 24 |
| Peak memory | 177796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2077052667 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.2077052667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/44.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.3446391397 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 1586050000 ps |
| CPU time | 2.11 seconds |
| Started | Oct 12 11:23:38 AM UTC 24 |
| Finished | Oct 12 11:23:50 AM UTC 24 |
| Peak memory | 177796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3446391397 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.3446391397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/45.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.2451982918 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 1520950000 ps |
| CPU time | 2.05 seconds |
| Started | Oct 12 11:23:38 AM UTC 24 |
| Finished | Oct 12 11:23:49 AM UTC 24 |
| Peak memory | 177796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2451982918 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.2451982918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/46.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.3962597827 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 1340770000 ps |
| CPU time | 1.96 seconds |
| Started | Oct 12 11:23:38 AM UTC 24 |
| Finished | Oct 12 11:23:48 AM UTC 24 |
| Peak memory | 177796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3962597827 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.3962597827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/47.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.529309775 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 1524030000 ps |
| CPU time | 2.1 seconds |
| Started | Oct 12 11:23:38 AM UTC 24 |
| Finished | Oct 12 11:23:49 AM UTC 24 |
| Peak memory | 177760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=529309775 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f ib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.529309775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/48.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.2500759439 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 1518910000 ps |
| CPU time | 2.14 seconds |
| Started | Oct 12 11:23:41 AM UTC 24 |
| Finished | Oct 12 11:23:52 AM UTC 24 |
| Peak memory | 177796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2500759439 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.2500759439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/49.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.3821454848 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 1409710000 ps |
| CPU time | 2.15 seconds |
| Started | Oct 12 11:22:57 AM UTC 24 |
| Finished | Oct 12 11:23:09 AM UTC 24 |
| Peak memory | 177764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3821454848 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.3821454848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/5.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.1029469334 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 1558850000 ps |
| CPU time | 2.35 seconds |
| Started | Oct 12 11:22:58 AM UTC 24 |
| Finished | Oct 12 11:23:11 AM UTC 24 |
| Peak memory | 177764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1029469334 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.1029469334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/6.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.1373090584 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 1467130000 ps |
| CPU time | 2.1 seconds |
| Started | Oct 12 11:22:58 AM UTC 24 |
| Finished | Oct 12 11:23:11 AM UTC 24 |
| Peak memory | 177764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1373090584 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.1373090584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/7.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.2607988451 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 1167610000 ps |
| CPU time | 1.83 seconds |
| Started | Oct 12 11:22:58 AM UTC 24 |
| Finished | Oct 12 11:23:08 AM UTC 24 |
| Peak memory | 177764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2607988451 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.2607988451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/8.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2500090111 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 1448150000 ps |
| CPU time | 2.15 seconds |
| Started | Oct 12 11:22:59 AM UTC 24 |
| Finished | Oct 12 11:23:12 AM UTC 24 |
| Peak memory | 177764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2500090111 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.2500090111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/9.prim_lfsr_fib_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.3229014294 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 1483210000 ps |
| CPU time | 2.02 seconds |
| Started | Oct 12 11:25:31 AM UTC 24 |
| Finished | Oct 12 11:25:41 AM UTC 24 |
| Peak memory | 177728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3229014294 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.3229014294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/1.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.156321888 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 1413230000 ps |
| CPU time | 1.81 seconds |
| Started | Oct 12 11:25:41 AM UTC 24 |
| Finished | Oct 12 11:25:51 AM UTC 24 |
| Peak memory | 177724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=156321888 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g al.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.156321888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/10.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.1675245228 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 1505870000 ps |
| CPU time | 2.09 seconds |
| Started | Oct 12 11:25:43 AM UTC 24 |
| Finished | Oct 12 11:25:54 AM UTC 24 |
| Peak memory | 177760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1675245228 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.1675245228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/11.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.3332097119 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 1570970000 ps |
| CPU time | 2.1 seconds |
| Started | Oct 12 11:25:44 AM UTC 24 |
| Finished | Oct 12 11:25:54 AM UTC 24 |
| Peak memory | 177760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3332097119 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.3332097119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/12.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.1679808887 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 1540830000 ps |
| CPU time | 2.14 seconds |
| Started | Oct 12 11:25:46 AM UTC 24 |
| Finished | Oct 12 11:25:56 AM UTC 24 |
| Peak memory | 177760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1679808887 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.1679808887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/13.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.1563067253 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 1533890000 ps |
| CPU time | 2.1 seconds |
| Started | Oct 12 11:25:49 AM UTC 24 |
| Finished | Oct 12 11:25:59 AM UTC 24 |
| Peak memory | 177760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1563067253 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.1563067253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/14.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.687397369 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 1315570000 ps |
| CPU time | 1.86 seconds |
| Started | Oct 12 11:25:49 AM UTC 24 |
| Finished | Oct 12 11:25:58 AM UTC 24 |
| Peak memory | 177724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=687397369 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g al.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.687397369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/15.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.3080385961 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 1441450000 ps |
| CPU time | 2.03 seconds |
| Started | Oct 12 11:25:49 AM UTC 24 |
| Finished | Oct 12 11:25:59 AM UTC 24 |
| Peak memory | 177760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3080385961 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.3080385961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/16.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.3570857180 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 1407750000 ps |
| CPU time | 1.93 seconds |
| Started | Oct 12 11:25:50 AM UTC 24 |
| Finished | Oct 12 11:25:59 AM UTC 24 |
| Peak memory | 177760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3570857180 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.3570857180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/17.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.490409252 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 1542050000 ps |
| CPU time | 2.07 seconds |
| Started | Oct 12 11:25:50 AM UTC 24 |
| Finished | Oct 12 11:26:00 AM UTC 24 |
| Peak memory | 177724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=490409252 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g al.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.490409252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/18.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.3101691244 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 1428290000 ps |
| CPU time | 1.87 seconds |
| Started | Oct 12 11:25:52 AM UTC 24 |
| Finished | Oct 12 11:26:01 AM UTC 24 |
| Peak memory | 177760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3101691244 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.3101691244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/19.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.3262043188 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 1357750000 ps |
| CPU time | 1.93 seconds |
| Started | Oct 12 11:25:31 AM UTC 24 |
| Finished | Oct 12 11:25:40 AM UTC 24 |
| Peak memory | 177728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3262043188 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.3262043188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/2.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.1537756549 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 1438550000 ps |
| CPU time | 2.07 seconds |
| Started | Oct 12 11:25:52 AM UTC 24 |
| Finished | Oct 12 11:26:02 AM UTC 24 |
| Peak memory | 177760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1537756549 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.1537756549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/20.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.1344836783 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 1525330000 ps |
| CPU time | 1.95 seconds |
| Started | Oct 12 11:25:53 AM UTC 24 |
| Finished | Oct 12 11:26:03 AM UTC 24 |
| Peak memory | 177760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1344836783 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.1344836783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/21.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.1662900235 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 1544470000 ps |
| CPU time | 1.95 seconds |
| Started | Oct 12 11:25:54 AM UTC 24 |
| Finished | Oct 12 11:26:05 AM UTC 24 |
| Peak memory | 177760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1662900235 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.1662900235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/22.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.1092318847 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 1299750000 ps |
| CPU time | 1.81 seconds |
| Started | Oct 12 11:25:55 AM UTC 24 |
| Finished | Oct 12 11:26:04 AM UTC 24 |
| Peak memory | 177760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1092318847 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.1092318847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/23.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.797812898 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 1507690000 ps |
| CPU time | 2.04 seconds |
| Started | Oct 12 11:25:56 AM UTC 24 |
| Finished | Oct 12 11:26:06 AM UTC 24 |
| Peak memory | 177716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=797812898 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g al.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.797812898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/24.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.1964393405 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 1256710000 ps |
| CPU time | 1.87 seconds |
| Started | Oct 12 11:25:58 AM UTC 24 |
| Finished | Oct 12 11:26:08 AM UTC 24 |
| Peak memory | 177760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1964393405 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.1964393405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/25.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.2106372413 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 1567950000 ps |
| CPU time | 2.11 seconds |
| Started | Oct 12 11:25:58 AM UTC 24 |
| Finished | Oct 12 11:26:09 AM UTC 24 |
| Peak memory | 177760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2106372413 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.2106372413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/26.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.905621374 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 1516310000 ps |
| CPU time | 1.95 seconds |
| Started | Oct 12 11:26:00 AM UTC 24 |
| Finished | Oct 12 11:26:10 AM UTC 24 |
| Peak memory | 177724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=905621374 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g al.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.905621374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/27.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.3460429713 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 1479150000 ps |
| CPU time | 2 seconds |
| Started | Oct 12 11:26:00 AM UTC 24 |
| Finished | Oct 12 11:26:10 AM UTC 24 |
| Peak memory | 177760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3460429713 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.3460429713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/28.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.3051451327 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 1273050000 ps |
| CPU time | 1.87 seconds |
| Started | Oct 12 11:26:00 AM UTC 24 |
| Finished | Oct 12 11:26:09 AM UTC 24 |
| Peak memory | 177760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3051451327 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.3051451327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/29.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.2194844167 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 1151890000 ps |
| CPU time | 1.8 seconds |
| Started | Oct 12 11:25:32 AM UTC 24 |
| Finished | Oct 12 11:25:40 AM UTC 24 |
| Peak memory | 177728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2194844167 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.2194844167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/3.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.3619383264 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 1442830000 ps |
| CPU time | 2.06 seconds |
| Started | Oct 12 11:26:01 AM UTC 24 |
| Finished | Oct 12 11:26:11 AM UTC 24 |
| Peak memory | 177760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3619383264 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.3619383264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/30.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.1638019031 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 1440530000 ps |
| CPU time | 1.96 seconds |
| Started | Oct 12 11:26:02 AM UTC 24 |
| Finished | Oct 12 11:26:12 AM UTC 24 |
| Peak memory | 177760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1638019031 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.1638019031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/31.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.3193797820 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 1437990000 ps |
| CPU time | 1.97 seconds |
| Started | Oct 12 11:26:03 AM UTC 24 |
| Finished | Oct 12 11:26:13 AM UTC 24 |
| Peak memory | 177760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3193797820 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.3193797820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/32.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.1126876448 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 1429250000 ps |
| CPU time | 1.91 seconds |
| Started | Oct 12 11:26:04 AM UTC 24 |
| Finished | Oct 12 11:26:14 AM UTC 24 |
| Peak memory | 177760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1126876448 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.1126876448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/33.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.1973160944 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 1363690000 ps |
| CPU time | 1.89 seconds |
| Started | Oct 12 11:26:05 AM UTC 24 |
| Finished | Oct 12 11:26:14 AM UTC 24 |
| Peak memory | 177760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1973160944 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.1973160944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/34.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.2104223730 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 1230950000 ps |
| CPU time | 1.76 seconds |
| Started | Oct 12 11:26:05 AM UTC 24 |
| Finished | Oct 12 11:26:14 AM UTC 24 |
| Peak memory | 177760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2104223730 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.2104223730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/35.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.944871101 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 1433190000 ps |
| CPU time | 1.83 seconds |
| Started | Oct 12 11:26:07 AM UTC 24 |
| Finished | Oct 12 11:26:17 AM UTC 24 |
| Peak memory | 177724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=944871101 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g al.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.944871101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/36.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.2055655755 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 1494150000 ps |
| CPU time | 1.96 seconds |
| Started | Oct 12 11:26:07 AM UTC 24 |
| Finished | Oct 12 11:26:17 AM UTC 24 |
| Peak memory | 177760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2055655755 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.2055655755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/37.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.90253073 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 1311690000 ps |
| CPU time | 1.89 seconds |
| Started | Oct 12 11:26:07 AM UTC 24 |
| Finished | Oct 12 11:26:16 AM UTC 24 |
| Peak memory | 177728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=90253073 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ga l.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.90253073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/38.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.1516592570 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 1376070000 ps |
| CPU time | 1.82 seconds |
| Started | Oct 12 11:26:07 AM UTC 24 |
| Finished | Oct 12 11:26:17 AM UTC 24 |
| Peak memory | 177760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1516592570 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.1516592570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/39.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.4073544001 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 1551250000 ps |
| CPU time | 1.95 seconds |
| Started | Oct 12 11:25:33 AM UTC 24 |
| Finished | Oct 12 11:25:43 AM UTC 24 |
| Peak memory | 177728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4073544001 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.4073544001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/4.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.692654112 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 1614490000 ps |
| CPU time | 2.14 seconds |
| Started | Oct 12 11:26:08 AM UTC 24 |
| Finished | Oct 12 11:26:19 AM UTC 24 |
| Peak memory | 177724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=692654112 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g al.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.692654112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/40.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.3128381048 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 1476210000 ps |
| CPU time | 2.09 seconds |
| Started | Oct 12 11:26:08 AM UTC 24 |
| Finished | Oct 12 11:26:18 AM UTC 24 |
| Peak memory | 177760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3128381048 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.3128381048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/41.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.180996113 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 1460830000 ps |
| CPU time | 1.97 seconds |
| Started | Oct 12 11:26:09 AM UTC 24 |
| Finished | Oct 12 11:26:19 AM UTC 24 |
| Peak memory | 177724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=180996113 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g al.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.180996113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/42.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.2410999769 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 1473690000 ps |
| CPU time | 1.98 seconds |
| Started | Oct 12 11:26:10 AM UTC 24 |
| Finished | Oct 12 11:26:21 AM UTC 24 |
| Peak memory | 177760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2410999769 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.2410999769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/43.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.3867052227 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 1479150000 ps |
| CPU time | 2.01 seconds |
| Started | Oct 12 11:26:13 AM UTC 24 |
| Finished | Oct 12 11:26:24 AM UTC 24 |
| Peak memory | 177760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3867052227 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.3867052227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/44.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.4196741152 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 1085610000 ps |
| CPU time | 1.69 seconds |
| Started | Oct 12 11:26:13 AM UTC 24 |
| Finished | Oct 12 11:26:22 AM UTC 24 |
| Peak memory | 177760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4196741152 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.4196741152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/45.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.2459971087 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 1470530000 ps |
| CPU time | 1.98 seconds |
| Started | Oct 12 11:26:13 AM UTC 24 |
| Finished | Oct 12 11:26:24 AM UTC 24 |
| Peak memory | 177760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2459971087 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.2459971087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/46.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.801598765 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 1474730000 ps |
| CPU time | 1.97 seconds |
| Started | Oct 12 11:26:13 AM UTC 24 |
| Finished | Oct 12 11:26:24 AM UTC 24 |
| Peak memory | 177724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=801598765 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g al.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.801598765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/47.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.350591641 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 1381150000 ps |
| CPU time | 1.88 seconds |
| Started | Oct 12 11:26:14 AM UTC 24 |
| Finished | Oct 12 11:26:24 AM UTC 24 |
| Peak memory | 177724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=350591641 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g al.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.350591641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/48.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.1082957984 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 1161950000 ps |
| CPU time | 1.71 seconds |
| Started | Oct 12 11:26:14 AM UTC 24 |
| Finished | Oct 12 11:26:23 AM UTC 24 |
| Peak memory | 177760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1082957984 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.1082957984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/49.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.3442451201 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 1503250000 ps |
| CPU time | 2.06 seconds |
| Started | Oct 12 11:25:35 AM UTC 24 |
| Finished | Oct 12 11:25:45 AM UTC 24 |
| Peak memory | 177728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3442451201 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.3442451201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/5.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.1874095174 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 1419130000 ps |
| CPU time | 2.01 seconds |
| Started | Oct 12 11:25:38 AM UTC 24 |
| Finished | Oct 12 11:25:48 AM UTC 24 |
| Peak memory | 177728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1874095174 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.1874095174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/6.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.2384077709 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 1225830000 ps |
| CPU time | 1.83 seconds |
| Started | Oct 12 11:25:39 AM UTC 24 |
| Finished | Oct 12 11:25:48 AM UTC 24 |
| Peak memory | 177728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2384077709 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.2384077709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/7.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.3154975522 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 1525630000 ps |
| CPU time | 2.14 seconds |
| Started | Oct 12 11:25:41 AM UTC 24 |
| Finished | Oct 12 11:25:51 AM UTC 24 |
| Peak memory | 177252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3154975522 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.3154975522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/8.prim_lfsr_gal_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.2022974333 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 1125350000 ps |
| CPU time | 1.71 seconds |
| Started | Oct 12 11:25:41 AM UTC 24 |
| Finished | Oct 12 11:25:49 AM UTC 24 |
| Peak memory | 177728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2022974333 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.2022974333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_lfsr-sim-vcs/9.prim_lfsr_gal_smoke/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |